<feed xmlns='http://www.w3.org/2005/Atom'>
<title>netbsd/common, branch lockdoc-9.3-0.4</title>
<subtitle>NetBSD fork for lockdoc analysis</subtitle>
<link rel='alternate' type='text/html' href='http://git.infra.scholz.ruhr/netbsd/'/>
<entry>
<title>Pull up following revision(s) (requested by skrll in ticket #1453):</title>
<updated>2022-05-17T13:48:45+00:00</updated>
<author>
<name>martin</name>
<email>martin@NetBSD.org</email>
</author>
<published>2022-05-17T13:48:45+00:00</published>
<link rel='alternate' type='text/html' href='http://git.infra.scholz.ruhr/netbsd/commit/?id=f932742206736bc8d83200c899d1c30e645663ca'/>
<id>f932742206736bc8d83200c899d1c30e645663ca</id>
<content type='text'>
	common/lib/libc/atomic/atomic_c11_compare_exchange_cas_32.c: revision 1.5

Fix the copy&amp;paste botch from previous.  Spotted by Tom Lane.</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
	common/lib/libc/atomic/atomic_c11_compare_exchange_cas_32.c: revision 1.5

Fix the copy&amp;paste botch from previous.  Spotted by Tom Lane.</pre>
</div>
</content>
</entry>
<entry>
<title>Pull up following revision(s) (requested by skrll in ticket #1451):</title>
<updated>2022-05-15T12:37:00+00:00</updated>
<author>
<name>martin</name>
<email>martin@NetBSD.org</email>
</author>
<published>2022-05-15T12:37:00+00:00</published>
<link rel='alternate' type='text/html' href='http://git.infra.scholz.ruhr/netbsd/commit/?id=010faf825ac26df299e5fcbcf67674b1e57d0fe1'/>
<id>010faf825ac26df299e5fcbcf67674b1e57d0fe1</id>
<content type='text'>
	common/lib/libc/atomic/atomic_c11_compare_exchange_cas_8.c: revision 1.4
	common/lib/libc/atomic/atomic_c11_compare_exchange_cas_32.c: revision 1.4
	common/lib/libc/atomic/atomic_c11_compare_exchange_cas_16.c: revision 1.4

PR 56832:
fix C implementations of __atomic_compare_exchange*</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
	common/lib/libc/atomic/atomic_c11_compare_exchange_cas_8.c: revision 1.4
	common/lib/libc/atomic/atomic_c11_compare_exchange_cas_32.c: revision 1.4
	common/lib/libc/atomic/atomic_c11_compare_exchange_cas_16.c: revision 1.4

PR 56832:
fix C implementations of __atomic_compare_exchange*</pre>
</div>
</content>
</entry>
<entry>
<title>Pull up following revision(s) (requested by skrll in ticket #1331):</title>
<updated>2021-08-11T17:19:01+00:00</updated>
<author>
<name>martin</name>
<email>martin@NetBSD.org</email>
</author>
<published>2021-08-11T17:19:01+00:00</published>
<link rel='alternate' type='text/html' href='http://git.infra.scholz.ruhr/netbsd/commit/?id=73c0c248e5c2a5e966cd810bdd2e40324230a24c'/>
<id>73c0c248e5c2a5e966cd810bdd2e40324230a24c</id>
<content type='text'>
	common/lib/libc/arch/aarch64/atomic/atomic_add_8.S: revision 1.2
	common/lib/libc/arch/aarch64/atomic/atomic_sub_8.S: revision 1.2
	common/lib/libc/arch/aarch64/atomic/atomic_sub_64.S: revision 1.2
	common/lib/libc/arch/aarch64/atomic/atomic_swap_64.S: revision 1.2
	common/lib/libc/arch/aarch64/atomic/atomic_swap_64.S: revision 1.5
	common/lib/libc/arch/aarch64/atomic/atomic_inc_32.S: revision 1.2
	common/lib/libc/arch/aarch64/atomic/atomic_or_64.S: revision 1.3
	common/lib/libc/arch/aarch64/atomic/atomic_and_16.S: revision 1.2
	common/lib/libc/arch/aarch64/atomic/atomic_xor_64.S: revision 1.2
	common/lib/libc/arch/aarch64/atomic/atomic_and_32.S: revision 1.2
	common/lib/libc/arch/aarch64/atomic/atomic_nand_8.S: revision 1.2
	common/lib/libc/arch/aarch64/atomic/atomic_add_64.S: revision 1.2
	common/lib/libc/arch/aarch64/atomic/atomic_op_asm.h: revision 1.5
	common/lib/libc/arch/aarch64/atomic/atomic_swap_8.S: revision 1.2
	common/lib/libc/arch/aarch64/atomic/atomic_op_asm.h: revision 1.6
	common/lib/libc/arch/aarch64/atomic/atomic_cas_64.S: revision 1.4
	common/lib/libc/arch/aarch64/atomic/atomic_nand_8.S: revision 1.5
	common/lib/libc/arch/aarch64/atomic/atomic_sub_16.S: revision 1.2
	common/lib/libc/arch/aarch64/atomic/atomic_cas_64.S: revision 1.6
	common/lib/libc/arch/aarch64/atomic/atomic_swap_8.S: revision 1.5
	common/lib/libc/arch/aarch64/atomic/atomic_sub_32.S: revision 1.2
	common/lib/libc/arch/aarch64/atomic/atomic_swap_32.S: revision 1.2
	common/lib/libc/arch/aarch64/atomic/atomic_nand_64.S: revision 1.2
	common/lib/libc/arch/aarch64/atomic/atomic_swap_16.S: revision 1.2
	common/lib/libc/arch/aarch64/atomic/atomic_xor_8.S: revision 1.2
	common/lib/libc/arch/aarch64/atomic/atomic_swap_32.S: revision 1.5
	common/lib/libc/arch/aarch64/atomic/atomic_or_32.S: revision 1.2
	common/lib/libc/arch/aarch64/atomic/atomic_nand_64.S: revision 1.5
	common/lib/libc/arch/aarch64/atomic/atomic_swap_16.S: revision 1.5
	common/lib/libc/arch/aarch64/atomic/atomic_or_8.S: revision 1.2
	common/lib/libc/arch/aarch64/atomic/atomic_or_16.S: revision 1.2
	common/lib/libc/arch/aarch64/atomic/atomic_cas_16.S: revision 1.2
	common/lib/libc/arch/aarch64/atomic/atomic_xor_16.S: revision 1.2
	common/lib/libc/arch/aarch64/atomic/atomic_cas_32.S: revision 1.2
	common/lib/libc/arch/aarch64/atomic/atomic_cas_16.S: revision 1.4
	common/lib/libc/arch/aarch64/atomic/atomic_add_32.S: revision 1.2
	common/lib/libc/arch/aarch64/atomic/atomic_cas_8.S: revision 1.2
	common/lib/libc/arch/aarch64/atomic/atomic_xor_32.S: revision 1.2
	common/lib/libc/arch/aarch64/atomic/atomic_dec_64.S: revision 1.2
	common/lib/libc/arch/aarch64/atomic/atomic_cas_32.S: revision 1.4
	common/lib/libc/arch/aarch64/atomic/atomic_add_16.S: revision 1.2
	common/lib/libc/arch/aarch64/atomic/atomic_cas_8.S: revision 1.4
	common/lib/libc/arch/aarch64/atomic/membar_ops.S: revision 1.2
	common/lib/libc/arch/aarch64/atomic/atomic_nand_16.S: revision 1.2
	common/lib/libc/arch/aarch64/atomic/atomic_nand_32.S: revision 1.2
	common/lib/libc/arch/aarch64/atomic/atomic_nand_16.S: revision 1.5
	common/lib/libc/arch/aarch64/atomic/atomic_nand_32.S: revision 1.5
	common/lib/libc/arch/aarch64/atomic/atomic_inc_64.S: revision 1.2
	common/lib/libc/arch/aarch64/atomic/atomic_dec_32.S: revision 1.2
	common/lib/libc/arch/aarch64/atomic/atomic_and_8.S: revision 1.2
	common/lib/libc/arch/aarch64/atomic/atomic_and_64.S: revision 1.2

Part I of ad@'s performance improvements for aarch64
- Remove memory barriers from the atomic ops.  I don't understand why thos=
e
   are there.  Is it some architectural thing, or for a CPU bug, or just
   over-caution maybe?  They're not needed for correctness.
- Have unlikely conditional branches go forwards to help the static branch
   predictor.

Remove memory barriers from the atomic ops macros in the same way as was
done for the other atomic ops earlier.

Use the correct barriers - all of membar_{sync,producer,consumer} have
less scope than before.

LGTM from riastradh

As we're providing the legacy gcc __sync built-in functions for atomic
memory access we might as well get the memory barriers right...

 From the gcc documentation:

In most cases, these built-in functions are considered a full barrier.
That is, no memory operand is moved across the operation, either forward
or backward. Further, instructions are issued as necessary to prevent the
processor from speculating loads across the operation and from queuing
stores after the operation.

type __sync_lock_test_and_set (type *ptr, type value, ...)
    This built-in function is not a full barrier, but rather an acquire
    barrier. This means that references after the operation cannot move to
    (or be speculated to) before the operation, but previous memory stores
    may not be globally visible yet, and previous memory loads may not yet
    be satisfied.

void __sync_lock_release (type *ptr, ...)
    This built-in function is not a full barrier, but rather a release
    barrier. This means that all previous memory stores are globally
    visible, and all previous memory loads have been satisfied, but
    following memory reads are not prevented from being speculated to
    before the barrier.</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
	common/lib/libc/arch/aarch64/atomic/atomic_add_8.S: revision 1.2
	common/lib/libc/arch/aarch64/atomic/atomic_sub_8.S: revision 1.2
	common/lib/libc/arch/aarch64/atomic/atomic_sub_64.S: revision 1.2
	common/lib/libc/arch/aarch64/atomic/atomic_swap_64.S: revision 1.2
	common/lib/libc/arch/aarch64/atomic/atomic_swap_64.S: revision 1.5
	common/lib/libc/arch/aarch64/atomic/atomic_inc_32.S: revision 1.2
	common/lib/libc/arch/aarch64/atomic/atomic_or_64.S: revision 1.3
	common/lib/libc/arch/aarch64/atomic/atomic_and_16.S: revision 1.2
	common/lib/libc/arch/aarch64/atomic/atomic_xor_64.S: revision 1.2
	common/lib/libc/arch/aarch64/atomic/atomic_and_32.S: revision 1.2
	common/lib/libc/arch/aarch64/atomic/atomic_nand_8.S: revision 1.2
	common/lib/libc/arch/aarch64/atomic/atomic_add_64.S: revision 1.2
	common/lib/libc/arch/aarch64/atomic/atomic_op_asm.h: revision 1.5
	common/lib/libc/arch/aarch64/atomic/atomic_swap_8.S: revision 1.2
	common/lib/libc/arch/aarch64/atomic/atomic_op_asm.h: revision 1.6
	common/lib/libc/arch/aarch64/atomic/atomic_cas_64.S: revision 1.4
	common/lib/libc/arch/aarch64/atomic/atomic_nand_8.S: revision 1.5
	common/lib/libc/arch/aarch64/atomic/atomic_sub_16.S: revision 1.2
	common/lib/libc/arch/aarch64/atomic/atomic_cas_64.S: revision 1.6
	common/lib/libc/arch/aarch64/atomic/atomic_swap_8.S: revision 1.5
	common/lib/libc/arch/aarch64/atomic/atomic_sub_32.S: revision 1.2
	common/lib/libc/arch/aarch64/atomic/atomic_swap_32.S: revision 1.2
	common/lib/libc/arch/aarch64/atomic/atomic_nand_64.S: revision 1.2
	common/lib/libc/arch/aarch64/atomic/atomic_swap_16.S: revision 1.2
	common/lib/libc/arch/aarch64/atomic/atomic_xor_8.S: revision 1.2
	common/lib/libc/arch/aarch64/atomic/atomic_swap_32.S: revision 1.5
	common/lib/libc/arch/aarch64/atomic/atomic_or_32.S: revision 1.2
	common/lib/libc/arch/aarch64/atomic/atomic_nand_64.S: revision 1.5
	common/lib/libc/arch/aarch64/atomic/atomic_swap_16.S: revision 1.5
	common/lib/libc/arch/aarch64/atomic/atomic_or_8.S: revision 1.2
	common/lib/libc/arch/aarch64/atomic/atomic_or_16.S: revision 1.2
	common/lib/libc/arch/aarch64/atomic/atomic_cas_16.S: revision 1.2
	common/lib/libc/arch/aarch64/atomic/atomic_xor_16.S: revision 1.2
	common/lib/libc/arch/aarch64/atomic/atomic_cas_32.S: revision 1.2
	common/lib/libc/arch/aarch64/atomic/atomic_cas_16.S: revision 1.4
	common/lib/libc/arch/aarch64/atomic/atomic_add_32.S: revision 1.2
	common/lib/libc/arch/aarch64/atomic/atomic_cas_8.S: revision 1.2
	common/lib/libc/arch/aarch64/atomic/atomic_xor_32.S: revision 1.2
	common/lib/libc/arch/aarch64/atomic/atomic_dec_64.S: revision 1.2
	common/lib/libc/arch/aarch64/atomic/atomic_cas_32.S: revision 1.4
	common/lib/libc/arch/aarch64/atomic/atomic_add_16.S: revision 1.2
	common/lib/libc/arch/aarch64/atomic/atomic_cas_8.S: revision 1.4
	common/lib/libc/arch/aarch64/atomic/membar_ops.S: revision 1.2
	common/lib/libc/arch/aarch64/atomic/atomic_nand_16.S: revision 1.2
	common/lib/libc/arch/aarch64/atomic/atomic_nand_32.S: revision 1.2
	common/lib/libc/arch/aarch64/atomic/atomic_nand_16.S: revision 1.5
	common/lib/libc/arch/aarch64/atomic/atomic_nand_32.S: revision 1.5
	common/lib/libc/arch/aarch64/atomic/atomic_inc_64.S: revision 1.2
	common/lib/libc/arch/aarch64/atomic/atomic_dec_32.S: revision 1.2
	common/lib/libc/arch/aarch64/atomic/atomic_and_8.S: revision 1.2
	common/lib/libc/arch/aarch64/atomic/atomic_and_64.S: revision 1.2

Part I of ad@'s performance improvements for aarch64
- Remove memory barriers from the atomic ops.  I don't understand why thos=
e
   are there.  Is it some architectural thing, or for a CPU bug, or just
   over-caution maybe?  They're not needed for correctness.
- Have unlikely conditional branches go forwards to help the static branch
   predictor.

Remove memory barriers from the atomic ops macros in the same way as was
done for the other atomic ops earlier.

Use the correct barriers - all of membar_{sync,producer,consumer} have
less scope than before.

LGTM from riastradh

As we're providing the legacy gcc __sync built-in functions for atomic
memory access we might as well get the memory barriers right...

 From the gcc documentation:

In most cases, these built-in functions are considered a full barrier.
That is, no memory operand is moved across the operation, either forward
or backward. Further, instructions are issued as necessary to prevent the
processor from speculating loads across the operation and from queuing
stores after the operation.

type __sync_lock_test_and_set (type *ptr, type value, ...)
    This built-in function is not a full barrier, but rather an acquire
    barrier. This means that references after the operation cannot move to
    (or be speculated to) before the operation, but previous memory stores
    may not be globally visible yet, and previous memory loads may not yet
    be satisfied.

void __sync_lock_release (type *ptr, ...)
    This built-in function is not a full barrier, but rather a release
    barrier. This means that all previous memory stores are globally
    visible, and all previous memory loads have been satisfied, but
    following memory reads are not prevented from being speculated to
    before the barrier.</pre>
</div>
</content>
</entry>
<entry>
<title>Pull up following revision(s) (requested by skrll in ticket #1330):</title>
<updated>2021-08-11T17:05:42+00:00</updated>
<author>
<name>martin</name>
<email>martin@NetBSD.org</email>
</author>
<published>2021-08-11T17:05:42+00:00</published>
<link rel='alternate' type='text/html' href='http://git.infra.scholz.ruhr/netbsd/commit/?id=64808e0cef9e4c9ea0be944266121cf333dadf3c'/>
<id>64808e0cef9e4c9ea0be944266121cf333dadf3c</id>
<content type='text'>
	common/lib/libc/arch/arm/atomic/atomic_swap.S: revision 1.18
	common/lib/libc/arch/arm/atomic/atomic_and_16.S: revision 1.5
	common/lib/libc/arch/arm/atomic/atomic_swap.S: revision 1.19
	common/lib/libc/arch/arm/atomic/atomic_xor_64.S: revision 1.6
	common/lib/libc/arch/arm/atomic/atomic_inc_32.S: revision 1.8
	common/lib/libc/arch/arm/atomic/atomic_and_32.S: revision 1.9
	common/lib/libc/arch/arm/atomic/atomic_add_8.S: revision 1.4
	common/lib/libc/arch/arm/atomic/atomic_xor_64.S: revision 1.7
	common/lib/libc/arch/arm/atomic/atomic_inc_32.S: revision 1.9
	common/lib/libc/arch/arm/atomic/atomic_cas_up.S: revision 1.8
	common/lib/libc/arch/arm/atomic/atomic_add_8.S: revision 1.5
	common/lib/libc/arch/arm/atomic/atomic_op_asm.h: revision 1.9
	common/lib/libc/arch/arm/atomic/membar_ops.S: revision 1.8
	common/lib/libc/arch/arm/atomic/membar_ops.S: revision 1.9
	common/lib/libc/arch/arm/atomic/atomic_op_asm.h: revision 1.10
	common/lib/libc/arch/arm/atomic/atomic_and_32.S: revision 1.10
	common/lib/libc/arch/arm/atomic/atomic_cas_16.S: revision 1.3
	common/lib/libc/arch/arm/atomic/sync_fetch_and_and_8.S: revision 1.6
	common/lib/libc/arch/arm/atomic/atomic_xor_32.S: revision 1.4
	common/lib/libc/arch/arm/atomic/atomic_xor_32.S: revision 1.5
	common/lib/libc/arch/arm/atomic/atomic_nand_64.S: revision 1.6
	common/lib/libc/arch/arm/atomic/atomic_xor_16.S: revision 1.4
	common/lib/libc/arch/arm/atomic/atomic_swap_16.S: revision 1.6
	common/lib/libc/arch/arm/atomic/atomic_nand_64.S: revision 1.7
	common/lib/libc/arch/arm/atomic/atomic_cas_32.S: revision 1.8
	common/lib/libc/arch/arm/atomic/atomic_xor_16.S: revision 1.5
	common/lib/libc/arch/arm/atomic/atomic_swap_16.S: revision 1.7
	common/lib/libc/arch/arm/atomic/atomic_add_32.S: revision 1.10
	common/lib/libc/arch/arm/atomic/sync_fetch_and_add_8.S: revision 1.6
	common/lib/libc/arch/arm/atomic/atomic_dec_64.S: revision 1.8
	common/lib/libc/arch/arm/atomic/atomic_add_16.S: revision 1.4
	common/lib/libc/arch/arm/atomic/sync_fetch_and_sub_8.S: revision 1.6
	common/lib/libc/arch/arm/atomic/atomic_xor_8.S: revision 1.4
	common/lib/libc/arch/arm/atomic/atomic_dec_64.S: revision 1.9
	common/lib/libc/arch/arm/atomic/atomic_add_16.S: revision 1.5
	common/lib/libc/arch/arm/atomic/atomic_xor_8.S: revision 1.5
	common/lib/libc/arch/arm/atomic/atomic_or_64.S: revision 1.13
	common/lib/libc/arch/arm/atomic/atomic_add_32.S: revision 1.9
	common/lib/libc/arch/arm/atomic/atomic_or_64.S: revision 1.14
	common/lib/libc/arch/arm/atomic/atomic_or_16.S: revision 1.4
	common/lib/libc/arch/arm/atomic/atomic_or_16.S: revision 1.5
	common/lib/libc/arch/arm/atomic/sync_fetch_and_nand_8.S: revision 1.6
	common/lib/libc/arch/arm/atomic/atomic_nand_16.S: revision 1.4
	common/lib/libc/arch/arm/atomic/atomic_nand_16.S: revision 1.5
	common/lib/libc/arch/arm/atomic/sync_fetch_and_or_8.S: revision 1.6
	common/lib/libc/arch/arm/atomic/atomic_nand_32.S: revision 1.4
	common/lib/libc/arch/arm/atomic/atomic_or_32.S: revision 1.9
	common/lib/libc/arch/arm/atomic/atomic_nand_32.S: revision 1.5
	common/lib/libc/arch/arm/atomic/atomic_cas_8.S: revision 1.9
	common/lib/libc/arch/arm/atomic/atomic_inc_64.S: revision 1.10
	common/lib/libc/arch/arm/atomic/atomic_inc_64.S: revision 1.11
	common/lib/libc/arch/arm/atomic/atomic_cas_64.S: revision 1.12
	common/lib/libc/arch/arm/atomic/sync_bool_compare_and_swap_8.S: revision 1.5
	common/lib/libc/arch/arm/atomic/atomic_or_8.S: revision 1.4
	common/lib/libc/arch/arm/atomic/atomic_dec_32.S: revision 1.6
	common/lib/libc/arch/arm/atomic/atomic_or_8.S: revision 1.5
	common/lib/libc/arch/arm/atomic/atomic_dec_32.S: revision 1.7
	common/lib/libc/arch/arm/atomic/atomic_sub_64.S: revision 1.4
	common/lib/libc/arch/arm/atomic/atomic_sub_64.S: revision 1.5
	common/lib/libc/arch/arm/atomic/sync_fetch_and_xor_8.S: revision 1.6
	common/lib/libc/arch/arm/atomic/sync_bool_compare_and_swap_4.S: revision 1.4
	common/lib/libc/arch/arm/atomic/atomic_and_64.S: revision 1.12
	common/lib/libc/arch/arm/atomic/atomic_or_32.S: revision 1.10
	common/lib/libc/arch/arm/atomic/atomic_and_64.S: revision 1.13
	common/lib/libc/arch/arm/atomic/sync_bool_compare_and_swap_2.S: revision 1.4
	common/lib/libc/arch/arm/atomic/atomic_swap_64.S: revision 1.14
	common/lib/libc/arch/arm/atomic/sync_bool_compare_and_swap_1.S: revision 1.4
	common/lib/libc/arch/arm/atomic/atomic_nand_8.S: revision 1.4
	common/lib/libc/arch/arm/atomic/atomic_and_8.S: revision 1.4
	common/lib/libc/arch/arm/atomic/atomic_add_64.S: revision 1.13
	common/lib/libc/arch/arm/atomic/atomic_nand_8.S: revision 1.5
	common/lib/libc/arch/arm/atomic/atomic_and_8.S: revision 1.5
	common/lib/libc/arch/arm/atomic/atomic_and_16.S: revision 1.4
	common/lib/libc/arch/arm/atomic/atomic_add_64.S: revision 1.14

Give the thumb atomic ops a chance of working

s/ifdef _ARM_ARCH_6/if defined(_ARM_ARCH_6)/ for consistency.  NFCI.

Remove memory barriers from the atomic_ops(3) atomic operations.  They're
not needed for correctness.

Add the correct memory barriers to the gcc legacy __sync built-in
functions for atomic memory access.  From the gcc documentation:

In most cases, these built-in functions are considered a full barrier.

That is, no memory operand is moved across the operation, either forward
or backward. Further, instructions are issued as necessary to prevent the
processor from speculating loads across the operation and from queuing
stores after the operation.

type __sync_lock_test_and_set (type *ptr, type value, ...)
    This built-in function is not a full barrier, but rather an acquire
    barrier. This means that references after the operation cannot move to
    (or be speculated to) before the operation, but previous memory stores
    may not be globally visible yet, and previous memory loads may not yet
    be satisfied.

void __sync_lock_release (type *ptr, ...)
    This built-in function is not a full barrier, but rather a release
    barrier. This means that all previous memory stores are globally
    visible, and all previous memory loads have been satisfied, but
    following memory reads are not prevented from being speculated to
    before the barrier.</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
	common/lib/libc/arch/arm/atomic/atomic_swap.S: revision 1.18
	common/lib/libc/arch/arm/atomic/atomic_and_16.S: revision 1.5
	common/lib/libc/arch/arm/atomic/atomic_swap.S: revision 1.19
	common/lib/libc/arch/arm/atomic/atomic_xor_64.S: revision 1.6
	common/lib/libc/arch/arm/atomic/atomic_inc_32.S: revision 1.8
	common/lib/libc/arch/arm/atomic/atomic_and_32.S: revision 1.9
	common/lib/libc/arch/arm/atomic/atomic_add_8.S: revision 1.4
	common/lib/libc/arch/arm/atomic/atomic_xor_64.S: revision 1.7
	common/lib/libc/arch/arm/atomic/atomic_inc_32.S: revision 1.9
	common/lib/libc/arch/arm/atomic/atomic_cas_up.S: revision 1.8
	common/lib/libc/arch/arm/atomic/atomic_add_8.S: revision 1.5
	common/lib/libc/arch/arm/atomic/atomic_op_asm.h: revision 1.9
	common/lib/libc/arch/arm/atomic/membar_ops.S: revision 1.8
	common/lib/libc/arch/arm/atomic/membar_ops.S: revision 1.9
	common/lib/libc/arch/arm/atomic/atomic_op_asm.h: revision 1.10
	common/lib/libc/arch/arm/atomic/atomic_and_32.S: revision 1.10
	common/lib/libc/arch/arm/atomic/atomic_cas_16.S: revision 1.3
	common/lib/libc/arch/arm/atomic/sync_fetch_and_and_8.S: revision 1.6
	common/lib/libc/arch/arm/atomic/atomic_xor_32.S: revision 1.4
	common/lib/libc/arch/arm/atomic/atomic_xor_32.S: revision 1.5
	common/lib/libc/arch/arm/atomic/atomic_nand_64.S: revision 1.6
	common/lib/libc/arch/arm/atomic/atomic_xor_16.S: revision 1.4
	common/lib/libc/arch/arm/atomic/atomic_swap_16.S: revision 1.6
	common/lib/libc/arch/arm/atomic/atomic_nand_64.S: revision 1.7
	common/lib/libc/arch/arm/atomic/atomic_cas_32.S: revision 1.8
	common/lib/libc/arch/arm/atomic/atomic_xor_16.S: revision 1.5
	common/lib/libc/arch/arm/atomic/atomic_swap_16.S: revision 1.7
	common/lib/libc/arch/arm/atomic/atomic_add_32.S: revision 1.10
	common/lib/libc/arch/arm/atomic/sync_fetch_and_add_8.S: revision 1.6
	common/lib/libc/arch/arm/atomic/atomic_dec_64.S: revision 1.8
	common/lib/libc/arch/arm/atomic/atomic_add_16.S: revision 1.4
	common/lib/libc/arch/arm/atomic/sync_fetch_and_sub_8.S: revision 1.6
	common/lib/libc/arch/arm/atomic/atomic_xor_8.S: revision 1.4
	common/lib/libc/arch/arm/atomic/atomic_dec_64.S: revision 1.9
	common/lib/libc/arch/arm/atomic/atomic_add_16.S: revision 1.5
	common/lib/libc/arch/arm/atomic/atomic_xor_8.S: revision 1.5
	common/lib/libc/arch/arm/atomic/atomic_or_64.S: revision 1.13
	common/lib/libc/arch/arm/atomic/atomic_add_32.S: revision 1.9
	common/lib/libc/arch/arm/atomic/atomic_or_64.S: revision 1.14
	common/lib/libc/arch/arm/atomic/atomic_or_16.S: revision 1.4
	common/lib/libc/arch/arm/atomic/atomic_or_16.S: revision 1.5
	common/lib/libc/arch/arm/atomic/sync_fetch_and_nand_8.S: revision 1.6
	common/lib/libc/arch/arm/atomic/atomic_nand_16.S: revision 1.4
	common/lib/libc/arch/arm/atomic/atomic_nand_16.S: revision 1.5
	common/lib/libc/arch/arm/atomic/sync_fetch_and_or_8.S: revision 1.6
	common/lib/libc/arch/arm/atomic/atomic_nand_32.S: revision 1.4
	common/lib/libc/arch/arm/atomic/atomic_or_32.S: revision 1.9
	common/lib/libc/arch/arm/atomic/atomic_nand_32.S: revision 1.5
	common/lib/libc/arch/arm/atomic/atomic_cas_8.S: revision 1.9
	common/lib/libc/arch/arm/atomic/atomic_inc_64.S: revision 1.10
	common/lib/libc/arch/arm/atomic/atomic_inc_64.S: revision 1.11
	common/lib/libc/arch/arm/atomic/atomic_cas_64.S: revision 1.12
	common/lib/libc/arch/arm/atomic/sync_bool_compare_and_swap_8.S: revision 1.5
	common/lib/libc/arch/arm/atomic/atomic_or_8.S: revision 1.4
	common/lib/libc/arch/arm/atomic/atomic_dec_32.S: revision 1.6
	common/lib/libc/arch/arm/atomic/atomic_or_8.S: revision 1.5
	common/lib/libc/arch/arm/atomic/atomic_dec_32.S: revision 1.7
	common/lib/libc/arch/arm/atomic/atomic_sub_64.S: revision 1.4
	common/lib/libc/arch/arm/atomic/atomic_sub_64.S: revision 1.5
	common/lib/libc/arch/arm/atomic/sync_fetch_and_xor_8.S: revision 1.6
	common/lib/libc/arch/arm/atomic/sync_bool_compare_and_swap_4.S: revision 1.4
	common/lib/libc/arch/arm/atomic/atomic_and_64.S: revision 1.12
	common/lib/libc/arch/arm/atomic/atomic_or_32.S: revision 1.10
	common/lib/libc/arch/arm/atomic/atomic_and_64.S: revision 1.13
	common/lib/libc/arch/arm/atomic/sync_bool_compare_and_swap_2.S: revision 1.4
	common/lib/libc/arch/arm/atomic/atomic_swap_64.S: revision 1.14
	common/lib/libc/arch/arm/atomic/sync_bool_compare_and_swap_1.S: revision 1.4
	common/lib/libc/arch/arm/atomic/atomic_nand_8.S: revision 1.4
	common/lib/libc/arch/arm/atomic/atomic_and_8.S: revision 1.4
	common/lib/libc/arch/arm/atomic/atomic_add_64.S: revision 1.13
	common/lib/libc/arch/arm/atomic/atomic_nand_8.S: revision 1.5
	common/lib/libc/arch/arm/atomic/atomic_and_8.S: revision 1.5
	common/lib/libc/arch/arm/atomic/atomic_and_16.S: revision 1.4
	common/lib/libc/arch/arm/atomic/atomic_add_64.S: revision 1.14

Give the thumb atomic ops a chance of working

s/ifdef _ARM_ARCH_6/if defined(_ARM_ARCH_6)/ for consistency.  NFCI.

Remove memory barriers from the atomic_ops(3) atomic operations.  They're
not needed for correctness.

Add the correct memory barriers to the gcc legacy __sync built-in
functions for atomic memory access.  From the gcc documentation:

In most cases, these built-in functions are considered a full barrier.

That is, no memory operand is moved across the operation, either forward
or backward. Further, instructions are issued as necessary to prevent the
processor from speculating loads across the operation and from queuing
stores after the operation.

type __sync_lock_test_and_set (type *ptr, type value, ...)
    This built-in function is not a full barrier, but rather an acquire
    barrier. This means that references after the operation cannot move to
    (or be speculated to) before the operation, but previous memory stores
    may not be globally visible yet, and previous memory loads may not yet
    be satisfied.

void __sync_lock_release (type *ptr, ...)
    This built-in function is not a full barrier, but rather a release
    barrier. This means that all previous memory stores are globally
    visible, and all previous memory loads have been satisfied, but
    following memory reads are not prevented from being speculated to
    before the barrier.</pre>
</div>
</content>
</entry>
<entry>
<title>Pull up following revision(s) (requested by skrll in ticket #1319):</title>
<updated>2021-07-08T11:22:01+00:00</updated>
<author>
<name>martin</name>
<email>martin@NetBSD.org</email>
</author>
<published>2021-07-08T11:22:01+00:00</published>
<link rel='alternate' type='text/html' href='http://git.infra.scholz.ruhr/netbsd/commit/?id=bc8a354aef7585978b6ae4380bdb2e673ea434ff'/>
<id>bc8a354aef7585978b6ae4380bdb2e673ea434ff</id>
<content type='text'>
	common/lib/libc/arch/aarch64/atomic/atomic_nand_16.S: revision 1.4

One more s/pte/ptr/</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
	common/lib/libc/arch/aarch64/atomic/atomic_nand_16.S: revision 1.4

One more s/pte/ptr/</pre>
</div>
</content>
</entry>
<entry>
<title>Pull up following revision(s) (requested by skrll in ticket #1314):</title>
<updated>2021-07-06T04:13:50+00:00</updated>
<author>
<name>martin</name>
<email>martin@NetBSD.org</email>
</author>
<published>2021-07-06T04:13:50+00:00</published>
<link rel='alternate' type='text/html' href='http://git.infra.scholz.ruhr/netbsd/commit/?id=0b2f0d04b0cc3b8dac61703b951d6dcaada73b2c'/>
<id>0b2f0d04b0cc3b8dac61703b951d6dcaada73b2c</id>
<content type='text'>
	common/lib/libc/arch/aarch64/atomic/atomic_nand_8.S: revision 1.3
	common/lib/libc/arch/aarch64/atomic/atomic_nand_8.S: revision 1.4
	common/lib/libc/arch/aarch64/atomic/atomic_nand_64.S: revision 1.3
	common/lib/libc/arch/aarch64/atomic/atomic_nand_64.S: revision 1.4
	common/lib/libc/arch/aarch64/atomic/atomic_nand_16.S: revision 1.3
	common/lib/libc/arch/aarch64/atomic/atomic_nand_32.S: revision 1.3
	common/lib/libc/arch/aarch64/atomic/atomic_nand_32.S: revision 1.4

Fix the logic operation for atomic_nand_{8,16,32,64}

 From the gcc docs the operations are as follows
  { tmp = *ptr; *ptr = ~(tmp &amp; value); return tmp; }   // nand
  { tmp = ~(*ptr &amp; value); *ptr = tmp; return *ptr; }   // nand

yes, this is really rather strange.

typo in comment s/pte/ptr/</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
	common/lib/libc/arch/aarch64/atomic/atomic_nand_8.S: revision 1.3
	common/lib/libc/arch/aarch64/atomic/atomic_nand_8.S: revision 1.4
	common/lib/libc/arch/aarch64/atomic/atomic_nand_64.S: revision 1.3
	common/lib/libc/arch/aarch64/atomic/atomic_nand_64.S: revision 1.4
	common/lib/libc/arch/aarch64/atomic/atomic_nand_16.S: revision 1.3
	common/lib/libc/arch/aarch64/atomic/atomic_nand_32.S: revision 1.3
	common/lib/libc/arch/aarch64/atomic/atomic_nand_32.S: revision 1.4

Fix the logic operation for atomic_nand_{8,16,32,64}

 From the gcc docs the operations are as follows
  { tmp = *ptr; *ptr = ~(tmp &amp; value); return tmp; }   // nand
  { tmp = ~(*ptr &amp; value); *ptr = tmp; return *ptr; }   // nand

yes, this is really rather strange.

typo in comment s/pte/ptr/</pre>
</div>
</content>
</entry>
<entry>
<title>Pull up following revision(s) (requested by skrll in ticket #1313):</title>
<updated>2021-07-06T04:11:31+00:00</updated>
<author>
<name>martin</name>
<email>martin@NetBSD.org</email>
</author>
<published>2021-07-06T04:11:31+00:00</published>
<link rel='alternate' type='text/html' href='http://git.infra.scholz.ruhr/netbsd/commit/?id=e9f7ec794c00bc3aa4378084ed51015dbc9414f5'/>
<id>e9f7ec794c00bc3aa4378084ed51015dbc9414f5</id>
<content type='text'>
	common/lib/libc/arch/arm/atomic/atomic_xor_64.S: revision 1.5
	common/lib/libc/arch/arm/atomic/atomic_nand_64.S: revision 1.5
	common/lib/libc/arch/arm/atomic/atomic_or_64.S: revision 1.12
	common/lib/libc/arch/arm/atomic/atomic_cas_8.S: revision 1.8
	common/lib/libc/arch/arm/atomic/atomic_sub_64.S: revision 1.3
	common/lib/libc/arch/arm/atomic/atomic_and_64.S: revision 1.11
	common/lib/libc/arch/arm/atomic/atomic_swap_64.S: revision 1.13
	common/lib/libc/arch/arm/atomic/atomic_add_64.S: revision 1.12

Whitespace</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
	common/lib/libc/arch/arm/atomic/atomic_xor_64.S: revision 1.5
	common/lib/libc/arch/arm/atomic/atomic_nand_64.S: revision 1.5
	common/lib/libc/arch/arm/atomic/atomic_or_64.S: revision 1.12
	common/lib/libc/arch/arm/atomic/atomic_cas_8.S: revision 1.8
	common/lib/libc/arch/arm/atomic/atomic_sub_64.S: revision 1.3
	common/lib/libc/arch/arm/atomic/atomic_and_64.S: revision 1.11
	common/lib/libc/arch/arm/atomic/atomic_swap_64.S: revision 1.13
	common/lib/libc/arch/arm/atomic/atomic_add_64.S: revision 1.12

Whitespace</pre>
</div>
</content>
</entry>
<entry>
<title>Pull up following revision(s) (requested by skrll in ticket #1261):</title>
<updated>2021-04-30T13:54:00+00:00</updated>
<author>
<name>martin</name>
<email>martin@NetBSD.org</email>
</author>
<published>2021-04-30T13:54:00+00:00</published>
<link rel='alternate' type='text/html' href='http://git.infra.scholz.ruhr/netbsd/commit/?id=90274acc20309fdd0e55599effe1e77d28c8f76c'/>
<id>90274acc20309fdd0e55599effe1e77d28c8f76c</id>
<content type='text'>
	sys/arch/arm/include/lock.h: revision 1.38
	common/lib/libc/arch/arm/atomic/membar_ops.S: revision 1.7
	common/lib/libc/arch/arm/atomic/atomic_swap_16.S: revision 1.5
	common/lib/libc/arch/arm/atomic/atomic_swap_64.S: revision 1.12
	common/lib/libc/arch/arm/atomic/atomic_swap.S: revision 1.17

Add the appropriate memory barrier before the lock is cleared in
__sync_lock_release_{1,2,4,8}.  That is, all reads and write for the
inner shareability domain before the lock clear store.

Improve the membar_ops barriers - no need to use dsb and wait for
completion.  Also, we only to act on the inner shareability domain.

Fix the barrier confusion.  From Riastradh - thanks!.</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
	sys/arch/arm/include/lock.h: revision 1.38
	common/lib/libc/arch/arm/atomic/membar_ops.S: revision 1.7
	common/lib/libc/arch/arm/atomic/atomic_swap_16.S: revision 1.5
	common/lib/libc/arch/arm/atomic/atomic_swap_64.S: revision 1.12
	common/lib/libc/arch/arm/atomic/atomic_swap.S: revision 1.17

Add the appropriate memory barrier before the lock is cleared in
__sync_lock_release_{1,2,4,8}.  That is, all reads and write for the
inner shareability domain before the lock clear store.

Improve the membar_ops barriers - no need to use dsb and wait for
completion.  Also, we only to act on the inner shareability domain.

Fix the barrier confusion.  From Riastradh - thanks!.</pre>
</div>
</content>
</entry>
<entry>
<title>Pull up following revision(s) (requested by skrll in ticket #1254):</title>
<updated>2021-04-26T18:34:28+00:00</updated>
<author>
<name>martin</name>
<email>martin@NetBSD.org</email>
</author>
<published>2021-04-26T18:34:28+00:00</published>
<link rel='alternate' type='text/html' href='http://git.infra.scholz.ruhr/netbsd/commit/?id=f2ef47fb1a107afe04c2d2bf02ec05cb0b492a80'/>
<id>f2ef47fb1a107afe04c2d2bf02ec05cb0b492a80</id>
<content type='text'>
	sys/arch/arm/include/lock.h: revision 1.37
	common/lib/libc/arch/arm/atomic/atomic_swap_64.S: revision 1.11
	common/lib/libc/arch/arm/atomic/atomic_swap.S: revision 1.15
	common/lib/libc/arch/arm/atomic/atomic_swap.S: revision 1.16
	sys/arch/arm/include/lock.h: revision 1.36

Fix ARMv8 instructions

Fix __sync_lock_release_4 to actually zeroise the whole 4bytes/32bits.

Trailing whitespace

Change #ifdef FOO to #if defined(FOO).  NFCI.</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
	sys/arch/arm/include/lock.h: revision 1.37
	common/lib/libc/arch/arm/atomic/atomic_swap_64.S: revision 1.11
	common/lib/libc/arch/arm/atomic/atomic_swap.S: revision 1.15
	common/lib/libc/arch/arm/atomic/atomic_swap.S: revision 1.16
	sys/arch/arm/include/lock.h: revision 1.36

Fix ARMv8 instructions

Fix __sync_lock_release_4 to actually zeroise the whole 4bytes/32bits.

Trailing whitespace

Change #ifdef FOO to #if defined(FOO).  NFCI.</pre>
</div>
</content>
</entry>
<entry>
<title>Pull up following revision(s) (requested by rin in ticket #755):</title>
<updated>2020-03-03T18:54:59+00:00</updated>
<author>
<name>martin</name>
<email>martin@NetBSD.org</email>
</author>
<published>2020-03-03T18:54:59+00:00</published>
<link rel='alternate' type='text/html' href='http://git.infra.scholz.ruhr/netbsd/commit/?id=a328d3c678f70d894b1f2608a44367bf83a29caf'/>
<id>a328d3c678f70d894b1f2608a44367bf83a29caf</id>
<content type='text'>
	sys/arch/evbppc/conf/std.virtex: revision 1.4
	sys/arch/powerpc/powerpc/trap_subr.S: revision 1.81
	sys/arch/powerpc/ibm4xx/4xx_trap_subr.S: revision 1.8
	sys/arch/evbppc/conf/std.walnut: revision 1.9
	common/lib/libc/arch/powerpc/atomic/atomic_op_asm.h: revision 1.7
	sys/arch/powerpc/include/asm.h: revision 1.49
	common/lib/libc/arch/powerpc/atomic/atomic_cas.S: revision 1.9
	sys/arch/powerpc/ibm4xx/trap_subr.S: revision 1.28
	sys/arch/powerpc/include/lock.h: revision 1.15
	sys/arch/evbppc/conf/std.obs266: revision 1.3
	common/lib/libc/arch/powerpc/atomic/atomic_swap.S: revision 1.8
	sys/arch/powerpc/powerpc/locore_subr.S: revision 1.61
	sys/arch/powerpc/powerpc/lock_stubs.S: revision 1.12
	sys/arch/evbppc/conf/std.obs200: revision 1.5

Implement workaround for IBM405 Errata 77 (aka CPU_210), where
interrupted stwcx. may errantly write data to memory:

     https://elinux.org/images/1/1d/Ppc405gp-errata.pdf

This is because stwcx. is split into two pieces in the pipeline.

We need to
(1) insert dcbt before every stwcx. instruction, as well as
(2) insert sync before every rfi/rfci instruction.

It is unclear which processors are affected, but according to Linux,
all 405-based cores up until 405GPR and 405EP are affected:

     https://github.com/torvalds/linux/blob/master/arch/powerpc/platforms/40x/Kconfig#L140

For kernel, this workaround can be restricted to affected processors.

However, for kernel modules and userland, we have to enable it for all
32bit powerpc archs in order to share common binaries as before.
Proposed on port-powerpc:

     http://mail-index.netbsd.org/port-powerpc/2020/02/21/msg003583.html</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
	sys/arch/evbppc/conf/std.virtex: revision 1.4
	sys/arch/powerpc/powerpc/trap_subr.S: revision 1.81
	sys/arch/powerpc/ibm4xx/4xx_trap_subr.S: revision 1.8
	sys/arch/evbppc/conf/std.walnut: revision 1.9
	common/lib/libc/arch/powerpc/atomic/atomic_op_asm.h: revision 1.7
	sys/arch/powerpc/include/asm.h: revision 1.49
	common/lib/libc/arch/powerpc/atomic/atomic_cas.S: revision 1.9
	sys/arch/powerpc/ibm4xx/trap_subr.S: revision 1.28
	sys/arch/powerpc/include/lock.h: revision 1.15
	sys/arch/evbppc/conf/std.obs266: revision 1.3
	common/lib/libc/arch/powerpc/atomic/atomic_swap.S: revision 1.8
	sys/arch/powerpc/powerpc/locore_subr.S: revision 1.61
	sys/arch/powerpc/powerpc/lock_stubs.S: revision 1.12
	sys/arch/evbppc/conf/std.obs200: revision 1.5

Implement workaround for IBM405 Errata 77 (aka CPU_210), where
interrupted stwcx. may errantly write data to memory:

     https://elinux.org/images/1/1d/Ppc405gp-errata.pdf

This is because stwcx. is split into two pieces in the pipeline.

We need to
(1) insert dcbt before every stwcx. instruction, as well as
(2) insert sync before every rfi/rfci instruction.

It is unclear which processors are affected, but according to Linux,
all 405-based cores up until 405GPR and 405EP are affected:

     https://github.com/torvalds/linux/blob/master/arch/powerpc/platforms/40x/Kconfig#L140

For kernel, this workaround can be restricted to affected processors.

However, for kernel modules and userland, we have to enable it for all
32bit powerpc archs in order to share common binaries as before.
Proposed on port-powerpc:

     http://mail-index.netbsd.org/port-powerpc/2020/02/21/msg003583.html</pre>
</div>
</content>
</entry>
</feed>
