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authorchristos <christos@NetBSD.org>2011-09-24 22:20:22 +0000
committerchristos <christos@NetBSD.org>2011-09-24 22:20:22 +0000
commitb075ecf291e34649961bbcb5ce206368a4c4f4e9 (patch)
treed77c336cb42f2096f85d00b4fceebda7683f55e3 /external/gpl3/binutils/dist/include/opcode
parentb3ac4aed2ab00b9a2ebb425421e5d0f13bf5aebc (diff)
from ftp.gnu.org
Diffstat (limited to 'external/gpl3/binutils/dist/include/opcode')
-rw-r--r--external/gpl3/binutils/dist/include/opcode/alpha.h27
-rw-r--r--external/gpl3/binutils/dist/include/opcode/arc.h7
-rw-r--r--external/gpl3/binutils/dist/include/opcode/arm.h88
-rw-r--r--external/gpl3/binutils/dist/include/opcode/avr.h7
-rw-r--r--external/gpl3/binutils/dist/include/opcode/bfin.h212
-rw-r--r--external/gpl3/binutils/dist/include/opcode/cgen.h51
-rw-r--r--external/gpl3/binutils/dist/include/opcode/convex.h27
-rw-r--r--external/gpl3/binutils/dist/include/opcode/cr16.h4
-rw-r--r--external/gpl3/binutils/dist/include/opcode/cris.h27
-rw-r--r--external/gpl3/binutils/dist/include/opcode/crx.h7
-rw-r--r--external/gpl3/binutils/dist/include/opcode/d10v.h27
-rw-r--r--external/gpl3/binutils/dist/include/opcode/d30v.h28
-rw-r--r--external/gpl3/binutils/dist/include/opcode/dlx.h7
-rw-r--r--external/gpl3/binutils/dist/include/opcode/h8300.h128
-rw-r--r--external/gpl3/binutils/dist/include/opcode/i370.h28
-rw-r--r--external/gpl3/binutils/dist/include/opcode/i386.h38
-rw-r--r--external/gpl3/binutils/dist/include/opcode/i860.h30
-rw-r--r--external/gpl3/binutils/dist/include/opcode/i960.h32
-rw-r--r--external/gpl3/binutils/dist/include/opcode/ia64.h34
-rw-r--r--external/gpl3/binutils/dist/include/opcode/m68hc11.h27
-rw-r--r--external/gpl3/binutils/dist/include/opcode/m68k.h8
-rw-r--r--external/gpl3/binutils/dist/include/opcode/m88k.h27
-rw-r--r--external/gpl3/binutils/dist/include/opcode/mmix.h27
-rw-r--r--external/gpl3/binutils/dist/include/opcode/mn10200.h27
-rw-r--r--external/gpl3/binutils/dist/include/opcode/mn10300.h27
-rw-r--r--external/gpl3/binutils/dist/include/opcode/moxie.h72
-rw-r--r--external/gpl3/binutils/dist/include/opcode/msp430.h7
-rw-r--r--external/gpl3/binutils/dist/include/opcode/np1.h35
-rw-r--r--external/gpl3/binutils/dist/include/opcode/ns32k.h28
-rw-r--r--external/gpl3/binutils/dist/include/opcode/or32.h7
-rw-r--r--external/gpl3/binutils/dist/include/opcode/pdp11.h31
-rw-r--r--external/gpl3/binutils/dist/include/opcode/pj.h26
-rw-r--r--external/gpl3/binutils/dist/include/opcode/pn.h27
-rw-r--r--external/gpl3/binutils/dist/include/opcode/pyr.h4
-rw-r--r--external/gpl3/binutils/dist/include/opcode/rx.h215
-rw-r--r--external/gpl3/binutils/dist/include/opcode/s390.h8
-rw-r--r--external/gpl3/binutils/dist/include/opcode/score-datadep.h229
-rw-r--r--external/gpl3/binutils/dist/include/opcode/score-inst.h315
-rw-r--r--external/gpl3/binutils/dist/include/opcode/sparc.h6
-rw-r--r--external/gpl3/binutils/dist/include/opcode/spu-insns.h4
-rw-r--r--external/gpl3/binutils/dist/include/opcode/spu.h5
-rw-r--r--external/gpl3/binutils/dist/include/opcode/tic30.h34
-rw-r--r--external/gpl3/binutils/dist/include/opcode/tic4x.h8
-rw-r--r--external/gpl3/binutils/dist/include/opcode/tic54x.h38
-rw-r--r--external/gpl3/binutils/dist/include/opcode/tic6x-control-registers.h56
-rw-r--r--external/gpl3/binutils/dist/include/opcode/tic6x-insn-formats.h198
-rw-r--r--external/gpl3/binutils/dist/include/opcode/tic6x-opcode-table.h2549
-rw-r--r--external/gpl3/binutils/dist/include/opcode/tic6x.h614
-rw-r--r--external/gpl3/binutils/dist/include/opcode/tic80.h27
-rw-r--r--external/gpl3/binutils/dist/include/opcode/v850.h121
-rw-r--r--external/gpl3/binutils/dist/include/opcode/vax.h27
51 files changed, 4528 insertions, 1115 deletions
diff --git a/external/gpl3/binutils/dist/include/opcode/alpha.h b/external/gpl3/binutils/dist/include/opcode/alpha.h
index 22c85a1f5ef..2c0d4f6cc74 100644
--- a/external/gpl3/binutils/dist/include/opcode/alpha.h
+++ b/external/gpl3/binutils/dist/include/opcode/alpha.h
@@ -1,23 +1,24 @@
/* alpha.h -- Header file for Alpha opcode table
- Copyright 1996, 1999, 2001, 2003 Free Software Foundation, Inc.
+ Copyright 1996, 1999, 2001, 2003, 2010 Free Software Foundation, Inc.
Contributed by Richard Henderson <rth@tamu.edu>,
patterned after the PPC opcode table written by Ian Lance Taylor.
-This file is part of GDB, GAS, and the GNU binutils.
+ This file is part of GDB, GAS, and the GNU binutils.
-GDB, GAS, and the GNU binutils are free software; you can redistribute
-them and/or modify them under the terms of the GNU General Public
-License as published by the Free Software Foundation; either version
-1, or (at your option) any later version.
+ GDB, GAS, and the GNU binutils are free software; you can redistribute
+ them and/or modify them under the terms of the GNU General Public
+ License as published by the Free Software Foundation; either version 3,
+ or (at your option) any later version.
-GDB, GAS, and the GNU binutils are distributed in the hope that they
-will be useful, but WITHOUT ANY WARRANTY; without even the implied
-warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
-the GNU General Public License for more details.
+ GDB, GAS, and the GNU binutils are distributed in the hope that they
+ will be useful, but WITHOUT ANY WARRANTY; without even the implied
+ warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
+ the GNU General Public License for more details.
-You should have received a copy of the GNU General Public License
-along with this file; see the file COPYING. If not, write to the Free
-Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
+ You should have received a copy of the GNU General Public License
+ along with this file; see the file COPYING3. If not, write to the Free
+ Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
+ MA 02110-1301, USA. */
#ifndef OPCODE_ALPHA_H
#define OPCODE_ALPHA_H
diff --git a/external/gpl3/binutils/dist/include/opcode/arc.h b/external/gpl3/binutils/dist/include/opcode/arc.h
index 8ddcf5433a4..695fec1ea8c 100644
--- a/external/gpl3/binutils/dist/include/opcode/arc.h
+++ b/external/gpl3/binutils/dist/include/opcode/arc.h
@@ -1,5 +1,5 @@
/* Opcode table for the ARC.
- Copyright 1994, 1995, 1997, 2001, 2002, 2003
+ Copyright 1994, 1995, 1997, 2001, 2002, 2003, 2010
Free Software Foundation, Inc.
Contributed by Doug Evans (dje@cygnus.com).
@@ -8,7 +8,7 @@
GAS/GDB is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2, or (at your option)
+ the Free Software Foundation; either version 3, or (at your option)
any later version.
GAS/GDB is distributed in the hope that it will be useful,
@@ -17,11 +17,10 @@
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
- along with GAS or GDB; see the file COPYING. If not, write to
+ along with GAS or GDB; see the file COPYING3. If not, write to
the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
-
/* List of the various cpu types.
The tables currently use bit masks to say whether the instruction or
whatever is supported by a particular cpu. This lets us have one entry
diff --git a/external/gpl3/binutils/dist/include/opcode/arm.h b/external/gpl3/binutils/dist/include/opcode/arm.h
index 11cab3e8448..50bc726a60f 100644
--- a/external/gpl3/binutils/dist/include/opcode/arm.h
+++ b/external/gpl3/binutils/dist/include/opcode/arm.h
@@ -1,11 +1,11 @@
/* ARM assembler/disassembler support.
- Copyright 2004 Free Software Foundation, Inc.
+ Copyright 2004, 2010 Free Software Foundation, Inc.
This file is part of GDB and GAS.
GDB and GAS are free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 1, or (at
+ published by the Free Software Foundation; either version 3, or (at
your option) any later version.
GDB and GAS are distributed in the hope that it will be useful, but
@@ -14,9 +14,9 @@
General Public License for more details.
You should have received a copy of the GNU General Public License
- along with GDB or GAS; see the file COPYING. If not, write to the
- Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
- 02110-1301, USA. */
+ along with GDB or GAS; see the file COPYING3. If not, write to the
+ Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
+ MA 02110-1301, USA. */
/* The following bitmasks control CPU extensions: */
#define ARM_EXT_V1 0x00000001 /* All processors (core set). */
@@ -33,7 +33,7 @@
#define ARM_EXT_V5J 0x00000800 /* Jazelle extension. */
#define ARM_EXT_V6 0x00001000 /* ARM V6. */
#define ARM_EXT_V6K 0x00002000 /* ARM V6K. */
-#define ARM_EXT_V6Z 0x00004000 /* ARM V6Z. */
+/* 0x00004000 Was ARM V6Z. */
#define ARM_EXT_V6T2 0x00008000 /* Thumb-2. */
#define ARM_EXT_DIV 0x00010000 /* Integer division. */
/* The 'M' in Arm V7M stands for Microcontroller.
@@ -47,6 +47,14 @@
#define ARM_EXT_V6M 0x00800000 /* ARM V6M. */
#define ARM_EXT_BARRIER 0x01000000 /* DSB/DMB/ISB. */
#define ARM_EXT_THUMB_MSR 0x02000000 /* Thumb MSR/MRS. */
+#define ARM_EXT_V6_DSP 0x04000000 /* ARM v6 (DSP-related),
+ not in v7-M. */
+#define ARM_EXT_MP 0x08000000 /* Multiprocessing Extensions. */
+#define ARM_EXT_SEC 0x10000000 /* Security extensions. */
+#define ARM_EXT_OS 0x20000000 /* OS Extensions. */
+#define ARM_EXT_ADIV 0x40000000 /* Integer divide extensions in ARM
+ state. */
+#define ARM_EXT_VIRT 0x80000000 /* Virtualization extensions. */
/* Co-processor space extensions. */
#define ARM_CEXT_XSCALE 0x00000001 /* Allow MIA etc. */
@@ -62,9 +70,13 @@
#define FPU_VFP_EXT_V1xD 0x08000000 /* Base VFP instruction set. */
#define FPU_VFP_EXT_V1 0x04000000 /* Double-precision insns. */
#define FPU_VFP_EXT_V2 0x02000000 /* ARM10E VFPr1. */
-#define FPU_VFP_EXT_V3 0x01000000 /* VFPv3 insns. */
-#define FPU_NEON_EXT_V1 0x00800000 /* Neon (SIMD) insns. */
-#define FPU_VFP_EXT_D32 0x00400000 /* Registers D16-D31. */
+#define FPU_VFP_EXT_V3xD 0x01000000 /* VFPv3 single-precision. */
+#define FPU_VFP_EXT_V3 0x00800000 /* VFPv3 double-precision. */
+#define FPU_NEON_EXT_V1 0x00400000 /* Neon (SIMD) insns. */
+#define FPU_VFP_EXT_D32 0x00200000 /* Registers D16-D31. */
+#define FPU_VFP_EXT_FP16 0x00100000 /* Half-precision extensions. */
+#define FPU_NEON_EXT_FMA 0x00080000 /* Neon fused multiply-add */
+#define FPU_VFP_EXT_FMA 0x00040000 /* VFP fused multiply-add */
/* Architectures are the sum of the base and extensions. The ARM ARM (rev E)
defines the following: ARMv3, ARMv3M, ARMv4xM, ARMv4, ARMv4TxM, ARMv4T,
@@ -89,25 +101,31 @@
#define ARM_AEXT_V5TEJ (ARM_AEXT_V5TE | ARM_EXT_V5J)
#define ARM_AEXT_V6 (ARM_AEXT_V5TEJ | ARM_EXT_V6)
#define ARM_AEXT_V6K (ARM_AEXT_V6 | ARM_EXT_V6K)
-#define ARM_AEXT_V6Z (ARM_AEXT_V6 | ARM_EXT_V6Z)
-#define ARM_AEXT_V6ZK (ARM_AEXT_V6 | ARM_EXT_V6K | ARM_EXT_V6Z)
+#define ARM_AEXT_V6Z (ARM_AEXT_V6K | ARM_EXT_SEC)
+#define ARM_AEXT_V6ZK (ARM_AEXT_V6K | ARM_EXT_SEC)
#define ARM_AEXT_V6T2 (ARM_AEXT_V6 \
- | ARM_EXT_V6T2 | ARM_EXT_V6_NOTM | ARM_EXT_THUMB_MSR)
+ | ARM_EXT_V6T2 | ARM_EXT_V6_NOTM | ARM_EXT_THUMB_MSR \
+ | ARM_EXT_V6_DSP )
#define ARM_AEXT_V6KT2 (ARM_AEXT_V6T2 | ARM_EXT_V6K)
-#define ARM_AEXT_V6ZT2 (ARM_AEXT_V6T2 | ARM_EXT_V6Z)
-#define ARM_AEXT_V6ZKT2 (ARM_AEXT_V6T2 | ARM_EXT_V6K | ARM_EXT_V6Z)
-#define ARM_AEXT_V7_ARM (ARM_AEXT_V6ZKT2 | ARM_EXT_V7 | ARM_EXT_BARRIER)
+#define ARM_AEXT_V6ZT2 (ARM_AEXT_V6T2 | ARM_EXT_SEC)
+#define ARM_AEXT_V6ZKT2 (ARM_AEXT_V6T2 | ARM_EXT_V6K | ARM_EXT_SEC)
+#define ARM_AEXT_V7_ARM (ARM_AEXT_V6KT2 | ARM_EXT_V7 | ARM_EXT_BARRIER)
#define ARM_AEXT_V7A (ARM_AEXT_V7_ARM | ARM_EXT_V7A)
#define ARM_AEXT_V7R (ARM_AEXT_V7_ARM | ARM_EXT_V7R | ARM_EXT_DIV)
#define ARM_AEXT_NOTM \
- (ARM_AEXT_V4 | ARM_EXT_V5ExP | ARM_EXT_V5J | ARM_EXT_V6_NOTM)
+ (ARM_AEXT_V4 | ARM_EXT_V5ExP | ARM_EXT_V5J | ARM_EXT_V6_NOTM \
+ | ARM_EXT_V6_DSP )
+#define ARM_AEXT_V6M_ONLY \
+ ((ARM_EXT_BARRIER | ARM_EXT_V6M | ARM_EXT_THUMB_MSR) & ~(ARM_AEXT_NOTM))
#define ARM_AEXT_V6M \
- ((ARM_AEXT_V6K | ARM_EXT_BARRIER | ARM_EXT_V6M | ARM_EXT_THUMB_MSR) \
- & ~(ARM_AEXT_NOTM))
+ ((ARM_AEXT_V6K | ARM_AEXT_V6M_ONLY) & ~(ARM_AEXT_NOTM))
+#define ARM_AEXT_V6SM (ARM_AEXT_V6M | ARM_EXT_OS)
#define ARM_AEXT_V7M \
((ARM_AEXT_V7_ARM | ARM_EXT_V6M | ARM_EXT_V7M | ARM_EXT_DIV) \
& ~(ARM_AEXT_NOTM))
#define ARM_AEXT_V7 (ARM_AEXT_V7A & ARM_AEXT_V7R & ARM_AEXT_V7M)
+#define ARM_AEXT_V7EM \
+ (ARM_AEXT_V7M | ARM_EXT_V5ExP | ARM_EXT_V6_DSP)
/* Processors with specific extensions in the co-processor space. */
#define ARM_ARCH_XSCALE ARM_FEATURE (ARM_AEXT_V5TE, ARM_CEXT_XSCALE)
@@ -119,9 +137,14 @@
#define FPU_VFP_V1xD (FPU_VFP_EXT_V1xD | FPU_ENDIAN_PURE)
#define FPU_VFP_V1 (FPU_VFP_V1xD | FPU_VFP_EXT_V1)
#define FPU_VFP_V2 (FPU_VFP_V1 | FPU_VFP_EXT_V2)
-#define FPU_VFP_V3D16 (FPU_VFP_V2 | FPU_VFP_EXT_V3)
+#define FPU_VFP_V3D16 (FPU_VFP_V2 | FPU_VFP_EXT_V3xD | FPU_VFP_EXT_V3)
#define FPU_VFP_V3 (FPU_VFP_V3D16 | FPU_VFP_EXT_D32)
+#define FPU_VFP_V3xD (FPU_VFP_V1xD | FPU_VFP_EXT_V2 | FPU_VFP_EXT_V3xD)
+#define FPU_VFP_V4D16 (FPU_VFP_V3D16 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA)
+#define FPU_VFP_V4 (FPU_VFP_V3 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA)
+#define FPU_VFP_V4_SP_D16 (FPU_VFP_V3xD | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA)
#define FPU_VFP_HARD (FPU_VFP_EXT_V1xD | FPU_VFP_EXT_V1 | FPU_VFP_EXT_V2 \
+ | FPU_VFP_EXT_V3xD | FPU_VFP_EXT_FMA | FPU_NEON_EXT_FMA \
| FPU_VFP_EXT_V3 | FPU_NEON_EXT_V1 | FPU_VFP_EXT_D32)
#define FPU_FPA (FPU_FPA_EXT_V1 | FPU_FPA_EXT_V2)
@@ -135,11 +158,23 @@
#define FPU_ARCH_VFP_V1 ARM_FEATURE (0, FPU_VFP_V1)
#define FPU_ARCH_VFP_V2 ARM_FEATURE (0, FPU_VFP_V2)
#define FPU_ARCH_VFP_V3D16 ARM_FEATURE (0, FPU_VFP_V3D16)
+#define FPU_ARCH_VFP_V3D16_FP16 \
+ ARM_FEATURE (0, FPU_VFP_V3D16 | FPU_VFP_EXT_FP16)
#define FPU_ARCH_VFP_V3 ARM_FEATURE (0, FPU_VFP_V3)
+#define FPU_ARCH_VFP_V3_FP16 ARM_FEATURE (0, FPU_VFP_V3 | FPU_VFP_EXT_FP16)
+#define FPU_ARCH_VFP_V3xD ARM_FEATURE (0, FPU_VFP_V3xD)
+#define FPU_ARCH_VFP_V3xD_FP16 ARM_FEATURE (0, FPU_VFP_V3xD | FPU_VFP_EXT_FP16)
#define FPU_ARCH_NEON_V1 ARM_FEATURE (0, FPU_NEON_EXT_V1)
#define FPU_ARCH_VFP_V3_PLUS_NEON_V1 \
ARM_FEATURE (0, FPU_VFP_V3 | FPU_NEON_EXT_V1)
+#define FPU_ARCH_NEON_FP16 \
+ ARM_FEATURE (0, FPU_VFP_V3 | FPU_NEON_EXT_V1 | FPU_VFP_EXT_FP16)
#define FPU_ARCH_VFP_HARD ARM_FEATURE (0, FPU_VFP_HARD)
+#define FPU_ARCH_VFP_V4 ARM_FEATURE(0, FPU_VFP_V4)
+#define FPU_ARCH_VFP_V4D16 ARM_FEATURE(0, FPU_VFP_V4D16)
+#define FPU_ARCH_VFP_V4_SP_D16 ARM_FEATURE(0, FPU_VFP_V4_SP_D16)
+#define FPU_ARCH_NEON_VFP_V4 \
+ ARM_FEATURE(0, FPU_VFP_V4 | FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA)
#define FPU_ARCH_ENDIAN_PURE ARM_FEATURE (0, FPU_ENDIAN_PURE)
@@ -170,10 +205,12 @@
#define ARM_ARCH_V6ZT2 ARM_FEATURE (ARM_AEXT_V6ZT2, 0)
#define ARM_ARCH_V6ZKT2 ARM_FEATURE (ARM_AEXT_V6ZKT2, 0)
#define ARM_ARCH_V6M ARM_FEATURE (ARM_AEXT_V6M, 0)
+#define ARM_ARCH_V6SM ARM_FEATURE (ARM_AEXT_V6SM, 0)
#define ARM_ARCH_V7 ARM_FEATURE (ARM_AEXT_V7, 0)
#define ARM_ARCH_V7A ARM_FEATURE (ARM_AEXT_V7A, 0)
#define ARM_ARCH_V7R ARM_FEATURE (ARM_AEXT_V7R, 0)
#define ARM_ARCH_V7M ARM_FEATURE (ARM_AEXT_V7M, 0)
+#define ARM_ARCH_V7EM ARM_FEATURE (ARM_AEXT_V7EM, 0)
/* Some useful combinations: */
#define ARM_ARCH_NONE ARM_FEATURE (0, 0)
@@ -181,6 +218,19 @@
#define ARM_ANY ARM_FEATURE (-1, 0) /* Any basic core. */
#define FPU_ANY_HARD ARM_FEATURE (0, FPU_FPA | FPU_VFP_HARD | FPU_MAVERICK)
#define ARM_ARCH_THUMB2 ARM_FEATURE (ARM_EXT_V6T2 | ARM_EXT_V7 | ARM_EXT_V7A | ARM_EXT_V7R | ARM_EXT_V7M | ARM_EXT_DIV, 0)
+/* v7-a+sec. */
+#define ARM_ARCH_V7A_SEC ARM_FEATURE (ARM_AEXT_V7A | ARM_EXT_SEC, 0)
+/* v7-a+mp+sec. */
+#define ARM_ARCH_V7A_MP_SEC \
+ ARM_FEATURE (ARM_AEXT_V7A | ARM_EXT_MP | ARM_EXT_SEC, \
+ 0)
+/* v7-a+idiv+mp+sec+virt. */
+#define ARM_ARCH_V7A_IDIV_MP_SEC_VIRT \
+ ARM_FEATURE (ARM_AEXT_V7A | ARM_EXT_MP | ARM_EXT_SEC \
+ | ARM_EXT_DIV | ARM_EXT_ADIV \
+ | ARM_EXT_VIRT, 0)
+/* Features that are present in v6M and v6S-M but not other v6 cores. */
+#define ARM_ARCH_V6M_ONLY ARM_FEATURE (ARM_AEXT_V6M_ONLY, 0)
/* There are too many feature bits to fit in a single word, so use a
structure. For simplicity we put all core features in one word and
diff --git a/external/gpl3/binutils/dist/include/opcode/avr.h b/external/gpl3/binutils/dist/include/opcode/avr.h
index 15a034a1563..bdf9823d840 100644
--- a/external/gpl3/binutils/dist/include/opcode/avr.h
+++ b/external/gpl3/binutils/dist/include/opcode/avr.h
@@ -1,11 +1,11 @@
/* Opcode table for the Atmel AVR micro controllers.
- Copyright 2000, 2001, 2004, 2006, 2008 Free Software Foundation, Inc.
+ Copyright 2000, 2001, 2004, 2006, 2008, 2010 Free Software Foundation, Inc.
Contributed by Denis Chertykov <denisc@overta.ru>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2, or (at your option)
+ the Free Software Foundation; either version 3, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
@@ -15,7 +15,8 @@
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
- Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
+ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+ MA 02110-1301, USA. */
#define AVR_ISA_1200 0x0001 /* In the beginning there was ... */
#define AVR_ISA_LPM 0x0002 /* device has LPM */
diff --git a/external/gpl3/binutils/dist/include/opcode/bfin.h b/external/gpl3/binutils/dist/include/opcode/bfin.h
index 4466fdce7a4..819ba6ee26e 100644
--- a/external/gpl3/binutils/dist/include/opcode/bfin.h
+++ b/external/gpl3/binutils/dist/include/opcode/bfin.h
@@ -1,21 +1,22 @@
/* bfin.h -- Header file for ADI Blackfin opcode table
- Copyright 2005 Free Software Foundation, Inc.
+ Copyright 2005, 2010 Free Software Foundation, Inc.
-This file is part of GDB, GAS, and the GNU binutils.
+ This file is part of GDB, GAS, and the GNU binutils.
-GDB, GAS, and the GNU binutils are free software; you can redistribute
-them and/or modify them under the terms of the GNU General Public
-License as published by the Free Software Foundation; either version
-1, or (at your option) any later version.
+ GDB, GAS, and the GNU binutils are free software; you can redistribute
+ them and/or modify them under the terms of the GNU General Public
+ License as published by the Free Software Foundation; either version 3,
+ or (at your option) any later version.
-GDB, GAS, and the GNU binutils are distributed in the hope that they
-will be useful, but WITHOUT ANY WARRANTY; without even the implied
-warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
-the GNU General Public License for more details.
+ GDB, GAS, and the GNU binutils are distributed in the hope that they
+ will be useful, but WITHOUT ANY WARRANTY; without even the implied
+ warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
+ the GNU General Public License for more details.
-You should have received a copy of the GNU General Public License
-along with this file; see the file COPYING. If not, write to the Free
-Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
+ You should have received a copy of the GNU General Public License
+ along with this file; see the file COPYING3. If not, write to the Free
+ Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
+ MA 02110-1301, USA. */
/* Common to all DSP32 instructions. */
#define BIT_MULTI_INS 0x0800
@@ -38,37 +39,37 @@ typedef struct
unsigned long opcode;
int bits_src1;
int mask_src1;
- int bits_src0;
+ int bits_src0;
int mask_src0;
- int bits_dst;
+ int bits_dst;
int mask_dst;
- int bits_h10;
+ int bits_h10;
int mask_h10;
- int bits_h00;
+ int bits_h00;
int mask_h00;
- int bits_op0;
+ int bits_op0;
int mask_op0;
- int bits_w0;
+ int bits_w0;
int mask_w0;
- int bits_h11;
+ int bits_h11;
int mask_h11;
- int bits_h01;
+ int bits_h01;
int mask_h01;
- int bits_op1;
+ int bits_op1;
int mask_op1;
- int bits_w1;
+ int bits_w1;
int mask_w1;
- int bits_P;
+ int bits_P;
int mask_P;
- int bits_MM;
+ int bits_MM;
int mask_MM;
- int bits_mmod;
+ int bits_mmod;
int mask_mmod;
- int bits_code2;
+ int bits_code2;
int mask_code2;
- int bits_M;
+ int bits_M;
int mask_M;
- int bits_code;
+ int bits_code;
int mask_code;
} DSP32Mac;
@@ -97,7 +98,7 @@ typedef struct
#define DSP32Mac_w1_mask 0x1
#define DSP32Mac_p_bits 19
#define DSP32Mac_p_mask 0x1
-#define DSP32Mac_MM_bits 20
+#define DSP32Mac_MM_bits 20
#define DSP32Mac_MM_mask 0x1
#define DSP32Mac_mmod_bits 21
#define DSP32Mac_mmod_mask 0xf
@@ -203,11 +204,11 @@ typedef struct
#define DSP32Alu_opcode 0xc4000000
#define DSP32Alu_src1_bits 0
#define DSP32Alu_src1_mask 0x7
-#define DSP32Alu_src0_bits 3
+#define DSP32Alu_src0_bits 3
#define DSP32Alu_src0_mask 0x7
#define DSP32Alu_dst1_bits 6
#define DSP32Alu_dst1_mask 0x7
-#define DSP32Alu_dst0_bits 9
+#define DSP32Alu_dst0_bits 9
#define DSP32Alu_dst0_mask 0x7
#define DSP32Alu_x_bits 12
#define DSP32Alu_x_mask 0x1
@@ -371,7 +372,7 @@ typedef struct
#define DSP32ShiftImm_code2_mask 0xf
#define DSP32ShiftImm_M_bits 27
#define DSP32ShiftImm_M_mask 0x1
-#define DSP32ShiftImm_code_bits 28
+#define DSP32ShiftImm_code_bits 28
#define DSP32ShiftImm_code_mask 0xf
#define init_DSP32ShiftImm \
@@ -939,7 +940,7 @@ typedef struct
/* PseudoDbg_assert
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-| 1 | 1 | 1 | 1 | 0 | - | - | - | - | - |.dbgop.....|.regtest...|
+| 1 | 1 | 1 | 1 | 0 | - | - | - | dbgop |.grp.......|.regtest...|
|.expected......................................................|
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
*/
@@ -951,6 +952,8 @@ typedef struct
int mask_expected;
int bits_regtest;
int mask_regtest;
+ int bits_grp;
+ int mask_grp;
int bits_dbgop;
int mask_dbgop;
int bits_dontcare;
@@ -964,10 +967,12 @@ typedef struct
#define PseudoDbg_Assert_expected_mask 0xffff
#define PseudoDbg_Assert_regtest_bits 16
#define PseudoDbg_Assert_regtest_mask 0x7
-#define PseudoDbg_Assert_dbgop_bits 19
-#define PseudoDbg_Assert_dbgop_mask 0x7
-#define PseudoDbg_Assert_dontcare_bits 22
-#define PseudoDbg_Assert_dontcare_mask 0x1f
+#define PseudoDbg_Assert_grp_bits 19
+#define PseudoDbg_Assert_grp_mask 0x7
+#define PseudoDbg_Assert_dbgop_bits 22
+#define PseudoDbg_Assert_dbgop_mask 0x3
+#define PseudoDbg_Assert_dontcare_bits 24
+#define PseudoDbg_Assert_dontcare_mask 0x7
#define PseudoDbg_Assert_code_bits 27
#define PseudoDbg_Assert_code_mask 0x1f
@@ -976,11 +981,40 @@ typedef struct
PseudoDbg_Assert_opcode, \
PseudoDbg_Assert_expected_bits, PseudoDbg_Assert_expected_mask, \
PseudoDbg_Assert_regtest_bits, PseudoDbg_Assert_regtest_mask, \
+ PseudoDbg_Assert_grp_bits, PseudoDbg_Assert_grp_mask, \
PseudoDbg_Assert_dbgop_bits, PseudoDbg_Assert_dbgop_mask, \
PseudoDbg_Assert_dontcare_bits, PseudoDbg_Assert_dontcare_mask, \
PseudoDbg_Assert_code_bits, PseudoDbg_Assert_code_mask \
};
+/* pseudoChr
++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+| 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |.ch............................|
++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+*/
+
+typedef struct
+{
+ unsigned short opcode;
+ int bits_ch;
+ int mask_ch;
+ int bits_code;
+ int mask_code;
+} PseudoChr;
+
+#define PseudoChr_opcode 0xf900
+#define PseudoChr_ch_bits 0
+#define PseudoChr_ch_mask 0xff
+#define PseudoChr_code_bits 8
+#define PseudoChr_code_mask 0xff
+
+#define init_PseudoChr \
+{ \
+ PseudoChr_opcode, \
+ PseudoChr_ch_bits, PseudoChr_ch_mask, \
+ PseudoChr_code_bits, PseudoChr_code_mask \
+};
+
/* CaCTRL
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |.a.|.op....|.reg.......|
@@ -1115,9 +1149,9 @@ typedef struct
typedef struct
{
unsigned long opcode;
- int bits_framesize;
+ int bits_framesize;
int mask_framesize;
- int bits_R;
+ int bits_R;
int mask_R;
int bits_code;
int mask_code;
@@ -1150,18 +1184,18 @@ typedef struct
{
unsigned long opcode;
int bits_eoffset;
- int mask_eoffset;
- int bits_dontcare;
+ int mask_eoffset;
+ int bits_dontcare;
int mask_dontcare;
- int bits_reg;
+ int bits_reg;
int mask_reg;
- int bits_soffset;
+ int bits_soffset;
int mask_soffset;
- int bits_c;
+ int bits_c;
int mask_c;
- int bits_rop;
+ int bits_rop;
int mask_rop;
- int bits_code;
+ int bits_code;
int mask_code;
} LoopSetup;
@@ -1205,17 +1239,17 @@ typedef struct
unsigned long opcode;
int bits_hword;
int mask_hword;
- int bits_reg;
+ int bits_reg;
int mask_reg;
- int bits_grp;
+ int bits_grp;
int mask_grp;
- int bits_S;
+ int bits_S;
int mask_S;
- int bits_H;
+ int bits_H;
int mask_H;
- int bits_Z;
+ int bits_Z;
int mask_Z;
- int bits_code;
+ int bits_code;
int mask_code;
} LDIMMhalf;
@@ -1259,9 +1293,9 @@ typedef struct
unsigned short opcode;
int bits_reg;
int mask_reg;
- int bits_op;
+ int bits_op;
int mask_op;
- int bits_code;
+ int bits_code;
int mask_code;
} CC2dreg;
@@ -1293,11 +1327,11 @@ typedef struct
unsigned short opcode;
int bits_dst;
int mask_dst;
- int bits_src;
+ int bits_src;
int mask_src;
- int bits_opc;
+ int bits_opc;
int mask_opc;
- int bits_code;
+ int bits_code;
int mask_code;
} PTR2op;
@@ -1308,7 +1342,7 @@ typedef struct
#define PTR2op_src_mask 0x7
#define PTR2op_opc_bits 6
#define PTR2op_opc_mask 0x7
-#define PTR2op_code_bits 9
+#define PTR2op_code_bits 9
#define PTR2op_code_mask 0x7f
#define init_PTR2op \
@@ -1332,13 +1366,13 @@ typedef struct
unsigned short opcode;
int bits_src0;
int mask_src0;
- int bits_src1;
+ int bits_src1;
int mask_src1;
- int bits_dst;
+ int bits_dst;
int mask_dst;
- int bits_opc;
+ int bits_opc;
int mask_opc;
- int bits_code;
+ int bits_code;
int mask_code;
} COMP3op;
@@ -1375,15 +1409,15 @@ typedef struct
unsigned short opcode;
int bits_src;
int mask_src;
- int bits_dst;
+ int bits_dst;
int mask_dst;
- int bits_s;
+ int bits_s;
int mask_s;
- int bits_d;
+ int bits_d;
int mask_d;
- int bits_T;
+ int bits_T;
int mask_T;
- int bits_code;
+ int bits_code;
int mask_code;
} CCmv;
@@ -1394,7 +1428,7 @@ typedef struct
#define CCmv_dst_mask 0x7
#define CCmv_s_bits 6
#define CCmv_s_mask 0x1
-#define CCmv_d_bits 7
+#define CCmv_d_bits 7
#define CCmv_d_mask 0x1
#define CCmv_T_bits 8
#define CCmv_T_mask 0x1
@@ -1424,15 +1458,15 @@ typedef struct
unsigned short opcode;
int bits_x;
int mask_x;
- int bits_y;
+ int bits_y;
int mask_y;
- int bits_G;
+ int bits_G;
int mask_G;
- int bits_opc;
+ int bits_opc;
int mask_opc;
- int bits_I;
+ int bits_I;
int mask_I;
- int bits_code;
+ int bits_code;
int mask_code;
} CCflag;
@@ -1473,11 +1507,11 @@ typedef struct
unsigned short opcode;
int bits_cbit;
int mask_cbit;
- int bits_op;
+ int bits_op;
int mask_op;
- int bits_D;
+ int bits_D;
int mask_D;
- int bits_code;
+ int bits_code;
int mask_code;
} CC2stat;
@@ -1512,13 +1546,13 @@ typedef struct
unsigned short opcode;
int bits_src;
int mask_src;
- int bits_dst;
+ int bits_dst;
int mask_dst;
- int bits_gs;
+ int bits_gs;
int mask_gs;
- int bits_gd;
+ int bits_gd;
int mask_gd;
- int bits_code;
+ int bits_code;
int mask_code;
} RegMv;
@@ -1556,11 +1590,11 @@ typedef struct
unsigned short opcode;
int bits_dst;
int mask_dst;
- int bits_src;
+ int bits_src;
int mask_src;
- int bits_op;
+ int bits_op;
int mask_op;
- int bits_code;
+ int bits_code;
int mask_code;
} COMPI2opD;
@@ -1622,15 +1656,15 @@ typedef struct
unsigned short opcode;
int bits_i;
int mask_i;
- int bits_m;
+ int bits_m;
int mask_m;
- int bits_op;
+ int bits_op;
int mask_op;
- int bits_code2;
+ int bits_code2;
int mask_code2;
- int bits_br;
+ int bits_br;
int mask_br;
- int bits_code;
+ int bits_code;
int mask_code;
} DagMODim;
diff --git a/external/gpl3/binutils/dist/include/opcode/cgen.h b/external/gpl3/binutils/dist/include/opcode/cgen.h
index e8fd5d3d9f7..b7e82d4dd93 100644
--- a/external/gpl3/binutils/dist/include/opcode/cgen.h
+++ b/external/gpl3/binutils/dist/include/opcode/cgen.h
@@ -1,29 +1,33 @@
/* Header file for targets using CGEN: Cpu tools GENerator.
-Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005
-Free Software Foundation, Inc.
+ Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2009, 2010
+ Free Software Foundation, Inc.
-This file is part of GDB, the GNU debugger, and the GNU Binutils.
+ This file is part of GDB, the GNU debugger, and the GNU Binutils.
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
+ You should have received a copy of the GNU General Public License along
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
-#ifndef CGEN_H
-#define CGEN_H
+#ifndef OPCODE_CGEN_H
+#define OPCODE_CGEN_H
#include "symcat.h"
-#include "cgen-bitset.h"
+#include "cgen/bitset.h"
+
+/* ??? IWBN to replace bfd in the name. */
+#include "bfd_stdint.h"
+
/* ??? This file requires bfd.h but only to get bfd_vma.
Seems like an awful lot to require just to get such a fundamental type.
Perhaps the definition of bfd_vma can be moved outside of bfd.h.
@@ -65,6 +69,9 @@ with this program; if not, write to the Free Software Foundation, Inc.,
when an array of characters the value is in target byte order. */
typedef unsigned int CGEN_INSN_INT;
+typedef int64_t CGEN_INSN_LGSINT; /* large/long SINT */
+typedef uint64_t CGEN_INSN_LGUINT; /* large/long UINT */
+
#if CGEN_INT_INSN_P
typedef CGEN_INSN_INT CGEN_INSN_BYTES;
typedef CGEN_INSN_INT *CGEN_INSN_BYTES_PTR;
@@ -122,7 +129,7 @@ typedef union
typedef struct
{
/* Boolean attributes. */
- unsigned int bool;
+ unsigned int bool_;
/* Non-boolean integer attributes. */
CGEN_ATTR_VALUE_TYPE nonbool[1];
} CGEN_ATTR;
@@ -133,12 +140,12 @@ typedef struct
in one host int). */
#define CGEN_ATTR_TYPE(n) \
-struct { unsigned int bool; \
+struct { unsigned int bool_; \
CGEN_ATTR_VALUE_TYPE nonbool[(n) ? (n) : 1]; }
/* Return the boolean attributes. */
-#define CGEN_ATTR_BOOLS(a) ((a)->bool)
+#define CGEN_ATTR_BOOLS(a) ((a)->bool_)
/* Non-boolean attribute numbers are offset by this much. */
@@ -975,7 +982,7 @@ typedef CGEN_ATTR_TYPE (CGEN_INSN_NBOOL_ATTRS) CGEN_INSN_ATTR_TYPE;
typedef enum cgen_insn_attr {
CGEN_INSN_ALIAS = 0
} CGEN_INSN_ATTR;
-#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) ((attrs)->bool & (1 << CGEN_INSN_ALIAS))
+#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) ((attrs)->bool_ & (1 << CGEN_INSN_ALIAS))
#endif
/* This struct defines each entry in the instruction table. */
@@ -1470,4 +1477,4 @@ extern void cgen_clear_signed_overflow_ok (CGEN_CPU_DESC);
/* Will an error message be generated if a signed field in an instruction overflows ? */
extern unsigned int cgen_signed_overflow_ok_p (CGEN_CPU_DESC);
-#endif /* CGEN_H */
+#endif /* OPCODE_CGEN_H */
diff --git a/external/gpl3/binutils/dist/include/opcode/convex.h b/external/gpl3/binutils/dist/include/opcode/convex.h
index 7843dce8b5b..4643f5e0697 100644
--- a/external/gpl3/binutils/dist/include/opcode/convex.h
+++ b/external/gpl3/binutils/dist/include/opcode/convex.h
@@ -1,21 +1,22 @@
/* Information for instruction disassembly on the Convex.
- Copyright 1989, 1993, 2002 Free Software Foundation, Inc.
+ Copyright 1989, 1993, 2002, 2010 Free Software Foundation, Inc.
-This file is part of GDB.
+ This file is part of GDB.
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software
-Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+ MA 02110-1301, USA. */
#define xxx 0
#define rrr 1
diff --git a/external/gpl3/binutils/dist/include/opcode/cr16.h b/external/gpl3/binutils/dist/include/opcode/cr16.h
index c99c51a6e5a..2d322882e4c 100644
--- a/external/gpl3/binutils/dist/include/opcode/cr16.h
+++ b/external/gpl3/binutils/dist/include/opcode/cr16.h
@@ -1,12 +1,12 @@
/* cr16.h -- Header file for CR16 opcode and register tables.
- Copyright 2007, 2008 Free Software Foundation, Inc.
+ Copyright 2007, 2008, 2010 Free Software Foundation, Inc.
Contributed by M R Swami Reddy
This file is part of GAS, GDB and the GNU binutils.
GAS, GDB, and GNU binutils is free software; you can redistribute it
and/or modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2, or (at your
+ published by the Free Software Foundation; either version 3, or (at your
option) any later version.
GAS, GDB, and GNU binutils are distributed in the hope that they will be
diff --git a/external/gpl3/binutils/dist/include/opcode/cris.h b/external/gpl3/binutils/dist/include/opcode/cris.h
index 00ddde010fb..e57a8825c0c 100644
--- a/external/gpl3/binutils/dist/include/opcode/cris.h
+++ b/external/gpl3/binutils/dist/include/opcode/cris.h
@@ -1,24 +1,25 @@
/* cris.h -- Header file for CRIS opcode and register tables.
- Copyright (C) 2000, 2001, 2004 Free Software Foundation, Inc.
+ Copyright (C) 2000, 2001, 2004, 2010 Free Software Foundation, Inc.
Contributed by Axis Communications AB, Lund, Sweden.
Originally written for GAS 1.38.1 by Mikael Asker.
Updated, BFDized and GNUified by Hans-Peter Nilsson.
-This file is part of GAS, GDB and the GNU binutils.
+ This file is part of GAS, GDB and the GNU binutils.
-GAS, GDB, and GNU binutils is free software; you can redistribute it
-and/or modify it under the terms of the GNU General Public License as
-published by the Free Software Foundation; either version 2, or (at your
-option) any later version.
+ GAS, GDB, and GNU binutils is free software; you can redistribute it
+ and/or modify it under the terms of the GNU General Public License as
+ published by the Free Software Foundation; either version 3, or (at your
+ option) any later version.
-GAS, GDB, and GNU binutils are distributed in the hope that they will be
-useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
+ GAS, GDB, and GNU binutils are distributed in the hope that they will be
+ useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software
-Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+ MA 02110-1301, USA. */
#ifndef __CRIS_H_INCLUDED_
#define __CRIS_H_INCLUDED_
diff --git a/external/gpl3/binutils/dist/include/opcode/crx.h b/external/gpl3/binutils/dist/include/opcode/crx.h
index 66def6b39b9..5c484bf26bc 100644
--- a/external/gpl3/binutils/dist/include/opcode/crx.h
+++ b/external/gpl3/binutils/dist/include/opcode/crx.h
@@ -1,5 +1,5 @@
/* crx.h -- Header file for CRX opcode and register tables.
- Copyright 2004 Free Software Foundation, Inc.
+ Copyright 2004, 2010 Free Software Foundation, Inc.
Contributed by Tomer Levi, NSC, Israel.
Originally written for GAS 2.12 by Tomer Levi, NSC, Israel.
Updates, BFDizing, GNUifying and ELF support by Tomer Levi.
@@ -8,7 +8,7 @@
GAS, GDB, and GNU binutils is free software; you can redistribute it
and/or modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2, or (at your
+ published by the Free Software Foundation; either version 3, or (at your
option) any later version.
GAS, GDB, and GNU binutils are distributed in the hope that they will be
@@ -18,7 +18,8 @@
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
- Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
+ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+ MA 02110-1301, USA. */
#ifndef _CRX_H_
#define _CRX_H_
diff --git a/external/gpl3/binutils/dist/include/opcode/d10v.h b/external/gpl3/binutils/dist/include/opcode/d10v.h
index c96ddebf18b..d0e115fab20 100644
--- a/external/gpl3/binutils/dist/include/opcode/d10v.h
+++ b/external/gpl3/binutils/dist/include/opcode/d10v.h
@@ -1,23 +1,24 @@
/* d10v.h -- Header file for D10V opcode table
- Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2003
+ Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2003, 2010
Free Software Foundation, Inc.
Written by Martin Hunt (hunt@cygnus.com), Cygnus Support
-This file is part of GDB, GAS, and the GNU binutils.
+ This file is part of GDB, GAS, and the GNU binutils.
-GDB, GAS, and the GNU binutils are free software; you can redistribute
-them and/or modify them under the terms of the GNU General Public
-License as published by the Free Software Foundation; either version
-1, or (at your option) any later version.
+ GDB, GAS, and the GNU binutils are free software; you can redistribute
+ them and/or modify them under the terms of the GNU General Public
+ License as published by the Free Software Foundation; either version 3,
+ or (at your option) any later version.
-GDB, GAS, and the GNU binutils are distributed in the hope that they
-will be useful, but WITHOUT ANY WARRANTY; without even the implied
-warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
-the GNU General Public License for more details.
+ GDB, GAS, and the GNU binutils are distributed in the hope that they
+ will be useful, but WITHOUT ANY WARRANTY; without even the implied
+ warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
+ the GNU General Public License for more details.
-You should have received a copy of the GNU General Public License
-along with this file; see the file COPYING. If not, write to the Free
-Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
+ You should have received a copy of the GNU General Public License
+ along with this file; see the file COPYING3. If not, write to the Free
+ Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
+ MA 02110-1301, USA. */
#ifndef D10V_H
#define D10V_H
diff --git a/external/gpl3/binutils/dist/include/opcode/d30v.h b/external/gpl3/binutils/dist/include/opcode/d30v.h
index 7aa5bb6feff..62c041da967 100644
--- a/external/gpl3/binutils/dist/include/opcode/d30v.h
+++ b/external/gpl3/binutils/dist/include/opcode/d30v.h
@@ -1,22 +1,24 @@
/* d30v.h -- Header file for D30V opcode table
- Copyright 1997, 1998, 1999, 2000, 2001, 2003 Free Software Foundation, Inc.
+ Copyright 1997, 1998, 1999, 2000, 2001, 2003, 2010
+ Free Software Foundation, Inc.
Written by Martin Hunt (hunt@cygnus.com), Cygnus Solutions
-This file is part of GDB, GAS, and the GNU binutils.
+ This file is part of GDB, GAS, and the GNU binutils.
-GDB, GAS, and the GNU binutils are free software; you can redistribute
-them and/or modify them under the terms of the GNU General Public
-License as published by the Free Software Foundation; either version
-1, or (at your option) any later version.
+ GDB, GAS, and the GNU binutils are free software; you can redistribute
+ them and/or modify them under the terms of the GNU General Public
+ License as published by the Free Software Foundation; either version 3,
+ or (at your option) any later version.
-GDB, GAS, and the GNU binutils are distributed in the hope that they
-will be useful, but WITHOUT ANY WARRANTY; without even the implied
-warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
-the GNU General Public License for more details.
+ GDB, GAS, and the GNU binutils are distributed in the hope that they
+ will be useful, but WITHOUT ANY WARRANTY; without even the implied
+ warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
+ the GNU General Public License for more details.
-You should have received a copy of the GNU General Public License
-along with this file; see the file COPYING. If not, write to the Free
-Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
+ You should have received a copy of the GNU General Public License
+ along with this file; see the file COPYING3. If not, write to the Free
+ Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
+ MA 02110-1301, USA. */
#ifndef D30V_H
#define D30V_H
diff --git a/external/gpl3/binutils/dist/include/opcode/dlx.h b/external/gpl3/binutils/dist/include/opcode/dlx.h
index 278e936cdf9..54dadd07277 100644
--- a/external/gpl3/binutils/dist/include/opcode/dlx.h
+++ b/external/gpl3/binutils/dist/include/opcode/dlx.h
@@ -1,11 +1,11 @@
/* Table of opcodes for the DLX microprocess.
- Copyright 2002 Free Software Foundation, Inc.
+ Copyright 2002, 2010 Free Software Foundation, Inc.
This file is part of GDB and GAS.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
+ the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
@@ -15,7 +15,8 @@
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
- Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+ MA 02110-1301, USA.
Initially created by Kuang Hwa Lin, 2002. */
diff --git a/external/gpl3/binutils/dist/include/opcode/h8300.h b/external/gpl3/binutils/dist/include/opcode/h8300.h
index 32e43c7a843..81b1c089410 100644
--- a/external/gpl3/binutils/dist/include/opcode/h8300.h
+++ b/external/gpl3/binutils/dist/include/opcode/h8300.h
@@ -1,6 +1,6 @@
/* Opcode table for the H8/300
Copyright 1991, 1992, 1993, 1994, 1996, 1997, 1998, 2000, 2001, 2002,
- 2003, 2004, 2008
+ 2003, 2004, 2005, 2008, 2009, 2010
Free Software Foundation, Inc.
Written by Steve Chamberlain <sac@cygnus.com>.
@@ -8,7 +8,7 @@
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
+ the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
@@ -1565,62 +1565,62 @@ struct h8_opcode h8_opcodes[] =
MOVFROM_AD (O (O_MOV, SL), PREFIX_0108, "mov.l", ABS32SRC, FROM_ABS32, ABS32LIST),
#define DO_MOVA1(TYPE, OP0, OP1) \
- {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0x8, B30 | R3_32, DISP16LIST, E}}}, \
- {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0x9, B30 | R3_32, DISP16LIST, E}}}, \
- {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xA, B30 | R3_32, DISP16LIST, E}}}, \
- {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xB, B30 | R3_32, DISP16LIST, E}}}, \
- {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xC, B30 | R3_32, DISP16LIST, E}}}, \
- {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xD, B30 | R3_32, DISP16LIST, E}}}, \
+ {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0x8, B30 | R3_32, MEMRELAX | DISP16LIST, E}}}, \
+ {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0x9, B30 | R3_32, MEMRELAX | DISP16LIST, E}}}, \
+ {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xA, B30 | R3_32, MEMRELAX | DISP16LIST, E}}}, \
+ {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xB, B30 | R3_32, MEMRELAX | DISP16LIST, E}}}, \
+ {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xC, B30 | R3_32, MEMRELAX | DISP16LIST, E}}}, \
+ {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xD, B30 | R3_32, MEMRELAX | DISP16LIST, E}}}, \
\
- {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0x8, B31 | R3_32, DISP32LIST, E}}}, \
- {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0x9, B31 | R3_32, DISP32LIST, E}}}, \
- {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xA, B31 | R3_32, DISP32LIST, E}}}, \
- {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xB, B31 | R3_32, DISP32LIST, E}}}, \
- {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xC, B31 | R3_32, DISP32LIST, E}}}, \
- {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xD, B31 | R3_32, DISP32LIST, E}}}
+ {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0x8, B31 | R3_32, MEMRELAX | DISP32LIST, E}}}, \
+ {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0x9, B31 | R3_32, MEMRELAX | DISP32LIST, E}}}, \
+ {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xA, B31 | R3_32, MEMRELAX | DISP32LIST, E}}}, \
+ {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xB, B31 | R3_32, MEMRELAX | DISP32LIST, E}}}, \
+ {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xC, B31 | R3_32, MEMRELAX | DISP32LIST, E}}}, \
+ {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xD, B31 | R3_32, MEMRELAX | DISP32LIST, E}}}
#define DO_MOVA2(TYPE, OP0, OP1, OP2) \
- {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0x8, B30 | R3_32, OP2, DISP16LIST, E}}}, \
- {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0x9, B30 | R3_32, OP2, DISP16LIST, E}}}, \
- {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xA, B30 | R3_32, OP2, DISP16LIST, E}}}, \
- {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xB, B30 | R3_32, OP2, DISP16LIST, E}}}, \
- {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xC, B30 | R3_32, OP2, DISP16LIST, E}}}, \
- {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xD, B30 | R3_32, OP2, DISP16LIST, E}}}, \
+ {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0x8, B30 | R3_32, OP2, MEMRELAX | DISP16LIST, E}}}, \
+ {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0x9, B30 | R3_32, OP2, MEMRELAX | DISP16LIST, E}}}, \
+ {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xA, B30 | R3_32, OP2, MEMRELAX | DISP16LIST, E}}}, \
+ {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xB, B30 | R3_32, OP2, MEMRELAX | DISP16LIST, E}}}, \
+ {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xC, B30 | R3_32, OP2, MEMRELAX | DISP16LIST, E}}}, \
+ {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xD, B30 | R3_32, OP2, MEMRELAX | DISP16LIST, E}}}, \
\
- {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0x8, B31 | R3_32, OP2, DISP32LIST, E}}}, \
- {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0x9, B31 | R3_32, OP2, DISP32LIST, E}}}, \
- {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xA, B31 | R3_32, OP2, DISP32LIST, E}}}, \
- {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xB, B31 | R3_32, OP2, DISP32LIST, E}}}, \
- {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xC, B31 | R3_32, OP2, DISP32LIST, E}}}, \
- {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xD, B31 | R3_32, OP2, DISP32LIST, E}}}
-
- {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB16, E}}, {{0x7, 0xA, 0x8, B31 | DISPREG, DISP16LIST, E}}},
- {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW16, E}}, {{0x7, 0xA, 0x9, B31 | DISPREG, DISP16LIST, E}}},
- {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB16, E}}, {{0x7, 0xA, 0xA, B31 | DISPREG, DISP16LIST, E}}},
- {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW16, E}}, {{0x7, 0xA, 0xB, B31 | DISPREG, DISP16LIST, E}}},
- {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB16, E}}, {{0x7, 0xA, 0xC, B31 | DISPREG, DISP16LIST, E}}},
- {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW16, E}}, {{0x7, 0xA, 0xD, B31 | DISPREG, DISP16LIST, E}}},
-
- {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB32, E}}, {{0x7, 0xA, 0x8, B30 | DISPREG, DISP32LIST, E}}},
- {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW32, E}}, {{0x7, 0xA, 0x9, B30 | DISPREG, DISP32LIST, E}}},
- {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB32, E}}, {{0x7, 0xA, 0xA, B30 | DISPREG, DISP32LIST, E}}},
- {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW32, E}}, {{0x7, 0xA, 0xB, B30 | DISPREG, DISP32LIST, E}}},
- {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB32, E}}, {{0x7, 0xA, 0xC, B30 | DISPREG, DISP32LIST, E}}},
- {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW32, E}}, {{0x7, 0xA, 0xD, B30 | DISPREG, DISP32LIST, E}}},
-
- {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB16, RD8, R3_32}}, {{0x7, 0x8, RD8, 0x8, 0x7, 0xA, 0x8, B31 | R3_32, DISP16LIST, E}}},
- {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW16, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0x9, B31 | R3_32, DISP16LIST, E}}},
- {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB16, RD8, R3_32}}, {{0x7, 0x8, RD8, 0x8, 0x7, 0xA, 0xA, B31 | R3_32, DISP16LIST, E}}},
- {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW16, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0xB, B31 | R3_32, DISP16LIST, E}}},
- {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB16, RD8, R3_32}}, {{0x7, 0x8, RD8, 0x8, 0x7, 0xA, 0xC, B31 | R3_32, DISP16LIST, E}}},
- {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW16, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0xD, B31 | R3_32, DISP16LIST, E}}},
-
- {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB32, RD8, R3_32}}, {{0x7, 0x8, RD8, 0x8, 0x7, 0xA, 0x8, B30 | R3_32, DISP32LIST, E}}},
- {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW32, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0x9, B30 | R3_32, DISP32LIST, E}}},
- {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB32, RD8, R3_32}}, {{0x7, 0x8, RD8, 0x8, 0x7, 0xA, 0xA, B30 | R3_32, DISP32LIST, E}}},
- {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW32, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0xB, B30 | R3_32, DISP32LIST, E}}},
- {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB32, RD8, R3_32}}, {{0x7, 0x8, RD8, 0x8, 0x7, 0xA, 0xC, B30 | R3_32, DISP32LIST, E}}},
- {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW32, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0xD, B30 | R3_32, DISP32LIST, E}}},
+ {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0x8, B31 | R3_32, OP2, MEMRELAX | DISP32LIST, E}}}, \
+ {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0x9, B31 | R3_32, OP2, MEMRELAX | DISP32LIST, E}}}, \
+ {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xA, B31 | R3_32, OP2, MEMRELAX | DISP32LIST, E}}}, \
+ {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xB, B31 | R3_32, OP2, MEMRELAX | DISP32LIST, E}}}, \
+ {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xC, B31 | R3_32, OP2, MEMRELAX | DISP32LIST, E}}}, \
+ {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xD, B31 | R3_32, OP2, MEMRELAX | DISP32LIST, E}}}
+
+ {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB16, E}}, {{0x7, 0xA, 0x8, B31 | DISPREG, MEMRELAX | DISP16LIST, E}}},
+ {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW16, E}}, {{0x7, 0xA, 0x9, B31 | DISPREG, MEMRELAX | DISP16LIST, E}}},
+ {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB16, E}}, {{0x7, 0xA, 0xA, B31 | DISPREG, MEMRELAX | DISP16LIST, E}}},
+ {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW16, E}}, {{0x7, 0xA, 0xB, B31 | DISPREG, MEMRELAX | DISP16LIST, E}}},
+ {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB16, E}}, {{0x7, 0xA, 0xC, B31 | DISPREG, MEMRELAX | DISP16LIST, E}}},
+ {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW16, E}}, {{0x7, 0xA, 0xD, B31 | DISPREG, MEMRELAX | DISP16LIST, E}}},
+
+ {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB32, E}}, {{0x7, 0xA, 0x8, B30 | DISPREG, MEMRELAX | DISP32LIST, E}}},
+ {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW32, E}}, {{0x7, 0xA, 0x9, B30 | DISPREG, MEMRELAX | DISP32LIST, E}}},
+ {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB32, E}}, {{0x7, 0xA, 0xA, B30 | DISPREG, MEMRELAX | DISP32LIST, E}}},
+ {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW32, E}}, {{0x7, 0xA, 0xB, B30 | DISPREG, MEMRELAX | DISP32LIST, E}}},
+ {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB32, E}}, {{0x7, 0xA, 0xC, B30 | DISPREG, MEMRELAX | DISP32LIST, E}}},
+ {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW32, E}}, {{0x7, 0xA, 0xD, B30 | DISPREG, MEMRELAX | DISP32LIST, E}}},
+
+ {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB16, RD8, R3_32}}, {{0x7, 0x8, RD8, 0x8, 0x7, 0xA, 0x8, B31 | R3_32, MEMRELAX | DISP16LIST, E}}},
+ {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW16, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0x9, B31 | R3_32, MEMRELAX | DISP16LIST, E}}},
+ {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB16, RD8, R3_32}}, {{0x7, 0x8, RD8, 0x8, 0x7, 0xA, 0xA, B31 | R3_32, MEMRELAX | DISP16LIST, E}}},
+ {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW16, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0xB, B31 | R3_32, MEMRELAX | DISP16LIST, E}}},
+ {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB16, RD8, R3_32}}, {{0x7, 0x8, RD8, 0x8, 0x7, 0xA, 0xC, B31 | R3_32, MEMRELAX | DISP16LIST, E}}},
+ {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW16, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0xD, B31 | R3_32, MEMRELAX | DISP16LIST, E}}},
+
+ {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB32, RD8, R3_32}}, {{0x7, 0x8, RD8, 0x8, 0x7, 0xA, 0x8, B30 | R3_32, MEMRELAX | DISP32LIST, E}}},
+ {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW32, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0x9, B30 | R3_32, MEMRELAX | DISP32LIST, E}}},
+ {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB32, RD8, R3_32}}, {{0x7, 0x8, RD8, 0x8, 0x7, 0xA, 0xA, B30 | R3_32, MEMRELAX | DISP32LIST, E}}},
+ {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW32, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0xB, B30 | R3_32, MEMRELAX | DISP32LIST, E}}},
+ {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB32, RD8, R3_32}}, {{0x7, 0x8, RD8, 0x8, 0x7, 0xA, 0xC, B30 | R3_32, MEMRELAX | DISP32LIST, E}}},
+ {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW32, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0xD, B30 | R3_32, MEMRELAX | DISP32LIST, E}}},
DO_MOVA1 (RDIND, 0x0, B30 | RDIND),
DO_MOVA1 (RDPOSTINC, 0x8, B30 | RDPOSTINC),
@@ -1628,16 +1628,16 @@ struct h8_opcode h8_opcodes[] =
DO_MOVA1 (RDPREINC, 0x9, B30 | RDPREINC),
DO_MOVA1 (RDPREDEC, 0xB, B30 | RDPREDEC),
DO_MOVA1 (DISP2DST, B30 | B20 | DISP2DST, B30 | DSTDISPREG),
- DO_MOVA2 (DISP16DST, 0xC, B30 | DSTDISPREG, DSTDISP16LIST),
- DO_MOVA2 (DISP32DST, 0xC, B31 | DSTDISPREG, DSTDISP32LIST),
- DO_MOVA2 (INDEXB16D, 0xD, B30 | DSTDISPREG, DSTDISP16LIST),
- DO_MOVA2 (INDEXW16D, 0xE, B30 | DSTDISPREG, DSTDISP16LIST),
- DO_MOVA2 (INDEXL16D, 0xF, B30 | DSTDISPREG, DSTDISP16LIST),
- DO_MOVA2 (INDEXB32D, 0xD, B31 | DSTDISPREG, DSTDISP32LIST),
- DO_MOVA2 (INDEXW32D, 0xE, B31 | DSTDISPREG, DSTDISP32LIST),
- DO_MOVA2 (INDEXL32D, 0xF, B31 | DSTDISPREG, DSTDISP32LIST),
- DO_MOVA2 (ABS16DST, 0x4, 0x0, DSTABS16LIST),
- DO_MOVA2 (ABS32DST, 0x4, 0x8, DSTABS32LIST),
+ DO_MOVA2 (DISP16DST, 0xC, B30 | DSTDISPREG, MEMRELAX | DSTDISP16LIST),
+ DO_MOVA2 (DISP32DST, 0xC, B31 | DSTDISPREG, MEMRELAX | DSTDISP32LIST),
+ DO_MOVA2 (INDEXB16D, 0xD, B30 | DSTDISPREG, MEMRELAX | DSTDISP16LIST),
+ DO_MOVA2 (INDEXW16D, 0xE, B30 | DSTDISPREG, MEMRELAX | DSTDISP16LIST),
+ DO_MOVA2 (INDEXL16D, 0xF, B30 | DSTDISPREG, MEMRELAX | DSTDISP16LIST),
+ DO_MOVA2 (INDEXB32D, 0xD, B31 | DSTDISPREG, MEMRELAX | DSTDISP32LIST),
+ DO_MOVA2 (INDEXW32D, 0xE, B31 | DSTDISPREG, MEMRELAX | DSTDISP32LIST),
+ DO_MOVA2 (INDEXL32D, 0xF, B31 | DSTDISPREG, MEMRELAX | DSTDISP32LIST),
+ DO_MOVA2 (ABS16DST, 0x4, 0x0, MEMRELAX | DSTABS16LIST),
+ DO_MOVA2 (ABS32DST, 0x4, 0x8, MEMRELAX | DSTABS32LIST),
{O (O_MOV, SB), AV_H8, 10, "movfpe", {{ABS16SRC, RD8, E}}, {{0x6, 0xA, 0x4, RD8, ABS16SRC, DATA3, E}}},
{O (O_MOV, SB), AV_H8, 10, "movtpe", {{RS8, ABS16DST, E}}, {{0x6, 0xA, 0xC, RS8, ABS16DST, DATA3, E}}},
diff --git a/external/gpl3/binutils/dist/include/opcode/i370.h b/external/gpl3/binutils/dist/include/opcode/i370.h
index bdbb2f42160..e3b7166d292 100644
--- a/external/gpl3/binutils/dist/include/opcode/i370.h
+++ b/external/gpl3/binutils/dist/include/opcode/i370.h
@@ -1,23 +1,25 @@
/* i370.h -- Header file for S/390 opcode table
- Copyright 1994, 1995, 1998, 1999, 2000, 2003 Free Software Foundation, Inc.
+ Copyright 1994, 1995, 1998, 1999, 2000, 2003, 2010
+ Free Software Foundation, Inc.
PowerPC version written by Ian Lance Taylor, Cygnus Support
Rewritten for i370 ESA/390 support, Linas Vepstas <linas@linas.org>
-This file is part of GDB, GAS, and the GNU binutils.
+ This file is part of GDB, GAS, and the GNU binutils.
-GDB, GAS, and the GNU binutils are free software; you can redistribute
-them and/or modify them under the terms of the GNU General Public
-License as published by the Free Software Foundation; either version
-1, or (at your option) any later version.
+ GDB, GAS, and the GNU binutils are free software; you can redistribute
+ them and/or modify them under the terms of the GNU General Public
+ License as published by the Free Software Foundation; either version 3,
+ or (at your option) any later version.
-GDB, GAS, and the GNU binutils are distributed in the hope that they
-will be useful, but WITHOUT ANY WARRANTY; without even the implied
-warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
-the GNU General Public License for more details.
+ GDB, GAS, and the GNU binutils are distributed in the hope that they
+ will be useful, but WITHOUT ANY WARRANTY; without even the implied
+ warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
+ the GNU General Public License for more details.
-You should have received a copy of the GNU General Public License
-along with this file; see the file COPYING. If not, write to the Free
-Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
+ You should have received a copy of the GNU General Public License
+ along with this file; see the file COPYING3. If not, write to the Free
+ Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
+ MA 02110-1301, USA. */
#ifndef I370_H
#define I370_H
diff --git a/external/gpl3/binutils/dist/include/opcode/i386.h b/external/gpl3/binutils/dist/include/opcode/i386.h
index f59eeeaff38..b635334e41d 100644
--- a/external/gpl3/binutils/dist/include/opcode/i386.h
+++ b/external/gpl3/binutils/dist/include/opcode/i386.h
@@ -1,13 +1,13 @@
/* opcode/i386.h -- Intel 80386 opcode macros
Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
- 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
+ 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
Free Software Foundation, Inc.
This file is part of GAS, the GNU Assembler, and GDB, the GNU Debugger.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
+ the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
@@ -17,7 +17,8 @@
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
- Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
+ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+ MA 02110-1301, USA. */
/* The SystemV/386 SVR3.2 assembler, and probably all AT&T derived
ix86 Unix assemblers, generate floating point instructions with
@@ -35,6 +36,9 @@
The affected opcode map is dceX, dcfX, deeX, defX. */
+#ifndef OPCODE_I386_H
+#define OPCODE_I386_H
+
#ifndef SYSV386_COMPAT
/* Set non-zero for broken, compatible instructions. Set to zero for
non-broken opcodes at your peril. gcc generates SystemV/386
@@ -56,6 +60,11 @@
/* The opcode for the fwait instruction, which disassembler treats as a
prefix when it can. */
#define FWAIT_OPCODE 0x9b
+
+/* Instruction prefixes.
+ NOTE: For certain SSE* instructions, 0x66,0xf2,0xf3 are treated as
+ part of the opcode. Other prefixes may still appear between them
+ and the 0x0f part of the opcode. */
#define ADDR_PREFIX_OPCODE 0x67
#define DATA_PREFIX_OPCODE 0x66
#define LOCK_PREFIX_OPCODE 0xf0
@@ -72,8 +81,14 @@
#define NOP_OPCODE (char) 0x90
/* register numbers */
-#define EBP_REG_NUM 5
+#define EAX_REG_NUM 0
+#define ECX_REG_NUM 1
+#define EDX_REG_NUM 2
+#define EBX_REG_NUM 3
#define ESP_REG_NUM 4
+#define EBP_REG_NUM 5
+#define ESI_REG_NUM 6
+#define EDI_REG_NUM 7
/* modrm_byte.regmem for twobyte escape */
#define ESCAPE_TO_TWO_BYTE_ADDRESSING ESP_REG_NUM
@@ -87,9 +102,22 @@
#define REGMEM_FIELD_HAS_REG 0x3/* always = 0x3 */
#define REGMEM_FIELD_HAS_MEM (~REGMEM_FIELD_HAS_REG)
+/* Extract fields from the mod/rm byte. */
+#define MODRM_MOD_FIELD(modrm) (((modrm) >> 6) & 3)
+#define MODRM_REG_FIELD(modrm) (((modrm) >> 3) & 7)
+#define MODRM_RM_FIELD(modrm) (((modrm) >> 0) & 7)
+
+/* Extract fields from the sib byte. */
+#define SIB_SCALE_FIELD(sib) (((sib) >> 6) & 3)
+#define SIB_INDEX_FIELD(sib) (((sib) >> 3) & 7)
+#define SIB_BASE_FIELD(sib) (((sib) >> 0) & 7)
+
/* x86-64 extension prefix. */
#define REX_OPCODE 0x40
+/* Non-zero if OPCODE is the rex prefix. */
+#define REX_PREFIX_P(opcode) (((opcode) & 0xf0) == REX_OPCODE)
+
/* Indicates 64 bit operand size. */
#define REX_W 8
/* High extension to reg field of modrm byte. */
@@ -113,3 +141,5 @@
/* max size of register name in insn mnemonics. */
#define MAX_REG_NAME_SIZE 8
+
+#endif /* OPCODE_I386_H */
diff --git a/external/gpl3/binutils/dist/include/opcode/i860.h b/external/gpl3/binutils/dist/include/opcode/i860.h
index 7836bff058d..7f4aafd9c2c 100644
--- a/external/gpl3/binutils/dist/include/opcode/i860.h
+++ b/external/gpl3/binutils/dist/include/opcode/i860.h
@@ -1,23 +1,23 @@
/* Table of opcodes for the i860.
- Copyright 1989, 1991, 2000, 2002, 2003 Free Software Foundation, Inc.
+ Copyright 1989, 1991, 2000, 2002, 2003, 2010
+ Free Software Foundation, Inc.
-This file is part of GAS, the GNU Assembler, and GDB, the GNU disassembler.
+ This file is part of GAS, the GNU Assembler, and GDB, the GNU disassembler.
-GAS/GDB is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 1, or (at your option)
-any later version.
+ GAS/GDB is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
-GAS/GDB is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GAS or GDB; see the file COPYING. If not, write to
-the Free Software Foundation, 51 Franklin Street - Fifth Floor,
-Boston, MA 02110-1301, USA. */
+ GAS/GDB is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+ You should have received a copy of the GNU General Public License
+ along with GAS or GDB; see the file COPYING3. If not, write to
+ the Free Software Foundation, 51 Franklin Street - Fifth Floor,
+ Boston, MA 02110-1301, USA. */
/* Structure of an opcode table entry. */
struct i860_opcode
diff --git a/external/gpl3/binutils/dist/include/opcode/i960.h b/external/gpl3/binutils/dist/include/opcode/i960.h
index 0999aa15d68..dc0e78f88a1 100644
--- a/external/gpl3/binutils/dist/include/opcode/i960.h
+++ b/external/gpl3/binutils/dist/include/opcode/i960.h
@@ -1,10 +1,10 @@
/* Basic 80960 instruction formats.
- Copyright 2001 Free Software Foundation, Inc.
+ Copyright 2001, 2010 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2, or (at your option)
+ the Free Software Foundation; either version 3, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
@@ -15,24 +15,24 @@
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor,
- Boston, MA 02110-1301, USA.
+ Boston, MA 02110-1301, USA. */
- The 'COJ' instructions are actually COBR instructions with the 'b' in
- the mnemonic replaced by a 'j'; they are ALWAYS "de-optimized" if necessary:
- if the displacement will not fit in 13 bits, the assembler will replace them
- with the corresponding compare and branch instructions.
+/* The 'COJ' instructions are actually COBR instructions with the 'b' in
+ the mnemonic replaced by a 'j'; they are ALWAYS "de-optimized" if
+ necessary: if the displacement will not fit in 13 bits, the assembler will
+ replace them with the corresponding compare and branch instructions.
- All of the 'MEMn' instructions are the same format; the 'n' in the name
- indicates the default index scale factor (the size of the datum operated on).
+ All of the 'MEMn' instructions are the same format; the 'n' in the name
+ indicates the default index scale factor (the size of the datum operated on).
- The FBRA formats are not actually an instruction format. They are the
- "convenience directives" for branching on floating-point comparisons,
- each of which generates 2 instructions (a 'bno' and one other branch).
+ The FBRA formats are not actually an instruction format. They are the
+ "convenience directives" for branching on floating-point comparisons,
+ each of which generates 2 instructions (a 'bno' and one other branch).
- The CALLJ format is not actually an instruction format. It indicates that
- the instruction generated (a CTRL-format 'call') should have its relocation
- specially flagged for link-time replacement with a 'bal' or 'calls' if
- appropriate. */
+ The CALLJ format is not actually an instruction format. It indicates that
+ the instruction generated (a CTRL-format 'call') should have its relocation
+ specially flagged for link-time replacement with a 'bal' or 'calls' if
+ appropriate. */
#define CTRL 0
#define COBR 1
diff --git a/external/gpl3/binutils/dist/include/opcode/ia64.h b/external/gpl3/binutils/dist/include/opcode/ia64.h
index 280862dfbcc..4285377f7ba 100644
--- a/external/gpl3/binutils/dist/include/opcode/ia64.h
+++ b/external/gpl3/binutils/dist/include/opcode/ia64.h
@@ -1,7 +1,23 @@
/* ia64.h -- Header file for ia64 opcode table
- Copyright (C) 1998, 1999, 2000, 2002, 2005, 2006
+ Copyright (C) 1998, 1999, 2000, 2002, 2005, 2006, 2010
Free Software Foundation, Inc.
- Contributed by David Mosberger-Tang <davidm@hpl.hp.com> */
+ Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
+
+ This file is part of BFD, the Binary File Descriptor library.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software Foundation,
+ Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
#ifndef opcode_ia64_h
#define opcode_ia64_h
@@ -327,7 +343,7 @@ enum ia64_operand_class
struct ia64_operand
{
- enum ia64_operand_class class;
+ enum ia64_operand_class op_class;
/* Set VALUE as the operand bits for the operand of type SELF in the
instruction pointed to by CODE. If an error occurs, *CODE is not
@@ -381,14 +397,14 @@ extern struct ia64_opcode ia64_opcodes_f[];
extern struct ia64_opcode ia64_opcodes_d[];
-extern struct ia64_opcode *ia64_find_opcode (const char *name);
-extern struct ia64_opcode *ia64_find_next_opcode (struct ia64_opcode *ent);
+extern struct ia64_opcode *ia64_find_opcode (const char *);
+extern struct ia64_opcode *ia64_find_next_opcode (struct ia64_opcode *);
-extern struct ia64_opcode *ia64_dis_opcode (ia64_insn insn,
- enum ia64_insn_type type);
+extern struct ia64_opcode *ia64_dis_opcode (ia64_insn,
+ enum ia64_insn_type);
-extern void ia64_free_opcode (struct ia64_opcode *ent);
-extern const struct ia64_dependency *ia64_find_dependency (int index);
+extern void ia64_free_opcode (struct ia64_opcode *);
+extern const struct ia64_dependency *ia64_find_dependency (int);
/* To avoid circular library dependencies, this array is implemented
in bfd/cpu-ia64-opc.c: */
diff --git a/external/gpl3/binutils/dist/include/opcode/m68hc11.h b/external/gpl3/binutils/dist/include/opcode/m68hc11.h
index cddc59ad030..83f5a9a651a 100644
--- a/external/gpl3/binutils/dist/include/opcode/m68hc11.h
+++ b/external/gpl3/binutils/dist/include/opcode/m68hc11.h
@@ -1,22 +1,23 @@
/* m68hc11.h -- Header file for Motorola 68HC11 & 68HC12 opcode table
- Copyright 1999, 2000, 2002, 2003 Free Software Foundation, Inc.
+ Copyright 1999, 2000, 2002, 2003, 2010 Free Software Foundation, Inc.
Written by Stephane Carrez (stcarrez@nerim.fr)
-This file is part of GDB, GAS, and the GNU binutils.
+ This file is part of GDB, GAS, and the GNU binutils.
-GDB, GAS, and the GNU binutils are free software; you can redistribute
-them and/or modify them under the terms of the GNU General Public
-License as published by the Free Software Foundation; either version
-1, or (at your option) any later version.
+ GDB, GAS, and the GNU binutils are free software; you can redistribute
+ them and/or modify them under the terms of the GNU General Public
+ License as published by the Free Software Foundation; either version 3,
+ or (at your option) any later version.
-GDB, GAS, and the GNU binutils are distributed in the hope that they
-will be useful, but WITHOUT ANY WARRANTY; without even the implied
-warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
-the GNU General Public License for more details.
+ GDB, GAS, and the GNU binutils are distributed in the hope that they
+ will be useful, but WITHOUT ANY WARRANTY; without even the implied
+ warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
+ the GNU General Public License for more details.
-You should have received a copy of the GNU General Public License
-along with this file; see the file COPYING. If not, write to the Free
-Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
+ You should have received a copy of the GNU General Public License
+ along with this file; see the file COPYING3. If not, write to the Free
+ Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
+ MA 02110-1301, USA. */
#ifndef _OPCODE_M68HC11_H
#define _OPCODE_M68HC11_H
diff --git a/external/gpl3/binutils/dist/include/opcode/m68k.h b/external/gpl3/binutils/dist/include/opcode/m68k.h
index 2dd6d3feda0..f7bd8b450e1 100644
--- a/external/gpl3/binutils/dist/include/opcode/m68k.h
+++ b/external/gpl3/binutils/dist/include/opcode/m68k.h
@@ -1,13 +1,13 @@
/* Opcode table header for m680[01234]0/m6888[12]/m68851.
Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1999, 2001,
- 2003, 2004, 2006 Free Software Foundation, Inc.
+ 2003, 2004, 2006, 2010 Free Software Foundation, Inc.
This file is part of GDB, GAS, and the GNU binutils.
GDB, GAS, and the GNU binutils are free software; you can redistribute
them and/or modify them under the terms of the GNU General Public
- License as published by the Free Software Foundation; either version
- 1, or (at your option) any later version.
+ License as published by the Free Software Foundation; either version 3,
+ or (at your option) any later version.
GDB, GAS, and the GNU binutils are distributed in the hope that they
will be useful, but WITHOUT ANY WARRANTY; without even the implied
@@ -15,7 +15,7 @@
the GNU General Public License for more details.
You should have received a copy of the GNU General Public License
- along with this file; see the file COPYING. If not, write to the Free
+ along with this file; see the file COPYING3. If not, write to the Free
Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
02110-1301, USA. */
diff --git a/external/gpl3/binutils/dist/include/opcode/m88k.h b/external/gpl3/binutils/dist/include/opcode/m88k.h
index 2589686069a..739c0e90af8 100644
--- a/external/gpl3/binutils/dist/include/opcode/m88k.h
+++ b/external/gpl3/binutils/dist/include/opcode/m88k.h
@@ -1,22 +1,23 @@
/* Table of opcodes for the Motorola M88k family.
- Copyright 1989, 1990, 1991, 1993, 2001, 2002
+ Copyright 1989, 1990, 1991, 1993, 2001, 2002, 2010
Free Software Foundation, Inc.
-This file is part of GDB and GAS.
+ This file is part of GDB and GAS.
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software
-Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+ MA 02110-1301, USA. */
/*
* Disassembler Instruction Table
diff --git a/external/gpl3/binutils/dist/include/opcode/mmix.h b/external/gpl3/binutils/dist/include/opcode/mmix.h
index 7f561c6393b..f931545d670 100644
--- a/external/gpl3/binutils/dist/include/opcode/mmix.h
+++ b/external/gpl3/binutils/dist/include/opcode/mmix.h
@@ -1,22 +1,23 @@
/* mmix.h -- Header file for MMIX opcode table
- Copyright (C) 2001, 2003 Free Software Foundation, Inc.
+ Copyright (C) 2001, 2003, 2010 Free Software Foundation, Inc.
Written by Hans-Peter Nilsson (hp@bitrange.com)
-This file is part of GDB, GAS, and the GNU binutils.
+ This file is part of GDB, GAS, and the GNU binutils.
-GDB, GAS, and the GNU binutils are free software; you can redistribute
-them and/or modify them under the terms of the GNU General Public
-License as published by the Free Software Foundation; either version 2,
-or (at your option) any later version.
+ GDB, GAS, and the GNU binutils are free software; you can redistribute
+ them and/or modify them under the terms of the GNU General Public
+ License as published by the Free Software Foundation; either version 3,
+ or (at your option) any later version.
-GDB, GAS, and the GNU binutils are distributed in the hope that they
-will be useful, but WITHOUT ANY WARRANTY; without even the implied
-warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
-the GNU General Public License for more details.
+ GDB, GAS, and the GNU binutils are distributed in the hope that they
+ will be useful, but WITHOUT ANY WARRANTY; without even the implied
+ warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
+ the GNU General Public License for more details.
-You should have received a copy of the GNU General Public License
-along with this file; see the file COPYING. If not, write to the Free
-Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
+ You should have received a copy of the GNU General Public License
+ along with this file; see the file COPYING3. If not, write to the Free
+ Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
+ MA 02110-1301, USA. */
/* We could have just a char*[] table indexed by the register number, but
that would not allow for synonyms. The table is terminated with an
diff --git a/external/gpl3/binutils/dist/include/opcode/mn10200.h b/external/gpl3/binutils/dist/include/opcode/mn10200.h
index 51e44c629b6..b597d7b4bf7 100644
--- a/external/gpl3/binutils/dist/include/opcode/mn10200.h
+++ b/external/gpl3/binutils/dist/include/opcode/mn10200.h
@@ -1,22 +1,23 @@
/* mn10200.h -- Header file for Matsushita 10200 opcode table
- Copyright 1996, 1997 Free Software Foundation, Inc.
+ Copyright 1996, 1997, 2010 Free Software Foundation, Inc.
Written by Jeff Law, Cygnus Support
-This file is part of GDB, GAS, and the GNU binutils.
+ This file is part of GDB, GAS, and the GNU binutils.
-GDB, GAS, and the GNU binutils are free software; you can redistribute
-them and/or modify them under the terms of the GNU General Public
-License as published by the Free Software Foundation; either version
-1, or (at your option) any later version.
+ GDB, GAS, and the GNU binutils are free software; you can redistribute
+ them and/or modify them under the terms of the GNU General Public
+ License as published by the Free Software Foundation; either version 3,
+ or (at your option) any later version.
-GDB, GAS, and the GNU binutils are distributed in the hope that they
-will be useful, but WITHOUT ANY WARRANTY; without even the implied
-warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
-the GNU General Public License for more details.
+ GDB, GAS, and the GNU binutils are distributed in the hope that they
+ will be useful, but WITHOUT ANY WARRANTY; without even the implied
+ warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
+ the GNU General Public License for more details.
-You should have received a copy of the GNU General Public License
-along with this file; see the file COPYING. If not, write to the Free
-Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
+ You should have received a copy of the GNU General Public License
+ along with this file; see the file COPYING3. If not, write to the Free
+ Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
+ MA 02110-1301, USA. */
#ifndef MN10200_H
#define MN10200_H
diff --git a/external/gpl3/binutils/dist/include/opcode/mn10300.h b/external/gpl3/binutils/dist/include/opcode/mn10300.h
index a47ef48a357..16a139bce5d 100644
--- a/external/gpl3/binutils/dist/include/opcode/mn10300.h
+++ b/external/gpl3/binutils/dist/include/opcode/mn10300.h
@@ -1,22 +1,23 @@
/* mn10300.h -- Header file for Matsushita 10300 opcode table
- Copyright 1996, 1997, 1998, 1999, 2003 Free Software Foundation, Inc.
+ Copyright 1996, 1997, 1998, 1999, 2003, 2010 Free Software Foundation, Inc.
Written by Jeff Law, Cygnus Support
-This file is part of GDB, GAS, and the GNU binutils.
+ This file is part of GDB, GAS, and the GNU binutils.
-GDB, GAS, and the GNU binutils are free software; you can redistribute
-them and/or modify them under the terms of the GNU General Public
-License as published by the Free Software Foundation; either version
-1, or (at your option) any later version.
+ GDB, GAS, and the GNU binutils are free software; you can redistribute
+ them and/or modify them under the terms of the GNU General Public
+ License as published by the Free Software Foundation; either version 3,
+ or (at your option) any later version.
-GDB, GAS, and the GNU binutils are distributed in the hope that they
-will be useful, but WITHOUT ANY WARRANTY; without even the implied
-warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
-the GNU General Public License for more details.
+ GDB, GAS, and the GNU binutils are distributed in the hope that they
+ will be useful, but WITHOUT ANY WARRANTY; without even the implied
+ warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
+ the GNU General Public License for more details.
-You should have received a copy of the GNU General Public License
-along with this file; see the file COPYING. If not, write to the Free
-Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
+ You should have received a copy of the GNU General Public License
+ along with this file; see the file COPYING3. If not, write to the Free
+ Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
+ MA 02110-1301, USA. */
#ifndef MN10300_H
#define MN10300_H
diff --git a/external/gpl3/binutils/dist/include/opcode/moxie.h b/external/gpl3/binutils/dist/include/opcode/moxie.h
new file mode 100644
index 00000000000..e2bc374f044
--- /dev/null
+++ b/external/gpl3/binutils/dist/include/opcode/moxie.h
@@ -0,0 +1,72 @@
+/* Definitions for decoding the moxie opcode table.
+ Copyright 2009 Free Software Foundation, Inc.
+ Contributed by Anthony Green (green@moxielogic.com).
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
+ 02110-1301, USA. */
+
+/* Form 1 instructions come in different flavors:
+
+ Some have no arguments (MOXIE_F1_NARG)
+ Some only use the A operand (MOXIE_F1_A)
+ Some use A and B registers (MOXIE_F1_AB)
+ Some use A and consume a 4 byte immediate value (MOXIE_F1_A4)
+ Some use just a 4 byte immediate value (MOXIE_F1_4)
+ Some use just a 4 byte memory address (MOXIE_F1_M)
+ Some use B and an indirect A (MOXIE_F1_AiB)
+ Some use A and an indirect B (MOXIE_F1_ABi)
+ Some consume a 4 byte immediate value and use X (MOXIE_F1_4A)
+ Some use B and an indirect A plus 4 bytes (MOXIE_F1_AiB4)
+ Some use A and an indirect B plus 4 bytes (MOXIE_F1_ABi4)
+
+ Form 2 instructions also come in different flavors:
+
+ Some have no arguments (MOXIE_F2_NARG)
+ Some use the A register and an 8-bit value (MOXIE_F2_A8V)
+
+ Form 3 instructions also come in different flavors:
+
+ Some have no arguments (MOXIE_F3_NARG)
+ Some have a 10-bit PC relative operand (MOXIE_F3_PCREL). */
+
+#define MOXIE_F1_NARG 0x100
+#define MOXIE_F1_A 0x101
+#define MOXIE_F1_AB 0x102
+/* #define MOXIE_F1_ABC 0x103 */
+#define MOXIE_F1_A4 0x104
+#define MOXIE_F1_4 0x105
+#define MOXIE_F1_AiB 0x106
+#define MOXIE_F1_ABi 0x107
+#define MOXIE_F1_4A 0x108
+#define MOXIE_F1_AiB4 0x109
+#define MOXIE_F1_ABi4 0x10a
+#define MOXIE_F1_M 0x10b
+
+#define MOXIE_F2_NARG 0x200
+#define MOXIE_F2_A8V 0x201
+
+#define MOXIE_F3_NARG 0x300
+#define MOXIE_F3_PCREL 0x301
+
+typedef struct moxie_opc_info_t
+{
+ short opcode;
+ unsigned itype;
+ const char * name;
+} moxie_opc_info_t;
+
+extern const moxie_opc_info_t moxie_form1_opc_info[64];
+extern const moxie_opc_info_t moxie_form2_opc_info[4];
+extern const moxie_opc_info_t moxie_form3_opc_info[16];
diff --git a/external/gpl3/binutils/dist/include/opcode/msp430.h b/external/gpl3/binutils/dist/include/opcode/msp430.h
index eec2f1e45a0..d3bf130ee09 100644
--- a/external/gpl3/binutils/dist/include/opcode/msp430.h
+++ b/external/gpl3/binutils/dist/include/opcode/msp430.h
@@ -1,11 +1,11 @@
/* Opcode table for the TI MSP430 microcontrollers
- Copyright 2002, 2004 Free Software Foundation, Inc.
+ Copyright 2002, 2004, 2010 Free Software Foundation, Inc.
Contributed by Dmitry Diky <diwil@mail.ru>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2, or (at your option)
+ the Free Software Foundation; either version 3, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
@@ -15,7 +15,8 @@
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
- Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
+ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+ MA 02110-1301, USA. */
#ifndef __MSP430_H_
#define __MSP430_H_
diff --git a/external/gpl3/binutils/dist/include/opcode/np1.h b/external/gpl3/binutils/dist/include/opcode/np1.h
index ebe37f5d2df..6dadafde0db 100644
--- a/external/gpl3/binutils/dist/include/opcode/np1.h
+++ b/external/gpl3/binutils/dist/include/opcode/np1.h
@@ -1,21 +1,22 @@
/* Print GOULD NPL instructions for GDB, the GNU debugger.
- Copyright 1986, 1987, 1989, 1991 Free Software Foundation, Inc.
+ Copyright 1986, 1987, 1989, 1991, 2010 Free Software Foundation, Inc.
-This file is part of GDB.
+ This file is part of GDB.
-GDB is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 1, or (at your option)
-any later version.
+ GDB is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
-GDB is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
+ GDB is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
-You should have received a copy of the GNU General Public License
-along with GDB; see the file COPYING. If not, write to
-the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
+ You should have received a copy of the GNU General Public License
+ along with GDB; see the file COPYING3. If not, write to
+ the Free Software Foundation, 51 Franklin Street - Fifth Floor,
+ Boston, MA 02110-1301, USA. */
struct gld_opcode
{
@@ -36,7 +37,7 @@ struct gld_opcode
of that opcode.
The args component is a string containing characters
- that are used to format the arguments to the instruction. */
+ that are used to format the arguments to the instruction. */
/* Kinds of operands:
r Register in first field
@@ -53,14 +54,12 @@ struct gld_opcode
d Offset field (14bits signed)
S Shift count field
- any other characters are printed as is...
-*/
+ any other characters are printed as is... */
/* The assembler requires that this array be sorted as follows:
all instances of the same mnemonic must be consecutive.
All instances of the same mnemonic with the same number of operands
- must be consecutive.
- */
+ must be consecutive. */
struct gld_opcode gld_opcodes[] =
{
{ "lb", 0xb4080000, 0xfc080000, "r,xOA,X", 4 },
diff --git a/external/gpl3/binutils/dist/include/opcode/ns32k.h b/external/gpl3/binutils/dist/include/opcode/ns32k.h
index 5cb2f97cc38..34c42f87593 100644
--- a/external/gpl3/binutils/dist/include/opcode/ns32k.h
+++ b/external/gpl3/binutils/dist/include/opcode/ns32k.h
@@ -1,22 +1,22 @@
/* ns32k-opcode.h -- Opcode table for National Semi 32k processor
- Copyright 1987, 1991, 1994, 2002 Free Software Foundation, Inc.
+ Copyright 1987, 1991, 1994, 2002, 2010 Free Software Foundation, Inc.
-This file is part of GAS, the GNU Assembler.
+ This file is part of GAS, the GNU Assembler.
-GAS is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 1, or (at your option)
-any later version.
+ GAS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
-GAS is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GAS; see the file COPYING. If not, write to
-the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
+ GAS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+ You should have received a copy of the GNU General Public License
+ along with GAS; see the file COPYING3. If not, write to
+ the Free Software Foundation, 51 Franklin Street - Fifth Floor,
+ Boston, MA 02110-1301, USA. */
#ifdef SEQUENT_COMPATABILITY
#define DEF_MODEC 20
diff --git a/external/gpl3/binutils/dist/include/opcode/or32.h b/external/gpl3/binutils/dist/include/opcode/or32.h
index 3412b22b65c..153d91ec42f 100644
--- a/external/gpl3/binutils/dist/include/opcode/or32.h
+++ b/external/gpl3/binutils/dist/include/opcode/or32.h
@@ -1,12 +1,12 @@
/* Table of opcodes for the OpenRISC 1000 ISA.
- Copyright 2002, 2003 Free Software Foundation, Inc.
+ Copyright 2002, 2003, 2010 Free Software Foundation, Inc.
Contributed by Damjan Lampret (lampret@opencores.org).
This file is part of or1k_gen_isa, or1ksim, GDB and GAS.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
+ the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
@@ -16,7 +16,8 @@
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
- Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
+ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+ MA 02110-1301, USA. */
/* We treat all letters the same in encode/decode routines so
we need to assign some characteristics to them like signess etc. */
diff --git a/external/gpl3/binutils/dist/include/opcode/pdp11.h b/external/gpl3/binutils/dist/include/opcode/pdp11.h
index 0f0256ba21b..24e13b25ae5 100644
--- a/external/gpl3/binutils/dist/include/opcode/pdp11.h
+++ b/external/gpl3/binutils/dist/include/opcode/pdp11.h
@@ -1,25 +1,24 @@
/* PDP-11 opcde list.
- Copyright 2001, 2002 Free Software Foundation, Inc.
+ Copyright 2001, 2002, 2010 Free Software Foundation, Inc.
-This file is part of GDB and GAS.
+ This file is part of GDB and GAS.
-GDB and GAS are free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 1, or (at your option)
-any later version.
+ GDB and GAS are free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
-GDB and GAS are distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
+ GDB and GAS are distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
-You should have received a copy of the GNU General Public License
-along with GDB or GAS; see the file COPYING. If not, write to
-the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
+ You should have received a copy of the GNU General Public License
+ along with GDB or GAS; see the file COPYING3. If not, write to
+ the Free Software Foundation, 51 Franklin Street - Fifth Floor,
+ Boston, MA 02110-1301, USA. */
-/*
- * PDP-11 opcode types.
- */
+/* PDP-11 opcode types. */
#define PDP11_OPCODE_NO_OPS 0
#define PDP11_OPCODE_REG 1 /* register */
diff --git a/external/gpl3/binutils/dist/include/opcode/pj.h b/external/gpl3/binutils/dist/include/opcode/pj.h
index 30201d68509..e6ffacc4ba3 100644
--- a/external/gpl3/binutils/dist/include/opcode/pj.h
+++ b/external/gpl3/binutils/dist/include/opcode/pj.h
@@ -1,21 +1,21 @@
/* Definitions for decoding the picoJava opcode table.
- Copyright 1999, 2002, 2003 Free Software Foundation, Inc.
+ Copyright 1999, 2002, 2003, 2010 Free Software Foundation, Inc.
Contributed by Steve Chamberlain of Transmeta (sac@pobox.com).
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software
-Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+ MA 02110-1301, USA. */
/* Names used to describe the type of instruction arguments, used by
the assembler and disassembler. Attributes are encoded in various fields. */
diff --git a/external/gpl3/binutils/dist/include/opcode/pn.h b/external/gpl3/binutils/dist/include/opcode/pn.h
index f8d474f60a5..6674030c4fd 100644
--- a/external/gpl3/binutils/dist/include/opcode/pn.h
+++ b/external/gpl3/binutils/dist/include/opcode/pn.h
@@ -1,21 +1,22 @@
/* Print GOULD PN (PowerNode) instructions for GDB, the GNU debugger.
- Copyright 1986, 1987, 1989, 1991 Free Software Foundation, Inc.
+ Copyright 1986, 1987, 1989, 1991, 2010 Free Software Foundation, Inc.
-This file is part of GDB.
+ This file is part of GDB.
-GDB is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 1, or (at your option)
-any later version.
+ GDB is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
-GDB is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
+ GDB is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
-You should have received a copy of the GNU General Public License
-along with GDB; see the file COPYING. If not, write to
-the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
+ You should have received a copy of the GNU General Public License
+ along with GDB; see the file COPYING3. If not, write to
+ the Free Software Foundation, 51 Franklin Street - Fifth Floor,
+ Boston, MA 02110-1301, USA. */
struct gld_opcode
{
diff --git a/external/gpl3/binutils/dist/include/opcode/pyr.h b/external/gpl3/binutils/dist/include/opcode/pyr.h
index a523dfd7284..2fffd946213 100644
--- a/external/gpl3/binutils/dist/include/opcode/pyr.h
+++ b/external/gpl3/binutils/dist/include/opcode/pyr.h
@@ -1,10 +1,10 @@
/* pyramid.opcode.h -- gdb initial attempt.
- Copyright 2001 Free Software Foundation, Inc.
+ Copyright 2001, 2010 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2, or (at your option)
+ the Free Software Foundation; either version 3, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
diff --git a/external/gpl3/binutils/dist/include/opcode/rx.h b/external/gpl3/binutils/dist/include/opcode/rx.h
new file mode 100644
index 00000000000..aa85fe4a916
--- /dev/null
+++ b/external/gpl3/binutils/dist/include/opcode/rx.h
@@ -0,0 +1,215 @@
+/* Opcode decoder for the Renesas RX
+ Copyright 2008, 2009, 2010
+ Free Software Foundation, Inc.
+ Written by DJ Delorie <dj@redhat.com>
+
+ This file is part of GDB, the GNU Debugger and GAS, the GNU Assembler.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
+ 02110-1301, USA. */
+
+/* The RX decoder in libopcodes is used by the simulator, gdb's
+ analyzer, and the disassembler. Given an opcode data source,
+ it decodes the next opcode into the following structures. */
+
+typedef enum
+{
+ RX_AnySize = 0,
+ RX_Byte, /* undefined extension */
+ RX_UByte,
+ RX_SByte,
+ RX_Word, /* undefined extension */
+ RX_UWord,
+ RX_SWord,
+ RX_3Byte,
+ RX_Long,
+} RX_Size;
+
+typedef enum
+{
+ RX_Operand_None,
+ RX_Operand_Immediate, /* #addend */
+ RX_Operand_Register, /* Rn */
+ RX_Operand_Indirect, /* [Rn + addend] */
+ RX_Operand_Postinc, /* [Rn+] */
+ RX_Operand_Predec, /* [-Rn] */
+ RX_Operand_Condition, /* eq, gtu, etc */
+ RX_Operand_Flag, /* [UIOSZC] */
+ RX_Operand_TwoReg, /* [Rn + scale*R2] */
+} RX_Operand_Type;
+
+typedef enum
+{
+ RXO_unknown,
+ RXO_mov, /* d = s (signed) */
+ RXO_movbi, /* d = [s,s2] (signed) */
+ RXO_movbir, /* [s,s2] = d (signed) */
+ RXO_pushm, /* s..s2 */
+ RXO_popm, /* s..s2 */
+ RXO_xchg, /* s <-> d */
+ RXO_stcc, /* d = s if cond(s2) */
+ RXO_rtsd, /* rtsd, 1=imm, 2-0 = reg if reg type */
+
+ /* These are all either d OP= s or, if s2 is set, d = s OP s2. Note
+ that d may be "None". */
+ RXO_and,
+ RXO_or,
+ RXO_xor,
+ RXO_add,
+ RXO_sub,
+ RXO_mul,
+ RXO_div,
+ RXO_divu,
+ RXO_shll,
+ RXO_shar,
+ RXO_shlr,
+
+ RXO_adc, /* d = d + s + carry */
+ RXO_sbb, /* d = d - s - ~carry */
+ RXO_abs, /* d = |s| */
+ RXO_max, /* d = max(d,s) */
+ RXO_min, /* d = min(d,s) */
+ RXO_emul, /* d:64 = d:32 * s */
+ RXO_emulu, /* d:64 = d:32 * s (unsigned) */
+
+ RXO_rolc, /* d <<= 1 through carry */
+ RXO_rorc, /* d >>= 1 through carry*/
+ RXO_rotl, /* d <<= #s without carry */
+ RXO_rotr, /* d >>= #s without carry*/
+ RXO_revw, /* d = revw(s) */
+ RXO_revl, /* d = revl(s) */
+ RXO_branch, /* pc = d if cond(s) */
+ RXO_branchrel,/* pc += d if cond(s) */
+ RXO_jsr, /* pc = d */
+ RXO_jsrrel, /* pc += d */
+ RXO_rts,
+ RXO_nop,
+ RXO_nop2,
+ RXO_nop3,
+
+ RXO_scmpu,
+ RXO_smovu,
+ RXO_smovb,
+ RXO_suntil,
+ RXO_swhile,
+ RXO_smovf,
+ RXO_sstr,
+
+ RXO_rmpa,
+ RXO_mulhi,
+ RXO_mullo,
+ RXO_machi,
+ RXO_maclo,
+ RXO_mvtachi,
+ RXO_mvtaclo,
+ RXO_mvfachi,
+ RXO_mvfacmi,
+ RXO_mvfaclo,
+ RXO_racw,
+
+ RXO_sat, /* sat(d) */
+ RXO_satr,
+
+ RXO_fadd, /* d op= s */
+ RXO_fcmp,
+ RXO_fsub,
+ RXO_ftoi,
+ RXO_fmul,
+ RXO_fdiv,
+ RXO_round,
+ RXO_itof,
+
+ RXO_bset, /* d |= (1<<s) */
+ RXO_bclr, /* d &= ~(1<<s) */
+ RXO_btst, /* s & (1<<s2) */
+ RXO_bnot, /* d ^= (1<<s) */
+ RXO_bmcc, /* d<s> = cond(s2) */
+
+ RXO_clrpsw, /* flag index in d */
+ RXO_setpsw, /* flag index in d */
+ RXO_mvtipl, /* new IPL in s */
+
+ RXO_rtfi,
+ RXO_rte,
+ RXO_rtd, /* undocumented */
+ RXO_brk,
+ RXO_dbt, /* undocumented */
+ RXO_int, /* vector id in s */
+ RXO_stop,
+ RXO_wait,
+
+ RXO_sccnd, /* d = cond(s) ? 1 : 0 */
+} RX_Opcode_ID;
+
+/* Condition bitpatterns, as registers. */
+#define RXC_eq 0
+#define RXC_z 0
+#define RXC_ne 1
+#define RXC_nz 1
+#define RXC_c 2
+#define RXC_nc 3
+#define RXC_gtu 4
+#define RXC_leu 5
+#define RXC_pz 6
+#define RXC_n 7
+#define RXC_ge 8
+#define RXC_lt 9
+#define RXC_gt 10
+#define RXC_le 11
+#define RXC_o 12
+#define RXC_no 13
+#define RXC_always 14
+#define RXC_never 15
+
+typedef struct
+{
+ RX_Operand_Type type;
+ int reg;
+ int addend;
+ RX_Size size;
+} RX_Opcode_Operand;
+
+typedef struct
+{
+ RX_Opcode_ID id;
+ int n_bytes;
+ int prefix;
+ char * syntax;
+ RX_Size size;
+ /* By convention, these are destination, source1, source2. */
+ RX_Opcode_Operand op[3];
+
+ /* The logic here is:
+ newflags = (oldflags & ~(int)flags_0) | flags_1 | (op_flags & flags_s)
+ Only the O, S, Z, and C flags are affected. */
+ char flags_0; /* This also clears out flags-to-be-set. */
+ char flags_1;
+ char flags_s;
+} RX_Opcode_Decoded;
+
+/* Within the syntax, %c-style format specifiers are as follows:
+
+ %% = '%' character
+ %0 = operand[0] (destination)
+ %1 = operand[1] (source)
+ %2 = operand[2] (2nd source)
+ %s = operation size (b/w/l)
+ %SN = operand size [N] (N=0,1,2)
+ %aN = op[N] as an address (N=0,1,2)
+
+ Register numbers 0..15 are general registers. 16..31 are control
+ registers. 32..47 are condition codes. */
+
+int rx_decode_opcode (unsigned long, RX_Opcode_Decoded *, int (*)(void *), void *);
diff --git a/external/gpl3/binutils/dist/include/opcode/s390.h b/external/gpl3/binutils/dist/include/opcode/s390.h
index 2c00f4b62e8..2cbe5f53d60 100644
--- a/external/gpl3/binutils/dist/include/opcode/s390.h
+++ b/external/gpl3/binutils/dist/include/opcode/s390.h
@@ -1,12 +1,12 @@
/* s390.h -- Header file for S390 opcode table
- Copyright 2000, 2001, 2003 Free Software Foundation, Inc.
+ Copyright 2000, 2001, 2003, 2010 Free Software Foundation, Inc.
Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com).
This file is part of BFD, the Binary File Descriptor library.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
+ the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
@@ -38,7 +38,9 @@ enum s390_opcode_cpu_val
S390_OPCODE_Z990,
S390_OPCODE_Z9_109,
S390_OPCODE_Z9_EC,
- S390_OPCODE_Z10
+ S390_OPCODE_Z10,
+ S390_OPCODE_Z196,
+ S390_OPCODE_MAXCPU
};
/* The opcode table is an array of struct s390_opcode. */
diff --git a/external/gpl3/binutils/dist/include/opcode/score-datadep.h b/external/gpl3/binutils/dist/include/opcode/score-datadep.h
index 8ef35adc807..10ddf32f67f 100644
--- a/external/gpl3/binutils/dist/include/opcode/score-datadep.h
+++ b/external/gpl3/binutils/dist/include/opcode/score-datadep.h
@@ -1,6 +1,7 @@
/* score-datadep.h -- Score Instructions data dependency table
- Copyright 2006 Free Software Foundation, Inc.
+ Copyright 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
Contributed by:
+ Brain.lin (brain.lin@sunplusct.com)
Mei Ligang (ligang@sunnorth.com.cn)
Pei-Lin Tsai (pltsai@sunplus.com)
@@ -8,7 +9,7 @@
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2, or (at your option)
+ the Free Software Foundation; either version 3, or (at your option)
any later version.
GAS is distributed in the hope that it will be useful,
@@ -17,7 +18,7 @@
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
- along with GAS; see the file COPYING. If not, write to the Free
+ along with GAS; see the file COPYING3. If not, write to the Free
Software Foundation, Inc., 51 Franklin Street - Fifth Floor,
Boston, MA 02110-1301, USA. */
@@ -28,20 +29,7 @@
enum insn_type_for_dependency
{
- D_pce,
- D_cond_br,
- D_cond_mv,
- D_cached,
- D_cachei,
- D_ldst,
- D_ldcombine,
D_mtcr,
- D_mfcr,
- D_mfsr,
- D_mftlb,
- D_mtptlb,
- D_mtrtlb,
- D_stlb,
D_all_insn
};
@@ -58,225 +46,20 @@ struct data_dependency
enum insn_type_for_dependency cur_insn_type;
char cur_reg[6];
int bubblenum_7;
- int bubblenum_5;
+ int bubblenum_3;
int warn_or_error; /* warning - 0; error - 1 */
};
static const struct insn_to_dependency insn_to_dependency_table[] =
{
- /* pce instruction. */
- {"pce", D_pce},
- /* conditional branch instruction. */
- {"bcs", D_cond_br},
- {"bcc", D_cond_br},
- {"bgtu", D_cond_br},
- {"bleu", D_cond_br},
- {"beq", D_cond_br},
- {"bne", D_cond_br},
- {"bgt", D_cond_br},
- {"ble", D_cond_br},
- {"bge", D_cond_br},
- {"blt", D_cond_br},
- {"bmi", D_cond_br},
- {"bpl", D_cond_br},
- {"bvs", D_cond_br},
- {"bvc", D_cond_br},
- {"bcsl", D_cond_br},
- {"bccl", D_cond_br},
- {"bgtul", D_cond_br},
- {"bleul", D_cond_br},
- {"beql", D_cond_br},
- {"bnel", D_cond_br},
- {"bgtl", D_cond_br},
- {"blel", D_cond_br},
- {"bgel", D_cond_br},
- {"bltl", D_cond_br},
- {"bmil", D_cond_br},
- {"bpll", D_cond_br},
- {"bvsl", D_cond_br},
- {"bvcl", D_cond_br},
- {"bcs!", D_cond_br},
- {"bcc!", D_cond_br},
- {"bgtu!", D_cond_br},
- {"bleu!", D_cond_br},
- {"beq!", D_cond_br},
- {"bne!", D_cond_br},
- {"bgt!", D_cond_br},
- {"ble!", D_cond_br},
- {"bge!", D_cond_br},
- {"blt!", D_cond_br},
- {"bmi!", D_cond_br},
- {"bpl!", D_cond_br},
- {"bvs!", D_cond_br},
- {"bvc!", D_cond_br},
- {"brcs", D_cond_br},
- {"brcc", D_cond_br},
- {"brgtu", D_cond_br},
- {"brleu", D_cond_br},
- {"breq", D_cond_br},
- {"brne", D_cond_br},
- {"brgt", D_cond_br},
- {"brle", D_cond_br},
- {"brge", D_cond_br},
- {"brlt", D_cond_br},
- {"brmi", D_cond_br},
- {"brpl", D_cond_br},
- {"brvs", D_cond_br},
- {"brvc", D_cond_br},
- {"brcsl", D_cond_br},
- {"brccl", D_cond_br},
- {"brgtul", D_cond_br},
- {"brleul", D_cond_br},
- {"breql", D_cond_br},
- {"brnel", D_cond_br},
- {"brgtl", D_cond_br},
- {"brlel", D_cond_br},
- {"brgel", D_cond_br},
- {"brltl", D_cond_br},
- {"brmil", D_cond_br},
- {"brpll", D_cond_br},
- {"brvsl", D_cond_br},
- {"brvcl", D_cond_br},
- {"brcs!", D_cond_br},
- {"brcc!", D_cond_br},
- {"brgtu!", D_cond_br},
- {"brleu!", D_cond_br},
- {"breq!", D_cond_br},
- {"brne!", D_cond_br},
- {"brgt!", D_cond_br},
- {"brle!", D_cond_br},
- {"brge!", D_cond_br},
- {"brlt!", D_cond_br},
- {"brmi!", D_cond_br},
- {"brpl!", D_cond_br},
- {"brvs!", D_cond_br},
- {"brvc!", D_cond_br},
- {"brcsl!", D_cond_br},
- {"brccl!", D_cond_br},
- {"brgtul!", D_cond_br},
- {"brleul!", D_cond_br},
- {"breql!", D_cond_br},
- {"brnel!", D_cond_br},
- {"brgtl!", D_cond_br},
- {"brlel!", D_cond_br},
- {"brgel!", D_cond_br},
- {"brltl!", D_cond_br},
- {"brmil!", D_cond_br},
- {"brpll!", D_cond_br},
- {"brvsl!", D_cond_br},
- {"brvcl!", D_cond_br},
- /* conditional move instruction. */
- {"mvcs", D_cond_mv},
- {"mvcc", D_cond_mv},
- {"mvgtu", D_cond_mv},
- {"mvleu", D_cond_mv},
- {"mveq", D_cond_mv},
- {"mvne", D_cond_mv},
- {"mvgt", D_cond_mv},
- {"mvle", D_cond_mv},
- {"mvge", D_cond_mv},
- {"mvlt", D_cond_mv},
- {"mvmi", D_cond_mv},
- {"mvpl", D_cond_mv},
- {"mvvs", D_cond_mv},
- {"mvvc", D_cond_mv},
/* move spectial instruction. */
{"mtcr", D_mtcr},
- {"mftlb", D_mftlb},
- {"mtptlb", D_mtptlb},
- {"mtrtlb", D_mtrtlb},
- {"stlb", D_stlb},
- {"mfcr", D_mfcr},
- {"mfsr", D_mfsr},
- /* cache instruction. */
- {"cache 8", D_cached},
- {"cache 9", D_cached},
- {"cache 10", D_cached},
- {"cache 11", D_cached},
- {"cache 12", D_cached},
- {"cache 13", D_cached},
- {"cache 14", D_cached},
- {"cache 24", D_cached},
- {"cache 26", D_cached},
- {"cache 27", D_cached},
- {"cache 29", D_cached},
- {"cache 30", D_cached},
- {"cache 31", D_cached},
- {"cache 0", D_cachei},
- {"cache 1", D_cachei},
- {"cache 2", D_cachei},
- {"cache 3", D_cachei},
- {"cache 4", D_cachei},
- {"cache 16", D_cachei},
- {"cache 17", D_cachei},
- /* load/store instruction. */
- {"lb", D_ldst},
- {"lbu", D_ldst},
- {"lbu!", D_ldst},
- {"lbup!", D_ldst},
- {"lh", D_ldst},
- {"lhu", D_ldst},
- {"lh!", D_ldst},
- {"lhp!", D_ldst},
- {"lw", D_ldst},
- {"lw!", D_ldst},
- {"lwp!", D_ldst},
- {"sb", D_ldst},
- {"sb!", D_ldst},
- {"sbp!", D_ldst},
- {"sh", D_ldst},
- {"sh!", D_ldst},
- {"shp!", D_ldst},
- {"sw", D_ldst},
- {"sw!", D_ldst},
- {"swp!", D_ldst},
- {"alw", D_ldst},
- {"asw", D_ldst},
- {"push!", D_ldst},
- {"pushhi!", D_ldst},
- {"pop!", D_ldst},
- {"pophi!", D_ldst},
- {"ldc1", D_ldst},
- {"ldc2", D_ldst},
- {"ldc3", D_ldst},
- {"stc1", D_ldst},
- {"stc2", D_ldst},
- {"stc3", D_ldst},
- {"scb", D_ldst},
- {"scw", D_ldst},
- {"sce", D_ldst},
- /* load combine instruction. */
- {"lcb", D_ldcombine},
- {"lcw", D_ldcombine},
- {"lce", D_ldcombine},
};
static const struct data_dependency data_dependency_table[] =
{
- /* Condition register. */
- {D_mtcr, "cr1", D_pce, "", 2, 1, 1},
- {D_mtcr, "cr1", D_cond_br, "", 1, 0, 1},
- {D_mtcr, "cr1", D_cond_mv, "", 1, 0, 1},
/* Status regiser. */
- {D_mtcr, "cr0", D_all_insn, "", 5, 4, 0},
- /* CCR regiser. */
- {D_mtcr, "cr4", D_all_insn, "", 6, 5, 0},
- /* EntryHi/EntryLo register. */
- {D_mftlb, "", D_mtptlb, "", 1, 1, 1},
- {D_mftlb, "", D_mtrtlb, "", 1, 1, 1},
- {D_mftlb, "", D_stlb, "", 1, 1,1},
- {D_mftlb, "", D_mfcr, "cr11", 1, 1, 1},
- {D_mftlb, "", D_mfcr, "cr12", 1, 1, 1},
- /* Index register. */
- {D_stlb, "", D_mtptlb, "", 1, 1, 1},
- {D_stlb, "", D_mftlb, "", 1, 1, 1},
- {D_stlb, "", D_mfcr, "cr8", 2, 2, 1},
- /* Cache. */
- {D_cached, "", D_ldst, "", 1, 1, 0},
- {D_cached, "", D_ldcombine, "", 1, 1, 0},
- {D_cachei, "", D_all_insn, "", 5, 4, 0},
- /* Load combine. */
- {D_ldcombine, "", D_mfsr, "sr1", 3, 3, 1},
+ {D_mtcr, "cr0", D_all_insn, "", 5, 1, 0},
};
#endif
diff --git a/external/gpl3/binutils/dist/include/opcode/score-inst.h b/external/gpl3/binutils/dist/include/opcode/score-inst.h
index e87794f7744..ecb18da2a91 100644
--- a/external/gpl3/binutils/dist/include/opcode/score-inst.h
+++ b/external/gpl3/binutils/dist/include/opcode/score-inst.h
@@ -1,6 +1,7 @@
/* score-inst.h -- Score Instructions Table
- Copyright 2006 Free Software Foundation, Inc.
+ Copyright 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
Contributed by:
+ Brain.lin (brain.lin@sunplusct.com)
Mei Ligang (ligang@sunnorth.com.cn)
Pei-Lin Tsai (pltsai@sunplus.com)
@@ -8,7 +9,7 @@
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2, or (at your option)
+ the Free Software Foundation; either version 3, or (at your option)
any later version.
GAS is distributed in the hope that it will be useful,
@@ -17,7 +18,7 @@
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
- along with GAS; see the file COPYING. If not, write to the Free
+ along with GAS; see the file COPYING3. If not, write to the Free
Software Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
02110-1301, USA. */
@@ -96,6 +97,8 @@ enum score_insn_type
Rd_Rs_I14,
I15,
Rd_I16,
+ Rd_I30,
+ Rd_I32,
Rd_rvalueRs_SI10,
Rd_lvalueRs_SI10,
Rd_rvalueRs_preSI12,
@@ -105,6 +108,8 @@ enum score_insn_type
Rd_Rs_SI14,
Rd_rvalueRs_SI15,
Rd_lvalueRs_SI15,
+ Rd_SI5,
+ Rd_SI6,
Rd_SI16,
PC_DISP8div2,
PC_DISP11div2,
@@ -139,6 +144,8 @@ enum score_insn_type
Insn_GP,
Insn_PIC,
Insn_internal,
+ Insn_BCMP,
+ Ra_I9_I5,
};
enum score_data_type
@@ -178,6 +185,13 @@ enum score_data_type
_SIMM16_pic = 42, /* Index in score_df_range. */
_IMM16_LO16_pic = 43,
_IMM16_pic = 44,
+
+ _SIMM5 = 45,
+ _SIMM6 = 46,
+ _IMM32 = 47,
+ _SIMM32 = 48,
+ _IMM11 = 49,
+ _IMM5_MULTI_LOAD = 50,
};
#define REG_TMP 1
@@ -206,302 +220,17 @@ enum score_data_type
#define OP16_SH_DISP8 (OP_IMM_TYPE | 0)
#define OP16_SH_DISP11 (OP_IMM_TYPE | 1)
-struct datafield_range
-{
- int data_type;
- int bits;
- int range[2];
-};
-
-struct datafield_range score_df_range[] =
-{
- {_IMM4, 4, {0, (1 << 4) - 1}}, /* ( 0 ~ 15 ) */
- {_IMM5, 5, {0, (1 << 5) - 1}}, /* ( 0 ~ 31 ) */
- {_IMM8, 8, {0, (1 << 8) - 1}}, /* ( 0 ~ 255 ) */
- {_IMM14, 14, {0, (1 << 14) - 1}}, /* ( 0 ~ 16383) */
- {_IMM15, 15, {0, (1 << 15) - 1}}, /* ( 0 ~ 32767) */
- {_IMM16, 16, {0, (1 << 16) - 1}}, /* ( 0 ~ 65535) */
- {_SIMM10, 10, {-(1 << 9), (1 << 9) - 1}}, /* ( -512 ~ 511 ) */
- {_SIMM12, 12, {-(1 << 11), (1 << 11) - 1}}, /* ( -2048 ~ 2047 ) */
- {_SIMM14, 14, {-(1 << 13), (1 << 13) - 1}}, /* ( -8192 ~ 8191 ) */
- {_SIMM15, 15, {-(1 << 14), (1 << 14) - 1}}, /* (-16384 ~ 16383) */
- {_SIMM16, 16, {-(1 << 15), (1 << 15) - 1}}, /* (-32768 ~ 32767) */
- {_SIMM14_NEG, 14, {-(1 << 13), (1 << 13) - 1}}, /* ( -8191 ~ 8192 ) */
- {_IMM16_NEG, 16, {0, (1 << 16) - 1}}, /* (-65535 ~ 0 ) */
- {_SIMM16_NEG, 16, {-(1 << 15), (1 << 15) - 1}}, /* (-32768 ~ 32767) */
- {_IMM20, 20, {0, (1 << 20) - 1}},
- {_IMM25, 25, {0, (1 << 25) - 1}},
- {_DISP8div2, 8, {-(1 << 8), (1 << 8) - 1}}, /* ( -256 ~ 255 ) */
- {_DISP11div2, 11, {0, 0}},
- {_DISP19div2, 19, {-(1 << 19), (1 << 19) - 1}}, /* (-524288 ~ 524287) */
- {_DISP24div2, 24, {0, 0}},
- {_VALUE, 32, {0, ((unsigned int)1 << 31) - 1}},
- {_VALUE_HI16, 16, {0, (1 << 16) - 1}},
- {_VALUE_LO16, 16, {0, (1 << 16) - 1}},
- {_VALUE_LDST_LO16, 16, {0, (1 << 16) - 1}},
- {_SIMM16_LA, 16, {-(1 << 15), (1 << 15) - 1}}, /* (-32768 ~ 32767) */
- {_IMM5_RSHIFT_1, 5, {0, (1 << 6) - 1}}, /* ( 0 ~ 63 ) */
- {_IMM5_RSHIFT_2, 5, {0, (1 << 7) - 1}}, /* ( 0 ~ 127 ) */
- {_SIMM16_LA_POS, 16, {0, (1 << 15) - 1}}, /* ( 0 ~ 32767) */
- {_IMM5_RANGE_8_31, 5, {8, 31}}, /* But for cop0 the valid data : (8 ~ 31). */
- {_IMM10_RSHIFT_2, 10, {-(1 << 11), (1 << 11) - 1}}, /* For ldc#, stc#. */
- {_SIMM10, 10, {0, (1 << 10) - 1}}, /* ( -1024 ~ 1023 ) */
- {_SIMM12, 12, {0, (1 << 12) - 1}}, /* ( -2048 ~ 2047 ) */
- {_SIMM14, 14, {0, (1 << 14) - 1}}, /* ( -8192 ~ 8191 ) */
- {_SIMM15, 15, {0, (1 << 15) - 1}}, /* (-16384 ~ 16383) */
- {_SIMM16, 16, {0, (1 << 16) - 1}}, /* (-65536 ~ 65536) */
- {_SIMM14_NEG, 14, {0, (1 << 16) - 1}}, /* ( -8191 ~ 8192 ) */
- {_IMM16_NEG, 16, {0, (1 << 16) - 1}}, /* ( 65535 ~ 0 ) */
- {_SIMM16_NEG, 16, {0, (1 << 16) - 1}}, /* ( 65535 ~ 0 ) */
- {_IMM20, 20, {0, (1 << 20) - 1}}, /* (-32768 ~ 32767) */
- {_IMM25, 25, {0, (1 << 25) - 1}}, /* (-32768 ~ 32767) */
- {_GP_IMM15, 15, {0, (1 << 15) - 1}}, /* ( 0 ~ 65535) */
- {_GP_IMM14, 14, {0, (1 << 14) - 1}}, /* ( 0 ~ 65535) */
- {_SIMM16_pic, 16, {-(1 << 15), (1 << 15) - 1}}, /* (-32768 ~ 32767) */
- {_IMM16_LO16_pic, 16, {0, (1 << 16) - 1}}, /* ( 65535 ~ 0 ) */
- {_IMM16_pic, 16, {0, (1 << 16) - 1}}, /* ( 0 ~ 65535) */
-};
-
-struct shift_bitmask
-{
- int opd_type;
- int opd_num;
- struct datafield_range *df_range;
- int sh[4];
- long fieldbits[4];
-};
-
-struct shift_bitmask score_sh_bits_map[] =
-{
- {
- Rd_I4, 2, &score_df_range[_IMM4],
- {OP16_SH_REGD, OP16_SH_I45, 0, 0},
- {0xf, 0xf, 0, 0},
- },
- {
- Rd_I5, 2, &score_df_range[_IMM5],
- {OP16_SH_REGD, OP16_SH_I45, 0, 0},
- {0xf, 0x1f, 0, 0},
- },
- {
- Rd_rvalueBP_I5, 2, &score_df_range[_IMM5],
- {OP16_SH_REGD, OP16_SH_I45, 0, 0},
- {0xf, 0x1f, 0, 0},
- },
- {
- Rd_lvalueBP_I5, 2, &score_df_range[_IMM5],
- {OP16_SH_REGD, OP16_SH_I45, 0, 0},
- {0xf, 0x1f, 0, 0},
- },
- {
- Rd_Rs_I5, 3, &score_df_range[_IMM5],
- {OP_SH_REGD, OP_SH_REGS1, OP_SH_I5, 0},
- {0x1f, 0x1f, 0x1f, 0},
- },
- {
- x_Rs_I5, 2, &score_df_range[_IMM5],
- {OP_SH_REGS1, OP_SH_I5, 0, 0},
- {0x1f, 0x1f, 0, 0},
- },
- {
- x_I5_x, 1, &score_df_range[_IMM5],
- {OP_SH_TRAPI5, 0, 0, 0},
- {0x1f, 0, 0, 0},
- },
- {
- Rd_I8, 2, &score_df_range[_IMM8],
- {OP16_SH_REGD, OP16_SH_I8, 0, 0},
- {0xf, 0xff, 0, 0},
- },
- {
- Rd_Rs_I14, 3, &score_df_range[_IMM14],
- {OP_SH_REGD, OP_SH_REGS1, OP_SH_I, 0},
- {0x1f, 0x1f, 0x3fff, 0},
- },
- {
- I15, 1, &score_df_range[_IMM15],
- {OP_SH_I15, 0, 0, 0},
- {0x7fff, 0, 0, 0},
- },
- {
- Rd_I16, 2, &score_df_range[_IMM16],
- {OP_SH_REGD, OP_SH_I, 0, 0},
- {0x1f, 0xffff, 0, 0},
- },
- {
- Rd_rvalueRs_SI10, 3, &score_df_range[_SIMM10],
- {OP_SH_REGD, OP_SH_REGS1, OP_SH_I10, 0},
- {0x1f, 0x1f, 0x3ff, 0},
- },
- {
- Rd_lvalueRs_SI10, 3, &score_df_range[_SIMM10],
- {OP_SH_REGD, OP_SH_REGS1, OP_SH_I10, 0},
- {0x1f, 0x1f, 0x3ff, 0},
- },
- {
- Rd_rvalueRs_preSI12, 3, &score_df_range[_SIMM12],
- {OP_SH_REGD, OP_SH_REGS1, OP_SH_I12, 0},
- {0xf, 0xf, 0xfff, 0},
- },
- {
- Rd_rvalueRs_postSI12, 3, &score_df_range[_SIMM12],
- {OP_SH_REGD, OP_SH_REGS1, OP_SH_I12, 0},
- {0xf, 0xf, 0xfff, 0},
- },
- {
- Rd_lvalueRs_preSI12, 3, &score_df_range[_SIMM12],
- {OP_SH_REGD, OP_SH_REGS1, OP_SH_I12, 0},
- {0xf, 0xf, 0xfff, 0},
- },
- {
- Rd_lvalueRs_postSI12, 3, &score_df_range[_SIMM12],
- {OP_SH_REGD, OP_SH_REGS1, OP_SH_I12, 0},
- {0xf, 0xf, 0xfff, 0},
- },
- {
- Rd_Rs_SI14, 3, &score_df_range[_SIMM14],
- {OP_SH_REGD, OP_SH_REGS1, OP_SH_I, 0},
- {0x1f, 0x1f, 0x3fff, 0},
- },
- {
- Rd_rvalueRs_SI15, 3, &score_df_range[_SIMM15],
- {OP_SH_REGD, OP_SH_REGS1, OP_SH_RI15, 0},
- {0x1f, 0x1f, 0x7fff, 0},
- },
- {
- Rd_lvalueRs_SI15, 3, &score_df_range[_SIMM15],
- {OP_SH_REGD, OP_SH_REGS1, OP_SH_RI15, 0},
- {0x1f, 0x1f, 0x7fff, 0},
- },
- {
- Rd_SI16, 2, &score_df_range[_SIMM16],
- {OP_SH_REGD, OP_SH_I, 0, 0},
- {0x1f, 0xffff, 0, 0},
- },
- {
- PC_DISP8div2, 1, &score_df_range[_DISP8div2],
- {OP16_SH_DISP8, 0, 0, 0},
- {0xff, 0, 0, 0},
- },
- {
- PC_DISP11div2, 1, &score_df_range[_DISP11div2],
- {OP16_SH_DISP11, 0, 0, 0},
- {0x7ff, 0, 0, 0},
- },
- {
- PC_DISP19div2, 2, &score_df_range[_DISP19div2],
- {OP_SH_DISP19_p1, OP_SH_DISP19_p2, 0, 0},
- {0x3ff, 0x1ff, 0, 0},
- },
- {
- PC_DISP24div2, 1, &score_df_range[_DISP24div2],
- {OP_SH_DISP24, 0, 0, 0},
- {0xffffff, 0, 0, 0},
- },
- {
- Rd_Rs_Rs, 3, NULL,
- {OP_SH_REGD, OP_SH_REGS1, OP_SH_REGS2, 0},
- {0x1f, 0x1f, 0x1f, 0}
- },
- {
- Rd_Rs_x, 2, NULL,
- {OP_SH_REGD, OP_SH_REGS1, 0, 0},
- {0x1f, 0x1f, 0, 0},
- },
- {
- Rd_x_Rs, 2, NULL,
- {OP_SH_REGD, OP_SH_REGS2, 0, 0},
- {0x1f, 0x1f, 0, 0},
- },
- {
- Rd_x_x, 1, NULL,
- {OP_SH_REGD, 0, 0, 0},
- {0x1f, 0, 0, 0},
- },
- {
- x_Rs_Rs, 2, NULL,
- {OP_SH_REGS1, OP_SH_REGS2, 0, 0},
- {0x1f, 0x1f, 0, 0},
- },
- {
- x_Rs_x, 1, NULL,
- {OP_SH_REGS1, 0, 0, 0},
- {0x1f, 0, 0, 0},
- },
- {
- Rd_Rs, 2, NULL,
- {OP16_SH_REGD, OP16_SH_REGS1, 0, 0},
- {0xf, 0xf, 0, 0},
- },
- {
- Rd_HighRs, 2, NULL,
- {OP16_SH_REGD, OP16_SH_REGS1, 0, 0},
- {0xf, 0xf, 0x1f, 0},
- },
- {
- Rd_rvalueRs, 2, NULL,
- {OP16_SH_REGD, OP16_SH_REGS1, 0, 0},
- {0xf, 0xf, 0, 0},
- },
- {
- Rd_lvalueRs, 2, NULL,
- {OP16_SH_REGD, OP16_SH_REGS1, 0, 0},
- {0xf, 0xf, 0, 0}
- },
- {
- Rd_lvalue32Rs, 2, NULL,
- {OP_SH_REGD, OP_SH_REGS1, 0, 0},
- {0x1f, 0x1f, 0, 0},
- },
- {
- Rd_rvalue32Rs, 2, NULL,
- {OP_SH_REGD, OP_SH_REGS1, 0, 0},
- {0x1f, 0x1f, 0, 0},
- },
- {
- x_Rs, 1, NULL,
- {OP16_SH_REGS1, 0, 0, 0},
- {0xf, 0, 0, 0},
- },
- {
- NO_OPD, 0, NULL,
- {0, 0, 0, 0},
- {0, 0, 0, 0},
- },
- {
- NO16_OPD, 0, NULL,
- {0, 0, 0, 0},
- {0, 0, 0, 0},
- },
-};
-
-struct asm_opcode
-{
- /* Instruction name. */
- const char *template;
-
- /* Instruction Opcode. */
- unsigned long value;
-
- /* Instruction bit mask. */
- unsigned long bitmask;
-
- /* Relax instruction opcode. 0x8000 imply no relaxation. */
- unsigned long relax_value;
-
- /* Instruction type. */
- enum score_insn_type type;
-
- /* Function to call to parse args. */
- void (*parms) (char *);
-};
-
enum insn_class
{
INSN_CLASS_16,
INSN_CLASS_32,
+ INSN_CLASS_48,
INSN_CLASS_PCE,
INSN_CLASS_SYN
};
+/* s3_s7: Globals for both tc-score.c and elf32-score.c. */
+extern int score3;
+extern int score7;
+
#endif
diff --git a/external/gpl3/binutils/dist/include/opcode/sparc.h b/external/gpl3/binutils/dist/include/opcode/sparc.h
index 9e238be93a6..0d6511c2a6b 100644
--- a/external/gpl3/binutils/dist/include/opcode/sparc.h
+++ b/external/gpl3/binutils/dist/include/opcode/sparc.h
@@ -1,13 +1,13 @@
/* Definitions for opcode table for the sparc.
Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 2000, 2002,
- 2003, 2005 Free Software Foundation, Inc.
+ 2003, 2005, 2010 Free Software Foundation, Inc.
This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
the GNU Binutils.
GAS/GDB is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2, or (at your option)
+ the Free Software Foundation; either version 3, or (at your option)
any later version.
GAS/GDB is distributed in the hope that it will be useful,
@@ -16,7 +16,7 @@
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
- along with GAS or GDB; see the file COPYING. If not, write to
+ along with GAS or GDB; see the file COPYING3. If not, write to
the Free Software Foundation, 51 Franklin Street - Fifth Floor,
Boston, MA 02110-1301, USA. */
diff --git a/external/gpl3/binutils/dist/include/opcode/spu-insns.h b/external/gpl3/binutils/dist/include/opcode/spu-insns.h
index 237d8ab8105..d6c260aaeef 100644
--- a/external/gpl3/binutils/dist/include/opcode/spu-insns.h
+++ b/external/gpl3/binutils/dist/include/opcode/spu-insns.h
@@ -1,12 +1,12 @@
/* SPU ELF support for BFD.
- Copyright 2006, 2007 Free Software Foundation, Inc.
+ Copyright 2006, 2007, 2010 Free Software Foundation, Inc.
This file is part of BFD, the Binary File Descriptor library.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
+ the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
diff --git a/external/gpl3/binutils/dist/include/opcode/spu.h b/external/gpl3/binutils/dist/include/opcode/spu.h
index 975b1fdde4b..c6468303bc0 100644
--- a/external/gpl3/binutils/dist/include/opcode/spu.h
+++ b/external/gpl3/binutils/dist/include/opcode/spu.h
@@ -1,12 +1,12 @@
/* SPU ELF support for BFD.
- Copyright 2006 Free Software Foundation, Inc.
+ Copyright 2006, 2010 Free Software Foundation, Inc.
This file is part of GDB, GAS, and the GNU binutils.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
+ the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
@@ -18,7 +18,6 @@
along with this program; if not, write to the Free Software Foundation,
Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
-
/* These two enums are from rel_apu/common/spu_asm_format.h */
/* definition of instruction format */
typedef enum {
diff --git a/external/gpl3/binutils/dist/include/opcode/tic30.h b/external/gpl3/binutils/dist/include/opcode/tic30.h
index 198e04e1759..3f4d3071524 100644
--- a/external/gpl3/binutils/dist/include/opcode/tic30.h
+++ b/external/gpl3/binutils/dist/include/opcode/tic30.h
@@ -1,23 +1,23 @@
/* tic30.h -- Header file for TI TMS320C30 opcode table
- Copyright 1998 Free Software Foundation, Inc.
+ Copyright 1998, 2005, 2009, 2010 Free Software Foundation, Inc.
Contributed by Steven Haworth (steve@pm.cse.rmit.edu.au)
-This file is part of GDB, GAS, and the GNU binutils.
+ This file is part of GDB, GAS, and the GNU binutils.
-GDB, GAS, and the GNU binutils are free software; you can redistribute
-them and/or modify them under the terms of the GNU General Public
-License as published by the Free Software Foundation; either version
-1, or (at your option) any later version.
+ GDB, GAS, and the GNU binutils are free software; you can redistribute
+ them and/or modify them under the terms of the GNU General Public
+ License as published by the Free Software Foundation; either version 3,
+ or (at your option) any later version.
-GDB, GAS, and the GNU binutils are distributed in the hope that they
-will be useful, but WITHOUT ANY WARRANTY; without even the implied
-warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
-the GNU General Public License for more details.
+ GDB, GAS, and the GNU binutils are distributed in the hope that they
+ will be useful, but WITHOUT ANY WARRANTY; without even the implied
+ warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
+ the GNU General Public License for more details.
-You should have received a copy of the GNU General Public License
-along with this file; see the file COPYING. If not, write to the Free
-Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
-02110-1301, USA. */
+ You should have received a copy of the GNU General Public License
+ along with this file; see the file COPYING3. If not, write to the Free
+ Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+ 02110-1301, USA. */
/* FIXME: The opcode table should be in opcodes/tic30-opc.c, not in a
header file. */
@@ -241,9 +241,9 @@ typedef struct _template
#define Imm_SInt 2
#define Imm_UInt 3
}
-template;
+insn_template;
-static const template tic30_optab[] = {
+static const insn_template tic30_optab[] = {
{ "absf" ,2,0x00000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
{ "absi" ,2,0x00800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
{ "addc" ,2,0x01000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
@@ -604,7 +604,7 @@ static const template tic30_optab[] = {
{ "" ,0,0x00000000,0, { 0, 0, 0 }, 0 }
};
-static const template *const tic30_optab_end =
+static const insn_template *const tic30_optab_end =
tic30_optab + sizeof(tic30_optab)/sizeof(tic30_optab[0]);
typedef struct {
diff --git a/external/gpl3/binutils/dist/include/opcode/tic4x.h b/external/gpl3/binutils/dist/include/opcode/tic4x.h
index 8830a7df161..6f16fcb404e 100644
--- a/external/gpl3/binutils/dist/include/opcode/tic4x.h
+++ b/external/gpl3/binutils/dist/include/opcode/tic4x.h
@@ -1,12 +1,12 @@
/* Table of opcodes for the Texas Instruments TMS320C[34]X family.
- Copyright (C) 2002, 2003 Free Software Foundation.
+ Copyright (C) 2002, 2003, 2010 Free Software Foundation.
Contributed by Michael P. Hayes (m.hayes@elec.canterbury.ac.nz)
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
+ the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
@@ -16,8 +16,8 @@
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
- Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+ MA 02110-1301, USA. */
#define IS_CPU_TIC3X(v) ((v) == 30 || (v) == 31 || (v) == 32 || (v) == 33)
#define IS_CPU_TIC4X(v) ((v) == 0 || (v) == 40 || (v) == 44)
diff --git a/external/gpl3/binutils/dist/include/opcode/tic54x.h b/external/gpl3/binutils/dist/include/opcode/tic54x.h
index a37ae33a838..f468714eefd 100644
--- a/external/gpl3/binutils/dist/include/opcode/tic54x.h
+++ b/external/gpl3/binutils/dist/include/opcode/tic54x.h
@@ -1,23 +1,23 @@
/* tic54x.h -- Header file for TI TMS320C54X opcode table
- Copyright 1999, 2000, 2001 Free Software Foundation, Inc.
+ Copyright 1999, 2000, 2001, 2005, 2009, 2010 Free Software Foundation, Inc.
Written by Timothy Wall (twall@cygnus.com)
-This file is part of GDB, GAS, and the GNU binutils.
+ This file is part of GDB, GAS, and the GNU binutils.
-GDB, GAS, and the GNU binutils are free software; you can redistribute
-them and/or modify them under the terms of the GNU General Public
-License as published by the Free Software Foundation; either version
-1, or (at your option) any later version.
+ GDB, GAS, and the GNU binutils are free software; you can redistribute
+ them and/or modify them under the terms of the GNU General Public
+ License as published by the Free Software Foundation; either version 3,
+ or (at your option) any later version.
-GDB, GAS, and the GNU binutils are distributed in the hope that they
-will be useful, but WITHOUT ANY WARRANTY; without even the implied
-warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
-the GNU General Public License for more details.
+ GDB, GAS, and the GNU binutils are distributed in the hope that they
+ will be useful, but WITHOUT ANY WARRANTY; without even the implied
+ warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
+ the GNU General Public License for more details.
-You should have received a copy of the GNU General Public License
-along with this file; see the file COPYING. If not, write to the Free
-Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
-02110-1301, USA. */
+ You should have received a copy of the GNU General Public License
+ along with this file; see the file COPYING3. If not, write to the Free
+ Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+ 02110-1301, USA. */
#ifndef _opcode_tic54x_h_
#define _opcode_tic54x_h_
@@ -147,17 +147,17 @@ typedef struct _template
const char* parname;
enum optype paroperand_types[MAX_OPERANDS];
-} template;
+} insn_template;
-extern const template tic54x_unknown_opcode;
-extern const template tic54x_optab[];
-extern const template tic54x_paroptab[];
+extern const insn_template tic54x_unknown_opcode;
+extern const insn_template tic54x_optab[];
+extern const insn_template tic54x_paroptab[];
extern const symbol mmregs[], regs[];
extern const symbol condition_codes[], cc2_codes[], status_bits[];
extern const symbol cc3_codes[];
extern const char *misc_symbols[];
struct disassemble_info;
-extern const template* tic54x_get_insn (struct disassemble_info *,
+extern const insn_template* tic54x_get_insn (struct disassemble_info *,
bfd_vma, unsigned short, int *);
#endif /* _opcode_tic54x_h_ */
diff --git a/external/gpl3/binutils/dist/include/opcode/tic6x-control-registers.h b/external/gpl3/binutils/dist/include/opcode/tic6x-control-registers.h
new file mode 100644
index 00000000000..b4387779aad
--- /dev/null
+++ b/external/gpl3/binutils/dist/include/opcode/tic6x-control-registers.h
@@ -0,0 +1,56 @@
+/* TI C6X control register information.
+ Copyright 2010
+ Free Software Foundation, Inc.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+ MA 02110-1301, USA. */
+
+/* Define the CTRL macro before including this file; it takes as
+ arguments the fields from tic6x_ctrl (defined in tic6x.h). The
+ control register name is given as an identifier; the isa_variants
+ field without the leading TIC6X_INSN_; the rw field without the
+ leading tic6x_rw_. */
+
+CTRL(amr, C62X, read_write, 0x0, 0x10)
+CTRL(csr, C62X, read_write, 0x1, 0x10)
+CTRL(dnum, C64XP, read, 0x11, 0x1f)
+CTRL(ecr, C64XP, write, 0x1d, 0x1f)
+CTRL(efr, C64XP, read, 0x1d, 0x1f)
+CTRL(fadcr, C67X, read_write, 0x12, 0x1f)
+CTRL(faucr, C67X, read_write, 0x13, 0x1f)
+CTRL(fmcr, C67X, read_write, 0x14, 0x1f)
+CTRL(gfpgfr, C64X, read_write, 0x18, 0x1f)
+CTRL(gplya, C64XP, read_write, 0x16, 0x1f)
+CTRL(gplyb, C64XP, read_write, 0x17, 0x1f)
+CTRL(icr, C62X, write, 0x3, 0x10)
+CTRL(ier, C62X, read_write, 0x4, 0x10)
+CTRL(ierr, C64XP, read_write, 0x1f, 0x1f)
+CTRL(ifr, C62X, read, 0x2, 0x1d)
+CTRL(ilc, C64XP, read_write, 0xd, 0x1f)
+CTRL(irp, C62X, read_write, 0x6, 0x10)
+CTRL(isr, C62X, write, 0x2, 0x10)
+CTRL(istp, C62X, read_write, 0x5, 0x10)
+CTRL(itsr, C64XP, read_write, 0x1b, 0x1f)
+CTRL(nrp, C62X, read_write, 0x7, 0x10)
+CTRL(ntsr, C64XP, read_write, 0x1c, 0x1f)
+CTRL(pce1, C62X, read, 0x10, 0xf)
+CTRL(rep, C64XP, read_write, 0xf, 0x1f)
+CTRL(rilc, C64XP, read_write, 0xe, 0x1f)
+CTRL(ssr, C64XP, read_write, 0x15, 0x1f)
+CTRL(tsch, C64XP, read, 0xb, 0x1f)
+/* Contrary to Table 3-26 in SPRUFE8, this register is read-write, as
+ documented in section 2.9.13. */
+CTRL(tscl, C64XP, read_write, 0xa, 0x1f)
+CTRL(tsr, C64XP, read_write, 0x1a, 0x1f)
diff --git a/external/gpl3/binutils/dist/include/opcode/tic6x-insn-formats.h b/external/gpl3/binutils/dist/include/opcode/tic6x-insn-formats.h
new file mode 100644
index 00000000000..8ce2418ec9b
--- /dev/null
+++ b/external/gpl3/binutils/dist/include/opcode/tic6x-insn-formats.h
@@ -0,0 +1,198 @@
+/* TI C6X instruction format information.
+ Copyright 2010
+ Free Software Foundation, Inc.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+ MA 02110-1301, USA. */
+
+/* Define the FMT macro before including this file; it takes a name
+ and the fields from tic6x_insn_format (defined in tic6x.h). */
+
+#define FLD(name, pos, width) { CONCAT2(tic6x_field_,name), (pos), (width) }
+#define CFLDS FLD(p, 0, 1), FLD(creg, 29, 3), FLD(z, 28, 1)
+#define CFLDS2(a, b) 5, { CFLDS, a, b }
+#define CFLDS3(a, b, c) 6, { CFLDS, a, b, c }
+#define CFLDS4(a, b, c, d) 7, { CFLDS, a, b, c, d }
+#define CFLDS5(a, b, c, d, e) 8, { CFLDS, a, b, c, d, e }
+#define CFLDS6(a, b, c, d, e, f) 9, { CFLDS, a, b, c, d, e, f }
+#define CFLDS7(a, b, c, d, e, f, g) 10, { CFLDS, a, b, c, d, e, f, g }
+#define CFLDS8(a, b, c, d, e, f, g, h) 11, { CFLDS, a, b, c, d, e, f, g, h }
+#define NFLDS FLD(p, 0, 1)
+#define NFLDS1(a) 2, { NFLDS, a }
+#define NFLDS2(a, b) 3, { NFLDS, a, b }
+#define NFLDS3(a, b, c) 4, { NFLDS, a, b, c }
+#define NFLDS5(a, b, c, d, e) 6, { NFLDS, a, b, c, d, e }
+#define NFLDS6(a, b, c, d, e, f) 7, { NFLDS, a, b, c, d, e, f }
+#define NFLDS7(a, b, c, d, e, f, g) 8, { NFLDS, a, b, c, d, e, f, g }
+
+/* These are in the order from SPRUFE8, appendices C-H. */
+
+/* Appendix C 32-bit formats. */
+
+FMT(d_1_or_2_src, 32, 0x40, 0x7c,
+ CFLDS5(FLD(s, 1, 1), FLD(op, 7, 6), FLD(src1, 13, 5), FLD(src2, 18, 5),
+ FLD(dst, 23, 5)))
+FMT(d_ext_1_or_2_src, 32, 0x830, 0xc3c,
+ CFLDS6(FLD(s, 1, 1), FLD(op, 6, 4), FLD(x, 12, 1), FLD(src1, 13, 5),
+ FLD(src2, 18, 5), FLD(dst, 23, 5)))
+FMT(d_load_store, 32, 0x4, 0xc,
+ CFLDS8(FLD(s, 1, 1), FLD(op, 4, 3), FLD(y, 7, 1), FLD(r, 8, 1),
+ FLD(mode, 9, 4), FLD(offsetR, 13, 5), FLD(baseR, 18, 5),
+ FLD(srcdst, 23, 5)))
+/* The nonaligned loads and stores have the formats shown in the
+ individual instruction descriptions; the appendix is incorrect. */
+FMT(d_load_nonaligned, 32, 0x124, 0x17c,
+ CFLDS7(FLD(s, 1, 1), FLD(y, 7, 1), FLD(mode, 9, 4), FLD(offsetR, 13, 5),
+ FLD(baseR, 18, 5), FLD(sc, 23, 1), FLD(dst, 24, 4)))
+FMT(d_store_nonaligned, 32, 0x174, 0x17c,
+ CFLDS7(FLD(s, 1, 1), FLD(y, 7, 1), FLD(mode, 9, 4), FLD(offsetR, 13, 5),
+ FLD(baseR, 18, 5), FLD(sc, 23, 1), FLD(src, 24, 4)))
+FMT(d_load_store_long, 32, 0xc, 0xc,
+ CFLDS5(FLD(s, 1, 1), FLD(op, 4, 3), FLD(y, 7, 1), FLD(offsetR, 8, 15),
+ FLD(dst, 23, 5)))
+FMT(d_adda_long, 32, 0x1000000c, 0xf000000c,
+ NFLDS5(FLD(s, 1, 1), FLD(op, 4, 3), FLD(y, 7, 1), FLD(offsetR, 8, 15),
+ FLD(dst, 23, 5)))
+
+/* Appendix C 16-bit formats will go here. */
+
+/* Appendix D 32-bit formats. */
+
+FMT(l_1_or_2_src, 32, 0x18, 0x1c,
+ CFLDS6(FLD(s, 1, 1), FLD(op, 5, 7), FLD(x, 12, 1), FLD(src1, 13, 5),
+ FLD(src2, 18, 5), FLD(dst, 23, 5)))
+FMT(l_1_or_2_src_noncond, 32, 0x10000018, 0xf000001c,
+ NFLDS6(FLD(s, 1, 1), FLD(op, 5, 7), FLD(x, 12, 1), FLD(src1, 13, 5),
+ FLD(src2, 18, 5), FLD(dst, 23, 5)))
+FMT(l_unary, 32, 0x358, 0xffc,
+ CFLDS5(FLD(s, 1, 1), FLD(x, 12, 1), FLD(op, 13, 5), FLD(src2, 18, 5),
+ FLD(dst, 23, 5)))
+
+/* Appendix D 16-bit formats will go here. */
+
+/* Appendix E 32-bit formats. */
+
+FMT(m_compound, 32, 0x30, 0x83c,
+ CFLDS6(FLD(s, 1, 1), FLD(op, 6, 5), FLD(x, 12, 1), FLD(src1, 13, 5),
+ FLD(src2, 18, 5), FLD(dst, 23, 5)))
+FMT(m_1_or_2_src, 32, 0x10000030, 0xf000083c,
+ NFLDS6(FLD(s, 1, 1), FLD(op, 6, 5), FLD(x, 12, 1), FLD(src1, 13, 5),
+ FLD(src2, 18, 5), FLD(dst, 23, 5)))
+/* Contrary to SPRUFE8, this does have predicate fields. */
+FMT(m_unary, 32, 0xf0, 0xffc,
+ CFLDS5(FLD(s, 1, 1), FLD(x, 12, 1), FLD(op, 13, 5), FLD(src2, 18, 5),
+ FLD(dst, 23, 5)))
+
+/* M-unit formats missing from Appendix E. */
+FMT(m_mpy, 32, 0x0, 0x7c,
+ CFLDS6(FLD(s, 1, 1), FLD(op, 7, 5), FLD(x, 12, 1), FLD(src1, 13, 5),
+ FLD(src2, 18, 5), FLD(dst, 23, 5)))
+
+/* Appendix E 16-bit formats will go here. */
+
+/* Appendix F 32-bit formats. */
+
+FMT(s_1_or_2_src, 32, 0x20, 0x3c,
+ CFLDS6(FLD(s, 1, 1), FLD(op, 6, 6), FLD(x, 12, 1), FLD(src1, 13, 5),
+ FLD(src2, 18, 5), FLD(dst, 23 ,5)))
+FMT(s_ext_1_or_2_src, 32, 0xc30, 0xc3c,
+ CFLDS6(FLD(s, 1, 1), FLD(op, 6, 4), FLD(x, 12, 1), FLD(src1, 13, 5),
+ FLD(src2, 18, 5), FLD(dst, 23, 5)))
+FMT(s_ext_1_or_2_src_noncond, 32, 0xc30, 0xe0000c3c,
+ NFLDS7(FLD(s, 1, 1), FLD(op, 6, 4), FLD(x, 12, 1), FLD(src1, 13, 5),
+ FLD(src2, 18, 5), FLD(dst, 23, 5), FLD(z, 28, 1)))
+FMT(s_unary, 32, 0xf20, 0xffc,
+ CFLDS5(FLD(s, 1, 1), FLD(x, 12, 1), FLD(op, 13, 5), FLD(src2, 18, 5),
+ FLD(dst, 23, 5)))
+FMT(s_ext_branch_cond_imm, 32, 0x10, 0x7c,
+ CFLDS2(FLD(s, 1, 1), FLD(cst, 7, 21)))
+FMT(s_call_imm_nop, 32, 0x10, 0xe000007c,
+ NFLDS3(FLD(s, 1, 1), FLD(cst, 7, 21), FLD(z, 28, 1)))
+FMT(s_branch_nop_cst, 32, 0x120, 0x1ffc,
+ CFLDS3(FLD(s, 1, 1), FLD(src1, 13, 3), FLD(src2, 16, 12)))
+FMT(s_branch_nop_reg, 32, 0x800360, 0xf830ffc,
+ CFLDS4(FLD(s, 1, 1), FLD(x, 12, 1), FLD(src1, 13, 3), FLD(src2, 18, 5)))
+FMT(s_branch, 32, 0x360, 0xf83effc,
+ CFLDS3(FLD(s, 1, 1), FLD(x, 12, 1), FLD(src2, 18, 5)))
+FMT(s_mvk, 32, 0x28, 0x3c,
+ CFLDS4(FLD(s, 1, 1), FLD(h, 6, 1), FLD(cst, 7, 16), FLD(dst, 23, 5)))
+FMT(s_field, 32, 0x8, 0x3c,
+ CFLDS6(FLD(s, 1, 1), FLD(op, 6, 2), FLD(cstb, 8, 5), FLD(csta, 13, 5),
+ FLD(src2, 18, 5), FLD(dst, 23, 5)))
+
+/* S-unit formats missing from Appendix F. */
+FMT(s_addk, 32, 0x50, 0x7c,
+ CFLDS3(FLD(s, 1, 1), FLD(cst, 7, 16), FLD(dst, 23, 5)))
+FMT(s_addkpc, 32, 0x160, 0x1ffc,
+ CFLDS4(FLD(s, 1, 1), FLD(src2, 13, 3), FLD(src1, 16, 7), FLD(dst, 23, 5)))
+FMT(s_b_irp, 32, 0x1800e0, 0x7feffc,
+ CFLDS3(FLD(s, 1, 1), FLD(x, 12, 1), FLD(dst, 23, 5)))
+FMT(s_b_nrp, 32, 0x1c00e0, 0x7feffc,
+ CFLDS3(FLD(s, 1, 1), FLD(x, 12, 1), FLD(dst, 23, 5)))
+FMT(s_bdec, 32, 0x1020, 0x1ffc,
+ CFLDS3(FLD(s, 1, 1), FLD(src, 13, 10), FLD(dst, 23, 5)))
+FMT(s_bpos, 32, 0x20, 0x1ffc,
+ CFLDS3(FLD(s, 1, 1), FLD(src, 13, 10), FLD(dst, 23, 5)))
+
+/* Appendix F 16-bit formats will go here. */
+
+/* Appendix G 16-bit formats will go here. */
+
+/* Appendix H 32-bit formats. */
+
+FMT(nfu_loop_buffer, 32, 0x00020000, 0x00021ffc,
+ CFLDS4(FLD(s, 1, 1), FLD(op, 13, 4), FLD(csta, 18, 5), FLD(cstb, 23, 5)))
+/* Corrected relative to Appendix H. */
+FMT(nfu_nop_idle, 32, 0x00000000, 0xfffe1ffc,
+ NFLDS2(FLD(s, 1, 1), FLD(op, 13, 4)))
+
+/* No-unit formats missing from Appendix H (given the NOP and IDLE
+ correction). */
+FMT(nfu_dint, 32, 0x10004000, 0xfffffffc,
+ NFLDS1(FLD(s, 1, 1)))
+FMT(nfu_rint, 32, 0x10006000, 0xfffffffc,
+ NFLDS1(FLD(s, 1, 1)))
+FMT(nfu_swe, 32, 0x10000000, 0xfffffffc,
+ NFLDS1(FLD(s, 1, 1)))
+FMT(nfu_swenr, 32, 0x10002000, 0xfffffffc,
+ NFLDS1(FLD(s, 1, 1)))
+/* Although formally covered by the loop buffer format, the fields in
+ that format are not useful for all such instructions and not all
+ instructions can be predicated. */
+FMT(nfu_spkernel, 32, 0x00034000, 0xf03ffffc,
+ NFLDS2(FLD(s, 1, 1), FLD(fstgfcyc, 22, 6)))
+FMT(nfu_spkernelr, 32, 0x00036000, 0xfffffffc,
+ NFLDS1(FLD(s, 1, 1)))
+FMT(nfu_spmask, 32, 0x00020000, 0xfc021ffc,
+ NFLDS3(FLD(s, 1, 1), FLD(op, 13, 4), FLD(mask, 18, 8)))
+
+/* Appendix H 16-bit formats will go here. */
+
+#undef FLD
+#undef CFLDS
+#undef CFLDS2
+#undef CFLDS3
+#undef CFLDS4
+#undef CFLDS5
+#undef CFLDS6
+#undef CFLDS7
+#undef CFLDS8
+#undef NFLDS
+#undef NFLDS1
+#undef NFLDS2
+#undef NFLDS3
+#undef NFLDS5
+#undef NFLDS6
+#undef NFLDS7
diff --git a/external/gpl3/binutils/dist/include/opcode/tic6x-opcode-table.h b/external/gpl3/binutils/dist/include/opcode/tic6x-opcode-table.h
new file mode 100644
index 00000000000..5bd8f175cd8
--- /dev/null
+++ b/external/gpl3/binutils/dist/include/opcode/tic6x-opcode-table.h
@@ -0,0 +1,2549 @@
+/* TI C6X opcode table.
+ Copyright 2010
+ Free Software Foundation, Inc.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+ MA 02110-1301, USA. */
+
+/* Define the INSN macro before including this file; it takes as
+ arguments the fields from tic6x_opcode (defined in tic6x.h). The
+ name is given as an identifier; the subsequent four operands should
+ have "tic6x_func_unit_", "tic6x_insn_format_", "tic6x_pipeline_"
+ and "TIC6X_INSN_", respectively, prepended to them by the macro
+ definition. Also define INSNE, which has a second argument that
+ goes after tic6x_opcode_NAME_ to form the enumeration value for
+ this instruction, where the value otherwise formed from the name,
+ functional unit and format is ambiguous, but otherwise has the same
+ arguments as INSN. */
+
+#define TIC6X_INSN_C64X_AND_C67X TIC6X_INSN_C64X|TIC6X_INSN_C67X
+#define tic6x_insn_format_nfu_s_branch_nop_cst \
+ tic6x_insn_format_s_branch_nop_cst
+#define tic6x_insn_format_s_l_1_or_2_src tic6x_insn_format_l_1_or_2_src
+#define RAN(id, min, max) { CONCAT2(tic6x_field_,id), (min), (max) }
+#define FIX(id, val) RAN(id, val, val)
+#define FIX0() 0, { { 0, 0, 0 } }
+#define FIX1(a) 1, { a }
+#define FIX2(a, b) 2, { a, b }
+#define FIX3(a, b, c) 3, { a, b, c }
+#define FIX4(a, b, c, d) 4, { a, b, c, d }
+#define OP0() 0, { { 0, 0, FALSE, 0, 0, 0, 0 } }
+#define OP1(a) 1, { a }
+#define OP2(a, b) 2, { a, b }
+#define OP3(a, b, c) 3, { a, b, c }
+#define OP4(a, b, c, d) 4, { a, b, c, d }
+#define OACST { tic6x_operand_asm_const, 0, tic6x_rw_none, 0, 0, 0, 0 }
+#define OLCST { tic6x_operand_link_const, 0, tic6x_rw_none, 0, 0, 0, 0 }
+#define OFULIST { tic6x_operand_func_unit, 0, tic6x_rw_none, 0, 0, 0, 0 }
+#define ORIRP1 { tic6x_operand_irp, 4, tic6x_rw_read, 1, 1, 0, 0 }
+#define ORNRP1 { tic6x_operand_nrp, 4, tic6x_rw_read, 1, 1, 0, 0 }
+#define OWREG1 { tic6x_operand_reg, 4, tic6x_rw_write, 1, 1, 0, 0 }
+#define OWRETREG1 { tic6x_operand_retreg, 4, tic6x_rw_write, 1, 1, 0, 0 }
+#define ORREG1 { tic6x_operand_reg, 4, tic6x_rw_read, 1, 1, 0, 0 }
+#define ORDREG1 { tic6x_operand_dreg, 4, tic6x_rw_read, 1, 1, 0, 0 }
+#define ORWREG1 { tic6x_operand_reg, 4, tic6x_rw_read_write, 1, 1, 0, 0 }
+#define ORAREG1 { tic6x_operand_areg, 4, tic6x_rw_read, 1, 1, 0, 0 }
+#define ORXREG1 { tic6x_operand_xreg, 4, tic6x_rw_read, 1, 1, 0, 0 }
+#define ORREG12 { tic6x_operand_reg, 4, tic6x_rw_read, 1, 2, 0, 0 }
+#define ORREG14 { tic6x_operand_reg, 4, tic6x_rw_read, 1, 4, 0, 0 }
+#define ORXREG14 { tic6x_operand_xreg, 4, tic6x_rw_read, 1, 4, 0, 0 }
+#define OWREG2 { tic6x_operand_reg, 4, tic6x_rw_write, 2, 2, 0, 0 }
+#define OWREG4 { tic6x_operand_reg, 4, tic6x_rw_write, 4, 4, 0, 0 }
+#define OWREG9 { tic6x_operand_reg, 4, tic6x_rw_write, 9, 9, 0, 0 }
+#define OWDREG5 { tic6x_operand_dreg, 4, tic6x_rw_write, 5, 5, 0, 0 }
+#define OWREGL1 { tic6x_operand_regpair, 5, tic6x_rw_write, 1, 1, 1, 1 }
+#define ORREGL1 { tic6x_operand_regpair, 5, tic6x_rw_read, 1, 1, 1, 1 }
+#define OWREGD1 { tic6x_operand_regpair, 8, tic6x_rw_write, 1, 1, 1, 1 }
+#define OWREGD12 { tic6x_operand_regpair, 8, tic6x_rw_write, 1, 1, 2, 2 }
+#define OWREGD4 { tic6x_operand_regpair, 8, tic6x_rw_write, 4, 4, 4, 4 }
+#define ORREGD1 { tic6x_operand_regpair, 8, tic6x_rw_read, 1, 1, 1, 1 }
+#define OWREGD45 { tic6x_operand_regpair, 8, tic6x_rw_write, 4, 4, 5, 5 }
+#define OWREGD67 { tic6x_operand_regpair, 8, tic6x_rw_write, 6, 6, 7, 7 }
+#define ORDREGD1 { tic6x_operand_dregpair, 8, tic6x_rw_read, 1, 1, 1, 1 }
+#define OWDREGD5 { tic6x_operand_dregpair, 8, tic6x_rw_write, 5, 5, 5, 5 }
+#define ORREGD12 { tic6x_operand_regpair, 8, tic6x_rw_read, 1, 1, 2, 2 }
+#define ORXREGD12 { tic6x_operand_xregpair, 8, tic6x_rw_read, 1, 1, 2, 2 }
+#define ORREGD1234 { tic6x_operand_regpair, 8, tic6x_rw_read, 1, 2, 3, 4 }
+#define ORREGD1324 { tic6x_operand_regpair, 8, tic6x_rw_read, 1, 3, 2, 4 }
+#define OWREGD910 { tic6x_operand_regpair, 8, tic6x_rw_write, 9, 9, 10, 10 }
+#define ORCREG1 { tic6x_operand_ctrl, 4, tic6x_rw_read, 1, 1, 0, 0 }
+#define OWCREG1 { tic6x_operand_ctrl, 4, tic6x_rw_write, 1, 1, 0, 0 }
+#define ORMEMDW { tic6x_operand_mem_deref, 4, tic6x_rw_read, 3, 3, 0, 0 }
+#define OWMEMDW { tic6x_operand_mem_deref, 4, tic6x_rw_write, 3, 3, 0, 0 }
+#define ORMEMSB { tic6x_operand_mem_short, 1, tic6x_rw_read, 3, 3, 0, 0 }
+#define OWMEMSB { tic6x_operand_mem_short, 1, tic6x_rw_write, 3, 3, 0, 0 }
+#define ORMEMLB { tic6x_operand_mem_long, 1, tic6x_rw_read, 3, 3, 0, 0 }
+#define OWMEMLB { tic6x_operand_mem_long, 1, tic6x_rw_write, 3, 3, 0, 0 }
+#define ORMEMSH { tic6x_operand_mem_short, 2, tic6x_rw_read, 3, 3, 0, 0 }
+#define OWMEMSH { tic6x_operand_mem_short, 2, tic6x_rw_write, 3, 3, 0, 0 }
+#define ORMEMLH { tic6x_operand_mem_long, 2, tic6x_rw_read, 3, 3, 0, 0 }
+#define OWMEMLH { tic6x_operand_mem_long, 2, tic6x_rw_write, 3, 3, 0, 0 }
+#define ORMEMSW { tic6x_operand_mem_short, 4, tic6x_rw_read, 3, 3, 0, 0 }
+#define OWMEMSW { tic6x_operand_mem_short, 4, tic6x_rw_write, 3, 3, 0, 0 }
+#define ORMEMLW { tic6x_operand_mem_long, 4, tic6x_rw_read, 3, 3, 0, 0 }
+#define OWMEMLW { tic6x_operand_mem_long, 4, tic6x_rw_write, 3, 3, 0, 0 }
+#define ORMEMSD { tic6x_operand_mem_short, 8, tic6x_rw_read, 3, 3, 0, 0 }
+#define OWMEMSD { tic6x_operand_mem_short, 8, tic6x_rw_write, 3, 3, 0, 0 }
+#define ORMEMND { tic6x_operand_mem_ndw, 8, tic6x_rw_read, 3, 3, 0, 0 }
+#define OWMEMND { tic6x_operand_mem_ndw, 8, tic6x_rw_write, 3, 3, 0, 0 }
+#define ENC(id, meth, op) { \
+ CONCAT2(tic6x_field_,id), \
+ CONCAT2(tic6x_coding_,meth), \
+ op \
+ }
+#define ENC0() 0, { { 0, 0, 0 } }
+#define ENC1(a) 1, { a }
+#define ENC2(a, b) 2, { a, b }
+#define ENC3(a, b, c) 3, { a, b, c }
+#define ENC4(a, b, c, d) 4, { a, b, c, d }
+#define ENC5(a, b, c, d, e) 5, { a, b, c, d, e }
+#define ENC6(a, b, c, d, e, f) 6, { a, b, c, d, e, f }
+#define ENC7(a, b, c, d, e, f, g) 7, { a, b, c, d, e, f, g }
+
+INSN(abs, l, unary, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0)),
+ OP2(ORXREG1, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(dst, reg, 1)))
+INSN(abs, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+ FIX3(FIX(op, 0x38), FIX(x, 0), FIX(src1, 0)),
+ OP2(ORREGL1, OWREGL1),
+ ENC3(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(dst, reg, 1)))
+
+INSN(abs2, l, unary, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x4)),
+ OP2(ORXREG1, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(dst, reg, 1)))
+
+INSN(absdp, s, 1_or_2_src, 2cycle_dp, C67X, TIC6X_FLAG_NO_CROSS,
+ FIX3(FIX(op, 0x2c), FIX(x, 0), FIX(src1, 0)),
+ OP2(ORREGD1, OWREGD12),
+ ENC3(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(dst, reg, 1)))
+
+INSN(abssp, s, unary, 1cycle, C67X, 0,
+ FIX1(FIX(op, 0)),
+ OP2(ORXREG1, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(dst, reg, 1)))
+
+INSNE(add, l_si_xsi_si, l, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x3)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(add, l_si_xsi_sl, l, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x23)),
+ OP3(ORREG1, ORXREG1, OWREGL1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(add, l_xsi_sl_sl, l, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x21)),
+ OP3(ORXREG1, ORREGL1, OWREGL1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(add, l_s5_xsi_si, l, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x2)),
+ OP3(OACST, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(add, l_s5_sl_sl, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+ FIX2(FIX(op, 0x20), FIX(x, 0)),
+ OP3(OACST, ORREGL1, OWREGL1),
+ ENC4(ENC(s, fu, 0), ENC(src1, scst, 0), ENC(src2, reg, 1),
+ ENC(dst, reg, 2)))
+INSNE(add, s_si_xsi_si, s, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x7)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(add, s_s5_xsi_si, s, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x6)),
+ OP3(OACST, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(add, d_si_si_si, d, 1_or_2_src, 1cycle, C62X,
+ TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1),
+ FIX1(FIX(op, 0x10)),
+ OP3(ORREG1, ORREG1, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, reg, 1),
+ ENC(dst, reg, 2)))
+INSNE(add, d_si_u5_si, d, 1_or_2_src, 1cycle, C62X,
+ TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1),
+ FIX1(FIX(op, 0x12)),
+ OP3(ORREG1, OACST, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1),
+ ENC(dst, reg, 2)))
+INSNE(add, d_si_xsi_si, d, ext_1_or_2_src, 1cycle, C64X, TIC6X_FLAG_PREFER(0),
+ FIX1(FIX(op, 0xa)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(add, d_xsi_s5_si, d, ext_1_or_2_src, 1cycle, C64X, TIC6X_FLAG_PREFER(0),
+ FIX1(FIX(op, 0xb)),
+ OP3(ORXREG1, OACST, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(src1, scst, 1), ENC(dst, reg, 2)))
+
+INSNE(addab, d_si_si_si, d, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+ FIX1(FIX(op, 0x30)),
+ OP3(ORREG1, ORREG1, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, reg, 1),
+ ENC(dst, reg, 2)))
+INSNE(addab, d_si_u5_si, d, 1_or_2_src, 1cycle, C62X,
+ TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1),
+ FIX1(FIX(op, 0x32)),
+ OP3(ORREG1, OACST, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1),
+ ENC(dst, reg, 2)))
+INSN(addab, d, adda_long, 1cycle, C64XP, TIC6X_FLAG_PREFER(0),
+ FIX1(FIX(op, 3)),
+ OP3(ORAREG1, OLCST, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(y, areg, 0), ENC(offsetR, ulcst_dpr_byte, 1),
+ ENC(dst, reg, 2)))
+
+INSNE(addad, d_si_si_si, d, 1_or_2_src, 1cycle, C64X_AND_C67X,
+ TIC6X_FLAG_NO_CROSS,
+ FIX1(FIX(op, 0x3c)),
+ OP3(ORREG1, ORREG1, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, reg, 1),
+ ENC(dst, reg, 2)))
+INSNE(addad, d_si_u5_si, d, 1_or_2_src, 1cycle, C64X_AND_C67X,
+ TIC6X_FLAG_NO_CROSS,
+ FIX1(FIX(op, 0x3d)),
+ OP3(ORREG1, OACST, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1),
+ ENC(dst, reg, 2)))
+
+INSNE(addah, d_si_si_si, d, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+ FIX1(FIX(op, 0x34)),
+ OP3(ORREG1, ORREG1, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, reg, 1),
+ ENC(dst, reg, 2)))
+INSNE(addah, d_si_u5_si, d, 1_or_2_src, 1cycle, C62X,
+ TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1),
+ FIX1(FIX(op, 0x36)),
+ OP3(ORREG1, OACST, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1),
+ ENC(dst, reg, 2)))
+INSN(addah, d, adda_long, 1cycle, C64XP, TIC6X_FLAG_PREFER(0),
+ FIX1(FIX(op, 5)),
+ OP3(ORAREG1, OLCST, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(y, areg, 0), ENC(offsetR, ulcst_dpr_half, 1),
+ ENC(dst, reg, 2)))
+
+INSNE(addaw, d_si_si_si, d, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+ FIX1(FIX(op, 0x38)),
+ OP3(ORREG1, ORREG1, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, reg, 1),
+ ENC(dst, reg, 2)))
+INSNE(addaw, d_si_u5_si, d, 1_or_2_src, 1cycle, C62X,
+ TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1),
+ FIX1(FIX(op, 0x3a)),
+ OP3(ORREG1, OACST, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1),
+ ENC(dst, reg, 2)))
+INSN(addaw, d, adda_long, 1cycle, C64XP, TIC6X_FLAG_PREFER(0),
+ FIX1(FIX(op, 7)),
+ OP3(ORAREG1, OLCST, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(y, areg, 0), ENC(offsetR, ulcst_dpr_word, 1),
+ ENC(dst, reg, 2)))
+
+INSN(adddp, l, 1_or_2_src, addsubdp, C67X, 0,
+ FIX1(FIX(op, 0x18)),
+ OP3(ORREGD12, ORXREGD12, OWREGD67),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSN(adddp, s, l_1_or_2_src, addsubdp, C67XP, 0,
+ FIX1(FIX(op, 0x72)),
+ OP3(ORREGD12, ORXREGD12, OWREGD67),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(addk, s, addk, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+ FIX0(),
+ OP2(OLCST, OWREG1),
+ ENC3(ENC(s, fu, 0), ENC(cst, scst, 0), ENC(dst, reg, 1)))
+
+INSN(addkpc, s, addkpc, 1cycle, C64X,
+ TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MCNOP|TIC6X_FLAG_SIDE_B_ONLY,
+ FIX1(FIX(s, 1)),
+ OP3(OLCST, OWREG1, OACST),
+ ENC3(ENC(src1, pcrel, 0), ENC(dst, reg, 1), ENC(src2, ucst, 2)))
+
+INSN(addsp, l, 1_or_2_src, 4cycle, C67X, 0,
+ FIX1(FIX(op, 0x10)),
+ OP3(ORREG1, ORXREG1, OWREG4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSN(addsp, s, l_1_or_2_src, 4cycle, C67XP, 0,
+ FIX1(FIX(op, 0x70)),
+ OP3(ORREG1, ORXREG1, OWREG4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(addsub, l, 1_or_2_src_noncond, 1cycle, C64XP, 0,
+ FIX1(FIX(op, 0xc)),
+ OP3(ORREG1, ORXREG1, OWREGD1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(addsub2, l, 1_or_2_src_noncond, 1cycle, C64XP, 0,
+ FIX1(FIX(op, 0xd)),
+ OP3(ORREG1, ORXREG1, OWREGD1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSNE(addu, l_ui_xui_ul, l, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x2b)),
+ OP3(ORREG1, ORXREG1, OWREGL1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(addu, l_xui_ul_ul, l, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x29)),
+ OP3(ORXREG1, ORREGL1, OWREGL1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(add2, s, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x1)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSN(add2, l, 1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x5)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSN(add2, d, ext_1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x4)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(add4, l, 1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x65)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSNE(and, l_ui_xui_ui, l, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x7b)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(and, l_s5_xui_ui, l, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x7a)),
+ OP3(OACST, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(and, s_ui_xui_ui, s, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x1f)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(and, s_s5_xui_ui, s, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x1e)),
+ OP3(OACST, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(and, d_ui_xui_ui, d, ext_1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x6)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(and, d_s5_xui_ui, d, ext_1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x7)),
+ OP3(OACST, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(andn, l, 1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x7c)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSN(andn, s, ext_1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x6)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSN(andn, d, ext_1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x0)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(avg2, m, compound, 1616_m, C64X, 0,
+ FIX1(FIX(op, 0x13)),
+ OP3(ORREG1, ORXREG1, OWREG2),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(avgu4, m, compound, 1616_m, C64X, 0,
+ FIX1(FIX(op, 0x12)),
+ OP3(ORREG1, ORXREG1, OWREG2),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(b, s, ext_branch_cond_imm, branch, C62X, TIC6X_FLAG_NO_CROSS,
+ FIX0(),
+ OP1(OLCST),
+ ENC2(ENC(s, fu, 0), ENC(cst, pcrel, 0)))
+INSN(b, s, branch, branch, C62X, TIC6X_FLAG_SIDE_B_ONLY,
+ FIX1(FIX(s, 1)),
+ OP1(ORXREG1),
+ ENC2(ENC(x, xpath, 0), ENC(src2, reg, 0)))
+INSN(b, s, b_irp, branch, C62X, TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY,
+ FIX3(FIX(s, 1), FIX(x, 0), FIX(dst, 0)),
+ OP1(ORIRP1),
+ ENC0())
+INSN(b, s, b_nrp, branch, C62X, TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY,
+ FIX3(FIX(s, 1), FIX(x, 0), FIX(dst, 0)),
+ OP1(ORNRP1),
+ ENC0())
+
+INSN(bdec, s, bdec, branch, C64X, TIC6X_FLAG_NO_CROSS,
+ FIX0(),
+ OP2(OLCST, ORWREG1),
+ ENC3(ENC(s, fu, 0), ENC(src, pcrel, 0), ENC(dst, reg, 1)))
+
+INSN(bitc4, m, unary, 1616_m, C64X, 0,
+ FIX1(FIX(op, 0x1e)),
+ OP2(ORXREG1, OWREG2),
+ ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(dst, reg, 1)))
+
+INSN(bitr, m, unary, 1616_m, C64X, 0,
+ FIX1(FIX(op, 0x1f)),
+ OP2(ORXREG1, OWREG2),
+ ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(dst, reg, 1)))
+
+INSN(bnop, s, branch_nop_cst, branch, C64X,
+ TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MCNOP,
+ FIX0(),
+ OP2(OLCST, OACST),
+ ENC3(ENC(s, fu, 0), ENC(src2, pcrel, 0), ENC(src1, ucst, 1)))
+INSN(bnop, nfu, s_branch_nop_cst, branch, C64XP,
+ TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO|TIC6X_FLAG_MCNOP,
+ FIX1(FIX(s, 0)),
+ OP2(OLCST, OACST),
+ ENC2(ENC(src2, pcrel, 0), ENC(src1, ucst, 1)))
+INSN(bnop, s, branch_nop_reg, branch, C64X,
+ TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_MCNOP,
+ FIX1(FIX(s, 1)),
+ OP2(ORXREG1, OACST),
+ ENC3(ENC(x, xpath, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1)))
+
+INSN(bpos, s, bpos, branch, C64X, TIC6X_FLAG_NO_CROSS,
+ FIX0(),
+ OP2(OLCST, ORREG1),
+ ENC3(ENC(s, fu, 0), ENC(src, pcrel, 0), ENC(dst, reg, 1)))
+
+INSN(call, s, ext_branch_cond_imm, branch, C62X,
+ TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO|TIC6X_FLAG_CALL,
+ FIX0(),
+ OP1(OLCST),
+ ENC2(ENC(s, fu, 0), ENC(cst, pcrel, 0)))
+INSN(call, s, branch, branch, C62X,
+ TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_MACRO|TIC6X_FLAG_CALL,
+ FIX1(FIX(s, 1)),
+ OP1(ORXREG1),
+ ENC2(ENC(x, xpath, 0), ENC(src2, reg, 0)))
+INSN(call, s, b_irp, branch, C62X,
+ TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_MACRO|TIC6X_FLAG_CALL,
+ FIX3(FIX(s, 1), FIX(x, 0), FIX(dst, 0)),
+ OP1(ORIRP1),
+ ENC0())
+INSN(call, s, b_nrp, branch, C62X,
+ TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_MACRO|TIC6X_FLAG_CALL,
+ FIX3(FIX(s, 1), FIX(x, 0), FIX(dst, 0)),
+ OP1(ORNRP1),
+ ENC0())
+
+INSN(callnop, s, branch_nop_cst, branch, C64X,
+ TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO|TIC6X_FLAG_MCNOP|TIC6X_FLAG_CALL,
+ FIX0(),
+ OP2(OLCST, OACST),
+ ENC3(ENC(s, fu, 0), ENC(src2, pcrel, 0), ENC(src1, ucst, 1)))
+INSN(callnop, nfu, s_branch_nop_cst, branch, C64XP,
+ TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO|TIC6X_FLAG_MCNOP|TIC6X_FLAG_CALL,
+ FIX1(FIX(s, 0)),
+ OP2(OLCST, OACST),
+ ENC2(ENC(src2, pcrel, 0), ENC(src1, ucst, 1)))
+INSN(callnop, s, branch_nop_reg, branch, C64X,
+ TIC6X_FLAG_MACRO|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_MCNOP|TIC6X_FLAG_CALL,
+ FIX1(FIX(s, 1)),
+ OP2(ORXREG1, OACST),
+ ENC3(ENC(x, xpath, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1)))
+
+INSN(callp, s, call_imm_nop, branch, C64XP,
+ TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MCNOP,
+ FIX1(FIX(z, 1)),
+ OP2(OLCST, OWRETREG1),
+ ENC2(ENC(s, fu, 0), ENC(cst, pcrel, 0)))
+
+INSN(callret, s, ext_branch_cond_imm, branch, C62X,
+ TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO|TIC6X_FLAG_CALL|TIC6X_FLAG_RETURN,
+ FIX0(),
+ OP1(OLCST),
+ ENC2(ENC(s, fu, 0), ENC(cst, pcrel, 0)))
+INSN(callret, s, branch, branch, C62X,
+ TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_MACRO|TIC6X_FLAG_CALL|TIC6X_FLAG_RETURN,
+ FIX1(FIX(s, 1)),
+ OP1(ORXREG1),
+ ENC2(ENC(x, xpath, 0), ENC(src2, reg, 0)))
+INSN(callret, s, b_irp, branch, C62X,
+ TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_MACRO|TIC6X_FLAG_CALL|TIC6X_FLAG_RETURN,
+ FIX3(FIX(s, 1), FIX(x, 0), FIX(dst, 0)),
+ OP1(ORIRP1),
+ ENC0())
+INSN(callret, s, b_nrp, branch, C62X,
+ TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_MACRO|TIC6X_FLAG_CALL|TIC6X_FLAG_RETURN,
+ FIX3(FIX(s, 1), FIX(x, 0), FIX(dst, 0)),
+ OP1(ORNRP1),
+ ENC0())
+
+INSN(clr, s, field, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+ FIX1(FIX(op, 0x3)),
+ OP4(ORREG1, OACST, OACST, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(csta, ucst, 1),
+ ENC(cstb, ucst, 2), ENC(dst, reg, 3)))
+INSN(clr, s, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x3f)),
+ OP3(ORXREG1, ORREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(src1, reg, 1), ENC(dst, reg, 2)))
+
+INSNE(cmpeq, l_si_xsi_ui, l, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x53)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(cmpeq, l_s5_xsi_ui, l, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x52)),
+ OP3(OACST, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(cmpeq, l_xsi_sl_ui, l, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x51)),
+ OP3(ORXREG1, ORREGL1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(cmpeq, l_s5_sl_ui, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+ FIX2(FIX(op, 0x50), FIX(x, 0)),
+ OP3(OACST, ORREGL1, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(src1, scst, 0), ENC(src2, reg, 1),
+ ENC(dst, reg, 2)))
+
+INSN(cmpeq2, s, 1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x1d)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(cmpeq4, s, 1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x1c)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(cmpeqdp, s, 1_or_2_src, dpcmp, C67X, 0,
+ FIX1(FIX(op, 0x28)),
+ OP3(ORREGD12, ORXREGD12, OWREG2),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(cmpeqsp, s, 1_or_2_src, 1cycle, C67X, 0,
+ FIX1(FIX(op, 0x38)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSNE(cmpgt, l_si_xsi_ui, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_PREFER(1),
+ FIX1(FIX(op, 0x47)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(cmpgt, l_s5_xsi_ui, l, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x46)),
+ OP3(OACST, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(cmpgt, l_xsi_sl_ui, l, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x45)),
+ OP3(ORXREG1, ORREGL1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(cmpgt, l_s5_sl_ui, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+ FIX2(FIX(op, 0x44), FIX(x, 0)),
+ OP3(OACST, ORREGL1, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(src1, scst, 0), ENC(src2, reg, 1),
+ ENC(dst, reg, 2)))
+INSNE(cmpgt, l_xsi_si_ui, l, 1_or_2_src, 1cycle, C62X,
+ TIC6X_FLAG_MACRO|TIC6X_FLAG_PREFER(0),
+ FIX1(FIX(op, 0x57)),
+ OP3(ORXREG1, ORREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 1),
+ ENC(src2, reg, 0), ENC(dst, reg, 2)))
+INSNE(cmpgt, l_xsi_s5_ui, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_MACRO,
+ FIX1(FIX(op, 0x56)),
+ OP3(ORXREG1, OACST, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 1),
+ ENC(src2, reg, 0), ENC(dst, reg, 2)))
+INSNE(cmpgt, l_sl_xsi_ui, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_MACRO,
+ FIX1(FIX(op, 0x55)),
+ OP3(ORREGL1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 1),
+ ENC(src2, reg, 0), ENC(dst, reg, 2)))
+INSNE(cmpgt, l_sl_s5_ui, l, 1_or_2_src, 1cycle, C62X,
+ TIC6X_FLAG_MACRO|TIC6X_FLAG_NO_CROSS,
+ FIX2(FIX(op, 0x54), FIX(x, 0)),
+ OP3(ORREGL1, OACST, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(src1, scst, 1), ENC(src2, reg, 0),
+ ENC(dst, reg, 2)))
+
+INSN(cmpgt2, s, 1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x14)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(cmpgtdp, s, 1_or_2_src, dpcmp, C67X, 0,
+ FIX1(FIX(op, 0x29)),
+ OP3(ORREGD12, ORXREGD12, OWREG2),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(cmpgtsp, s, 1_or_2_src, 1cycle, C67X, 0,
+ FIX1(FIX(op, 0x39)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSNE(cmpgtu, l_ui_xui_ui, l, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x4f)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(cmpgtu, l_u4_xui_ui, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_PREFER(1),
+ FIX2(FIX(op, 0x4e), RAN(src1, 0, 15)),
+ OP3(OACST, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, ucst, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+/* Although not mentioned in SPRUFE8, CMPGTU and CMPLTU support a
+ 5-bit unsigned constant operand on C64X and above. */
+INSNE(cmpgtu, l_u5_xui_ui, l, 1_or_2_src, 1cycle, C64X, 0,
+ FIX2(FIX(op, 0x4e), RAN(src1, 16, 31)),
+ OP3(OACST, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, ucst, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(cmpgtu, l_xui_ul_ui, l, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x4d)),
+ OP3(ORXREG1, ORREGL1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(cmpgtu, l_u4_ul_ui, l, 1_or_2_src, 1cycle, C62X,
+ TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1),
+ FIX3(FIX(op, 0x4c), FIX(x, 0), RAN(src1, 0, 15)),
+ OP3(OACST, ORREGL1, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(src1, ucst, 0), ENC(src2, reg, 1),
+ ENC(dst, reg, 2)))
+INSNE(cmpgtu, l_u5_ul_ui, l, 1_or_2_src, 1cycle, C64X, TIC6X_FLAG_NO_CROSS,
+ FIX3(FIX(op, 0x4c), FIX(x, 0), RAN(src1, 16, 31)),
+ OP3(OACST, ORREGL1, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(src1, ucst, 0), ENC(src2, reg, 1),
+ ENC(dst, reg, 2)))
+
+INSN(cmpgtu4, s, 1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x15)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSNE(cmplt, l_si_xsi_ui, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_PREFER(1),
+ FIX1(FIX(op, 0x57)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(cmplt, l_s5_xsi_ui, l, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x56)),
+ OP3(OACST, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(cmplt, l_xsi_sl_ui, l, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x55)),
+ OP3(ORXREG1, ORREGL1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(cmplt, l_s5_sl_ui, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+ FIX2(FIX(op, 0x54), FIX(x, 0)),
+ OP3(OACST, ORREGL1, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(src1, scst, 0), ENC(src2, reg, 1),
+ ENC(dst, reg, 2)))
+INSNE(cmplt, l_xsi_si_ui, l, 1_or_2_src, 1cycle, C62X,
+ TIC6X_FLAG_MACRO|TIC6X_FLAG_PREFER(0),
+ FIX1(FIX(op, 0x47)),
+ OP3(ORXREG1, ORREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 1),
+ ENC(src2, reg, 0), ENC(dst, reg, 2)))
+INSNE(cmplt, l_xsi_s5_ui, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_MACRO,
+ FIX1(FIX(op, 0x46)),
+ OP3(ORXREG1, OACST, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 1),
+ ENC(src2, reg, 0), ENC(dst, reg, 2)))
+INSNE(cmplt, l_sl_xsi_ui, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_MACRO,
+ FIX1(FIX(op, 0x45)),
+ OP3(ORREGL1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 1),
+ ENC(src2, reg, 0), ENC(dst, reg, 2)))
+INSNE(cmplt, l_sl_s5_ui, l, 1_or_2_src, 1cycle, C62X,
+ TIC6X_FLAG_MACRO|TIC6X_FLAG_NO_CROSS,
+ FIX2(FIX(op, 0x44), FIX(x, 0)),
+ OP3(ORREGL1, OACST, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(src1, scst, 1), ENC(src2, reg, 0),
+ ENC(dst, reg, 2)))
+
+INSN(cmplt2, s, 1_or_2_src, 1cycle, C64X, TIC6X_FLAG_MACRO,
+ FIX1(FIX(op, 0x14)),
+ OP3(ORXREG1, ORREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(src1, reg, 1), ENC(dst, reg, 2)))
+
+INSN(cmpltdp, s, 1_or_2_src, dpcmp, C67X, 0,
+ FIX1(FIX(op, 0x2a)),
+ OP3(ORREGD12, ORXREGD12, OWREG2),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(cmpltsp, s, 1_or_2_src, 1cycle, C67X, 0,
+ FIX1(FIX(op, 0x3a)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSNE(cmpltu, l_ui_xui_ui, l, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x5f)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(cmpltu, l_u4_xui_ui, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_PREFER(1),
+ FIX2(FIX(op, 0x5e), RAN(src1, 0, 15)),
+ OP3(OACST, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, ucst, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(cmpltu, l_u5_xui_ui, l, 1_or_2_src, 1cycle, C64X, 0,
+ FIX2(FIX(op, 0x5e), RAN(src1, 16, 31)),
+ OP3(OACST, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, ucst, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(cmpltu, l_xui_ul_ui, l, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x5d)),
+ OP3(ORXREG1, ORREGL1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(cmpltu, l_u4_ul_ui, l, 1_or_2_src, 1cycle, C62X,
+ TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1),
+ FIX3(FIX(op, 0x5c), FIX(x, 0), RAN(src1, 0, 15)),
+ OP3(OACST, ORREGL1, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(src1, ucst, 0), ENC(src2, reg, 1),
+ ENC(dst, reg, 2)))
+INSNE(cmpltu, l_u5_ul_ui, l, 1_or_2_src, 1cycle, C64X, TIC6X_FLAG_NO_CROSS,
+ FIX3(FIX(op, 0x5c), FIX(x, 0), RAN(src1, 16, 31)),
+ OP3(OACST, ORREGL1, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(src1, ucst, 0), ENC(src2, reg, 1),
+ ENC(dst, reg, 2)))
+
+INSN(cmpltu4, s, 1_or_2_src, 1cycle, C64X, TIC6X_FLAG_MACRO,
+ FIX1(FIX(op, 0x15)),
+ OP3(ORXREG1, ORREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(src1, reg, 1), ENC(dst, reg, 2)))
+
+INSN(cmpy, m, 1_or_2_src, 4cycle, C64XP, 0,
+ FIX1(FIX(op, 0xa)),
+ OP3(ORREG1, ORXREG1, OWREGD4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(cmpyr, m, 1_or_2_src, 4cycle, C64XP, 0,
+ FIX1(FIX(op, 0xb)),
+ OP3(ORREG1, ORXREG1, OWREG4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(cmpyr1, m, 1_or_2_src, 4cycle, C64XP, 0,
+ FIX1(FIX(op, 0xc)),
+ OP3(ORREG1, ORXREG1, OWREG4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(cmtl, d, 1_or_2_src, load, ATOMIC,
+ TIC6X_FLAG_LOAD|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_SIDE_T2_ONLY|TIC6X_FLAG_NO_CROSS,
+ FIX3(FIX(s, 1), FIX(op, 0xe), FIX(src1, 0)),
+ OP2(ORMEMDW, OWDREG5),
+ ENC2(ENC(src2, reg, 0), ENC(dst, reg, 1)))
+
+INSN(ddotp4, m, 1_or_2_src, 4cycle, C64XP, 0,
+ FIX1(FIX(op, 0x18)),
+ OP3(ORREG1, ORXREG1, OWREGD4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(ddotph2, m, 1_or_2_src, 4cycle, C64XP, 0,
+ FIX1(FIX(op, 0x17)),
+ OP3(ORREGD1, ORXREG1, OWREGD4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(ddotph2r, m, 1_or_2_src, 4cycle, C64XP, 0,
+ FIX1(FIX(op, 0x15)),
+ OP3(ORREGD1, ORXREG1, OWREG4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(ddotpl2, m, 1_or_2_src, 4cycle, C64XP, 0,
+ FIX1(FIX(op, 0x16)),
+ OP3(ORREGD1, ORXREG1, OWREGD4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(ddotpl2r, m, 1_or_2_src, 4cycle, C64XP, 0,
+ FIX1(FIX(op, 0x14)),
+ OP3(ORREGD1, ORXREG1, OWREG4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(deal, m, unary, 1616_m, C64X, 0,
+ FIX1(FIX(op, 0x1d)),
+ OP2(ORXREG1, OWREG2),
+ ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(dst, reg, 1)))
+
+INSN(dint, nfu, dint, 1cycle, C64XP, 0,
+ FIX1(FIX(s, 0)),
+ OP0(),
+ ENC0())
+
+INSN(dmv, s, ext_1_or_2_src, 1cycle, C64XP, 0,
+ FIX1(FIX(op, 0xb)),
+ OP3(ORREG1, ORXREG1, OWREGD1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSNE(dotp2, m_s2_xs2_si, m, compound, 4cycle, C64X, 0,
+ FIX1(FIX(op, 0xc)),
+ OP3(ORREG1, ORXREG1, OWREG4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(dotp2, m_s2_xs2_sll, m, compound, 4cycle, C64X, 0,
+ FIX1(FIX(op, 0xb)),
+ OP3(ORREG1, ORXREG1, OWREGD4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(dotpn2, m, compound, 4cycle, C64X, 0,
+ FIX1(FIX(op, 0x9)),
+ OP3(ORREG1, ORXREG1, OWREG4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(dotpnrsu2, m, compound, 4cycle, C64X, 0,
+ FIX1(FIX(op, 0x7)),
+ OP3(ORREG1, ORXREG1, OWREG4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(dotpnrus2, m, compound, 4cycle, C64X, TIC6X_FLAG_MACRO,
+ FIX1(FIX(op, 0x7)),
+ OP3(ORXREG1, ORREG1, OWREG4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(src1, reg, 1), ENC(dst, reg, 2)))
+
+INSN(dotprsu2, m, compound, 4cycle, C64X, 0,
+ FIX1(FIX(op, 0xd)),
+ OP3(ORREG1, ORXREG1, OWREG4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(dotprus2, m, compound, 4cycle, C64X, TIC6X_FLAG_MACRO,
+ FIX1(FIX(op, 0xd)),
+ OP3(ORXREG1, ORREG1, OWREG4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(src1, reg, 1), ENC(dst, reg, 2)))
+
+INSN(dotpsu4, m, compound, 4cycle, C64X, 0,
+ FIX1(FIX(op, 0x2)),
+ OP3(ORREG1, ORXREG1, OWREG4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(dotpus4, m, compound, 4cycle, C64X, TIC6X_FLAG_MACRO,
+ FIX1(FIX(op, 0x2)),
+ OP3(ORXREG1, ORREG1, OWREG4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(src1, reg, 1), ENC(dst, reg, 2)))
+
+INSN(dotpu4, m, compound, 4cycle, C64X, 0,
+ FIX1(FIX(op, 0x6)),
+ OP3(ORREG1, ORXREG1, OWREG4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(dpack2, l, 1_or_2_src_noncond, 1cycle, C64XP, 0,
+ FIX1(FIX(op, 0x34)),
+ OP3(ORREG1, ORXREG1, OWREGD1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(dpackx2, l, 1_or_2_src_noncond, 1cycle, C64XP, 0,
+ FIX1(FIX(op, 0x33)),
+ OP3(ORREG1, ORXREG1, OWREGD1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(dpint, l, 1_or_2_src, 4cycle, C67X, TIC6X_FLAG_NO_CROSS,
+ FIX3(FIX(op, 0x8), FIX(x, 0), FIX(src1, 0)),
+ OP2(ORREGD1, OWREG4),
+ ENC3(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(dst, reg, 1)))
+
+INSN(dpsp, l, 1_or_2_src, 4cycle, C67X, TIC6X_FLAG_NO_CROSS,
+ FIX3(FIX(op, 0x9), FIX(x, 0), FIX(src1, 0)),
+ OP2(ORREGD1, OWREG4),
+ ENC3(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(dst, reg, 1)))
+
+INSN(dptrunc, l, 1_or_2_src, 4cycle, C67X, TIC6X_FLAG_NO_CROSS,
+ FIX3(FIX(op, 0x1), FIX(x, 0), FIX(src1, 0)),
+ OP2(ORREGD1, OWREG4),
+ ENC3(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(dst, reg, 1)))
+
+INSN(ext, s, field, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+ FIX1(FIX(op, 0x1)),
+ OP4(ORREG1, OACST, OACST, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(csta, ucst, 1),
+ ENC(cstb, ucst, 2), ENC(dst, reg, 3)))
+INSN(ext, s, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x2f)),
+ OP3(ORXREG1, ORREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(src1, reg, 1), ENC(dst, reg, 2)))
+
+INSN(extu, s, field, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+ FIX1(FIX(op, 0x0)),
+ OP4(ORREG1, OACST, OACST, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(csta, ucst, 1),
+ ENC(cstb, ucst, 2), ENC(dst, reg, 3)))
+INSN(extu, s, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x2b)),
+ OP3(ORXREG1, ORREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(src1, reg, 1), ENC(dst, reg, 2)))
+
+INSN(gmpy, m, 1_or_2_src, 4cycle, C64XP, TIC6X_FLAG_NO_CROSS,
+ FIX2(FIX(op, 0x1f), FIX(x, 0)),
+ OP3(ORREG1, ORREG1, OWREG4),
+ ENC4(ENC(s, fu, 0), ENC(src1, reg, 0), ENC(src2, reg, 1),
+ ENC(dst, reg, 2)))
+
+/* This instruction can be predicated as usual; SPRUFE8 is incorrect
+ where it shows the "z" field as fixed to 1. */
+INSN(gmpy4, m, compound, 4cycle, C64X, 0,
+ FIX1(FIX(op, 0x11)),
+ OP3(ORREG1, ORXREG1, OWREG4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(idle, nfu, nop_idle, nop, C62X, TIC6X_FLAG_MCNOP,
+ FIX2(FIX(s, 0), FIX(op, 0xf)),
+ OP0(),
+ ENC0())
+
+INSN(intdp, l, 1_or_2_src, intdp, C67X, 0,
+ FIX2(FIX(op, 0x39), FIX(src1, 0)),
+ OP2(ORXREG1, OWREGD45),
+ ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(dst, reg, 1)))
+
+INSN(intdpu, l, 1_or_2_src, intdp, C67X, 0,
+ FIX2(FIX(op, 0x3b), FIX(src1, 0)),
+ OP2(ORXREG1, OWREGD45),
+ ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(dst, reg, 1)))
+
+INSN(intsp, l, 1_or_2_src, 4cycle, C67X, 0,
+ FIX2(FIX(op, 0x4a), FIX(src1, 0)),
+ OP2(ORXREG1, OWREG4),
+ ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(dst, reg, 1)))
+
+INSN(intspu, l, 1_or_2_src, 4cycle, C67X, 0,
+ FIX2(FIX(op, 0x49), FIX(src1, 0)),
+ OP2(ORXREG1, OWREG4),
+ ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(dst, reg, 1)))
+
+INSN(ldb, d, load_store, load, C62X,
+ TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1),
+ FIX2(FIX(op, 2), FIX(r, 0)),
+ OP2(ORMEMSB, OWDREG5),
+ ENC6(ENC(s, data_fu, 0), ENC(y, fu, 0), ENC(mode, mem_mode, 0),
+ ENC(offsetR, mem_offset, 0), ENC(baseR, reg, 0),
+ ENC(srcdst, reg, 1)))
+INSN(ldb, d, load_store_long, load, C62X,
+ TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_PREFER(0),
+ FIX1(FIX(op, 2)),
+ OP2(ORMEMLB, OWDREG5),
+ ENC4(ENC(s, data_fu, 0), ENC(y, areg, 0), ENC(offsetR, ulcst_dpr_byte, 0),
+ ENC(dst, reg, 1)))
+
+INSN(ldbu, d, load_store, load, C62X,
+ TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1),
+ FIX2(FIX(op, 1), FIX(r, 0)),
+ OP2(ORMEMSB, OWDREG5),
+ ENC6(ENC(s, data_fu, 0), ENC(y, fu, 0), ENC(mode, mem_mode, 0),
+ ENC(offsetR, mem_offset, 0), ENC(baseR, reg, 0),
+ ENC(srcdst, reg, 1)))
+INSN(ldbu, d, load_store_long, load, C62X,
+ TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_PREFER(0),
+ FIX1(FIX(op, 1)),
+ OP2(ORMEMLB, OWDREG5),
+ ENC4(ENC(s, data_fu, 0), ENC(y, areg, 0), ENC(offsetR, ulcst_dpr_byte, 0),
+ ENC(dst, reg, 1)))
+
+INSN(lddw, d, load_store, load, C64X_AND_C67X,
+ TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS,
+ FIX2(FIX(op, 6), FIX(r, 1)),
+ OP2(ORMEMSD, OWDREGD5),
+ ENC6(ENC(s, data_fu, 0), ENC(y, fu, 0), ENC(mode, mem_mode, 0),
+ ENC(offsetR, mem_offset, 0), ENC(baseR, reg, 0),
+ ENC(srcdst, reg, 1)))
+
+INSN(ldh, d, load_store, load, C62X,
+ TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1),
+ FIX2(FIX(op, 4), FIX(r, 0)),
+ OP2(ORMEMSH, OWDREG5),
+ ENC6(ENC(s, data_fu, 0), ENC(y, fu, 0), ENC(mode, mem_mode, 0),
+ ENC(offsetR, mem_offset, 0), ENC(baseR, reg, 0),
+ ENC(srcdst, reg, 1)))
+INSN(ldh, d, load_store_long, load, C62X,
+ TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_PREFER(0),
+ FIX1(FIX(op, 4)),
+ OP2(ORMEMLH, OWDREG5),
+ ENC4(ENC(s, data_fu, 0), ENC(y, areg, 0), ENC(offsetR, ulcst_dpr_half, 0),
+ ENC(dst, reg, 1)))
+
+INSN(ldhu, d, load_store, load, C62X,
+ TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1),
+ FIX2(FIX(op, 0), FIX(r, 0)),
+ OP2(ORMEMSH, OWDREG5),
+ ENC6(ENC(s, data_fu, 0), ENC(y, fu, 0), ENC(mode, mem_mode, 0),
+ ENC(offsetR, mem_offset, 0), ENC(baseR, reg, 0),
+ ENC(srcdst, reg, 1)))
+INSN(ldhu, d, load_store_long, load, C62X,
+ TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_PREFER(0),
+ FIX1(FIX(op, 0)),
+ OP2(ORMEMLH, OWDREG5),
+ ENC4(ENC(s, data_fu, 0), ENC(y, areg, 0), ENC(offsetR, ulcst_dpr_half, 0),
+ ENC(dst, reg, 1)))
+
+INSN(ldndw, d, load_nonaligned, load, C64X,
+ TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_UNALIGNED,
+ FIX0(),
+ OP2(ORMEMND, OWDREGD5),
+ ENC7(ENC(s, data_fu, 0), ENC(y, fu, 0), ENC(mode, mem_mode, 0),
+ ENC(offsetR, mem_offset_noscale, 0), ENC(baseR, reg, 0),
+ ENC(sc, scaled, 0), ENC(dst, reg_shift, 1)))
+
+INSN(ldnw, d, load_store, load, C64X,
+ TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_UNALIGNED,
+ FIX2(FIX(op, 3), FIX(r, 1)),
+ OP2(ORMEMSW, OWDREG5),
+ ENC6(ENC(s, data_fu, 0), ENC(y, fu, 0), ENC(mode, mem_mode, 0),
+ ENC(offsetR, mem_offset, 0), ENC(baseR, reg, 0),
+ ENC(srcdst, reg, 1)))
+
+INSN(ldw, d, load_store, load, C62X,
+ TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1),
+ FIX2(FIX(op, 6), FIX(r, 0)),
+ OP2(ORMEMSW, OWDREG5),
+ ENC6(ENC(s, data_fu, 0), ENC(y, fu, 0), ENC(mode, mem_mode, 0),
+ ENC(offsetR, mem_offset, 0), ENC(baseR, reg, 0),
+ ENC(srcdst, reg, 1)))
+INSN(ldw, d, load_store_long, load, C62X,
+ TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_PREFER(0),
+ FIX1(FIX(op, 6)),
+ OP2(ORMEMLW, OWDREG5),
+ ENC4(ENC(s, data_fu, 0), ENC(y, areg, 0), ENC(offsetR, ulcst_dpr_word, 0),
+ ENC(dst, reg, 1)))
+
+INSN(ll, d, 1_or_2_src, load, ATOMIC,
+ TIC6X_FLAG_LOAD|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_SIDE_T2_ONLY|TIC6X_FLAG_NO_CROSS,
+ FIX3(FIX(s, 1), FIX(op, 0xc), FIX(src1, 0)),
+ OP2(ORMEMDW, OWDREG5),
+ ENC2(ENC(src2, reg, 0), ENC(dst, reg, 1)))
+
+INSNE(lmbd, l_ui_xui_ui, l, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x6b)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(lmbd, l_s5_xui_ui, l, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x6a)),
+ OP3(OACST, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(max2, l, 1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x42)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSN(max2, s, ext_1_or_2_src, 1cycle, C64XP, 0,
+ FIX1(FIX(op, 0xd)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(maxu4, l, 1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x43)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(min2, l, 1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x41)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSN(min2, s, ext_1_or_2_src, 1cycle, C64XP, 0,
+ FIX1(FIX(op, 0xc)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(minu4, l, 1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x48)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSNE(mpy, m_sl16_xsl16_si, m, mpy, 1616_m, C62X, 0,
+ FIX1(FIX(op, 0x19)),
+ OP3(ORREG1, ORXREG1, OWREG2),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(mpy, m_s5_xsl16_si, m, mpy, 1616_m, C62X, 0,
+ FIX1(FIX(op, 0x18)),
+ OP3(OACST, ORXREG1, OWREG2),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpydp, m, mpy, mpydp, C67X, TIC6X_FLAG_NO_CROSS,
+ FIX2(FIX(op, 0x0e), FIX(x, 0)),
+ OP3(ORREGD1234, ORREGD1324, OWREGD910),
+ ENC4(ENC(s, fu, 0), ENC(src1, reg, 0), ENC(src2, reg, 1),
+ ENC(dst, reg, 2)))
+
+INSN(mpyh, m, mpy, 1616_m, C62X, 0,
+ FIX1(FIX(op, 0x01)),
+ OP3(ORREG1, ORXREG1, OWREG2),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpyhi, m, compound, 4cycle, C64X, 0,
+ FIX1(FIX(op, 0x14)),
+ OP3(ORREG1, ORXREG1, OWREGD4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpyhir, m, compound, 4cycle, C64X, 0,
+ FIX1(FIX(op, 0x10)),
+ OP3(ORREG1, ORXREG1, OWREG4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpyhl, m, mpy, 1616_m, C62X, 0,
+ FIX1(FIX(op, 0x09)),
+ OP3(ORREG1, ORXREG1, OWREG2),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpyhlu, m, mpy, 1616_m, C62X, 0,
+ FIX1(FIX(op, 0x0f)),
+ OP3(ORREG1, ORXREG1, OWREG2),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpyhslu, m, mpy, 1616_m, C62X, 0,
+ FIX1(FIX(op, 0x0b)),
+ OP3(ORREG1, ORXREG1, OWREG2),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpyhsu, m, mpy, 1616_m, C62X, 0,
+ FIX1(FIX(op, 0x03)),
+ OP3(ORREG1, ORXREG1, OWREG2),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpyhu, m, mpy, 1616_m, C62X, 0,
+ FIX1(FIX(op, 0x07)),
+ OP3(ORREG1, ORXREG1, OWREG2),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpyhuls, m, mpy, 1616_m, C62X, 0,
+ FIX1(FIX(op, 0x0d)),
+ OP3(ORREG1, ORXREG1, OWREG2),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpyhus, m, mpy, 1616_m, C62X, 0,
+ FIX1(FIX(op, 0x05)),
+ OP3(ORREG1, ORXREG1, OWREG2),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSNE(mpyi, m_si_xsi_si, m, mpy, mpyi, C67X, 0,
+ FIX1(FIX(op, 0x04)),
+ OP3(ORREG14, ORXREG14, OWREG9),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(mpyi, m_s5_xsi_si, m, mpy, mpyi, C67X, 0,
+ FIX1(FIX(op, 0x06)),
+ OP3(OACST, ORXREG14, OWREG9),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSNE(mpyid, m_si_xsi_sll, m, mpy, mpyid, C67X, 0,
+ FIX1(FIX(op, 0x08)),
+ OP3(ORREG14, ORXREG14, OWREGD910),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(mpyid, m_s5_xsi_sll, m, mpy, mpyid, C67X, 0,
+ FIX1(FIX(op, 0x0c)),
+ OP3(OACST, ORXREG14, OWREGD910),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpyih, m, compound, 4cycle, C64X, TIC6X_FLAG_MACRO,
+ FIX1(FIX(op, 0x14)),
+ OP3(ORXREG1, ORREG1, OWREGD4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(src1, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpyihr, m, compound, 4cycle, C64X, TIC6X_FLAG_MACRO,
+ FIX1(FIX(op, 0x10)),
+ OP3(ORXREG1, ORREG1, OWREG4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(src1, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpyil, m, compound, 4cycle, C64X, TIC6X_FLAG_MACRO,
+ FIX1(FIX(op, 0x15)),
+ OP3(ORXREG1, ORREG1, OWREGD4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(src1, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpyilr, m, compound, 4cycle, C64X, TIC6X_FLAG_MACRO,
+ FIX1(FIX(op, 0x0e)),
+ OP3(ORXREG1, ORREG1, OWREG4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(src1, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpylh, m, mpy, 1616_m, C62X, 0,
+ FIX1(FIX(op, 0x11)),
+ OP3(ORREG1, ORXREG1, OWREG2),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpylhu, m, mpy, 1616_m, C62X, 0,
+ FIX1(FIX(op, 0x17)),
+ OP3(ORREG1, ORXREG1, OWREG2),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpyli, m, compound, 4cycle, C64X, 0,
+ FIX1(FIX(op, 0x15)),
+ OP3(ORREG1, ORXREG1, OWREGD4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpylir, m, compound, 4cycle, C64X, 0,
+ FIX1(FIX(op, 0x0e)),
+ OP3(ORREG1, ORXREG1, OWREG4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpylshu, m, mpy, 1616_m, C62X, 0,
+ FIX1(FIX(op, 0x13)),
+ OP3(ORREG1, ORXREG1, OWREG2),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpyluhs, m, mpy, 1616_m, C62X, 0,
+ FIX1(FIX(op, 0x15)),
+ OP3(ORREG1, ORXREG1, OWREG2),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpysp, m, mpy, 4cycle, C67X, 0,
+ FIX1(FIX(op, 0x1c)),
+ OP3(ORREG1, ORXREG1, OWREG4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+/* Contrary to SPRU733A, MPYSPDP and MPYSP2DP are on both C67X and
+ C67X+. */
+INSN(mpyspdp, m, compound, mpyspdp, C67X, 0,
+ FIX1(FIX(op, 0x16)),
+ OP3(ORREG12, ORXREGD12, OWREGD67),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpysp2dp, m, compound, mpyspdp, C67X, 0,
+ FIX1(FIX(op, 0x17)),
+ OP3(ORREG1, ORXREG1, OWREGD45),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSNE(mpysu, m_sl16_xul16_si, m, mpy, 1616_m, C62X, 0,
+ FIX1(FIX(op, 0x1b)),
+ OP3(ORREG1, ORXREG1, OWREG2),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(mpysu, m_s5_xul16_si, m, mpy, 1616_m, C62X, 0,
+ FIX1(FIX(op, 0x1e)),
+ OP3(OACST, ORXREG1, OWREG2),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpysu4, m, compound, 4cycle, C64X, 0,
+ FIX1(FIX(op, 0x05)),
+ OP3(ORREG1, ORXREG1, OWREGD4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpyu, m, mpy, 1616_m, C62X, 0,
+ FIX1(FIX(op, 0x1f)),
+ OP3(ORREG1, ORXREG1, OWREG2),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpyu4, m, compound, 4cycle, C64X, 0,
+ FIX1(FIX(op, 0x04)),
+ OP3(ORREG1, ORXREG1, OWREGD4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpyus, m, mpy, 1616_m, C62X, 0,
+ FIX1(FIX(op, 0x1d)),
+ OP3(ORREG1, ORXREG1, OWREG2),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpyus4, m, compound, 4cycle, C64X, TIC6X_FLAG_MACRO,
+ FIX1(FIX(op, 0x05)),
+ OP3(ORXREG1, ORREG1, OWREGD4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(src1, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpy2, m, compound, 4cycle, C64X, 0,
+ FIX1(FIX(op, 0x00)),
+ OP3(ORREG1, ORXREG1, OWREGD4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpy2ir, m, 1_or_2_src, 4cycle, C64XP, 0,
+ FIX1(FIX(op, 0x0f)),
+ OP3(ORREG1, ORXREG1, OWREGD4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSNE(mpy32, 32_32_32, m, mpy, 4cycle, C64XP, 0,
+ FIX1(FIX(op, 0x10)),
+ OP3(ORREG1, ORXREG1, OWREG4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(mpy32, 32_32_64, m, mpy, 4cycle, C64XP, 0,
+ FIX1(FIX(op, 0x14)),
+ OP3(ORREG1, ORXREG1, OWREGD4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpy32su, m, mpy, 4cycle, C64XP, 0,
+ FIX1(FIX(op, 0x16)),
+ OP3(ORREG1, ORXREG1, OWREGD4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpy32u, m, compound, 4cycle, C64XP, 0,
+ FIX1(FIX(op, 0x18)),
+ OP3(ORREG1, ORXREG1, OWREGD4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpy32us, m, compound, 4cycle, C64XP, 0,
+ FIX1(FIX(op, 0x19)),
+ OP3(ORREG1, ORXREG1, OWREGD4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+/* "or" forms of "mv" are preferred over "add" forms when available
+ because "or" uses less power. However, 40-bit moves are only
+ available through "add", and before C64X D-unit moves are only
+ available through "add" (without cross paths being available). */
+INSNE(mv, l_xui_ui, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_MACRO,
+ FIX2(FIX(op, 0x7e), FIX(src1, 0)),
+ OP2(ORXREG1, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(dst, reg, 1)))
+INSNE(mv, l_sl_sl, l, 1_or_2_src, 1cycle, C62X,
+ TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO,
+ FIX3(FIX(op, 0x20), FIX(x, 0), FIX(src1, 0)),
+ OP2(ORREGL1, OWREGL1),
+ ENC3(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(dst, reg, 1)))
+INSNE(mv, s_xui_ui, s, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_MACRO,
+ FIX2(FIX(op, 0x1a), FIX(src1, 0)),
+ OP2(ORXREG1, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(dst, reg, 1)))
+INSNE(mv, d_si_si, d, 1_or_2_src, 1cycle, C62X,
+ TIC6X_FLAG_MACRO|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(0),
+ FIX2(FIX(op, 0x12), FIX(src1, 0)),
+ OP2(ORREG1, OWREG1),
+ ENC3(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(dst, reg, 1)))
+INSNE(mv, d_xui_ui, d, ext_1_or_2_src, 1cycle, C64X,
+ TIC6X_FLAG_MACRO|TIC6X_FLAG_PREFER(1),
+ FIX2(FIX(op, 0x3), FIX(src1, 0)),
+ OP2(ORXREG1, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(dst, reg, 1)))
+
+INSNE(mvc, from_cr, s, 1_or_2_src, 1cycle, C62X,
+ TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_NO_CROSS,
+ FIX3(FIX(s, 1), FIX(op, 0x0f), FIX(x, 0)),
+ OP2(ORCREG1, OWREG1),
+ ENC3(ENC(src1, crhi, 0), ENC(src2, crlo, 0), ENC(dst, reg, 1)))
+INSNE(mvc, to_cr, s, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_SIDE_B_ONLY,
+ FIX2(FIX(s, 1), FIX(op, 0x0e)),
+ OP2(ORXREG1, OWCREG1),
+ ENC4(ENC(x, xpath, 0), ENC(src2, reg, 0), ENC(src1, crhi, 1),
+ ENC(dst, crlo, 1)))
+
+INSN(mvd, m, unary, 4cycle, C64X, 0,
+ FIX1(FIX(op, 0x1a)),
+ OP2(ORXREG1, OWREG4),
+ ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(dst, reg, 1)))
+
+INSN(mvk, s, mvk, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+ FIX1(FIX(h, 0)),
+ OP2(OLCST, OWREG1),
+ ENC3(ENC(s, fu, 0), ENC(cst, scst, 0), ENC(dst, reg, 1)))
+INSN(mvk, l, unary, 1cycle, C64X, TIC6X_FLAG_NO_CROSS,
+ FIX2(FIX(x, 0), FIX(op, 0x05)),
+ OP2(OACST, OWREG1),
+ ENC3(ENC(s, fu, 0), ENC(src2, scst, 0), ENC(dst, reg, 1)))
+INSN(mvk, d, 1_or_2_src, 1cycle, C64X, TIC6X_FLAG_NO_CROSS,
+ FIX2(FIX(op, 0x00), FIX(src2, 0)),
+ OP2(OACST, OWREG1),
+ ENC3(ENC(s, fu, 0), ENC(src1, scst, 0), ENC(dst, reg, 1)))
+
+INSN(mvkh, s, mvk, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+ FIX1(FIX(h, 1)),
+ OP2(OLCST, OWREG1),
+ ENC3(ENC(s, fu, 0), ENC(cst, lcst_high16, 0), ENC(dst, reg, 1)))
+
+INSN(mvklh, s, mvk, 1cycle, C62X, TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO,
+ FIX1(FIX(h, 1)),
+ OP2(OLCST, OWREG1),
+ ENC3(ENC(s, fu, 0), ENC(cst, lcst_low16, 0), ENC(dst, reg, 1)))
+
+INSN(mvkl, s, mvk, 1cycle, C62X, TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO,
+ FIX1(FIX(h, 0)),
+ OP2(OLCST, OWREG1),
+ ENC3(ENC(s, fu, 0), ENC(cst, lcst_low16, 0), ENC(dst, reg, 1)))
+
+INSNE(neg, s_xsi_si, s, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_MACRO,
+ FIX2(FIX(op, 0x16), FIX(src1, 0)),
+ OP2(ORXREG1, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(dst, reg, 1)))
+INSNE(neg, l_xsi_si, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_MACRO,
+ FIX2(FIX(op, 0x06), FIX(src1, 0)),
+ OP2(ORXREG1, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(dst, reg, 1)))
+INSNE(neg, l_sl_sl, l, 1_or_2_src, 1cycle, C62X,
+ TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO,
+ FIX2(FIX(op, 0x24), FIX(src1, 0)),
+ OP2(ORREGL1, OWREGL1),
+ ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(dst, reg, 1)))
+
+INSN(nop, nfu, nop_idle, nop, C62X, 0,
+ FIX2(FIX(s, 0), RAN(op, 0, 8)),
+ OP1(OACST),
+ ENC1(ENC(op, ucst_minus_one, 0)))
+INSNE(nop, 1, nfu, nop_idle, nop, C62X, TIC6X_FLAG_MACRO,
+ FIX2(FIX(s, 0), FIX(op, 0)),
+ OP0(),
+ ENC0())
+
+INSNE(norm, l_xsi_ui, l, 1_or_2_src, 1cycle, C62X, 0,
+ FIX2(FIX(op, 0x63), FIX(src1, 0)),
+ OP2(ORXREG1, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(dst, reg, 1)))
+INSNE(norm, l_sl_ui, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+ FIX3(FIX(op, 0x60), FIX(x, 0), FIX(src1, 0)),
+ OP2(ORREGL1, OWREG1),
+ ENC3(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(dst, reg, 1)))
+
+INSN(not, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_MACRO,
+ FIX2(FIX(op, 0x6e), FIX(src1, 0x1f)),
+ OP2(ORXREG1, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(dst, reg, 1)))
+INSN(not, s, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_MACRO,
+ FIX2(FIX(op, 0x0a), FIX(src1, 0x1f)),
+ OP2(ORXREG1, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(dst, reg, 1)))
+INSN(not, d, ext_1_or_2_src, 1cycle, C64X, TIC6X_FLAG_MACRO,
+ FIX2(FIX(op, 0xf), FIX(src1, 0x1f)),
+ OP2(ORXREG1, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(dst, reg, 1)))
+
+INSNE(or, d_ui_xui_ui, d, ext_1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x2)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(or, d_s5_xui_ui, d, ext_1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x3)),
+ OP3(OACST, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(or, l_ui_xui_ui, l, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x7f)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(or, l_s5_xui_ui, l, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x7e)),
+ OP3(OACST, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(or, s_ui_xui_ui, s, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x1b)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(or, s_s5_xui_ui, s, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x1a)),
+ OP3(OACST, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(pack2, l, 1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x0)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSN(pack2, s, ext_1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0xf)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(packh2, l, 1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x1e)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSN(packh2, s, 1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x9)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(packh4, l, 1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x69)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(packhl2, l, 1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x1c)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSN(packhl2, s, 1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x8)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(packlh2, l, 1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x1b)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSN(packlh2, s, 1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x10)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(packl4, l, 1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x68)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(rcpdp, s, 1_or_2_src, 2cycle_dp, C67X, TIC6X_FLAG_NO_CROSS,
+ FIX3(FIX(op, 0x2d), FIX(x, 0), FIX(src1, 0)),
+ OP2(ORREGD1, OWREGD12),
+ ENC3(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(dst, reg, 1)))
+
+INSN(rcpsp, s, 1_or_2_src, 1cycle, C67X, 0,
+ FIX2(FIX(op, 0x3d), FIX(src1, 0)),
+ OP2(ORXREG1, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(dst, reg, 1)))
+
+INSN(ret, s, ext_branch_cond_imm, branch, C62X,
+ TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO|TIC6X_FLAG_RETURN,
+ FIX0(),
+ OP1(OLCST),
+ ENC2(ENC(s, fu, 0), ENC(cst, pcrel, 0)))
+INSN(ret, s, branch, branch, C62X,
+ TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_MACRO|TIC6X_FLAG_RETURN,
+ FIX1(FIX(s, 1)),
+ OP1(ORXREG1),
+ ENC2(ENC(x, xpath, 0), ENC(src2, reg, 0)))
+INSN(ret, s, b_irp, branch, C62X,
+ TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_MACRO|TIC6X_FLAG_RETURN,
+ FIX3(FIX(s, 1), FIX(x, 0), FIX(dst, 0)),
+ OP1(ORIRP1),
+ ENC0())
+INSN(ret, s, b_nrp, branch, C62X,
+ TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_MACRO|TIC6X_FLAG_RETURN,
+ FIX3(FIX(s, 1), FIX(x, 0), FIX(dst, 0)),
+ OP1(ORNRP1),
+ ENC0())
+
+INSN(retp, s, call_imm_nop, branch, C64XP,
+ TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MCNOP|TIC6X_FLAG_MACRO|TIC6X_FLAG_RETURN,
+ FIX1(FIX(z, 1)),
+ OP2(OLCST, OWRETREG1),
+ ENC2(ENC(s, fu, 0), ENC(cst, pcrel, 0)))
+
+INSN(rint, nfu, rint, 1cycle, C64XP, 0,
+ FIX1(FIX(s, 0)),
+ OP0(),
+ ENC0())
+
+INSNE(rotl, m_ui_xui_ui, m, compound, 1616_m, C64X, 0,
+ FIX1(FIX(op, 0x1d)),
+ OP3(ORXREG1, ORREG1, OWREG2),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(src1, reg, 1), ENC(dst, reg, 2)))
+INSNE(rotl, m_u5_xui_ui, m, compound, 1616_m, C64X, 0,
+ FIX1(FIX(op, 0x1e)),
+ OP3(ORXREG1, OACST, OWREG2),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(src1, ucst, 1), ENC(dst, reg, 2)))
+
+INSN(rpack2, s, ext_1_or_2_src_noncond, 1cycle, C64XP, 0,
+ FIX2(FIX(op, 0xb), FIX(z, 1)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(rsqrdp, s, 1_or_2_src, 2cycle_dp, C67X, TIC6X_FLAG_NO_CROSS,
+ FIX3(FIX(op, 0x2e), FIX(x, 0), FIX(src1, 0)),
+ OP2(ORREGD1, OWREGD12),
+ ENC3(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(dst, reg, 1)))
+
+INSN(rsqrsp, s, 1_or_2_src, 1cycle, C67X, 0,
+ FIX2(FIX(op, 0x3e), FIX(src1, 0)),
+ OP2(ORXREG1, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(dst, reg, 1)))
+
+INSNE(sadd, l_si_xsi_si, l, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x13)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(sadd, l_xsi_sl_sl, l, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x31)),
+ OP3(ORXREG1, ORREGL1, OWREGL1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(sadd, l_s5_xsi_si, l, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x12)),
+ OP3(OACST, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(sadd, l_s5_sl_sl, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+ FIX1(FIX(op, 0x30)),
+ OP3(OACST, ORREGL1, OWREGL1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(sadd, s_si_xsi_si, s, 1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x20)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(sadd2, s, ext_1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x0)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(saddsub, l, 1_or_2_src_noncond, 1cycle, C64XP, 0,
+ FIX1(FIX(op, 0x0e)),
+ OP3(ORREG1, ORXREG1, OWREGD1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(saddsub2, l, 1_or_2_src_noncond, 1cycle, C64XP, 0,
+ FIX1(FIX(op, 0x0f)),
+ OP3(ORREG1, ORXREG1, OWREGD1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(saddsu2, s, ext_1_or_2_src, 1cycle, C64X, TIC6X_FLAG_MACRO,
+ FIX1(FIX(op, 0x1)),
+ OP3(ORXREG1, ORREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(src1, reg, 1), ENC(dst, reg, 2)))
+
+INSN(saddus2, s, ext_1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x1)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(saddu4, s, ext_1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x3)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(sat, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+ FIX3(FIX(op, 0x40), FIX(x, 0), FIX(src1, 0)),
+ OP2(ORREGL1, OWREG1),
+ ENC3(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(dst, reg, 1)))
+
+INSN(set, s, field, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+ FIX1(FIX(op, 0x2)),
+ OP4(ORREG1, OACST, OACST, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(csta, ucst, 1),
+ ENC(cstb, ucst, 2), ENC(dst, reg, 3)))
+INSN(set, s, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x3b)),
+ OP3(ORXREG1, ORREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(src1, reg, 1), ENC(dst, reg, 2)))
+
+INSN(shfl, m, unary, 1616_m, C64X, 0,
+ FIX1(FIX(op, 0x1c)),
+ OP2(ORXREG1, OWREG2),
+ ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(dst, reg, 1)))
+
+INSN(shfl3, l, 1_or_2_src_noncond, 1cycle, C64XP, 0,
+ FIX1(FIX(op, 0x36)),
+ OP3(ORREG1, ORXREG1, OWREGD1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSNE(shl, s_xsi_ui_si, s, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x33)),
+ OP3(ORXREG1, ORREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(src1, reg, 1), ENC(dst, reg, 2)))
+INSNE(shl, s_sl_ui_sl, s, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+ FIX2(FIX(op, 0x31), FIX(x, 0)),
+ OP3(ORREGL1, ORREG1, OWREGL1),
+ ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, reg, 1),
+ ENC(dst, reg, 2)))
+INSNE(shl, s_xui_ui_ul, s, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x13)),
+ OP3(ORXREG1, ORREG1, OWREGL1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(src1, reg, 1), ENC(dst, reg, 2)))
+INSNE(shl, s_xsi_u5_si, s, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x32)),
+ OP3(ORXREG1, OACST, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(src1, ucst, 1), ENC(dst, reg, 2)))
+INSNE(shl, s_sl_u5_sl, s, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+ FIX2(FIX(op, 0x30), FIX(x, 0)),
+ OP3(ORREGL1, OACST, OWREGL1),
+ ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1),
+ ENC(dst, reg, 2)))
+INSNE(shl, s_xui_u5_ul, s, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x12)),
+ OP3(ORXREG1, OACST, OWREGL1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(src1, ucst, 1), ENC(dst, reg, 2)))
+
+INSN(shlmb, l, 1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x61)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSN(shlmb, s, ext_1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x9)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSNE(shr, s_xsi_ui_si, s, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x37)),
+ OP3(ORXREG1, ORREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(src1, reg, 1), ENC(dst, reg, 2)))
+INSNE(shr, s_sl_ui_sl, s, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+ FIX2(FIX(op, 0x35), FIX(x, 0)),
+ OP3(ORREGL1, ORREG1, OWREGL1),
+ ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, reg, 1),
+ ENC(dst, reg, 2)))
+INSNE(shr, s_xsi_u5_si, s, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x36)),
+ OP3(ORXREG1, OACST, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(src1, ucst, 1), ENC(dst, reg, 2)))
+INSNE(shr, s_sl_u5_sl, s, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+ FIX2(FIX(op, 0x34), FIX(x, 0)),
+ OP3(ORREGL1, OACST, OWREGL1),
+ ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1),
+ ENC(dst, reg, 2)))
+
+INSNE(shr2, s_xs2_ui_s2, s, ext_1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x7)),
+ OP3(ORXREG1, ORREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(src1, reg, 1), ENC(dst, reg, 2)))
+INSNE(shr2, s_xs2_u5_s2, s, 1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x18)),
+ OP3(ORXREG1, OACST, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(src1, ucst, 1), ENC(dst, reg, 2)))
+
+INSN(shrmb, l, 1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x62)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSN(shrmb, s, ext_1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0xa)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSNE(shru, s_xui_ui_ui, s, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x27)),
+ OP3(ORXREG1, ORREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(src1, reg, 1), ENC(dst, reg, 2)))
+INSNE(shru, s_ul_ui_ul, s, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+ FIX2(FIX(op, 0x25), FIX(x, 0)),
+ OP3(ORREGL1, ORREG1, OWREGL1),
+ ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, reg, 1),
+ ENC(dst, reg, 2)))
+INSNE(shru, s_xui_u5_ui, s, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x26)),
+ OP3(ORXREG1, OACST, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(src1, ucst, 1), ENC(dst, reg, 2)))
+INSNE(shru, s_ul_u5_ul, s, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+ FIX2(FIX(op, 0x24), FIX(x, 0)),
+ OP3(ORREGL1, OACST, OWREGL1),
+ ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1),
+ ENC(dst, reg, 2)))
+
+INSNE(shru2, s_xu2_ui_u2, s, ext_1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x8)),
+ OP3(ORXREG1, ORREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(src1, reg, 1), ENC(dst, reg, 2)))
+INSNE(shru2, s_xu2_u5_u2, s, 1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x19)),
+ OP3(ORXREG1, OACST, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(src1, ucst, 1), ENC(dst, reg, 2)))
+
+INSN(sl, d, 1_or_2_src, store, ATOMIC,
+ TIC6X_FLAG_STORE|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_SIDE_T2_ONLY|TIC6X_FLAG_NO_CROSS,
+ FIX3(FIX(s, 1), FIX(op, 0xd), FIX(src1, 0)),
+ OP2(ORDREG1, OWMEMDW),
+ ENC2(ENC(dst, reg, 0), ENC(src2, reg, 1)))
+
+INSN(smpy, m, mpy, 1616_m, C62X, 0,
+ FIX1(FIX(op, 0x1a)),
+ OP3(ORREG1, ORXREG1, OWREG2),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(smpyh, m, mpy, 1616_m, C62X, 0,
+ FIX1(FIX(op, 0x02)),
+ OP3(ORREG1, ORXREG1, OWREG2),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(smpyhl, m, mpy, 1616_m, C62X, 0,
+ FIX1(FIX(op, 0x0a)),
+ OP3(ORREG1, ORXREG1, OWREG2),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(smpylh, m, mpy, 1616_m, C62X, 0,
+ FIX1(FIX(op, 0x12)),
+ OP3(ORREG1, ORXREG1, OWREG2),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(smpy2, m, compound, 4cycle, C64X, 0,
+ FIX1(FIX(op, 0x01)),
+ OP3(ORREG1, ORXREG1, OWREGD4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+/* Contrary to SPRUFE8, this is the correct operand order for this
+ instruction. */
+INSN(smpy32, m, 1_or_2_src, 4cycle, C64XP, 0,
+ FIX1(FIX(op, 0x19)),
+ OP3(ORREG1, ORXREG1, OWREG4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(spack2, s, ext_1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x2)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(spacku4, s, ext_1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x4)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(spdp, s, 1_or_2_src, 2cycle_dp, C67X, 0,
+ FIX2(FIX(op, 0x02), FIX(src1, 0)),
+ OP2(ORXREG1, OWREGD12),
+ ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(dst, reg, 1)))
+
+INSN(spint, l, 1_or_2_src, 4cycle, C67X, 0,
+ FIX2(FIX(op, 0x0a), FIX(src1, 0)),
+ OP2(ORXREG1, OWREG4),
+ ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(dst, reg, 1)))
+
+INSNE(spkernel, nfu_2, nfu, spkernel, 1cycle, C64XP,
+ TIC6X_FLAG_FIRST|TIC6X_FLAG_NO_MCNOP|TIC6X_FLAG_SPKERNEL,
+ FIX1(FIX(s, 0)),
+ OP2(OACST, OACST),
+ ENC2(ENC(fstgfcyc, fstg, 0), ENC(fstgfcyc, fcyc, 1)))
+INSNE(spkernel, nfu_0, nfu, spkernel, 1cycle, C64XP,
+ TIC6X_FLAG_FIRST|TIC6X_FLAG_NO_MCNOP|TIC6X_FLAG_SPKERNEL|TIC6X_FLAG_MACRO,
+ FIX2(FIX(s, 0), FIX(fstgfcyc, 0)),
+ OP0(),
+ ENC0())
+
+INSN(spkernelr, nfu, spkernelr, 1cycle, C64XP,
+ TIC6X_FLAG_FIRST|TIC6X_FLAG_NO_MCNOP|TIC6X_FLAG_SPKERNEL,
+ FIX1(FIX(s, 0)),
+ OP0(),
+ ENC0())
+
+INSN(sploop, nfu, loop_buffer, 1cycle, C64XP,
+ TIC6X_FLAG_FIRST|TIC6X_FLAG_NO_MCNOP|TIC6X_FLAG_SPLOOP,
+ FIX4(FIX(s, 0), FIX(op, 0xc), FIX(csta, 0), RAN(cstb, 0, 13)),
+ OP1(OACST),
+ ENC1(ENC(cstb, ucst_minus_one, 0)))
+
+INSN(sploopd, nfu, loop_buffer, 1cycle, C64XP,
+ TIC6X_FLAG_FIRST|TIC6X_FLAG_NO_MCNOP|TIC6X_FLAG_SPLOOP,
+ FIX4(FIX(s, 0), FIX(op, 0xd), FIX(csta, 0), RAN(cstb, 0, 13)),
+ OP1(OACST),
+ ENC1(ENC(cstb, ucst_minus_one, 0)))
+
+INSN(sploopw, nfu, loop_buffer, 1cycle, C64XP,
+ TIC6X_FLAG_FIRST|TIC6X_FLAG_NO_MCNOP|TIC6X_FLAG_SPLOOP,
+ FIX4(FIX(s, 0), FIX(op, 0xf), FIX(csta, 0), RAN(cstb, 0, 13)),
+ OP1(OACST),
+ ENC1(ENC(cstb, ucst_minus_one, 0)))
+
+/* Contrary to SPRUFE8, this is the correct encoding for this
+ instruction. */
+INSN(spmask, nfu, spmask, 1cycle, C64XP, TIC6X_FLAG_FIRST|TIC6X_FLAG_SPMASK,
+ FIX2(FIX(s, 0), FIX(op, 0x8)),
+ OP1(OFULIST),
+ ENC1(ENC(mask, spmask, 0)))
+
+INSN(spmaskr, nfu, spmask, 1cycle, C64XP, TIC6X_FLAG_FIRST|TIC6X_FLAG_SPMASK,
+ FIX2(FIX(s, 0), FIX(op, 0x9)),
+ OP1(OFULIST),
+ ENC1(ENC(mask, spmask, 0)))
+
+INSN(sptrunc, l, 1_or_2_src, 4cycle, C67X, 0,
+ FIX2(FIX(op, 0x0b), FIX(src1, 0)),
+ OP2(ORXREG1, OWREG4),
+ ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(dst, reg, 1)))
+
+INSNE(sshl, s_xsi_ui_si, s, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x23)),
+ OP3(ORXREG1, ORREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(src1, reg, 1), ENC(dst, reg, 2)))
+INSNE(sshl, s_xsi_u5_si, s, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x22)),
+ OP3(ORXREG1, OACST, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(src1, ucst, 1), ENC(dst, reg, 2)))
+
+INSN(sshvl, m, compound, 1616_m, C64X, 0,
+ FIX1(FIX(op, 0x1c)),
+ OP3(ORXREG1, ORREG1, OWREG2),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(src1, reg, 1), ENC(dst, reg, 2)))
+
+/* Contrary to SPRUFE8, this is the correct encoding for this
+ instruction. */
+INSN(sshvr, m, compound, 1616_m, C64X, 0,
+ FIX1(FIX(op, 0x1a)),
+ OP3(ORXREG1, ORREG1, OWREG2),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(src1, reg, 1), ENC(dst, reg, 2)))
+
+INSNE(ssub, l_si_xsi_si, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_PREFER(1),
+ FIX1(FIX(op, 0x0f)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(ssub, l_xsi_si_si, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_PREFER(0),
+ FIX1(FIX(op, 0x1f)),
+ OP3(ORXREG1, ORREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(ssub, l_s5_xsi_si, l, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x0e)),
+ OP3(OACST, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(ssub, l_s5_sl_sl, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+ FIX1(FIX(op, 0x2c)),
+ OP3(OACST, ORREGL1, OWREGL1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(ssub2, l, 1_or_2_src, 1cycle, C64XP, 0,
+ FIX1(FIX(op, 0x64)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(stb, d, load_store, store, C62X,
+ TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1),
+ FIX2(FIX(op, 3), FIX(r, 0)),
+ OP2(ORDREG1, OWMEMSB),
+ ENC6(ENC(s, data_fu, 0), ENC(y, fu, 0), ENC(mode, mem_mode, 1),
+ ENC(offsetR, mem_offset, 1), ENC(baseR, reg, 1),
+ ENC(srcdst, reg, 0)))
+INSN(stb, d, load_store_long, store, C62X,
+ TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_PREFER(0),
+ FIX1(FIX(op, 3)),
+ OP2(ORDREG1, OWMEMLB),
+ ENC4(ENC(s, data_fu, 0), ENC(y, areg, 1), ENC(offsetR, ulcst_dpr_byte, 1),
+ ENC(dst, reg, 0)))
+
+INSN(stdw, d, load_store, store, C64X, TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS,
+ FIX2(FIX(op, 4), FIX(r, 1)),
+ OP2(ORDREGD1, OWMEMSD),
+ ENC6(ENC(s, data_fu, 0), ENC(y, fu, 0), ENC(mode, mem_mode, 1),
+ ENC(offsetR, mem_offset, 1), ENC(baseR, reg, 1),
+ ENC(srcdst, reg, 0)))
+
+INSN(sth, d, load_store, store, C62X,
+ TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1),
+ FIX2(FIX(op, 5), FIX(r, 0)),
+ OP2(ORDREG1, OWMEMSH),
+ ENC6(ENC(s, data_fu, 0), ENC(y, fu, 0), ENC(mode, mem_mode, 1),
+ ENC(offsetR, mem_offset, 1), ENC(baseR, reg, 1),
+ ENC(srcdst, reg, 0)))
+INSN(sth, d, load_store_long, store, C62X,
+ TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_PREFER(0),
+ FIX1(FIX(op, 5)),
+ OP2(ORDREG1, OWMEMLH),
+ ENC4(ENC(s, data_fu, 0), ENC(y, areg, 1), ENC(offsetR, ulcst_dpr_half, 1),
+ ENC(dst, reg, 0)))
+
+INSN(stndw, d, store_nonaligned, store, C64X,
+ TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_UNALIGNED,
+ FIX0(),
+ OP2(ORDREGD1, OWMEMND),
+ ENC7(ENC(s, data_fu, 0), ENC(y, fu, 0), ENC(mode, mem_mode, 1),
+ ENC(offsetR, mem_offset_noscale, 1), ENC(baseR, reg, 1),
+ ENC(sc, scaled, 1), ENC(src, reg_shift, 0)))
+
+INSN(stnw, d, load_store, store, C64X,
+ TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_UNALIGNED,
+ FIX2(FIX(op, 5), FIX(r, 1)),
+ OP2(ORDREG1, OWMEMSW),
+ ENC6(ENC(s, data_fu, 0), ENC(y, fu, 0), ENC(mode, mem_mode, 1),
+ ENC(offsetR, mem_offset, 1), ENC(baseR, reg, 1),
+ ENC(srcdst, reg, 0)))
+
+INSN(stw, d, load_store, store, C62X,
+ TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1),
+ FIX2(FIX(op, 7), FIX(r, 0)),
+ OP2(ORDREG1, OWMEMSW),
+ ENC6(ENC(s, data_fu, 0), ENC(y, fu, 0), ENC(mode, mem_mode, 1),
+ ENC(offsetR, mem_offset, 1), ENC(baseR, reg, 1),
+ ENC(srcdst, reg, 0)))
+INSN(stw, d, load_store_long, store, C62X,
+ TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_PREFER(0),
+ FIX1(FIX(op, 7)),
+ OP2(ORDREG1, OWMEMLW),
+ ENC4(ENC(s, data_fu, 0), ENC(y, areg, 1), ENC(offsetR, ulcst_dpr_word, 1),
+ ENC(dst, reg, 0)))
+
+INSNE(sub, l_si_xsi_si, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_PREFER(1),
+ FIX1(FIX(op, 0x07)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(sub, l_xsi_si_si, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_PREFER(0),
+ FIX1(FIX(op, 0x17)),
+ OP3(ORXREG1, ORREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(sub, l_si_xsi_sl, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_PREFER(1),
+ FIX1(FIX(op, 0x27)),
+ OP3(ORREG1, ORXREG1, OWREGL1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(sub, l_xsi_si_sl, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_PREFER(0),
+ FIX1(FIX(op, 0x37)),
+ OP3(ORXREG1, ORREG1, OWREGL1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(sub, l_s5_xsi_si, l, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x06)),
+ OP3(OACST, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(sub, l_s5_sl_sl, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+ FIX1(FIX(op, 0x24)),
+ OP3(OACST, ORREGL1, OWREGL1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(sub, l_xsi_s5_si, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_MACRO,
+ FIX1(FIX(op, 0x2)),
+ OP3(ORXREG1, OACST, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst_negate, 1),
+ ENC(src2, reg, 0), ENC(dst, reg, 2)))
+INSNE(sub, l_sl_s5_sl, l, 1_or_2_src, 1cycle, C62X,
+ TIC6X_FLAG_MACRO|TIC6X_FLAG_NO_CROSS,
+ FIX2(FIX(op, 0x20), FIX(x, 0)),
+ OP3(ORREGL1, OACST, OWREGL1),
+ ENC4(ENC(s, fu, 0), ENC(src1, scst_negate, 1), ENC(src2, reg, 0),
+ ENC(dst, reg, 2)))
+INSNE(sub, s_si_xsi_si, s, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_PREFER(1),
+ FIX1(FIX(op, 0x17)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(sub, s_s5_xsi_si, s, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x16)),
+ OP3(OACST, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+/* Contrary to SPRUFE8, this is the correct encoding for this
+ instruction; this instruction can be predicated. */
+INSNE(sub, s_xsi_si_si, s, ext_1_or_2_src, 1cycle, C64X, TIC6X_FLAG_PREFER(0),
+ FIX1(FIX(op, 0x5)),
+ OP3(ORXREG1, ORREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(src1, reg, 1), ENC(dst, reg, 2)))
+INSNE(sub, s_xsi_s5_si, s, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_MACRO,
+ FIX1(FIX(op, 0x6)),
+ OP3(ORXREG1, OACST, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst_negate, 1),
+ ENC(src2, reg, 0), ENC(dst, reg, 2)))
+INSNE(sub, d_si_si_si, d, 1_or_2_src, 1cycle, C62X,
+ TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1),
+ FIX1(FIX(op, 0x11)),
+ OP3(ORREG1, ORREG1, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, reg, 1),
+ ENC(dst, reg, 2)))
+INSNE(sub, d_si_u5_si, d, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+ FIX1(FIX(op, 0x13)),
+ OP3(ORREG1, OACST, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1),
+ ENC(dst, reg, 2)))
+INSNE(sub, d_si_xsi_si, d, ext_1_or_2_src, 1cycle, C64X, TIC6X_FLAG_PREFER(0),
+ FIX1(FIX(op, 0xc)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSNE(subab, d_si_si_si, d, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+ FIX1(FIX(op, 0x31)),
+ OP3(ORREG1, ORREG1, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, reg, 1),
+ ENC(dst, reg, 2)))
+INSNE(subab, d_si_u5_si, d, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+ FIX1(FIX(op, 0x33)),
+ OP3(ORREG1, OACST, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1),
+ ENC(dst, reg, 2)))
+
+INSN(subabs4, l, 1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x5a)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSNE(subah, d_si_si_si, d, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+ FIX1(FIX(op, 0x35)),
+ OP3(ORREG1, ORREG1, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, reg, 1),
+ ENC(dst, reg, 2)))
+INSNE(subah, d_si_u5_si, d, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+ FIX1(FIX(op, 0x37)),
+ OP3(ORREG1, OACST, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1),
+ ENC(dst, reg, 2)))
+
+INSNE(subaw, d_si_si_si, d, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+ FIX1(FIX(op, 0x39)),
+ OP3(ORREG1, ORREG1, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, reg, 1),
+ ENC(dst, reg, 2)))
+INSNE(subaw, d_si_u5_si, d, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+ FIX1(FIX(op, 0x3b)),
+ OP3(ORREG1, OACST, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1),
+ ENC(dst, reg, 2)))
+
+INSN(subc, l, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x4b)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSNE(subdp, l_dp_xdp_dp, l, 1_or_2_src, addsubdp, C67X, TIC6X_FLAG_PREFER(1),
+ FIX1(FIX(op, 0x19)),
+ OP3(ORREGD12, ORXREGD12, OWREGD67),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(subdp, l_xdp_dp_dp, l, 1_or_2_src, addsubdp, C67X, TIC6X_FLAG_PREFER(0),
+ FIX1(FIX(op, 0x1d)),
+ OP3(ORXREGD12, ORREGD12, OWREGD67),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(subdp, s_dp_xdp_dp, s, l_1_or_2_src, addsubdp, C67XP,
+ TIC6X_FLAG_PREFER(1),
+ FIX1(FIX(op, 0x73)),
+ OP3(ORREGD12, ORXREGD12, OWREGD67),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(subdp, s_xdp_dp_dp, s, l_1_or_2_src, addsubdp, C67XP,
+ TIC6X_FLAG_PREFER(0),
+ FIX1(FIX(op, 0x77)),
+ OP3(ORXREGD12, ORREGD12, OWREGD67),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(src1, reg, 1), ENC(dst, reg, 2)))
+
+INSNE(subsp, l_sp_xsp_sp, l, 1_or_2_src, 4cycle, C67X, TIC6X_FLAG_PREFER(1),
+ FIX1(FIX(op, 0x11)),
+ OP3(ORREG1, ORXREG1, OWREG4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(subsp, l_xsp_sp_sp, l, 1_or_2_src, 4cycle, C67X, TIC6X_FLAG_PREFER(0),
+ FIX1(FIX(op, 0x15)),
+ OP3(ORXREG1, ORREG1, OWREG4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(subsp, s_sp_xsp_sp, s, l_1_or_2_src, 4cycle, C67XP,
+ TIC6X_FLAG_PREFER(1),
+ FIX1(FIX(op, 0x71)),
+ OP3(ORREG1, ORXREG1, OWREG4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(subsp, s_xsp_sp_sp, s, l_1_or_2_src, 4cycle, C67XP,
+ TIC6X_FLAG_PREFER(0),
+ FIX1(FIX(op, 0x75)),
+ OP3(ORXREG1, ORREG1, OWREG4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(src1, reg, 1), ENC(dst, reg, 2)))
+
+INSNE(subu, l_ui_xui_ul, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_PREFER(1),
+ FIX1(FIX(op, 0x2f)),
+ OP3(ORREG1, ORXREG1, OWREGL1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(subu, l_xui_ui_ul, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_PREFER(0),
+ FIX1(FIX(op, 0x3f)),
+ OP3(ORXREG1, ORREG1, OWREGL1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(sub2, l, 1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x04)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSN(sub2, s, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x11)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSN(sub2, d, ext_1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x5)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(sub4, l, 1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x66)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(swap2, l, 1_or_2_src, 1cycle, C64X, TIC6X_FLAG_MACRO|TIC6X_FLAG_NO_CROSS,
+ FIX2(FIX(op, 0x1b), FIX(x, 0)),
+ OP2(ORREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 0), ENC(dst, reg, 1)))
+INSN(swap2, s, 1_or_2_src, 1cycle, C64X, TIC6X_FLAG_MACRO|TIC6X_FLAG_NO_CROSS,
+ FIX2(FIX(op, 0x10), FIX(x, 0)),
+ OP2(ORREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 0), ENC(dst, reg, 1)))
+
+/* Contrary to SPRUFE8, this is the correct encoding for this
+ instruction. */
+INSN(swap4, l, unary, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x1)),
+ OP2(ORXREG1, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(dst, reg, 1)))
+
+INSN(swe, nfu, swe, 1cycle, C64XP, 0,
+ FIX1(FIX(s, 0)),
+ OP0(),
+ ENC0())
+
+INSN(swenr, nfu, swenr, 1cycle, C64XP, 0,
+ FIX1(FIX(s, 0)),
+ OP0(),
+ ENC0())
+
+INSN(unpkhu4, l, unary, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x03)),
+ OP2(ORXREG1, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(dst, reg, 1)))
+INSN(unpkhu4, s, unary, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x03)),
+ OP2(ORXREG1, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(dst, reg, 1)))
+
+INSN(unpklu4, l, unary, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x02)),
+ OP2(ORXREG1, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(dst, reg, 1)))
+INSN(unpklu4, s, unary, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0x02)),
+ OP2(ORXREG1, OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(dst, reg, 1)))
+
+INSNE(xor, l_ui_xui_ui, l, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x6f)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(xor, l_s5_xui_ui, l, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x6e)),
+ OP3(OACST, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(xor, s_ui_xui_ui, s, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x0b)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(xor, s_s5_xui_ui, s, 1_or_2_src, 1cycle, C62X, 0,
+ FIX1(FIX(op, 0x0a)),
+ OP3(OACST, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(xor, d_ui_xui_ui, d, ext_1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0xe)),
+ OP3(ORREG1, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(xor, d_s5_xui_ui, d, ext_1_or_2_src, 1cycle, C64X, 0,
+ FIX1(FIX(op, 0xf)),
+ OP3(OACST, ORXREG1, OWREG1),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(xormpy, m, 1_or_2_src, 4cycle, C64XP, 0,
+ FIX1(FIX(op, 0x1b)),
+ OP3(ORREG1, ORXREG1, OWREG4),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(xpnd2, m, unary, 1616_m, C64X, 0,
+ FIX1(FIX(op, 0x19)),
+ OP2(ORXREG1, OWREG2),
+ ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(dst, reg, 1)))
+
+INSN(xpnd4, m, unary, 1616_m, C64X, 0,
+ FIX1(FIX(op, 0x18)),
+ OP2(ORXREG1, OWREG2),
+ ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+ ENC(dst, reg, 1)))
+
+INSN(zero, s, mvk, 1cycle, C62X, TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO,
+ FIX2(FIX(h, 0), FIX(cst, 0)),
+ OP1(OWREG1),
+ ENC2(ENC(s, fu, 0), ENC(dst, reg, 0)))
+INSN(zero, l, unary, 1cycle, C64X,
+ TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO|TIC6X_FLAG_PREFER(1),
+ FIX3(FIX(x, 0), FIX(op, 0x05), FIX(src2, 0)),
+ OP1(OWREG1),
+ ENC2(ENC(s, fu, 0), ENC(dst, reg, 0)))
+INSNE(zero, l_sub, l, 1_or_2_src, 1cycle, C62X,
+ TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO|TIC6X_FLAG_PREFER(0),
+ FIX2(FIX(op, 0x07), FIX(x, 0)),
+ OP1(OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(src1, reg_unused, 0), ENC(src2, reg_unused, 0),
+ ENC(dst, reg, 0)))
+INSNE(zero, l_sub_sl, l, 1_or_2_src, 1cycle, C62X,
+ TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO,
+ FIX2(FIX(op, 0x27), FIX(x, 0)),
+ OP1(OWREGL1),
+ ENC4(ENC(s, fu, 0), ENC(src1, reg_unused, 0), ENC(src2, reg_unused, 0),
+ ENC(dst, reg, 0)))
+INSNE(zero, d_mvk, d, 1_or_2_src, 1cycle, C64X,
+ TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO|TIC6X_FLAG_PREFER(1),
+ FIX3(FIX(op, 0x00), FIX(src1, 0), FIX(src2, 0)),
+ OP1(OWREG1),
+ ENC2(ENC(s, fu, 0), ENC(dst, reg, 0)))
+INSNE(zero, d_sub, d, 1_or_2_src, 1cycle, C62X,
+ TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO|TIC6X_FLAG_PREFER(0),
+ FIX1(FIX(op, 0x11)),
+ OP1(OWREG1),
+ ENC4(ENC(s, fu, 0), ENC(src2, reg_unused, 0), ENC(src1, reg_unused, 0),
+ ENC(dst, reg, 0)))
+
+#undef TIC6X_INSN_C64X_AND_C67X
+#undef tic6x_insn_format_nfu_s_branch_nop_cst
+#undef tic6x_insn_format_s_l_1_or_2_src
+#undef RAN
+#undef FIX
+#undef FIX0
+#undef FIX1
+#undef FIX2
+#undef FIX3
+#undef FIX4
+#undef OP0
+#undef OP1
+#undef OP2
+#undef OP3
+#undef OP4
+#undef OACST
+#undef OLCST
+#undef OFULIST
+#undef ORIRP1
+#undef ORNRP1
+#undef OWREG1
+#undef OWRETREG1
+#undef ORREG1
+#undef ORDREG1
+#undef ORWREG1
+#undef ORAREG1
+#undef ORXREG1
+#undef ORREG12
+#undef ORREG14
+#undef ORXREG14
+#undef OWREG2
+#undef OWREG4
+#undef OWREG9
+#undef OWDREG5
+#undef OWREGL1
+#undef ORREGL1
+#undef OWREGD1
+#undef OWREGD12
+#undef OWREGD4
+#undef ORREGD1
+#undef OWREGD45
+#undef OWREGD67
+#undef ORDREGD1
+#undef OWDREGD5
+#undef ORREGD12
+#undef ORXREGD12
+#undef ORREGD1234
+#undef ORREGD1324
+#undef OWREGD910
+#undef ORCREG1
+#undef OWCREG1
+#undef ORMEMDW
+#undef OWMEMDW
+#undef ORMEMSB
+#undef OWMEMSB
+#undef ORMEMLB
+#undef OWMEMLB
+#undef ORMEMSH
+#undef OWMEMSH
+#undef ORMEMLH
+#undef OWMEMLH
+#undef ORMEMSW
+#undef OWMEMSW
+#undef ORMEMLW
+#undef OWMEMLW
+#undef ORMEMSD
+#undef OWMEMSD
+#undef ORMEMND
+#undef OWMEMND
+#undef ENC
+#undef ENC0
+#undef ENC1
+#undef ENC2
+#undef ENC3
+#undef ENC4
+#undef ENC5
+#undef ENC6
+#undef ENC7
diff --git a/external/gpl3/binutils/dist/include/opcode/tic6x.h b/external/gpl3/binutils/dist/include/opcode/tic6x.h
new file mode 100644
index 00000000000..ab2f2e9907b
--- /dev/null
+++ b/external/gpl3/binutils/dist/include/opcode/tic6x.h
@@ -0,0 +1,614 @@
+/* TI C6X opcode information.
+ Copyright 2010
+ Free Software Foundation, Inc.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+ MA 02110-1301, USA. */
+
+#ifndef OPCODE_TIC6X_H
+#define OPCODE_TIC6X_H
+
+#include "bfd.h"
+#include "symcat.h"
+
+/* A field in an instruction format. The names are based on those
+ used in the architecture manuals. */
+typedef enum
+ {
+ tic6x_field_baseR,
+ tic6x_field_creg,
+ tic6x_field_cst,
+ tic6x_field_csta,
+ tic6x_field_cstb,
+ tic6x_field_dst,
+ tic6x_field_fstgfcyc,
+ tic6x_field_h,
+ tic6x_field_mask,
+ tic6x_field_mode,
+ tic6x_field_offsetR,
+ tic6x_field_op,
+ tic6x_field_p,
+ tic6x_field_r,
+ tic6x_field_s,
+ tic6x_field_sc,
+ tic6x_field_src,
+ tic6x_field_src1,
+ tic6x_field_src2,
+ tic6x_field_srcdst,
+ tic6x_field_x,
+ tic6x_field_y,
+ tic6x_field_z
+ } tic6x_insn_field_id;
+
+typedef struct
+{
+ /* The name used to reference the field. */
+ tic6x_insn_field_id field_id;
+
+ /* The least-significant bit position in the field. */
+ unsigned short low_pos;
+
+ /* The number of bits in the field. */
+ unsigned short width;
+} tic6x_insn_field;
+
+/* Maximum number of variable fields in an instruction format. */
+#define TIC6X_MAX_INSN_FIELDS 11
+
+/* A particular instruction format. */
+typedef struct
+{
+ /* How many bits in the instruction. */
+ unsigned int num_bits;
+
+ /* Constant bits in the instruction. */
+ unsigned int cst_bits;
+
+ /* Mask matching those bits. */
+ unsigned int mask;
+
+ /* The number of instruction fields. */
+ unsigned int num_fields;
+
+ /* Descriptions of instruction fields. */
+ tic6x_insn_field fields[TIC6X_MAX_INSN_FIELDS];
+} tic6x_insn_format;
+
+/* An index into the table of instruction formats. */
+typedef enum
+ {
+#define FMT(name, num_bits, cst_bits, mask, fields) \
+ CONCAT2(tic6x_insn_format_, name),
+#include "tic6x-insn-formats.h"
+#undef FMT
+ tic6x_insn_format_max
+ } tic6x_insn_format_id;
+
+/* The table itself. */
+extern const tic6x_insn_format tic6x_insn_format_table[tic6x_insn_format_max];
+
+/* If instruction format FMT has a field FIELD, return a pointer to
+ the description of that field; otherwise return NULL. */
+
+const tic6x_insn_field *tic6x_field_from_fmt (const tic6x_insn_format *fmt,
+ tic6x_insn_field_id field);
+
+/* Description of a field (in an instruction format) whose value is
+ fixed, or constrained to be in a particular range, in a particular
+ opcode. */
+typedef struct
+{
+ /* The name of the field. */
+ tic6x_insn_field_id field_id;
+
+ /* The least value of the field in this instruction. */
+ unsigned int min_val;
+
+ /* The greatest value of the field in this instruction. */
+ unsigned int max_val;
+} tic6x_fixed_field;
+
+/* Bit-masks for defining instructions present on some subset of
+ processors; each indicates an instruction present on that processor
+ and those that are supersets of it. The options passed to the
+ assembler determine a bit-mask ANDed with the bit-mask indicating
+ when the instruction was added to determine whether the instruction
+ is enabled. */
+#define TIC6X_INSN_C62X 0x0001
+#define TIC6X_INSN_C64X 0x0002
+#define TIC6X_INSN_C64XP 0x0004
+#define TIC6X_INSN_C67X 0x0008
+#define TIC6X_INSN_C67XP 0x0010
+#define TIC6X_INSN_C674X 0x0020
+#define TIC6X_INSN_ATOMIC 0x0040
+
+/* Flags with further information about an opcode table entry. */
+
+/* Only used by the assembler, not the disassembler. */
+#define TIC6X_FLAG_MACRO 0x0001
+
+/* Must be first in its execute packet. */
+#define TIC6X_FLAG_FIRST 0x0002
+
+/* Multi-cycle NOP (not used for the NOP n instruction itself, which
+ is only a multicycle NOP if n > 1). */
+#define TIC6X_FLAG_MCNOP 0x0004
+
+/* Cannot be in parallel with a multi-cycle NOP. */
+#define TIC6X_FLAG_NO_MCNOP 0x0008
+
+/* Load instruction. */
+#define TIC6X_FLAG_LOAD 0x0010
+
+/* Store instruction. */
+#define TIC6X_FLAG_STORE 0x0020
+
+/* Unaligned memory operation. */
+#define TIC6X_FLAG_UNALIGNED 0x0040
+
+/* Only on side B. */
+#define TIC6X_FLAG_SIDE_B_ONLY 0x0080
+
+/* Only on data path T2. */
+#define TIC6X_FLAG_SIDE_T2_ONLY 0x0100
+
+/* Does not support cross paths. */
+#define TIC6X_FLAG_NO_CROSS 0x0200
+
+/* Annotate this branch instruction as a call. */
+#define TIC6X_FLAG_CALL 0x0400
+
+/* Annotate this branch instruction as a return. */
+#define TIC6X_FLAG_RETURN 0x0800
+
+/* This instruction starts a software pipelined loop. */
+#define TIC6X_FLAG_SPLOOP 0x1000
+
+/* This instruction ends a software pipelined loop. */
+#define TIC6X_FLAG_SPKERNEL 0x2000
+
+/* This instruction takes a list of functional units as parameters;
+ although described as having one parameter, the number may be 0 to
+ 8. */
+#define TIC6X_FLAG_SPMASK 0x4000
+
+/* When more than one opcode matches the assembly source, prefer the
+ one with the highest value for this bit-field. If two opcode table
+ entries can match the same syntactic form, they must have different
+ values here. */
+#define TIC6X_PREFER_VAL(n) (((n) & 0x8000) >> 15)
+#define TIC6X_FLAG_PREFER(n) ((n) << 15)
+#define TIC6X_NUM_PREFER 2
+
+/* Maximum number of fixed fields for a particular opcode. */
+#define TIC6X_MAX_FIXED_FIELDS 4
+
+/* Maximum number of operands in the opcode table for a particular
+ opcode. */
+#define TIC6X_MAX_OPERANDS 4
+
+/* Maximum number of operands in the source code for a particular
+ opcode (different from the number in the opcode table for SPMASK
+ and SPMASKR). */
+#define TIC6X_MAX_SOURCE_OPERANDS 8
+
+/* Maximum number of variable fields for a particular opcode. */
+#define TIC6X_MAX_VAR_FIELDS 7
+
+/* Which functional units an opcode uses. This only describes the
+ basic choice of D, L, M, S or no functional unit; other fields are
+ used to describe further restrictions (instructions only operating
+ on one side), use of cross paths and load/store instructions using
+ one side for the address and the other side for the source or
+ destination register. */
+typedef enum
+ {
+ tic6x_func_unit_d,
+ tic6x_func_unit_l,
+ tic6x_func_unit_m,
+ tic6x_func_unit_s,
+ tic6x_func_unit_nfu
+ } tic6x_func_unit_base;
+
+/* Possible forms of source operand. */
+typedef enum
+ {
+ /* An assembly-time constant. */
+ tic6x_operand_asm_const,
+ /* A link-time constant. */
+ tic6x_operand_link_const,
+ /* A register, from the same side as the functional unit
+ selected. */
+ tic6x_operand_reg,
+ /* A register, that is from the other side if a cross path is
+ used. */
+ tic6x_operand_xreg,
+ /* A register, that is from the side of the data path
+ selected. */
+ tic6x_operand_dreg,
+ /* An address register usable with 15-bit offsets (B14 or B15).
+ This is from the same side as the functional unit if a cross
+ path is not used, and the other side if a cross path is
+ used. */
+ tic6x_operand_areg,
+ /* A return address register (A3 or B3), from the same side as the
+ functional unit selected. */
+ tic6x_operand_retreg,
+ /* A register pair, from the same side as the functional unit
+ selected. */
+ tic6x_operand_regpair,
+ /* A register pair, that is from the other side if a cross path is
+ used. */
+ tic6x_operand_xregpair,
+ /* A register pair, from the side of the data path selected. */
+ tic6x_operand_dregpair,
+ /* The literal string "irp" (case-insensitive). */
+ tic6x_operand_irp,
+ /* The literal string "nrp" (case-insensitive). */
+ tic6x_operand_nrp,
+ /* A control register. */
+ tic6x_operand_ctrl,
+ /* A memory reference (base and offset registers from the side of
+ the functional unit selected), using either unsigned 5-bit
+ constant or register offset, if any offset; register offsets
+ cannot use unscaled () syntax. */
+ tic6x_operand_mem_short,
+ /* A memory reference (base and offset registers from the side of
+ the functional unit selected), using either unsigned 5-bit
+ constant or register offset, if any offset; register offsets
+ can use unscaled () syntax (for LDNDW and STNDW). */
+ tic6x_operand_mem_ndw,
+ /* A memory reference using 15-bit link-time constant offset
+ relative to B14 or B15. */
+ tic6x_operand_mem_long,
+ /* A memory reference that only dereferences a register with no
+ further adjustments (*REG), that register being from the side
+ of the functional unit selected. */
+ tic6x_operand_mem_deref,
+ /* A functional unit name or a list thereof (for SPMASK and
+ SPMASKR). */
+ tic6x_operand_func_unit
+ } tic6x_operand_form;
+
+/* Whether something is, or can be, read or written. */
+typedef enum
+ {
+ tic6x_rw_none,
+ tic6x_rw_read,
+ tic6x_rw_write,
+ tic6x_rw_read_write
+ } tic6x_rw;
+
+/* Description of a source operand and how it is used. */
+typedef struct
+{
+ /* The syntactic form of the operand. */
+ tic6x_operand_form form;
+
+ /* For non-constant operands, the size in bytes (1, 2, 4, 5 or
+ 8). Ignored for constant operands. */
+ unsigned int size;
+
+ /* Whether the operand is read, written or both. In addition to the
+ operations described here, address registers are read on cycle 1
+ regardless of when the memory operand is read or written, and may
+ be modified as described by the addressing mode, and control
+ registers may be implicitly read by some instructions. There are
+ also some special cases not fully described by this
+ structure.
+
+ - For mpydp, the low part of src2 is read on cycles 1 and 3 but
+ not 2, and the high part on cycles 2 and 4 but not 3.
+
+ - The swap2 pseudo-operation maps to packlh2, reading the first
+ operand of swap2 twice. */
+ tic6x_rw rw;
+
+ /* The first and last cycles (1 for E1, etc.) at which the operand,
+ or the low part for two-register operands, is read or
+ written. */
+ unsigned short low_first;
+ unsigned short low_last;
+
+ /* Likewise, for the high part. */
+ unsigned short high_first;
+ unsigned short high_last;
+} tic6x_operand_info;
+
+/* Ways of converting an operand or functional unit specifier to a
+ field value. */
+typedef enum
+ {
+ /* Store an unsigned assembly-time constant (which must fit) in
+ the field. */
+ tic6x_coding_ucst,
+ /* Store a signed constant (which must fit) in the field. This
+ may be used both for assembly-time constants and for link-time
+ constants. */
+ tic6x_coding_scst,
+ /* Subtract one from an unsigned assembly-time constant (which
+ must be strictly positive before the subtraction) and store the
+ value (which must fit) in the field. */
+ tic6x_coding_ucst_minus_one,
+ /* Negate a signed assembly-time constant, and store the result of
+ negation (which must fit) in the field. Used only for
+ pseudo-operations. */
+ tic6x_coding_scst_negate,
+ /* Store an unsigned link-time constant, implicitly DP-relative
+ and counting in bytes, in the field. For expression operands,
+ assembly-time constants are encoded as-is. For memory
+ reference operands, the offset is encoded as-is if [] syntax is
+ used and shifted if () is used. */
+ tic6x_coding_ulcst_dpr_byte,
+ /* Store an unsigned link-time constant, implicitly DP-relative
+ and counting in half-words, in the field. For expression
+ operands, assembly-time constants are encoded as-is. For
+ memory reference operands, the offset is encoded as-is if []
+ syntax is used and shifted if () is used. */
+ tic6x_coding_ulcst_dpr_half,
+ /* Store an unsigned link-time constant, implicitly DP-relative
+ and counting in words, in the field. For expression operands,
+ assembly-time constants are encoded as-is. For memory
+ reference operands, the offset is encoded as-is if [] syntax is
+ used and shifted if () is used. */
+ tic6x_coding_ulcst_dpr_word,
+ /* Store the low 16 bits of a link-time constant in the field;
+ considered unsigned for disassembly. */
+ tic6x_coding_lcst_low16,
+ /* Store the high 16 bits of a link-time constant in the field;
+ considered unsigned for disassembly. */
+ tic6x_coding_lcst_high16,
+ /* Store a signed PC-relative value (address of label minus
+ address of fetch packet containing the current instruction,
+ counted in words) in the field. */
+ tic6x_coding_pcrel,
+ /* Likewise, but counting in half-words if in a header-based fetch
+ packet. */
+ tic6x_coding_pcrel_half,
+ /* Encode the register number (even number for a register pair) in
+ the field. When applied to a memory reference, encode the base
+ register. */
+ tic6x_coding_reg,
+ /* Store 0 for register B14, 1 for register B15. When applied to
+ a memory reference, encode the base register. */
+ tic6x_coding_areg,
+ /* Store the low part of a control register address. */
+ tic6x_coding_crlo,
+ /* Store the high part of a control register address. */
+ tic6x_coding_crhi,
+ /* Encode the even register number for a register pair, shifted
+ right by one bit. */
+ tic6x_coding_reg_shift,
+ /* Store either the offset register or the 5-bit unsigned offset
+ for a memory reference. If an offset uses the unscaled ()
+ form, which is only permitted with constants, it is scaled
+ according to the access size of the operand before being
+ stored. */
+ tic6x_coding_mem_offset,
+ /* Store either the offset register or the 5-bit unsigned offset
+ for a memory reference, but with no scaling applied to the
+ offset (for nonaligned doubleword operations). */
+ tic6x_coding_mem_offset_noscale,
+ /* Store the addressing mode for a memory reference. */
+ tic6x_coding_mem_mode,
+ /* Store whether a memory reference is scaled. */
+ tic6x_coding_scaled,
+ /* Store the stage in an SPKERNEL instruction in the upper part of
+ the field. */
+ tic6x_coding_fstg,
+ /* Store the cycle in an SPKERNEL instruction in the lower part of
+ the field. */
+ tic6x_coding_fcyc,
+ /* Store the mask bits for functional units in the field in an
+ SPMASK or SPMASKR instruction. */
+ tic6x_coding_spmask,
+ /* Store the number of a register that is unused, or minimally
+ used, in this execute packet. The number must be the same for
+ all uses of this coding in a single instruction, but may be
+ different for different instructions in the execute packet.
+ This is for the "zero" pseudo-operation. This is not safe when
+ reads may occur from instructions in previous execute packets;
+ in such cases the programmer or compiler should use explicit
+ "sub" instructions for those cases of "zero" that cannot be
+ implemented as "mvk" for the processor specified. */
+ tic6x_coding_reg_unused,
+ /* Store 1 if the functional unit used is on side B, 0 for side
+ A. */
+ tic6x_coding_fu,
+ /* Store 1 if the data path used (source register for store,
+ destination for load) is on side B, 0 for side A. */
+ tic6x_coding_data_fu,
+ /* Store 1 if the cross path is being used, 0 otherwise. */
+ tic6x_coding_xpath
+ } tic6x_coding_method;
+
+/* How to generate the value of a particular field. */
+typedef struct
+{
+ /* The name of the field. */
+ tic6x_insn_field_id field_id;
+
+ /* How it is encoded. */
+ tic6x_coding_method coding_method;
+
+ /* Source operand number, if any. */
+ unsigned int operand_num;
+} tic6x_coding_field;
+
+/* Types of instruction for pipeline purposes. The type determines
+ functional unit and cross path latency (when the same functional
+ unit can be used by other instructions, when the same cross path
+ can be used by other instructions). */
+typedef enum
+ {
+ tic6x_pipeline_nop,
+ tic6x_pipeline_1cycle,
+ tic6x_pipeline_1616_m,
+ tic6x_pipeline_store,
+ tic6x_pipeline_mul_ext,
+ tic6x_pipeline_load,
+ tic6x_pipeline_branch,
+ tic6x_pipeline_2cycle_dp,
+ tic6x_pipeline_4cycle,
+ tic6x_pipeline_intdp,
+ tic6x_pipeline_dpcmp,
+ tic6x_pipeline_addsubdp,
+ tic6x_pipeline_mpyi,
+ tic6x_pipeline_mpyid,
+ tic6x_pipeline_mpydp,
+ tic6x_pipeline_mpyspdp,
+ tic6x_pipeline_mpysp2dp
+ } tic6x_pipeline_type;
+
+/* Description of a control register. */
+typedef struct
+{
+ /* The name of the register. */
+ const char *name;
+
+ /* Which ISA variants include this control register. */
+ unsigned short isa_variants;
+
+ /* Whether it can be read, written or both (in supervisor mode).
+ Some registers use the same address, but different names, for
+ reading and writing. */
+ tic6x_rw rw;
+
+ /* crlo value for this register. */
+ unsigned int crlo;
+
+ /* Mask that, ANDed with the crhi value in the instruction, must be
+ 0. 0 is always generated when generating code. */
+ unsigned int crhi_mask;
+} tic6x_ctrl;
+
+/* An index into the table of control registers. */
+typedef enum
+ {
+#define CTRL(name, isa, rw, crlo, crhi_mask) \
+ CONCAT2(tic6x_ctrl_,name),
+#include "tic6x-control-registers.h"
+#undef CTRL
+ tic6x_ctrl_max
+ } tic6x_ctrl_id;
+
+/* The table itself. */
+extern const tic6x_ctrl tic6x_ctrl_table[tic6x_ctrl_max];
+
+/* An entry in the opcode table. */
+typedef struct
+{
+ /* The name of the instruction. */
+ const char *name;
+
+ /* Functional unit used by this instruction (basic information). */
+ tic6x_func_unit_base func_unit;
+
+ /* The format of this instruction. */
+ tic6x_insn_format_id format;
+
+ /* The pipeline type of this instruction. */
+ tic6x_pipeline_type type;
+
+ /* Which ISA variants include this instruction. */
+ unsigned short isa_variants;
+
+ /* Flags for this instruction. */
+ unsigned short flags;
+
+ /* Number of fixed fields, or fields with restricted value ranges,
+ for this instruction. */
+ unsigned int num_fixed_fields;
+
+ /* Values of fields fixed for this instruction. */
+ tic6x_fixed_field fixed_fields[TIC6X_MAX_FIXED_FIELDS];
+
+ /* The number of operands in the source form of this
+ instruction. */
+ unsigned int num_operands;
+
+ /* Information about individual operands. */
+ tic6x_operand_info operand_info[TIC6X_MAX_OPERANDS];
+
+ /* The number of variable fields for this instruction with encoding
+ instructions explicitly given. */
+ unsigned int num_variable_fields;
+
+ /* How fields (other than ones with fixed value) are computed from
+ the source operands and functional unit specifiers. In addition
+ to fields specified here:
+
+ - creg, if present, is set from the predicate, along with z which
+ must be present if creg is present.
+
+ - p, if present (on all non-compact instructions), is set from
+ the parallel bars.
+ */
+ tic6x_coding_field variable_fields[TIC6X_MAX_VAR_FIELDS];
+} tic6x_opcode;
+
+/* An index into the table of opcodes. */
+typedef enum
+ {
+#define INSN(name, func_unit, format, type, isa, flags, fixed, ops, var) \
+ CONCAT6(tic6x_opcode_,name,_,func_unit,_,format),
+#define INSNE(name, e, func_unit, format, type, isa, flags, fixed, ops, var) \
+ CONCAT4(tic6x_opcode_,name,_,e),
+#include "tic6x-opcode-table.h"
+#undef INSN
+#undef INSNE
+ tic6x_opcode_max
+ } tic6x_opcode_id;
+
+/* The table itself. */
+extern const tic6x_opcode tic6x_opcode_table[tic6x_opcode_max];
+
+/* A linked list of opcodes. */
+typedef struct tic6x_opcode_list_tag
+{
+ tic6x_opcode_id id;
+ struct tic6x_opcode_list_tag *next;
+} tic6x_opcode_list;
+
+/* The information from a fetch packet header. */
+typedef struct
+{
+ /* The header itself. */
+ unsigned int header;
+
+ /* Whether each word uses compact instructions. */
+ bfd_boolean word_compact[7];
+
+ /* Whether loads are protected. */
+ bfd_boolean prot;
+
+ /* Whether instructions use the high register set. */
+ bfd_boolean rs;
+
+ /* Data size. */
+ unsigned int dsz;
+
+ /* Whether compact instructions in the S unit are decoded as
+ branches. */
+ bfd_boolean br;
+
+ /* Whether compact instructions saturate. */
+ bfd_boolean sat;
+
+ /* P-bits. */
+ bfd_boolean p_bits[14];
+} tic6x_fetch_packet_header;
+
+#endif /* OPCODE_TIC6X_H */
diff --git a/external/gpl3/binutils/dist/include/opcode/tic80.h b/external/gpl3/binutils/dist/include/opcode/tic80.h
index c89b81c6d70..43c84be574f 100644
--- a/external/gpl3/binutils/dist/include/opcode/tic80.h
+++ b/external/gpl3/binutils/dist/include/opcode/tic80.h
@@ -1,22 +1,23 @@
/* tic80.h -- Header file for TI TMS320C80 (MV) opcode table
- Copyright 1996, 1997, 2003 Free Software Foundation, Inc.
+ Copyright 1996, 1997, 2003, 2010 Free Software Foundation, Inc.
Written by Fred Fish (fnf@cygnus.com), Cygnus Support
-This file is part of GDB, GAS, and the GNU binutils.
+ This file is part of GDB, GAS, and the GNU binutils.
-GDB, GAS, and the GNU binutils are free software; you can redistribute
-them and/or modify them under the terms of the GNU General Public
-License as published by the Free Software Foundation; either version
-1, or (at your option) any later version.
+ GDB, GAS, and the GNU binutils are free software; you can redistribute
+ them and/or modify them under the terms of the GNU General Public
+ License as published by the Free Software Foundation; either version 3,
+ or (at your option) any later version.
-GDB, GAS, and the GNU binutils are distributed in the hope that they
-will be useful, but WITHOUT ANY WARRANTY; without even the implied
-warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
-the GNU General Public License for more details.
+ GDB, GAS, and the GNU binutils are distributed in the hope that they
+ will be useful, but WITHOUT ANY WARRANTY; without even the implied
+ warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
+ the GNU General Public License for more details.
-You should have received a copy of the GNU General Public License
-along with this file; see the file COPYING. If not, write to the Free
-Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
+ You should have received a copy of the GNU General Public License
+ along with this file; see the file COPYING3. If not, write to the Free
+ Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
+ MA 02110-1301, USA. */
#ifndef TIC80_H
#define TIC80_H
diff --git a/external/gpl3/binutils/dist/include/opcode/v850.h b/external/gpl3/binutils/dist/include/opcode/v850.h
index 436ff399684..59033059179 100644
--- a/external/gpl3/binutils/dist/include/opcode/v850.h
+++ b/external/gpl3/binutils/dist/include/opcode/v850.h
@@ -1,22 +1,23 @@
/* v850.h -- Header file for NEC V850 opcode table
- Copyright 1996, 1997, 2001, 2003 Free Software Foundation, Inc.
+ Copyright 1996, 1997, 2001, 2003, 2010 Free Software Foundation, Inc.
Written by J.T. Conklin, Cygnus Support
-This file is part of GDB, GAS, and the GNU binutils.
+ This file is part of GDB, GAS, and the GNU binutils.
-GDB, GAS, and the GNU binutils are free software; you can redistribute
-them and/or modify them under the terms of the GNU General Public
-License as published by the Free Software Foundation; either version
-1, or (at your option) any later version.
+ GDB, GAS, and the GNU binutils are free software; you can redistribute
+ them and/or modify them under the terms of the GNU General Public
+ License as published by the Free Software Foundation; either version 3,
+ or (at your option) any later version.
-GDB, GAS, and the GNU binutils are distributed in the hope that they
-will be useful, but WITHOUT ANY WARRANTY; without even the implied
-warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
-the GNU General Public License for more details.
+ GDB, GAS, and the GNU binutils are distributed in the hope that they
+ will be useful, but WITHOUT ANY WARRANTY; without even the implied
+ warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
+ the GNU General Public License for more details.
-You should have received a copy of the GNU General Public License
-along with this file; see the file COPYING. If not, write to the Free
-Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
+ You should have received a copy of the GNU General Public License
+ along with this file; see the file COPYING3. If not, write to the Free
+ Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
+ MA 02110-1301, USA. */
#ifndef V850_H
#define V850_H
@@ -54,12 +55,18 @@ struct v850_opcode
};
/* Values for the processors field in the v850_opcode structure. */
+#define PROCESSOR_MASK 0x1f
+#define PROCESSOR_OPTION_EXTENSION (1 << 5) /* Enable extension opcodes. */
+#define PROCESSOR_OPTION_ALIAS (1 << 6) /* Enable alias opcodes. */
#define PROCESSOR_V850 (1 << 0) /* Just the V850. */
-#define PROCESSOR_ALL -1 /* Any processor. */
-#define PROCESSOR_V850E (1 << 1) /* Just the V850E. */
-#define PROCESSOR_NOT_V850 (~ PROCESSOR_V850) /* Any processor except the V850. */
-#define PROCESSOR_V850EA (1 << 2) /* Just the V850EA. */
-#define PROCESSOR_V850E1 (1 << 3) /* Just the V850E1. */
+#define PROCESSOR_ALL PROCESSOR_MASK /* Any processor. */
+#define PROCESSOR_V850E (1 << 1) /* Just the V850E. */
+#define PROCESSOR_NOT_V850 (PROCESSOR_ALL & (~ PROCESSOR_V850)) /* Any processor except the V850. */
+#define PROCESSOR_V850E1 (1 << 2) /* Just the V850E1. */
+#define PROCESSOR_V850E2 (1 << 3) /* Just the V850E2. */
+#define PROCESSOR_V850E2V3 (1 << 4) /* Just the V850E2V3. */
+#define PROCESSOR_V850E2_ALL (PROCESSOR_V850E2 | PROCESSOR_V850E2V3) /* V850E2 & V850E2V3. */
+#define SET_PROCESSOR_MASK(mask,set) ((mask) = ((mask) & ~PROCESSOR_MASK) | (set))
/* The table itself is sorted by major opcode number, and is otherwise
in the order in which the disassembler should consider
@@ -73,7 +80,8 @@ extern const int v850_num_opcodes;
struct v850_operand
{
/* The number of bits in the operand. */
- /* If this value is -1 then the operand's bits are in a discontinous distribution in the instruction. */
+ /* If this value is -1 then the operand's bits are in a discontinous
+ distribution in the instruction. */
int bits;
/* (bits >= 0): How far the operand is left shifted in the instruction. */
@@ -119,6 +127,8 @@ struct v850_operand
/* One bit syntax flags. */
int flags;
+
+ int default_reloc;
};
/* Elements in the table are retrieved by indexing with values from
@@ -128,39 +138,70 @@ extern const struct v850_operand v850_operands[];
/* Values defined for the flags field of a struct v850_operand. */
-/* This operand names a general purpose register */
+/* This operand names a general purpose register. */
#define V850_OPERAND_REG 0x01
-/* This operand names a system register */
-#define V850_OPERAND_SRG 0x02
+/* This operand is the ep register. */
+#define V850_OPERAND_EP 0x02
-/* This operand names a condition code used in the setf instruction */
-#define V850_OPERAND_CC 0x04
+/* This operand names a system register. */
+#define V850_OPERAND_SRG 0x04
-/* This operand takes signed values */
-#define V850_OPERAND_SIGNED 0x08
+/* Prologue eilogue type instruction, V850E specific. */
+#define V850E_OPERAND_REG_LIST 0x08
-/* This operand is the ep register. */
-#define V850_OPERAND_EP 0x10
+/* This operand names a condition code used in the setf instruction. */
+#define V850_OPERAND_CC 0x10
-/* This operand is a PC displacement */
-#define V850_OPERAND_DISP 0x20
+#define V850_OPERAND_FLOAT_CC 0x20
-/* This is a relaxable operand. Only used for D9->D22 branch relaxing
- right now. We may need others in the future (or maybe handle them like
- promoted operands on the mn10300?) */
-#define V850_OPERAND_RELAX 0x40
+/* This operand names a vector purpose register. */
+#define V850_OPERAND_VREG 0x40
-/* The register specified must not be r0 */
-#define V850_NOT_R0 0x80
+/* 16 bit immediate follows instruction, V850E specific. */
+#define V850E_IMMEDIATE16 0x80
-/* push/pop type instruction, V850E specific. */
-#define V850E_PUSH_POP 0x100
+/* hi16 bit immediate follows instruction, V850E specific. */
+#define V850E_IMMEDIATE16HI 0x100
-/* 16 bit immediate follows instruction, V850E specific. */
-#define V850E_IMMEDIATE16 0x200
+/* 23 bit immediate follows instruction, V850E specific. */
+#define V850E_IMMEDIATE23 0x200
/* 32 bit immediate follows instruction, V850E specific. */
#define V850E_IMMEDIATE32 0x400
+/* This is a relaxable operand. Only used for D9->D22 branch relaxing
+ right now. We may need others in the future (or maybe handle them like
+ promoted operands on the mn10300?). */
+#define V850_OPERAND_RELAX 0x800
+
+/* This operand takes signed values. */
+#define V850_OPERAND_SIGNED 0x1000
+
+/* This operand is a displacement. */
+#define V850_OPERAND_DISP 0x2000
+
+/* This operand is a PC displacement. */
+#define V850_PCREL 0x4000
+
+/* The register specified must be even number. */
+#define V850_REG_EVEN 0x8000
+
+/* The register specified must not be r0. */
+#define V850_NOT_R0 0x20000
+
+/* The register specified must not be 0. */
+#define V850_NOT_IMM0 0x40000
+
+/* The condition code must not be SA CONDITION. */
+#define V850_NOT_SA 0x80000
+
+/* The operand has '!' prefix. */
+#define V850_OPERAND_BANG 0x100000
+
+/* The operand has '%' prefix. */
+#define V850_OPERAND_PERCENT 0x200000
+
+extern int v850_msg_is_out_of_range (const char * msg);
+
#endif /* V850_H */
diff --git a/external/gpl3/binutils/dist/include/opcode/vax.h b/external/gpl3/binutils/dist/include/opcode/vax.h
index a521303960f..f5cdd24397f 100644
--- a/external/gpl3/binutils/dist/include/opcode/vax.h
+++ b/external/gpl3/binutils/dist/include/opcode/vax.h
@@ -1,21 +1,22 @@
/* Vax opcde list.
- Copyright 1989, 1991, 1992, 1995 Free Software Foundation, Inc.
+ Copyright 1989, 1991, 1992, 1995, 2010 Free Software Foundation, Inc.
-This file is part of GDB and GAS.
+ This file is part of GDB and GAS.
-GDB and GAS are free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 1, or (at your option)
-any later version.
+ GDB and GAS are free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
-GDB and GAS are distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
+ GDB and GAS are distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
-You should have received a copy of the GNU General Public License
-along with GDB or GAS; see the file COPYING. If not, write to
-the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
+ You should have received a copy of the GNU General Public License
+ along with GDB or GAS; see the file COPYING3. If not, write to
+ the Free Software Foundation, 51 Franklin Street - Fifth Floor,
+ Boston, MA 02110-1301, USA. */
#ifndef vax_opcodeT
#define vax_opcodeT int