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authorskrll <skrll@NetBSD.org>2006-02-02 20:58:06 +0000
committerskrll <skrll@NetBSD.org>2006-02-02 20:58:06 +0000
commit8d2c6a4e34b1fbb538663dee24b3dce5a6ad7ce8 (patch)
tree01a760df00b921200616456eed856334b4fdd092 /gnu/dist/binutils/include
parent27523fbf84c1ee6539d56f021f9ed5f7f9a0dd70 (diff)
Import binutils 2.16.1.
Diffstat (limited to 'gnu/dist/binutils/include')
-rw-r--r--gnu/dist/binutils/include/ChangeLog2363
-rw-r--r--gnu/dist/binutils/include/ansidecl.h31
-rw-r--r--gnu/dist/binutils/include/aout/aout64.h2
-rw-r--r--gnu/dist/binutils/include/bfdlink.h97
-rw-r--r--gnu/dist/binutils/include/bin-bugs.h2
-rw-r--r--gnu/dist/binutils/include/coff/ChangeLog33
-rw-r--r--gnu/dist/binutils/include/coff/arm.h2
-rw-r--r--gnu/dist/binutils/include/coff/ecoff.h30
-rw-r--r--gnu/dist/binutils/include/coff/ia64.h2
-rw-r--r--gnu/dist/binutils/include/coff/internal.h4
-rw-r--r--gnu/dist/binutils/include/coff/maxq.h56
-rw-r--r--gnu/dist/binutils/include/coff/mcore.h2
-rw-r--r--gnu/dist/binutils/include/coff/mips.h32
-rw-r--r--gnu/dist/binutils/include/coff/mipspe.h2
-rw-r--r--gnu/dist/binutils/include/coff/pe.h7
-rw-r--r--gnu/dist/binutils/include/coff/rs6000.h2
-rw-r--r--gnu/dist/binutils/include/coff/rs6k64.h2
-rw-r--r--gnu/dist/binutils/include/coff/sh.h2
-rw-r--r--gnu/dist/binutils/include/coff/symconst.h2
-rw-r--r--gnu/dist/binutils/include/coff/ti.h2
-rw-r--r--gnu/dist/binutils/include/coff/tic54x.h2
-rw-r--r--gnu/dist/binutils/include/coff/xcoff.h4
-rw-r--r--gnu/dist/binutils/include/demangle.h2
-rw-r--r--gnu/dist/binutils/include/dis-asm.h18
-rw-r--r--gnu/dist/binutils/include/dyn-string.h31
-rw-r--r--gnu/dist/binutils/include/elf/ChangeLog150
-rw-r--r--gnu/dist/binutils/include/elf/alpha.h2
-rw-r--r--gnu/dist/binutils/include/elf/arm.h47
-rw-r--r--gnu/dist/binutils/include/elf/avr.h29
-rw-r--r--gnu/dist/binutils/include/elf/common.h12
-rw-r--r--gnu/dist/binutils/include/elf/cr16c.h258
-rw-r--r--gnu/dist/binutils/include/elf/cris.h14
-rw-r--r--gnu/dist/binutils/include/elf/crx.h53
-rw-r--r--gnu/dist/binutils/include/elf/dwarf2.h5
-rw-r--r--gnu/dist/binutils/include/elf/external.h2
-rw-r--r--gnu/dist/binutils/include/elf/frv.h20
-rw-r--r--gnu/dist/binutils/include/elf/i386.h5
-rw-r--r--gnu/dist/binutils/include/elf/ia64.h3
-rw-r--r--gnu/dist/binutils/include/elf/internal.h4
-rw-r--r--gnu/dist/binutils/include/elf/iq2000.h2
-rw-r--r--gnu/dist/binutils/include/elf/m32r.h5
-rw-r--r--gnu/dist/binutils/include/elf/m68k.h2
-rw-r--r--gnu/dist/binutils/include/elf/mips.h35
-rw-r--r--gnu/dist/binutils/include/elf/mn10300.h2
-rw-r--r--gnu/dist/binutils/include/elf/msp430.h4
-rw-r--r--gnu/dist/binutils/include/elf/ppc.h8
-rw-r--r--gnu/dist/binutils/include/elf/s390.h2
-rw-r--r--gnu/dist/binutils/include/elf/sh.h85
-rw-r--r--gnu/dist/binutils/include/elf/sparc.h3
-rw-r--r--gnu/dist/binutils/include/elf/v850.h4
-rw-r--r--gnu/dist/binutils/include/elf/x86-64.h6
-rw-r--r--gnu/dist/binutils/include/elf/xtensa.h112
-rw-r--r--gnu/dist/binutils/include/fibheap.h2
-rw-r--r--gnu/dist/binutils/include/gdb/ChangeLog41
-rw-r--r--gnu/dist/binutils/include/gdb/callback.h58
-rw-r--r--gnu/dist/binutils/include/gdb/sim-ppc.h771
-rw-r--r--gnu/dist/binutils/include/gdb/sim-sh.h15
-rw-r--r--gnu/dist/binutils/include/hashtab.h17
-rw-r--r--gnu/dist/binutils/include/libiberty.h51
-rw-r--r--gnu/dist/binutils/include/obstack.h4
-rw-r--r--gnu/dist/binutils/include/opcode/ChangeLog182
-rw-r--r--gnu/dist/binutils/include/opcode/arm.h390
-rw-r--r--gnu/dist/binutils/include/opcode/avr.h17
-rw-r--r--gnu/dist/binutils/include/opcode/cgen.h5
-rw-r--r--gnu/dist/binutils/include/opcode/cris.h79
-rw-r--r--gnu/dist/binutils/include/opcode/crx.h418
-rw-r--r--gnu/dist/binutils/include/opcode/h8300.h5
-rw-r--r--gnu/dist/binutils/include/opcode/hppa.h2
-rw-r--r--gnu/dist/binutils/include/opcode/i386.h1060
-rw-r--r--gnu/dist/binutils/include/opcode/i860.h2
-rw-r--r--gnu/dist/binutils/include/opcode/ia64.h2
-rw-r--r--gnu/dist/binutils/include/opcode/m68k.h63
-rw-r--r--gnu/dist/binutils/include/opcode/m88k.h3
-rw-r--r--gnu/dist/binutils/include/opcode/maxq.h1132
-rw-r--r--gnu/dist/binutils/include/opcode/mips.h21
-rw-r--r--gnu/dist/binutils/include/opcode/mn10300.h2
-rw-r--r--gnu/dist/binutils/include/opcode/msp430.h16
-rw-r--r--gnu/dist/binutils/include/opcode/ppc.h2
-rw-r--r--gnu/dist/binutils/include/opcode/s390.h2
-rw-r--r--gnu/dist/binutils/include/opcode/tic54x.h2
-rw-r--r--gnu/dist/binutils/include/splay-tree.h12
-rw-r--r--gnu/dist/binutils/include/xtensa-config.h15
-rw-r--r--gnu/dist/binutils/include/xtensa-isa-internal.h234
-rw-r--r--gnu/dist/binutils/include/xtensa-isa.h846
84 files changed, 5655 insertions, 3422 deletions
diff --git a/gnu/dist/binutils/include/ChangeLog b/gnu/dist/binutils/include/ChangeLog
index 9ea1d2a4b34..d83b4da32db 100644
--- a/gnu/dist/binutils/include/ChangeLog
+++ b/gnu/dist/binutils/include/ChangeLog
@@ -1,2157 +1,352 @@
-2004-04-08 Alan Modra <amodra@bigpond.net.au>
+2005-03-22 Bob Wilson <bob.wilson@acm.org>
- Apply from mainline.
- 2004-03-20 H.J. Lu <hongjiu.lu@intel.com>
- * bfdlink.h (bfd_link_info): Correct comments for the
- unresolved_syms_in_objects field.
-
-2004-03-23 Alan Modra <amodra@bigpond.net.au>
-
- PR 51.
- * bfdlink.h (struct bfd_link_info): Add wrap_char.
-
-2004-01-12 Ian Lance Taylor <ian@wasabisystems.com>
-
- * demangle.h: Instead of checking ANSI_PROTOTYPES, just include
- "libiberty.h".
-
- * demangle.h: If ANSI_PROTOTYPES is defined, include <stddef.h>.
-
- * demangle.h (enum demangle_component_type): Define.
- (struct demangle_operator_info): Declare.
- (struct demangle_builtin_type_info): Declare.
- (struct demangle_component): Define.
- (cplus_demangle_fill_component): Declare.
- (cplus_demangle_fill_name): Declare.
- (cplus_demangle_fill_builtin_type): Declare.
- (cplus_demangle_fill_operator): Declare.
- (cplus_demangle_fill_extended_operator): Declare.
- (cplus_demangle_fill_ctor, cplus_demangle_fill_dtor): Declare.
- (cplus_demangle_v3_components): Declare.
- (cplus_demangle_print): Declare.
-
-2003-12-19 Andreas Tobler <a.tobler@schweiz.ch>
-
- * include/fibheap.h (fibnode): Use __extension__ for
- bit-fields mark and degree if __GNUC__.
-
-2003-12-18 Kazu Hirata <kazu@cs.umass.edu>
-
- * include/fibheap.h (fibnode): Use unsigned long int for
- bit-fields if __GNUC__ is defined.
-
-2003-10-22 Joseph S. Myers <jsm@polyomino.org.uk>
-
- * obstack.h: Merge the following change from gnulib:
- 2003-10-21 Paul Eggert <eggert@twinsun.com>
- * obstack.h (obstack_1grow_fast): Properly parenthesize arg.
- (obstack_ptr_grow_fast, obstack_int_grow_fast):
- Don't use lvalue casts, as GCC plans to remove support for them
- in GCC 3.5. Reported by Joseph S. Myers. This bug
- was also present in the non-GCC version, indicating that this
- code had always been buggy and had never been widely used.
- (obstack_1grow, obstack_ptr_grow, obstack_int_grow, obstack_blank):
- Use the fast variant of each macro, rather than copying the
- definiens of the fast variant; that way, we'll be more likely to
- catch future bugs in the fast variants.
-
-2003-09-22 Andrew Cagney <cagney@redhat.com>
-
- * floatformat.h (struct floatformat): Add field "is_valid".
-
-2003-09-15 Andrew Cagney <cagney@redhat.com>
-
- * floatformat.h (floatformat_to_double): Make input buffer constant.
- (floatformat_from_double, floatformat_is_valid): Ditto.
-
-2003-09-15 Andrew Cagney <cagney@redhat.com>
-
- * floatformat.h (struct floatformat): Make "exp_bias" signed.
-
-2003-09-15 Daniel Jacobowitz <drow@mvista.com>
-
- * floatformat.h (floatformat_is_valid): Add prototype.
-
-2003-07-09 Bob Wilson <bob.wilson@acm.org>
-
- * xtensa-config.h: Undef all macros before defining them.
-
-2003-07-06 H.J. Lu <hongjiu.lu@intel.com>
-
- * demangle.h: Support C++.
-
-2003-07-01 Zack Weinberg <zack@codesourcery.com>
-
- * filenames.h: New file imported from binutils.
-
-2003-06-30 Bob Wilson <bob.wilson@acm.org>
-
- * xtensa-config.h: New file imported from binutils.
-
-2003-06-22 Zack Weinberg <zack@codesourcery.com>
-
- * safe-ctype.h (HC_UNKNOWN, HC_ASCII, HC_EBCDIC): Rename to
- HOST_CHARSET_UNKNOWN, HOST_CHARSET_ASCII, HOST_CHARSET_EBCDIC
- respectively.
-
-2003-06-21 Zack Weinberg <zack@codesourcery.com>
-
- * safe-ctype.h (HC_UNKNOWN, HC_ASCII, HC_EBCDIC, HOST_CHARSET):
- New #defines.
-
-2003-06-17 Kaveh R. Ghazi <ghazi@caip.rutgers.edu>
-
- * ansidecl.h: Delete HAVE_LONG_DOUBLE GCC bootstrap support.
-
-2003-05-15 Jim Blandy <jimb@redhat.com>
-
- * libiberty.h (hex_value): Make the value an unsigned int, to
- avoid unexpected sign-extension when cast to unsigned types larger
- than int --- like bfd_vma, on some platforms.
- (_hex_value): Update declaration.
-
-2003-05-07 Jason Merrill <jason@redhat.com>
-
- * hashtab.h (iterative_hash): Prototype.
- (iterative_hash_object): New macro.
-
-2003-03-17 Kaveh R. Ghazi <ghazi@caip.rutgers.edu>
-
- * ansidecl.h (ATTRIBUTE_NONNULL, ATTRIBUTE_NULL_PRINTF,
- ATTRIBUTE_NULL_PRINTF_1, ATTRIBUTE_NULL_PRINTF_2,
- ATTRIBUTE_NULL_PRINTF_3, ATTRIBUTE_NULL_PRINTF_4,
- ATTRIBUTE_NULL_PRINTF_5): New.
- (ATTRIBUTE_PRINTF): Add ATTRIBUTE_NONNULL.
-
-2003-03-17 Jan Hubicka <jh@suse.cz>
-
- * hashtab.h (htab_traverse_noresize): Declare.
-
-2003-02-27 Kaveh R. Ghazi <ghazi@caip.rutgers.edu>
-
- * libiberty.h: Document return value of physmem routines.
-
-2003-02-20 Kaveh R. Ghazi <ghazi@caip.rutgers.edu>
-
- * libiberty.h (physmem_total, physmem_available): Prototype.
-
-2003-02-20 Daniel Jacobowitz <drow@mvista.com>
-
- * libiberty.h (lrealpath): Add declaration.
-
-2003-01-26 Daniel Jacobowitz <drow@mvista.com>
-
- * hashtab.h (htab_alloc_with_arg, htab_free_with_arg): Add new types.
- (struct htab): Add alloc_arg, alloc_with_arg_f, free_with_arg_f.
- (htab_create_alloc_ex): New prototype.
- (htab_set_functions_ex): New prototype.
-
-2002-07-17 Geoffrey Keating <geoffk@redhat.com>
-
- * splay-tree.h (GTY): Define if undefined.
- (splay_tree_allocate_fn): Return PTR for compatibility, not void *.
- (struct splay_tree_node_s): Support gengtype.
- (struct splay_tree_s): Likewise. Make allocate_data a PTR,
- not a void *.
-
-2002-11-23 Simon Burge <simonb@wasabisystems.com>
-
- * libiberty.h (basename): Add NetBSD to the list.
-
-2002-11-22 Daniel Jacobowitz <drow@mvista.com>
-
- * libiberty.h (make_relative_prefix): Add prototype.
-
-2002-10-26 Roger Sayle <roger@eyesopen.com>
-
- * partition.h: Close the extern "C" scope when compiling with C++.
-
-2002-10-26 Roger Sayle <roger@eyesopen.com>
- DJ Delorie <dj@redhat.com>
-
- PR bootstrap/8351
- * getopt.h: Avoid prototyping getopt with no arguments in C++.
-
-2002-10-24 Nathan Tallent <eraxxon@alumni.rice.edu>
-
- * ansidecl.h (__STDC__): Add (__alpha && __cplusplus) to the
- list of platform compilers that may look, smell and act
- like __STDC__ but that may not define it.
-
-2002-10-11 David O'Brien <obrien@FreeBSD.org>
-
- * getopt.h: getopt is in unistd.h (based on SUSv2).
-
-2002-09-19 Alexandre Oliva <aoliva@redhat.com>
-
- * libiberty.h (asprintf, vasprintf): Don't declare them if the
- corresponding HAVE_DECL_ macro is 1.
-
-2002-06-25 Alan Modra <amodra@bigpond.net.au>
-
- * demangle.h: #include "ansidecl.h" rather than #include <ansidecl.h>.
- * fibheap.h: Likewise.
- * hashtab.h: Likewise.
- * partition.h: Likewise.
- * sort.h: Likewise.
- * splay-tree.h: Likewise.
-
-2002-06-24 Alan Modra <amodra@bigpond.net.au>
-
- * libiberty.h (basename): Don't declare if HAVE_DECL_BASENAME.
- * getopt.h (getopt): Don't declare if HAVE_DECL_GETOPT.
-
-2002-06-06 DJ Delorie <dj@redhat.com>
-
- * hashtab.h (htab): Rearrange new members for backward
- compatibility.
- (htab_create): Don't use a macro that requires other headers.
-
-2002-06-05 Geoffrey Keating <geoffk@redhat.com>
-
- * hashtab.h (htab_create): Restore prototype for backward
- compatibility.
- (htab_try_create): Likewise.
-
-2002-05-22 Geoffrey Keating <geoffk@redhat.com>
-
- * hashtab.h (struct htab): Update for change to length specifier.
-
-2002-05-10 Geoffrey Keating <geoffk@redhat.com>
-
- * hashtab.h (GTY): Define if undefined.
- (htab_alloc): New typedef.
- (htab_free): New typedef.
- (struct htab): Support gengtype; allow user-specified memory
- allocation.
- (htab_create_alloc): New.
- (htab_create): Replace with #define.
- (htab_try_create): Delete.
-
-2002-04-16 David S. Miller <davem@redhat.com>
-
- * xregex2.h (__restrict_arr): Define to __restrict on GCC
- 3.1 and later. Do not redefine.
-
-2002-04-01 Phil Edwards <pme@gcc.gnu.org>
-
- * dyn-string.h: Also allow IN_GLIBCPP_V3 to redefine names.
-
-2002-03-06 Andrew Cagney <ac131313@redhat.com>
-
- * floatformat.h (floatformat_arm_ext): Delete declaration.
-
-2002-02-22 Jim Blandy <jimb@redhat.com>
-
- Allow the user to specify functions for allocating memory for
- splay tree roots and nodes.
- * splay-tree.h (splay_tree_allocate_fn, splay_tree_deallocate_fn):
- New types.
- (splay_tree): New fields: `allocate', `deallocate', and
- `allocate_data'.
- (splay_tree_new_with_allocator): New function declaration.
-
-2002-02-05 Jason Merrill <jason@redhat.com>
-
- * demangle.h (cplus_demangle_v3): Add "options" parm.
- (cplus_demangle_v3_type): Remove prototype.
- (DMGL_VERBOSE): New macro.
- (DMGL_TYPES): New macro.
-
-2002-02-02 H.J. Lu (hjl@gnu.org)
-
- * demangle.h (cplus_demangle_v3_type): New prototype.
-
-2002-01-28 Kaveh R. Ghazi <ghazi@caip.rutgers.edu>
-
- * libiberty.h (C_alloca): Add ATTRIBUTE_MALLOC.
-
-2001-12-06 Richard Henderson <rth@redhat.com>
-
- * demangle.h (no_demangling): New.
- (NO_DEMANGLING_STYLE_STRING): New.
-
-2001-10-24 Neil Booth <neil@daikokuya.demon.co.uk>
-
- * safe-ctype.h (_sch_isbasic, IS_ISOBASIC): New.
-
-2001-10-22 Kaveh R. Ghazi <ghazi@caip.rutgers.edu>
-
- * libiberty.h (hex_init): Revert delete.
-
- * libiberty.h (_hex_value): Const-ify.
- (hex_init): Delete.
-
-2001-10-07 Kaveh R. Ghazi <ghazi@caip.rutgers.edu>
-
- * demangle.h (demangler_engine): Const-ify.
- * libiberty.h (buildargv): Likewise.
-
-2001-09-24 Kaveh R. Ghazi <ghazi@caip.rutgers.edu>
-
- * libiberty.h (reconcat): New function.
-
-2001-09-18 Kaveh R. Ghazi <ghazi@caip.rutgers.edu>
-
- * libiberty.h (concat, concat_length, concat_copy, concat_copy2,
- ACONCAT): Improve comments.
-
-2001-09-18 Alan Modra <amodra@bigpond.net.au>
-
- * objalloc.h (OBJALLOC_ALIGN): Define using offsetof.
-
-2001-09-17 Kaveh R. Ghazi <ghazi@caip.rutgers.edu>
-
- * libiberty.h (concat_length, concat_copy, concat_copy2,
- libiberty_concat_ptr, ACONCAT): New.
-
- * libiberty.h (ASTRDUP): New macro.
- libiberty_optr, libiberty_nptr, libiberty_len): Declare.
-
-2001-08-29 Kaveh R. Ghazi <ghazi@caip.rutgers.edu>
-
- * ansidecl.h: Update comments reflecting previous change.
-
-2001-08-27 Kaveh R. Ghazi <ghazi@caip.rutgers.edu>
-
- * ansidecl.h (VA_OPEN, VA_CLOSE): Allow multiple uses.
-
-2001-08-23 Lars Brinkhoff <lars@nocrew.org>
-
- * dyn-string.h, fibheap.h, partition.h, sort.h, splay-tree.h:
- replace "GNU CC" with "GCC".
-
-2001-08-21 Richard Henderson <rth@redhat.com>
-
- * fibheap.h: Tidy formatting.
- (fibnode_t): Limit degree to 31 bits to avoid warning.
-
-2001-08-20 Andrew Cagney <ac131313@redhat.com>
-
- * floatformat.h (floatformat_arm_ext): Document as deprecated.
- (floatformat_arm_ext_big, floatformat_arm_ext_littlebyte_bigword)
- (floatformat_ia64_spill_little, floatformat_ia64_quad_little)
- (floatformat_ia64_spill_big, floatformat_ia64_quad_big)
- (floatformat_m88110_harris_ext): Declare.
-
-2001-08-20 Daniel Berlin <dan@cgsoftware.com>
-
- * fibheap.h: New file. Fibonacci heap.
-
-2001-08-18 Zack Weinberg <zackw@panix.com>
-
- * ansidecl.h: Reorganize for readability, remove documentation
- of obsolete macros, document PARAMS and VPARAMS. Add new
- macros VA_OPEN, VA_CLOSE, and VA_FIXEDARG for nicer variadic
- function implementation.
-
-2001-08-16 Richard Henderson <rth@redhat.com>
-
- * hashtab.h (htab_hash_string): Declare.
-
-2001-08-10 Andrew Cagney <ac131313@redhat.com>
-
- * libiberty.h (lbasename): Change function declaration to return a
- const char pointer.
-
-2001-08-02 Mark Kettenis <kettenis@gnu.org>
-
- * xregex.h (_REGEX_RE_COMP): Define.
- (re_comp): Define to xre_comp.
- (re_exec): Define to xre_exec.
-
-2001-07-18 Andreas Jaeger <aj@suse.de>
-
- * xregex2.h: Place under LGPL version 2.1.
-
-2001-07-10 Jeff Johnston <jjohnstn@redhat.com>
-
- * xregex.h: New file to support libiberty regex.
- * xregex2.h: Ditto.
-
-2001-05-16 Matt Kraai <kraai@alumni.carnegiemellon.edu>
-
- * partition.h: Fix misspelling of `implementation'.
-
-2001-05-10 Kaveh R. Ghazi <ghazi@caip.rutgers.edu>
-
- * ansidecl.h (NULL_PTR): Delete.
-
-2001-05-07 Zack Weinberg <zackw@stanford.edu>
-
- * demangle.h: Use PARAMS for all prototypes.
- * ternary.h: Use PARAMS for all prototypes. Use PTR, not void *.
- Make arguments constant where possible.
-
-2001-05-07 Mark Mitchell <mark@codesourcery.com>
-
- * splay-tree.h (splay_tree_max): New function.
- (splay_tree_min): Likewise.
-
-2001-04-15 Daniel Berlin <dan@cgsoftware.com>
-
- * ternary.h: New file - Ternary search tree header.
-
-2001-04-03 Zack Weinberg <zackw@stanford.edu>
-
- * ansidecl.h: All logic from gcc/gansidecl.h moved here.
-
-2001-03-31 Kaveh R. Ghazi <ghazi@caip.rutgers.edu>
-
- * libiberty.h (alloca): Handle setting C_ALLOCA.
-
-2001-03-20 Jim Blandy <jimb@redhat.com>
-
- * demangle.h (enum gnu_v3_constructor_kinds,
- is_gnu_v3_mangled_ctor, enum gnu_v3_destructor_kinds,
- is_gnu_v3_mangled_dtor): New declarations.
-
-2001-03-14 Nick Clifton <nickc@redhat.com>
-
- * ansidecl.h: Fix copyright dates.
- * demangle.h: Fix copyright dates.
- * floatformat.h: Fix copyright dates.
- * fnmatch.h: Fix copyright dates.
- * getopt.h: Fix copyright dates.
- * libiberty.h: Add FSF copyright notice.
- * md5.h: Fix copyright dates.
- * obstack.h: Fix copyright dates.
- * splay-tree.h: Fix copyright dates.
-
-2001-03-10 Neil Booth <neil@daikokuya.demon.co.uk>
- John David Anglin <dave@hiauly1.hia.nrc.ca>
-
- * libiberty.h: Add lbasename.
-
-2001-03-06 Zack Weinberg <zackw@stanford.edu>
-
- * libiberty.h: Prototype C_alloca; define alloca to either
- __builtin_alloca or C_alloca as appropriate.
-
-2001-03-01 John David Anglin <dave@hiauly1.hia.nrc.ca>
-
- * safe-ctype.h (_sch_test): Cast enum bit to unsigned short int for pcc
- compatibility.
-
-2000-12-18 Joseph S. Myers <jsm28@cam.ac.uk>
-
- * COPYING: Update to current
- ftp://ftp.gnu.org/pub/gnu/Licenses/COPYING-2.0 (fixes references
- to 19yy as example year in copyright notice).
-
-2000-12-16 Herman A.J. ten Brugge <Haj.Ten.Brugge@net.HCC.nl>
-
- * safe-ctype.h: Make code work on all targets and not just on
- targets where a char is 8 bits.
-
-2000-12-07 Zack Weinberg <zack@wolery.stanford.edu>
-
- * safe-ctype.h: New file.
-
-2000-12-06 Rodney Brown <RodneyBrown@mynd.com>
-
- * getopt.h obstack.h: Standarize copyright statement.
-
-2000-12-04 Richard Henderson <rth@redhat.com>
-
- * demangle.h: Change "new_abi" to "v3" everywhere.
-
-2000-11-22 Zack Weinberg <zack@wolery.stanford.edu>
-
- * libiberty.h: Move #includes to top. Prototype xmalloc_failed.
-
-2000-11-15 Kenneth Block <kenneth.block@compaq.com>
-
- * demangle.h: Add gnat and java demangle styles.
-
-2000-11-04 Hans-Peter Nilsson <hp@bitrange.com>
-
- * hashtab.h (struct htab): Add member return_allocation_failure.
- (htab_try_create): New prototype. Mention which functions may
- return NULL when this is used.
-
-2000-11-03 Hans-Peter Nilsson <hp@bitrange.com>
-
- * hashtab.h: Change void * to PTR where necessary.
-
-2000-09-10 Mark Mitchell <mark@codesourcery.com>
-
- * splay-tree.h (splay_tree_predecessor): Declare.
-
-2000-09-05 John David Anglin <dave@hiauly1.hia.nrc.ca>
-
- * md5.h (md5_uint32): Choose via INT_MAX instead of UINT_MAX.
-
-2000-09-04 Alex Samuel <samuel@codesourcery.com>
-
- * dyn-string.h: Adjust formatting.
- (dyn_string_insert_char): New macro. New declaration.
-
-2000-08-28 Jason Merrill <jason@redhat.com>
-
- * md5.h: New file.
-
-2000-08-24 Greg McGary <greg@mcgary.org>
-
- * libiberty.h (ARRAY_SIZE): New macro.
-
-2000-06-21 Alex Samuel <samuel@codesourcery.com>
-
- * dyn-string.h (dyn_string_init, dyn_string_new,
- dyn_string_delete, dyn_string_release, dyn_string_resize,
- dyn_string_clear, dyn_string_copy, dyn_string_copy_cstr,
- dyn_string_prepend, dyn_string_prepend_cstr, dyn_string_insert,
- dyn_string_insert_cstr, dyn_string_append, dyn_string_append_cstr,
- dyn_string_append_char, dyn_string_substring_dyn_string_eq):
- Define as same name with __cxa_ prepended, if IN_LIBGCC2.
- (dyn_string_init, dyn_string_copy, dyn_string_copy_cstr,
- dyn_string_prepend, dyn_string_prepend_cstr, dyn_string_insert,
- dyn_string_insert_cstr, dyn_string_append, dyn_string_append_cstr,
- dyn_string_append_char, dyn_string_substring): Change return type
- to int.
-
-2000-06-07 Kaveh R. Ghazi <ghazi@caip.rutgers.edu>
-
- * demangle.h (demangling_styles): Remove trailing comma in enum.
-
- * dyn-string.h (dyn_string_append_char): Change parameter from
- char to int.
-
-2000-06-04 Alex Samuel <samuel@codesourcery.com>
-
- * dyn-string.h: Move here from gcc/dyn-string.h. Add new functions.
-
- * demangle.h (DMGL_GNU_NEW_ABI): New macro.
- (DMGL_STYLE_MASK): Or in DMGL_GNU_NEW_ABI.
- (current_demangling_style): Add gnu_new_abi_demangling.
- (GNU_NEW_ABI_DEMANGLING_STYLE_STRING): New macro.
- (GNU_NEW_ABI_DEMANGLING): Likewise.
- (cplus_demangle_new_abi): New declaration.
-
-Tue May 30 16:53:34 2000 Andrew Cagney <cagney@b1.cygnus.com>
-
- * floatformat.h (struct floatformat): Add field name.
-
-2000-05-23 Kaveh R. Ghazi <ghazi@caip.rutgers.edu>
-
- * getopt.h (getopt): Also check HAVE_DECL_* when prototyping.
-
- * libiberty.h (basename): Likewise.
-
-2000-05-06 Zack Weinberg <zack@wolery.cumb.org>
-
- * ansidecl.h: #define __extension__ to nothing if
- GCC_VERSION < 2008.
-
-2000-05-04 Kaveh R. Ghazi <ghazi@caip.rutgers.edu>
-
- * demangle.h (demangler_engine): Constify.
-
-Thu May 4 17:15:26 2000 Philippe De Muyter <phdm@macqel.be>
-
- * sort.h (sys/types.h): File included unconditionnaly.
- (stddef.h): File include only #ifdef __STDC__.
-
-2000-05-03 Zack Weinberg <zack@wolery.cumb.org>
-
- * symcat.h: Remove #endif label.
-
-2000-04-28 Kenneth Block <block@zk3.dec.com>
- Jason Merrill <jason@casey.cygnus.com>
-
- * demangle.h (libiberty_demanglers): new table for different styles.
- (cplus_demangle_set_style): New function for setting style.
- (cplus_demangle_name_to_style): New function to translate name.
-
-2000-04-24 Mark Mitchell <mark@codesourcery.com>
-
- * hashtab.h (hash_pointer): Declare.
- (eq_pointer): Likewise.
-
-2000-04-23 Mark Mitchell <mark@codesourcery.com>
-
- * sort.h: New file.
-
-Tue Apr 18 16:22:30 2000 Richard Kenner <kenner@vlsi1.ultra.nyu.edu>
-
- * hashtab.h (enum insert_option): New type.
- (htab_find_slot, htab_find_slot_with_hash): Use it.
-
-2000-04-17 Kaveh R. Ghazi <ghazi@caip.rutgers.edu>
-
- * symcat.h: Honor autoconf macro HAVE_STRINGIZE. Add
- comments/caveats with regard to traditional C behavior.
-
-2000-04-05 Richard Henderson <rth@cygnus.com>
-
- * splay-tree.h (splay_tree_remove): Declare.
-
-2000-03-30 Mark Mitchell <mark@codesourcery.com>
-
- * hashtab.h (hashval_t): New type.
- (htab_find_with_hash): Use it as an argument.
- (htab_find_slot_with_hash): Likewise.
-
-2000-03-14 Bernd Schmidt <bernds@cygnus.co.uk>
-
- * hashtab.h (htab_trav): Modify type so that first arg is of type
- void **.
- (htab_find_with_hash, htab_find_slot_with_hash): Declare new
- functions.
-
-2000-03-09 Alex Samuel <samuel@codesourcery.com>
-
- * partition.h: New file.
-
-2000-03-09 Zack Weinberg <zack@wolery.cumb.org>
-
- * hashtab.h (struct htab): Add del_f.
- (htab_del): New type.
- (htab_create): Add fourth argument.
-
-2000-03-08 Zack Weinberg <zack@wolery.cumb.org>
-
- * hashtab.h (hash_table_t): Rename to htab_t.
- (struct hash_table): Rename to struct htab. Shorten element
- names. Reorder elements by size.
- (htab_hash, htab_eq, htab_trav): New typedefs for the callback
- function pointers.
- (hash_table_entry_t): Discard; just use void * for element
- type.
-
-Sat Jan 1 19:06:52 2000 Hans-Peter Nilsson <hp@bitrange.com>
-
- * symcat.h (STRINGX) [!__STDC__ || ALMOST_STDC]: Change "?" to "s"
- to stringify argument s.
-
-1999-12-05 Mark Mitchell <mark@codesourcery.com>
-
- * splay-tree.h (struct splay_tree_node): Rename to ...
- (struct splay_tree_node_s): ... this.
- (struct splay_tree): Rename to ...
- (struct splay_tree_s): ... this.
-
-1999-11-30 Kaveh R. Ghazi <ghazi@caip.rutgers.edu>
-
- * ansidecl.h (ATTRIBUTE_MALLOC): New macro.
-
- * libiberty.h (buildargv, dupargv, concat, choose_temp_base,
- make_temp_file, xmalloc, xcalloc, xstrdup, xmemdup): Add
- ATTRIBUTE_MALLOC.
- (xatexit): Remove __GNUC__ check, add ATTRIBUTE_NORETURN.
-
-1999-11-28 Kaveh R. Ghazi <ghazi@caip.rutgers.edu>
-
- * libiberty.h: Include stdarg.h when ANSI_PROTOTYPES is defined.
- (asprintf, vasprintf): Provide declarations.
-
-Wed Nov 10 12:43:21 1999 Philippe De Muyter <phdm@macqel.be>
- Kaveh R. Ghazi <ghazi@caip.rutgers.edu>
-
- * ansidecl.h: Define and test `GCC_VERSION', not `HAVE_GCC_VERSION'.
-
-1999-10-23 08:51 -0700 Zack Weinberg <zack@bitmover.com>
-
- * hashtab.h: Give hash_table_t a struct tag. Add prototypes
- for clear_hash_table_slot and traverse_hash_table. Correct
- prototype of all_hash_table_collisions.
-
-Fri Oct 15 01:47:51 1999 Vladimir Makarov <vmakarov@loony.cygnus.com>
-
- * hashtab.h: New file.
-
-1999-10-10 Kaveh R. Ghazi <ghazi@caip.rutgers.edu>
-
- * ansidecl.h (HAVE_GCC_VERSION): New macro. Use it instead of
- explicitly testing __GNUC__ and __GNUC_MINOR__.
-
- (ATTRIBUTE_PRINTF): Use `__format__', not `format'.
-
-1999-09-25 Kaveh R. Ghazi <ghazi@caip.rutgers.edu>
-
- * libiberty.h (make_temp_file): Add a prototype.
-
-Tue Sep 14 00:35:02 1999 Marc Espie <espie@cvs.openbsd.org>
-
- * libiberty.h (basename): OpenBSD has a correct prototype.
- (xrealloc): Remove outdated comment.
-
-1999-09-07 Jeff Garzik <jgarzik@pobox.com>
-
- * libiberty.h (xmemdup): Add prototype for new function.
-
-1999-09-01 Kaveh R. Ghazi <ghazi@caip.rutgers.edu>
-
- * obstack.h (obstack_grow, obstack_grow0): Move (char*) casts
- in calls to `_obstack_memcpy' from here ...
-
- (_obstack_memcpy): ... to here, except in the __STDC__ case which
- doesn't need it.
-
-1999-08-30 Kaveh R. Ghazi <ghazi@caip.rutgers.edu>
-
- * libiberty.h (getpwd): Prototype.
-
-1999-08-01 Mark Mitchell <mark@codesourcery.com>
-
- * splay-tree.h (splay_tree_insert): Return the new node.
-
-1999-07-11 Ian Lance Taylor <ian@zembu.com>
-
- * ansidecl.h: Copy attribute support macros from egcs.
-
-1999-04-02 Mark Mitchell <mark@codesourcery.com>
-
- * splay-tree.h (splay_tree_compare_pointers): Declare.
-
-1999-03-30 Mark Mitchell <mark@codesourcery.com>
-
- * splay-tree.h (splay_tree_compare_ints): Declare.
-
-Wed Mar 24 12:46:29 1999 Andrew Cagney <cagney@amy.cygnus.com>
-
- * libiberty.h (basename): Cygwin{,32} should have the prototype.
-
-Mon Dec 14 09:53:31 1998 Kaveh R. Ghazi <ghazi@caip.rutgers.edu>
-
- * demangle.h: Don't check IN_GCC anymore.
- * splay-tree.h: Likewise.
-
-Tue Dec 8 00:30:31 1998 Elena Zannoni <ezannoni@kwikemart.cygnus.com>
-
- * demangle.h: (DMGL_EDG): new macro for Kuck and Associates
- (DMGL_STYLE_MASK): modify to include Kuck and Assoc style
- (demangling_styles): add new edg_demangling style
- (EDG_DEMANGLING_STYLE_STRING): new macro
- (EDG_DEMANGLING): new macro
- (DMGL_HP): new macro, for HP/aCC compiler.
- (DMGL_STYLE_MASK): modify to include new HP's style.
- (demangling_styles): add new hp_demangling value.
- (HP_DEMANGLING_STYLE_STRING): new macro.
- (ARM_DEMANGLING): coerce to int.
- (HP_DEMANGLING): new macro.
-
-Fri Nov 20 13:14:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
-
- * libiberty.h (basename): Add prototype for FreeBSD.
-
-Fri Nov 13 19:19:11 1998 Kaveh R. Ghazi <ghazi@caip.rutgers.edu>
-
- * libiberty.h: Prototype xcalloc.
-
-Sun Nov 8 17:42:25 1998 Kaveh R. Ghazi <ghazi@caip.rutgers.edu>
-
- * ansidecl.h: Wrap problematic macros with !IN_GCC.
-
- * demangle.h: Never define PARAMS().
- * splay-tree.h: Likewise.
-
-Sat Nov 7 16:04:03 1998 Kaveh R. Ghazi <ghazi@caip.rutgers.edu>
-
- * demangle.h: Don't include gansidecl.h.
- * splay-tree.h: Likewise.
-
-Thu Oct 22 19:58:00 1998 Kaveh R. Ghazi <ghazi@caip.rutgers.edu>
-
- * splay-tree.h: Wrap function pointer parameter declarations in
- PARAMS() macro.
-
-1998-10-21 Mark Mitchell <mark@markmitchell.com>
-
- * splay-tree.h: New file.
-
-Fri Oct 9 00:02:03 1998 Jeffrey A Law (law@cygnus.com)
-
- * Merge devo and egcs include directories.
-
-Sat Sep 5 12:16:33 1998 Jeffrey A Law (law@cygnus.com)
-
- * getopt.h, obstack.h: Updated from gcc.
-
-1998-08-03 Jason Molenda (jsm@bugshack.cygnus.com)
-
- * libiberty.h (xexit): Change decl to use modern GCC attribute
- to indicate exit does not return.
-
-Mon Jun 1 13:48:32 1998 Jason Molenda (crash@bugshack.cygnus.com)
-
- * obstack.h: Update to latest FSF version.
-
-Tue Feb 24 13:05:02 1998 Doug Evans <devans@canuck.cygnus.com>
-
- * dis-asm.h (disassemble_info): Member `symbol' renamed to `symbols'
- and made an "asymbol **". New member num_symbols.
- (INIT_DISASSEMBLE_INFO_NO_ARCH): Update.
-
-Tue Feb 17 12:32:18 1998 Andrew Cagney <cagney@b1.cygnus.com>
-
- * remote-sim.h (sim_fetch_register, sim_store_register): Add
- register length parameter. Functions return actual length of
- register.
-
-Thu Feb 12 16:29:01 1998 Ian Lance Taylor <ian@cygnus.com>
-
- * getopt.h: Update to latest FSF version.
-
-Wed Feb 11 16:56:06 1998 Doug Evans <devans@canuck.cygnus.com>
-
- * symcat.h: New file.
-
-Mon Feb 2 17:13:31 1998 Steve Haworth <steve@pm.cse.rmit.EDU.AU>
-
- * dis-asm.h (print_insn_tic30): Declare.
-
-Thu Jan 22 16:23:59 1998 Fred Fish <fnf@cygnus.com>
-
- * dis-asm.h: Add flag INSN_HAS_RELOC to tell disassembly
- function there is a reloc on this line.
-
-Mon Dec 8 11:22:23 1997 Nick Clifton <nickc@cygnus.com>
-
- * dis-asm.h: Remove prototype of disasm_symaddr() as this function
- no longer exists.
-
-Tue Dec 2 10:20:53 1997 Nick Clifton <nickc@cygnus.com>
-
- * dis-asm.h (disasm_symaddr): New prototype.
-
-Mon Dec 1 20:24:18 1997 J"orn Rennecke <amylaar@cygnus.co.uk>
-
- * coff/sh.h (R_SH_SWITCH8): New.
-
-Mon Dec 1 11:29:35 1997 Doug Evans <devans@canuck.cygnus.com>
-
- * callback.h (CB_SYSCALL): Comment out arg names in prototypes.
-
-Wed Nov 26 16:47:58 1997 Michael Meissner <meissner@cygnus.com>
-
- * callback.h (CB_SYSCALL): Consistantly use names for prototype
- arguments.
-
-Wed Nov 26 11:39:30 1997 Doug Evans <devans@canuck.cygnus.com>
-
- * callback.h (CB_SYSCALL): Change byte count arguments to
- {read,write}_mem to `int'. New member `magic'.
- (CB_SYSCALL_MAGIC,CB_SYSCALL_INIT): New macros.
-
-Tue Nov 25 01:35:52 1997 Doug Evans <devans@seba.cygnus.com>
-
- * callback.h (struct stat): Move forward decl up.
- (host_callback): Pass stat struct pointer to stat,fstat.
- (CB_SYS_nnn): Reorganize.
- (CB_SYSCALL): New members p1,p2.
- (cb_host_to_target_stat): Delete fourth arg.
-
-Sat Nov 22 23:34:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
-
- * remote-sim.h (sim_stop_reason): Clarify sim_signalled SIGRC
- argument.
-
-Mon Nov 17 14:00:51 1997 Doug Evans <devans@seba.cygnus.com>
-
- * callback.h (CB_TARGET_DEFS_MAP): Renamed from target_defs_map.
- (host_callback): Add stat, fstat, syscall_map, errno_map, open_map,
- signal_map, stat_map.
- (errn_map,open_map): Renamed to cb_init_foo_map.
- (cb_host_to_target_errno,cb_target_to_host_open): Renamed from
- host_to_target_errno,target_to_host_open.
- (cb_read_target_syscall_maps): Add prototype.
- (cb_target_to_host_syscall): Likewise.
- (cb_host_to_target_stat): Likewise.
- (cb_syscall): Likewise.
- (CB_SYS_{exit,open,close,read,write,lseek,unlink,getpid,kill,fstat,
- argvlen,argv,chdir,stat,chmod,utime,time}): Define.
- (CB_SYSCALL): New type.
- (CB_RC): New enum.
-
-Fri Nov 7 10:34:09 1997 Rob Savoye <rob@darkstar.cygnus.com>
-
- * libiberty.h: Add extern "C" { so it can be used with C++
- programs.
- * remote-sim.h: Add extern "C" { so it can be used with C++
- programs.
-
-Tue Oct 14 16:07:51 1997 Nick Clifton <nickc@cygnus.com>
-
- * dis-asm.h (struct disassemble_info): New field
- 'symbol_at_address_func'.
- (INIT_DISASSEMBLE_INFO_NO_ARCH): Initialise new field with
- generic_symbol_at_address.
-
-Mon Oct 13 10:17:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
-
- * remote-sim.h: Clarify sim_read, sim_write MEM argument.
-
-Wed Sep 24 18:03:10 1997 Stu Grossman <grossman@babylon-5.cygnus.com>
-
- * remote-sim.h (SIM_RC): Add a bunch of new return codes for
- breakpoint stuff.
- * Add functions to tell the simulator to set/clear/enable/disable
- intrinsic breakpoints.
-
-Thu Aug 28 19:41:42 1997 Andrew Cagney <cagney@b1.cygnus.com>
-
- * libiberty.h (dupargv): Add prototype.
-
-Tue Aug 26 12:25:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
-
- * remote-sim.h (sim_create_inferior): Add ABFD arg. Document.
-
-Mon Aug 25 10:50:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
-
- * remote-sim.h (sim_open): Add ABFD arg. Document.
-
-Fri Aug 8 16:43:56 1997 Doug Evans <dje@canuck.cygnus.com>
-
- * dis-asm.h (arc_get_disassembler): Declare.
-
-Wed Jul 30 11:39:50 1997 Per Bothner <bothner@deneb.cygnus.com>
-
- * demangle.h (DMGL_JAVA): New option to request Java demangling.
-
-Tue Jul 22 17:59:54 1997 Ian Lance Taylor <ian@cygnus.com>
-
- * libiberty.h (PEXECUTE_*): Define.
- (pexecute, pwait): Declare.
-
-Fri Jun 6 13:02:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
-
- * remote-sim.h (sim_kill): Mark as deprecated.
-
-Fri May 23 13:43:41 1997 Fred Fish <fnf@cygnus.com>
-
- * bfdlink.h (struct bfd_link_info): Add task_link member.
-
-Thu May 22 11:32:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
-
- * remote-sim.h: Review documentation. Clarify restrictions on
- when functions can be called.
-
-Wed May 21 16:47:53 1997 Andrew Cagney <cagney@b1.cygnus.com>
-
- * remote-sim.h (sim_set_profile_size): Add prototype, document as
- deprecated.
-
-Tue May 20 09:32:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
-
- * remote-sim.h (sim_open): Add callback struct.
- (sim_set_callbacks): Drop SIM_DESC argument. Document.
- (sim_size): Remove recently added SIM_DESC argument. Document.
-
-Mon May 19 19:14:44 1997 Andrew Cagney <cagney@b1.cygnus.com>
-
- * remote-sim.h: Pass SD into sim_size.
-
-Thu May 15 01:24:16 1997 Mark Alexander <marka@cygnus.com>
-
- * obstack.h (obstack_specify_allocation_with_arg, obstack_chunkfun,
- obstack_freefun): Eliminate compile warnings in gdb.
-
-Tue May 13 10:21:14 1997 Nick Clifton <nickc@cygnus.com>
-
- * coff/arm.h (constants): Added new flag bits F_APCS_26 and
- F_APCS_SET for the f_flags field of the filehdr structure. Added new
- flags: F_APCS26, F_ARM_2, F_ARM_3, F_ARM_7, F_ARM_7T to store
- information in the flags field of the internal_f structure used by BFD
- routines.
-
-Tue Apr 22 10:24:34 1997 Fred Fish <fnf@cygnus.com>
-
- * floatformat.h (floatformat_byteorders): Add comments for previous
- formats and add floatformat_littlebyte_bigword, primarily for ARM.
- Add declaration for floatformat_ieee_double_littlebyte_bigword.
-
-Fri Apr 18 13:04:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
-
- * remote-sim.h (sim_stop): New interface - asynchronous
- notification of a request to stop / suspend the running
- simulation.
-
- * remote-sim.h (enum sim_stop): Add sim_running and sim_polling as
- states for use internal to simulators.
-
- * callback.h (struct host_callback_strut): Put a magic number at
- the end of the struct to allow basic checking.
- (struct host_callback_struct ): Add poll_quit - so
- that the console etc can be polled at regular intervals.
-
-Thu Apr 17 02:17:12 1997 Doug Evans <dje@canuck.cygnus.com>
-
- * remote-sim.h (struct _bfd): Declare.
- (sim_load): Return SIM_RC. New arg `abfd'.
- (sim_create_inferior): Return SIM_RC. Delete arg `start_address'.
-
-Wed Apr 2 17:09:12 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
-
- * remote-sim.h (sim_trace, sim_size): Make these global. They
- will go away shortly.
-
-Wed Apr 2 15:23:49 1997 Doug Evans <dje@canuck.cygnus.com>
-
- * remote-sim.h (SIM_OPEN_KIND, SIM_RC): New enums.
- (sim_open): New argument `kind'.
-
-Wed Apr 2 14:45:51 1997 Ian Lance Taylor <ian@cygnus.com>
-
- * COPYING: Update FSF address.
-
-Fri Mar 28 15:29:54 1997 Mike Meissner <meissner@cygnus.com>
-
- * callback.h (top level): Include stdarg.h or varargs.h if
- va_start is not defined.
- (host_callback_struct): Make {,e}vprintf_filtered take a va_list
- instead of void *, since va_list might be an array or structure
- type.
-
-Fri Mar 28 15:44:41 1997 H.J. Lu <hjl@gnu.ai.mit.edu>
-
- * libiberty.h (basename): Add prototype for glibc and linux.
+ * xtensa-isa.h: Update a comment and whitespace.
-Mon Mar 17 19:22:12 1997 Ian Lance Taylor <ian@cygnus.com>
+2005-03-01 Jan Beulich <jbeulich@novell.com>
- * objalloc.h: New file.
+ * libiberty.h: Declare unlink_if_ordinary.
-Mon Mar 17 14:57:55 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
+2005-02-21 Alan Modra <amodra@bigpond.net.au>
- * remote-sim.h: New file, copied in from gdb/remote-sim.h. One
- day this will be placed in a directory of its own.
+ * xtensa-isa-internal.h (xtensa_length_decode_fn): Warning fix.
+ * xtensa-isa.h (xtensa_insnbuf_to_chars): Likewise.
+ (xtensa_insnbuf_from_chars, xtensa_isa_length_from_chars): Likewise.
-Sat Mar 15 19:00:14 1997 Ian Lance Taylor <ian@cygnus.com>
+2005-02-14 Paolo Bonzini <bonzini@gnu.org>
- * obstack.h: Update to current FSF version.
+ PR bootstrap/19818
+ * ansidecl.h (PARAMS): Guard from redefinition.
-Thu Mar 6 15:46:59 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
+2005-02-03 Alan Modra <amodra@bigpond.net.au>
- * callback.h (struct host_callback_struct): Add callbacks -
- flush_stdout, write_stderr, flush_stderr, vprintf_filtered,
- evprintf_filtered. Delete redundant callbacks - printf_filtered.
+ * bfdlink.h (struct bfd_link_hash_entry): Add u.undef.weak.
-Thu Feb 27 23:18:27 1997 Ian Lance Taylor <ian@cygnus.com>
+2005-02-01 Alan Modra <amodra@bigpond.net.au>
- * bfdlink.h (struct bfd_link_info): Remove lprefix and lprefix_len
- fields.
+ * bfdlink.h (bfd_link_repair_undef_list): Declare.
-Tue Feb 25 00:10:49 1997 Ian Lance Taylor <ian@cygnus.com>
+2005-01-10 Andreas Schwab <schwab@suse.de>
- * dis-asm.h (INIT_DISASSEMBLE_INFO_NO_ARCH): Initialize
- bytes_per_chunk and display_endian.
+ * dis-asm.h (struct disassemble_info): Add skip_zeroes and
+ skip_zeroes_at_end.
-Mon Feb 24 17:47:02 1997 Ian Lance Taylor <ian@cygnus.com>
+2004-12-11 Ben Elliston <bje@au.ibm.com>
- From Eric Youngdale <eric@andante.jic.com>:
- * bfdlink.h (struct bfd_elf_version_expr): Define.
- (struct bfd_elf_version_deps): Define.
- (struct bfd_elf_version_tree): Define.
+ * fibheap.h (struct fibnode): Only use unsigned long bitfields
+ when __GNUC__ is defined and ints are less than 32-bits wide.
-Thu Feb 6 14:20:01 1997 Martin M. Hunt <hunt@pizza.cygnus.com>
+2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
- * dis-asm.h: (disassemble_info): Add new fields
- bytes_per_chunk and display_endian to control the
- display of raw instructions.
+ * opcode/crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
+ Remove redundant instruction types.
+ (struct argument): X_op - new field.
+ (struct cst4_entry): Remove.
+ (no_op_insn): Declare.
-Sun Dec 8 17:11:12 1996 Doug Evans <dje@canuck.cygnus.com>
+2004-11-04 Paul Brook <paul@codesourcery.com>
- * callback.h (host_callback): New member `error'.
+ * bfdlink.h (bfd_link_info): Add default_imported_symver.
-Wed Nov 20 00:40:23 1996 Doug Evans <dje@canuck.cygnus.com>
+2004-11-12 Bob Wilson <bob.wilson@acm.org>
- * callback.h: New file, moved here from gdb.
+ * xtensa-isa-internal.h (xtensa_interface_internal): Add class_id.
+ * xtensa-isa.h (xtensa_interface_class_id): New prototype.
-Mon Nov 18 16:34:00 1996 Dawn Perchik <dawn@critters.cygnus.com>
+2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
+ Vineet Sharma <vineets@noida.hcltech.com>
- * libiberty.h: Checkin again; last checkin failed due to sticky tag.
+ * dis-asm.h: Add prototype for print_insn_maxq_little.
-Wed Nov 13 08:22:00 1996 Dawn Perchik <dawn@critters.cygnus.com>
+2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
+
+ * opcode/crx.h (enum argtype): Rename types, remove unused types.
- * libiberty.h: Revert last commit due to conflicts with hpux
- system headers.
+2004-10-27 Richard Earnshaw <rearnsha@arm.com>
-Tue Nov 12 16:31:00 1996 Dawn Perchik <dawn@critters.cygnus.com>
+ * elf/arm.h: Add R_ARM_CALL and R_ARM_JUMP32.
- * libiberty.h: Move prototypes from argv.c here.
+2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
+
+ * opcode/crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
+ (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
+ (enum operand_type): Rearrange operands, edit comments.
+ replace us<N> with ui<N> for unsigned immediate.
+ replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
+ displacements (respectively).
+ replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
+ (instruction type): Add NO_TYPE_INS.
+ (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
+ (operand_entry): New field - 'flags'.
+ (operand flags): New.
+
+2004-10-26 Paul Brook <paul@codesourcery.com>
+
+ * bfdlink.h (struct bfd_link_info): Add create_default_symver.
+
+2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
+
+ * opcode/crx.h (operand_type): Remove redundant types i3, i4,
+ i5, i8, i12.
+ Add new unsigned immediate types us3, us4, us5, us16.
+
+2004-10-21 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR 463
+ * bfdlink.h (bfd_link_callbacks): Add a pointer to struct
+ bfd_link_hash_entry to reloc_overflow.
+
+2004-10-12 Paul Brook <paul@codesourcery.com>
+
+ * elf/arm.h (EF_ARM_EABI_VER4): Define.
+
+2004-10-08 Daniel Jacobowitz <dan@debian.org>
+
+ * elf/common.h (PT_SUNW_EH_FRAME): Define.
+ * elf/x86-64.h (SHT_X86_64_UNWIND): Define.
+
+2004-10-07 Bob Wilson <bob.wilson@acm.org>
+
+ * xtensa-config.h (XSHAL_USE_ABSOLUTE_LITERALS,
+ XCHAL_HAVE_PREDICTED_BRANCHES, XCHAL_INST_FETCH_WIDTH): New.
+ (XCHAL_EXTRA_SA_SIZE, XCHAL_EXTRA_SA_ALIGN): Delete.
+
+ * xtensa-isa-internal.h (ISA_INTERFACE_VERSION): Delete.
+ (config_sturct struct): Delete.
+ (XTENSA_OPERAND_IS_REGISTER, XTENSA_OPERAND_IS_PCRELATIVE,
+ XTENSA_OPERAND_IS_INVISIBLE, XTENSA_OPERAND_IS_UNKNOWN,
+ XTENSA_OPCODE_IS_BRANCH, XTENSA_OPCODE_IS_JUMP,
+ XTENSA_OPCODE_IS_LOOP, XTENSA_OPCODE_IS_CALL,
+ XTENSA_STATE_IS_EXPORTED, XTENSA_INTERFACE_HAS_SIDE_EFFECT): Define.
+ (xtensa_format_encode_fn, xtensa_get_slot_fn, xtensa_set_slot_fn): New.
+ (xtensa_insn_decode_fn): Rename to ...
+ (xtensa_opcode_decode_fn): ... this.
+ (xtensa_immed_decode_fn, xtensa_immed_encode_fn, xtensa_do_reloc_fn,
+ xtensa_undo_reloc_fn): Update.
+ (xtensa_encoding_template_fn): Delete.
+ (xtensa_opcode_encode_fn, xtensa_format_decode_fn,
+ xtensa_length_decode_fn): New.
+ (xtensa_format_internal, xtensa_slot_internal): New types.
+ (xtensa_operand_internal): Delete operand_kind, inout, isPCRelative,
+ get_field, and set_field fields. Add name, field_id, regfile,
+ num_regs, and flags fields.
+ (xtensa_arg_internal): New type.
+ (xtensa_iclass_internal): Change operands field to array of
+ xtensa_arg_internal. Add num_stateOperands, stateOperands,
+ num_interfaceOperands, and interfaceOperands fields.
+ (xtensa_opcode_internal): Delete length, template, and iclass fields.
+ Add iclass_id, flags, encode_fns, num_funcUnit_uses, and funcUnit_uses.
+ (opname_lookup_entry): Delete.
+ (xtensa_regfile_internal, xtensa_interface_internal,
+ xtensa_funcUnit_internal, xtensa_state_internal,
+ xtensa_sysreg_internal, xtensa_lookup_entry): New.
+ (xtensa_isa_internal): Replace opcode_table field with opcodes field.
+ Change type of opname_lookup_table. Delete num_modules,
+ module_opcode_base, module_decode_fn, config, and has_density fields.
+ Add num_formats, formats, format_decode_fn, length_decode_fn,
+ num_slots, slots, num_fields, num_operands, operands, num_iclasses,
+ iclasses, num_regfiles, regfiles, num_states, states,
+ state_lookup_table, num_sysregs, sysregs, sysreg_lookup_table,
+ max_sysreg_num, sysreg_table, num_interfaces, interfaces,
+ interface_lookup_table, num_funcUnits, funcUnits and
+ funcUnit_lookup_table fields.
+ (xtensa_isa_module, xtensa_isa_modules): Delete.
+ (xtensa_isa_name_compare): New prototype.
+ (xtisa_errno, xtisa_error_msg): New.
+ * xtensa-isa.h (XTENSA_ISA_VERSION): Define.
+ (xtensa_isa): Change type.
+ (xtensa_operand): Delete.
+ (xtensa_format, xtensa_regfile, xtensa_state, xtensa_sysreg,
+ xtensa_interface, xtensa_funcUnit, xtensa_isa_status,
+ xtensa_funcUnit_use): New types.
+ (libisa_module_specifier): Delete.
+ (xtensa_isa_errno, xtensa_isa_error_msg): New prototypes.
+ (xtensa_insnbuf_free, xtensa_insnbuf_to_chars,
+ xtensa_insnbuf_from_chars): Update prototypes.
+ (xtensa_load_isa, xtensa_extend_isa, xtensa_default_isa,
+ xtensa_insn_maxlength, xtensa_num_opcodes, xtensa_decode_insn,
+ xtensa_encode_insn, xtensa_insn_length,
+ xtensa_insn_length_from_first_byte, xtensa_num_operands,
+ xtensa_operand_kind, xtensa_encode_result,
+ xtensa_operand_isPCRelative): Delete.
+ (xtensa_isa_init, xtensa_operand_inout, xtensa_operand_get_field,
+ xtensa_operand_set_field, xtensa_operand_encode,
+ xtensa_operand_decode, xtensa_operand_do_reloc,
+ xtensa_operand_undo_reloc): Update prototypes.
+ (xtensa_isa_maxlength, xtensa_isa_length_from_chars,
+ xtensa_isa_num_pipe_stages, xtensa_isa_num_formats,
+ xtensa_isa_num_opcodes, xtensa_isa_num_regfiles, xtensa_isa_num_states,
+ xtensa_isa_num_sysregs, xtensa_isa_num_interfaces,
+ xtensa_isa_num_funcUnits, xtensa_format_name, xtensa_format_lookup,
+ xtensa_format_decode, xtensa_format_encode, xtensa_format_length,
+ xtensa_format_num_slots, xtensa_format_slot_nop_opcode,
+ xtensa_format_get_slot, xtensa_format_set_slot, xtensa_opcode_decode,
+ xtensa_opcode_encode, xtensa_opcode_is_branch, xtensa_opcode_is_jump,
+ xtensa_opcode_is_loop, xtensa_opcode_is_call,
+ xtensa_opcode_num_operands, xtensa_opcode_num_stateOperands,
+ xtensa_opcode_num_interfaceOperands, xtensa_opcode_num_funcUnit_uses,
+ xtensa_opcode_funcUnit_use, xtensa_operand_name,
+ xtensa_operand_is_visible, xtensa_operand_is_register,
+ xtensa_operand_regfile, xtensa_operand_num_regs,
+ xtensa_operand_is_known_reg, xtensa_operand_is_PCrelative,
+ xtensa_stateOperand_state, xtensa_stateOperand_inout,
+ xtensa_interfaceOperand_interface, xtensa_regfile_lookup,
+ xtensa_regfile_lookup_shortname, xtensa_regfile_name,
+ xtensa_regfile_shortname, xtensa_regfile_view_parent,
+ xtensa_regfile_num_bits, xtensa_regfile_num_entries,
+ xtensa_state_lookup, xtensa_state_name, xtensa_state_num_bits,
+ xtensa_state_is_exported, xtensa_sysreg_lookup,
+ xtensa_sysreg_lookup_name, xtensa_sysreg_name, xtensa_sysreg_number,
+ xtensa_sysreg_is_user, xtensa_interface_lookup, xtensa_interface_name,
+ xtensa_interface_num_bits, xtensa_interface_inout,
+ xtensa_interface_has_side_effect, xtensa_funcUnit_lookup,
+ xtensa_funcUnit_name, xtensa_funcUnit_num_copies): New prototypes.
+ * elf/xtensa.h (R_XTENSA_DIFF8, R_XTENSA_DIFF16, R_XTENSA_DIFF32,
+ R_XTENSA_SLOT*_OP, R_XTENSA_SLOT*_ALT): New relocations.
+ (XTENSA_PROP_SEC_NAME): Define.
+ (property_table_entry): Add flags field.
+ (XTENSA_PROP_*, GET_XTENSA_PROP_*, SET_XTENSA_PROP_*): Define.
+
+2004-10-07 Jeff Baker <jbaker@qnx.com>
+
+ * bfdlink.h (bfd_link_info): Add bitfield: warn_shared_textrel.
+
+2004-09-17 Paul Brook <paul@codesourcery.com>
+
+ * elf/arm.h: Remove R_ARM_STKCHK and R_ARM_THM_STKCHK.
+ Add R_ARM_TARGET2, R_ARM_PREL31, R_ARM_GOT_ABS, R_ARM_GOT_PREL,
+ R_ARM_GOT_BREL12, R_ARM_GOTOFF12 and R_ARM_GOTRELAX.
+
+2004-09-17 Alan Modra <amodra@bigpond.net.au>
+
+ * bfdlink.h (struct bfd_link_hash_entry): Move und_next into elements
+ of union.
+
+2004-09-13 Aaron W. LaFramboise <aaronavay62@aaronwl.com>
+
+ * libiberty.h (basename): Prototype for __MINGW32__.
+
+2004-09-13 Paul Brook <paul@codesourcery.com>
+
+ * elf/arm.h: Rename RELABS to TARGET1.
+
+2004-09-04 Kaveh R. Ghazi <ghazi@caip.rutgers.edu>
+
+ * ansidecl.h (ATTRIBUTE_SENTINEL): Define.
+ * libiberty.h (concat, reconcat, concat_length, concat_copy,
+ concat_copy2): Use ATTRIBUTE_SENTINEL.
-Thu Oct 31 14:56:18 1996 Doug Evans <dje@canuck.cygnus.com>
+2004-08-13 Alan Modra <amodra@bigpond.net.au>
- * ansidecl.h (VPARAMS,VA_START): Define.
+ * bfdlink.h (struct bfd_link_callbacks): Remove "error_handler".
+ (LD_DEFINITION_IN_DISCARDED_SECTION): Delete.
-Fri Oct 25 12:08:04 1996 Ian Lance Taylor <ian@cygnus.com>
+2004-08-02 Gabriel Dos Reis <gdr@integrable-solutions.net>
- * dis-asm.h (disassemble_info): Add bytes_per_line field.
- (INIT_DISASSEMBLE_INFO_NO_ARCH): Initialize bytes_per_line field.
+ * libiberty.h (XDELETE, XDELETEVEC, XRESIZEVEC): Remove any
+ const-qualification before disposal.
-Thu Oct 24 17:10:01 1996 Ian Lance Taylor <ian@cygnus.com>
+2004-07-24 Bernardo Innocenti <bernie@develer.com>
- * dis-asm.h (disassemble_info): Add symbol field.
- (INIT_DISASSEMBLE_INFO_NO_ARCH): Initialize symbol field.
+ * ansidecl.h (ARG_UNUSED): New Macro.
-Thu Oct 17 11:17:40 1996 Doug Evans <dje@canuck.cygnus.com>
+2004-07-23 H.J. Lu <hongjiu.lu@intel.com>
- * dis-asm.h (print_insn_m32r): Declare.
+ * bin-bugs.h (REPORT_BUGS_TO): Set to
+ "<URL:http://www.sourceware.org/bugzilla/>".
-Mon Oct 14 23:56:52 1996 Ian Lance Taylor <ian@cygnus.com>
+2004-07-21 Paolo Bonzini <bonzini@gnu.org>
- * libiberty.h: Declare parameter types for xmalloc and xrealloc.
+ * ansidecl.h (ATTRIBUTE_PURE): New.
-Thu Oct 3 13:45:27 1996 Ian Lance Taylor <ian@cygnus.com>
+2004-07-13 Bernardo Innocenti <bernie@develer.com>
- * fnmatch.h: New file.
+ * libiberty.h (XNEW, XCNEW, XNEWVEC, XCNEWVEC, XOBNEW): Move here from
+ libcpp/internal.h.
+ (XDELETE, XRESIZEVEC, XDELETEVEC, XNEWVAR, XCNEWVAR, XRESIZEVAR): New
+ macros.
-Thu Oct 3 10:33:14 1996 Jeffrey A Law (law@cygnus.com)
+2004-07-13 Bernardo Innocenti <bernie@develer.com>
- * dis-asm.h (print_insn_mn10x00): Delete declaration.
- (print_insn_mn10200, print_insn_mn10300): Declare.
+ * libiberty.h (ASTRDUP): Add casts required for stricter
+ type conversion rules of C++.
+ * obstack.h (obstack_free): Likewise.
-Wed Oct 2 21:24:43 1996 Jeffrey A Law (law@cygnus.com)
+2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
- * dis-asm.h (print_insn_mn10x00): Declare.
+ * dis-asm.h (print_insn_crx): Declare.
-Mon Sep 30 13:56:11 1996 Fred Fish <fnf@cygnus.com>
+2004-06-24 Alan Modra <amodra@bigpond.net.au>
- * libiberty.h: Remove #ifndef PRIVATE_XMALLOC.
+ * bfdlink.h (struct bfd_link_order): Update comment.
-Sat Aug 31 13:27:06 1996 Jeffrey A Law (law@cygnus.com)
+2004-05-11 Jakub Jelinek <jakub@redhat.com>
- * dis-asm.h (print_insn_v850): Declare.
+ * bfdlink.h (struct bfd_link_info): Add relro, relro_start and
+ relro_end fields.
+ * elf/common.h (PT_GNU_EH_FRAME, PT_GNU_STACK): Add comments.
+ (PT_GNU_RELRO): Define.
-Tue Aug 13 16:10:30 1996 Stu Grossman (grossman@critters.cygnus.com)
+2004-05-04 Andreas Jaeger <aj@suse.de>
- * obstack.h: Change bcopy to memcpy. Works better on Posix
- systems, which generally lack bcopy.
+ * demangle.h: Do not use C++ reserved keyword typename as
+ parameter for cplus_demangle_fill_builtin_type.
-Mon Aug 12 17:03:18 1996 Stu Grossman (grossman@critters.cygnus.com)
+2004-04-22 Richard Henderson <rth@redhat.com>
- * ansidecl.h: Change WIN32 to _WIN32.
+ * hashtab.h (struct htab): Add size_prime_index.
-Fri Jul 26 13:58:18 1996 Ian Lance Taylor <ian@cygnus.com>
+2004-04-13 Jeff Law <law@redhat.com>
- * dis-asm.h: Add flavour field.
- (print_insn_alpha): Declare.
- (print_insn_alpha_osf, print_insn_alpha_vms): Don't declare.
- (INIT_DISASSEMBLE_INFO): Initialize flavour field.
+ * hashtab.h (htab_remove_elt_with_hash): Prototype new function.
-Tue Jul 23 17:37:58 1996 Fred Fish <fnf@cygnus.com>
+2004-03-30 Zack Weinberg <zack@codesourcery.com>
- * libiberty.h (PRIVATE_XMALLOC): Enclose xmalloc/xrealloc
- definitions inside #ifndef so that programs that want to
- can define PRIVATE_XMALLOC and then define xmalloc and
- xrealloc anyway they want.
- (basename): Document in source that we can't declare the
- parameter type because it is declared inconsistently across
- different systems.
+ * hashtab.h, splay-tree.h: Use new shorter form of GTY markers.
-Mon Jul 22 13:16:13 1996 Richard Henderson <rth@tamu.edu>
+2004-03-25 Stan Shebs <shebs@apple.com>
- * dis-asm.h (print_insn_alpha): Don't declare.
- (print_insn_alpha_osf, print_insn_alpha_vms): Declare.
+ * mpw/: Remove subdirectory and everything in it.
-Wed Jul 17 14:45:12 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
-
- * dis-asm.h: (print_insn_d10v): Declare.
-
-Mon Jul 15 16:55:38 1996 Stu Grossman (grossman@critters.cygnus.com)
-
- * dis-asm.h: Get rid of decls for print_insn_i8086,
- print_insn_sparc64 and print_insn_sparclite.
- * (INIT_DISASSEMBLE_INFO): Split into two pieces. One,
- INIT_DISASSEMBLE_INFO_NO_ARCH inits everything except for endian,
- mach, and arch.
-
-Fri Jul 12 10:19:27 1996 Stu Grossman (grossman@critters.cygnus.com)
-
- * dis-asm.h (print_insn_i8086): Declare.
-
-Wed Jul 3 16:02:39 1996 Stu Grossman (grossman@critters.cygnus.com)
-
- * dis-asm.h (print_insn_sparclite): Declare.
-
-Tue Jun 18 16:02:46 1996 Jeffrey A. Law <law@rtl.cygnus.com>
-
- * dis-asm.h (print_insn_h8300s): Declare.
-
-Tue Jun 18 15:11:33 1996 Klaus Kaempf <kkaempf@progis.de>
-
- * fopen-vms.h: New file.
-
-Tue Jun 4 18:58:16 1996 Ian Lance Taylor <ian@cygnus.com>
-
- * bfdlink.h (struct bfd_link_info): Add notice_all field.
-
-Fri Apr 26 10:33:12 1996 Doug Evans <dje@canuck.cygnus.com>
-
- * demangle.h (#ifdef IN_GCC): #include "gansidecl.h".
- (PROTO,PTR,const): Delete.
-
-Mon Apr 22 17:27:42 1996 Ian Lance Taylor <ian@cygnus.com>
-
- * bfdlink.h (struct bfd_link_info): Add traditional_format field.
-
-Mon Apr 15 15:16:56 1996 Doug Evans <dje@canuck.cygnus.com>
-
- * libiberty.h (choose_temp_base): Add prototype.
-
-Tue Mar 12 17:29:46 1996 Ian Lance Taylor <ian@cygnus.com>
-
- * bfdlink.h (bfd_wrapped_link_hash_lookup): Declare.
- (struct bfd_link_info): Add wrap_hash field.
-
-Wed Feb 14 16:49:17 1996 Martin Anantharaman <martin@mail.imech.uni-duisburg.de>
-
- * ieee.h (ieee_record_enum_type): Define
- ieee_external_reference_info_enum.
-
-Fri Feb 2 17:09:25 1996 Doug Evans <dje@charmed.cygnus.com>
-
- * dis-asm.h (DISASM_RAW_INSN): Delete.
-
-Tue Jan 23 09:21:47 1996 Doug Evans <dje@charmed.cygnus.com>
-
- * dis-asm.h (INIT_DISASSEMBLE_INFO): Set endian to BFD_ENDIAN_UNKNOWN.
- New argument FPRINTF_FUNC.
-
-Mon Jan 22 16:37:59 1996 Doug Evans <dje@charmed.cygnus.com>
-
- * dis-asm.h (disassemble_info): New members arch, mach, endian.
- (INIT_DISASSEMBLE_INFO): Initialize them.
- (DISASM_RAW_INSN{,FLAG}): Define.
-
-Thu Jan 18 11:32:38 1996 Ian Lance Taylor <ian@cygnus.com>
-
- * demangle.h (cplus_demangle_opname): Change opname parameter to
- const char *.
- (cplus_mangle_opname): Change return type and opname parameter to
- const char *.
-
-Fri Jan 5 00:01:22 1996 Ian Lance Taylor <ian@cygnus.com>
-
- * ieee.h (enum ieee_record): Add ieee_asn_record_enum,
- ieee_at_record_enum, ieee_ty_record_enum, ieee_atn_record_enum,
- ieee_bb_record_enum, and ieee_be_record_enum.
-
-Wed Jan 3 13:12:09 1996 Fred Fish <fnf@cygnus.com>
-
- * obstack.h: Update copyright to 1996.
- (_obstack_memory_used): Declare.
- (obstack_memory_used): Define macro.
-
-Thu Dec 28 11:42:12 1995 Ian Lance Taylor <ian@cygnus.com>
-
- * libiberty.h (xstrdup): Declare.
-
-Thu Dec 21 14:47:17 1995 Michael Meissner <meissner@tiktok.cygnus.com>
-
- * wait.h: Protect all macros with #ifndef.
-
-Tue Oct 24 21:45:40 1995 Ian Lance Taylor <ian@cygnus.com>
-
- * bfdlink.h (struct bfd_link_info): Add static_link field.
-
-Tue Sep 12 16:28:04 1995 Ian Lance Taylor <ian@cygnus.com>
-
- * bfdlink.h (struct bfd_link_callbacks): Add symbol parameter to
- warning callback.
-
-Fri Sep 1 13:11:51 1995 Ian Lance Taylor <ian@cygnus.com>
-
- * bfdlink.h (struct bfd_link_callbacks): Change warning callback
- to take BFD, section, and address arguments.
-
-Thu Aug 31 16:45:12 1995 steve chamberlain <sac@slash.cygnus.com>
-
- * bfdlink.h (struct bfd_link_info): Remove PE stuff.
-
-Tue Aug 22 03:18:23 1995 Ken Raeburn <raeburn@kr-laptop.cygnus.com>
-
- * libiberty.h: Declare xstrerror. From Pat Rankin.
-
-Mon Aug 21 18:11:36 1995 steve chamberlain <sac@slash.cygnus.com>
-
- * bfdlink.h (struct bfd_link_info): Remove PE stuff.
-
-Wed Aug 2 08:14:12 1995 Doug Evans <dje@canuck.cygnus.com>
-
- * dis-asm.h (print_insn_sparc64): Declare.
-
-Mon Jul 10 13:26:49 1995 Eric Youngdale <eric@aib.com>
-
- * bfdlink.h (struct bfd_link_info): Add new field symbolic.
-
-Sun Jul 2 17:48:40 1995 Ian Lance Taylor <ian@cygnus.com>
-
- * bfdlink.h (struct bfd_link_info): Change type of base_file to
- PTR.
-
-Thu Jun 29 00:02:45 1995 Steve Chamberlain <sac@slash.cygnus.com>
-
- * bfdlink.h (struct bfd_link_info): Added base_file member.
-
-Tue Jun 20 16:40:04 1995 Steve Chamberlain <sac@slash.cygnus.com>
-
- * ansidecl.h: win32s is ANSI enough.
-
-Thu May 18 04:25:50 1995 Ken Raeburn <raeburn@kr-laptop.cygnus.com>
-
- Wed May 10 14:28:16 1995 Richard Earnshaw (rearnsha@armltd.co.uk)
-
- * dis-asm.h (print_insn_arm): Delete declaration.
- (print_insn_{little,big}_arm): New declarations.
-
- * floatformat.h (floatformat_arm_ext): Declare.
-
-Sat May 13 10:14:08 1995 Steve Chamberlain <sac@slash.cygnus.com>
-
- * coff/pe.h: New file.
- * bfdlink.h (subsytem, stack_heap_parameters): New.
- * coff/i386.h (NT_SECTION_ALIGNMENT, NT_FILE_ALIGNMENT,
- NT_DEF_RESERVE, NT_DEF_COMMIT): New.
- * coff/internal.h (internal_filehdr): New fields for PE.
- (IMAGE_DATA_DIRECTORY): New.
- (internal_aouthdr): New fields for PE.
-
-Thu May 4 14:36:42 1995 Jason Merrill <jason@phydeaux.cygnus.com>
-
- * demangle.h: Don't include ansidecl.h if IN_GCC.
-
-Tue Feb 21 00:37:28 1995 Jeff Law (law@snake.cs.utah.edu)
-
- * hp-symtab.h: Don't use bitfield enumerations, the HP C compiler
- does not handle them correctly.
-
-Thu Feb 9 14:20:27 1995 Ian Lance Taylor <ian@cygnus.com>
-
- * libiberty.h (basename): Don't declare parameter type; some
- systems have this in their header files.
-
-Wed Feb 8 17:35:38 1995 Ian Lance Taylor <ian@cygnus.com>
-
- * bfdlink.h (struct bfd_link_hash_entry): Change format of common
- symbol information, to remove restrictions on maximum size and
- alignment power, by using a pointer to a structure instead.
-
-Mon Feb 6 14:55:32 1995 Ian Lance Taylor <ian@cygnus.com>
-
- * bfdlink.h (enum bfd_link_hash_type): Rename bfd_link_hash_weak
- to bfd_link_hash_undefweak. Add bfd_link_hash_defweak.
-
-Mon Jan 16 21:00:23 1995 Stan Shebs <shebs@andros.cygnus.com>
-
- * dis-asm.h (GDB_INIT_DISASSEMBLE_INFO, etc): Remove all
- GDB-specific definitions.
-
-Sun Jan 15 18:39:35 1995 Steve Chamberlain <sac@splat>
-
- * dis-asm.h (print_insn_w65): Declare.
-
-Thu Jan 12 17:51:17 1995 Ken Raeburn <raeburn@cujo.cygnus.com>
-
- * libiberty.h (hex_p): Fix sense of test.
-
-Wed Jan 11 22:36:40 1995 Ken Raeburn <raeburn@cujo.cygnus.com>
-
- * libiberty.h (_hex_array_size, _hex_bad, _hex_value, hex_init,
- hex_p, hex_value): New macros and declarations, for hex.c.
-
-Fri Jan 6 17:44:14 1995 Ian Lance Taylor <ian@sanguine.cygnus.com>
-
- * dis-asm.h: Make idempotent.
-
-Wed Dec 14 13:08:43 1994 Stan Shebs <shebs@andros.cygnus.com>
-
- * progress.h: New file, empty definitions for progress macros.
-
-Fri Nov 25 00:14:05 1994 Jeff Law (law@snake.cs.utah.edu)
-
- * hp-symtab.h: New file describing the debug symbols emitted
- by the HP C compilers.
-
-Fri Nov 11 15:48:37 1994 Ian Lance Taylor <ian@sanguine.cygnus.com>
-
- * bfdlink.h (struct bfd_link_hash_entry): Change u.c.size from 24
- to 26 bits, and change u.c.alignment_power from 8 to 6 bits. 6
- bit in the alignment power is enough for a 64 bit address space.
-
-Mon Oct 31 13:02:51 1994 Stan Shebs (shebs@andros.cygnus.com)
-
- * demangle.h (cplus_mangle_opname): Declare.
-
-Tue Oct 25 11:38:02 1994 Ian Lance Taylor <ian@sanguine.cygnus.com>
-
- * bfdlink.h (struct bfd_link_callbacks): Fix comments for
- multiple_common field.
-
-Sun Sep 04 17:58:10 1994 Richard Earnshaw (rwe@pegasus.esprit.ec.org)
-
- * aout/aout64.h: Only define QMAGIC if it isn't already defined.
-
- * dis-asm.h: Add support for the ARM.
-
-Wed Aug 10 12:51:41 1994 Doug Evans (dje@canuck.cygnus.com)
-
- * libiberty.h (strsignal): Document its existence even if we
- can't declare it.
-
-Tue Aug 2 14:40:03 1994 Jim Kingdon (kingdon@lioth.cygnus.com)
-
- * os9k.h: Remove u_int16, u_int32, and owner_id typedefs and
- expand their uses. Those names conflict with Mach headers.
-
-Fri Jul 22 14:17:12 1994 Ian Lance Taylor (ian@sanguine.cygnus.com)
-
- * bfdlink.h (struct bfd_link_hash_entry): Change u.c.size into a
- bitfield. Add field u.c.alignment_power.
-
-Sun Jul 10 00:26:39 1994 Ian Dall (dall@hfrd.dsto.gov.au)
-
- * dis-asm.h: Add print_insn_ns32k declaration.
-
-Mon Jun 20 17:13:29 1994 Ian Lance Taylor (ian@sanguine.cygnus.com)
-
- * bfdlink.h (bfd_link_hash_table): Make creator a const pointer.
-
-Sat Jun 18 16:09:32 1994 Stan Shebs (shebs@andros.cygnus.com)
-
- * demangle.h (cplus_demangle_opname): Declare.
-
-Thu Jun 16 15:19:03 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com)
-
- * bfdlink.h (struct bfd_link_info): Add new field shared.
-
-Mon Jun 6 14:39:44 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com)
-
- * bfdlink.h (struct bfd_link_hash_entry): Remove written field:
- not needed for all backends.
-
-Thu Apr 28 19:06:50 1994 Ken Raeburn (raeburn@cujo.cygnus.com)
-
- * dis-asm.h (disassembler): Declare.
-
-Fri Apr 1 00:38:17 1994 Jim Wilson (wilson@mole.gnu.ai.mit.edu)
-
- * obstack.h: Delete use of IN_GCC to control whether
- stddef.h or gstddef.h is included.
-
-Tue Mar 22 13:06:02 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com)
-
- * bfdlink.h (enum bfd_link_order_type): Add bfd_data_link_order.
- (struct bfd_link_order): Add data field to union.
-
-Mon Mar 21 18:45:26 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com)
-
- * bfdlink.h (struct bfd_link_callbacks): Change bitsize argument
- to add_to_set to reloc. Remove bitsize argument from constructor.
- Comment that reloc_overflow, reloc_dangerous and unattached_reloc
- must handle NULL pointers for reloc location.
- (enum bfd_link_order_type): Add bfd_section_reloc_link_order and
- bfd_symbol_reloc_link_order.
- (struct bfd_link_order): Add reloc field to union.
- (struct bfd_link_order_reloc): Define.
-
-Mon Mar 14 12:27:50 1994 Ian Lance Taylor (ian@cygnus.com)
-
- * ieee-float.h: Removed; no longer used.
-
-Tue Mar 1 18:10:49 1994 Kung Hsu (kung@mexican.cygnus.com)
-
- * os9k.h: os9000 target specific header file, the header of the
- object file is used now.
-
-Sun Feb 27 21:52:26 1994 Jim Kingdon (kingdon@deneb.cygnus.com)
-
- * floatformat.h: New file, intended to replace ieee-float.h.
-
-Sun Feb 20 17:15:42 1994 Ian Lance Taylor (ian@lisa.cygnus.com)
-
- * ansidecl.h (ANSI_PROTOTYPES): Define if using ANSI prototypes.
-
-Wed Feb 16 01:07:12 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com)
-
- * libiberty.h: Don't declare strsignal, to avoid conflicts with
- Solaris system header files.
-
-Sat Feb 12 22:11:32 1994 Jeffrey A. Law (law@snake.cs.utah.edu)
-
- * libiberty.h (xexit): Use __volatile__ to avoid losing if
- compiling with gcc -traditional.
-
-Thu Feb 10 14:05:41 1994 Ian Lance Taylor (ian@cygnus.com)
-
- * libiberty.h: New file. Declares functions provided by
- libiberty.
-
-Tue Feb 8 05:19:52 1994 David J. Mackenzie (djm@thepub.cygnus.com)
-
- Handle obstack_chunk_alloc returning NULL. This allows
- obstacks to be used by libraries, without forcing them
- to call exit or longjmp.
- * obstack.h (struct obstack): Add alloc_failed flag.
- _obstack_begin, _obstack_begin_1): Declare to return int, not void.
- (obstack_finish): If alloc_failed, return NULL.
- (obstack_base, obstack_next_free, objstack_object_size):
- If alloc_failed, return 0.
- (obstack_grow, obstack_grow0, obstack_1grow, obstack_ptr_grow,
- obstack_int_grow, obstack_blank): If alloc_failed, do nothing that
- could corrupt the obstack.
-
-Mon Jan 24 15:06:05 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com)
-
- * bfdlink.h (struct bfd_link_callbacks): Add name, reloc_name and
- addend argments to reloc_overflow callback.
-
-Fri Jan 21 19:13:12 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com)
-
- * dis-asm.h (print_insn_big_powerpc, print_insn_little_powerpc,
- print_insn_rs6000): Declare.
-
-Thu Jan 6 14:15:55 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com)
-
- * bfdlink.h (struct bfd_link_callbacks): Add bitsize argument to
- add_to_set field. Add new callback named constructor.
-
-Thu Dec 30 10:44:06 1993 Ian Lance Taylor (ian@rtl.cygnus.com)
-
- * bfdlink.h: New file for new BFD linker backend routines.
-
-Mon Nov 29 10:43:57 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com)
-
- * dis-asm.h (enum dis_insn_tyupe): Remove non-ANSI trailing comma.
-
-Sat Oct 2 20:42:26 1993 Jim Kingdon (kingdon@lioth.cygnus.com)
-
- * dis-asm.h: Move comment to right place.
-
-Mon Aug 9 19:03:35 1993 David J. Mackenzie (djm@thepub.cygnus.com)
-
- * obstack.h (obstack_chunkfun, obstack_freefun): Add defns from
- previous version. Are these Cygnus local changes?
-
-Fri Aug 6 17:05:47 1993 David J. Mackenzie (djm@thepub.cygnus.com)
-
- * getopt.h, obstack.h: Update to latest FSF version.
-
-Mon Aug 2 16:37:14 1993 Stu Grossman (grossman at cygnus.com)
-
- * coff/i386.h: Add Lynx magic number.
-
-Mon Aug 2 14:45:29 1993 John Gilmore (gnu@cygnus.com)
-
- * dis-asm.h: Move enum outside of struct defn to avoid warnings.
-
-Mon Aug 2 08:49:30 1993 Stu Grossman (grossman at cygnus.com)
-
- * wait.h (WEXITSTATUS, WSTOPSIG): Mask down to 8 bits. This is
- for systems that store stuff into the high 16 bits of a wait
- status.
-
-Fri Jul 30 18:38:02 1993 John Gilmore (gnu@cygnus.com)
-
- * dis-asm.h: Add new fields insn_info_valid, branch_delay_insns,
- data_size, insn_type, target, target2. These are used to return
- information from the instruction decoders back to the calling
- program. Add comments, make more readable.
-
-Mon Jul 19 22:14:14 1993 Fred Fish (fnf@deneb.cygnus.com)
-
- * nlm: New directory containing NLM/NetWare includes.
-
-Thu Jul 15 12:10:04 1993 Ken Raeburn (raeburn@cambridge.cygnus.com)
-
- * dis-asm.h (struct disassemble_info): New field application_data.
-
-Thu Jul 15 12:41:15 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com)
-
- * dis-asm.h: Added declaration of print_insn_m88k.
-
-Thu Jul 8 09:05:26 1993 Doug Evans (dje@canuck.cygnus.com)
-
- * opcode/h8300.h: Lots of little fixes for the h8/300h.
-
-Fri Jul 2 10:31:59 1993 Ian Lance Taylor (ian@cygnus.com)
-
- * ansidecl.h: Use ANSI macros if __mips and _SYSTYPE_SVR4 are
- defined, since RISC/OS cc handles ANSI declarations in SVR4 mode
- but does not define __STDC__.
-
-Sun Jun 20 18:27:52 1993 Ken Raeburn (raeburn@poseidon.cygnus.com)
-
- * dis-asm.h: Don't need to include ansidecl.h any more.
-
-Fri Jun 18 03:22:10 1993 John Gilmore (gnu@cygnus.com)
-
- * oasys.h: Eliminate "int8_type", "int16_type", "int32_type", and
- their variants. These changes are coordinated with corresponding
- changes in ../bfd/oasys.c.
-
-Wed Jun 16 10:43:08 1993 Fred Fish (fnf@cygnus.com)
-
- * bfd.h: Note that it has been removed.
-
-Tue Jun 8 12:16:03 1993 Steve Chamberlain (sac@phydeaux.cygnus.com)
-
- Support for H8/300-H
- * dis-asm.h (print_insn_h8300, print_insn_h8300h): Declare it.
- * coff/h8300.h: New magic number.
- * coff/internal.h: New relocations.
- * opcode/h8300.h: Lots of new opcodes.
-
-Tue Jun 1 07:35:03 1993 Ken Raeburn (raeburn@kr-pc.cygnus.com)
-
- * ansidecl.h (const): Don't define it if it's already defined.
-
-Thu May 27 18:19:51 1993 Ken Raeburn (raeburn@cambridge.cygnus.com)
-
- * dis-asm.h (print_insn_hppa): Declare it.
-
- * bfd.h: Moved to bfd directory. Small stub here includes it
- without requiring "-I../bfd".
-
-Thu Apr 29 12:06:13 1993 Ken Raeburn (raeburn@deneb.cygnus.com)
-
- * bfd.h: Updated with BSF_FUNCTION.
-
-Mon Apr 26 18:15:50 1993 Steve Chamberlain (sac@thepub.cygnus.com)
-
- * bfd.h, dis-asm.h: Updated with Hitachi SH.
-
-Fri Apr 23 18:41:38 1993 Steve Chamberlain (sac@thepub.cygnus.com)
-
- * bfd.h: Updated with alpha changes.
- * dis-asm.h: Added alpha.
-
-Fri Apr 16 17:35:30 1993 Jim Kingdon (kingdon@cygnus.com)
-
- * bfd.h: Update for signed bfd_*get_*.
-
-Thu Apr 15 09:24:21 1993 Jim Kingdon (kingdon@cygnus.com)
-
- * bfd.h: Updated for file_truncated error.
-
-Thu Apr 8 10:53:47 1993 Ian Lance Taylor (ian@cygnus.com)
-
- * ansidecl.h: If no ANSI, define const to be empty.
-
-Thu Apr 1 09:00:10 1993 Jim Kingdon (kingdon@cygnus.com)
-
- * dis-asm.h: Declare a29k and i960 print_insn_*.
-
- * dis-asm.h: Add print_address_func and related stuff.
-
- * dis-asm.h (dis_asm_read_memory): Fix prototype.
-
-Wed Mar 31 17:40:16 1993 Jim Kingdon (kingdon@lioth.cygnus.com)
-
- * dis-asm.h: Add print_insn_sparc.
-
-Wed Mar 31 17:51:42 1993 Ian Lance Taylor (ian@cygnus.com)
-
- * bfd.h: Updated for BFD_RELOC_MIPS_GPREL and bfd_[gs]et_gp_size
- prototypes.
-
-Wed Mar 31 16:35:12 1993 Stu Grossman (grossman@cygnus.com)
-
- * dis-asm.h: (disassemble_info): Fix typo in prototype of
- dis_asm_memory_error().
-
-Tue Mar 30 19:09:23 1993 Jim Kingdon (kingdon@lioth.cygnus.com)
-
- * dis-asm.h (disassembler_info): Add read_memory_func,
- memory_error_func, buffer, and length.
- ({GDB_,}INIT_DISASSEMBLE_INFO): Set them.
- print_insn_*: Remove second argument.
-
-Tue Mar 30 14:48:55 1993 Steve Chamberlain (sac@thepub.cygnus.com)
-
- * bfd.h: Update for lma field of section.
-
-Tue Mar 30 12:22:55 1993 Jim Kingdon (kingdon@cygnus.com)
-
- * ansidecl.h: Use ANSI versions on AIX regardless of __STDC__.
-
-Fri Mar 19 14:49:49 1993 Steve Chamberlain (sac@thepub.cygnus.com)
-
- * dis-asm.h: Add h8500.
-
-Thu Mar 18 13:49:09 1993 Per Bothner (bothner@rtl.cygnus.com)
-
- * ieee-float.h: Moved from ../gdb.
- * dis-asm.h: New file. Interface to dis-assembler.
-
-Thu Mar 11 10:52:57 1993 Fred Fish (fnf@cygnus.com)
-
- * demangle.h (DMGL_NO_OPTS): Add define (set to 0) to use
- in place of bare 0, for readability reasons.
-
-Tue Mar 2 17:50:11 1993 Fred Fish (fnf@cygnus.com)
-
- * demangle.h: Replace all references to cfront with ARM.
-
-Tue Feb 23 12:21:14 1993 Ian Lance Taylor (ian@cygnus.com)
-
- * bfd.h: Update for new elements in JUMP_TABLE.
-
-Tue Feb 16 00:51:30 1993 John Gilmore (gnu@cygnus.com)
-
- * bfd.h: Update for BFD_VERSION 2.1.
-
-Tue Jan 26 11:49:20 1993 Ian Lance Taylor (ian@cygnus.com)
-
- * bfd.h: Update for SEC_IS_COMMON flag.
-
-Tue Jan 19 12:25:12 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com)
-
- * bfd.h: Update for bfd_asymbol_value bug fix.
-
-Fri Jan 8 16:37:18 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com)
-
- * bfd.h: Update to include ECOFF tdata and target_flavour.
-
-Sun Dec 27 17:52:30 1992 Fred Fish (fnf@cygnus.com)
-
- * bfd.h: Add declaration for bfd_get_size().
-
-Tue Dec 22 22:42:46 1992 Fred Fish (fnf@cygnus.com)
-
- * demangle.h: Protect file from multiple inclusions with
- #if !defined(DEMANGLE_H)...#define DEMANGLE_H...#endif.
-
-Mon Dec 21 21:25:50 1992 Stu Grossman (grossman at cygnus.com)
-
- * bfd.h: Update to get hppa_core_struct from bfd.c.
-
-Thu Dec 17 00:42:35 1992 John Gilmore (gnu@cygnus.com)
-
- * bfd.h: Update to get tekhex tdata name change from bfd.
-
-Mon Nov 9 23:55:42 1992 John Gilmore (gnu@cygnus.com)
-
- * ansidecl.h: Update comments to discourage use of EXFUN.
-
-Thu Nov 5 16:35:44 1992 Ian Lance Taylor (ian@cygnus.com)
-
- * bfd.h: Update to bring in SEC_SHARED_LIBRARY.
-
-Thu Nov 5 03:21:32 1992 John Gilmore (gnu@cygnus.com)
-
- * bfd.h: Update to match EXFUN, bfd_seclet_struct, and SDEF
- cleanups in bfd.
-
-Wed Nov 4 07:28:05 1992 Ken Raeburn (raeburn@cygnus.com)
-
- * bout.h (N_CALLNAME, N_BALNAME): Define as char-type values, so
- widening works consistently.
-
-Fri Oct 16 03:17:08 1992 John Gilmore (gnu@cygnus.com)
-
- * getopt.h: Update to Revised Standard FSF Version.
-
-Thu Oct 15 21:43:22 1992 K. Richard Pixley (rich@sendai.cygnus.com)
-
- * getopt.h (struct option): use the provided enum for has_arg.
-
- * demangle.h (AUTO_DEMANGLING, GNU_DEMANGLING,
- LUCID_DEMANGLING): ultrix compilers require enums to be
- enums and ints to be ints and casts where they meet. cast some
- enums into ints.
-
-Thu Oct 15 04:35:51 1992 John Gilmore (gnu@cygnus.com)
-
- * bfd.h: Update after comment changes.
-
-Thu Oct 8 09:03:02 1992 Steve Chamberlain (sac@thepub.cygnus.com)
-
- * bfd.h (bfd_get_symbol_leading_char): new macro for getting in xvec
-
-Thu Sep 3 09:10:50 1992 Stu Grossman (grossman at cygnus.com)
-
- * bfd.h (struct reloc_howto_struct): size needs to be signed if
- it's going to hold negative values.
-
-Sun Aug 30 17:50:27 1992 Per Bothner (bothner@rtl.cygnus.com)
-
- * demangle.h: New file, moved from ../gdb. Made independent
- of gdb. Allow demangling style option to be passed as a
- parameter to cplus_demangle(), but using the
- current_demangling_style global as the default.
-
-Sat Aug 29 10:07:55 1992 Fred Fish (fnf@cygnus.com)
-
- * obstack.h: Merge comment change from current FSF version.
-
-Thu Aug 27 12:59:29 1992 Brendan Kehoe (brendan@cygnus.com)
-
- * bfd.h: add we32k
-
-Tue Aug 25 15:07:47 1992 Steve Chamberlain (sac@thepub.cygnus.com)
-
- * bfd.h: new after Z8000 stuff
-
-Mon Aug 17 09:01:23 1992 Ken Raeburn (raeburn@cygnus.com)
-
- * bfd.h: Regenerated after page/segment size changes.
-
-Sat Aug 1 13:46:31 1992 Fred Fish (fnf@cygnus.com)
-
- * obstack.h: Merge changes from current FSF version.
-
-Mon Jul 20 21:06:23 1992 Fred Fish (fnf@cygnus.com)
-
- * obstack.h (area_id, flags): Remove, replace with extra_arg,
- use_extra_arg, and maybe_empty_object.
- * obstack.h (OBSTACK_MAYBE_EMPTY_OBJECT, OBSTACK_MMALLOC_LIKE):
- Remove, replaced by maybe_empty_object and use_extra_arg bitfields.
- * obstack.h (obstack_full_begin, _obstack_begin): Remove area_id
- and flags arguments.
- * obstack.h (obstack_alloc_arg): New macro to set extra_arg.
-
-Thu Jul 16 08:12:44 1992 Steve Chamberlain (sac@thepub.cygnus.com)
-
- * bfd.h: new after adding BFD_IS_RELAXABLE
-
-Sat Jul 4 03:22:23 1992 John Gilmore (gnu at cygnus.com)
-
- * bfd.h: Regen after adding BSF_FILE.
-
-Mon Jun 29 14:18:36 1992 Fred Fish (fnf at sunfish)
-
- * obstack.h: Convert bcopy() use to memcpy(), which is more
- portable, more standard, and can take advantage of gcc's builtin
- functions for increased performance.
-
-Thu Jun 25 04:46:08 1992 John Gilmore (gnu at cygnus.com)
-
- * ansidecl.h (PARAMS): Incorporate this macro from gdb's defs.h.
- It's a cleaner way to forward-declare function prototypes.
-
-Fri Jun 19 15:46:32 1992 Stu Grossman (grossman at cygnus.com)
-
- * bfd.h: HPPA merge.
-
-Tue Jun 16 21:30:56 1992 K. Richard Pixley (rich@cygnus.com)
-
- * getopt.h: gratuitous white space changes merged from other prep
- releases.
-
-Thu Jun 11 01:10:55 1992 John Gilmore (gnu at cygnus.com)
-
- * bfd.h: Regen'd from bfd.c after removing elf_core_tdata_struct.
-
-Mon May 18 17:29:03 1992 K. Richard Pixley (rich@cygnus.com)
-
- * getopt.h: merged changes from make-3.62.11.
-
- * getopt.h: merged changes from grep-1.6 (alpha).
-
-Fri May 8 14:53:32 1992 K. Richard Pixley (rich@cygnus.com)
-
- * getopt.h: merged changes from bison-1.18.
-
-Sat Mar 14 17:25:20 1992 Fred Fish (fnf@cygnus.com)
-
- * obstack.h: Add "area_id" and "flags" members to obstack
- structure. Add obstack_chunkfun() and obstack_freefun() to
- set functions explicitly. Convert maybe_empty_object to
- a bit in "flags".
-
-Thu Feb 27 22:01:02 1992 Per Bothner (bothner@cygnus.com)
-
- * wait.h (WIFSTOPPED): Add IBM rs6000-specific version.
-
-Fri Feb 21 20:49:20 1992 John Gilmore (gnu at cygnus.com)
-
- * obstack.h: Add obstack_full_begin.
- * bfd.h, obstack.h: Protolint.
-
-Thu Jan 30 01:18:42 1992 John Gilmore (gnu at cygnus.com)
-
- * bfd.h: Remove comma from enum declaration.
-
-Mon Jan 27 22:01:13 1992 Steve Chamberlain (sac at cygnus.com)
-
- * bfd.h : new target entr, bfd_relax_section
-
-Wed Dec 18 17:19:44 1991 Stu Grossman (grossman at cygnus.com)
-
- * bfd.h, ieee.h, opcode/m68k.h, opcode/sparc.h: ANSIfy enums.
-
-Thu Dec 12 20:59:56 1991 John Gilmore (gnu at cygnus.com)
-
- * fopen-same.h, fopen-bin.h: New files for configuring
- whether fopen distinguishes binary files or not. For use
- by host-dependent config files.
-
-Sat Nov 30 20:46:43 1991 Steve Chamberlain (sac at rtl.cygnus.com)
-
- * bfd.h: change the documentation format.
-
- * created coff, elf and opcode and aout directories. Moved:
-
- aout64.h ==> aout/aout64.h
- ar.h ==> aout/ar.h
- a.out.encap.h ==> aout/encap.h
- a.out.host.h ==> aout/host.h
- a.out.hp.h ==> aout/hp.h
- a.out.sun4.h ==> aout/sun4.h
- ranlib.h ==> aout/ranlib.h
- reloc.h ==> aout/reloc.h
- stab.def ==> aout/stab.def
- stab.gnu.h ==> aout/stab_gnu.h
-
- coff-a29k.h ==> coff/a29k.h
- coff-h8300.h ==> coff/h8300.h
- coff-i386.h ==> coff/i386.h
- coff-i960.h ==> coff/i960.h
- internalcoff.h ==> coff/internal.h
- coff-m68k.h ==> coff/m68k.h
- coff-m88k.h ==> coff/m88k.h
- coff-mips.h ==> coff/mips.h
- coff-rs6000.h ==> coff/rs6000.h
-
- elf-common.h ==> elf/common.h
- dwarf.h ==> elf/dwarf.h
- elf-external.h ==> elf/external.h
- elf-internal.h ==> elf/internal.h
-
- a29k-opcode.h ==> opcode/a29k.h
- arm-opcode.h ==> opcode/arm.h
- h8300-opcode.h ==> opcode/h8300.h
- i386-opcode.h ==> opcode/i386.h
- i860-opcode.h ==> opcode/i860.h
- i960-opcode.h ==> opcode/i960.h
- m68k-opcode.h ==> opcode/m68k.h
- m88k-opcode.h ==> opcode/m88k.h
- mips-opcode.h ==> opcode/mips.h
- np1-opcode.h ==> opcode/np1.h
- ns32k-opcode.h ==> opcode/ns32k.h
- pn-opcode.h ==> opcode/pn.h
- pyr-opcode.h ==> opcode/pyr.h
- sparc-opcode.h ==> opcode/sparc.h
- tahoe-opcode.h ==> opcode/tahoe.h
- vax-opcode.h ==> opcode/vax.h
-
-
-
-Wed Nov 27 10:38:31 1991 Steve Chamberlain (sac at rtl.cygnus.com)
-
- * internalcoff.h: (internal_scnhdr) took out #def dependency, now
- s_nreloc and s_nlnno are always long.
- (internal_reloc): Always has an offset field now.
-
-Fri Nov 22 08:12:58 1991 John Gilmore (gnu at cygnus.com)
-
- * coff-rs6000.h: Lint; use unsigned chars for external fields.
- * internalcoff.h: Lint; cast storage classes to signed char.
-
-Thu Nov 21 21:01:05 1991 Per Bothner (bothner at cygnus.com)
-
- * stab.def: Remove the GNU extended type codes (e.g. N_SETT).
- * aout64.h: The heuristic for distinguishing between
- sunos-style and bsd-style ZMAGIC files (wrt. where the
- text segment starts) is moved into (the default definition of)
- the macro N_HEADER_IN_TEXT. This definition is only used
- if no other definition is used - e.g. bfd/newsos3.c defines
- N_HEADER_IN_TEXT(x) to be always 0 (as before).
-
-Thu Nov 21 11:53:03 1991 John Gilmore (gnu at cygnus.com)
-
- * aout64.h (N_TXTADDR, N_TXTOFF, N_TXTSIZE): New definitions
- that should handle all uses. LOGICAL_ versions deleted.
- Eliminate N_HEADER_IN_TEXT, using a_entry to determine which
- kind of zmagic a.out file we are looking at.
- * coff-rs6000.h: Typo.
-
-Tue Nov 19 18:43:37 1991 Per Bothner (bothner at cygnus.com)
-
- (Note: This is a revised entry, as was aout64.h.)
- * aout64.h: Some cleanups of N_TXTADDR and N_TXTOFF:
- Will now work for both old- and new-style ZMAGIC files,
- depending on N_HEADER_IN_TEXT macro.
- Add LOGICAL_TXTADDR, LOICAL_TXTOFF and LOGICAL_TXTSIZE
- that don't count the exec header as part
- of the text segment, to be consistent with bfd.
- * a.out.sun4.h: Simplified/fixed for previous change.
-
-Mon Nov 18 00:02:06 1991 Fred Fish (fnf at cygnus.com)
-
- * dwarf.h: Update to DWARF draft 5 version from gcc2.
-
-Thu Nov 14 19:44:59 1991 Per Bothner (bothner at cygnus.com)
-
- * stab.def: Added defs for extended GNU symbol types,
- such as N_SETT. These are normally ifdef'd out (because
- of conflicts with a.out.gnu.h), but are used by bfb_stab_name().
-
-Thu Nov 14 19:17:03 1991 Fred Fish (fnf at cygnus.com)
-
- * elf-common.h: Add defines to support ELF symbol table code.
-
-Mon Nov 11 19:01:06 1991 Fred Fish (fnf at cygnus.com)
-
- * elf-internal.h, elf-external.h, elf-common.h: Add support for
- note sections, which are used in ELF core files to hold copies
- of various /proc structures.
-
-Thu Nov 7 08:58:26 1991 Steve Chamberlain (sac at cygnus.com)
-
- * internalcoff.h: took out the M88 dependency in the lineno
- struct.
- * coff-m88k.h: defines GET_LINENO_LNNO and PUT_LINENO_LNNO to use
- 32bit linno entries.
- * a29k-opcode.h: fixed encoding of mtacc
-
-Sun Nov 3 11:54:22 1991 Per Bothner (bothner at cygnus.com)
-
- * bfd.h: Updated from ../bfd/bfd-in.h (q.v).
-
-Fri Nov 1 11:13:53 1991 John Gilmore (gnu at cygnus.com)
-
- * internalcoff.h: Add x_csect defines.
-
-Fri Oct 25 03:18:20 1991 John Gilmore (gnu at cygnus.com)
-
- * Rename COFF-related files in `coff-ARCH.h' form.
- coff-a29k.h, coff-i386.h, coff-i960.h, coff-m68k.h, coff-m88k.h,
- coff-mips.h, coff-rs6000.h to be exact.
-
-Thu Oct 24 22:11:11 1991 John Gilmore (gnu at cygnus.com)
-
- RS/6000 support, by Metin G. Ozisik, Mimi Phûông-Thåo Võ, and
- John Gilmore.
-
- * a.out.gnu.h: Update slightly.
- * bfd.h: Add new error code, fix doc, add bfd_arch_rs6000.
- * internalcoff.h: Add more F_ codes for filehdr. Add
- rs/6000-dependent fields to aouthdr. Add storage classes
- to syments. Add 6000-specific auxent. Add r_size in reloc.
- * rs6000coff.c: New file.
-
-Thu Oct 24 04:13:20 1991 Fred Fish (fnf at cygnus.com)
-
- * dwarf.h: New file for dwarf support. Copied from gcc2
- distribution.
-
-Wed Oct 16 13:31:45 1991 John Gilmore (gnu at cygnus.com)
-
- * aout64.h: Remove PAGE_SIZE defines; they are target-dependent.
- Add N_FN_SEQ for N_FN symbol type used on Sequent machines.
- * stab.def: Include N_FN_SEQ in table.
- * bout.h: External formats of structures use unsigned chars.
-
-Fri Oct 11 12:40:43 1991 Steve Chamberlain (steve at cygnus.com)
-
- * bfd.h:upgrade from bfd.c
- * internalcoff.h: add n_name, n_zeroes and n_offset macros
- * amdcoff.h: Define OMAGIC and AOUTHDRSZ.
-
-Fri Oct 11 10:58:06 1991 Per Bothner (bothner at cygnus.com)
-
- * a.out.host.h: Change SEGMENT_SIZE to 0x1000 for Sony.
- * bfd.h (align_power): Add (actually move) comment.
-
-Tue Oct 8 15:29:32 1991 Per Bothner (bothner at cygnus.com)
-
- * sys/h-rtbsd.h: Define MISSING_VFPRINT (for binutils/bucomm.c).
-
-Sun Oct 6 19:24:39 1991 John Gilmore (gnu at cygnus.com)
-
- * aout64.h: Move struct internal_exec to ../bfd/libaout.h so
- it can be shared by all `a.out-family' code. Rename
- EXTERNAL_LIST_SIZE to EXTERNAL_NLIST_SIZE. Use basic types
- for nlist members, and make strx integral rather than pointer.
- More commentary on n_type values.
- * bout.h: Provide a struct external_exec rather than an
- internal_exec.
- * m68kcoff.h: Remove `tagentries' which snuck in from the i960
- COFF port.
-
-Fri Oct 4 01:25:59 1991 John Gilmore (gnu at cygnus.com)
-
- * h8300-opcode.h: Remove `_enum' from the typedef for an enum.
- * bfd.h: Update to match bfd changes.
-
- * sys/h-i386mach.h, sysdep.h: Add 386 Mach host support.
-
-Tue Oct 1 04:58:42 1991 John Gilmore (gnu at cygnus.com)
-
- * bfd.h, elf-common.h, elf-external.h, elf-internal.h:
- Add preliminary ELF support, sufficient for GDB, from Fred Fish.
- * sysdep.h, sys/h-amix.h: Support Amiga SVR4.
-
- * sys/h-vaxult.h: Make it work. (David Taylor <taylor@think.com>)
- * a.out.vax.h: Remove unused and confusing file.
-
-Mon Sep 30 12:52:35 1991 Per Bothner (bothner at cygnus.com)
-
- * sysdep.h: Define NEWSOS3_SYS, and use it.
-
-Fri Sep 20 13:38:21 1991 John Gilmore (gnu at cygnus.com)
-
- * a.out.gnu.h (N_FN): Its value *really is* 0x1F.
- Fix it, and add comments warning about or-ing N_EXT with it
- and/or N_WARNING.
- * aout64.h (N_FN): Fix value, add comments about N_EXT.
- * stab.def (table at end): Update to show all the type
- values <0x20, including low order bits. Move N_FN to
- its rightful place.
-
-Tue Sep 17 17:41:37 1991 Stu Grossman (grossman at cygnus.com)
-
- * sys/h-irix3.h: sgi/irix support.
-
-Tue Sep 17 07:52:59 1991 John Gilmore (gnu at cygint.cygnus.com)
-
- * stab.def (N_DEFD): Add GNU Modula-2 debug stab, from Andrew
- Beers.
-
-Thu Sep 12 14:12:59 1991 John Gilmore (gnu at cygint.cygnus.com)
-
- * internalcoff.h (SYMNMLEN, FILNMLEN, DIMNUM): Define these
- for internalcoff, separately from the various external coff's.
- * amdcoff.h, bcs88kcoff.h, i386coff.h, intel-coff.h, m68kcoff.h,
- m88k-bcs.h: Prefix SYMNMLEN, FILNMLEN, and DIMNUM with E_'s for
- the external struct definitions.
- * ecoff.h: Remove these #define's, kludge no longer needed.
-
- * sys/h-ultra3.h: Add new Ultracomputer host.
- * sysdep.h: Add ULTRA3_SYM1_SYS and use it.
-
-Tue Sep 10 10:11:46 1991 John Gilmore (gnu at cygint.cygnus.com)
-
- * i386coff.h (LINESZ): Always 6, not based on sizeof().
- (Fix from Peter Schauer <pes@regent.e-technik.tu-muenchen.de>.)
+2004-03-23 Alan Modra <amodra@bigpond.net.au>
-Wed Sep 4 08:58:37 1991 John Gilmore (gnu at cygint.cygnus.com)
+ PR 51.
+ * bfdlink.h (struct bfd_link_info): Add wrap_char.
- * a.out.gnu.h, aout64.h: Add N_WARNING. Change N_FN to 0x0E,
- to match SunOS and BSD. Add N_COMM as 0x12 for SunOS shared lib
- support.
- * stab.def: Add N_COMM to table, fix overlap comment.
+2004-03-20 H.J. Lu <hongjiu.lu@intel.com>
-Tue Sep 3 06:29:20 1991 John Gilmore (gnu at cygint.cygnus.com)
+ * bfdlink.h (bfd_link_info): Correct comments for the
+ unresolved_syms_in_objects field.
- Merge with latest FSF versions of these files.
+2004-02-24 Ian Lance Taylor <ian@wasabisystems.com>
- * stab.gnu.h: Add LAST_UNUSED_STAB_CODE.
- * stab.def: Update to GPL2. Move N_WARNING out, since not a
- debug symbol. Change comments, and reorder table to numeric
- order. Update final table comment.
- (N_DSLINE, N_BSLINE): Renumber from 0x66 and 0x68, to 0x46 and 0x48.
+ * dyn-string.h: Update copyright date.
- * obstack.h: GPL2. Merge.
+2004-02-23 Ian Lance Taylor <ian@wasabisystems.com>
-Fri Aug 23 01:54:23 1991 John Gilmore (gnu at cygint.cygnus.com)
+ * dyn-string.h: Remove test of IN_LIBGCC2 and IN_GLIBCPP_V3 and
+ the associated #defines.
- * a.out.gnu.h, a.out.sun4.h: Make SEGMENT_SIZE able to depend
- on the particular a.out being examined.
- * a.out.sun4.h: Define segment sizes for Sun-3's and Sun-4's.
- * FIXME: a.out.gnu.h is almost obsolete.
- * FIXME: a.out.sun4.h should be renamed a.out.sun.h now.
+2004-01-12 Ian Lance Taylor <ian@wasabisystems.com>
-Wed Aug 21 20:32:13 1991 John Gilmore (gnu at cygint.cygnus.com)
+ * demangle.h: Instead of checking ANSI_PROTOTYPES, just include
+ "libiberty.h".
- * Start a ChangeLog for the includes directory.
+ * demangle.h: If ANSI_PROTOTYPES is defined, include <stddef.h>.
- * a.out.gnu.h (N_FN): Fix value -- was 15, should be 0x1E.
- * stab.def: Update allocation table in comments at end,
- to reflect reality as I know it.
+ * demangle.h (enum demangle_component_type): Define.
+ (struct demangle_operator_info): Declare.
+ (struct demangle_builtin_type_info): Declare.
+ (struct demangle_component): Define.
+ (cplus_demangle_fill_component): Declare.
+ (cplus_demangle_fill_name): Declare.
+ (cplus_demangle_fill_builtin_type): Declare.
+ (cplus_demangle_fill_operator): Declare.
+ (cplus_demangle_fill_extended_operator): Declare.
+ (cplus_demangle_fill_ctor, cplus_demangle_fill_dtor): Declare.
+ (cplus_demangle_v3_components): Declare.
+ (cplus_demangle_print): Declare.
+For older changes see ChangeLog-9103
Local Variables:
mode: change-log
diff --git a/gnu/dist/binutils/include/ansidecl.h b/gnu/dist/binutils/include/ansidecl.h
index d2c87768ce2..2eeccf20351 100644
--- a/gnu/dist/binutils/include/ansidecl.h
+++ b/gnu/dist/binutils/include/ansidecl.h
@@ -149,7 +149,12 @@ So instead we use the macro below and test it against specific values. */
#define PTRCONST void *const
#define LONG_DOUBLE long double
+/* PARAMS is often defined elsewhere (e.g. by libintl.h), so wrap it in
+ a #ifndef. */
+#ifndef PARAMS
#define PARAMS(ARGS) ARGS
+#endif
+
#define VPARAMS(ARGS) ARGS
#define VA_START(VA_LIST, VAR) va_start(VA_LIST, VAR)
@@ -264,6 +269,14 @@ So instead we use the macro below and test it against specific values. */
#define ATTRIBUTE_UNUSED __attribute__ ((__unused__))
#endif /* ATTRIBUTE_UNUSED */
+/* Before GCC 3.4, the C++ frontend couldn't parse attributes placed after the
+ identifier name. */
+#if ! defined(__cplusplus) || (GCC_VERSION >= 3004)
+# define ARG_UNUSED(NAME) NAME ATTRIBUTE_UNUSED
+#else /* !__cplusplus || GNUC >= 3.4 */
+# define ARG_UNUSED(NAME) NAME
+#endif /* !__cplusplus || GNUC >= 3.4 */
+
#ifndef ATTRIBUTE_NORETURN
#define ATTRIBUTE_NORETURN __attribute__ ((__noreturn__))
#endif /* ATTRIBUTE_NORETURN */
@@ -277,6 +290,15 @@ So instead we use the macro below and test it against specific values. */
# endif /* GNUC >= 3.3 */
#endif /* ATTRIBUTE_NONNULL */
+/* Attribute `pure' was valid as of gcc 3.0. */
+#ifndef ATTRIBUTE_PURE
+# if (GCC_VERSION >= 3000)
+# define ATTRIBUTE_PURE __attribute__ ((__pure__))
+# else
+# define ATTRIBUTE_PURE
+# endif /* GNUC >= 3.0 */
+#endif /* ATTRIBUTE_PURE */
+
/* Use ATTRIBUTE_PRINTF when the format specifier must not be NULL.
This was the case for the `printf' format attribute by itself
before GCC 3.3, but as of 3.3 we need to add the `nonnull'
@@ -305,6 +327,15 @@ So instead we use the macro below and test it against specific values. */
# define ATTRIBUTE_NULL_PRINTF_5 ATTRIBUTE_NULL_PRINTF(5, 6)
#endif /* ATTRIBUTE_NULL_PRINTF */
+/* Attribute `sentinel' was valid as of gcc 3.5. */
+#ifndef ATTRIBUTE_SENTINEL
+# if (GCC_VERSION >= 3005)
+# define ATTRIBUTE_SENTINEL __attribute__ ((__sentinel__))
+# else
+# define ATTRIBUTE_SENTINEL
+# endif /* GNUC >= 3.5 */
+#endif /* ATTRIBUTE_SENTINEL */
+
/* We use __extension__ in some places to suppress -pedantic warnings
about GCC extensions. This feature didn't work properly before
gcc 2.8. */
diff --git a/gnu/dist/binutils/include/aout/aout64.h b/gnu/dist/binutils/include/aout/aout64.h
index 4843410d276..170af690674 100644
--- a/gnu/dist/binutils/include/aout/aout64.h
+++ b/gnu/dist/binutils/include/aout/aout64.h
@@ -1,6 +1,6 @@
/* `a.out' object-file definitions, including extensions to 64-bit fields
- Copyright 2001, 2003 Free Software Foundation, Inc.
+ Copyright 1999, 2000, 2001, 2003 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
diff --git a/gnu/dist/binutils/include/bfdlink.h b/gnu/dist/binutils/include/bfdlink.h
index cc2043e10ed..9d93154378b 100644
--- a/gnu/dist/binutils/include/bfdlink.h
+++ b/gnu/dist/binutils/include/bfdlink.h
@@ -1,6 +1,6 @@
/* bfdlink.h -- header file for BFD link routines
- Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2002, 2003,
- 2004 Free Software Foundation, Inc.
+ Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
+ 2003, 2004, 2005 Free Software Foundation, Inc.
Written by Steve Chamberlain and Ian Lance Taylor, Cygnus Support.
This file is part of BFD, the Binary File Descriptor library.
@@ -85,26 +85,6 @@ struct bfd_link_hash_entry
/* Type of this entry. */
enum bfd_link_hash_type type;
- /* Undefined and common symbols are kept in a linked list through
- this field. This field is not in the union because that would
- force us to remove entries from the list when we changed their
- type, which would force the list to be doubly linked, which would
- waste more memory. When an undefined or common symbol is
- created, it should be added to this list, the head of which is in
- the link hash table itself. As symbols are defined, they need
- not be removed from the list; anything which reads the list must
- doublecheck the symbol type.
-
- Weak symbols are not kept on this list.
-
- Defined and defweak symbols use this field as a reference marker.
- If the field is not NULL, or this structure is the tail of the
- undefined symbol list, the symbol has been referenced. If the
- symbol is undefined and becomes defined, this field will
- automatically be non-NULL since the symbol will have been on the
- undefined symbol list. */
- struct bfd_link_hash_entry *und_next;
-
/* A union of information depending upon the type. */
union
{
@@ -112,23 +92,47 @@ struct bfd_link_hash_entry
/* bfd_link_hash_undefined, bfd_link_hash_undefweak. */
struct
{
+ /* Undefined and common symbols are kept in a linked list through
+ this field. This field is present in all of the union element
+ so that we don't need to remove entries from the list when we
+ change their type. Removing entries would either require the
+ list to be doubly linked, which would waste more memory, or
+ require a traversal. When an undefined or common symbol is
+ created, it should be added to this list, the head of which is in
+ the link hash table itself. As symbols are defined, they need
+ not be removed from the list; anything which reads the list must
+ doublecheck the symbol type.
+
+ Weak symbols are not kept on this list.
+
+ Defined and defweak symbols use this field as a reference marker.
+ If the field is not NULL, or this structure is the tail of the
+ undefined symbol list, the symbol has been referenced. If the
+ symbol is undefined and becomes defined, this field will
+ automatically be non-NULL since the symbol will have been on the
+ undefined symbol list. */
+ struct bfd_link_hash_entry *next;
bfd *abfd; /* BFD symbol was found in. */
+ bfd *weak; /* BFD weak symbol was found in. */
} undef;
/* bfd_link_hash_defined, bfd_link_hash_defweak. */
struct
{
- bfd_vma value; /* Symbol value. */
+ struct bfd_link_hash_entry *next;
asection *section; /* Symbol section. */
+ bfd_vma value; /* Symbol value. */
} def;
/* bfd_link_hash_indirect, bfd_link_hash_warning. */
struct
{
+ struct bfd_link_hash_entry *next;
struct bfd_link_hash_entry *link; /* Real symbol. */
const char *warning; /* Warning (bfd_link_hash_warning only). */
} i;
/* bfd_link_hash_common. */
struct
{
+ struct bfd_link_hash_entry *next;
/* The linker needs to know three things about common
symbols: the size, the alignment, and the section in
which the symbol should be placed. We store the size
@@ -138,12 +142,12 @@ struct bfd_link_hash_entry
directly because we don't want to increase the size of
the union; this structure is a major space user in the
linker. */
- bfd_size_type size; /* Common symbol size. */
struct bfd_link_hash_common_entry
{
unsigned int alignment_power; /* Alignment. */
asection *section; /* Symbol section. */
} *p;
+ bfd_size_type size; /* Common symbol size. */
} c;
} u;
};
@@ -194,6 +198,10 @@ extern void bfd_link_hash_traverse
extern void bfd_link_add_undef
(struct bfd_link_hash_table *, struct bfd_link_hash_entry *);
+/* Remove symbols from the undefs list that don't belong there. */
+extern void bfd_link_repair_undef_list
+ (struct bfd_link_hash_table *table);
+
struct bfd_sym_chain
{
struct bfd_sym_chain *next;
@@ -259,6 +267,14 @@ struct bfd_link_info
/* TRUE if ok to have version with no definition. */
unsigned int allow_undefined_version: 1;
+ /* TRUE if a default symbol version should be created and used for
+ exported symbols. */
+ unsigned int create_default_symver: 1;
+
+ /* TRUE if a default symbol version should be created and used for
+ imported symbols. */
+ unsigned int default_imported_symver: 1;
+
/* TRUE if symbols should be retained in memory, FALSE if they
should be freed and reread. */
unsigned int keep_memory: 1;
@@ -302,6 +318,12 @@ struct bfd_link_info
flags. */
unsigned int noexecstack: 1;
+ /* TRUE if PT_GNU_RELRO segment should be created. */
+ unsigned int relro: 1;
+
+ /* TRUE if we should warn when adding a DT_TEXTREL to a shared object. */
+ unsigned int warn_shared_textrel: 1;
+
/* What to do with unresolved symbols in an object file.
When producing executables the default is GENERATE_ERROR.
When producing shared libraries the default is IGNORE. The
@@ -391,6 +413,9 @@ struct bfd_link_info
/* May be used to set DT_FLAGS_1 for ELF. */
bfd_vma flags_1;
+
+ /* Start and end of RELRO region. */
+ bfd_vma relro_start, relro_end;
};
/* This structures holds a set of callback functions. These are
@@ -469,16 +494,18 @@ struct bfd_link_callbacks
bfd_boolean (*undefined_symbol)
(struct bfd_link_info *, const char *name, bfd *abfd,
asection *section, bfd_vma address, bfd_boolean fatal);
- /* A function which is called when a reloc overflow occurs. NAME is
- the name of the symbol or section the reloc is against,
- RELOC_NAME is the name of the relocation, and ADDEND is any
- addend that is used. ABFD, SECTION and ADDRESS identify the
+ /* A function which is called when a reloc overflow occurs. ENTRY is
+ the link hash table entry for the symbol the reloc is against.
+ NAME is the name of the local symbol or section the reloc is
+ against, RELOC_NAME is the name of the relocation, and ADDEND is
+ any addend that is used. ABFD, SECTION and ADDRESS identify the
location at which the overflow occurs; if this is the result of a
bfd_section_reloc_link_order or bfd_symbol_reloc_link_order, then
ABFD will be NULL. */
bfd_boolean (*reloc_overflow)
- (struct bfd_link_info *, const char *name, const char *reloc_name,
- bfd_vma addend, bfd *abfd, asection *section, bfd_vma address);
+ (struct bfd_link_info *, struct bfd_link_hash_entry *entry,
+ const char *name, const char *reloc_name, bfd_vma addend,
+ bfd *abfd, asection *section, bfd_vma address);
/* A function which is called when a dangerous reloc is performed.
The canonical example is an a29k IHCONST reloc which does not
follow an IHIHALF reloc. MESSAGE is an appropriate message.
@@ -505,14 +532,6 @@ struct bfd_link_callbacks
bfd_boolean (*notice)
(struct bfd_link_info *, const char *name,
bfd *abfd, asection *section, bfd_vma address);
- /* A function which is called for reporting a linker error. ID is the
- error identifier. The remaining input is the same as einfo () in
- ld. */
- bfd_boolean (*error_handler)
- (int id, const char *fmt, ...);
-
-/* Identifiers of linker error messages used by error_handler. */
-#define LD_DEFINITION_IN_DISCARDED_SECTION 1
};
/* The linker builds link_order structures which tell the code how to
@@ -550,7 +569,7 @@ struct bfd_link_order
/* Section to include. If this is used, then
section->output_section must be the section the
link_order is attached to, section->output_offset must
- equal the link_order offset field, and section->_raw_size
+ equal the link_order offset field, and section->size
must equal the link_order size field. Maybe these
restrictions should be relaxed someday. */
asection *section;
diff --git a/gnu/dist/binutils/include/bin-bugs.h b/gnu/dist/binutils/include/bin-bugs.h
index 3c97715add4..63901b044f4 100644
--- a/gnu/dist/binutils/include/bin-bugs.h
+++ b/gnu/dist/binutils/include/bin-bugs.h
@@ -1,3 +1,3 @@
#ifndef REPORT_BUGS_TO
-#define REPORT_BUGS_TO "bug-binutils@gnu.org"
+#define REPORT_BUGS_TO "<URL:http://www.sourceware.org/bugzilla/>"
#endif
diff --git a/gnu/dist/binutils/include/coff/ChangeLog b/gnu/dist/binutils/include/coff/ChangeLog
index 33163834229..88cf310935f 100644
--- a/gnu/dist/binutils/include/coff/ChangeLog
+++ b/gnu/dist/binutils/include/coff/ChangeLog
@@ -1,3 +1,36 @@
+2005-02-21 Alan Modra <amodra@bigpond.net.au>
+
+ * xcoff.h (struct xcoff_loader_info): Warning fix.
+
+2005-01-10 Inderpreet Singh <inderpreetb@noida.hcltech.com>
+
+ * maxq.h (F_MAXQ10, F_MAXQ20): Define.
+
+2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
+ Vineet Sharma <vineets@noida.hcltech.com>
+
+ * maxq.h: New file: Defintions for the maxq port.
+
+2004-11-08 Aaron W. LaFramboise <aaron98wiridge9@aaronwl.com>
+
+ * pe.h (IMAGE_WEAK_EXTERN_SEARCH_NOLIBRARY): Define.
+ (IMAGE_WEAK_EXTERN_SEARCH_LIBRARY): Same.
+ (IMAGE_WEAK_EXTERN_SEARCH_ALIAS): Same.
+
+2004-08-13 Mark Kettenis <kettenis@gnu.org>
+
+ * symconst.h (langMax): Fix typo in comment.
+
+2004-04-23 Chris Demetriou <cgd@broadcom.com>
+
+ * mips.h (MIPS_R_RELHI, MIPS_R_RELLO, MIPS_R_SWITCH): Remove
+ (MIPS_R_PCREL16): Update comment.
+ * ecoff.h (struct ecoff_value_adjust): Remove structure.
+ (struct ecoff_debug_info): Remove 'adjust' member.
+
+2004-04-20 DJ Delorie <dj@redhat.com>
+
+ * internal.h (R_SECREL32): Add.
For older changes see ChangeLog-9103
diff --git a/gnu/dist/binutils/include/coff/arm.h b/gnu/dist/binutils/include/coff/arm.h
index 8b90228ca98..b05fa0fb1de 100644
--- a/gnu/dist/binutils/include/coff/arm.h
+++ b/gnu/dist/binutils/include/coff/arm.h
@@ -1,5 +1,5 @@
/* ARM COFF support for BFD.
- Copyright 1998, 1999, 2000, 2002 Free Software Foundation, Inc.
+ Copyright 1998, 1999, 2000, 2002, 2003 Free Software Foundation, Inc.
This file is part of BFD, the Binary File Descriptor library.
diff --git a/gnu/dist/binutils/include/coff/ecoff.h b/gnu/dist/binutils/include/coff/ecoff.h
index 3a7aa4fbbb5..5726a19d91f 100644
--- a/gnu/dist/binutils/include/coff/ecoff.h
+++ b/gnu/dist/binutils/include/coff/ecoff.h
@@ -2,7 +2,7 @@
This does not include symbol information, found in sym.h and
symconst.h.
- Copyright 2001, 2002, 2003 Free Software Foundation, Inc.
+ Copyright 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
@@ -322,34 +322,6 @@ struct ecoff_debug_info
this changes in the future. This is a pointer to an array, not a
single structure. */
FDR *fdr;
-
- /* When relaxing MIPS embedded PIC code, we may need to adjust
- symbol values when they are output. This is a linked list of
- structures indicating how values should be adjusted. There is no
- requirement that the entries be in any order, or that they not
- overlap. This field is normally NULL, in which case no
- adjustments need to be made. */
- struct ecoff_value_adjust *adjust;
-};
-
-/* This structure describes how to adjust symbol values when
- outputting MIPS embedded PIC code. These adjustments only apply to
- the internal symbols, as the external symbol values will come from
- the hash table and have already been adjusted. */
-
-struct ecoff_value_adjust
-{
- /* Next entry on adjustment list. */
- struct ecoff_value_adjust *next;
- /* Starting VMA of adjustment. This is the VMA in the ECOFF file,
- not the offset from the start of the section. Thus it should
- indicate a particular section. */
- bfd_vma start;
- /* Ending VMA of adjustment. */
- bfd_vma end;
- /* Adjustment. This should be added to the value of the symbol, or
- FDR. This is zero for the last entry in the array. */
- long adjust;
};
/* These structures are used by the ECOFF find_nearest_line function. */
diff --git a/gnu/dist/binutils/include/coff/ia64.h b/gnu/dist/binutils/include/coff/ia64.h
index f7ff0ee22f0..978255dd36a 100644
--- a/gnu/dist/binutils/include/coff/ia64.h
+++ b/gnu/dist/binutils/include/coff/ia64.h
@@ -1,6 +1,6 @@
/* coff information for HP/Intel IA-64.
- Copyright 2001 Free Software Foundation, Inc.
+ Copyright 2000 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
diff --git a/gnu/dist/binutils/include/coff/internal.h b/gnu/dist/binutils/include/coff/internal.h
index 2d41bf9a5f4..a400e8c9282 100644
--- a/gnu/dist/binutils/include/coff/internal.h
+++ b/gnu/dist/binutils/include/coff/internal.h
@@ -1,7 +1,8 @@
/* Internal format of COFF object file data structures, for GNU BFD.
This file is part of BFD, the Binary File Descriptor library.
- Copyright 2001 Free Software Foundation, Inc.
+ Copyright 1999, 2000, 2001, 2002, 2003, 2004
+ Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
@@ -607,6 +608,7 @@ struct internal_reloc
#define R_REL24 5
#define R_DIR32 6
#define R_IMAGEBASE 7
+#define R_SECREL32 11
#define R_RELBYTE 15
#define R_RELWORD 16
#define R_RELLONG 17
diff --git a/gnu/dist/binutils/include/coff/maxq.h b/gnu/dist/binutils/include/coff/maxq.h
new file mode 100644
index 00000000000..694a3fa63ad
--- /dev/null
+++ b/gnu/dist/binutils/include/coff/maxq.h
@@ -0,0 +1,56 @@
+/* COFF spec for MAXQ
+
+ Copyright 2004, 2005 Free Software Foundation, Inc.
+
+ This program is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published by the Free
+ Software Foundation; either version 2 of the License, or (at your option)
+ any later version.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ for more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program; if not, write to the Free Software Foundation, Inc., 59
+ Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+ Contributed by Vineet Sharma(vineets@noida.hcltech.com) Inderpreet
+ S.(inderpreetb@noida.hcltech.com) HCL Technologies Ltd. */
+
+#define L_LNNO_SIZE 2
+
+#include "coff/external.h"
+
+/* Bits for f_flags: F_RELFLG relocation info stripped from file F_EXEC file
+ is executable (no unresolved external references) F_LNNO line numbers
+ stripped from file F_LSYMS local symbols stripped from file. */
+
+#define F_RELFLG (0x0001)
+#define F_EXEC (0x0002)
+#define F_LNNO (0x0004)
+#define F_LSYMS (0x0008)
+
+/* Variant Specific Flags for MAXQ10 and MAXQ20. */
+#define F_MAXQ10 (0x0030)
+#define F_MAXQ20 (0x0040)
+
+#define F_MACHMASK (0x00F0)
+
+/* Magic numbers for maxq. */
+#define MAXQ20MAGIC 0xa0
+#define MAXQ20BADMAG(x) (((x).f_magic != MAXQ20MAGIC))
+#define BADMAG(x) MAXQ20BADMAG (x)
+
+/* Relocation information declaration and related definitions. */
+struct external_reloc
+{
+ char r_vaddr[4]; /* (Virtual) address of reference. */
+ char r_symndx[4]; /* Index into symbol table. */
+ char r_type[2]; /* Relocation type. */
+ char r_offset[2]; /* Addend. */
+};
+
+#define RELOC struct external_reloc
+#define RELSZ (10 + 2) /* sizeof (RELOC) */
diff --git a/gnu/dist/binutils/include/coff/mcore.h b/gnu/dist/binutils/include/coff/mcore.h
index 980cf133da9..02579c42a60 100644
--- a/gnu/dist/binutils/include/coff/mcore.h
+++ b/gnu/dist/binutils/include/coff/mcore.h
@@ -1,5 +1,5 @@
/* Motorola MCore support for BFD.
- Copyright 1999 Free Software Foundation, Inc.
+ Copyright 1999, 2000 Free Software Foundation, Inc.
This file is part of BFD, the Binary File Descriptor library.
diff --git a/gnu/dist/binutils/include/coff/mips.h b/gnu/dist/binutils/include/coff/mips.h
index b9503bd5555..e3d2c1ccc05 100644
--- a/gnu/dist/binutils/include/coff/mips.h
+++ b/gnu/dist/binutils/include/coff/mips.h
@@ -1,7 +1,7 @@
/* ECOFF support on MIPS machines.
coff/ecoff.h must be included before this file.
- Copyright 2001 Free Software Foundation, Inc.
+ Copyright 1999, 2004 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
@@ -105,34 +105,10 @@ struct external_reloc
#define MIPS_R_GPREL 6
#define MIPS_R_LITERAL 7
-/* These reloc types are a Cygnus extension used when generating
- position independent code for embedded systems. The numbers are
- taken from Irix 4, but at least for internal relocs Irix 5 does not
- give them the same meaning. For an internal reloc the symbol index
- of RELHI and RELLO is modified as described below for
- MIPS_R_SWITCH. */
+/* FIXME: This relocation is used (internally only) to represent branches
+ when assembling. It should never appear in output files, and
+ be removed. (It used to be used for embedded-PIC support.) */
#define MIPS_R_PCREL16 12
-#define MIPS_R_RELHI 13
-#define MIPS_R_RELLO 14
-
-/* This reloc type is a Cygnus extension used when generating position
- independent code for embedded systems. It is used for an entry in
- a switch table, which looks like this:
- .word $L3-$LS12
- The object file will contain the correct difference, and does not
- require adjustment. However, when the linker is relaxing PC
- relative calls, it is possible for $L3 to move farther away. This
- reloc always appears in the .text section, and is always against
- the .text section. However, the symbol index is not
- RELOC_SECTION_TEXT. It is, instead, the distance between this
- switch table entry and $LS12. Thus, the original value of $L12 is
- vaddr - symndx
- and the original value of $L3 is
- vaddr - symndx + addend
- where addend is the value in the object file. Knowing this, the
- linker can know whether the addend in the object file must be
- adjusted. */
-#define MIPS_R_SWITCH 22
/********************** STABS **********************/
diff --git a/gnu/dist/binutils/include/coff/mipspe.h b/gnu/dist/binutils/include/coff/mipspe.h
index 9b4ffab70a0..cd2480b01d2 100644
--- a/gnu/dist/binutils/include/coff/mipspe.h
+++ b/gnu/dist/binutils/include/coff/mipspe.h
@@ -1,6 +1,6 @@
/* coff information for Windows CE with MIPS VR4111
- Copyright 2001 Free Software Foundation, Inc.
+ Copyright 2000 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
diff --git a/gnu/dist/binutils/include/coff/pe.h b/gnu/dist/binutils/include/coff/pe.h
index 363d307379b..4d3621905b7 100644
--- a/gnu/dist/binutils/include/coff/pe.h
+++ b/gnu/dist/binutils/include/coff/pe.h
@@ -1,6 +1,6 @@
/* pe.h - PE COFF header information
- Copyright 2000, 2001, 2003 Free Software Foundation, Inc.
+ Copyright 1999, 2000, 2001, 2003, 2004 Free Software Foundation, Inc.
This file is part of BFD, the Binary File Descriptor library.
@@ -310,4 +310,9 @@ typedef struct
#define IMPORT_NAME_NOPREFIX 2
#define IMPORT_NAME_UNDECORATE 3
+/* Weak external characteristics. */
+#define IMAGE_WEAK_EXTERN_SEARCH_NOLIBRARY 1
+#define IMAGE_WEAK_EXTERN_SEARCH_LIBRARY 2
+#define IMAGE_WEAK_EXTERN_SEARCH_ALIAS 3
+
#endif /* _PE_H */
diff --git a/gnu/dist/binutils/include/coff/rs6000.h b/gnu/dist/binutils/include/coff/rs6000.h
index 0c34861142a..5323662823e 100644
--- a/gnu/dist/binutils/include/coff/rs6000.h
+++ b/gnu/dist/binutils/include/coff/rs6000.h
@@ -1,5 +1,5 @@
/* IBM RS/6000 "XCOFF" file definitions for BFD.
- Copyright (C) 1990, 1991 Free Software Foundation, Inc.
+ Copyright (C) 1990, 1991, 2001 Free Software Foundation, Inc.
FIXME: Can someone provide a transliteration of this name into ASCII?
Using the following chars caused a compiler warning on HIUX (so I replaced
them with octal escapes), and isn't useful without an understanding of what
diff --git a/gnu/dist/binutils/include/coff/rs6k64.h b/gnu/dist/binutils/include/coff/rs6k64.h
index 47d08021318..4eab91daa6a 100644
--- a/gnu/dist/binutils/include/coff/rs6k64.h
+++ b/gnu/dist/binutils/include/coff/rs6k64.h
@@ -1,5 +1,5 @@
/* IBM RS/6000 "XCOFF64" file definitions for BFD.
- Copyright (C) 2000, 2002 Free Software Foundation, Inc.
+ Copyright (C) 2000, 2001, 2002 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
diff --git a/gnu/dist/binutils/include/coff/sh.h b/gnu/dist/binutils/include/coff/sh.h
index d20834ca667..d224379b2a9 100644
--- a/gnu/dist/binutils/include/coff/sh.h
+++ b/gnu/dist/binutils/include/coff/sh.h
@@ -1,6 +1,6 @@
/* coff information for Renesas SH
- Copyright 2001, 2003 Free Software Foundation, Inc.
+ Copyright 2000, 2003 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
diff --git a/gnu/dist/binutils/include/coff/symconst.h b/gnu/dist/binutils/include/coff/symconst.h
index f40eef2a311..3e45705f408 100644
--- a/gnu/dist/binutils/include/coff/symconst.h
+++ b/gnu/dist/binutils/include/coff/symconst.h
@@ -48,7 +48,7 @@
#define langStdc 9 /* FIXME: Collides with SGI langCplusplus */
#define langCplusplus 9 /* FIXME: Collides with langStdc */
#define langCplusplusV2 10 /* SGI addition */
-#define langMax 11 /* maximun allowed 32 -- 5 bits */
+#define langMax 11 /* maximum allowed 32 -- 5 bits */
/* The following are value definitions for the fields in the SYMR */
diff --git a/gnu/dist/binutils/include/coff/ti.h b/gnu/dist/binutils/include/coff/ti.h
index a15fe717ab6..cf5ffea7a12 100644
--- a/gnu/dist/binutils/include/coff/ti.h
+++ b/gnu/dist/binutils/include/coff/ti.h
@@ -2,7 +2,7 @@
customized in a target-specific file, and then this file included (see
tic54x.h for an example).
- Copyright 2001, 2003 Free Software Foundation, Inc.
+ Copyright 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
diff --git a/gnu/dist/binutils/include/coff/tic54x.h b/gnu/dist/binutils/include/coff/tic54x.h
index a7b7003a9f2..e8bac07231c 100644
--- a/gnu/dist/binutils/include/coff/tic54x.h
+++ b/gnu/dist/binutils/include/coff/tic54x.h
@@ -1,7 +1,7 @@
/* TI COFF information for Texas Instruments TMS320C54X.
This file customizes the settings in coff/ti.h.
- Copyright 2001 Free Software Foundation, Inc.
+ Copyright 2000, 2001 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
diff --git a/gnu/dist/binutils/include/coff/xcoff.h b/gnu/dist/binutils/include/coff/xcoff.h
index 64a9ee164ce..a70449eb7f3 100644
--- a/gnu/dist/binutils/include/coff/xcoff.h
+++ b/gnu/dist/binutils/include/coff/xcoff.h
@@ -1,6 +1,6 @@
/* Internal format of XCOFF object file data structures for BFD.
- Copyright 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
+ Copyright 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005
Free Software Foundation, Inc.
Written by Ian Lance Taylor <ian@cygnus.com>, Cygnus Support.
@@ -409,7 +409,7 @@ struct xcoff_loader_info
size_t string_size;
/* String table. */
- bfd_byte *strings;
+ char *strings;
/* Allocated size of string table. */
size_t string_alc;
diff --git a/gnu/dist/binutils/include/demangle.h b/gnu/dist/binutils/include/demangle.h
index 6e995e4817d..b3b8c58c517 100644
--- a/gnu/dist/binutils/include/demangle.h
+++ b/gnu/dist/binutils/include/demangle.h
@@ -458,7 +458,7 @@ cplus_demangle_fill_name PARAMS ((struct demangle_component *fill,
extern int
cplus_demangle_fill_builtin_type PARAMS ((struct demangle_component *fill,
- const char *typename));
+ const char *type_name));
/* Fill in a DEMANGLE_COMPONENT_OPERATOR, using the name of the
operator and the number of arguments which it takes (the latter is
diff --git a/gnu/dist/binutils/include/dis-asm.h b/gnu/dist/binutils/include/dis-asm.h
index 3670c518986..05d050767be 100644
--- a/gnu/dist/binutils/include/dis-asm.h
+++ b/gnu/dist/binutils/include/dis-asm.h
@@ -1,6 +1,7 @@
/* Interface between the opcode library and its callers.
- Copyright 2001, 2002, 2003 Free Software Foundation, Inc.
+ Copyright 1999, 2000, 2001, 2002, 2003, 2004, 2005
+ Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
@@ -159,6 +160,18 @@ typedef struct disassemble_info {
Normally one, but some DSPs have byte sizes of 16 or 32 bits. */
unsigned int octets_per_byte;
+ /* The number of zeroes we want to see at the end of a section before we
+ start skipping them. */
+ unsigned int skip_zeroes;
+
+ /* The number of zeroes to skip at the end of a section. If the number
+ of zeroes at the end is between SKIP_ZEROES_AT_END and SKIP_ZEROES,
+ they will be disassembled. If there are fewer than
+ SKIP_ZEROES_AT_END, they will be skipped. This is a heuristic
+ attempt to avoid disassembling zeroes inserted by section
+ alignment. */
+ unsigned int skip_zeroes_at_end;
+
/* Results from instruction decoders. Not all decoders yet support
this information. This info is set each time an instruction is
decoded, and is only valid for the last such instruction.
@@ -218,12 +231,15 @@ extern int print_insn_i960 (bfd_vma, disassemble_info *);
extern int print_insn_ip2k (bfd_vma, disassemble_info *);
extern int print_insn_m32r (bfd_vma, disassemble_info *);
extern int print_insn_m88k (bfd_vma, disassemble_info *);
+extern int print_insn_maxq_little (bfd_vma, disassemble_info *);
+extern int print_insn_maxq_big (bfd_vma, disassemble_info *);
extern int print_insn_mcore (bfd_vma, disassemble_info *);
extern int print_insn_mmix (bfd_vma, disassemble_info *);
extern int print_insn_mn10200 (bfd_vma, disassemble_info *);
extern int print_insn_mn10300 (bfd_vma, disassemble_info *);
extern int print_insn_msp430 (bfd_vma, disassemble_info *);
extern int print_insn_ns32k (bfd_vma, disassemble_info *);
+extern int print_insn_crx (bfd_vma, disassemble_info *);
extern int print_insn_openrisc (bfd_vma, disassemble_info *);
extern int print_insn_big_or32 (bfd_vma, disassemble_info *);
extern int print_insn_little_or32 (bfd_vma, disassemble_info *);
diff --git a/gnu/dist/binutils/include/dyn-string.h b/gnu/dist/binutils/include/dyn-string.h
index 2a771c7a5d1..85f88b12cf6 100644
--- a/gnu/dist/binutils/include/dyn-string.h
+++ b/gnu/dist/binutils/include/dyn-string.h
@@ -1,5 +1,5 @@
/* An abstract string datatype.
- Copyright (C) 1998, 1999, 2000, 2002 Free Software Foundation, Inc.
+ Copyright (C) 1998, 1999, 2000, 2002, 2004 Free Software Foundation, Inc.
Contributed by Mark Mitchell (mark@markmitchell.com).
This file is part of GCC.
@@ -40,35 +40,6 @@ typedef struct dyn_string
(strcmp ((DS1)->s, (DS2)->s))
-/* dyn_string functions are used in the demangling implementation
- included in the G++ runtime library. To prevent collisions with
- names in user programs, the functions that are used in the
- demangler are given implementation-reserved names. */
-
-#if defined(IN_LIBGCC2) || defined(IN_GLIBCPP_V3)
-
-#define dyn_string_init __cxa_dyn_string_init
-#define dyn_string_new __cxa_dyn_string_new
-#define dyn_string_delete __cxa_dyn_string_delete
-#define dyn_string_release __cxa_dyn_string_release
-#define dyn_string_resize __cxa_dyn_string_resize
-#define dyn_string_clear __cxa_dyn_string_clear
-#define dyn_string_copy __cxa_dyn_string_copy
-#define dyn_string_copy_cstr __cxa_dyn_string_copy_cstr
-#define dyn_string_prepend __cxa_dyn_string_prepend
-#define dyn_string_prepend_cstr __cxa_dyn_string_prepend_cstr
-#define dyn_string_insert __cxa_dyn_string_insert
-#define dyn_string_insert_cstr __cxa_dyn_string_insert_cstr
-#define dyn_string_insert_char __cxa_dyn_string_insert_char
-#define dyn_string_append __cxa_dyn_string_append
-#define dyn_string_append_cstr __cxa_dyn_string_append_cstr
-#define dyn_string_append_char __cxa_dyn_string_append_char
-#define dyn_string_substring __cxa_dyn_string_substring
-#define dyn_string_eq __cxa_dyn_string_eq
-
-#endif /* IN_LIBGCC2 || IN_GLIBCPP_V3 */
-
-
extern int dyn_string_init PARAMS ((struct dyn_string *, int));
extern dyn_string_t dyn_string_new PARAMS ((int));
extern void dyn_string_delete PARAMS ((dyn_string_t));
diff --git a/gnu/dist/binutils/include/elf/ChangeLog b/gnu/dist/binutils/include/elf/ChangeLog
index ea008d62423..46df13d03a0 100644
--- a/gnu/dist/binutils/include/elf/ChangeLog
+++ b/gnu/dist/binutils/include/elf/ChangeLog
@@ -1,3 +1,153 @@
+2005-03-17 Paul Brook <paul@codesourcery.com>
+ Dan Jacobowitz <dan@codesourcery.com>
+ Mark Mitchell <mark@codesourcery.com>
+
+ * arm.h (PT_ARM_EXIDX): Define.
+
+2005-03-02 Daniel Jacobowitz <dan@codesourcery.com>
+ Joseph Myers <joseph@codesourcery.com>
+
+ * mips.h: Define MIPS TLS relocations.
+
+2005-02-15 Nigel Stephens <nigel@mips.com>
+ Maciej W. Rozycki <macro@mips.com>
+
+ * mips.h (R_MIPS16_GOT16): New reloc code.
+ (R_MIPS16_CALL16): Likewise.
+ (R_MIPS16_HI16): Likewise.
+ (R_MIPS16_LO16): Likewise.
+ (R_MIPS16_min): New fake reloc code.
+ (R_MIPS16_max): Likewise.
+
+2005-02-11 Maciej W. Rozycki <macro@mips.com>
+
+ * mips.h (R_MIPS_max): Use FAKE_RELOC to define.
+
+2005-01-25 Alexandre Oliva <aoliva@redhat.com>
+
+ 2004-12-10 Alexandre Oliva <aoliva@redhat.com>
+ * frv.h: Add R_FRV_TLSMOFF.
+ 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
+ * frv.h: Add TLS relocations.
+
+2005-01-17 Nick Clifton <nickc@redhat.com>
+
+ * sh.h (EF_SH2A_SH4_NOFPU, EF_SH2A_SH3_NOFPU, EF_SH2A_SH4,
+ EF_SH2A_SH3E): New flags.
+ (EF_SH_BFD_TABLE): Add these new flags to the table.
+
+2005-01-12 Alan Modra <amodra@bigpond.net.au>
+
+ * ppc.h (R_PPC_RELAX32_PLT, R_PPC_RELAX32PC_PLT): Define.
+ (R_PPC_RELAX32, R_PPC_RELAX32PC): Adjust value.
+
+2004-12-22 Klaus Rudolph <lts-rudolph@gmx.de>
+
+ * include/elf/avr.h (R_AVR_LDI, R_AVR_6, R_AVR_6_ADIW): New
+ relocs.
+
+2004-12-16 Richard Sandiford <rsandifo@redhat.com>
+
+ * v850.h (R_V850_LO16_SPLIT_OFFSET): New reloc.
+
+2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
+
+ * mips.h (E_MIPS_MACH_9000): Define.
+
+2004-11-04 Hans-Peter Nilsson <hp@axis.com>
+
+ * cris.h (EF_CRIS_VARIANT_MASK, EF_CRIS_VARIANT_ANY_V0_V10)
+ (EF_CRIS_VARIANT_V32, EF_CRIS_VARIANT_COMMON_V10_V32): New
+ macros.
+
+2004-10-06 Eric Christopher <echristo@redhat.com>
+
+ * dwarf2.h: Sync with gcc dwarf2.h. Fix typo.
+
+2004-10-01 Paul Brook <paul@codesourcery.com>
+
+ * arm.h (SHT_ARM_EXIDX): Define.
+ (ELF_STRING_ARM_unwind, ELF_STRING_ARM_unwind,
+ ELF_STRING_ARM_unwind_once, ELF_STRING_ARM_unwind_info_once):
+ Define.
+
+2004-08-25 Dmitry Diky <diwil@spec.ru>
+
+ * msp430.h: Add new relocs.
+
+2004-08-12 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386.h (R_386_USED_BY_INTEL_200): New.
+
+2004-07-29 Alexandre Oliva <aoliva@redhat.com>
+
+ Introduce SH2a support.
+ 2004-02-18 Corinna Vinschen <vinschen@redhat.com>
+ * sh.h (EF_SH2A_NOFPU): New.
+ 2003-12-01 Michael Snyder <msnyder@redhat.com>
+ * sh.h (EF_SH2A): New.
+
+2004-07-27 Tomer Levi <Tomer.Levi@nsc.com>
+
+ * crx.h: Add BFD_RELOC_CRX_SWITCH8, BFD_RELOC_CRX_SWITCH16,
+ BFD_RELOC_CRX_SWITCH32.
+
+2004-07-06 Tomer Levi <Tomer.Levi@nsc.com>
+
+ * common.h (EM_CRX): Define.
+ * crx.h: New file.
+
+2004-06-25 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
+
+ * m32r.h: Add defintions of R_M32R_GOTOFF_HI_ULO,
+ R_M32R_GOTOFF_HI_SLO and R_M32R_GOTOFF_LO.
+
+2004-06-19 Alan Modra <amodra@bigpond.net.au>
+
+ * common.h (ELF64_R_INFO): Warning fix.
+
+2004-06-14 Chris Demetriou <cgd@broadcom.com>
+
+ * mips.h (R_MIPS_PC32): Add back (undoing removal on 2004-04-24),
+ with an updated comment.
+
+2004-05-28 Andrew Stubbs <andrew.stubbs@superh.com>
+
+ * sh.h (EF_SH_HAS_DSP): Remove.
+ (EF_SH_HAS_FP): Remove.
+ (EF_SH_MERGE_MACH): Remove.
+ (EF_SH4_NOFPU): Convert to decimal.
+ (EF_SH4A_NOFPU): Likewise.
+ (EF_SH4_NOMMU_NOFPU): Likewise.
+ (EF_SH3_NOMMU): Add new macro.
+ (EF_SH_BFD_TABLE): Likewise.
+ (sh_find_elf_flags): Add prototype.
+ (sh_elf_get_flags_from_mach): Likewise.
+
+2004-04-24 Chris Demetriou <cgd@broadcom.com>
+
+ * mips.h (R_MIPS_PC32, R_MIPS_PC64, R_MIPS_GNU_REL_LO16)
+ (R_MIPS_GNU_REL_HI16): Remove.
+ (R_MIPS_GNU_REL16_S2): Update comment.
+
+2004-30-30 Galit Heller <Galit.Heller@nsc.com>
+ Tomer Levi <Tomer.Levi@nsc.com>
+
+ * common.h (EM_CR): Define.
+ * cr16c.h: New file.
+
+2004-03-23 Paul Brook <paul@codesourcery.com>
+
+ * arm.h (EF_ERM_BE8, EF_ARM_LE8, EF_ARM_EABI_VER3): Add.
+
+2003-03-03 Andrew Stubbs <andrew.stubbs@superh.com>
+
+ * sh.h: Add EF_SH4_NOMMU_NOFPU.
+
+2004-03-01 Richard Sandiford <rsandifo@redhat.com>
+
+ * frv.h (EF_FRV_CPU_FR405, EF_FRV_CPU_FR450): Define.
+
2004-01-28 Roland McGrath <roland@redhat.com>
* common.h (AT_SECURE): New macro.
diff --git a/gnu/dist/binutils/include/elf/alpha.h b/gnu/dist/binutils/include/elf/alpha.h
index 0313b5be6bb..4cee1495f61 100644
--- a/gnu/dist/binutils/include/elf/alpha.h
+++ b/gnu/dist/binutils/include/elf/alpha.h
@@ -1,5 +1,5 @@
/* ALPHA ELF support for BFD.
- Copyright 1996, 1998, 2000 Free Software Foundation, Inc.
+ Copyright 1996, 1998, 2000, 2001, 2002 Free Software Foundation, Inc.
By Eric Youngdale, <eric@aib.com>. No processor supplement available
for this platform.
diff --git a/gnu/dist/binutils/include/elf/arm.h b/gnu/dist/binutils/include/elf/arm.h
index 181a9f0c5c9..de3ed066441 100644
--- a/gnu/dist/binutils/include/elf/arm.h
+++ b/gnu/dist/binutils/include/elf/arm.h
@@ -1,5 +1,6 @@
/* ARM ELF support for BFD.
- Copyright 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
+ Copyright 1998, 1999, 2000, 2001, 2002, 2003, 2004
+ Free Software Foundation, Inc.
This file is part of BFD, the Binary File Descriptor library.
@@ -36,16 +37,25 @@
#define EF_ARM_VFP_FLOAT 0x400
#define EF_ARM_MAVERICK_FLOAT 0x800
+/* Frame unwind information */
+#define PT_ARM_EXIDX (PT_LOPROC + 1)
+
/* Other constants defined in the ARM ELF spec. version B-01. */
#define EF_ARM_SYMSARESORTED 0x04 /* NB conflicts with EF_INTERWORK */
#define EF_ARM_DYNSYMSUSESEGIDX 0x08 /* NB conflicts with EF_APCS26 */
#define EF_ARM_MAPSYMSFIRST 0x10 /* NB conflicts with EF_APCS_FLOAT */
#define EF_ARM_EABIMASK 0xFF000000
+/* Constants defined in AAELF. */
+#define EF_ARM_BE8 0x00800000
+#define EF_ARM_LE8 0x00400000
+
#define EF_ARM_EABI_VERSION(flags) ((flags) & EF_ARM_EABIMASK)
#define EF_ARM_EABI_UNKNOWN 0x00000000
#define EF_ARM_EABI_VER1 0x01000000
#define EF_ARM_EABI_VER2 0x02000000
+#define EF_ARM_EABI_VER3 0x03000000
+#define EF_ARM_EABI_VER4 0x04000000
/* Local aliases for some flags to match names used by COFF port. */
#define F_INTERWORK EF_ARM_INTERWORK
@@ -59,6 +69,9 @@
#define STT_ARM_TFUNC STT_LOPROC /* A Thumb function. */
#define STT_ARM_16BIT STT_HIPROC /* A Thumb label. */
+/* Additional section types. */
+#define SHT_ARM_EXIDX 0x70000001 /* Section holds ARM unwind info. */
+
/* ARM-specific values for sh_flags. */
#define SHF_ENTRYSECT 0x10000000 /* Section contains an entry point. */
#define SHF_COMDEF 0x80000000 /* Section may be multiply defined in the input to a link step. */
@@ -114,16 +127,28 @@ START_RELOC_NUMBERS (elf_arm_reloc_type)
FAKE_RELOC (FIRST_INVALID_RELOC, 28)
FAKE_RELOC (LAST_INVALID_RELOC, 249)
#else /* not OLD_ARM_ABI */
- FAKE_RELOC (FIRST_INVALID_RELOC1, 28)
+ RELOC_NUMBER (R_ARM_CALL, 28)
+ RELOC_NUMBER (R_ARM_JUMP24, 29)
+ FAKE_RELOC (FIRST_INVALID_RELOC1, 30)
FAKE_RELOC (LAST_INVALID_RELOC1, 31)
RELOC_NUMBER (R_ARM_ALU_PCREL7_0, 32)
RELOC_NUMBER (R_ARM_ALU_PCREL15_8, 33)
RELOC_NUMBER (R_ARM_ALU_PCREL23_15, 34)
- RELOC_NUMBER (R_ARM_LDR_SBREL11_0, 35)
- RELOC_NUMBER (R_ARM_ALU_SBREL19_12, 36)
- RELOC_NUMBER (R_ARM_ALU_SBREL27_20, 37)
- FAKE_RELOC (FIRST_INVALID_RELOC2, 38)
- FAKE_RELOC (LAST_INVALID_RELOC2, 99)
+ RELOC_NUMBER (R_ARM_LDR_SBREL_11_0, 35)
+ RELOC_NUMBER (R_ARM_ALU_SBREL_19_12, 36)
+ RELOC_NUMBER (R_ARM_ALU_SBREL_27_20, 37)
+ RELOC_NUMBER (R_ARM_TARGET1, 38)
+ RELOC_NUMBER (R_ARM_ROSEGREL32, 39)
+ RELOC_NUMBER (R_ARM_V4BX, 40)
+ RELOC_NUMBER (R_ARM_TARGET2, 41)
+ RELOC_NUMBER (R_ARM_PREL31, 42)
+ FAKE_RELOC (FIRST_INVALID_RELOC2, 43)
+ FAKE_RELOC (LAST_INVALID_RELOC2, 94)
+ RELOC_NUMBER (R_ARM_GOT_ABS, 95)
+ RELOC_NUMBER (R_ARM_GOT_PREL, 96)
+ RELOC_NUMBER (R_ARM_GOT_BREL12, 97)
+ RELOC_NUMBER (R_ARM_GOTOFF12, 98)
+ RELOC_NUMBER (R_ARM_GOTRELAX, 99)
RELOC_NUMBER (R_ARM_GNU_VTENTRY, 100)
RELOC_NUMBER (R_ARM_GNU_VTINHERIT, 101)
RELOC_NUMBER (R_ARM_THM_PC11, 102) /* Cygnus extension to abi: Thumb unconditional branch. */
@@ -142,5 +167,11 @@ END_RELOC_NUMBERS (R_ARM_max)
/* The name of the note section used to identify arm variants. */
#define ARM_NOTE_SECTION ".note.gnu.arm.ident"
-
+
+/* Special section names. */
+#define ELF_STRING_ARM_unwind ".ARM.exidx"
+#define ELF_STRING_ARM_unwind_info ".ARM.extab"
+#define ELF_STRING_ARM_unwind_once ".gnu.linkonce.armexidx."
+#define ELF_STRING_ARM_unwind_info_once ".gnu.linkonce.armextab."
+
#endif /* _ELF_ARM_H */
diff --git a/gnu/dist/binutils/include/elf/avr.h b/gnu/dist/binutils/include/elf/avr.h
index 59cf0734715..86905cf0999 100644
--- a/gnu/dist/binutils/include/elf/avr.h
+++ b/gnu/dist/binutils/include/elf/avr.h
@@ -1,22 +1,22 @@
/* AVR ELF support for BFD.
- Copyright 1999, 2000 Free Software Foundation, Inc.
+ Copyright 1999, 2000, 2004 Free Software Foundation, Inc.
Contributed by Denis Chertykov <denisc@overta.ru>
-This file is part of BFD, the Binary File Descriptor library.
+ This file is part of BFD, the Binary File Descriptor library.
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software Foundation, Inc.,
+ 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#ifndef _ELF_AVR_H
#define _ELF_AVR_H
@@ -53,6 +53,9 @@ START_RELOC_NUMBERS (elf_avr_reloc_type)
RELOC_NUMBER (R_AVR_HI8_LDI_PM_NEG, 16)
RELOC_NUMBER (R_AVR_HH8_LDI_PM_NEG, 17)
RELOC_NUMBER (R_AVR_CALL, 18)
+ RELOC_NUMBER (R_AVR_LDI, 19)
+ RELOC_NUMBER (R_AVR_6, 20)
+ RELOC_NUMBER (R_AVR_6_ADIW, 21)
END_RELOC_NUMBERS (R_AVR_max)
#endif /* _ELF_AVR_H */
diff --git a/gnu/dist/binutils/include/elf/common.h b/gnu/dist/binutils/include/elf/common.h
index bf233f61dfd..db92ff6a8f8 100644
--- a/gnu/dist/binutils/include/elf/common.h
+++ b/gnu/dist/binutils/include/elf/common.h
@@ -1,6 +1,6 @@
/* ELF support for BFD.
Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
- 2001, 2002, 2003
+ 2001, 2002, 2003, 2004
Free Software Foundation, Inc.
Written by Fred Fish @ Cygnus Support, from information published
@@ -180,7 +180,9 @@
#define EM_ARC_A5 93 /* ARC Cores Tangent-A5 */
#define EM_XTENSA 94 /* Tensilica Xtensa Architecture */
#define EM_IP2K 101 /* Ubicom IP2022 micro controller */
+#define EM_CR 103 /* National Semiconductor CompactRISC */
#define EM_MSP430 105 /* TI msp430 micro controller */
+#define EM_CRX 114 /* National Semiconductor CRX */
/* If it is necessary to assign new unofficial EM_* values, please pick large
random numbers (0x8523, 0xa7f2, etc.) to minimize the chances of collision
@@ -287,8 +289,10 @@
#define PT_LOPROC 0x70000000 /* Processor-specific */
#define PT_HIPROC 0x7FFFFFFF /* Processor-specific */
-#define PT_GNU_EH_FRAME (PT_LOOS + 0x474e550)
-#define PT_GNU_STACK (PT_LOOS + 0x474e551)
+#define PT_GNU_EH_FRAME (PT_LOOS + 0x474e550) /* Frame unwind information */
+#define PT_SUNW_EH_FRAME PT_GNU_EH_FRAME /* Solaris uses the same value */
+#define PT_GNU_STACK (PT_LOOS + 0x474e551) /* Stack flags */
+#define PT_GNU_RELRO (PT_LOOS + 0x474e552) /* Read-only after relocation */
/* Program segment permissions, in program header p_flags field. */
@@ -493,7 +497,7 @@
#define ELF64_R_SYM(i) ((i) >> 32)
#define ELF64_R_TYPE(i) ((i) & 0xffffffff)
-#define ELF64_R_INFO(s,t) (((bfd_vma) (s) << 32) + (bfd_vma) (t))
+#define ELF64_R_INFO(s,t) (((bfd_vma) (s) << 31 << 1) + (bfd_vma) (t))
/* Dynamic section tags. */
diff --git a/gnu/dist/binutils/include/elf/cr16c.h b/gnu/dist/binutils/include/elf/cr16c.h
new file mode 100644
index 00000000000..1a91afe0fea
--- /dev/null
+++ b/gnu/dist/binutils/include/elf/cr16c.h
@@ -0,0 +1,258 @@
+/* CR16C ELF support for BFD.
+ Copyright 2004 Free Software Foundation, Inc.
+
+ This file is part of BFD, the Binary File Descriptor library.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software Foundation,
+ Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+
+#ifndef _ELF_CR16C_H
+#define _ELF_CR16C_H
+
+#include "bfd.h"
+#include "elf/reloc-macros.h"
+
+/* Creating indices for reloc_map_index array. */
+START_RELOC_NUMBERS (elf_cr16c_reloc_type)
+ RELOC_NUMBER (RINDEX_16C_NUM08, 0)
+ RELOC_NUMBER (RINDEX_16C_NUM08_C, 1)
+ RELOC_NUMBER (RINDEX_16C_NUM16, 2)
+ RELOC_NUMBER (RINDEX_16C_NUM16_C, 3)
+ RELOC_NUMBER (RINDEX_16C_NUM32, 4)
+ RELOC_NUMBER (RINDEX_16C_NUM32_C, 5)
+ RELOC_NUMBER (RINDEX_16C_DISP04, 6)
+ RELOC_NUMBER (RINDEX_16C_DISP04_C, 7)
+ RELOC_NUMBER (RINDEX_16C_DISP08, 8)
+ RELOC_NUMBER (RINDEX_16C_DISP08_C, 9)
+ RELOC_NUMBER (RINDEX_16C_DISP16, 10)
+ RELOC_NUMBER (RINDEX_16C_DISP16_C, 11)
+ RELOC_NUMBER (RINDEX_16C_DISP24, 12)
+ RELOC_NUMBER (RINDEX_16C_DISP24_C, 13)
+ RELOC_NUMBER (RINDEX_16C_DISP24a, 14)
+ RELOC_NUMBER (RINDEX_16C_DISP24a_C, 15)
+ RELOC_NUMBER (RINDEX_16C_REG04, 16)
+ RELOC_NUMBER (RINDEX_16C_REG04_C, 17)
+ RELOC_NUMBER (RINDEX_16C_REG04a, 18)
+ RELOC_NUMBER (RINDEX_16C_REG04a_C, 19)
+ RELOC_NUMBER (RINDEX_16C_REG14, 20)
+ RELOC_NUMBER (RINDEX_16C_REG14_C, 21)
+ RELOC_NUMBER (RINDEX_16C_REG16, 22)
+ RELOC_NUMBER (RINDEX_16C_REG16_C, 23)
+ RELOC_NUMBER (RINDEX_16C_REG20, 24)
+ RELOC_NUMBER (RINDEX_16C_REG20_C, 25)
+ RELOC_NUMBER (RINDEX_16C_ABS20, 26)
+ RELOC_NUMBER (RINDEX_16C_ABS20_C, 27)
+ RELOC_NUMBER (RINDEX_16C_ABS24, 28)
+ RELOC_NUMBER (RINDEX_16C_ABS24_C, 29)
+ RELOC_NUMBER (RINDEX_16C_IMM04, 30)
+ RELOC_NUMBER (RINDEX_16C_IMM04_C, 31)
+ RELOC_NUMBER (RINDEX_16C_IMM16, 32)
+ RELOC_NUMBER (RINDEX_16C_IMM16_C, 33)
+ RELOC_NUMBER (RINDEX_16C_IMM20, 34)
+ RELOC_NUMBER (RINDEX_16C_IMM20_C, 35)
+ RELOC_NUMBER (RINDEX_16C_IMM24, 36)
+ RELOC_NUMBER (RINDEX_16C_IMM24_C, 37)
+ RELOC_NUMBER (RINDEX_16C_IMM32, 38)
+ RELOC_NUMBER (RINDEX_16C_IMM32_C, 39)
+END_RELOC_NUMBERS (RINDEX_16C_MAX)
+
+/* CR16C Relocation Types ('cr_reloc_type' entry in the reloc_map structure).
+ The relocation constant name is determined as follows :
+
+ R_16C_<format><size>[_C]
+
+ Where :
+
+ <format> is one of the following:
+ NUM - R_NUMBER mnemonic,
+ DISP - R_16C_DISPL mnemonic,
+ REG - R_16C_REGREL mnemonic,
+ ABS - R_16C_ABS mnemonic,
+ IMM - R_16C_IMMED mnemonic,
+ <size> stands for R_S_16C_<size>
+ _C means 'code label' and is only added when R_ADDRTYPE subfield
+ is of type R_CODE_ADDR. */
+
+/* The table below shows what the hex digits in the definition of the
+ relocation type constants correspond to.
+ ------------------------------------------------------------------
+ R_SIZESP R_FORMAT R_RELTO R_ADDRTYPE
+ ------------------------------------------------------------------ */
+/* R_S_16C_08 R_NUMBER R_ABS R_ADDRESS */
+#define R_16C_NUM08 0X0001
+
+/* R_S_16C_08 R_NUMBER R_ABS R_CODE_ADDR */
+#define R_16C_NUM08_C 0X0006
+
+/* R_S_16C_16 R_NUMBER R_ABS R_ADDRESS */
+#define R_16C_NUM16 0X1001
+
+/* R_S_16C_16 R_NUMBER R_ABS R_CODE_ADDR */
+#define R_16C_NUM16_C 0X1006
+
+/* R_S_16C_32 R_NUMBER R_ABS R_ADDRESS */
+#define R_16C_NUM32 0X2001
+
+/* R_S_16C_32 R_NUMBER R_ABS R_CODE_ADDR */
+#define R_16C_NUM32_C 0X2006
+
+/* R_S_16C_04 R_16C_DISPL R_PCREL R_ADDRESS */
+#define R_16C_DISP04 0X5411
+
+/* R_S_16C_04 R_16C_DISPL R_PCREL R_CODE_ADDR */
+#define R_16C_DISP04_C 0X5416
+
+/* R_S_16C_08 R_16C_DISPL R_PCREL R_ADDRESS */
+#define R_16C_DISP08 0X0411
+
+/* R_S_16C_08 R_16C_DISPL R_PCREL R_CODE_ADDR */
+#define R_16C_DISP08_C 0X0416
+
+/* R_S_16C_16 R_16C_DISPL R_PCREL R_ADDRESS */
+#define R_16C_DISP16 0X1411
+
+/* R_S_16C_16 R_16C_DISPL R_PCREL R_CODE_ADDR */
+#define R_16C_DISP16_C 0X1416
+
+/* R_S_16C_24 R_16C_DISPL R_PCREL R_ADDRESS */
+#define R_16C_DISP24 0X7411
+
+/* R_S_16C_24 R_16C_DISPL R_PCREL R_CODE_ADDR */
+#define R_16C_DISP24_C 0X7416
+
+/* R_S_16C_24a R_16C_DISPL R_PCREL R_ADDRESS */
+#define R_16C_DISP24a 0X6411
+
+/* R_S_16C_24a R_16C_DISPL R_PCREL R_CODE_ADDR */
+#define R_16C_DISP24a_C 0X6416
+
+/* R_S_16C_04 R_16C_REGREL R_ABS R_ADDRESS */
+#define R_16C_REG04 0X5201
+
+/* R_S_16C_04 R_16C_REGREL R_ABS R_CODE_ADDR */
+#define R_16C_REG04_C 0X5206
+
+/* R_S_16C_04_a R_16C_REGREL R_ABS R_ADDRESS */
+#define R_16C_REG04a 0X4201
+
+/* R_S_16C_04_a R_16C_REGREL R_ABS R_CODE_ADDR */
+#define R_16C_REG04a_C 0X4206
+
+/* R_S_16C_14 R_16C_REGREL R_ABS R_ADDRESS */
+#define R_16C_REG14 0X3201
+
+/* R_S_16C_14 R_16C_REGREL R_ABS R_CODE_ADDR */
+#define R_16C_REG14_C 0X3206
+
+/* R_S_16C_16 R_16C_REGREL R_ABS R_ADDRESS */
+#define R_16C_REG16 0X1201
+
+/* R_S_16C_16 R_16C_REGREL R_ABS R_CODE_ADDR */
+#define R_16C_REG16_C 0X1206
+
+/* R_S_16C_20 R_16C_REGREL R_ABS R_ADDRESS */
+#define R_16C_REG20 0X8201
+
+/* R_S_16C_20 R_16C_REGREL R_ABS R_CODE_ADDR */
+#define R_16C_REG20_C 0X8206
+
+/* R_S_16C_20 R_16C_ABS R_ABS R_ADDRESS */
+#define R_16C_ABS20 0X8101
+
+/* R_S_16C_20 R_16C_ABS R_ABS R_CODE_ADDR */
+#define R_16C_ABS20_C 0X8106
+
+/* R_S_16C_24 R_16C_ABS R_ABS R_ADDRESS */
+#define R_16C_ABS24 0X7101
+
+/* R_S_16C_24 R_16C_ABS R_ABS R_CODE_ADDR */
+#define R_16C_ABS24_C 0X7106
+
+/* R_S_16C_04 R_16C_IMMED R_ABS R_ADDRESS */
+#define R_16C_IMM04 0X5301
+
+/* R_S_16C_04 R_16C_IMMED R_ABS R_CODE_ADDR */
+#define R_16C_IMM04_C 0X5306
+
+/* R_S_16C_16 R_16C_IMMED R_ABS R_ADDRESS */
+#define R_16C_IMM16 0X1301
+
+/* R_S_16C_16 R_16C_IMMED R_ABS R_CODE_ADDR */
+#define R_16C_IMM16_C 0X1306
+
+/* R_S_16C_20 R_16C_IMMED R_ABS R_ADDRESS */
+#define R_16C_IMM20 0X8301
+
+/* R_S_16C_20 R_16C_IMMED R_ABS R_CODE_ADDR */
+#define R_16C_IMM20_C 0X8306
+
+/* R_S_16C_24 R_16C_IMMED R_ABS R_ADDRESS */
+#define R_16C_IMM24 0X7301
+
+/* R_S_16C_24 R_16C_IMMED R_ABS R_CODE_ADDR */
+#define R_16C_IMM24_C 0X7306
+
+/* R_S_16C_32 R_16C_IMMED R_ABS R_ADDRESS */
+#define R_16C_IMM32 0X2301
+
+/* R_S_16C_32 R_16C_IMMED R_ABS R_CODE_ADDR */
+#define R_16C_IMM32_C 0X2306
+
+
+/* Relocation item type. */
+#define R_ADDRTYPE 0x000f
+#define R_ADDRESS 0x0001 /* Take address of symbol. */
+#define R_CODE_ADDR 0x0006 /* Take address of symbol divided by 2. */
+
+/* Relocation action. */
+#define R_RELTO 0x00f0
+#define R_ABS 0x0000 /* Keep symbol's address as such. */
+#define R_PCREL 0x0010 /* Subtract the pc address of hole. */
+
+/* Relocation item data format. */
+#define R_FORMAT 0x0f00
+#define R_NUMBER 0x0000 /* Retain as two's complement value. */
+#define R_16C_DISPL 0x0400 /* CR16C displacement type. */
+#define R_16C_ABS 0x0100 /* CR16C absolute type. */
+#define R_16C_REGREL 0x0200 /* CR16C register-relative type. */
+#define R_16C_IMMED 0x0300 /* CR16C immediate type. */
+
+/* Relocation item size. */
+#define R_SIZESP 0xf000
+#define R_S_16C_04 0x5000
+#define R_S_16C_04_a 0x4000
+#define R_S_16C_08 0x0000
+#define R_S_16C_14 0x3000
+#define R_S_16C_16 0x1000
+#define R_S_16C_20 0x8000
+#define R_S_16C_24_a 0x6000
+#define R_S_16C_24 0x7000
+#define R_S_16C_32 0x2000
+
+
+/* Processor specific section indices. These sections do not actually
+ exist. Symbols with a st_shndx field corresponding to one of these
+ values have a special meaning. */
+
+/* Far common symbol. */
+#define SHN_CR16C_FCOMMON 0xff00
+#define SHN_CR16C_NCOMMON 0xff01
+
+typedef struct reloc_map
+{
+ unsigned short cr_reloc_type; /* CR relocation type. */
+ bfd_reloc_code_real_type bfd_reloc_enum; /* BFD relocation enum. */
+} RELOC_MAP;
+
+#endif /* _ELF_CR16C_H */
diff --git a/gnu/dist/binutils/include/elf/cris.h b/gnu/dist/binutils/include/elf/cris.h
index 3bd03e8aa81..5af5576c735 100644
--- a/gnu/dist/binutils/include/elf/cris.h
+++ b/gnu/dist/binutils/include/elf/cris.h
@@ -1,5 +1,5 @@
/* CRIS ELF support for BFD.
- Copyright 2000, 2001 Free Software Foundation, Inc.
+ Copyright 2000, 2001, 2004 Free Software Foundation, Inc.
Contributed by Axis Communications AB, Lund, Sweden.
Written by Hans-Peter Nilsson.
@@ -98,4 +98,16 @@ END_RELOC_NUMBERS (R_CRIS_max)
/* User symbols in this file have a leading underscore. */
#define EF_CRIS_UNDERSCORE 0x00000001
+/* This is a mask for different incompatible machine variants. */
+#define EF_CRIS_VARIANT_MASK 0x0000000e
+
+/* Variant 0; may contain v0..10 object. */
+#define EF_CRIS_VARIANT_ANY_V0_V10 0x00000000
+
+/* Variant 1; contains v32 object. */
+#define EF_CRIS_VARIANT_V32 0x00000002
+
+/* Variant 2; contains object compatible with v32 and v10. */
+#define EF_CRIS_VARIANT_COMMON_V10_V32 0x00000004
+
#endif /* _ELF_CRIS_H */
diff --git a/gnu/dist/binutils/include/elf/crx.h b/gnu/dist/binutils/include/elf/crx.h
new file mode 100644
index 00000000000..33ba0051478
--- /dev/null
+++ b/gnu/dist/binutils/include/elf/crx.h
@@ -0,0 +1,53 @@
+/* CRX ELF support for BFD.
+ Copyright 2004 Free Software Foundation, Inc.
+ Contributed by Tomer Levi, NSC, Israel.
+ Originally written for GAS 2.12 by Tomer Levi, NSC, Israel.
+ Updates, BFDizing, GNUifying and ELF support by Tomer Levi.
+
+ This file is part of BFD, the Binary File Descriptor library.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software Foundation,
+ Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+
+#ifndef _ELF_CRX_H
+#define _ELF_CRX_H
+
+#include "elf/reloc-macros.h"
+
+/* Creating indices for reloc_map_index array. */
+START_RELOC_NUMBERS(elf_crx_reloc_type)
+ RELOC_NUMBER (R_CRX_NONE, 0)
+ RELOC_NUMBER (R_CRX_REL4, 1)
+ RELOC_NUMBER (R_CRX_REL8, 2)
+ RELOC_NUMBER (R_CRX_REL8_CMP, 3)
+ RELOC_NUMBER (R_CRX_REL16, 4)
+ RELOC_NUMBER (R_CRX_REL24, 5)
+ RELOC_NUMBER (R_CRX_REL32, 6)
+ RELOC_NUMBER (R_CRX_REGREL12, 7)
+ RELOC_NUMBER (R_CRX_REGREL22, 8)
+ RELOC_NUMBER (R_CRX_REGREL28, 9)
+ RELOC_NUMBER (R_CRX_REGREL32, 10)
+ RELOC_NUMBER (R_CRX_ABS16, 11)
+ RELOC_NUMBER (R_CRX_ABS32, 12)
+ RELOC_NUMBER (R_CRX_NUM8, 13)
+ RELOC_NUMBER (R_CRX_NUM16, 14)
+ RELOC_NUMBER (R_CRX_NUM32, 15)
+ RELOC_NUMBER (R_CRX_IMM16, 16)
+ RELOC_NUMBER (R_CRX_IMM32, 17)
+ RELOC_NUMBER (R_CRX_SWITCH8, 18)
+ RELOC_NUMBER (R_CRX_SWITCH16, 19)
+ RELOC_NUMBER (R_CRX_SWITCH32, 20)
+END_RELOC_NUMBERS(R_CRX_MAX)
+
+#endif /* _ELF_CRX_H */
diff --git a/gnu/dist/binutils/include/elf/dwarf2.h b/gnu/dist/binutils/include/elf/dwarf2.h
index bede7e297a3..94589076f11 100644
--- a/gnu/dist/binutils/include/elf/dwarf2.h
+++ b/gnu/dist/binutils/include/elf/dwarf2.h
@@ -4,7 +4,7 @@
2003 Free Software Foundation, Inc.
Written by Gary Funck (gary@intrepid.com) The Ada Joint Program
- Office (AJPO), Florida State Unviversity and Silicon Graphics Inc.
+ Office (AJPO), Florida State University and Silicon Graphics Inc.
provided support for this effort -- June 21, 1995.
Derived from the DWARF 1 implementation written by Ron Guilmette
@@ -605,7 +605,8 @@ enum dwarf_calling_convention
{
DW_CC_normal = 0x1,
DW_CC_program = 0x2,
- DW_CC_nocall = 0x3
+ DW_CC_nocall = 0x3,
+ DW_CC_GNU_renesas_sh = 0x40
};
#define DW_CC_lo_user 0x40
diff --git a/gnu/dist/binutils/include/elf/external.h b/gnu/dist/binutils/include/elf/external.h
index a171439172d..e87db932bb9 100644
--- a/gnu/dist/binutils/include/elf/external.h
+++ b/gnu/dist/binutils/include/elf/external.h
@@ -1,5 +1,5 @@
/* ELF support for BFD.
- Copyright 1991, 1992, 1993, 1995, 1997, 1998, 1999, 2001
+ Copyright 1991, 1992, 1993, 1995, 1997, 1998, 1999, 2001, 2003
Free Software Foundation, Inc.
Written by Fred Fish @ Cygnus Support, from information published
diff --git a/gnu/dist/binutils/include/elf/frv.h b/gnu/dist/binutils/include/elf/frv.h
index 8246a21bd41..5e6f2204fc2 100644
--- a/gnu/dist/binutils/include/elf/frv.h
+++ b/gnu/dist/binutils/include/elf/frv.h
@@ -1,5 +1,5 @@
/* FRV ELF support for BFD.
- Copyright (C) 2002 Free Software Foundation, Inc.
+ Copyright (C) 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
This file is part of BFD, the Binary File Descriptor library.
@@ -49,6 +49,22 @@ START_RELOC_NUMBERS (elf_frv_reloc_type)
RELOC_NUMBER (R_FRV_GOTOFF12, 22)
RELOC_NUMBER (R_FRV_GOTOFFHI, 23)
RELOC_NUMBER (R_FRV_GOTOFFLO, 24)
+ RELOC_NUMBER (R_FRV_GETTLSOFF, 25)
+ RELOC_NUMBER (R_FRV_TLSDESC_VALUE, 26)
+ RELOC_NUMBER (R_FRV_GOTTLSDESC12, 27)
+ RELOC_NUMBER (R_FRV_GOTTLSDESCHI, 28)
+ RELOC_NUMBER (R_FRV_GOTTLSDESCLO, 29)
+ RELOC_NUMBER (R_FRV_TLSMOFF12, 30)
+ RELOC_NUMBER (R_FRV_TLSMOFFHI, 31)
+ RELOC_NUMBER (R_FRV_TLSMOFFLO, 32)
+ RELOC_NUMBER (R_FRV_GOTTLSOFF12, 33)
+ RELOC_NUMBER (R_FRV_GOTTLSOFFHI, 34)
+ RELOC_NUMBER (R_FRV_GOTTLSOFFLO, 35)
+ RELOC_NUMBER (R_FRV_TLSOFF, 36)
+ RELOC_NUMBER (R_FRV_TLSDESC_RELAX, 37)
+ RELOC_NUMBER (R_FRV_GETTLSOFF_RELAX, 38)
+ RELOC_NUMBER (R_FRV_TLSOFF_RELAX, 39)
+ RELOC_NUMBER (R_FRV_TLSMOFF, 40)
RELOC_NUMBER (R_FRV_GNU_VTINHERIT, 200)
RELOC_NUMBER (R_FRV_GNU_VTENTRY, 201)
END_RELOC_NUMBERS(R_FRV_max)
@@ -91,6 +107,8 @@ END_RELOC_NUMBERS(R_FRV_max)
#define EF_FRV_CPU_TOMCAT 0x04000000 /* Tomcat, FR500 prototype */
#define EF_FRV_CPU_FR400 0x05000000 /* FRV400 */
#define EF_FRV_CPU_FR550 0x06000000 /* FRV550 */
+#define EF_FRV_CPU_FR405 0x07000000
+#define EF_FRV_CPU_FR450 0x08000000
/* Mask of PIC related bits */
#define EF_FRV_PIC_FLAGS (EF_FRV_PIC | EF_FRV_LIBPIC | EF_FRV_BIGPIC \
diff --git a/gnu/dist/binutils/include/elf/i386.h b/gnu/dist/binutils/include/elf/i386.h
index 95941196c7e..f361edc84cd 100644
--- a/gnu/dist/binutils/include/elf/i386.h
+++ b/gnu/dist/binutils/include/elf/i386.h
@@ -1,5 +1,5 @@
/* ix86 ELF support for BFD.
- Copyright 1998, 1999, 2000 Free Software Foundation, Inc.
+ Copyright 1998, 1999, 2000, 2002, 2004 Free Software Foundation, Inc.
This file is part of BFD, the Binary File Descriptor library.
@@ -62,6 +62,9 @@ START_RELOC_NUMBERS (elf_i386_reloc_type)
RELOC_NUMBER (R_386_TLS_DTPOFF32, 36)
RELOC_NUMBER (R_386_TLS_TPOFF32, 37)
+ /* Used by Intel. */
+ RELOC_NUMBER (R_386_USED_BY_INTEL_200, 200)
+
/* These are GNU extensions to enable C++ vtable garbage collection. */
RELOC_NUMBER (R_386_GNU_VTINHERIT, 250)
RELOC_NUMBER (R_386_GNU_VTENTRY, 251)
diff --git a/gnu/dist/binutils/include/elf/ia64.h b/gnu/dist/binutils/include/elf/ia64.h
index 06dfa606dc7..62b971c23f5 100644
--- a/gnu/dist/binutils/include/elf/ia64.h
+++ b/gnu/dist/binutils/include/elf/ia64.h
@@ -1,5 +1,6 @@
/* IA-64 ELF support for BFD.
- Copyright 1998, 1999, 2000, 2003 Free Software Foundation, Inc.
+ Copyright 1998, 1999, 2000, 2001, 2002, 2003
+ Free Software Foundation, Inc.
Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
This file is part of BFD, the Binary File Descriptor library.
diff --git a/gnu/dist/binutils/include/elf/internal.h b/gnu/dist/binutils/include/elf/internal.h
index a7299d90534..eddf82e9451 100644
--- a/gnu/dist/binutils/include/elf/internal.h
+++ b/gnu/dist/binutils/include/elf/internal.h
@@ -1,6 +1,6 @@
/* ELF support for BFD.
- Copyright 1991, 1992, 1993, 1994, 1995, 1997, 1998, 2000, 2001, 2002
- Free Software Foundation, Inc.
+ Copyright 1991, 1992, 1993, 1994, 1995, 1997, 1998, 2000, 2001, 2002,
+ 2003 Free Software Foundation, Inc.
Written by Fred Fish @ Cygnus Support, from information published
in "UNIX System V Release 4, Programmers Guide: ANSI C and
diff --git a/gnu/dist/binutils/include/elf/iq2000.h b/gnu/dist/binutils/include/elf/iq2000.h
index 83c690c7091..56fc0ca4ae2 100644
--- a/gnu/dist/binutils/include/elf/iq2000.h
+++ b/gnu/dist/binutils/include/elf/iq2000.h
@@ -1,5 +1,5 @@
/* IQ2000 ELF support for BFD.
- Copyright (C) 2002 Free Software Foundation, Inc.
+ Copyright (C) 2002, 2003 Free Software Foundation, Inc.
This file is part of BFD, the Binary File Descriptor library.
diff --git a/gnu/dist/binutils/include/elf/m32r.h b/gnu/dist/binutils/include/elf/m32r.h
index 709d7923446..6441efe27e8 100644
--- a/gnu/dist/binutils/include/elf/m32r.h
+++ b/gnu/dist/binutils/include/elf/m32r.h
@@ -1,5 +1,5 @@
/* M32R ELF support for BFD.
- Copyright 1996, 1997, 1998, 1999, 2000, 2003 Free Software Foundation, Inc.
+ Copyright 1996, 1997, 1998, 1999, 2000, 2003, 2004 Free Software Foundation, Inc.
This file is part of BFD, the Binary File Descriptor library.
@@ -67,6 +67,9 @@ START_RELOC_NUMBERS (elf_m32r_reloc_type)
RELOC_NUMBER (R_M32R_GOTPC_HI_ULO, 59)
RELOC_NUMBER (R_M32R_GOTPC_HI_SLO, 60)
RELOC_NUMBER (R_M32R_GOTPC_LO, 61)
+ RELOC_NUMBER (R_M32R_GOTOFF_HI_ULO, 62)
+ RELOC_NUMBER (R_M32R_GOTOFF_HI_SLO, 63)
+ RELOC_NUMBER (R_M32R_GOTOFF_LO, 64)
END_RELOC_NUMBERS (R_M32R_max)
/* Processor specific section indices. These sections do not actually
diff --git a/gnu/dist/binutils/include/elf/m68k.h b/gnu/dist/binutils/include/elf/m68k.h
index 7769c59eb39..fe66c5552db 100644
--- a/gnu/dist/binutils/include/elf/m68k.h
+++ b/gnu/dist/binutils/include/elf/m68k.h
@@ -1,5 +1,5 @@
/* MC68k ELF support for BFD.
- Copyright 1998, 1999, 2000 Free Software Foundation, Inc.
+ Copyright 1998, 1999, 2000, 2002 Free Software Foundation, Inc.
This file is part of BFD, the Binary File Descriptor library.
diff --git a/gnu/dist/binutils/include/elf/mips.h b/gnu/dist/binutils/include/elf/mips.h
index ce43158123f..472a7c9d205 100644
--- a/gnu/dist/binutils/include/elf/mips.h
+++ b/gnu/dist/binutils/include/elf/mips.h
@@ -1,5 +1,6 @@
/* MIPS ELF support for BFD.
- Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2003
+ Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
+ 2003, 2004, 2005
Free Software Foundation, Inc.
By Ian Lance Taylor, Cygnus Support, <ian@cygnus.com>, from
@@ -72,16 +73,37 @@ START_RELOC_NUMBERS (elf_mips_reloc_type)
RELOC_NUMBER (R_MIPS_PJUMP, 35)
RELOC_NUMBER (R_MIPS_RELGOT, 36)
RELOC_NUMBER (R_MIPS_JALR, 37)
- RELOC_NUMBER (R_MIPS_max, 38)
+ /* TLS relocations. */
+ RELOC_NUMBER (R_MIPS_TLS_DTPMOD32, 38)
+ RELOC_NUMBER (R_MIPS_TLS_DTPREL32, 39)
+ RELOC_NUMBER (R_MIPS_TLS_DTPMOD64, 40)
+ RELOC_NUMBER (R_MIPS_TLS_DTPREL64, 41)
+ RELOC_NUMBER (R_MIPS_TLS_GD, 42)
+ RELOC_NUMBER (R_MIPS_TLS_LDM, 43)
+ RELOC_NUMBER (R_MIPS_TLS_DTPREL_HI16, 44)
+ RELOC_NUMBER (R_MIPS_TLS_DTPREL_LO16, 45)
+ RELOC_NUMBER (R_MIPS_TLS_GOTTPREL, 46)
+ RELOC_NUMBER (R_MIPS_TLS_TPREL32, 47)
+ RELOC_NUMBER (R_MIPS_TLS_TPREL64, 48)
+ RELOC_NUMBER (R_MIPS_TLS_TPREL_HI16, 49)
+ RELOC_NUMBER (R_MIPS_TLS_TPREL_LO16, 50)
+ FAKE_RELOC (R_MIPS_max, 51)
/* These relocs are used for the mips16. */
+ FAKE_RELOC (R_MIPS16_min, 100)
RELOC_NUMBER (R_MIPS16_26, 100)
RELOC_NUMBER (R_MIPS16_GPREL, 101)
- /* These are GNU extensions to handle embedded-pic. */
+ RELOC_NUMBER (R_MIPS16_GOT16, 102)
+ RELOC_NUMBER (R_MIPS16_CALL16, 103)
+ RELOC_NUMBER (R_MIPS16_HI16, 104)
+ RELOC_NUMBER (R_MIPS16_LO16, 105)
+ FAKE_RELOC (R_MIPS16_max, 106)
+ /* This was a GNU extension used by embedded-PIC. It was co-opted by
+ mips-linux for exception-handling data. It is no longer used, but
+ should continue to be supported by the linker for backward
+ compatibility. (GCC stopped using it in May, 2004.) */
RELOC_NUMBER (R_MIPS_PC32, 248)
- RELOC_NUMBER (R_MIPS_PC64, 249)
+ /* FIXME: this relocation is used internally by gas. */
RELOC_NUMBER (R_MIPS_GNU_REL16_S2, 250)
- RELOC_NUMBER (R_MIPS_GNU_REL_LO16, 251)
- RELOC_NUMBER (R_MIPS_GNU_REL_HI16, 252)
/* These are GNU extensions to enable C++ vtable garbage collection. */
RELOC_NUMBER (R_MIPS_GNU_VTINHERIT, 253)
RELOC_NUMBER (R_MIPS_GNU_VTENTRY, 254)
@@ -189,6 +211,7 @@ END_RELOC_NUMBERS (R_MIPS_maxext)
#define E_MIPS_MACH_SB1 0x008a0000
#define E_MIPS_MACH_5400 0x00910000
#define E_MIPS_MACH_5500 0x00980000
+#define E_MIPS_MACH_9000 0x00990000
/* Processor specific section indices. These sections do not actually
exist. Symbols with a st_shndx field corresponding to one of these
diff --git a/gnu/dist/binutils/include/elf/mn10300.h b/gnu/dist/binutils/include/elf/mn10300.h
index e640096a24f..5ae52f1d876 100644
--- a/gnu/dist/binutils/include/elf/mn10300.h
+++ b/gnu/dist/binutils/include/elf/mn10300.h
@@ -1,5 +1,5 @@
/* MN10300 ELF support for BFD.
- Copyright 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
+ Copyright 1998, 1999, 2000, 2003 Free Software Foundation, Inc.
This file is part of BFD, the Binary File Descriptor library.
diff --git a/gnu/dist/binutils/include/elf/msp430.h b/gnu/dist/binutils/include/elf/msp430.h
index 912ded7685d..40ab2e27eab 100644
--- a/gnu/dist/binutils/include/elf/msp430.h
+++ b/gnu/dist/binutils/include/elf/msp430.h
@@ -1,5 +1,5 @@
/* MSP430 ELF support for BFD.
- Copyright (C) 2002 Free Software Foundation, Inc.
+ Copyright (C) 2002, 2003, 2004 Free Software Foundation, Inc.
Contributed by Dmitry Diky <diwil@mail.ru>
This file is part of BFD, the Binary File Descriptor library.
@@ -50,6 +50,8 @@ START_RELOC_NUMBERS (elf_msp430_reloc_type)
RELOC_NUMBER (R_MSP430_16_PCREL, 4)
RELOC_NUMBER (R_MSP430_16_BYTE, 5)
RELOC_NUMBER (R_MSP430_16_PCREL_BYTE, 6)
+ RELOC_NUMBER (R_MSP430_2X_PCREL, 7)
+ RELOC_NUMBER (R_MSP430_RL_PCREL, 8)
END_RELOC_NUMBERS (R_MSP430_max)
diff --git a/gnu/dist/binutils/include/elf/ppc.h b/gnu/dist/binutils/include/elf/ppc.h
index b510f441c65..a41b6997f73 100644
--- a/gnu/dist/binutils/include/elf/ppc.h
+++ b/gnu/dist/binutils/include/elf/ppc.h
@@ -1,5 +1,5 @@
/* PPC ELF support for BFD.
- Copyright 1995, 1996, 1998, 2000, 2001, 2002, 2003
+ Copyright 1995, 1996, 1998, 2000, 2001, 2002, 2003, 2005
Free Software Foundation, Inc.
By Michael Meissner, Cygnus Support, <meissner@cygnus.com>, from information
@@ -122,8 +122,10 @@ START_RELOC_NUMBERS (elf_ppc_reloc_type)
/* Fake relocations for branch stubs. This will keep them
together. */
-#define R_PPC_RELAX32 251
-#define R_PPC_RELAX32PC 252
+#define R_PPC_RELAX32 249
+#define R_PPC_RELAX32PC 250
+#define R_PPC_RELAX32_PLT 251
+#define R_PPC_RELAX32PC_PLT 252
/* These are GNU extensions to enable C++ vtable garbage collection. */
RELOC_NUMBER (R_PPC_GNU_VTINHERIT, 253)
diff --git a/gnu/dist/binutils/include/elf/s390.h b/gnu/dist/binutils/include/elf/s390.h
index 3a1306fa750..d7db6996a6f 100644
--- a/gnu/dist/binutils/include/elf/s390.h
+++ b/gnu/dist/binutils/include/elf/s390.h
@@ -1,5 +1,5 @@
/* 390 ELF support for BFD.
- Copyright 2000, 2001 Free Software Foundation, Inc.
+ Copyright 2000, 2001, 2003 Free Software Foundation, Inc.
Contributed by Carl B. Pedersen and Martin Schwidefsky.
This file is part of BFD, the Binary File Descriptor library.
diff --git a/gnu/dist/binutils/include/elf/sh.h b/gnu/dist/binutils/include/elf/sh.h
index 15d460d36b4..ae4ac78fe45 100644
--- a/gnu/dist/binutils/include/elf/sh.h
+++ b/gnu/dist/binutils/include/elf/sh.h
@@ -1,5 +1,5 @@
/* SH ELF support for BFD.
- Copyright 1998, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
+ Copyright 1998, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
This file is part of BFD, the Binary File Descriptor library.
@@ -27,56 +27,63 @@
#define EF_SH1 1
#define EF_SH2 2
#define EF_SH3 3
-#define EF_SH_HAS_DSP(flags) (((flags) & EF_SH_MACH_MASK & ~3) == 4)
#define EF_SH_DSP 4
#define EF_SH3_DSP 5
#define EF_SH4AL_DSP 6
-#define EF_SH_HAS_FP(flags) ((flags) & 8)
#define EF_SH3E 8
#define EF_SH4 9
#define EF_SH2E 11
#define EF_SH4A 12
+#define EF_SH2A 13
-#define EF_SH4_NOFPU 0x10
-#define EF_SH4A_NOFPU 0x11
+#define EF_SH4_NOFPU 16
+#define EF_SH4A_NOFPU 17
+#define EF_SH4_NOMMU_NOFPU 18
+#define EF_SH2A_NOFPU 19
+#define EF_SH3_NOMMU 20
+
+#define EF_SH2A_SH4_NOFPU 21
+#define EF_SH2A_SH3_NOFPU 22
+#define EF_SH2A_SH4 23
+#define EF_SH2A_SH3E 24
/* This one can only mix in objects from other EF_SH5 objects. */
#define EF_SH5 10
-#define EF_SH_MERGE_MACH(mach1, mach2) \
- (((((mach1) == EF_SH3 || (mach1) == EF_SH_UNKNOWN) && (mach2) == EF_SH_DSP) \
- || ((mach1) == EF_SH_DSP \
- && ((mach2) == EF_SH3 || (mach2) == EF_SH_UNKNOWN))) \
- ? EF_SH3_DSP \
- : (((mach1) < EF_SH3 && (mach2) == EF_SH_UNKNOWN) \
- || ((mach2) < EF_SH3 && (mach1) == EF_SH_UNKNOWN)) \
- ? EF_SH3 \
- : ((mach1) == EF_SH2E && EF_SH_HAS_FP (mach2)) \
- ? (mach2) \
- : ((mach2) == EF_SH2E && EF_SH_HAS_FP (mach1)) \
- ? (mach1) \
- : (((mach1) == EF_SH2E && (mach2) == EF_SH_UNKNOWN) \
- || ((mach2) == EF_SH2E && (mach1) == EF_SH_UNKNOWN)) \
- ? EF_SH2E \
- : (((mach1) == EF_SH3E && (mach2) == EF_SH_UNKNOWN) \
- || ((mach2) == EF_SH3E && (mach1) == EF_SH_UNKNOWN)) \
- ? EF_SH4 \
- /* ??? SH4? Why not SH3E? */ \
- : ((((mach1) == EF_SH4_NOFPU || (mach1) == EF_SH4A_NOFPU) \
- && EF_SH_HAS_DSP (mach2)) \
- || (((mach2) == EF_SH4_NOFPU || (mach2) == EF_SH4A_NOFPU) \
- && EF_SH_HAS_DSP (mach1))) \
- ? EF_SH4AL_DSP \
- : ((mach1) == EF_SH4_NOFPU && EF_SH_HAS_FP (mach2)) \
- ? ((mach2) < EF_SH4A) ? EF_SH4 : (mach2) \
- : ((mach2) == EF_SH4_NOFPU && EF_SH_HAS_FP (mach1)) \
- ? ((mach1) < EF_SH4A) ? EF_SH4 : (mach1) \
- : ((mach1) == EF_SH4A_NOFPU && EF_SH_HAS_FP (mach2)) \
- ? ((mach2) <= EF_SH4A) ? EF_SH4A : (mach2) \
- : ((mach2) == EF_SH4A_NOFPU && EF_SH_HAS_FP (mach1)) \
- ? ((mach1) <= EF_SH4A) ? EF_SH4A : (mach1) \
- : (((mach1) == EF_SH2E ? 7 : (mach1)) > ((mach2) == EF_SH2E ? 7 : (mach2)) \
- ? (mach1) : (mach2)))
+/* Define the mapping from ELF to bfd mach numbers.
+ bfd_mach_* are defined in bfd_in2.h (generated from
+ archures.c). */
+#define EF_SH_BFD_TABLE \
+/* EF_SH_UNKNOWN */ bfd_mach_sh3 , \
+/* EF_SH1 */ bfd_mach_sh , \
+/* EF_SH2 */ bfd_mach_sh2 , \
+/* EF_SH3 */ bfd_mach_sh3 , \
+/* EF_SH_DSP */ bfd_mach_sh_dsp , \
+/* EF_SH3_DSP */ bfd_mach_sh3_dsp , \
+/* EF_SHAL_DSP */ bfd_mach_sh4al_dsp , \
+/* 7 */ 0, \
+/* EF_SH3E */ bfd_mach_sh3e , \
+/* EF_SH4 */ bfd_mach_sh4 , \
+/* EF_SH5 */ 0, \
+/* EF_SH2E */ bfd_mach_sh2e , \
+/* EF_SH4A */ bfd_mach_sh4a , \
+/* EF_SH2A */ bfd_mach_sh2a , \
+/* 14, 15 */ 0, 0, \
+/* EF_SH4_NOFPU */ bfd_mach_sh4_nofpu , \
+/* EF_SH4A_NOFPU */ bfd_mach_sh4a_nofpu , \
+/* EF_SH4_NOMMU_NOFPU */ bfd_mach_sh4_nommu_nofpu, \
+/* EF_SH2A_NOFPU */ bfd_mach_sh2a_nofpu , \
+/* EF_SH3_NOMMU */ bfd_mach_sh3_nommu , \
+/* EF_SH2A_SH4_NOFPU */ bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu, \
+/* EF_SH2A_SH3_NOFPU */ bfd_mach_sh2a_nofpu_or_sh3_nommu, \
+/* EF_SH2A_SH4 */ bfd_mach_sh2a_or_sh4 , \
+/* EF_SH2A_SH3E */ bfd_mach_sh2a_or_sh3e
+
+/* Convert arch_sh* into EF_SH*. */
+int sh_find_elf_flags (unsigned int arch_set);
+
+/* Convert bfd_mach_* into EF_SH*. */
+int sh_elf_get_flags_from_mach (unsigned long mach);
/* Flags for the st_other symbol field.
Keep away from the STV_ visibility flags (bit 0..1). */
diff --git a/gnu/dist/binutils/include/elf/sparc.h b/gnu/dist/binutils/include/elf/sparc.h
index 2d28d26f9b4..82702144b24 100644
--- a/gnu/dist/binutils/include/elf/sparc.h
+++ b/gnu/dist/binutils/include/elf/sparc.h
@@ -1,5 +1,6 @@
/* SPARC ELF support for BFD.
- Copyright 1996, 1997, 1998, 1999, 2000, 2002 Free Software Foundation, Inc.
+ Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2003
+ Free Software Foundation, Inc.
By Doug Evans, Cygnus Support, <dje@cygnus.com>.
This file is part of BFD, the Binary File Descriptor library.
diff --git a/gnu/dist/binutils/include/elf/v850.h b/gnu/dist/binutils/include/elf/v850.h
index 7d5110b3342..c5ce366b086 100644
--- a/gnu/dist/binutils/include/elf/v850.h
+++ b/gnu/dist/binutils/include/elf/v850.h
@@ -1,5 +1,6 @@
/* V850 ELF support for BFD.
- Copyright 1997, 1998, 2000, 2002, 2003 Free Software Foundation, Inc.
+ Copyright 1997, 1998, 2000, 2002, 2003, 2004
+ Free Software Foundation, Inc.
Created by Michael Meissner, Cygnus Support <meissner@cygnus.com>
This file is part of BFD, the Binary File Descriptor library.
@@ -79,6 +80,7 @@ START_RELOC_NUMBERS (v850_reloc_type)
RELOC_NUMBER (R_V850_LONGJUMP, 26)
RELOC_NUMBER (R_V850_ALIGN, 27)
RELOC_NUMBER (R_V850_REL32, 28)
+ RELOC_NUMBER (R_V850_LO16_SPLIT_OFFSET, 29) /* For ld.bu */
END_RELOC_NUMBERS (R_V850_max)
diff --git a/gnu/dist/binutils/include/elf/x86-64.h b/gnu/dist/binutils/include/elf/x86-64.h
index 7e9100dba4a..775c0e4d9d5 100644
--- a/gnu/dist/binutils/include/elf/x86-64.h
+++ b/gnu/dist/binutils/include/elf/x86-64.h
@@ -1,5 +1,5 @@
/* x86_64 ELF support for BFD.
- Copyright (C) 2000, 2002 Free Software Foundation, Inc.
+ Copyright (C) 2000, 2001, 2002, 2004 Free Software Foundation, Inc.
Contributed by Jan Hubicka <jh@suse.cz>
This file is part of BFD, the Binary File Descriptor library.
@@ -53,4 +53,8 @@ START_RELOC_NUMBERS (elf_x86_64_reloc_type)
RELOC_NUMBER (R_X86_64_GNU_VTENTRY, 251) /* GNU C++ hack */
END_RELOC_NUMBERS (R_X86_64_max)
+/* Processor specific section types. */
+
+#define SHT_X86_64_UNWIND 0x70000001 /* unwind information */
+
#endif
diff --git a/gnu/dist/binutils/include/elf/xtensa.h b/gnu/dist/binutils/include/elf/xtensa.h
index 6c584c71515..14f99132299 100644
--- a/gnu/dist/binutils/include/elf/xtensa.h
+++ b/gnu/dist/binutils/include/elf/xtensa.h
@@ -1,5 +1,5 @@
/* Xtensa ELF support for BFD.
- Copyright 2003 Free Software Foundation, Inc.
+ Copyright 2003, 2004 Free Software Foundation, Inc.
Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica.
This file is part of BFD, the Binary File Descriptor library.
@@ -42,6 +42,39 @@ START_RELOC_NUMBERS (elf_xtensa_reloc_type)
RELOC_NUMBER (R_XTENSA_ASM_SIMPLIFY, 12)
RELOC_NUMBER (R_XTENSA_GNU_VTINHERIT, 15)
RELOC_NUMBER (R_XTENSA_GNU_VTENTRY, 16)
+ RELOC_NUMBER (R_XTENSA_DIFF8, 17)
+ RELOC_NUMBER (R_XTENSA_DIFF16, 18)
+ RELOC_NUMBER (R_XTENSA_DIFF32, 19)
+ RELOC_NUMBER (R_XTENSA_SLOT0_OP, 20)
+ RELOC_NUMBER (R_XTENSA_SLOT1_OP, 21)
+ RELOC_NUMBER (R_XTENSA_SLOT2_OP, 22)
+ RELOC_NUMBER (R_XTENSA_SLOT3_OP, 23)
+ RELOC_NUMBER (R_XTENSA_SLOT4_OP, 24)
+ RELOC_NUMBER (R_XTENSA_SLOT5_OP, 25)
+ RELOC_NUMBER (R_XTENSA_SLOT6_OP, 26)
+ RELOC_NUMBER (R_XTENSA_SLOT7_OP, 27)
+ RELOC_NUMBER (R_XTENSA_SLOT8_OP, 28)
+ RELOC_NUMBER (R_XTENSA_SLOT9_OP, 29)
+ RELOC_NUMBER (R_XTENSA_SLOT10_OP, 30)
+ RELOC_NUMBER (R_XTENSA_SLOT11_OP, 31)
+ RELOC_NUMBER (R_XTENSA_SLOT12_OP, 32)
+ RELOC_NUMBER (R_XTENSA_SLOT13_OP, 33)
+ RELOC_NUMBER (R_XTENSA_SLOT14_OP, 34)
+ RELOC_NUMBER (R_XTENSA_SLOT0_ALT, 35)
+ RELOC_NUMBER (R_XTENSA_SLOT1_ALT, 36)
+ RELOC_NUMBER (R_XTENSA_SLOT2_ALT, 37)
+ RELOC_NUMBER (R_XTENSA_SLOT3_ALT, 38)
+ RELOC_NUMBER (R_XTENSA_SLOT4_ALT, 39)
+ RELOC_NUMBER (R_XTENSA_SLOT5_ALT, 40)
+ RELOC_NUMBER (R_XTENSA_SLOT6_ALT, 41)
+ RELOC_NUMBER (R_XTENSA_SLOT7_ALT, 42)
+ RELOC_NUMBER (R_XTENSA_SLOT8_ALT, 43)
+ RELOC_NUMBER (R_XTENSA_SLOT9_ALT, 44)
+ RELOC_NUMBER (R_XTENSA_SLOT10_ALT, 45)
+ RELOC_NUMBER (R_XTENSA_SLOT11_ALT, 46)
+ RELOC_NUMBER (R_XTENSA_SLOT12_ALT, 47)
+ RELOC_NUMBER (R_XTENSA_SLOT13_ALT, 48)
+ RELOC_NUMBER (R_XTENSA_SLOT14_ALT, 49)
END_RELOC_NUMBERS (R_XTENSA_max)
/* Processor-specific flags for the ELF header e_flags field. */
@@ -78,11 +111,88 @@ END_RELOC_NUMBERS (R_XTENSA_max)
#define XTENSA_INSN_SEC_NAME ".xt.insn"
#define XTENSA_LIT_SEC_NAME ".xt.lit"
+#define XTENSA_PROP_SEC_NAME ".xt.prop"
typedef struct property_table_entry_t
{
bfd_vma address;
bfd_vma size;
+ flagword flags;
} property_table_entry;
+/* Flags in the property tables to specify whether blocks of memory are
+ literals, instructions, data, or unreachable. For instructions,
+ blocks that begin loop targets and branch targets are designated.
+ Blocks that do not allow density instructions, instruction reordering
+ or transformation are also specified. Finally, for branch targets,
+ branch target alignment priority is included. Alignment of the next
+ block is specified in the current block and the size of the current
+ block does not include any fill required to align to the next
+ block. */
+
+#define XTENSA_PROP_LITERAL 0x00000001
+#define XTENSA_PROP_INSN 0x00000002
+#define XTENSA_PROP_DATA 0x00000004
+#define XTENSA_PROP_UNREACHABLE 0x00000008
+/* Instruction-only properties at beginning of code. */
+#define XTENSA_PROP_INSN_LOOP_TARGET 0x00000010
+#define XTENSA_PROP_INSN_BRANCH_TARGET 0x00000020
+/* Instruction-only properties about code. */
+#define XTENSA_PROP_INSN_NO_DENSITY 0x00000040
+#define XTENSA_PROP_INSN_NO_REORDER 0x00000080
+#define XTENSA_PROP_INSN_NO_TRANSFORM 0x00000100
+
+/* Branch target alignment information. This transmits information
+ to the linker optimization about the priority of aligning a
+ particular block for branch target alignment: None, low priority,
+ high priority, or required. These only need to be checked in
+ instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET.
+ Common usage is:
+
+ switch (GET_XTENSA_PROP_BT_ALIGN(flags))
+ case XTENSA_PROP_BT_ALIGN_NONE:
+ case XTENSA_PROP_BT_ALIGN_LOW:
+ case XTENSA_PROP_BT_ALIGN_HIGH:
+ case XTENSA_PROP_BT_ALIGN_REQUIRE:
+*/
+#define XTENSA_PROP_BT_ALIGN_MASK 0x00000600
+
+/* No branch target alignment. */
+#define XTENSA_PROP_BT_ALIGN_NONE 0x0
+/* Low priority branch target alignment. */
+#define XTENSA_PROP_BT_ALIGN_LOW 0x1
+/* High priority branch target alignment. */
+#define XTENSA_PROP_BT_ALIGN_HIGH 0x2
+/* Required branch target alignment. */
+#define XTENSA_PROP_BT_ALIGN_REQUIRE 0x3
+
+#define GET_XTENSA_PROP_BT_ALIGN(flag) \
+ (((unsigned)((flag) & (XTENSA_PROP_BT_ALIGN_MASK))) >> 9)
+#define SET_XTENSA_PROP_BT_ALIGN(flag, align) \
+ (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \
+ (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK))
+
+/* Alignment is specified in the block BEFORE the one that needs
+ alignment. Up to 5 bits. Use GET_XTENSA_PROP_ALIGNMENT(flags) to
+ get the required alignment specified as a power of 2. Use
+ SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required
+ alignment. Be careful of side effects since the SET will evaluate
+ flags twice. Also, note that the SIZE of a block in the property
+ table does not include the alignment size, so the alignment fill
+ must be calculated to determine if two blocks are contiguous.
+ TEXT_ALIGN is not currently implemented but is a placeholder for a
+ possible future implementation. */
+
+#define XTENSA_PROP_ALIGN 0x00000800
+
+#define XTENSA_PROP_ALIGNMENT_MASK 0x0001f000
+
+#define GET_XTENSA_PROP_ALIGNMENT(flag) \
+ (((unsigned)((flag) & (XTENSA_PROP_ALIGNMENT_MASK))) >> 12)
+#define SET_XTENSA_PROP_ALIGNMENT(flag, align) \
+ (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \
+ (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK))
+
+#define XTENSA_PROP_INSN_ABSLIT 0x00020000
+
#endif /* _ELF_XTENSA_H */
diff --git a/gnu/dist/binutils/include/fibheap.h b/gnu/dist/binutils/include/fibheap.h
index 4eebaf13ba6..e1e843ddbb1 100644
--- a/gnu/dist/binutils/include/fibheap.h
+++ b/gnu/dist/binutils/include/fibheap.h
@@ -59,7 +59,7 @@ typedef struct fibnode
struct fibnode *right;
fibheapkey_t key;
void *data;
-#ifdef __GNUC__
+#if defined (__GNUC__) && (!defined (SIZEOF_INT) || SIZEOF_INT < 4)
__extension__ unsigned long int degree : 31;
__extension__ unsigned long int mark : 1;
#else
diff --git a/gnu/dist/binutils/include/gdb/ChangeLog b/gnu/dist/binutils/include/gdb/ChangeLog
index 3a17b1d797f..42e1bfac4b8 100644
--- a/gnu/dist/binutils/include/gdb/ChangeLog
+++ b/gnu/dist/binutils/include/gdb/ChangeLog
@@ -1,3 +1,44 @@
+2005-01-28 Hans-Peter Nilsson <hp@axis.com>
+
+ * callback.h (struct host_callback_struct): New members pipe,
+ pipe_empty, pipe_nonempty, ispipe, pipe_buffer and
+ target_sizeof_int.
+ (CB_SYS_pipe): New macro.
+
+ * callback.h: Include "bfd.h".
+ (struct host_callback_struct): New member target_endian.
+ (cb_store_target_endian): Declare.
+
+2004-12-15 Hans-Peter Nilsson <hp@axis.com>
+
+ * callback.h (CB_SYS_truncate, CB_SYS_ftruncate): New macros.
+
+2004-12-13 Hans-Peter Nilsson <hp@axis.com>
+
+ * callback.h (struct host_callback_struct): New member lstat.
+ (CB_SYS_lstat): New macro.
+ (CB_SYS_rename): New macro.
+
+2004-09-08 Michael Snyder <msnyder@redhat.com>
+
+ Commited by Corinna Vinschen <vinschen@redhat.com>
+ * sim-sh.h: Add new sh2a banked registers.
+
+2004-08-04 Andrew Cagney <cagney@gnu.org>
+
+ * sim-ppc.h: Add extern "C" wrapper.
+ (enum sim_ppc_regnum): Add full list of SPRs.
+
+2004-08-04 Jim Blandy <jimb@redhat.com>
+
+ * sim-ppc.h: New file.
+
+2004-06-25 J"orn Rennecke <joern.rennecke@superh.com>
+
+ * callback.h (host_callback_struct): Replace members fdopen and
+ alwaysopen with fd_buddy.
+ [sim/common: * callback.c: Changed all users. ]
+
2003-10-31 Kevin Buettner <kevin@redhat.com>
* sim-frv.h: New file.
diff --git a/gnu/dist/binutils/include/gdb/callback.h b/gnu/dist/binutils/include/gdb/callback.h
index 3fa419143ae..6c75a193d06 100644
--- a/gnu/dist/binutils/include/gdb/callback.h
+++ b/gnu/dist/binutils/include/gdb/callback.h
@@ -56,6 +56,8 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#include <varargs.h>
#endif
#endif
+/* Needed for enum bfd_endian. */
+#include "bfd.h"
/* Mapping of host/target values. */
/* ??? For debugging purposes, one might want to add a string of the
@@ -93,8 +95,17 @@ struct host_callback_struct
void (*flush_stderr) PARAMS ((host_callback *));
int (*stat) PARAMS ((host_callback *, const char *, struct stat *));
int (*fstat) PARAMS ((host_callback *, int, struct stat *));
+ int (*lstat) PARAMS ((host_callback *, const char *, struct stat *));
int (*ftruncate) PARAMS ((host_callback *, int, long));
int (*truncate) PARAMS ((host_callback *, const char *, long));
+ int (*pipe) PARAMS ((host_callback *, int *));
+
+ /* Called by the framework when a read call has emptied a pipe buffer. */
+ void (*pipe_empty) PARAMS ((host_callback *, int read_fd, int write_fd));
+
+ /* Called by the framework when a write call makes a pipe buffer
+ non-empty. */
+ void (*pipe_nonempty) PARAMS ((host_callback *, int read_fd, int write_fd));
/* When present, call to the client to give it the oportunity to
poll any io devices for a request to quit (indicated by a nonzero
@@ -123,8 +134,31 @@ struct host_callback_struct
int last_errno; /* host format */
int fdmap[MAX_CALLBACK_FDS];
- char fdopen[MAX_CALLBACK_FDS];
- char alwaysopen[MAX_CALLBACK_FDS];
+ /* fd_buddy is used to contruct circular lists of target fds that point to
+ the same host fd. A uniquely mapped fd points to itself; for a closed
+ one, fd_buddy has the value -1. The host file descriptors for stdin /
+ stdout / stderr are never closed by the simulators, so they are put
+ in a special fd_buddy circular list which also has MAX_CALLBACK_FDS
+ as a member. */
+ /* ??? We don't have a callback entry for dup, although it is trival to
+ implement now. */
+ short fd_buddy[MAX_CALLBACK_FDS+1];
+
+ /* 0 = none, >0 = reader (index of writer),
+ <0 = writer (negative index of reader).
+ If abs (ispipe[N]) == N, then N is an end of a pipe whose other
+ end is closed. */
+ short ispipe[MAX_CALLBACK_FDS];
+
+ /* A writer stores the buffer at its index. Consecutive writes
+ realloc the buffer and add to the size. The reader indicates the
+ read part in its .size, until it has consumed it all, at which
+ point it deallocates the buffer and zeroes out both sizes. */
+ struct pipe_write_buffer
+ {
+ int size;
+ char *buffer;
+ } pipe_buffer[MAX_CALLBACK_FDS];
/* System call numbers. */
CB_TARGET_DEFS_MAP *syscall_map;
@@ -143,6 +177,16 @@ struct host_callback_struct
Example: "st_dev,4:st_ino,4:st_mode,4:..." */
const char *stat_map;
+ enum bfd_endian target_endian;
+
+ /* Size of an "int" on the target (for syscalls whose ABI uses "int").
+ This must include padding, and only padding-at-higher-address is
+ supported. For example, a 64-bit target with 32-bit int:s which
+ are padded to 64 bits when in an array, should supposedly set this
+ to 8. The default is 4 which matches ILP32 targets and 64-bit
+ targets with 32-bit ints and no padding. */
+ int target_sizeof_int;
+
/* Marker for those wanting to do sanity checks.
This should remain the last member of this struct to help catch
miscompilation errors. */
@@ -181,6 +225,13 @@ extern host_callback default_callback;
#define CB_SYS_chmod 16
#define CB_SYS_utime 17
#define CB_SYS_time 18
+
+/* More standard syscalls. */
+#define CB_SYS_lstat 19
+#define CB_SYS_rename 20
+#define CB_SYS_truncate 21
+#define CB_SYS_ftruncate 22
+#define CB_SYS_pipe 23
/* Struct use to pass and return information necessary to perform a
system call. */
@@ -266,6 +317,9 @@ int cb_host_to_target_signal PARAMS ((host_callback *, int));
Result is size of target stat struct or 0 if error. */
int cb_host_to_target_stat PARAMS ((host_callback *, const struct stat *, PTR));
+/* Translate a value to target endian. */
+void cb_store_target_endian PARAMS ((host_callback *, char *, int, long));
+
/* Perform a system call. */
CB_RC cb_syscall PARAMS ((host_callback *, CB_SYSCALL *));
diff --git a/gnu/dist/binutils/include/gdb/sim-ppc.h b/gnu/dist/binutils/include/gdb/sim-ppc.h
new file mode 100644
index 00000000000..e31a6711292
--- /dev/null
+++ b/gnu/dist/binutils/include/gdb/sim-ppc.h
@@ -0,0 +1,771 @@
+/* sim-ppc.h --- interface between PowerPC simulator and GDB.
+
+ Copyright 2004 Free Software Foundation, Inc.
+
+ Contributed by Red Hat.
+
+ This file is part of GDB.
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License as
+ published by the Free Software Foundation; either version 2 of the
+ License, or (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
+ 02111-1307, USA. */
+
+#if !defined (SIM_PPC_H)
+#define SIM_PPC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* The register access functions, sim_fetch_register and
+ sim_store_register, use the following numbering for PowerPC
+ registers. */
+
+enum sim_ppc_regnum
+ {
+ /* General-purpose registers, r0 -- r31. */
+ sim_ppc_r0_regnum,
+ sim_ppc_r1_regnum,
+ sim_ppc_r2_regnum,
+ sim_ppc_r3_regnum,
+ sim_ppc_r4_regnum,
+ sim_ppc_r5_regnum,
+ sim_ppc_r6_regnum,
+ sim_ppc_r7_regnum,
+ sim_ppc_r8_regnum,
+ sim_ppc_r9_regnum,
+ sim_ppc_r10_regnum,
+ sim_ppc_r11_regnum,
+ sim_ppc_r12_regnum,
+ sim_ppc_r13_regnum,
+ sim_ppc_r14_regnum,
+ sim_ppc_r15_regnum,
+ sim_ppc_r16_regnum,
+ sim_ppc_r17_regnum,
+ sim_ppc_r18_regnum,
+ sim_ppc_r19_regnum,
+ sim_ppc_r20_regnum,
+ sim_ppc_r21_regnum,
+ sim_ppc_r22_regnum,
+ sim_ppc_r23_regnum,
+ sim_ppc_r24_regnum,
+ sim_ppc_r25_regnum,
+ sim_ppc_r26_regnum,
+ sim_ppc_r27_regnum,
+ sim_ppc_r28_regnum,
+ sim_ppc_r29_regnum,
+ sim_ppc_r30_regnum,
+ sim_ppc_r31_regnum,
+
+ /* Floating-point registers, f0 -- f31. */
+ sim_ppc_f0_regnum,
+ sim_ppc_f1_regnum,
+ sim_ppc_f2_regnum,
+ sim_ppc_f3_regnum,
+ sim_ppc_f4_regnum,
+ sim_ppc_f5_regnum,
+ sim_ppc_f6_regnum,
+ sim_ppc_f7_regnum,
+ sim_ppc_f8_regnum,
+ sim_ppc_f9_regnum,
+ sim_ppc_f10_regnum,
+ sim_ppc_f11_regnum,
+ sim_ppc_f12_regnum,
+ sim_ppc_f13_regnum,
+ sim_ppc_f14_regnum,
+ sim_ppc_f15_regnum,
+ sim_ppc_f16_regnum,
+ sim_ppc_f17_regnum,
+ sim_ppc_f18_regnum,
+ sim_ppc_f19_regnum,
+ sim_ppc_f20_regnum,
+ sim_ppc_f21_regnum,
+ sim_ppc_f22_regnum,
+ sim_ppc_f23_regnum,
+ sim_ppc_f24_regnum,
+ sim_ppc_f25_regnum,
+ sim_ppc_f26_regnum,
+ sim_ppc_f27_regnum,
+ sim_ppc_f28_regnum,
+ sim_ppc_f29_regnum,
+ sim_ppc_f30_regnum,
+ sim_ppc_f31_regnum,
+
+ /* Altivec vector registers, vr0 -- vr31. */
+ sim_ppc_vr0_regnum,
+ sim_ppc_vr1_regnum,
+ sim_ppc_vr2_regnum,
+ sim_ppc_vr3_regnum,
+ sim_ppc_vr4_regnum,
+ sim_ppc_vr5_regnum,
+ sim_ppc_vr6_regnum,
+ sim_ppc_vr7_regnum,
+ sim_ppc_vr8_regnum,
+ sim_ppc_vr9_regnum,
+ sim_ppc_vr10_regnum,
+ sim_ppc_vr11_regnum,
+ sim_ppc_vr12_regnum,
+ sim_ppc_vr13_regnum,
+ sim_ppc_vr14_regnum,
+ sim_ppc_vr15_regnum,
+ sim_ppc_vr16_regnum,
+ sim_ppc_vr17_regnum,
+ sim_ppc_vr18_regnum,
+ sim_ppc_vr19_regnum,
+ sim_ppc_vr20_regnum,
+ sim_ppc_vr21_regnum,
+ sim_ppc_vr22_regnum,
+ sim_ppc_vr23_regnum,
+ sim_ppc_vr24_regnum,
+ sim_ppc_vr25_regnum,
+ sim_ppc_vr26_regnum,
+ sim_ppc_vr27_regnum,
+ sim_ppc_vr28_regnum,
+ sim_ppc_vr29_regnum,
+ sim_ppc_vr30_regnum,
+ sim_ppc_vr31_regnum,
+
+ /* SPE APU GPR upper halves. These are the upper 32 bits of the
+ gprs; there is one upper-half register for each gpr, so it is
+ appropriate to use sim_ppc_num_gprs for iterating through
+ these. */
+ sim_ppc_rh0_regnum,
+ sim_ppc_rh1_regnum,
+ sim_ppc_rh2_regnum,
+ sim_ppc_rh3_regnum,
+ sim_ppc_rh4_regnum,
+ sim_ppc_rh5_regnum,
+ sim_ppc_rh6_regnum,
+ sim_ppc_rh7_regnum,
+ sim_ppc_rh8_regnum,
+ sim_ppc_rh9_regnum,
+ sim_ppc_rh10_regnum,
+ sim_ppc_rh11_regnum,
+ sim_ppc_rh12_regnum,
+ sim_ppc_rh13_regnum,
+ sim_ppc_rh14_regnum,
+ sim_ppc_rh15_regnum,
+ sim_ppc_rh16_regnum,
+ sim_ppc_rh17_regnum,
+ sim_ppc_rh18_regnum,
+ sim_ppc_rh19_regnum,
+ sim_ppc_rh20_regnum,
+ sim_ppc_rh21_regnum,
+ sim_ppc_rh22_regnum,
+ sim_ppc_rh23_regnum,
+ sim_ppc_rh24_regnum,
+ sim_ppc_rh25_regnum,
+ sim_ppc_rh26_regnum,
+ sim_ppc_rh27_regnum,
+ sim_ppc_rh28_regnum,
+ sim_ppc_rh29_regnum,
+ sim_ppc_rh30_regnum,
+ sim_ppc_rh31_regnum,
+
+ /* SPE APU GPR full registers. Each of these registers is the
+ 64-bit concatenation of a 32-bit GPR (providing the lower bits)
+ and a 32-bit upper-half register (providing the higher bits).
+ As for the upper-half registers, it is appropriate to use
+ sim_ppc_num_gprs with these. */
+ sim_ppc_ev0_regnum,
+ sim_ppc_ev1_regnum,
+ sim_ppc_ev2_regnum,
+ sim_ppc_ev3_regnum,
+ sim_ppc_ev4_regnum,
+ sim_ppc_ev5_regnum,
+ sim_ppc_ev6_regnum,
+ sim_ppc_ev7_regnum,
+ sim_ppc_ev8_regnum,
+ sim_ppc_ev9_regnum,
+ sim_ppc_ev10_regnum,
+ sim_ppc_ev11_regnum,
+ sim_ppc_ev12_regnum,
+ sim_ppc_ev13_regnum,
+ sim_ppc_ev14_regnum,
+ sim_ppc_ev15_regnum,
+ sim_ppc_ev16_regnum,
+ sim_ppc_ev17_regnum,
+ sim_ppc_ev18_regnum,
+ sim_ppc_ev19_regnum,
+ sim_ppc_ev20_regnum,
+ sim_ppc_ev21_regnum,
+ sim_ppc_ev22_regnum,
+ sim_ppc_ev23_regnum,
+ sim_ppc_ev24_regnum,
+ sim_ppc_ev25_regnum,
+ sim_ppc_ev26_regnum,
+ sim_ppc_ev27_regnum,
+ sim_ppc_ev28_regnum,
+ sim_ppc_ev29_regnum,
+ sim_ppc_ev30_regnum,
+ sim_ppc_ev31_regnum,
+
+ /* Segment registers, sr0 -- sr15. */
+ sim_ppc_sr0_regnum,
+ sim_ppc_sr1_regnum,
+ sim_ppc_sr2_regnum,
+ sim_ppc_sr3_regnum,
+ sim_ppc_sr4_regnum,
+ sim_ppc_sr5_regnum,
+ sim_ppc_sr6_regnum,
+ sim_ppc_sr7_regnum,
+ sim_ppc_sr8_regnum,
+ sim_ppc_sr9_regnum,
+ sim_ppc_sr10_regnum,
+ sim_ppc_sr11_regnum,
+ sim_ppc_sr12_regnum,
+ sim_ppc_sr13_regnum,
+ sim_ppc_sr14_regnum,
+ sim_ppc_sr15_regnum,
+
+ /* Miscellaneous --- but non-SPR --- registers. */
+ sim_ppc_pc_regnum,
+ sim_ppc_ps_regnum,
+ sim_ppc_cr_regnum,
+ sim_ppc_fpscr_regnum,
+ sim_ppc_acc_regnum,
+ sim_ppc_vscr_regnum,
+
+ /* Special-purpose registers. */
+ sim_ppc_spr0_regnum, sim_ppc_spr1_regnum,
+ sim_ppc_spr2_regnum, sim_ppc_spr3_regnum,
+ sim_ppc_spr4_regnum, sim_ppc_spr5_regnum,
+ sim_ppc_spr6_regnum, sim_ppc_spr7_regnum,
+ sim_ppc_spr8_regnum, sim_ppc_spr9_regnum,
+ sim_ppc_spr10_regnum, sim_ppc_spr11_regnum,
+ sim_ppc_spr12_regnum, sim_ppc_spr13_regnum,
+ sim_ppc_spr14_regnum, sim_ppc_spr15_regnum,
+ sim_ppc_spr16_regnum, sim_ppc_spr17_regnum,
+ sim_ppc_spr18_regnum, sim_ppc_spr19_regnum,
+ sim_ppc_spr20_regnum, sim_ppc_spr21_regnum,
+ sim_ppc_spr22_regnum, sim_ppc_spr23_regnum,
+ sim_ppc_spr24_regnum, sim_ppc_spr25_regnum,
+ sim_ppc_spr26_regnum, sim_ppc_spr27_regnum,
+ sim_ppc_spr28_regnum, sim_ppc_spr29_regnum,
+ sim_ppc_spr30_regnum, sim_ppc_spr31_regnum,
+ sim_ppc_spr32_regnum, sim_ppc_spr33_regnum,
+ sim_ppc_spr34_regnum, sim_ppc_spr35_regnum,
+ sim_ppc_spr36_regnum, sim_ppc_spr37_regnum,
+ sim_ppc_spr38_regnum, sim_ppc_spr39_regnum,
+ sim_ppc_spr40_regnum, sim_ppc_spr41_regnum,
+ sim_ppc_spr42_regnum, sim_ppc_spr43_regnum,
+ sim_ppc_spr44_regnum, sim_ppc_spr45_regnum,
+ sim_ppc_spr46_regnum, sim_ppc_spr47_regnum,
+ sim_ppc_spr48_regnum, sim_ppc_spr49_regnum,
+ sim_ppc_spr50_regnum, sim_ppc_spr51_regnum,
+ sim_ppc_spr52_regnum, sim_ppc_spr53_regnum,
+ sim_ppc_spr54_regnum, sim_ppc_spr55_regnum,
+ sim_ppc_spr56_regnum, sim_ppc_spr57_regnum,
+ sim_ppc_spr58_regnum, sim_ppc_spr59_regnum,
+ sim_ppc_spr60_regnum, sim_ppc_spr61_regnum,
+ sim_ppc_spr62_regnum, sim_ppc_spr63_regnum,
+ sim_ppc_spr64_regnum, sim_ppc_spr65_regnum,
+ sim_ppc_spr66_regnum, sim_ppc_spr67_regnum,
+ sim_ppc_spr68_regnum, sim_ppc_spr69_regnum,
+ sim_ppc_spr70_regnum, sim_ppc_spr71_regnum,
+ sim_ppc_spr72_regnum, sim_ppc_spr73_regnum,
+ sim_ppc_spr74_regnum, sim_ppc_spr75_regnum,
+ sim_ppc_spr76_regnum, sim_ppc_spr77_regnum,
+ sim_ppc_spr78_regnum, sim_ppc_spr79_regnum,
+ sim_ppc_spr80_regnum, sim_ppc_spr81_regnum,
+ sim_ppc_spr82_regnum, sim_ppc_spr83_regnum,
+ sim_ppc_spr84_regnum, sim_ppc_spr85_regnum,
+ sim_ppc_spr86_regnum, sim_ppc_spr87_regnum,
+ sim_ppc_spr88_regnum, sim_ppc_spr89_regnum,
+ sim_ppc_spr90_regnum, sim_ppc_spr91_regnum,
+ sim_ppc_spr92_regnum, sim_ppc_spr93_regnum,
+ sim_ppc_spr94_regnum, sim_ppc_spr95_regnum,
+ sim_ppc_spr96_regnum, sim_ppc_spr97_regnum,
+ sim_ppc_spr98_regnum, sim_ppc_spr99_regnum,
+ sim_ppc_spr100_regnum, sim_ppc_spr101_regnum,
+ sim_ppc_spr102_regnum, sim_ppc_spr103_regnum,
+ sim_ppc_spr104_regnum, sim_ppc_spr105_regnum,
+ sim_ppc_spr106_regnum, sim_ppc_spr107_regnum,
+ sim_ppc_spr108_regnum, sim_ppc_spr109_regnum,
+ sim_ppc_spr110_regnum, sim_ppc_spr111_regnum,
+ sim_ppc_spr112_regnum, sim_ppc_spr113_regnum,
+ sim_ppc_spr114_regnum, sim_ppc_spr115_regnum,
+ sim_ppc_spr116_regnum, sim_ppc_spr117_regnum,
+ sim_ppc_spr118_regnum, sim_ppc_spr119_regnum,
+ sim_ppc_spr120_regnum, sim_ppc_spr121_regnum,
+ sim_ppc_spr122_regnum, sim_ppc_spr123_regnum,
+ sim_ppc_spr124_regnum, sim_ppc_spr125_regnum,
+ sim_ppc_spr126_regnum, sim_ppc_spr127_regnum,
+ sim_ppc_spr128_regnum, sim_ppc_spr129_regnum,
+ sim_ppc_spr130_regnum, sim_ppc_spr131_regnum,
+ sim_ppc_spr132_regnum, sim_ppc_spr133_regnum,
+ sim_ppc_spr134_regnum, sim_ppc_spr135_regnum,
+ sim_ppc_spr136_regnum, sim_ppc_spr137_regnum,
+ sim_ppc_spr138_regnum, sim_ppc_spr139_regnum,
+ sim_ppc_spr140_regnum, sim_ppc_spr141_regnum,
+ sim_ppc_spr142_regnum, sim_ppc_spr143_regnum,
+ sim_ppc_spr144_regnum, sim_ppc_spr145_regnum,
+ sim_ppc_spr146_regnum, sim_ppc_spr147_regnum,
+ sim_ppc_spr148_regnum, sim_ppc_spr149_regnum,
+ sim_ppc_spr150_regnum, sim_ppc_spr151_regnum,
+ sim_ppc_spr152_regnum, sim_ppc_spr153_regnum,
+ sim_ppc_spr154_regnum, sim_ppc_spr155_regnum,
+ sim_ppc_spr156_regnum, sim_ppc_spr157_regnum,
+ sim_ppc_spr158_regnum, sim_ppc_spr159_regnum,
+ sim_ppc_spr160_regnum, sim_ppc_spr161_regnum,
+ sim_ppc_spr162_regnum, sim_ppc_spr163_regnum,
+ sim_ppc_spr164_regnum, sim_ppc_spr165_regnum,
+ sim_ppc_spr166_regnum, sim_ppc_spr167_regnum,
+ sim_ppc_spr168_regnum, sim_ppc_spr169_regnum,
+ sim_ppc_spr170_regnum, sim_ppc_spr171_regnum,
+ sim_ppc_spr172_regnum, sim_ppc_spr173_regnum,
+ sim_ppc_spr174_regnum, sim_ppc_spr175_regnum,
+ sim_ppc_spr176_regnum, sim_ppc_spr177_regnum,
+ sim_ppc_spr178_regnum, sim_ppc_spr179_regnum,
+ sim_ppc_spr180_regnum, sim_ppc_spr181_regnum,
+ sim_ppc_spr182_regnum, sim_ppc_spr183_regnum,
+ sim_ppc_spr184_regnum, sim_ppc_spr185_regnum,
+ sim_ppc_spr186_regnum, sim_ppc_spr187_regnum,
+ sim_ppc_spr188_regnum, sim_ppc_spr189_regnum,
+ sim_ppc_spr190_regnum, sim_ppc_spr191_regnum,
+ sim_ppc_spr192_regnum, sim_ppc_spr193_regnum,
+ sim_ppc_spr194_regnum, sim_ppc_spr195_regnum,
+ sim_ppc_spr196_regnum, sim_ppc_spr197_regnum,
+ sim_ppc_spr198_regnum, sim_ppc_spr199_regnum,
+ sim_ppc_spr200_regnum, sim_ppc_spr201_regnum,
+ sim_ppc_spr202_regnum, sim_ppc_spr203_regnum,
+ sim_ppc_spr204_regnum, sim_ppc_spr205_regnum,
+ sim_ppc_spr206_regnum, sim_ppc_spr207_regnum,
+ sim_ppc_spr208_regnum, sim_ppc_spr209_regnum,
+ sim_ppc_spr210_regnum, sim_ppc_spr211_regnum,
+ sim_ppc_spr212_regnum, sim_ppc_spr213_regnum,
+ sim_ppc_spr214_regnum, sim_ppc_spr215_regnum,
+ sim_ppc_spr216_regnum, sim_ppc_spr217_regnum,
+ sim_ppc_spr218_regnum, sim_ppc_spr219_regnum,
+ sim_ppc_spr220_regnum, sim_ppc_spr221_regnum,
+ sim_ppc_spr222_regnum, sim_ppc_spr223_regnum,
+ sim_ppc_spr224_regnum, sim_ppc_spr225_regnum,
+ sim_ppc_spr226_regnum, sim_ppc_spr227_regnum,
+ sim_ppc_spr228_regnum, sim_ppc_spr229_regnum,
+ sim_ppc_spr230_regnum, sim_ppc_spr231_regnum,
+ sim_ppc_spr232_regnum, sim_ppc_spr233_regnum,
+ sim_ppc_spr234_regnum, sim_ppc_spr235_regnum,
+ sim_ppc_spr236_regnum, sim_ppc_spr237_regnum,
+ sim_ppc_spr238_regnum, sim_ppc_spr239_regnum,
+ sim_ppc_spr240_regnum, sim_ppc_spr241_regnum,
+ sim_ppc_spr242_regnum, sim_ppc_spr243_regnum,
+ sim_ppc_spr244_regnum, sim_ppc_spr245_regnum,
+ sim_ppc_spr246_regnum, sim_ppc_spr247_regnum,
+ sim_ppc_spr248_regnum, sim_ppc_spr249_regnum,
+ sim_ppc_spr250_regnum, sim_ppc_spr251_regnum,
+ sim_ppc_spr252_regnum, sim_ppc_spr253_regnum,
+ sim_ppc_spr254_regnum, sim_ppc_spr255_regnum,
+ sim_ppc_spr256_regnum, sim_ppc_spr257_regnum,
+ sim_ppc_spr258_regnum, sim_ppc_spr259_regnum,
+ sim_ppc_spr260_regnum, sim_ppc_spr261_regnum,
+ sim_ppc_spr262_regnum, sim_ppc_spr263_regnum,
+ sim_ppc_spr264_regnum, sim_ppc_spr265_regnum,
+ sim_ppc_spr266_regnum, sim_ppc_spr267_regnum,
+ sim_ppc_spr268_regnum, sim_ppc_spr269_regnum,
+ sim_ppc_spr270_regnum, sim_ppc_spr271_regnum,
+ sim_ppc_spr272_regnum, sim_ppc_spr273_regnum,
+ sim_ppc_spr274_regnum, sim_ppc_spr275_regnum,
+ sim_ppc_spr276_regnum, sim_ppc_spr277_regnum,
+ sim_ppc_spr278_regnum, sim_ppc_spr279_regnum,
+ sim_ppc_spr280_regnum, sim_ppc_spr281_regnum,
+ sim_ppc_spr282_regnum, sim_ppc_spr283_regnum,
+ sim_ppc_spr284_regnum, sim_ppc_spr285_regnum,
+ sim_ppc_spr286_regnum, sim_ppc_spr287_regnum,
+ sim_ppc_spr288_regnum, sim_ppc_spr289_regnum,
+ sim_ppc_spr290_regnum, sim_ppc_spr291_regnum,
+ sim_ppc_spr292_regnum, sim_ppc_spr293_regnum,
+ sim_ppc_spr294_regnum, sim_ppc_spr295_regnum,
+ sim_ppc_spr296_regnum, sim_ppc_spr297_regnum,
+ sim_ppc_spr298_regnum, sim_ppc_spr299_regnum,
+ sim_ppc_spr300_regnum, sim_ppc_spr301_regnum,
+ sim_ppc_spr302_regnum, sim_ppc_spr303_regnum,
+ sim_ppc_spr304_regnum, sim_ppc_spr305_regnum,
+ sim_ppc_spr306_regnum, sim_ppc_spr307_regnum,
+ sim_ppc_spr308_regnum, sim_ppc_spr309_regnum,
+ sim_ppc_spr310_regnum, sim_ppc_spr311_regnum,
+ sim_ppc_spr312_regnum, sim_ppc_spr313_regnum,
+ sim_ppc_spr314_regnum, sim_ppc_spr315_regnum,
+ sim_ppc_spr316_regnum, sim_ppc_spr317_regnum,
+ sim_ppc_spr318_regnum, sim_ppc_spr319_regnum,
+ sim_ppc_spr320_regnum, sim_ppc_spr321_regnum,
+ sim_ppc_spr322_regnum, sim_ppc_spr323_regnum,
+ sim_ppc_spr324_regnum, sim_ppc_spr325_regnum,
+ sim_ppc_spr326_regnum, sim_ppc_spr327_regnum,
+ sim_ppc_spr328_regnum, sim_ppc_spr329_regnum,
+ sim_ppc_spr330_regnum, sim_ppc_spr331_regnum,
+ sim_ppc_spr332_regnum, sim_ppc_spr333_regnum,
+ sim_ppc_spr334_regnum, sim_ppc_spr335_regnum,
+ sim_ppc_spr336_regnum, sim_ppc_spr337_regnum,
+ sim_ppc_spr338_regnum, sim_ppc_spr339_regnum,
+ sim_ppc_spr340_regnum, sim_ppc_spr341_regnum,
+ sim_ppc_spr342_regnum, sim_ppc_spr343_regnum,
+ sim_ppc_spr344_regnum, sim_ppc_spr345_regnum,
+ sim_ppc_spr346_regnum, sim_ppc_spr347_regnum,
+ sim_ppc_spr348_regnum, sim_ppc_spr349_regnum,
+ sim_ppc_spr350_regnum, sim_ppc_spr351_regnum,
+ sim_ppc_spr352_regnum, sim_ppc_spr353_regnum,
+ sim_ppc_spr354_regnum, sim_ppc_spr355_regnum,
+ sim_ppc_spr356_regnum, sim_ppc_spr357_regnum,
+ sim_ppc_spr358_regnum, sim_ppc_spr359_regnum,
+ sim_ppc_spr360_regnum, sim_ppc_spr361_regnum,
+ sim_ppc_spr362_regnum, sim_ppc_spr363_regnum,
+ sim_ppc_spr364_regnum, sim_ppc_spr365_regnum,
+ sim_ppc_spr366_regnum, sim_ppc_spr367_regnum,
+ sim_ppc_spr368_regnum, sim_ppc_spr369_regnum,
+ sim_ppc_spr370_regnum, sim_ppc_spr371_regnum,
+ sim_ppc_spr372_regnum, sim_ppc_spr373_regnum,
+ sim_ppc_spr374_regnum, sim_ppc_spr375_regnum,
+ sim_ppc_spr376_regnum, sim_ppc_spr377_regnum,
+ sim_ppc_spr378_regnum, sim_ppc_spr379_regnum,
+ sim_ppc_spr380_regnum, sim_ppc_spr381_regnum,
+ sim_ppc_spr382_regnum, sim_ppc_spr383_regnum,
+ sim_ppc_spr384_regnum, sim_ppc_spr385_regnum,
+ sim_ppc_spr386_regnum, sim_ppc_spr387_regnum,
+ sim_ppc_spr388_regnum, sim_ppc_spr389_regnum,
+ sim_ppc_spr390_regnum, sim_ppc_spr391_regnum,
+ sim_ppc_spr392_regnum, sim_ppc_spr393_regnum,
+ sim_ppc_spr394_regnum, sim_ppc_spr395_regnum,
+ sim_ppc_spr396_regnum, sim_ppc_spr397_regnum,
+ sim_ppc_spr398_regnum, sim_ppc_spr399_regnum,
+ sim_ppc_spr400_regnum, sim_ppc_spr401_regnum,
+ sim_ppc_spr402_regnum, sim_ppc_spr403_regnum,
+ sim_ppc_spr404_regnum, sim_ppc_spr405_regnum,
+ sim_ppc_spr406_regnum, sim_ppc_spr407_regnum,
+ sim_ppc_spr408_regnum, sim_ppc_spr409_regnum,
+ sim_ppc_spr410_regnum, sim_ppc_spr411_regnum,
+ sim_ppc_spr412_regnum, sim_ppc_spr413_regnum,
+ sim_ppc_spr414_regnum, sim_ppc_spr415_regnum,
+ sim_ppc_spr416_regnum, sim_ppc_spr417_regnum,
+ sim_ppc_spr418_regnum, sim_ppc_spr419_regnum,
+ sim_ppc_spr420_regnum, sim_ppc_spr421_regnum,
+ sim_ppc_spr422_regnum, sim_ppc_spr423_regnum,
+ sim_ppc_spr424_regnum, sim_ppc_spr425_regnum,
+ sim_ppc_spr426_regnum, sim_ppc_spr427_regnum,
+ sim_ppc_spr428_regnum, sim_ppc_spr429_regnum,
+ sim_ppc_spr430_regnum, sim_ppc_spr431_regnum,
+ sim_ppc_spr432_regnum, sim_ppc_spr433_regnum,
+ sim_ppc_spr434_regnum, sim_ppc_spr435_regnum,
+ sim_ppc_spr436_regnum, sim_ppc_spr437_regnum,
+ sim_ppc_spr438_regnum, sim_ppc_spr439_regnum,
+ sim_ppc_spr440_regnum, sim_ppc_spr441_regnum,
+ sim_ppc_spr442_regnum, sim_ppc_spr443_regnum,
+ sim_ppc_spr444_regnum, sim_ppc_spr445_regnum,
+ sim_ppc_spr446_regnum, sim_ppc_spr447_regnum,
+ sim_ppc_spr448_regnum, sim_ppc_spr449_regnum,
+ sim_ppc_spr450_regnum, sim_ppc_spr451_regnum,
+ sim_ppc_spr452_regnum, sim_ppc_spr453_regnum,
+ sim_ppc_spr454_regnum, sim_ppc_spr455_regnum,
+ sim_ppc_spr456_regnum, sim_ppc_spr457_regnum,
+ sim_ppc_spr458_regnum, sim_ppc_spr459_regnum,
+ sim_ppc_spr460_regnum, sim_ppc_spr461_regnum,
+ sim_ppc_spr462_regnum, sim_ppc_spr463_regnum,
+ sim_ppc_spr464_regnum, sim_ppc_spr465_regnum,
+ sim_ppc_spr466_regnum, sim_ppc_spr467_regnum,
+ sim_ppc_spr468_regnum, sim_ppc_spr469_regnum,
+ sim_ppc_spr470_regnum, sim_ppc_spr471_regnum,
+ sim_ppc_spr472_regnum, sim_ppc_spr473_regnum,
+ sim_ppc_spr474_regnum, sim_ppc_spr475_regnum,
+ sim_ppc_spr476_regnum, sim_ppc_spr477_regnum,
+ sim_ppc_spr478_regnum, sim_ppc_spr479_regnum,
+ sim_ppc_spr480_regnum, sim_ppc_spr481_regnum,
+ sim_ppc_spr482_regnum, sim_ppc_spr483_regnum,
+ sim_ppc_spr484_regnum, sim_ppc_spr485_regnum,
+ sim_ppc_spr486_regnum, sim_ppc_spr487_regnum,
+ sim_ppc_spr488_regnum, sim_ppc_spr489_regnum,
+ sim_ppc_spr490_regnum, sim_ppc_spr491_regnum,
+ sim_ppc_spr492_regnum, sim_ppc_spr493_regnum,
+ sim_ppc_spr494_regnum, sim_ppc_spr495_regnum,
+ sim_ppc_spr496_regnum, sim_ppc_spr497_regnum,
+ sim_ppc_spr498_regnum, sim_ppc_spr499_regnum,
+ sim_ppc_spr500_regnum, sim_ppc_spr501_regnum,
+ sim_ppc_spr502_regnum, sim_ppc_spr503_regnum,
+ sim_ppc_spr504_regnum, sim_ppc_spr505_regnum,
+ sim_ppc_spr506_regnum, sim_ppc_spr507_regnum,
+ sim_ppc_spr508_regnum, sim_ppc_spr509_regnum,
+ sim_ppc_spr510_regnum, sim_ppc_spr511_regnum,
+ sim_ppc_spr512_regnum, sim_ppc_spr513_regnum,
+ sim_ppc_spr514_regnum, sim_ppc_spr515_regnum,
+ sim_ppc_spr516_regnum, sim_ppc_spr517_regnum,
+ sim_ppc_spr518_regnum, sim_ppc_spr519_regnum,
+ sim_ppc_spr520_regnum, sim_ppc_spr521_regnum,
+ sim_ppc_spr522_regnum, sim_ppc_spr523_regnum,
+ sim_ppc_spr524_regnum, sim_ppc_spr525_regnum,
+ sim_ppc_spr526_regnum, sim_ppc_spr527_regnum,
+ sim_ppc_spr528_regnum, sim_ppc_spr529_regnum,
+ sim_ppc_spr530_regnum, sim_ppc_spr531_regnum,
+ sim_ppc_spr532_regnum, sim_ppc_spr533_regnum,
+ sim_ppc_spr534_regnum, sim_ppc_spr535_regnum,
+ sim_ppc_spr536_regnum, sim_ppc_spr537_regnum,
+ sim_ppc_spr538_regnum, sim_ppc_spr539_regnum,
+ sim_ppc_spr540_regnum, sim_ppc_spr541_regnum,
+ sim_ppc_spr542_regnum, sim_ppc_spr543_regnum,
+ sim_ppc_spr544_regnum, sim_ppc_spr545_regnum,
+ sim_ppc_spr546_regnum, sim_ppc_spr547_regnum,
+ sim_ppc_spr548_regnum, sim_ppc_spr549_regnum,
+ sim_ppc_spr550_regnum, sim_ppc_spr551_regnum,
+ sim_ppc_spr552_regnum, sim_ppc_spr553_regnum,
+ sim_ppc_spr554_regnum, sim_ppc_spr555_regnum,
+ sim_ppc_spr556_regnum, sim_ppc_spr557_regnum,
+ sim_ppc_spr558_regnum, sim_ppc_spr559_regnum,
+ sim_ppc_spr560_regnum, sim_ppc_spr561_regnum,
+ sim_ppc_spr562_regnum, sim_ppc_spr563_regnum,
+ sim_ppc_spr564_regnum, sim_ppc_spr565_regnum,
+ sim_ppc_spr566_regnum, sim_ppc_spr567_regnum,
+ sim_ppc_spr568_regnum, sim_ppc_spr569_regnum,
+ sim_ppc_spr570_regnum, sim_ppc_spr571_regnum,
+ sim_ppc_spr572_regnum, sim_ppc_spr573_regnum,
+ sim_ppc_spr574_regnum, sim_ppc_spr575_regnum,
+ sim_ppc_spr576_regnum, sim_ppc_spr577_regnum,
+ sim_ppc_spr578_regnum, sim_ppc_spr579_regnum,
+ sim_ppc_spr580_regnum, sim_ppc_spr581_regnum,
+ sim_ppc_spr582_regnum, sim_ppc_spr583_regnum,
+ sim_ppc_spr584_regnum, sim_ppc_spr585_regnum,
+ sim_ppc_spr586_regnum, sim_ppc_spr587_regnum,
+ sim_ppc_spr588_regnum, sim_ppc_spr589_regnum,
+ sim_ppc_spr590_regnum, sim_ppc_spr591_regnum,
+ sim_ppc_spr592_regnum, sim_ppc_spr593_regnum,
+ sim_ppc_spr594_regnum, sim_ppc_spr595_regnum,
+ sim_ppc_spr596_regnum, sim_ppc_spr597_regnum,
+ sim_ppc_spr598_regnum, sim_ppc_spr599_regnum,
+ sim_ppc_spr600_regnum, sim_ppc_spr601_regnum,
+ sim_ppc_spr602_regnum, sim_ppc_spr603_regnum,
+ sim_ppc_spr604_regnum, sim_ppc_spr605_regnum,
+ sim_ppc_spr606_regnum, sim_ppc_spr607_regnum,
+ sim_ppc_spr608_regnum, sim_ppc_spr609_regnum,
+ sim_ppc_spr610_regnum, sim_ppc_spr611_regnum,
+ sim_ppc_spr612_regnum, sim_ppc_spr613_regnum,
+ sim_ppc_spr614_regnum, sim_ppc_spr615_regnum,
+ sim_ppc_spr616_regnum, sim_ppc_spr617_regnum,
+ sim_ppc_spr618_regnum, sim_ppc_spr619_regnum,
+ sim_ppc_spr620_regnum, sim_ppc_spr621_regnum,
+ sim_ppc_spr622_regnum, sim_ppc_spr623_regnum,
+ sim_ppc_spr624_regnum, sim_ppc_spr625_regnum,
+ sim_ppc_spr626_regnum, sim_ppc_spr627_regnum,
+ sim_ppc_spr628_regnum, sim_ppc_spr629_regnum,
+ sim_ppc_spr630_regnum, sim_ppc_spr631_regnum,
+ sim_ppc_spr632_regnum, sim_ppc_spr633_regnum,
+ sim_ppc_spr634_regnum, sim_ppc_spr635_regnum,
+ sim_ppc_spr636_regnum, sim_ppc_spr637_regnum,
+ sim_ppc_spr638_regnum, sim_ppc_spr639_regnum,
+ sim_ppc_spr640_regnum, sim_ppc_spr641_regnum,
+ sim_ppc_spr642_regnum, sim_ppc_spr643_regnum,
+ sim_ppc_spr644_regnum, sim_ppc_spr645_regnum,
+ sim_ppc_spr646_regnum, sim_ppc_spr647_regnum,
+ sim_ppc_spr648_regnum, sim_ppc_spr649_regnum,
+ sim_ppc_spr650_regnum, sim_ppc_spr651_regnum,
+ sim_ppc_spr652_regnum, sim_ppc_spr653_regnum,
+ sim_ppc_spr654_regnum, sim_ppc_spr655_regnum,
+ sim_ppc_spr656_regnum, sim_ppc_spr657_regnum,
+ sim_ppc_spr658_regnum, sim_ppc_spr659_regnum,
+ sim_ppc_spr660_regnum, sim_ppc_spr661_regnum,
+ sim_ppc_spr662_regnum, sim_ppc_spr663_regnum,
+ sim_ppc_spr664_regnum, sim_ppc_spr665_regnum,
+ sim_ppc_spr666_regnum, sim_ppc_spr667_regnum,
+ sim_ppc_spr668_regnum, sim_ppc_spr669_regnum,
+ sim_ppc_spr670_regnum, sim_ppc_spr671_regnum,
+ sim_ppc_spr672_regnum, sim_ppc_spr673_regnum,
+ sim_ppc_spr674_regnum, sim_ppc_spr675_regnum,
+ sim_ppc_spr676_regnum, sim_ppc_spr677_regnum,
+ sim_ppc_spr678_regnum, sim_ppc_spr679_regnum,
+ sim_ppc_spr680_regnum, sim_ppc_spr681_regnum,
+ sim_ppc_spr682_regnum, sim_ppc_spr683_regnum,
+ sim_ppc_spr684_regnum, sim_ppc_spr685_regnum,
+ sim_ppc_spr686_regnum, sim_ppc_spr687_regnum,
+ sim_ppc_spr688_regnum, sim_ppc_spr689_regnum,
+ sim_ppc_spr690_regnum, sim_ppc_spr691_regnum,
+ sim_ppc_spr692_regnum, sim_ppc_spr693_regnum,
+ sim_ppc_spr694_regnum, sim_ppc_spr695_regnum,
+ sim_ppc_spr696_regnum, sim_ppc_spr697_regnum,
+ sim_ppc_spr698_regnum, sim_ppc_spr699_regnum,
+ sim_ppc_spr700_regnum, sim_ppc_spr701_regnum,
+ sim_ppc_spr702_regnum, sim_ppc_spr703_regnum,
+ sim_ppc_spr704_regnum, sim_ppc_spr705_regnum,
+ sim_ppc_spr706_regnum, sim_ppc_spr707_regnum,
+ sim_ppc_spr708_regnum, sim_ppc_spr709_regnum,
+ sim_ppc_spr710_regnum, sim_ppc_spr711_regnum,
+ sim_ppc_spr712_regnum, sim_ppc_spr713_regnum,
+ sim_ppc_spr714_regnum, sim_ppc_spr715_regnum,
+ sim_ppc_spr716_regnum, sim_ppc_spr717_regnum,
+ sim_ppc_spr718_regnum, sim_ppc_spr719_regnum,
+ sim_ppc_spr720_regnum, sim_ppc_spr721_regnum,
+ sim_ppc_spr722_regnum, sim_ppc_spr723_regnum,
+ sim_ppc_spr724_regnum, sim_ppc_spr725_regnum,
+ sim_ppc_spr726_regnum, sim_ppc_spr727_regnum,
+ sim_ppc_spr728_regnum, sim_ppc_spr729_regnum,
+ sim_ppc_spr730_regnum, sim_ppc_spr731_regnum,
+ sim_ppc_spr732_regnum, sim_ppc_spr733_regnum,
+ sim_ppc_spr734_regnum, sim_ppc_spr735_regnum,
+ sim_ppc_spr736_regnum, sim_ppc_spr737_regnum,
+ sim_ppc_spr738_regnum, sim_ppc_spr739_regnum,
+ sim_ppc_spr740_regnum, sim_ppc_spr741_regnum,
+ sim_ppc_spr742_regnum, sim_ppc_spr743_regnum,
+ sim_ppc_spr744_regnum, sim_ppc_spr745_regnum,
+ sim_ppc_spr746_regnum, sim_ppc_spr747_regnum,
+ sim_ppc_spr748_regnum, sim_ppc_spr749_regnum,
+ sim_ppc_spr750_regnum, sim_ppc_spr751_regnum,
+ sim_ppc_spr752_regnum, sim_ppc_spr753_regnum,
+ sim_ppc_spr754_regnum, sim_ppc_spr755_regnum,
+ sim_ppc_spr756_regnum, sim_ppc_spr757_regnum,
+ sim_ppc_spr758_regnum, sim_ppc_spr759_regnum,
+ sim_ppc_spr760_regnum, sim_ppc_spr761_regnum,
+ sim_ppc_spr762_regnum, sim_ppc_spr763_regnum,
+ sim_ppc_spr764_regnum, sim_ppc_spr765_regnum,
+ sim_ppc_spr766_regnum, sim_ppc_spr767_regnum,
+ sim_ppc_spr768_regnum, sim_ppc_spr769_regnum,
+ sim_ppc_spr770_regnum, sim_ppc_spr771_regnum,
+ sim_ppc_spr772_regnum, sim_ppc_spr773_regnum,
+ sim_ppc_spr774_regnum, sim_ppc_spr775_regnum,
+ sim_ppc_spr776_regnum, sim_ppc_spr777_regnum,
+ sim_ppc_spr778_regnum, sim_ppc_spr779_regnum,
+ sim_ppc_spr780_regnum, sim_ppc_spr781_regnum,
+ sim_ppc_spr782_regnum, sim_ppc_spr783_regnum,
+ sim_ppc_spr784_regnum, sim_ppc_spr785_regnum,
+ sim_ppc_spr786_regnum, sim_ppc_spr787_regnum,
+ sim_ppc_spr788_regnum, sim_ppc_spr789_regnum,
+ sim_ppc_spr790_regnum, sim_ppc_spr791_regnum,
+ sim_ppc_spr792_regnum, sim_ppc_spr793_regnum,
+ sim_ppc_spr794_regnum, sim_ppc_spr795_regnum,
+ sim_ppc_spr796_regnum, sim_ppc_spr797_regnum,
+ sim_ppc_spr798_regnum, sim_ppc_spr799_regnum,
+ sim_ppc_spr800_regnum, sim_ppc_spr801_regnum,
+ sim_ppc_spr802_regnum, sim_ppc_spr803_regnum,
+ sim_ppc_spr804_regnum, sim_ppc_spr805_regnum,
+ sim_ppc_spr806_regnum, sim_ppc_spr807_regnum,
+ sim_ppc_spr808_regnum, sim_ppc_spr809_regnum,
+ sim_ppc_spr810_regnum, sim_ppc_spr811_regnum,
+ sim_ppc_spr812_regnum, sim_ppc_spr813_regnum,
+ sim_ppc_spr814_regnum, sim_ppc_spr815_regnum,
+ sim_ppc_spr816_regnum, sim_ppc_spr817_regnum,
+ sim_ppc_spr818_regnum, sim_ppc_spr819_regnum,
+ sim_ppc_spr820_regnum, sim_ppc_spr821_regnum,
+ sim_ppc_spr822_regnum, sim_ppc_spr823_regnum,
+ sim_ppc_spr824_regnum, sim_ppc_spr825_regnum,
+ sim_ppc_spr826_regnum, sim_ppc_spr827_regnum,
+ sim_ppc_spr828_regnum, sim_ppc_spr829_regnum,
+ sim_ppc_spr830_regnum, sim_ppc_spr831_regnum,
+ sim_ppc_spr832_regnum, sim_ppc_spr833_regnum,
+ sim_ppc_spr834_regnum, sim_ppc_spr835_regnum,
+ sim_ppc_spr836_regnum, sim_ppc_spr837_regnum,
+ sim_ppc_spr838_regnum, sim_ppc_spr839_regnum,
+ sim_ppc_spr840_regnum, sim_ppc_spr841_regnum,
+ sim_ppc_spr842_regnum, sim_ppc_spr843_regnum,
+ sim_ppc_spr844_regnum, sim_ppc_spr845_regnum,
+ sim_ppc_spr846_regnum, sim_ppc_spr847_regnum,
+ sim_ppc_spr848_regnum, sim_ppc_spr849_regnum,
+ sim_ppc_spr850_regnum, sim_ppc_spr851_regnum,
+ sim_ppc_spr852_regnum, sim_ppc_spr853_regnum,
+ sim_ppc_spr854_regnum, sim_ppc_spr855_regnum,
+ sim_ppc_spr856_regnum, sim_ppc_spr857_regnum,
+ sim_ppc_spr858_regnum, sim_ppc_spr859_regnum,
+ sim_ppc_spr860_regnum, sim_ppc_spr861_regnum,
+ sim_ppc_spr862_regnum, sim_ppc_spr863_regnum,
+ sim_ppc_spr864_regnum, sim_ppc_spr865_regnum,
+ sim_ppc_spr866_regnum, sim_ppc_spr867_regnum,
+ sim_ppc_spr868_regnum, sim_ppc_spr869_regnum,
+ sim_ppc_spr870_regnum, sim_ppc_spr871_regnum,
+ sim_ppc_spr872_regnum, sim_ppc_spr873_regnum,
+ sim_ppc_spr874_regnum, sim_ppc_spr875_regnum,
+ sim_ppc_spr876_regnum, sim_ppc_spr877_regnum,
+ sim_ppc_spr878_regnum, sim_ppc_spr879_regnum,
+ sim_ppc_spr880_regnum, sim_ppc_spr881_regnum,
+ sim_ppc_spr882_regnum, sim_ppc_spr883_regnum,
+ sim_ppc_spr884_regnum, sim_ppc_spr885_regnum,
+ sim_ppc_spr886_regnum, sim_ppc_spr887_regnum,
+ sim_ppc_spr888_regnum, sim_ppc_spr889_regnum,
+ sim_ppc_spr890_regnum, sim_ppc_spr891_regnum,
+ sim_ppc_spr892_regnum, sim_ppc_spr893_regnum,
+ sim_ppc_spr894_regnum, sim_ppc_spr895_regnum,
+ sim_ppc_spr896_regnum, sim_ppc_spr897_regnum,
+ sim_ppc_spr898_regnum, sim_ppc_spr899_regnum,
+ sim_ppc_spr900_regnum, sim_ppc_spr901_regnum,
+ sim_ppc_spr902_regnum, sim_ppc_spr903_regnum,
+ sim_ppc_spr904_regnum, sim_ppc_spr905_regnum,
+ sim_ppc_spr906_regnum, sim_ppc_spr907_regnum,
+ sim_ppc_spr908_regnum, sim_ppc_spr909_regnum,
+ sim_ppc_spr910_regnum, sim_ppc_spr911_regnum,
+ sim_ppc_spr912_regnum, sim_ppc_spr913_regnum,
+ sim_ppc_spr914_regnum, sim_ppc_spr915_regnum,
+ sim_ppc_spr916_regnum, sim_ppc_spr917_regnum,
+ sim_ppc_spr918_regnum, sim_ppc_spr919_regnum,
+ sim_ppc_spr920_regnum, sim_ppc_spr921_regnum,
+ sim_ppc_spr922_regnum, sim_ppc_spr923_regnum,
+ sim_ppc_spr924_regnum, sim_ppc_spr925_regnum,
+ sim_ppc_spr926_regnum, sim_ppc_spr927_regnum,
+ sim_ppc_spr928_regnum, sim_ppc_spr929_regnum,
+ sim_ppc_spr930_regnum, sim_ppc_spr931_regnum,
+ sim_ppc_spr932_regnum, sim_ppc_spr933_regnum,
+ sim_ppc_spr934_regnum, sim_ppc_spr935_regnum,
+ sim_ppc_spr936_regnum, sim_ppc_spr937_regnum,
+ sim_ppc_spr938_regnum, sim_ppc_spr939_regnum,
+ sim_ppc_spr940_regnum, sim_ppc_spr941_regnum,
+ sim_ppc_spr942_regnum, sim_ppc_spr943_regnum,
+ sim_ppc_spr944_regnum, sim_ppc_spr945_regnum,
+ sim_ppc_spr946_regnum, sim_ppc_spr947_regnum,
+ sim_ppc_spr948_regnum, sim_ppc_spr949_regnum,
+ sim_ppc_spr950_regnum, sim_ppc_spr951_regnum,
+ sim_ppc_spr952_regnum, sim_ppc_spr953_regnum,
+ sim_ppc_spr954_regnum, sim_ppc_spr955_regnum,
+ sim_ppc_spr956_regnum, sim_ppc_spr957_regnum,
+ sim_ppc_spr958_regnum, sim_ppc_spr959_regnum,
+ sim_ppc_spr960_regnum, sim_ppc_spr961_regnum,
+ sim_ppc_spr962_regnum, sim_ppc_spr963_regnum,
+ sim_ppc_spr964_regnum, sim_ppc_spr965_regnum,
+ sim_ppc_spr966_regnum, sim_ppc_spr967_regnum,
+ sim_ppc_spr968_regnum, sim_ppc_spr969_regnum,
+ sim_ppc_spr970_regnum, sim_ppc_spr971_regnum,
+ sim_ppc_spr972_regnum, sim_ppc_spr973_regnum,
+ sim_ppc_spr974_regnum, sim_ppc_spr975_regnum,
+ sim_ppc_spr976_regnum, sim_ppc_spr977_regnum,
+ sim_ppc_spr978_regnum, sim_ppc_spr979_regnum,
+ sim_ppc_spr980_regnum, sim_ppc_spr981_regnum,
+ sim_ppc_spr982_regnum, sim_ppc_spr983_regnum,
+ sim_ppc_spr984_regnum, sim_ppc_spr985_regnum,
+ sim_ppc_spr986_regnum, sim_ppc_spr987_regnum,
+ sim_ppc_spr988_regnum, sim_ppc_spr989_regnum,
+ sim_ppc_spr990_regnum, sim_ppc_spr991_regnum,
+ sim_ppc_spr992_regnum, sim_ppc_spr993_regnum,
+ sim_ppc_spr994_regnum, sim_ppc_spr995_regnum,
+ sim_ppc_spr996_regnum, sim_ppc_spr997_regnum,
+ sim_ppc_spr998_regnum, sim_ppc_spr999_regnum,
+ sim_ppc_spr1000_regnum, sim_ppc_spr1001_regnum,
+ sim_ppc_spr1002_regnum, sim_ppc_spr1003_regnum,
+ sim_ppc_spr1004_regnum, sim_ppc_spr1005_regnum,
+ sim_ppc_spr1006_regnum, sim_ppc_spr1007_regnum,
+ sim_ppc_spr1008_regnum, sim_ppc_spr1009_regnum,
+ sim_ppc_spr1010_regnum, sim_ppc_spr1011_regnum,
+ sim_ppc_spr1012_regnum, sim_ppc_spr1013_regnum,
+ sim_ppc_spr1014_regnum, sim_ppc_spr1015_regnum,
+ sim_ppc_spr1016_regnum, sim_ppc_spr1017_regnum,
+ sim_ppc_spr1018_regnum, sim_ppc_spr1019_regnum,
+ sim_ppc_spr1020_regnum, sim_ppc_spr1021_regnum,
+ sim_ppc_spr1022_regnum, sim_ppc_spr1023_regnum
+ };
+
+
+/* Sizes of various register sets. */
+enum
+ {
+ sim_ppc_num_gprs = 32,
+ sim_ppc_num_fprs = 32,
+ sim_ppc_num_vrs = 32,
+ sim_ppc_num_srs = 16,
+ sim_ppc_num_sprs = 1024,
+ };
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SIM_PPC_H */
diff --git a/gnu/dist/binutils/include/gdb/sim-sh.h b/gnu/dist/binutils/include/gdb/sim-sh.h
index ec0d6276b4b..a40eff6311c 100644
--- a/gnu/dist/binutils/include/gdb/sim-sh.h
+++ b/gnu/dist/binutils/include/gdb/sim-sh.h
@@ -1,5 +1,5 @@
/* This file defines the interface between the sh simulator and gdb.
- Copyright (C) 2000, 2002 Free Software Foundation, Inc.
+ Copyright (C) 2000, 2002, 2004 Free Software Foundation, Inc.
This file is part of GDB.
@@ -129,8 +129,17 @@ enum
SIM_SH_R4_BANK_REGNUM,
SIM_SH_R5_BANK_REGNUM,
SIM_SH_R6_BANK_REGNUM,
- SIM_SH_R7_BANK_REGNUM
- /* 100..127: room for expansion. */
+ SIM_SH_R7_BANK_REGNUM,
+ /* 109..127: room for expansion. */
+ SIM_SH_TBR_REGNUM,
+ SIM_SH_IBNR_REGNUM,
+ SIM_SH_IBCR_REGNUM,
+ SIM_SH_BANK_REGNUM,
+ SIM_SH_BANK_MACL_REGNUM,
+ SIM_SH_BANK_GBR_REGNUM,
+ SIM_SH_BANK_PR_REGNUM,
+ SIM_SH_BANK_IVN_REGNUM,
+ SIM_SH_BANK_MACH_REGNUM
};
enum
diff --git a/gnu/dist/binutils/include/hashtab.h b/gnu/dist/binutils/include/hashtab.h
index f7bd4ae69d3..de24dedb91b 100644
--- a/gnu/dist/binutils/include/hashtab.h
+++ b/gnu/dist/binutils/include/hashtab.h
@@ -1,5 +1,5 @@
/* An expandable hash tables datatype.
- Copyright (C) 1999, 2000, 2002, 2003 Free Software Foundation, Inc.
+ Copyright (C) 1999, 2000, 2002, 2003, 2004 Free Software Foundation, Inc.
Contributed by Vladimir Makarov (vmakarov@cygnus.com).
This program is free software; you can redistribute it and/or modify
@@ -99,15 +99,15 @@ struct htab GTY(())
htab_del del_f;
/* Table itself. */
- PTR * GTY ((use_param (""), length ("%h.size"))) entries;
+ PTR * GTY ((use_param, length ("%h.size"))) entries;
- /* Current size (in entries) of the hash table */
+ /* Current size (in entries) of the hash table. */
size_t size;
- /* Current number of elements including also deleted elements */
+ /* Current number of elements including also deleted elements. */
size_t n_elements;
- /* Current number of deleted elements in the table */
+ /* Current number of deleted elements in the table. */
size_t n_deleted;
/* The following member is used for debugging. Its value is number
@@ -123,9 +123,13 @@ struct htab GTY(())
htab_free free_f;
/* Alternate allocate/free functions, which take an extra argument. */
- PTR GTY((skip (""))) alloc_arg;
+ PTR GTY((skip)) alloc_arg;
htab_alloc_with_arg alloc_with_arg_f;
htab_free_with_arg free_with_arg_f;
+
+ /* Current size (in entries) of the hash table, as an index into the
+ table of primes. */
+ unsigned int size_prime_index;
};
typedef struct htab *htab_t;
@@ -166,6 +170,7 @@ extern PTR *htab_find_slot_with_hash PARAMS ((htab_t, const void *,
enum insert_option));
extern void htab_clear_slot PARAMS ((htab_t, void **));
extern void htab_remove_elt PARAMS ((htab_t, void *));
+extern void htab_remove_elt_with_hash PARAMS ((htab_t, void *, hashval_t));
extern void htab_traverse PARAMS ((htab_t, htab_trav, void *));
extern void htab_traverse_noresize PARAMS ((htab_t, htab_trav, void *));
diff --git a/gnu/dist/binutils/include/libiberty.h b/gnu/dist/binutils/include/libiberty.h
index 761b2cf060f..4df814092c5 100644
--- a/gnu/dist/binutils/include/libiberty.h
+++ b/gnu/dist/binutils/include/libiberty.h
@@ -74,7 +74,7 @@ extern char **dupargv PARAMS ((char **)) ATTRIBUTE_MALLOC;
to find the declaration so provide a fully prototyped one. If it
is 1, we found it so don't provide any declaration at all. */
#if !HAVE_DECL_BASENAME
-#if defined (__GNU_LIBRARY__ ) || defined (__linux__) || defined (__FreeBSD__) || defined (__OpenBSD__) || defined(__NetBSD__) || defined (__CYGWIN__) || defined (__CYGWIN32__) || defined (HAVE_DECL_BASENAME)
+#if defined (__GNU_LIBRARY__ ) || defined (__linux__) || defined (__FreeBSD__) || defined (__OpenBSD__) || defined(__NetBSD__) || defined (__CYGWIN__) || defined (__CYGWIN32__) || defined (__MINGW32__) || defined (HAVE_DECL_BASENAME)
extern char *basename PARAMS ((const char *));
#else
extern char *basename ();
@@ -93,7 +93,7 @@ extern char *lrealpath PARAMS ((const char *));
the last argument of this function, to terminate the list of
strings. Allocates memory using xmalloc. */
-extern char *concat PARAMS ((const char *, ...)) ATTRIBUTE_MALLOC;
+extern char *concat PARAMS ((const char *, ...)) ATTRIBUTE_MALLOC ATTRIBUTE_SENTINEL;
/* Concatenate an arbitrary number of strings. You must pass NULL as
the last argument of this function, to terminate the list of
@@ -102,27 +102,27 @@ extern char *concat PARAMS ((const char *, ...)) ATTRIBUTE_MALLOC;
pointer to be freed after the new string is created, similar to the
way xrealloc works. */
-extern char *reconcat PARAMS ((char *, const char *, ...)) ATTRIBUTE_MALLOC;
+extern char *reconcat PARAMS ((char *, const char *, ...)) ATTRIBUTE_MALLOC ATTRIBUTE_SENTINEL;
/* Determine the length of concatenating an arbitrary number of
strings. You must pass NULL as the last argument of this function,
to terminate the list of strings. */
-extern unsigned long concat_length PARAMS ((const char *, ...));
+extern unsigned long concat_length PARAMS ((const char *, ...)) ATTRIBUTE_SENTINEL;
/* Concatenate an arbitrary number of strings into a SUPPLIED area of
memory. You must pass NULL as the last argument of this function,
to terminate the list of strings. The supplied memory is assumed
to be large enough. */
-extern char *concat_copy PARAMS ((char *, const char *, ...));
+extern char *concat_copy PARAMS ((char *, const char *, ...)) ATTRIBUTE_SENTINEL;
/* Concatenate an arbitrary number of strings into a GLOBAL area of
memory. You must pass NULL as the last argument of this function,
to terminate the list of strings. The supplied memory is assumed
to be large enough. */
-extern char *concat_copy2 PARAMS ((const char *, ...));
+extern char *concat_copy2 PARAMS ((const char *, ...)) ATTRIBUTE_SENTINEL;
/* This is the global area used by concat_copy2. */
@@ -163,6 +163,10 @@ extern char *choose_temp_base PARAMS ((void)) ATTRIBUTE_MALLOC;
extern char *make_temp_file PARAMS ((const char *)) ATTRIBUTE_MALLOC;
+/* Remove a link to a file unless it is special. */
+
+extern int unlink_if_ordinary PARAMS((const char *));
+
/* Allocate memory filled with spaces. Allocates using malloc. */
extern const char *spaces PARAMS ((int count));
@@ -250,6 +254,37 @@ extern PTR xmemdup PARAMS ((const PTR, size_t, size_t)) ATTRIBUTE_MALLOC;
extern double physmem_total PARAMS ((void));
extern double physmem_available PARAMS ((void));
+
+/* These macros provide a K&R/C89/C++-friendly way of allocating structures
+ with nice encapsulation. The XDELETE*() macros are technically
+ superfluous, but provided here for symmetry. Using them consistently
+ makes it easier to update client code to use different allocators such
+ as new/delete and new[]/delete[]. */
+
+/* Scalar allocators. */
+
+#define XNEW(T) ((T *) xmalloc (sizeof (T)))
+#define XCNEW(T) ((T *) xcalloc (1, sizeof (T)))
+#define XDELETE(P) free ((void*) (P))
+
+/* Array allocators. */
+
+#define XNEWVEC(T, N) ((T *) xmalloc (sizeof (T) * (N)))
+#define XCNEWVEC(T, N) ((T *) xcalloc ((N), sizeof (T)))
+#define XRESIZEVEC(T, P, N) ((T *) xrealloc ((void *) (P), sizeof (T) * (N)))
+#define XDELETEVEC(P) free ((void*) (P))
+
+/* Allocators for variable-sized structures and raw buffers. */
+
+#define XNEWVAR(T, S) ((T *) xmalloc ((S)))
+#define XCNEWVAR(T, S) ((T *) xcalloc (1, (S)))
+#define XRESIZEVAR(T, P, S) ((T *) xrealloc ((P), (S)))
+
+/* Type-safe obstack allocator. */
+
+#define XOBNEW(O, T) ((T *) obstack_alloc ((O), sizeof (T)))
+
+
/* hex character manipulation routines */
#define _hex_array_size 256
@@ -309,7 +344,7 @@ extern PTR C_alloca PARAMS ((size_t)) ATTRIBUTE_MALLOC;
# define ASTRDUP(X) \
(__extension__ ({ const char *const libiberty_optr = (X); \
const unsigned long libiberty_len = strlen (libiberty_optr) + 1; \
- char *const libiberty_nptr = alloca (libiberty_len); \
+ char *const libiberty_nptr = (char *const) alloca (libiberty_len); \
(char *) memcpy (libiberty_nptr, libiberty_optr, libiberty_len); }))
#else
# define alloca(x) C_alloca(x)
@@ -323,7 +358,7 @@ extern unsigned long libiberty_len;
# define ASTRDUP(X) \
(libiberty_optr = (X), \
libiberty_len = strlen (libiberty_optr) + 1, \
- libiberty_nptr = alloca (libiberty_len), \
+ libiberty_nptr = (char *) alloca (libiberty_len), \
(char *) memcpy (libiberty_nptr, libiberty_optr, libiberty_len))
#endif
diff --git a/gnu/dist/binutils/include/obstack.h b/gnu/dist/binutils/include/obstack.h
index 5496ff24071..007853e805d 100644
--- a/gnu/dist/binutils/include/obstack.h
+++ b/gnu/dist/binutils/include/obstack.h
@@ -494,9 +494,9 @@ __extension__ \
# define obstack_free(OBSTACK, OBJ) \
__extension__ \
({ struct obstack *__o = (OBSTACK); \
- void *__obj = (OBJ); \
+ void *__obj = (void *) (OBJ); \
if (__obj > (void *)__o->chunk && __obj < (void *)__o->chunk_limit) \
- __o->next_free = __o->object_base = __obj; \
+ __o->next_free = __o->object_base = (char *) __obj; \
else (obstack_free) (__o, __obj); })
#else /* not __GNUC__ or not __STDC__ */
diff --git a/gnu/dist/binutils/include/opcode/ChangeLog b/gnu/dist/binutils/include/opcode/ChangeLog
index 6c50775ea1c..2152ae57e70 100644
--- a/gnu/dist/binutils/include/opcode/ChangeLog
+++ b/gnu/dist/binutils/include/opcode/ChangeLog
@@ -1,13 +1,187 @@
-2004-04-08 Alan Modra <amodra@bigpond.net.au>
+2005-03-15 Jan Beulich <jbeulich@novell.com>
- Apply from mainline.
- 2004-03-12 Jakub Jelinek <jakub@redhat.com>
- * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
+ * i386.h (i386_optab): Add rdtscp.
+
+2005-02-09 Jan Beulich <jbeulich@novell.com>
+
+ PR gas/707
+ * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
+ FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
+ fnstsw.
+
+2005-01-25 Alexandre Oliva <aoliva@redhat.com>
+
+ 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
+ * cgen.h (enum cgen_parse_operand_type): Add
+ CGEN_PARSE_OPERAND_SYMBOLIC.
+
+2005-01-21 Fred Fish <fnf@specifixinc.com>
+
+ * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
+ Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
+ Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
+
+2005-01-19 Fred Fish <fnf@specifixinc.com>
+
+ * mips.h (struct mips_opcode): Add new pinfo2 member.
+ (INSN_ALIAS): New define for opcode table entries that are
+ specific instances of another entry, such as 'move' for an 'or'
+ with a zero operand.
+ (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
+ (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
+
+2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
+
+ * mips.h (CPU_RM9000): Define.
+ (OPCODE_IS_MEMBER): Handle CPU_RM9000.
+
+2004-11-25 Jan Beulich <jbeulich@novell.com>
+
+ * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
+ to/from test registers are illegal in 64-bit mode. Add missing
+ NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
+ (previously one had to explicitly encode a rex64 prefix). Re-enable
+ lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
+ support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
+
+2004-11-23 Jan Beulich <jbeulich@novell.com>
+
+ * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
+ available only with SSE2. Change the MMX additions introduced by SSE
+ and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
+ instructions by their now designated identifier (since combining i686
+ and 3DNow! does not really imply 3DNow!A).
+
+2004-11-19 Alan Modra <amodra@bigpond.net.au>
+
+ * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
+ struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
+
+2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
+ Vineet Sharma <vineets@noida.hcltech.com>
+
+ * maxq.h: New file: Disassembly information for the maxq port.
+
+2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386.h (i386_optab): Put back "movzb".
+
+2004-11-04 Hans-Peter Nilsson <hp@axis.com>
+
+ * cris.h (enum cris_insn_version_usage): Tweak formatting and
+ comments. Remove member cris_ver_sim. Add members
+ cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
+ cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
+ (struct cris_support_reg, struct cris_cond15): New types.
+ (cris_conds15): Declare.
+ (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
+ (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
+ (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
+ (NOP_Z_BITS): Define in terms of NOP_OPCODE.
+ (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
+ SIZE_FIELD_UNSIGNED.
+
+2004-11-04 Jan Beulich <jbeulich@novell.com>
+
+ * i386.h (sldx_Suf): Remove.
+ (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
+ (q_FP): Define, implying no REX64.
+ (x_FP, sl_FP): Imply FloatMF.
+ (i386_optab): Split reg and mem forms of moving from segment registers
+ so that the memory forms can ignore the 16-/32-bit operand size
+ distinction. Adjust a few others for Intel mode. Remove *FP uses from
+ all non-floating-point instructions. Unite 32- and 64-bit forms of
+ movsx, movzx, and movd. Adjust floating point operations for the above
+ changes to the *FP macros. Add DefaultSize to floating point control
+ insns operating on larger memory ranges. Remove left over comments
+ hinting at certain insns being Intel-syntax ones where the ones
+ actually meant are already gone.
+
+2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
+
+ * crx.h: Add COPS_REG_INS - Coprocessor Special register
+ instruction type.
+
+2004-09-30 Paul Brook <paul@codesourcery.com>
+
+ * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
+ (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
+
+2004-09-11 Theodore A. Roth <troth@openavr.org>
+
+ * avr.h: Add support for
+ atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
+
+2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
+
+ * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
+
+2004-08-24 Dmitry Diky <diwil@spec.ru>
+
+ * msp430.h (msp430_opc): Add new instructions.
+ (msp430_rcodes): Declare new instructions.
+ (msp430_hcodes): Likewise..
+
+2004-08-13 Nick Clifton <nickc@redhat.com>
+
+ PR/301
+ * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
+ processors.
+
+2004-08-30 Michal Ludvig <mludvig@suse.cz>
+
+ * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
+
+2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
+
+2004-07-21 Jan Beulich <jbeulich@novell.com>
+
+ * i386.h: Adjust instruction descriptions to better match the
+ specification.
+
+2004-07-16 Richard Earnshaw <rearnsha@arm.com>
+
+ * arm.h: Remove all old content. Replace with architecture defines
+ from gas/config/tc-arm.c.
+
+2004-07-09 Andreas Schwab <schwab@suse.de>
+
+ * m68k.h: Fix comment.
+
+2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
+
+ * crx.h: New file.
+
+2004-06-24 Alan Modra <amodra@bigpond.net.au>
+
+ * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
+
+2004-05-24 Peter Barada <peter@the-baradas.com>
+
+ * m68k.h: Add 'size' to m68k_opcode.
+
+2004-05-05 Peter Barada <peter@the-baradas.com>
+
+ * m68k.h: Switch from ColdFire chip name to core variant.
+
+2004-04-22 Peter Barada <peter@the-baradas.com>
+
+ * m68k.h: Add mcfmac/mcfemac definitions. Update operand
+ descriptions for new EMAC cases.
+ Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
+ handle Motorola MAC syntax.
+ Allow disassembly of ColdFire V4e object files.
2004-03-16 Alan Modra <amodra@bigpond.net.au>
* ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
+2004-03-12 Jakub Jelinek <jakub@redhat.com>
+
+ * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
+
2004-03-12 Michal Ludvig <mludvig@suse.cz>
* i386.h (i386_optab): Added xstore as an alias for xstorerng.
diff --git a/gnu/dist/binutils/include/opcode/arm.h b/gnu/dist/binutils/include/opcode/arm.h
index 99bb9a64f01..dd90e2ac669 100644
--- a/gnu/dist/binutils/include/opcode/arm.h
+++ b/gnu/dist/binutils/include/opcode/arm.h
@@ -1,294 +1,96 @@
-/* ARM opcode list.
- Copyright 1989, 1991 Free Software Foundation, Inc.
-
-This file is part of GDB and GAS.
-
-GDB and GAS are free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 1, or (at your option)
-any later version.
-
-GDB and GAS are distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GDB or GAS; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
-
-/* types of instruction (encoded in bits 26 and 27 of the instruction) */
-
-#define TYPE_ARITHMETIC 0
-#define TYPE_LDR_STR 1
-#define TYPE_BLOCK_BRANCH 2
-#define TYPE_SWI 3
-
-/* bit 25 decides whether an instruction is a block move or a branch */
-#define SUBTYPE_BLOCK 0
-#define SUBTYPE_BRANCH 1
-
-/* codes to distinguish the arithmetic instructions */
-
-#define OPCODE_AND 0
-#define OPCODE_EOR 1
-#define OPCODE_SUB 2
-#define OPCODE_RSB 3
-#define OPCODE_ADD 4
-#define OPCODE_ADC 5
-#define OPCODE_SBC 6
-#define OPCODE_RSC 7
-#define OPCODE_TST 8
-#define OPCODE_TEQ 9
-#define OPCODE_CMP 10
-#define OPCODE_CMN 11
-#define OPCODE_ORR 12
-#define OPCODE_MOV 13
-#define OPCODE_BIC 14
-#define OPCODE_MVN 15
-
-/* condition codes */
-
-#define COND_EQ 0
-#define COND_NE 1
-#define COND_CS 2
-#define COND_CC 3
-#define COND_MI 4
-#define COND_PL 5
-#define COND_VS 6
-#define COND_VC 7
-#define COND_HI 8
-#define COND_LS 9
-#define COND_GE 10
-#define COND_LT 11
-#define COND_GT 12
-#define COND_LE 13
-#define COND_AL 14
-#define COND_NV 15
-
-/* Describes the format of an ARM machine instruction */
-
-struct generic_fmt {
- unsigned rest :25; /* the rest of the instruction */
- unsigned subtype :1; /* used to decide between block and branch */
- unsigned type :2; /* one of TYPE_* */
- unsigned cond :4; /* one of COND_* defined above */
-};
-
-struct arith_fmt {
- unsigned operand2 :12; /* #nn or rn or rn shift #m or rn shift rm */
- unsigned dest :4; /* place where the answer goes */
- unsigned operand1 :4; /* first operand to instruction */
- unsigned set :1; /* == 1 means set processor flags */
- unsigned opcode :4; /* one of OPCODE_* defined above */
- unsigned immed :1; /* operand2 is an immediate value */
- unsigned type :2; /* == TYPE_ARITHMETIC */
- unsigned cond :4; /* one of COND_* defined above */
-};
-
-struct ldr_str_fmt {
- unsigned offset :12; /* #nn or rn or rn shift #m */
- unsigned reg :4; /* destination for LDR, source for STR */
- unsigned base :4; /* base register */
- unsigned is_load :1; /* == 1 for LDR */
- unsigned writeback :1; /* == 1 means write back (base+offset) into base */
- unsigned byte :1; /* == 1 means byte access else word */
- unsigned up :1; /* == 1 means add offset else subtract it */
- unsigned pre_index :1; /* == 1 means [a,b] form else [a],b form */
- unsigned immed :1; /* == 0 means immediate offset */
- unsigned type :2; /* == TYPE_LDR_STR */
- unsigned cond :4; /* one of COND_* defined above */
-};
-
-struct block_fmt {
- unsigned mask :16; /* register mask */
- unsigned base :4; /* register used as base of move */
- unsigned is_load :1; /* == 1 for LDM */
- unsigned writeback :1; /* == 1 means update base after move */
- unsigned set :1; /* == 1 means set flags in pc if included in mask */
- unsigned increment :1; /* == 1 means increment base register */
- unsigned before :1; /* == 1 means inc/dec before each move */
- unsigned is_block :1; /* == SUBTYPE_BLOCK */
- unsigned type :2; /* == TYPE_BLOCK_BRANCH */
- unsigned cond :4; /* one of COND_* defined above */
-};
-
-struct branch_fmt {
- unsigned dest :24; /* destination of the branch */
- unsigned link :1; /* branch with link (function call) */
- unsigned is_branch :1; /* == SUBTYPE_BRANCH */
- unsigned type :2; /* == TYPE_BLOCK_BRANCH */
- unsigned cond :4; /* one of COND_* defined above */
-};
-
-#define ROUND_N 0
-#define ROUND_P 1
-#define ROUND_M 2
-#define ROUND_Z 3
-
-#define FLOAT2_MVF 0
-#define FLOAT2_MNF 1
-#define FLOAT2_ABS 2
-#define FLOAT2_RND 3
-#define FLOAT2_SQT 4
-#define FLOAT2_LOG 5
-#define FLOAT2_LGN 6
-#define FLOAT2_EXP 7
-#define FLOAT2_SIN 8
-#define FLOAT2_COS 9
-#define FLOAT2_TAN 10
-#define FLOAT2_ASN 11
-#define FLOAT2_ACS 12
-#define FLOAT2_ATN 13
-
-#define FLOAT3_ADF 0
-#define FLOAT3_MUF 1
-#define FLOAT3_SUF 2
-#define FLOAT3_RSF 3
-#define FLOAT3_DVF 4
-#define FLOAT3_RDF 5
-#define FLOAT3_POW 6
-#define FLOAT3_RPW 7
-#define FLOAT3_RMF 8
-#define FLOAT3_FML 9
-#define FLOAT3_FDV 10
-#define FLOAT3_FRD 11
-#define FLOAT3_POL 12
-
-struct float2_fmt {
- unsigned operand2 :3; /* second operand */
- unsigned immed :1; /* == 1 if second operand is a constant */
- unsigned pad1 :1; /* == 0 */
- unsigned rounding :2; /* ROUND_* */
- unsigned is_double :1; /* == 1 if precision is double (only if not extended) */
- unsigned pad2 :4; /* == 1 */
- unsigned dest :3; /* destination */
- unsigned is_2_op :1; /* == 1 if 2 operand ins */
- unsigned operand1 :3; /* first operand (only of is_2_op == 0) */
- unsigned is_extended :1; /* == 1 if precision is extended */
- unsigned opcode :4; /* FLOAT2_* or FLOAT3_* depending on is_2_op */
- unsigned must_be_2 :2; /* == 2 */
- unsigned type :2; /* == TYPE_SWI */
- unsigned cond :4; /* COND_* */
-};
-
-struct swi_fmt {
- unsigned argument :24; /* argument to SWI (syscall number) */
- unsigned must_be_3 :2; /* == 3 */
- unsigned type :2; /* == TYPE_SWI */
- unsigned cond :4; /* one of COND_* defined above */
-};
-
-union insn_fmt {
- struct generic_fmt generic;
- struct arith_fmt arith;
- struct ldr_str_fmt ldr_str;
- struct block_fmt block;
- struct branch_fmt branch;
- struct swi_fmt swi;
- unsigned long ins;
-};
-
-struct opcode {
- unsigned long value, mask; /* recognise instruction if (op&mask)==value */
- char *assembler; /* how to disassemble this instruction */
-};
-
-/* format of the assembler string :
-
- %% %
- %<bitfield>d print the bitfield in decimal
- %<bitfield>x print the bitfield in hex
- %<bitfield>r print as an ARM register
- %<bitfield>f print a floating point constant if >7 else an fp register
- %c print condition code (always bits 28-31)
- %P print floating point precision in arithmetic insn
- %Q print floating point precision in ldf/stf insn
- %R print floating point rounding mode
- %<bitnum>'c print specified char iff bit is one
- %<bitnum>`c print specified char iff bit is zero
- %<bitnum>?ab print a if bit is one else print b
- %p print 'p' iff bits 12-15 are 15
- %o print operand2 (immediate or register + shift)
- %a print address for ldr/str instruction
- %b print branch destination
- %A print address for ldc/stc/ldf/stf instruction
- %m print register mask for ldm/stm instruction
-*/
-
-static struct opcode opcodes[] = {
- /* ARM instructions */
- 0x00000090, 0x0fe000f0, "mul%20's %12-15r, %16-19r, %0-3r",
- 0x00200090, 0x0fe000f0, "mla%20's %12-15r, %16-19r, %0-3r, %8-11r",
- 0x00000000, 0x0de00000, "and%c%20's %12-15r, %16-19r, %o",
- 0x00200000, 0x0de00000, "eor%c%20's %12-15r, %16-19r, %o",
- 0x00400000, 0x0de00000, "sub%c%20's %12-15r, %16-19r, %o",
- 0x00600000, 0x0de00000, "rsb%c%20's %12-15r, %16-19r, %o",
- 0x00800000, 0x0de00000, "add%c%20's %12-15r, %16-19r, %o",
- 0x00a00000, 0x0de00000, "adc%c%20's %12-15r, %16-19r, %o",
- 0x00c00000, 0x0de00000, "sbc%c%20's %12-15r, %16-19r, %o",
- 0x00e00000, 0x0de00000, "rsc%c%20's %12-15r, %16-19r, %o",
- 0x01000000, 0x0de00000, "tst%c%p %16-19r, %o",
- 0x01200000, 0x0de00000, "teq%c%p %16-19r, %o",
- 0x01400000, 0x0de00000, "cmp%c%p %16-19r, %o",
- 0x01600000, 0x0de00000, "cmn%c%p %16-19r, %o",
- 0x01800000, 0x0de00000, "orr%c%20's %12-15r, %16-19r, %o",
- 0x01a00000, 0x0de00000, "mov%c%20's %12-15r, %o",
- 0x01c00000, 0x0de00000, "bic%c%20's %12-15r, %16-19r, %o",
- 0x01e00000, 0x0de00000, "mvn%c%20's %12-15r, %o",
- 0x04000000, 0x0c100000, "str%c%22'b %12-15r, %a",
- 0x04100000, 0x0c100000, "ldr%c%22'b %12-15r, %a",
- 0x08000000, 0x0e100000, "stm%c%23?id%24?ba %16-19r%22`!, %m",
- 0x08100000, 0x0e100000, "ldm%c%23?id%24?ba %16-19r%22`!, %m%22'^",
- 0x0a000000, 0x0e000000, "b%c%24'l %b",
- 0x0f000000, 0x0f000000, "swi%c %0-23x",
- /* Floating point coprocessor instructions */
- 0x0e000100, 0x0ff08f10, "adf%c%P%R %12-14f, %16-18f, %0-3f",
- 0x0e100100, 0x0ff08f10, "muf%c%P%R %12-14f, %16-18f, %0-3f",
- 0x0e200100, 0x0ff08f10, "suf%c%P%R %12-14f, %16-18f, %0-3f",
- 0x0e300100, 0x0ff08f10, "rsf%c%P%R %12-14f, %16-18f, %0-3f",
- 0x0e400100, 0x0ff08f10, "dvf%c%P%R %12-14f, %16-18f, %0-3f",
- 0x0e500100, 0x0ff08f10, "rdf%c%P%R %12-14f, %16-18f, %0-3f",
- 0x0e600100, 0x0ff08f10, "pow%c%P%R %12-14f, %16-18f, %0-3f",
- 0x0e700100, 0x0ff08f10, "rpw%c%P%R %12-14f, %16-18f, %0-3f",
- 0x0e800100, 0x0ff08f10, "rmf%c%P%R %12-14f, %16-18f, %0-3f",
- 0x0e900100, 0x0ff08f10, "fml%c%P%R %12-14f, %16-18f, %0-3f",
- 0x0ea00100, 0x0ff08f10, "fdv%c%P%R %12-14f, %16-18f, %0-3f",
- 0x0eb00100, 0x0ff08f10, "frd%c%P%R %12-14f, %16-18f, %0-3f",
- 0x0ec00100, 0x0ff08f10, "pol%c%P%R %12-14f, %16-18f, %0-3f",
- 0x0e008100, 0x0ff08f10, "mvf%c%P%R %12-14f, %0-3f",
- 0x0e108100, 0x0ff08f10, "mnf%c%P%R %12-14f, %0-3f",
- 0x0e208100, 0x0ff08f10, "abs%c%P%R %12-14f, %0-3f",
- 0x0e308100, 0x0ff08f10, "rnd%c%P%R %12-14f, %0-3f",
- 0x0e408100, 0x0ff08f10, "sqt%c%P%R %12-14f, %0-3f",
- 0x0e508100, 0x0ff08f10, "log%c%P%R %12-14f, %0-3f",
- 0x0e608100, 0x0ff08f10, "lgn%c%P%R %12-14f, %0-3f",
- 0x0e708100, 0x0ff08f10, "exp%c%P%R %12-14f, %0-3f",
- 0x0e808100, 0x0ff08f10, "sin%c%P%R %12-14f, %0-3f",
- 0x0e908100, 0x0ff08f10, "cos%c%P%R %12-14f, %0-3f",
- 0x0ea08100, 0x0ff08f10, "tan%c%P%R %12-14f, %0-3f",
- 0x0eb08100, 0x0ff08f10, "asn%c%P%R %12-14f, %0-3f",
- 0x0ec08100, 0x0ff08f10, "acs%c%P%R %12-14f, %0-3f",
- 0x0ed08100, 0x0ff08f10, "atn%c%P%R %12-14f, %0-3f",
- 0x0e000110, 0x0ff00f1f, "flt%c%P%R %16-18f, %12-15r",
- 0x0e100110, 0x0fff0f98, "fix%c%R %12-15r, %0-2f",
- 0x0e200110, 0x0fff0fff, "wfs%c %12-15r",
- 0x0e300110, 0x0fff0fff, "rfs%c %12-15r",
- 0x0e400110, 0x0fff0fff, "wfc%c %12-15r",
- 0x0e500110, 0x0fff0fff, "rfc%c %12-15r",
- 0x0e90f110, 0x0ff8fff0, "cmf%c %16-18f, %0-3f",
- 0x0eb0f110, 0x0ff8fff0, "cnf%c %16-18f, %0-3f",
- 0x0ed0f110, 0x0ff8fff0, "cmfe%c %16-18f, %0-3f",
- 0x0ef0f110, 0x0ff8fff0, "cnfe%c %16-18f, %0-3f",
- 0x0c000100, 0x0e100f00, "stf%c%Q %12-14f, %A",
- 0x0c100100, 0x0e100f00, "ldf%c%Q %12-14f, %A",
- /* Generic coprocessor instructions */
- 0x0e000000, 0x0f000010, "cdp%c %8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}",
- 0x0e000010, 0x0f100010, "mrc%c %8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}",
- 0x0e100010, 0x0f100010, "mcr%c %8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}",
- 0x0c000000, 0x0e100000, "stc%c%22`l %8-11d, cr%12-15d, %A",
- 0x0c100000, 0x0e100000, "ldc%c%22`l %8-11d, cr%12-15d, %A",
- /* the rest */
- 0x00000000, 0x00000000, "undefined instruction %0-31x",
-};
-#define N_OPCODES (sizeof opcodes / sizeof opcodes[0])
+/* ARM assembler/disassembler support.
+ Copyright 2004 Free Software Foundation, Inc.
+
+ This file is part of GDB and GAS.
+
+ GDB and GAS are free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License as
+ published by the Free Software Foundation; either version 1, or (at
+ your option) any later version.
+
+ GDB and GAS are distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with GDB or GAS; see the file COPYING. If not, write to the
+ Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+ 02111-1307, USA. */
+
+/* The following bitmasks control CPU extensions: */
+#define ARM_EXT_V1 0x00000001 /* All processors (core set). */
+#define ARM_EXT_V2 0x00000002 /* Multiply instructions. */
+#define ARM_EXT_V2S 0x00000004 /* SWP instructions. */
+#define ARM_EXT_V3 0x00000008 /* MSR MRS. */
+#define ARM_EXT_V3M 0x00000010 /* Allow long multiplies. */
+#define ARM_EXT_V4 0x00000020 /* Allow half word loads. */
+#define ARM_EXT_V4T 0x00000040 /* Thumb v1. */
+#define ARM_EXT_V5 0x00000080 /* Allow CLZ, etc. */
+#define ARM_EXT_V5T 0x00000100 /* Thumb v2. */
+#define ARM_EXT_V5ExP 0x00000200 /* DSP core set. */
+#define ARM_EXT_V5E 0x00000400 /* DSP Double transfers. */
+#define ARM_EXT_V5J 0x00000800 /* Jazelle extension. */
+#define ARM_EXT_V6 0x00001000 /* ARM V6. */
+#define ARM_EXT_V6K 0x00002000 /* ARM V6K. */
+#define ARM_EXT_V6Z 0x00004000 /* ARM V6Z. */
+
+/* Co-processor space extensions. */
+#define ARM_CEXT_XSCALE 0x00800000 /* Allow MIA etc. */
+#define ARM_CEXT_MAVERICK 0x00400000 /* Use Cirrus/DSP coprocessor. */
+#define ARM_CEXT_IWMMXT 0x00200000 /* Intel Wireless MMX technology coprocessor. */
+
+/* Architectures are the sum of the base and extensions. The ARM ARM (rev E)
+ defines the following: ARMv3, ARMv3M, ARMv4xM, ARMv4, ARMv4TxM, ARMv4T,
+ ARMv5xM, ARMv5, ARMv5TxM, ARMv5T, ARMv5TExP, ARMv5TE. To these we add
+ three more to cover cores prior to ARM6. Finally, there are cores which
+ implement further extensions in the co-processor space. */
+#define ARM_ARCH_V1 ARM_EXT_V1
+#define ARM_ARCH_V2 (ARM_ARCH_V1 | ARM_EXT_V2)
+#define ARM_ARCH_V2S (ARM_ARCH_V2 | ARM_EXT_V2S)
+#define ARM_ARCH_V3 (ARM_ARCH_V2S | ARM_EXT_V3)
+#define ARM_ARCH_V3M (ARM_ARCH_V3 | ARM_EXT_V3M)
+#define ARM_ARCH_V4xM (ARM_ARCH_V3 | ARM_EXT_V4)
+#define ARM_ARCH_V4 (ARM_ARCH_V3M | ARM_EXT_V4)
+#define ARM_ARCH_V4TxM (ARM_ARCH_V4xM | ARM_EXT_V4T)
+#define ARM_ARCH_V4T (ARM_ARCH_V4 | ARM_EXT_V4T)
+#define ARM_ARCH_V5xM (ARM_ARCH_V4xM | ARM_EXT_V5)
+#define ARM_ARCH_V5 (ARM_ARCH_V4 | ARM_EXT_V5)
+#define ARM_ARCH_V5TxM (ARM_ARCH_V5xM | ARM_EXT_V4T | ARM_EXT_V5T)
+#define ARM_ARCH_V5T (ARM_ARCH_V5 | ARM_EXT_V4T | ARM_EXT_V5T)
+#define ARM_ARCH_V5TExP (ARM_ARCH_V5T | ARM_EXT_V5ExP)
+#define ARM_ARCH_V5TE (ARM_ARCH_V5TExP | ARM_EXT_V5E)
+#define ARM_ARCH_V5TEJ (ARM_ARCH_V5TE | ARM_EXT_V5J)
+#define ARM_ARCH_V6 (ARM_ARCH_V5TEJ | ARM_EXT_V6)
+#define ARM_ARCH_V6K (ARM_ARCH_V6 | ARM_EXT_V6K)
+#define ARM_ARCH_V6Z (ARM_ARCH_V6 | ARM_EXT_V6Z)
+#define ARM_ARCH_V6ZK (ARM_ARCH_V6 | ARM_EXT_V6K | ARM_EXT_V6Z)
+
+/* Processors with specific extensions in the co-processor space. */
+#define ARM_ARCH_XSCALE (ARM_ARCH_V5TE | ARM_CEXT_XSCALE)
+#define ARM_ARCH_IWMMXT (ARM_ARCH_XSCALE | ARM_CEXT_IWMMXT)
+
+#define FPU_FPA_EXT_V1 0x80000000 /* Base FPA instruction set. */
+#define FPU_FPA_EXT_V2 0x40000000 /* LFM/SFM. */
+#define FPU_VFP_EXT_NONE 0x20000000 /* Use VFP word-ordering. */
+#define FPU_VFP_EXT_V1xD 0x10000000 /* Base VFP instruction set. */
+#define FPU_VFP_EXT_V1 0x08000000 /* Double-precision insns. */
+#define FPU_VFP_EXT_V2 0x04000000 /* ARM10E VFPr1. */
+#define FPU_MAVERICK 0x02000000 /* Cirrus Maverick. */
+#define FPU_NONE 0
+
+#define FPU_ARCH_FPE FPU_FPA_EXT_V1
+#define FPU_ARCH_FPA (FPU_ARCH_FPE | FPU_FPA_EXT_V2)
+
+#define FPU_ARCH_VFP FPU_VFP_EXT_NONE
+#define FPU_ARCH_VFP_V1xD (FPU_VFP_EXT_V1xD | FPU_VFP_EXT_NONE)
+#define FPU_ARCH_VFP_V1 (FPU_ARCH_VFP_V1xD | FPU_VFP_EXT_V1)
+#define FPU_ARCH_VFP_V2 (FPU_ARCH_VFP_V1 | FPU_VFP_EXT_V2)
+
+#define FPU_ARCH_MAVERICK FPU_MAVERICK
+
+/* Some useful combinations: */
+#define ARM_ANY 0x0000ffff /* Any basic core. */
+#define ARM_ALL 0x00ffffff /* Any core + co-processor */
+#define CPROC_ANY 0x00ff0000 /* Any co-processor */
+#define FPU_ANY 0xff000000 /* Note this is ~ARM_ALL. */
diff --git a/gnu/dist/binutils/include/opcode/avr.h b/gnu/dist/binutils/include/opcode/avr.h
index bcc093d302b..6e93b73d46e 100644
--- a/gnu/dist/binutils/include/opcode/avr.h
+++ b/gnu/dist/binutils/include/opcode/avr.h
@@ -1,6 +1,6 @@
/* Opcode table for the Atmel AVR micro controllers.
- Copyright 2000 Free Software Foundation, Inc.
+ Copyright 2000, 2001, 2004 Free Software Foundation, Inc.
Contributed by Denis Chertykov <denisc@overta.ru>
This program is free software; you can redistribute it and/or modify
@@ -23,20 +23,25 @@
#define AVR_ISA_SRAM 0x0008 /* device has SRAM (LD, ST, PUSH, POP, ...) */
#define AVR_ISA_MEGA 0x0020 /* device has >8K program memory (JMP and CALL
supported, no 8K wrap on RJMP and RCALL) */
-#define AVR_ISA_MUL 0x0040 /* device has new core (MUL, MOVW, ...) */
+#define AVR_ISA_MUL 0x0040 /* device has new core (MUL, FMUL, ...) */
#define AVR_ISA_ELPM 0x0080 /* device has >64K program memory (ELPM) */
#define AVR_ISA_ELPMX 0x0100 /* device has ELPM Rd,Z[+] */
#define AVR_ISA_SPM 0x0200 /* device can program itself */
#define AVR_ISA_BRK 0x0400 /* device has BREAK (on-chip debug) */
#define AVR_ISA_EIND 0x0800 /* device has >128K program memory (none yet) */
+#define AVR_ISA_MOVW 0x1000 /* device has MOVW */
#define AVR_ISA_TINY1 (AVR_ISA_1200 | AVR_ISA_LPM)
#define AVR_ISA_2xxx (AVR_ISA_TINY1 | AVR_ISA_SRAM)
-#define AVR_ISA_M8 (AVR_ISA_2xxx | AVR_ISA_MUL | AVR_ISA_LPMX | AVR_ISA_SPM)
+#define AVR_ISA_TINY2 (AVR_ISA_2xxx | AVR_ISA_MOVW | AVR_ISA_LPMX | \
+ AVR_ISA_SPM | AVR_ISA_BRK)
+#define AVR_ISA_M8 (AVR_ISA_2xxx | AVR_ISA_MUL | AVR_ISA_MOVW | \
+ AVR_ISA_LPMX | AVR_ISA_SPM)
#define AVR_ISA_M603 (AVR_ISA_2xxx | AVR_ISA_MEGA)
#define AVR_ISA_M103 (AVR_ISA_M603 | AVR_ISA_ELPM)
-#define AVR_ISA_M161 (AVR_ISA_M603 | AVR_ISA_MUL | AVR_ISA_LPMX | AVR_ISA_SPM)
-#define AVR_ISA_94K (AVR_ISA_M603 | AVR_ISA_MUL | AVR_ISA_LPMX)
+#define AVR_ISA_M161 (AVR_ISA_M603 | AVR_ISA_MUL | AVR_ISA_MOVW | \
+ AVR_ISA_LPMX | AVR_ISA_SPM)
+#define AVR_ISA_94K (AVR_ISA_M603 | AVR_ISA_MUL | AVR_ISA_MOVW | AVR_ISA_LPMX)
#define AVR_ISA_M323 (AVR_ISA_M161 | AVR_ISA_BRK)
#define AVR_ISA_M128 (AVR_ISA_M323 | AVR_ISA_ELPM | AVR_ISA_ELPMX)
@@ -236,7 +241,7 @@ AVR_INSN (ror, "r", "1001010rrrrr0111", 1, AVR_ISA_1200, 0x9407)
AVR_INSN (swap, "r", "1001010rrrrr0010", 1, AVR_ISA_1200, 0x9402)
/* Known to be decoded as `nop' by the old core. */
-AVR_INSN (movw, "v,v", "00000001ddddrrrr", 1, AVR_ISA_MUL, 0x0100)
+AVR_INSN (movw, "v,v", "00000001ddddrrrr", 1, AVR_ISA_MOVW, 0x0100)
AVR_INSN (muls, "d,d", "00000010ddddrrrr", 1, AVR_ISA_MUL, 0x0200)
AVR_INSN (mulsu,"a,a", "000000110ddd0rrr", 1, AVR_ISA_MUL, 0x0300)
AVR_INSN (fmul, "a,a", "000000110ddd1rrr", 1, AVR_ISA_MUL, 0x0308)
diff --git a/gnu/dist/binutils/include/opcode/cgen.h b/gnu/dist/binutils/include/opcode/cgen.h
index 16366fd0d75..f9441618a96 100644
--- a/gnu/dist/binutils/include/opcode/cgen.h
+++ b/gnu/dist/binutils/include/opcode/cgen.h
@@ -1,6 +1,6 @@
/* Header file for targets using CGEN: Cpu tools GENerator.
-Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002
+Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005
Free Software Foundation, Inc.
This file is part of GDB, the GNU debugger, and the GNU Binutils.
@@ -369,7 +369,8 @@ enum cgen_parse_operand_type
{
CGEN_PARSE_OPERAND_INIT,
CGEN_PARSE_OPERAND_INTEGER,
- CGEN_PARSE_OPERAND_ADDRESS
+ CGEN_PARSE_OPERAND_ADDRESS,
+ CGEN_PARSE_OPERAND_SYMBOLIC
};
/* Values for indicating what was parsed. */
diff --git a/gnu/dist/binutils/include/opcode/cris.h b/gnu/dist/binutils/include/opcode/cris.h
index 1f10034c304..9b33f199c56 100644
--- a/gnu/dist/binutils/include/opcode/cris.h
+++ b/gnu/dist/binutils/include/opcode/cris.h
@@ -1,5 +1,5 @@
/* cris.h -- Header file for CRIS opcode and register tables.
- Copyright (C) 2000, 2001 Free Software Foundation, Inc.
+ Copyright (C) 2000, 2001, 2004 Free Software Foundation, Inc.
Contributed by Axis Communications AB, Lund, Sweden.
Originally written for GAS 1.38.1 by Mikael Asker.
Updated, BFDized and GNUified by Hans-Peter Nilsson.
@@ -38,15 +38,12 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
immediate operands. */
enum cris_insn_version_usage
{
- /* Any version. */
+ /* Any version. */
cris_ver_version_all=0,
/* Indeterminate (intended for disassembly only, or obsolete). */
cris_ver_warning,
- /* Simulator only (reserved). */
- cris_ver_sim,
-
/* Only for v0..3 (Etrax 1..4). */
cris_ver_v0_3,
@@ -59,10 +56,28 @@ enum cris_insn_version_usage
/* Only for v8 or higher (ETRAX 100, ETRAX 100 LX). */
cris_ver_v8p,
- /* Only for v10 or higher (ETRAX 100 LX).
- Of course some or all these of may change to cris_ver_v10p if/when
+ /* Only for v0..10. FIXME: Not sure what to do with this. */
+ cris_ver_sim_v0_10,
+
+ /* Only for v0..10. */
+ cris_ver_v0_10,
+
+ /* Only for v3..10. (ETRAX 4, ETRAX 100 and ETRAX 100 LX). */
+ cris_ver_v3_10,
+
+ /* Only for v8..10 (ETRAX 100 and ETRAX 100 LX). */
+ cris_ver_v8_10,
+
+ /* Only for v10 (ETRAX 100 LX) and same series. */
+ cris_ver_v10,
+
+ /* Only for v10 (ETRAX 100 LX) and same series. */
+ cris_ver_v10p,
+
+ /* Only for v32 or higher (codename GUINNESS).
+ Of course some or all these of may change to cris_ver_v32p if/when
there's a new revision. */
- cris_ver_v10p
+ cris_ver_v32p
};
@@ -85,6 +100,25 @@ struct cris_spec_reg
};
extern const struct cris_spec_reg cris_spec_regs[];
+
+/* Support registers (kind of special too, but not named as such). */
+struct cris_support_reg
+{
+ const char *const name;
+ unsigned int number;
+};
+extern const struct cris_support_reg cris_support_regs[];
+
+struct cris_cond15
+{
+ /* The name of the condition. */
+ const char *const name;
+
+ /* What CPU version this condition name applies to. */
+ enum cris_insn_version_usage applicable_version;
+};
+extern const struct cris_cond15 cris_conds15[];
+
/* Opcode-dependent constants. */
#define AUTOINCR_BIT (0x04)
@@ -163,9 +197,28 @@ extern const char *const cris_cc_strings[];
#define ADD_PC_INCR_OPCODE \
(0xfa00 + (2 << 4) + AUTOINCR_BIT * 0x0100 + REG_PC)
+#define JUMP_PC_INCR_OPCODE_V32 (0x0DBF)
+
+/* BA DWORD (V32). */
+#define BA_DWORD_OPCODE (0x0EBF)
+
/* Nop. */
#define NOP_OPCODE (0x050F)
-#define NOP_Z_BITS (0xFAF0)
+#define NOP_Z_BITS (0xFFFF ^ NOP_OPCODE)
+
+#define NOP_OPCODE_V32 (0x05B0)
+#define NOP_Z_BITS_V32 (0xFFFF ^ NOP_OPCODE_V32)
+
+/* For the compatibility mode, let's use "MOVE R0,P0". Doesn't affect
+ registers or flags. Unfortunately shuts off interrupts for one cycle
+ for < v32, but there doesn't seem to be any alternative without that
+ effect. */
+#define NOP_OPCODE_COMMON (0x630)
+#define NOP_OPCODE_ZBITS_COMMON (0xffff & ~NOP_OPCODE_COMMON)
+
+/* LAPC.D */
+#define LAPC_DWORD_OPCODE (0x0D7F)
+#define LAPC_DWORD_Z_BITS (0x0fff & ~LAPC_DWORD_OPCODE)
/* Structure of an opcode table entry. */
enum cris_imm_oprnd_size_type
@@ -179,7 +232,13 @@ enum cris_imm_oprnd_size_type
/* Indicated by size of special register. */
SIZE_SPEC_REG,
- /* Indicated by size field. */
+ /* Indicated by size field, signed. */
+ SIZE_FIELD_SIGNED,
+
+ /* Indicated by size field, unsigned. */
+ SIZE_FIELD_UNSIGNED,
+
+ /* Indicated by size field, no sign implied. */
SIZE_FIELD
};
diff --git a/gnu/dist/binutils/include/opcode/crx.h b/gnu/dist/binutils/include/opcode/crx.h
new file mode 100644
index 00000000000..f0fd41a30cb
--- /dev/null
+++ b/gnu/dist/binutils/include/opcode/crx.h
@@ -0,0 +1,418 @@
+/* crx.h -- Header file for CRX opcode and register tables.
+ Copyright 2004 Free Software Foundation, Inc.
+ Contributed by Tomer Levi, NSC, Israel.
+ Originally written for GAS 2.12 by Tomer Levi, NSC, Israel.
+ Updates, BFDizing, GNUifying and ELF support by Tomer Levi.
+
+ This file is part of GAS, GDB and the GNU binutils.
+
+ GAS, GDB, and GNU binutils is free software; you can redistribute it
+ and/or modify it under the terms of the GNU General Public License as
+ published by the Free Software Foundation; either version 2, or (at your
+ option) any later version.
+
+ GAS, GDB, and GNU binutils are distributed in the hope that they will be
+ useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+
+#ifndef _CRX_H_
+#define _CRX_H_
+
+/* CRX core/debug Registers :
+ The enums are used as indices to CRX registers table (crx_regtab).
+ Therefore, order MUST be preserved. */
+
+typedef enum
+ {
+ /* 32-bit general purpose registers. */
+ r0, r1, r2, r3, r4, r5, r6, r7, r8, r9,
+ r10, r11, r12, r13, r14, r15, ra, sp,
+ /* 32-bit user registers. */
+ u0, u1, u2, u3, u4, u5, u6, u7, u8, u9,
+ u10, u11, u12, u13, u14, u15, ura, usp,
+ /* hi and lo registers. */
+ hi, lo,
+ /* hi and lo user registers. */
+ uhi, ulo,
+ /* Processor Status Register. */
+ psr,
+ /* Interrupt Base Register. */
+ intbase,
+ /* Interrupt Stack Pointer Register. */
+ isp,
+ /* Configuration Register. */
+ cfg,
+ /* Coprocessor Configuration Register. */
+ cpcfg,
+ /* Coprocessor Enable Register. */
+ cen,
+ /* Not a register. */
+ nullregister,
+ MAX_REG
+ }
+reg;
+
+/* CRX Coprocessor registers and special registers :
+ The enums are used as indices to CRX coprocessor registers table
+ (crx_copregtab). Therefore, order MUST be preserved. */
+
+typedef enum
+ {
+ /* Coprocessor registers. */
+ c0 = MAX_REG, c1, c2, c3, c4, c5, c6, c7, c8,
+ c9, c10, c11, c12, c13, c14, c15,
+ /* Coprocessor special registers. */
+ cs0, cs1 ,cs2, cs3, cs4, cs5, cs6, cs7, cs8,
+ cs9, cs10, cs11, cs12, cs13, cs14, cs15,
+ /* Not a Coprocessor register. */
+ nullcopregister,
+ MAX_COPREG
+ }
+copreg;
+
+/* CRX Register types. */
+
+typedef enum
+ {
+ CRX_R_REGTYPE, /* r<N> */
+ CRX_U_REGTYPE, /* u<N> */
+ CRX_C_REGTYPE, /* c<N> */
+ CRX_CS_REGTYPE, /* cs<N> */
+ CRX_CFG_REGTYPE /* configuration register */
+ }
+reg_type;
+
+/* CRX argument types :
+ The argument types correspond to instructions operands
+
+ Argument types :
+ r - register
+ c - constant
+ i - immediate
+ idxr - index register
+ rbase - register base
+ s - star ('*')
+ copr - coprocessor register
+ copsr - coprocessor special register. */
+
+typedef enum
+ {
+ arg_r, arg_c, arg_cr, arg_ic, arg_icr, arg_sc,
+ arg_idxr, arg_rbase, arg_copr, arg_copsr,
+ /* Not an argument. */
+ nullargs
+ }
+argtype;
+
+/* CRX operand types :
+ The operand types correspond to instructions operands. */
+
+typedef enum
+ {
+ dummy,
+ /* 4-bit encoded constant. */
+ cst4,
+ /* N-bit immediate. */
+ i16, i32,
+ /* N-bit unsigned immediate. */
+ ui3, ui4, ui5, ui16,
+ /* N-bit signed displacement. */
+ disps9, disps17, disps25, disps32,
+ /* N-bit unsigned displacement. */
+ dispu5,
+ /* N-bit escaped displacement. */
+ dispe9,
+ /* N-bit absolute address. */
+ abs16, abs32,
+ /* Register relative. */
+ rbase, rbase_dispu4,
+ rbase_disps12, rbase_disps16, rbase_disps28, rbase_disps32,
+ /* Register index. */
+ rindex_disps6, rindex_disps22,
+ /* 4-bit genaral-purpose register specifier. */
+ regr,
+ /* 8-bit register address space. */
+ regr8,
+ /* coprocessor register. */
+ copregr,
+ /* coprocessor special register. */
+ copsregr,
+ /* Not an operand. */
+ nulloperand,
+ /* Maximum supported operand. */
+ MAX_OPRD
+ }
+operand_type;
+
+/* CRX instruction types. */
+
+#define NO_TYPE_INS 0
+#define ARITH_INS 1
+#define LD_STOR_INS 2
+#define BRANCH_INS 3
+#define ARITH_BYTE_INS 4
+#define CMPBR_INS 5
+#define SHIFT_INS 6
+#define BRANCH_NEQ_INS 7
+#define LD_STOR_INS_INC 8
+#define STOR_IMM_INS 9
+#define CSTBIT_INS 10
+#define COP_BRANCH_INS 11
+#define COP_REG_INS 12
+#define COPS_REG_INS 13
+#define DCR_BRANCH_INS 14
+
+/* Maximum value supported for instruction types. */
+#define CRX_INS_MAX (1 << 4)
+/* Mask to record an instruction type. */
+#define CRX_INS_MASK (CRX_INS_MAX - 1)
+/* Return instruction type, given instruction's attributes. */
+#define CRX_INS_TYPE(attr) ((attr) & CRX_INS_MASK)
+
+/* Indicates whether this instruction has a register list as parameter. */
+#define REG_LIST CRX_INS_MAX
+/* The operands in binary and assembly are placed in reverse order.
+ load - (REVERSE_MATCH)/store - (! REVERSE_MATCH). */
+#define REVERSE_MATCH (1 << 5)
+
+/* Kind of displacement map used DISPU[BWD]4. */
+#define DISPUB4 (1 << 6)
+#define DISPUW4 (1 << 7)
+#define DISPUD4 (1 << 8)
+#define DISPU4MAP (DISPUB4 | DISPUW4 | DISPUD4)
+
+/* Printing formats, where the instruction prefix isn't consecutive. */
+#define FMT_1 (1 << 9) /* 0xF0F00000 */
+#define FMT_2 (1 << 10) /* 0xFFF0FF00 */
+#define FMT_3 (1 << 11) /* 0xFFF00F00 */
+#define FMT_4 (1 << 12) /* 0xFFF0F000 */
+#define FMT_5 (1 << 13) /* 0xFFF0FFF0 */
+#define FMT_CRX (FMT_1 | FMT_2 | FMT_3 | FMT_4 | FMT_5)
+
+/* Indicates whether this instruction can be relaxed. */
+#define RELAXABLE (1 << 14)
+
+/* Indicates that instruction uses user registers (and not
+ general-purpose registers) as operands. */
+#define USER_REG (1 << 15)
+
+/* Indicates that instruction can perfom a cst4 mapping. */
+#define CST4MAP (1 << 16)
+
+/* Instruction shouldn't allow 'sp' usage. */
+#define NO_SP (1 << 17)
+
+/* Instruction shouldn't allow to push a register which is used as a rptr. */
+#define NO_RPTR (1 << 18)
+
+/* Maximum operands per instruction. */
+#define MAX_OPERANDS 5
+/* Maximum register name length. */
+#define MAX_REGNAME_LEN 10
+/* Maximum instruction length. */
+#define MAX_INST_LEN 256
+
+
+/* Values defined for the flags field of a struct operand_entry. */
+
+/* Operand must be an unsigned number. */
+#define OP_UNSIGNED (1 << 0)
+/* Operand must be a signed number. */
+#define OP_SIGNED (1 << 1)
+/* A special arithmetic 4-bit constant operand. */
+#define OP_CST4 (1 << 2)
+/* A special load/stor 4-bit unsigned displacement operand. */
+#define OP_DISPU4 (1 << 3)
+/* Operand must be an even number. */
+#define OP_EVEN (1 << 4)
+/* Operand is shifted right. */
+#define OP_SHIFT (1 << 5)
+/* Operand is shifted right and decremented. */
+#define OP_SHIFT_DEC (1 << 6)
+/* Operand has reserved escape sequences. */
+#define OP_ESC (1 << 7)
+/* Operand is used only for the upper 64 KB (FFFF0000 to FFFFFFFF). */
+#define OP_UPPER_64KB (1 << 8)
+
+/* Single operand description. */
+
+typedef struct
+ {
+ /* Operand type. */
+ operand_type op_type;
+ /* Operand location within the opcode. */
+ unsigned int shift;
+ }
+operand_desc;
+
+/* Instruction data structure used in instruction table. */
+
+typedef struct
+ {
+ /* Name. */
+ const char *mnemonic;
+ /* Size (in words). */
+ unsigned int size;
+ /* Constant prefix (matched by the disassembler). */
+ unsigned long match;
+ /* Match size (in bits). */
+ int match_bits;
+ /* Attributes. */
+ unsigned int flags;
+ /* Operands (always last, so unreferenced operands are initialized). */
+ operand_desc operands[MAX_OPERANDS];
+ }
+inst;
+
+/* Data structure for a single instruction's arguments (Operands). */
+
+typedef struct
+ {
+ /* Register or base register. */
+ reg r;
+ /* Index register. */
+ reg i_r;
+ /* Coprocessor register. */
+ copreg cr;
+ /* Constant/immediate/absolute value. */
+ long constant;
+ /* Scaled index mode. */
+ unsigned int scale;
+ /* Argument type. */
+ argtype type;
+ /* Size of the argument (in bits) required to represent. */
+ int size;
+ /* The type of the expression. */
+ unsigned char X_op;
+ }
+argument;
+
+/* Internal structure to hold the various entities
+ corresponding to the current assembling instruction. */
+
+typedef struct
+ {
+ /* Number of arguments. */
+ int nargs;
+ /* The argument data structure for storing args (operands). */
+ argument arg[MAX_OPERANDS];
+/* The following fields are required only by CRX-assembler. */
+#ifdef TC_CRX
+ /* Expression used for setting the fixups (if any). */
+ expressionS exp;
+ bfd_reloc_code_real_type rtype;
+#endif /* TC_CRX */
+ /* Instruction size (in bytes). */
+ int size;
+ }
+ins;
+
+/* Structure to hold information about predefined operands. */
+
+typedef struct
+ {
+ /* Size (in bits). */
+ unsigned int bit_size;
+ /* Argument type. */
+ argtype arg_type;
+ /* One bit syntax flags. */
+ int flags;
+ }
+operand_entry;
+
+/* Structure to hold trap handler information. */
+
+typedef struct
+ {
+ /* Trap name. */
+ char *name;
+ /* Index in dispatch table. */
+ unsigned int entry;
+ }
+trap_entry;
+
+/* Structure to hold information about predefined registers. */
+
+typedef struct
+ {
+ /* Name (string representation). */
+ char *name;
+ /* Value (enum representation). */
+ union
+ {
+ /* Register. */
+ reg reg_val;
+ /* Coprocessor register. */
+ copreg copreg_val;
+ } value;
+ /* Register image. */
+ int image;
+ /* Register type. */
+ reg_type type;
+ }
+reg_entry;
+
+/* Structure to hold a cst4 operand mapping. */
+
+/* CRX opcode table. */
+extern const inst crx_instruction[];
+extern const int crx_num_opcodes;
+#define NUMOPCODES crx_num_opcodes
+
+/* CRX operands table. */
+extern const operand_entry crx_optab[];
+
+/* CRX registers table. */
+extern const reg_entry crx_regtab[];
+extern const int crx_num_regs;
+#define NUMREGS crx_num_regs
+
+/* CRX coprocessor registers table. */
+extern const reg_entry crx_copregtab[];
+extern const int crx_num_copregs;
+#define NUMCOPREGS crx_num_copregs
+
+/* CRX trap/interrupt table. */
+extern const trap_entry crx_traps[];
+extern const int crx_num_traps;
+#define NUMTRAPS crx_num_traps
+
+/* cst4 operand mapping. */
+extern const long cst4_map[];
+extern const int cst4_maps;
+
+/* Table of instructions with no operands. */
+extern const char* no_op_insn[];
+
+/* Current instruction we're assembling. */
+extern const inst *instruction;
+
+/* A macro for representing the instruction "constant" opcode, that is,
+ the FIXED part of the instruction. The "constant" opcode is represented
+ as a 32-bit unsigned long, where OPC is expanded (by a left SHIFT)
+ over that range. */
+#define BIN(OPC,SHIFT) (OPC << SHIFT)
+
+/* Is the current instruction type is TYPE ? */
+#define IS_INSN_TYPE(TYPE) \
+ (CRX_INS_TYPE(instruction->flags) == TYPE)
+
+/* Is the current instruction mnemonic is MNEMONIC ? */
+#define IS_INSN_MNEMONIC(MNEMONIC) \
+ (strcmp(instruction->mnemonic,MNEMONIC) == 0)
+
+/* Does the current instruction has register list ? */
+#define INST_HAS_REG_LIST \
+ (instruction->flags & REG_LIST)
+
+/* Long long type handling. */
+/* Replace all appearances of 'long long int' with LONGLONG. */
+typedef long long int LONGLONG;
+typedef unsigned long long ULONGLONG;
+
+#endif /* _CRX_H_ */
diff --git a/gnu/dist/binutils/include/opcode/h8300.h b/gnu/dist/binutils/include/opcode/h8300.h
index 29374df5b4f..2bc7b44bc30 100644
--- a/gnu/dist/binutils/include/opcode/h8300.h
+++ b/gnu/dist/binutils/include/opcode/h8300.h
@@ -1,5 +1,6 @@
/* Opcode table for the H8/300
- Copyright 1991, 1992, 1993, 1994, 1996, 1997, 1998, 2000, 2002, 2003, 2004
+ Copyright 1991, 1992, 1993, 1994, 1996, 1997, 1998, 2000, 2001, 2002,
+ 2003, 2004
Free Software Foundation, Inc.
Written by Steve Chamberlain <sac@cygnus.com>.
@@ -1418,7 +1419,7 @@ struct h8_opcode h8_opcodes[] =
{O (O_JSR, SN), AV_H8SX, 0, "jsr", {{ABSJMP | L_32, E}}, {{0x5, 0xD, 0x0, 0x8, ABSJMP | L_32, DATA7, E}}},
{O (O_JSR, SN), AV_H8, 8, "jsr", {{MEMIND, E}}, {{0x5, 0xF, SRC | MEMIND, DATA, E}}},
- {O (O_JSR, SN), AV_H8, 8, "jsr", {{VECIND, E}}, {{0x5, 0xD, SRC | VECIND, DATA, E}}},
+ {O (O_JSR, SN), AV_H8SX, 8, "jsr", {{VECIND, E}}, {{0x5, 0xD, SRC | VECIND, DATA, E}}},
{O (O_LDC, SB), AV_H8, 2, "ldc", {{IMM8, CCR | DST, E}}, {{ 0x0, 0x7, IMM8LIST, E}}},
{O (O_LDC, SB), AV_H8S, 2, "ldc", {{IMM8, EXR | DST, E}}, {{0x0, 0x1, 0x4, EXR | DST, 0x0, 0x7, IMM8LIST, E}}},
diff --git a/gnu/dist/binutils/include/opcode/hppa.h b/gnu/dist/binutils/include/opcode/hppa.h
index 8234664a626..312cb7f7c44 100644
--- a/gnu/dist/binutils/include/opcode/hppa.h
+++ b/gnu/dist/binutils/include/opcode/hppa.h
@@ -1,6 +1,6 @@
/* Table of opcodes for the PA-RISC.
Copyright 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000,
- 2001, 2002
+ 2001, 2002, 2003
Free Software Foundation, Inc.
Contributed by the Center for Software Science at the
diff --git a/gnu/dist/binutils/include/opcode/i386.h b/gnu/dist/binutils/include/opcode/i386.h
index 5e3673e2b04..07163f07754 100644
--- a/gnu/dist/binutils/include/opcode/i386.h
+++ b/gnu/dist/binutils/include/opcode/i386.h
@@ -1,23 +1,23 @@
/* opcode/i386.h -- Intel 80386 opcode table
Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
- 2000, 2001, 2002, 2003, 2004
+ 2000, 2001, 2002, 2003, 2004, 2005
Free Software Foundation, Inc.
-This file is part of GAS, the GNU Assembler, and GDB, the GNU Debugger.
+ This file is part of GAS, the GNU Assembler, and GDB, the GNU Debugger.
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software
-Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
/* The SystemV/386 SVR3.2 assembler, and probably all AT&T derived
ix86 Unix assemblers, generate floating point instructions with
@@ -48,7 +48,8 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#define OLDGCC_COMPAT SYSV386_COMPAT
#endif
-static const template i386_optab[] = {
+static const template i386_optab[] =
+{
#define X None
#define NoSuf (No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf)
@@ -64,13 +65,13 @@ static const template i386_optab[] = {
#define lq_Suf (No_bSuf|No_wSuf|No_sSuf|No_xSuf)
#define wq_Suf (No_bSuf|No_lSuf|No_sSuf|No_xSuf)
#define sl_Suf (No_bSuf|No_wSuf|No_xSuf|No_qSuf)
-#define sldx_Suf (No_bSuf|No_wSuf|No_qSuf)
#define bwl_Suf (No_sSuf|No_xSuf|No_qSuf)
#define bwlq_Suf (No_sSuf|No_xSuf)
-#define FP (NoSuf|IgnoreSize)
-#define l_FP (l_Suf|IgnoreSize)
-#define x_FP (x_Suf|IgnoreSize)
-#define sl_FP (sl_Suf|IgnoreSize)
+#define FP (NoSuf)
+#define l_FP (l_Suf)
+#define q_FP (q_Suf|NoRex64)
+#define x_FP (x_Suf|FloatMF)
+#define sl_FP (sl_Suf|FloatMF)
#if SYSV386_COMPAT
/* Someone forgot that the FloatR bit reverses the operation when not
equal to the FloatD bit. ie. Changing only FloatD results in the
@@ -84,7 +85,7 @@ static const template i386_optab[] = {
#define MOV_AX_DISP32 0xa0
/* In the 64bit mode the short form mov immediate is redefined to have
64bit displacement value. */
-{ "mov", 2, 0xa0, X, CpuNo64,bwlq_Suf|D|W, { Disp16|Disp32, Acc, 0 } },
+{ "mov", 2, 0xa0, X, CpuNo64,bwl_Suf|D|W, { Disp16|Disp32, Acc, 0 } },
{ "mov", 2, 0x88, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
/* In the 64bit mode the short form mov immediate is redefined to have
64bit displacement value. */
@@ -96,8 +97,10 @@ static const template i386_optab[] = {
size prefix. When moving to a 32 bit register, the upper 16 bits
are set to an implementation defined value (on the Pentium Pro,
the implementation defined value is zero). */
-{ "mov", 2, 0x8c, X, 0, wl_Suf|Modrm, { SReg2, WordReg|WordMem, 0 } },
-{ "mov", 2, 0x8c, X, Cpu386, wl_Suf|Modrm, { SReg3, WordReg|WordMem, 0 } },
+{ "mov", 2, 0x8c, X, 0, wl_Suf|Modrm, { SReg2, WordReg|InvMem, 0 } },
+{ "mov", 2, 0x8c, X, 0, wl_Suf|Modrm|IgnoreSize, { SReg2, WordMem, 0 } },
+{ "mov", 2, 0x8c, X, Cpu386, wl_Suf|Modrm, { SReg3, WordReg|InvMem, 0 } },
+{ "mov", 2, 0x8c, X, Cpu386, wl_Suf|Modrm|IgnoreSize, { SReg3, WordMem, 0 } },
{ "mov", 2, 0x8e, X, 0, wl_Suf|Modrm|IgnoreSize, { WordReg|WordMem, SReg2, 0 } },
{ "mov", 2, 0x8e, X, Cpu386, wl_Suf|Modrm|IgnoreSize, { WordReg|WordMem, SReg3, 0 } },
/* Move to/from control debug registers. In the 16 or 32bit modes they are 32bit. In the 64bit
@@ -106,7 +109,7 @@ static const template i386_optab[] = {
{ "mov", 2, 0x0f20, X, Cpu64, q_Suf|D|Modrm|IgnoreSize|NoRex64,{ Control, Reg64|InvMem, 0} },
{ "mov", 2, 0x0f21, X, Cpu386|CpuNo64, l_Suf|D|Modrm|IgnoreSize,{ Debug, Reg32|InvMem, 0} },
{ "mov", 2, 0x0f21, X, Cpu64, q_Suf|D|Modrm|IgnoreSize|NoRex64,{ Debug, Reg64|InvMem, 0} },
-{ "mov", 2, 0x0f24, X, Cpu386, l_Suf|D|Modrm|IgnoreSize, { Test, Reg32|InvMem, 0} },
+{ "mov", 2, 0x0f24, X, Cpu386|CpuNo64, l_Suf|D|Modrm|IgnoreSize, { Test, Reg32|InvMem, 0} },
{ "movabs",2, 0xa0, X, Cpu64, bwlq_Suf|D|W, { Disp64, Acc, 0 } },
{ "movabs",2, 0xb0, X, Cpu64, q_Suf|W|ShortForm, { Imm64, Reg64, 0 } },
@@ -119,42 +122,41 @@ static const template i386_optab[] = {
{"movsbq", 2, 0x0fbe, X, Cpu64, NoSuf|Modrm|Rex64, { Reg8|ByteMem, Reg64, 0} },
{"movswq", 2, 0x0fbf, X, Cpu64, NoSuf|Modrm|Rex64, { Reg16|ShortMem,Reg64, 0} },
{"movslq", 2, 0x63, X, Cpu64, NoSuf|Modrm|Rex64, { Reg32|WordMem, Reg64, 0} },
-/* Intel Syntax next 5 insns */
+/* Intel Syntax next 3 insns */
{"movsx", 2, 0x0fbe, X, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, WordReg, 0} },
-{"movsx", 2, 0x0fbf, X, Cpu386, w_Suf|Modrm, { Reg16|ShortMem, Reg32, 0} },
-{"movsx", 2, 0x0fbe, X, Cpu64, b_Suf|Modrm|Rex64, { Reg8|ByteMem, Reg64, 0} },
-{"movsx", 2, 0x0fbf, X, Cpu64, w_Suf|Modrm|Rex64, { Reg16|ShortMem, Reg64, 0} },
+{"movsx", 2, 0x0fbf, X, Cpu386, w_Suf|Modrm, { Reg16|ShortMem, Reg32|Reg64, 0} },
{"movsx", 2, 0x63, X, Cpu64, l_Suf|Modrm|Rex64, { Reg32|WordMem, Reg64, 0} },
-/* Move with zero extend. */
+/* Move with zero extend. We can't remove "movzb" since existing
+ assembly codes may use it. */
{"movzb", 2, 0x0fb6, X, Cpu386, wl_Suf|Modrm, { Reg8|ByteMem, WordReg, 0} },
+/* "movzbl" & "movzbw" should not be unified into "movzb" for
+ consistency with the sign extending moves above. */
+{"movzbl", 2, 0x0fb6, X, Cpu386, NoSuf|Modrm, { Reg8|ByteMem, Reg32, 0} },
+{"movzbw", 2, 0x0fb6, X, Cpu386, NoSuf|Modrm, { Reg8|ByteMem, Reg16, 0} },
{"movzwl", 2, 0x0fb7, X, Cpu386, NoSuf|Modrm, { Reg16|ShortMem, Reg32, 0} },
-/* These instructions are not particulary usefull, since the zero extend
+/* These instructions are not particulary useful, since the zero extend
32->64 is implicit, but we can encode them. */
{"movzbq", 2, 0x0fb6, X, Cpu64, NoSuf|Modrm|Rex64, { Reg8|ByteMem, Reg64, 0} },
{"movzwq", 2, 0x0fb7, X, Cpu64, NoSuf|Modrm|Rex64, { Reg16|ShortMem, Reg64, 0} },
-/* Intel Syntax next 4 insns */
+/* Intel Syntax next 2 insns (the 64-bit variants are not particulary useful,
+ since the zero extend 32->64 is implicit, but we can encode them). */
{"movzx", 2, 0x0fb6, X, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, WordReg, 0} },
-{"movzx", 2, 0x0fb7, X, Cpu386, w_Suf|Modrm, { Reg16|ShortMem, Reg32, 0} },
-/* These instructions are not particulary usefull, since the zero extend
- 32->64 is implicit, but we can encode them. */
-{"movzx", 2, 0x0fb6, X, Cpu386, b_Suf|Modrm|Rex64, { Reg8|ByteMem, Reg64, 0} },
-{"movzx", 2, 0x0fb7, X, Cpu386, w_Suf|Modrm|Rex64, { Reg16|ShortMem, Reg64, 0} },
+{"movzx", 2, 0x0fb7, X, Cpu386, w_Suf|Modrm, { Reg16|ShortMem, Reg32|Reg64, 0} },
/* Push instructions. */
{"push", 1, 0x50, X, CpuNo64, wl_Suf|ShortForm|DefaultSize, { WordReg, 0, 0 } },
{"push", 1, 0xff, 6, CpuNo64, wl_Suf|Modrm|DefaultSize, { WordReg|WordMem, 0, 0 } },
{"push", 1, 0x6a, X, Cpu186|CpuNo64, wl_Suf|DefaultSize, { Imm8S, 0, 0} },
{"push", 1, 0x68, X, Cpu186|CpuNo64, wl_Suf|DefaultSize, { Imm16|Imm32, 0, 0} },
-{"push", 1, 0x06, X, 0|CpuNo64, wl_Suf|Seg2ShortForm|DefaultSize, { SReg2, 0, 0 } },
+{"push", 1, 0x06, X, CpuNo64, wl_Suf|Seg2ShortForm|DefaultSize, { SReg2, 0, 0 } },
{"push", 1, 0x0fa0, X, Cpu386|CpuNo64, wl_Suf|Seg3ShortForm|DefaultSize, { SReg3, 0, 0 } },
/* In 64bit mode, the operand size is implicitly 64bit. */
-{"push", 1, 0x50, X, Cpu64, wq_Suf|ShortForm|DefaultSize|NoRex64, { WordReg, 0, 0 } },
-{"push", 1, 0xff, 6, Cpu64, wq_Suf|Modrm|DefaultSize|NoRex64, { WordReg|WordMem, 0, 0 } },
-{"push", 1, 0x6a, X, Cpu186|Cpu64, wq_Suf|DefaultSize|NoRex64, { Imm8S, 0, 0} },
-{"push", 1, 0x68, X, Cpu186|Cpu64, wq_Suf|DefaultSize|NoRex64, { Imm32S|Imm16, 0, 0} },
-{"push", 1, 0x06, X, Cpu64, wq_Suf|Seg2ShortForm|DefaultSize|NoRex64, { SReg2, 0, 0 } },
-{"push", 1, 0x0fa0, X, Cpu386|Cpu64, wq_Suf|Seg3ShortForm|DefaultSize|NoRex64, { SReg3, 0, 0 } },
+{"push", 1, 0x50, X, Cpu64, wq_Suf|ShortForm|DefaultSize|NoRex64, { Reg16|Reg64, 0, 0 } },
+{"push", 1, 0xff, 6, Cpu64, wq_Suf|Modrm|DefaultSize|NoRex64, { Reg16|Reg64|WordMem, 0, 0 } },
+{"push", 1, 0x6a, X, Cpu64, wq_Suf|DefaultSize|NoRex64, { Imm8S, 0, 0} },
+{"push", 1, 0x68, X, Cpu64, wq_Suf|DefaultSize|NoRex64, { Imm32S|Imm16, 0, 0} },
+{"push", 1, 0x0fa0, X, Cpu64, wq_Suf|Seg3ShortForm|DefaultSize|NoRex64, { SReg3, 0, 0 } },
{"pusha", 0, 0x60, X, Cpu186|CpuNo64, wl_Suf|DefaultSize, { 0, 0, 0 } },
@@ -165,9 +167,8 @@ static const template i386_optab[] = {
{"pop", 1, 0x07, X, CpuNo64, wl_Suf|Seg2ShortForm|DefaultSize, { SReg2, 0, 0 } },
{"pop", 1, 0x0fa1, X, Cpu386|CpuNo64, wl_Suf|Seg3ShortForm|DefaultSize, { SReg3, 0, 0 } },
/* In 64bit mode, the operand size is implicitly 64bit. */
-{"pop", 1, 0x58, X, Cpu64, wq_Suf|ShortForm|DefaultSize|NoRex64, { WordReg, 0, 0 } },
-{"pop", 1, 0x8f, 0, Cpu64, wq_Suf|Modrm|DefaultSize|NoRex64, { WordReg|WordMem, 0, 0 } },
-{"pop", 1, 0x07, X, Cpu64, wq_Suf|Seg2ShortForm|DefaultSize|NoRex64, { SReg2, 0, 0 } },
+{"pop", 1, 0x58, X, Cpu64, wq_Suf|ShortForm|DefaultSize|NoRex64, { Reg16|Reg64, 0, 0 } },
+{"pop", 1, 0x8f, 0, Cpu64, wq_Suf|Modrm|DefaultSize|NoRex64, { Reg16|Reg64|WordMem, 0, 0 } },
{"pop", 1, 0x0fa1, X, Cpu64, wq_Suf|Seg3ShortForm|DefaultSize|NoRex64, { SReg3, 0, 0 } },
{"popa", 0, 0x61, X, Cpu186|CpuNo64, wl_Suf|DefaultSize, { 0, 0, 0 } },
@@ -175,14 +176,24 @@ static const template i386_optab[] = {
/* Exchange instructions.
xchg commutes: we allow both operand orders.
- In the 64bit code, xchg eax, eax is reused for new nop instruction.
- */
+ In the 64bit code, xchg eax, eax is reused for new nop instruction. */
+#if 0 /* While the two entries that are disabled generate shorter code
+ for xchg eax, reg (on x86_64), the special case xchg eax, eax
+ does not get handled correctly - it degenerates into nop, but
+ that way the side effect of zero-extending eax to rax is lost. */
{"xchg", 2, 0x90, X, 0, wlq_Suf|ShortForm, { WordReg, Acc, 0 } },
{"xchg", 2, 0x90, X, 0, wlq_Suf|ShortForm, { Acc, WordReg, 0 } },
+#else
+{"xchg", 2, 0x90, X, CpuNo64, wl_Suf|ShortForm, { WordReg, Acc, 0 } },
+{"xchg", 2, 0x90, X, CpuNo64, wl_Suf|ShortForm, { Acc, WordReg, 0 } },
+{"xchg", 2, 0x90, X, Cpu64, wq_Suf|ShortForm, { Reg16|Reg64, Acc, 0 } },
+{"xchg", 2, 0x90, X, Cpu64, wq_Suf|ShortForm, { Acc, Reg16|Reg64, 0 } },
+#endif
{"xchg", 2, 0x86, X, 0, bwlq_Suf|W|Modrm, { Reg, Reg|AnyMem, 0 } },
{"xchg", 2, 0x86, X, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, Reg, 0 } },
/* In/out from ports. */
+/* XXX should reject %rax */
{"in", 2, 0xe4, X, 0, bwl_Suf|W, { Imm8, Acc, 0 } },
{"in", 2, 0xec, X, 0, bwl_Suf|W, { InOutPortReg, Acc, 0 } },
{"in", 1, 0xe4, X, 0, bwl_Suf|W, { Imm8, 0, 0 } },
@@ -196,11 +207,11 @@ static const template i386_optab[] = {
{"lea", 2, 0x8d, X, 0, wlq_Suf|Modrm, { WordMem, WordReg, 0 } },
/* Load segment registers from memory. */
-{"lds", 2, 0xc5, X, CpuNo64, wlq_Suf|Modrm, { WordMem, WordReg, 0} },
-{"les", 2, 0xc4, X, CpuNo64, wlq_Suf|Modrm, { WordMem, WordReg, 0} },
-{"lfs", 2, 0x0fb4, X, Cpu386, wlq_Suf|Modrm, { WordMem, WordReg, 0} },
-{"lgs", 2, 0x0fb5, X, Cpu386, wlq_Suf|Modrm, { WordMem, WordReg, 0} },
-{"lss", 2, 0x0fb2, X, Cpu386, wlq_Suf|Modrm, { WordMem, WordReg, 0} },
+{"lds", 2, 0xc5, X, CpuNo64, wl_Suf|Modrm, { WordMem, WordReg, 0} },
+{"les", 2, 0xc4, X, CpuNo64, wl_Suf|Modrm, { WordMem, WordReg, 0} },
+{"lfs", 2, 0x0fb4, X, Cpu386, wl_Suf|Modrm, { WordMem, WordReg, 0} },
+{"lgs", 2, 0x0fb5, X, Cpu386, wl_Suf|Modrm, { WordMem, WordReg, 0} },
+{"lss", 2, 0x0fb2, X, Cpu386, wl_Suf|Modrm, { WordMem, WordReg, 0} },
/* Flags register instructions. */
{"clc", 0, 0xf8, X, 0, NoSuf, { 0, 0, 0} },
@@ -208,11 +219,11 @@ static const template i386_optab[] = {
{"cli", 0, 0xfa, X, 0, NoSuf, { 0, 0, 0} },
{"clts", 0, 0x0f06, X, Cpu286, NoSuf, { 0, 0, 0} },
{"cmc", 0, 0xf5, X, 0, NoSuf, { 0, 0, 0} },
-{"lahf", 0, 0x9f, X, CpuNo64,NoSuf, { 0, 0, 0} },
-{"sahf", 0, 0x9e, X, CpuNo64,NoSuf, { 0, 0, 0} },
-{"pushf", 0, 0x9c, X, CpuNo64,wlq_Suf|DefaultSize, { 0, 0, 0} },
+{"lahf", 0, 0x9f, X, 0, NoSuf, { 0, 0, 0} },
+{"sahf", 0, 0x9e, X, 0, NoSuf, { 0, 0, 0} },
+{"pushf", 0, 0x9c, X, CpuNo64,wl_Suf|DefaultSize, { 0, 0, 0} },
{"pushf", 0, 0x9c, X, Cpu64, wq_Suf|DefaultSize|NoRex64,{ 0, 0, 0} },
-{"popf", 0, 0x9d, X, CpuNo64,wlq_Suf|DefaultSize, { 0, 0, 0} },
+{"popf", 0, 0x9d, X, CpuNo64,wl_Suf|DefaultSize, { 0, 0, 0} },
{"popf", 0, 0x9d, X, Cpu64, wq_Suf|DefaultSize|NoRex64,{ 0, 0, 0} },
{"stc", 0, 0xf9, X, 0, NoSuf, { 0, 0, 0} },
{"std", 0, 0xfd, X, 0, NoSuf, { 0, 0, 0} },
@@ -276,14 +287,14 @@ static const template i386_optab[] = {
{"neg", 1, 0xf6, 3, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
{"not", 1, 0xf6, 2, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
-{"aaa", 0, 0x37, X, 0, NoSuf, { 0, 0, 0} },
-{"aas", 0, 0x3f, X, 0, NoSuf, { 0, 0, 0} },
-{"daa", 0, 0x27, X, 0, NoSuf, { 0, 0, 0} },
-{"das", 0, 0x2f, X, 0, NoSuf, { 0, 0, 0} },
-{"aad", 0, 0xd50a, X, 0, NoSuf, { 0, 0, 0} },
-{"aad", 1, 0xd5, X, 0, NoSuf, { Imm8S, 0, 0} },
-{"aam", 0, 0xd40a, X, 0, NoSuf, { 0, 0, 0} },
-{"aam", 1, 0xd4, X, 0, NoSuf, { Imm8S, 0, 0} },
+{"aaa", 0, 0x37, X, CpuNo64, NoSuf, { 0, 0, 0} },
+{"aas", 0, 0x3f, X, CpuNo64, NoSuf, { 0, 0, 0} },
+{"daa", 0, 0x27, X, CpuNo64, NoSuf, { 0, 0, 0} },
+{"das", 0, 0x2f, X, CpuNo64, NoSuf, { 0, 0, 0} },
+{"aad", 0, 0xd50a, X, CpuNo64, NoSuf, { 0, 0, 0} },
+{"aad", 1, 0xd5, X, CpuNo64, NoSuf, { Imm8S, 0, 0} },
+{"aam", 0, 0xd40a, X, CpuNo64, NoSuf, { 0, 0, 0} },
+{"aam", 1, 0xd4, X, CpuNo64, NoSuf, { Imm8S, 0, 0} },
/* Conversion insns. */
/* Intel naming */
@@ -370,37 +381,38 @@ static const template i386_optab[] = {
{"shrd", 2, 0x0fad, X, Cpu386, wlq_Suf|Modrm, { WordReg, WordReg|WordMem, 0} },
/* Control transfer instructions. */
-{"call", 1, 0xe8, X, 0, wlq_Suf|JumpDword|DefaultSize, { Disp16|Disp32, 0, 0} },
+{"call", 1, 0xe8, X, CpuNo64, wl_Suf|JumpDword|DefaultSize, { Disp16|Disp32, 0, 0} },
+{"call", 1, 0xe8, X, Cpu64, wq_Suf|JumpDword|DefaultSize|NoRex64, { Disp16|Disp32, 0, 0} },
{"call", 1, 0xff, 2, CpuNo64, wl_Suf|Modrm|DefaultSize, { WordReg|WordMem|JumpAbsolute, 0, 0} },
-{"call", 1, 0xff, 2, Cpu64, wq_Suf|Modrm|DefaultSize|NoRex64,{ WordReg|WordMem|JumpAbsolute, 0, 0} },
+{"call", 1, 0xff, 2, Cpu64, wq_Suf|Modrm|DefaultSize|NoRex64, { Reg16|Reg64|WordMem|LLongMem|JumpAbsolute, 0, 0} },
/* Intel Syntax */
-{"call", 2, 0x9a, X, CpuNo64,wlq_Suf|JumpInterSegment|DefaultSize, { Imm16, Imm16|Imm32, 0} },
+{"call", 2, 0x9a, X, CpuNo64, wl_Suf|JumpInterSegment|DefaultSize, { Imm16, Imm16|Imm32, 0} },
/* Intel Syntax */
-{"call", 1, 0xff, 3, 0, x_Suf|Modrm|DefaultSize, { WordMem, 0, 0} },
-{"lcall", 2, 0x9a, X, CpuNo64, wl_Suf|JumpInterSegment|DefaultSize, { Imm16, Imm16|Imm32, 0} },
-{"lcall", 1, 0xff, 3, CpuNo64, wl_Suf|Modrm|DefaultSize, { WordMem|JumpAbsolute, 0, 0} },
-{"lcall", 1, 0xff, 3, Cpu64, q_Suf|Modrm|DefaultSize|NoRex64,{ WordMem|JumpAbsolute, 0, 0} },
+{"call", 1, 0xff, 3, 0, x_Suf|Modrm|DefaultSize, {WordMem|JumpAbsolute, 0, 0} },
+{"lcall", 2, 0x9a, X, CpuNo64, wl_Suf|JumpInterSegment|DefaultSize, {Imm16, Imm16|Imm32, 0} },
+{"lcall", 1, 0xff, 3, 0, wl_Suf|Modrm|DefaultSize, {WordMem|JumpAbsolute, 0, 0} },
#define JUMP_PC_RELATIVE 0xeb
-{"jmp", 1, 0xeb, X, 0, NoSuf|Jump, { Disp, 0, 0} },
+{"jmp", 1, 0xeb, X, 0, NoSuf|Jump, { Disp,0, 0} },
{"jmp", 1, 0xff, 4, CpuNo64, wl_Suf|Modrm, { WordReg|WordMem|JumpAbsolute, 0, 0} },
-{"jmp", 1, 0xff, 4, Cpu64, wq_Suf|Modrm|NoRex64, { WordReg|WordMem|JumpAbsolute, 0, 0} },
-/* Intel Syntax */
+{"jmp", 1, 0xff, 4, Cpu64, wq_Suf|Modrm|NoRex64, { Reg16|Reg64|ShortMem|LLongMem|JumpAbsolute, 0, 0} },
+/* Intel Syntax. */
{"jmp", 2, 0xea, X, CpuNo64,wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} },
-/* Intel Syntax */
-{"jmp", 1, 0xff, 5, 0, x_Suf|Modrm, { WordMem, 0, 0} },
-{"ljmp", 2, 0xea, X, CpuNo64, wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} },
-{"ljmp", 1, 0xff, 5, CpuNo64, wl_Suf|Modrm, { WordMem|JumpAbsolute, 0, 0} },
-{"ljmp", 1, 0xff, 5, Cpu64, q_Suf|Modrm|NoRex64, { WordMem|JumpAbsolute, 0, 0} },
-
-{"ret", 0, 0xc3, X, CpuNo64,wlq_Suf|DefaultSize, { 0, 0, 0} },
-{"ret", 1, 0xc2, X, CpuNo64,wlq_Suf|DefaultSize, { Imm16, 0, 0} },
-{"ret", 0, 0xc3, X, Cpu64, q_Suf|DefaultSize|NoRex64,{ 0, 0, 0} },
-{"ret", 1, 0xc2, X, Cpu64, q_Suf|DefaultSize|NoRex64,{ Imm16, 0, 0} },
+/* Intel Syntax. */
+{"jmp", 1, 0xff, 5, 0, x_Suf|Modrm, { WordMem|JumpAbsolute, 0, 0} },
+{"ljmp", 2, 0xea, X, CpuNo64, wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} },
+{"ljmp", 1, 0xff, 5, 0, wl_Suf|Modrm, { WordMem|JumpAbsolute, 0, 0} },
+
+{"ret", 0, 0xc3, X, CpuNo64,wl_Suf|DefaultSize, { 0, 0, 0} },
+{"ret", 1, 0xc2, X, CpuNo64,wl_Suf|DefaultSize, { Imm16, 0, 0} },
+{"ret", 0, 0xc3, X, Cpu64, wq_Suf|DefaultSize|NoRex64,{ 0, 0, 0} },
+{"ret", 1, 0xc2, X, Cpu64, wq_Suf|DefaultSize|NoRex64,{ Imm16, 0, 0} },
{"lret", 0, 0xcb, X, 0, wlq_Suf|DefaultSize, { 0, 0, 0} },
{"lret", 1, 0xca, X, 0, wlq_Suf|DefaultSize, { Imm16, 0, 0} },
-{"enter", 2, 0xc8, X, Cpu186, wlq_Suf|DefaultSize, { Imm16, Imm8, 0} },
-{"leave", 0, 0xc9, X, Cpu186, wlq_Suf|DefaultSize, { 0, 0, 0} },
+{"enter", 2, 0xc8, X, Cpu186|CpuNo64, wl_Suf|DefaultSize, { Imm16, Imm8, 0} },
+{"enter", 2, 0xc8, X, Cpu64, wq_Suf|DefaultSize|NoRex64, { Imm16, Imm8, 0} },
+{"leave", 0, 0xc9, X, Cpu186|CpuNo64, wl_Suf|DefaultSize, { 0, 0, 0} },
+{"leave", 0, 0xc9, X, Cpu64, wq_Suf|DefaultSize|NoRex64, { 0, 0, 0} },
/* Conditional jumps. */
{"jo", 1, 0x70, X, 0, NoSuf|Jump, { Disp, 0, 0} },
@@ -536,33 +548,37 @@ static const template i386_optab[] = {
/* Interrupts & op. sys insns. */
/* See gas/config/tc-i386.c for conversion of 'int $3' into the special
int 3 insn. */
-#define INT_OPCODE 0xcd
+#define INT_OPCODE 0xcd
#define INT3_OPCODE 0xcc
{"int", 1, 0xcd, X, 0, NoSuf, { Imm8, 0, 0} },
{"int3", 0, 0xcc, X, 0, NoSuf, { 0, 0, 0} },
-{"into", 0, 0xce, X, 0, NoSuf, { 0, 0, 0} },
+{"into", 0, 0xce, X, CpuNo64, NoSuf, { 0, 0, 0} },
{"iret", 0, 0xcf, X, 0, wlq_Suf|DefaultSize, { 0, 0, 0} },
/* i386sl, i486sl, later 486, and Pentium. */
{"rsm", 0, 0x0faa, X, Cpu386, NoSuf, { 0, 0, 0} },
-{"bound", 2, 0x62, X, Cpu186, wlq_Suf|Modrm, { WordReg, WordMem, 0} },
+{"bound", 2, 0x62, X, Cpu186|CpuNo64, wl_Suf|Modrm, { WordReg, WordMem, 0} },
{"hlt", 0, 0xf4, X, 0, NoSuf, { 0, 0, 0} },
/* nop is actually 'xchgl %eax, %eax'. */
{"nop", 0, 0x90, X, 0, NoSuf, { 0, 0, 0} },
/* Protection control. */
-{"arpl", 2, 0x63, X, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16, Reg16|ShortMem, 0} },
+{"arpl", 2, 0x63, X, Cpu286|CpuNo64, w_Suf|Modrm|IgnoreSize,{ Reg16, Reg16|ShortMem, 0} },
{"lar", 2, 0x0f02, X, Cpu286, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
-{"lgdt", 1, 0x0f01, 2, Cpu286, wlq_Suf|Modrm, { WordMem, 0, 0} },
-{"lidt", 1, 0x0f01, 3, Cpu286, wlq_Suf|Modrm, { WordMem, 0, 0} },
+{"lgdt", 1, 0x0f01, 2, Cpu286|CpuNo64, wl_Suf|Modrm, { WordMem, 0, 0} },
+{"lgdt", 1, 0x0f01, 2, Cpu64, q_Suf|Modrm|NoRex64, { LLongMem, 0, 0} },
+{"lidt", 1, 0x0f01, 3, Cpu286|CpuNo64, wl_Suf|Modrm, { WordMem, 0, 0} },
+{"lidt", 1, 0x0f01, 3, Cpu64, q_Suf|Modrm|NoRex64, { LLongMem, 0, 0} },
{"lldt", 1, 0x0f00, 2, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
{"lmsw", 1, 0x0f01, 6, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
{"lsl", 2, 0x0f03, X, Cpu286, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
{"ltr", 1, 0x0f00, 3, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
-{"sgdt", 1, 0x0f01, 0, Cpu286, wlq_Suf|Modrm, { WordMem, 0, 0} },
-{"sidt", 1, 0x0f01, 1, Cpu286, wlq_Suf|Modrm, { WordMem, 0, 0} },
+{"sgdt", 1, 0x0f01, 0, Cpu286|CpuNo64, wl_Suf|Modrm, { WordMem, 0, 0} },
+{"sgdt", 1, 0x0f01, 0, Cpu64, q_Suf|Modrm|NoRex64, { LLongMem, 0, 0} },
+{"sidt", 1, 0x0f01, 1, Cpu286|CpuNo64, wl_Suf|Modrm, { WordMem, 0, 0} },
+{"sidt", 1, 0x0f01, 1, Cpu64, q_Suf|Modrm|NoRex64, { LLongMem, 0, 0} },
{"sldt", 1, 0x0f00, 0, Cpu286, wlq_Suf|Modrm, { WordReg|InvMem, 0, 0} },
{"sldt", 1, 0x0f00, 0, Cpu286, w_Suf|Modrm|IgnoreSize,{ ShortMem, 0, 0} },
{"smsw", 1, 0x0f01, 4, Cpu286, wlq_Suf|Modrm, { WordReg|InvMem, 0, 0} },
@@ -577,37 +593,33 @@ static const template i386_optab[] = {
/* load */
{"fld", 1, 0xd9c0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
-{"fld", 1, 0xd9, 0, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} },
-{"fld", 1, 0xd9c0, X, 0, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} },
+{"fld", 1, 0xd9, 0, 0, sl_FP|Modrm, { LongMem|LLongMem, 0, 0} },
+{"fld", 1, 0xd9c0, X, 0, l_FP|ShortForm|IgnoreSize|Ugh, { FloatReg, 0, 0} },
/* Intel Syntax */
{"fld", 1, 0xdb, 5, 0, x_FP|Modrm, { LLongMem, 0, 0} },
-{"fild", 1, 0xdf, 0, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },
-/* Intel Syntax */
-{"fildd", 1, 0xdf, 5, 0, FP|Modrm, { LLongMem, 0, 0} },
-{"fildq", 1, 0xdf, 5, 0, FP|Modrm, { LLongMem, 0, 0} },
+{"fild", 1, 0xdf, 0, 0, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} },
+{"fild", 1, 0xdf, 5, 0, q_FP|Modrm, { LLongMem, 0, 0} },
{"fildll", 1, 0xdf, 5, 0, FP|Modrm, { LLongMem, 0, 0} },
{"fldt", 1, 0xdb, 5, 0, FP|Modrm, { LLongMem, 0, 0} },
-{"fbld", 1, 0xdf, 4, 0, FP|Modrm, { LLongMem, 0, 0} },
+{"fbld", 1, 0xdf, 4, 0, x_Suf|Modrm, { LLongMem, 0, 0} },
/* store (no pop) */
{"fst", 1, 0xddd0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
-{"fst", 1, 0xd9, 2, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} },
-{"fst", 1, 0xddd0, X, 0, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} },
-{"fist", 1, 0xdf, 2, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },
+{"fst", 1, 0xd9, 2, 0, sl_FP|Modrm, { LongMem|LLongMem, 0, 0} },
+{"fst", 1, 0xddd0, X, 0, l_FP|ShortForm|IgnoreSize|Ugh, { FloatReg, 0, 0} },
+{"fist", 1, 0xdf, 2, 0, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} },
/* store (with pop) */
{"fstp", 1, 0xddd8, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
-{"fstp", 1, 0xd9, 3, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} },
-{"fstp", 1, 0xddd8, X, 0, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} },
+{"fstp", 1, 0xd9, 3, 0, sl_FP|Modrm, { LongMem|LLongMem, 0, 0} },
+{"fstp", 1, 0xddd8, X, 0, l_FP|ShortForm|IgnoreSize|Ugh, { FloatReg, 0, 0} },
/* Intel Syntax */
{"fstp", 1, 0xdb, 7, 0, x_FP|Modrm, { LLongMem, 0, 0} },
-{"fistp", 1, 0xdf, 3, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },
-/* Intel Syntax */
-{"fistpd", 1, 0xdf, 7, 0, FP|Modrm, { LLongMem, 0, 0} },
-{"fistpq", 1, 0xdf, 7, 0, FP|Modrm, { LLongMem, 0, 0} },
+{"fistp", 1, 0xdf, 3, 0, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} },
+{"fistp", 1, 0xdf, 7, 0, q_FP|Modrm, { LLongMem, 0, 0} },
{"fistpll",1, 0xdf, 7, 0, FP|Modrm, { LLongMem, 0, 0} },
{"fstpt", 1, 0xdb, 7, 0, FP|Modrm, { LLongMem, 0, 0} },
-{"fbstp", 1, 0xdf, 6, 0, FP|Modrm, { LLongMem, 0, 0} },
+{"fbstp", 1, 0xdf, 6, 0, x_Suf|Modrm, { LLongMem, 0, 0} },
/* exchange %st<n> with %st0 */
{"fxch", 1, 0xd9c8, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
@@ -618,17 +630,17 @@ static const template i386_optab[] = {
{"fcom", 1, 0xd8d0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
/* alias for fcom %st(1) */
{"fcom", 0, 0xd8d1, X, 0, FP, { 0, 0, 0} },
-{"fcom", 1, 0xd8, 2, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} },
-{"fcom", 1, 0xd8d0, X, 0, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} },
-{"ficom", 1, 0xde, 2, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },
+{"fcom", 1, 0xd8, 2, 0, sl_FP|Modrm, { LongMem|LLongMem, 0, 0} },
+{"fcom", 1, 0xd8d0, X, 0, l_FP|ShortForm|IgnoreSize|Ugh, { FloatReg, 0, 0} },
+{"ficom", 1, 0xde, 2, 0, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} },
/* comparison (with pop) */
{"fcomp", 1, 0xd8d8, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
/* alias for fcomp %st(1) */
{"fcomp", 0, 0xd8d9, X, 0, FP, { 0, 0, 0} },
-{"fcomp", 1, 0xd8, 3, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} },
-{"fcomp", 1, 0xd8d8, X, 0, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} },
-{"ficomp", 1, 0xde, 3, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },
+{"fcomp", 1, 0xd8, 3, 0, sl_FP|Modrm, { LongMem|LLongMem, 0, 0} },
+{"fcomp", 1, 0xd8d8, X, 0, l_FP|ShortForm|IgnoreSize|Ugh, { FloatReg, 0, 0} },
+{"ficomp", 1, 0xde, 3, 0, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} },
{"fcompp", 0, 0xded9, X, 0, FP, { 0, 0, 0} },
/* unordered comparison (with pop) */
@@ -652,7 +664,7 @@ static const template i386_optab[] = {
{"fldln2", 0, 0xd9ed, X, 0, FP, { 0, 0, 0} },
{"fldz", 0, 0xd9ee, X, 0, FP, { 0, 0, 0} },
-/* arithmetic */
+/* Arithmetic. */
/* add */
{"fadd", 2, 0xd8c0, X, 0, FP|ShortForm|FloatD, { FloatReg, FloatAcc, 0} },
@@ -662,8 +674,8 @@ static const template i386_optab[] = {
/* alias for faddp */
{"fadd", 0, 0xdec1, X, 0, FP|Ugh, { 0, 0, 0} },
#endif
-{"fadd", 1, 0xd8, 0, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} },
-{"fiadd", 1, 0xde, 0, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },
+{"fadd", 1, 0xd8, 0, 0, sl_FP|Modrm, { LongMem|LLongMem, 0, 0} },
+{"fiadd", 1, 0xde, 0, 0, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} },
{"faddp", 2, 0xdec0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} },
{"faddp", 1, 0xdec0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
@@ -678,8 +690,8 @@ static const template i386_optab[] = {
/* alias for fsubp */
{"fsub", 0, 0xdee1, X, 0, FP|Ugh, { 0, 0, 0} },
#endif
-{"fsub", 1, 0xd8, 4, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} },
-{"fisub", 1, 0xde, 4, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },
+{"fsub", 1, 0xd8, 4, 0, sl_FP|Modrm, { LongMem|LLongMem, 0, 0} },
+{"fisub", 1, 0xde, 4, 0, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} },
#if SYSV386_COMPAT
{"fsubp", 2, 0xdee0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} },
@@ -701,8 +713,8 @@ static const template i386_optab[] = {
/* alias for fsubrp */
{"fsubr", 0, 0xdee9, X, 0, FP|Ugh, { 0, 0, 0} },
#endif
-{"fsubr", 1, 0xd8, 5, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} },
-{"fisubr", 1, 0xde, 5, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },
+{"fsubr", 1, 0xd8, 5, 0, sl_FP|Modrm, { LongMem|LLongMem, 0, 0} },
+{"fisubr", 1, 0xde, 5, 0, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} },
#if SYSV386_COMPAT
{"fsubrp", 2, 0xdee8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} },
@@ -724,8 +736,8 @@ static const template i386_optab[] = {
/* alias for fmulp */
{"fmul", 0, 0xdec9, X, 0, FP|Ugh, { 0, 0, 0} },
#endif
-{"fmul", 1, 0xd8, 1, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} },
-{"fimul", 1, 0xde, 1, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },
+{"fmul", 1, 0xd8, 1, 0, sl_FP|Modrm, { LongMem|LLongMem, 0, 0} },
+{"fimul", 1, 0xde, 1, 0, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} },
{"fmulp", 2, 0xdec8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} },
{"fmulp", 1, 0xdec8, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
@@ -739,8 +751,8 @@ static const template i386_optab[] = {
/* alias for fdivp */
{"fdiv", 0, 0xdef1, X, 0, FP|Ugh, { 0, 0, 0} },
#endif
-{"fdiv", 1, 0xd8, 6, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} },
-{"fidiv", 1, 0xde, 6, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },
+{"fdiv", 1, 0xd8, 6, 0, sl_FP|Modrm, { LongMem|LLongMem, 0, 0} },
+{"fidiv", 1, 0xde, 6, 0, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} },
#if SYSV386_COMPAT
{"fdivp", 2, 0xdef0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} },
@@ -762,8 +774,8 @@ static const template i386_optab[] = {
/* alias for fdivrp */
{"fdivr", 0, 0xdef9, X, 0, FP|Ugh, { 0, 0, 0} },
#endif
-{"fdivr", 1, 0xd8, 7, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} },
-{"fidivr", 1, 0xde, 7, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },
+{"fdivr", 1, 0xd8, 7, 0, sl_FP|Modrm, { LongMem|LLongMem, 0, 0} },
+{"fidivr", 1, 0xde, 7, 0, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} },
#if SYSV386_COMPAT
{"fdivrp", 2, 0xdef8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} },
@@ -800,24 +812,26 @@ static const template i386_optab[] = {
/* processor control */
{"fninit", 0, 0xdbe3, X, 0, FP, { 0, 0, 0} },
{"finit", 0, 0xdbe3, X, 0, FP|FWait, { 0, 0, 0} },
-{"fldcw", 1, 0xd9, 5, 0, FP|Modrm, { ShortMem, 0, 0} },
-{"fnstcw", 1, 0xd9, 7, 0, FP|Modrm, { ShortMem, 0, 0} },
-{"fstcw", 1, 0xd9, 7, 0, FP|FWait|Modrm, { ShortMem, 0, 0} },
-{"fnstsw", 1, 0xdfe0, X, 0, FP, { Acc, 0, 0} },
-{"fnstsw", 1, 0xdd, 7, 0, FP|Modrm, { ShortMem, 0, 0} },
+{"fldcw", 1, 0xd9, 5, 0, w_Suf|FloatMF|Modrm, { ShortMem, 0, 0} },
+{"fnstcw", 1, 0xd9, 7, 0, w_Suf|FloatMF|Modrm, { ShortMem, 0, 0} },
+{"fstcw", 1, 0xd9, 7, 0, w_Suf|FloatMF|FWait|Modrm, { ShortMem, 0, 0} },
+/* XXX should reject %al, %eax, and %rax */
+{"fnstsw", 1, 0xdfe0, X, 0, FP|IgnoreSize, { Acc, 0, 0} },
+{"fnstsw", 1, 0xdd, 7, 0, w_Suf|FloatMF|Modrm, { ShortMem, 0, 0} },
{"fnstsw", 0, 0xdfe0, X, 0, FP, { 0, 0, 0} },
-{"fstsw", 1, 0xdfe0, X, 0, FP|FWait, { Acc, 0, 0} },
-{"fstsw", 1, 0xdd, 7, 0, FP|FWait|Modrm, { ShortMem, 0, 0} },
+/* XXX should reject %al, %eax, and %rax */
+{"fstsw", 1, 0xdfe0, X, 0, FP|FWait|IgnoreSize, { Acc, 0, 0} },
+{"fstsw", 1, 0xdd, 7, 0, w_Suf|FloatMF|FWait|Modrm, { ShortMem, 0, 0} },
{"fstsw", 0, 0xdfe0, X, 0, FP|FWait, { 0, 0, 0} },
{"fnclex", 0, 0xdbe2, X, 0, FP, { 0, 0, 0} },
{"fclex", 0, 0xdbe2, X, 0, FP|FWait, { 0, 0, 0} },
/* Short forms of fldenv, fstenv use data size prefix. */
-{"fnstenv",1, 0xd9, 6, 0, sl_Suf|Modrm, { LLongMem, 0, 0} },
-{"fstenv", 1, 0xd9, 6, 0, sl_Suf|FWait|Modrm, { LLongMem, 0, 0} },
-{"fldenv", 1, 0xd9, 4, 0, sl_Suf|Modrm, { LLongMem, 0, 0} },
-{"fnsave", 1, 0xdd, 6, 0, sl_Suf|Modrm, { LLongMem, 0, 0} },
-{"fsave", 1, 0xdd, 6, 0, sl_Suf|FWait|Modrm, { LLongMem, 0, 0} },
-{"frstor", 1, 0xdd, 4, 0, sl_Suf|Modrm, { LLongMem, 0, 0} },
+{"fnstenv",1, 0xd9, 6, 0, sl_Suf|Modrm|DefaultSize, { LLongMem, 0, 0} },
+{"fstenv", 1, 0xd9, 6, 0, sl_Suf|FWait|Modrm|DefaultSize, { LLongMem, 0, 0} },
+{"fldenv", 1, 0xd9, 4, 0, sl_Suf|Modrm|DefaultSize, { LLongMem, 0, 0} },
+{"fnsave", 1, 0xdd, 6, 0, sl_Suf|Modrm|DefaultSize, { LLongMem, 0, 0} },
+{"fsave", 1, 0xdd, 6, 0, sl_Suf|FWait|Modrm|DefaultSize, { LLongMem, 0, 0} },
+{"frstor", 1, 0xdd, 4, 0, sl_Suf|Modrm|DefaultSize, { LLongMem, 0, 0} },
{"ffree", 1, 0xddc0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
/* P6:free st(i), pop st */
@@ -829,30 +843,30 @@ static const template i386_optab[] = {
/* Opcode prefixes; we allow them as separate insns too. */
#define ADDR_PREFIX_OPCODE 0x67
-{"addr16", 0, 0x67, X, Cpu386, NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} },
-{"addr32", 0, 0x67, X, Cpu386, NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} },
-{"aword", 0, 0x67, X, Cpu386, NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} },
-{"adword", 0, 0x67, X, Cpu386, NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} },
+{"addr16", 0, 0x67, X, Cpu386|CpuNo64, NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} },
+{"addr32", 0, 0x67, X, Cpu386,NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} },
+{"aword", 0, 0x67, X, Cpu386|CpuNo64,NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} },
+{"adword", 0, 0x67, X, Cpu386,NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} },
#define DATA_PREFIX_OPCODE 0x66
-{"data16", 0, 0x66, X, Cpu386, NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} },
-{"data32", 0, 0x66, X, Cpu386, NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} },
-{"word", 0, 0x66, X, Cpu386, NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} },
-{"dword", 0, 0x66, X, Cpu386, NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} },
+{"data16", 0, 0x66, X, Cpu386,NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} },
+{"data32", 0, 0x66, X, Cpu386|CpuNo64,NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} },
+{"word", 0, 0x66, X, Cpu386,NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} },
+{"dword", 0, 0x66, X, Cpu386|CpuNo64,NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} },
#define LOCK_PREFIX_OPCODE 0xf0
{"lock", 0, 0xf0, X, 0, NoSuf|IsPrefix, { 0, 0, 0} },
{"wait", 0, 0x9b, X, 0, NoSuf|IsPrefix, { 0, 0, 0} },
#define CS_PREFIX_OPCODE 0x2e
-{"cs", 0, 0x2e, X, 0, NoSuf|IsPrefix, { 0, 0, 0} },
+{"cs", 0, 0x2e, X, 0, NoSuf|IsPrefix, { 0, 0, 0} },
#define DS_PREFIX_OPCODE 0x3e
-{"ds", 0, 0x3e, X, 0, NoSuf|IsPrefix, { 0, 0, 0} },
+{"ds", 0, 0x3e, X, 0, NoSuf|IsPrefix, { 0, 0, 0} },
#define ES_PREFIX_OPCODE 0x26
-{"es", 0, 0x26, X, 0, NoSuf|IsPrefix, { 0, 0, 0} },
+{"es", 0, 0x26, X, CpuNo64, NoSuf|IsPrefix, { 0, 0, 0} },
#define FS_PREFIX_OPCODE 0x64
{"fs", 0, 0x64, X, Cpu386, NoSuf|IsPrefix, { 0, 0, 0} },
#define GS_PREFIX_OPCODE 0x65
{"gs", 0, 0x65, X, Cpu386, NoSuf|IsPrefix, { 0, 0, 0} },
#define SS_PREFIX_OPCODE 0x36
-{"ss", 0, 0x36, X, 0, NoSuf|IsPrefix, { 0, 0, 0} },
+{"ss", 0, 0x36, X, CpuNo64, NoSuf|IsPrefix, { 0, 0, 0} },
#define REPNE_PREFIX_OPCODE 0xf2
#define REPE_PREFIX_OPCODE 0xf3
{"rep", 0, 0xf3, X, 0, NoSuf|IsPrefix, { 0, 0, 0} },
@@ -884,7 +898,7 @@ static const template i386_optab[] = {
{"cmpxchg", 2, 0x0fb0, X, Cpu486, bwlq_Suf|W|Modrm, { Reg, Reg|AnyMem, 0 } },
{"invd", 0, 0x0f08, X, Cpu486, NoSuf, { 0, 0, 0} },
{"wbinvd", 0, 0x0f09, X, Cpu486, NoSuf, { 0, 0, 0} },
-{"invlpg", 1, 0x0f01, 7, Cpu486, NoSuf|Modrm, { AnyMem, 0, 0} },
+{"invlpg", 1, 0x0f01, 7, Cpu486, NoSuf|Modrm|IgnoreSize, { AnyMem, 0, 0} },
/* 586 and late 486 extensions. */
{"cpuid", 0, 0x0fa2, X, Cpu486, NoSuf, { 0, 0, 0} },
@@ -893,13 +907,13 @@ static const template i386_optab[] = {
{"wrmsr", 0, 0x0f30, X, Cpu586, NoSuf, { 0, 0, 0} },
{"rdtsc", 0, 0x0f31, X, Cpu586, NoSuf, { 0, 0, 0} },
{"rdmsr", 0, 0x0f32, X, Cpu586, NoSuf, { 0, 0, 0} },
-{"cmpxchg8b",1,0x0fc7, 1, Cpu586, NoSuf|Modrm, { LLongMem, 0, 0} },
+{"cmpxchg8b",1,0x0fc7, 1, Cpu586, q_Suf|Modrm, { LLongMem, 0, 0} },
/* Pentium II/Pentium Pro extensions. */
{"sysenter",0, 0x0f34, X, Cpu686, NoSuf, { 0, 0, 0} },
{"sysexit", 0, 0x0f35, X, Cpu686, NoSuf, { 0, 0, 0} },
-{"fxsave", 1, 0x0fae, 0, Cpu686, FP|Modrm, { LLongMem, 0, 0} },
-{"fxrstor", 1, 0x0fae, 1, Cpu686, FP|Modrm, { LLongMem, 0, 0} },
+{"fxsave", 1, 0x0fae, 0, Cpu686, q_Suf|Modrm, { LLongMem, 0, 0} },
+{"fxrstor", 1, 0x0fae, 1, Cpu686, q_Suf|Modrm, { LLongMem, 0, 0} },
{"rdpmc", 0, 0x0f33, X, Cpu686, NoSuf, { 0, 0, 0} },
/* official undefined instr. */
{"ud2", 0, 0x0f0b, X, Cpu686, NoSuf, { 0, 0, 0} },
@@ -967,30 +981,25 @@ static const template i386_optab[] = {
/* Pentium4 extensions. */
-{"movnti", 2, 0x0fc3, X, CpuP4, FP|Modrm, { WordReg, WordMem, 0 } },
-{"clflush", 1, 0x0fae, 7, CpuP4, FP|Modrm, { ByteMem, 0, 0 } },
-{"lfence", 0, 0x0fae, 0xe8, CpuP4, FP|ImmExt, { 0, 0, 0 } },
-{"mfence", 0, 0x0fae, 0xf0, CpuP4, FP|ImmExt, { 0, 0, 0 } },
-{"pause", 0, 0xf390, X, CpuP4, FP, { 0, 0, 0 } },
+{"movnti", 2, 0x0fc3, X, CpuP4, wlq_Suf|Modrm, { WordReg, WordMem, 0 } },
+{"clflush", 1, 0x0fae, 7, CpuP4, NoSuf|Modrm|IgnoreSize, { ByteMem, 0, 0 } },
+{"lfence", 0, 0x0fae, 0xe8, CpuP4, NoSuf|ImmExt, { 0, 0, 0 } },
+{"mfence", 0, 0x0fae, 0xf0, CpuP4, NoSuf|ImmExt, { 0, 0, 0 } },
+{"pause", 0, 0xf390, X, CpuP4, NoSuf, { 0, 0, 0 } },
/* MMX/SSE2 instructions. */
-{"emms", 0, 0x0f77, X, CpuMMX, FP, { 0, 0, 0 } },
-{"movd", 2, 0x0f6e, X, CpuMMX, FP|Modrm, { Reg32|LongMem, RegMMX, 0 } },
-{"movd", 2, 0x0f7e, X, CpuMMX, FP|Modrm, { RegMMX, Reg32|LongMem, 0 } },
-{"movd", 2, 0x660f6e,X,CpuSSE2,FP|Modrm, { Reg32|LLongMem, RegXMM, 0 } },
-{"movd", 2, 0x660f7e,X,CpuSSE2,FP|Modrm, { RegXMM, Reg32|LLongMem, 0 } },
-/* Real MMX instructions. */
-{"movd", 2, 0x0f6e, X, CpuMMX, FP|Modrm, { Reg64|LLongMem, RegMMX, 0 } },
-{"movd", 2, 0x0f7e, X, CpuMMX, FP|Modrm, { RegMMX, Reg64|LLongMem, 0 } },
-{"movd", 2, 0x660f6e,X,CpuSSE2,FP|Modrm, { Reg64|LLongMem, RegXMM, 0 } },
-{"movd", 2, 0x660f7e,X,CpuSSE2,FP|Modrm, { RegXMM, Reg64|LLongMem, 0 } },
+{"emms", 0, 0x0f77, X, CpuMMX, NoSuf, { 0, 0, 0 } },
+{"movd", 2, 0x0f6e, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { Reg32|Reg64|LongMem, RegMMX, 0 } },
+{"movd", 2, 0x0f7e, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX, Reg32|Reg64|LongMem, 0 } },
+{"movd", 2, 0x660f6e,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { Reg32|Reg64|LLongMem, RegXMM, 0 } },
+{"movd", 2, 0x660f7e,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM, Reg32|Reg64|LLongMem, 0 } },
/* In the 64bit mode the short form mov immediate is redefined to have
64bit displacement value. */
-{"movq", 2, 0x0f6f, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
-{"movq", 2, 0x0f7f, X, CpuMMX, FP|Modrm, { RegMMX, RegMMX|LongMem, 0 } },
-{"movq", 2, 0xf30f7e,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"movq", 2, 0x660fd6,X,CpuSSE2,FP|Modrm, { RegXMM, RegXMM|LLongMem, 0 } },
+{"movq", 2, 0x0f6f, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
+{"movq", 2, 0x0f7f, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX, RegMMX|LongMem, 0 } },
+{"movq", 2, 0xf30f7e,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"movq", 2, 0x660fd6,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM|LLongMem, 0 } },
{"movq", 2, 0x88, X, Cpu64, NoSuf|D|W|Modrm|Size64,{ Reg64, Reg64|AnyMem, 0 } },
{"movq", 2, 0xc6, 0, Cpu64, NoSuf|W|Modrm|Size64, { Imm32S, Reg64|WordMem, 0 } },
{"movq", 2, 0xb0, X, Cpu64, NoSuf|W|ShortForm|Size64,{ Imm64, Reg64, 0 } },
@@ -998,377 +1007,381 @@ static const template i386_optab[] = {
mode they are 64bit.*/
{"movq", 2, 0x0f20, X, Cpu64, NoSuf|D|Modrm|IgnoreSize|NoRex64|Size64,{ Control, Reg64|InvMem, 0} },
{"movq", 2, 0x0f21, X, Cpu64, NoSuf|D|Modrm|IgnoreSize|NoRex64|Size64,{ Debug, Reg64|InvMem, 0} },
-{"packssdw", 2, 0x0f6b, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
-{"packssdw", 2, 0x660f6b,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"packsswb", 2, 0x0f63, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
-{"packsswb", 2, 0x660f63,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"packuswb", 2, 0x0f67, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
-{"packuswb", 2, 0x660f67,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"paddb", 2, 0x0ffc, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
-{"paddb", 2, 0x660ffc,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"paddw", 2, 0x0ffd, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
-{"paddw", 2, 0x660ffd,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"paddd", 2, 0x0ffe, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
-{"paddd", 2, 0x660ffe,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"paddq", 2, 0x0fd4, X, CpuMMX, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
-{"paddq", 2, 0x660fd4,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"paddsb", 2, 0x0fec, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
-{"paddsb", 2, 0x660fec,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"paddsw", 2, 0x0fed, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
-{"paddsw", 2, 0x660fed,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"paddusb", 2, 0x0fdc, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
-{"paddusb", 2, 0x660fdc,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"paddusw", 2, 0x0fdd, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
-{"paddusw", 2, 0x660fdd,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"pand", 2, 0x0fdb, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
-{"pand", 2, 0x660fdb,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"pandn", 2, 0x0fdf, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
-{"pandn", 2, 0x660fdf,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"pcmpeqb", 2, 0x0f74, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
-{"pcmpeqb", 2, 0x660f74,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"pcmpeqw", 2, 0x0f75, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
-{"pcmpeqw", 2, 0x660f75,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"pcmpeqd", 2, 0x0f76, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
-{"pcmpeqd", 2, 0x660f76,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"pcmpgtb", 2, 0x0f64, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
-{"pcmpgtb", 2, 0x660f64,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"pcmpgtw", 2, 0x0f65, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
-{"pcmpgtw", 2, 0x660f65,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"pcmpgtd", 2, 0x0f66, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
-{"pcmpgtd", 2, 0x660f66,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"pmaddwd", 2, 0x0ff5, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
-{"pmaddwd", 2, 0x660ff5,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"pmulhw", 2, 0x0fe5, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
-{"pmulhw", 2, 0x660fe5,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"pmullw", 2, 0x0fd5, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
-{"pmullw", 2, 0x660fd5,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"por", 2, 0x0feb, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
-{"por", 2, 0x660feb,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"psllw", 2, 0x0ff1, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
-{"psllw", 2, 0x660ff1,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"psllw", 2, 0x0f71, 6, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } },
-{"psllw", 2, 0x660f71,6,CpuSSE2,FP|Modrm, { Imm8, RegXMM, 0 } },
-{"pslld", 2, 0x0ff2, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
-{"pslld", 2, 0x660ff2,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"pslld", 2, 0x0f72, 6, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } },
-{"pslld", 2, 0x660f72,6,CpuSSE2,FP|Modrm, { Imm8, RegXMM, 0 } },
-{"psllq", 2, 0x0ff3, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
-{"psllq", 2, 0x660ff3,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"psllq", 2, 0x0f73, 6, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } },
-{"psllq", 2, 0x660f73,6,CpuSSE2,FP|Modrm, { Imm8, RegXMM, 0 } },
-{"psraw", 2, 0x0fe1, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
-{"psraw", 2, 0x660fe1,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"psraw", 2, 0x0f71, 4, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } },
-{"psraw", 2, 0x660f71,4,CpuSSE2,FP|Modrm, { Imm8, RegXMM, 0 } },
-{"psrad", 2, 0x0fe2, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
-{"psrad", 2, 0x660fe2,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"psrad", 2, 0x0f72, 4, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } },
-{"psrad", 2, 0x660f72,4,CpuSSE2,FP|Modrm, { Imm8, RegXMM, 0 } },
-{"psrlw", 2, 0x0fd1, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
-{"psrlw", 2, 0x660fd1,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"psrlw", 2, 0x0f71, 2, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } },
-{"psrlw", 2, 0x660f71,2,CpuSSE2,FP|Modrm, { Imm8, RegXMM, 0 } },
-{"psrld", 2, 0x0fd2, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
-{"psrld", 2, 0x660fd2,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"psrld", 2, 0x0f72, 2, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } },
-{"psrld", 2, 0x660f72,2,CpuSSE2,FP|Modrm, { Imm8, RegXMM, 0 } },
-{"psrlq", 2, 0x0fd3, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
-{"psrlq", 2, 0x660fd3,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"psrlq", 2, 0x0f73, 2, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } },
-{"psrlq", 2, 0x660f73,2,CpuSSE2,FP|Modrm, { Imm8, RegXMM, 0 } },
-{"psubb", 2, 0x0ff8, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
-{"psubb", 2, 0x660ff8,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"psubw", 2, 0x0ff9, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
-{"psubw", 2, 0x660ff9,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"psubd", 2, 0x0ffa, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
-{"psubd", 2, 0x660ffa,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"psubq", 2, 0x0ffb, X, CpuMMX, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
-{"psubq", 2, 0x660ffb,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"psubsb", 2, 0x0fe8, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
-{"psubsb", 2, 0x660fe8,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"psubsw", 2, 0x0fe9, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
-{"psubsw", 2, 0x660fe9,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"psubusb", 2, 0x0fd8, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
-{"psubusb", 2, 0x660fd8,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"psubusw", 2, 0x0fd9, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
-{"psubusw", 2, 0x660fd9,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"punpckhbw",2, 0x0f68, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
-{"punpckhbw",2, 0x660f68,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"punpckhwd",2, 0x0f69, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
-{"punpckhwd",2, 0x660f69,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"punpckhdq",2, 0x0f6a, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
-{"punpckhdq",2, 0x660f6a,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"punpcklbw",2, 0x0f60, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
-{"punpcklbw",2, 0x660f60,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"punpcklwd",2, 0x0f61, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
-{"punpcklwd",2, 0x660f61,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"punpckldq",2, 0x0f62, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
-{"punpckldq",2, 0x660f62,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"pxor", 2, 0x0fef, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
-{"pxor", 2, 0x660fef,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+/* Real MMX instructions. */
+{"packssdw", 2, 0x0f6b, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
+{"packssdw", 2, 0x660f6b,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"packsswb", 2, 0x0f63, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
+{"packsswb", 2, 0x660f63,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"packuswb", 2, 0x0f67, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
+{"packuswb", 2, 0x660f67,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"paddb", 2, 0x0ffc, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
+{"paddb", 2, 0x660ffc,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"paddw", 2, 0x0ffd, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
+{"paddw", 2, 0x660ffd,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"paddd", 2, 0x0ffe, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
+{"paddd", 2, 0x660ffe,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"paddq", 2, 0x0fd4, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
+{"paddq", 2, 0x660fd4,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"paddsb", 2, 0x0fec, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
+{"paddsb", 2, 0x660fec,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"paddsw", 2, 0x0fed, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
+{"paddsw", 2, 0x660fed,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"paddusb", 2, 0x0fdc, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
+{"paddusb", 2, 0x660fdc,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"paddusw", 2, 0x0fdd, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
+{"paddusw", 2, 0x660fdd,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"pand", 2, 0x0fdb, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
+{"pand", 2, 0x660fdb,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"pandn", 2, 0x0fdf, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
+{"pandn", 2, 0x660fdf,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"pcmpeqb", 2, 0x0f74, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
+{"pcmpeqb", 2, 0x660f74,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"pcmpeqw", 2, 0x0f75, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
+{"pcmpeqw", 2, 0x660f75,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"pcmpeqd", 2, 0x0f76, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
+{"pcmpeqd", 2, 0x660f76,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"pcmpgtb", 2, 0x0f64, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
+{"pcmpgtb", 2, 0x660f64,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"pcmpgtw", 2, 0x0f65, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
+{"pcmpgtw", 2, 0x660f65,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"pcmpgtd", 2, 0x0f66, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
+{"pcmpgtd", 2, 0x660f66,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"pmaddwd", 2, 0x0ff5, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
+{"pmaddwd", 2, 0x660ff5,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"pmulhw", 2, 0x0fe5, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
+{"pmulhw", 2, 0x660fe5,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"pmullw", 2, 0x0fd5, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
+{"pmullw", 2, 0x660fd5,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"por", 2, 0x0feb, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
+{"por", 2, 0x660feb,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"psllw", 2, 0x0ff1, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
+{"psllw", 2, 0x660ff1,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"psllw", 2, 0x0f71, 6, CpuMMX, NoSuf|IgnoreSize|Modrm, { Imm8, RegMMX, 0 } },
+{"psllw", 2, 0x660f71,6,CpuSSE2,NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM, 0 } },
+{"pslld", 2, 0x0ff2, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
+{"pslld", 2, 0x660ff2,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"pslld", 2, 0x0f72, 6, CpuMMX, NoSuf|IgnoreSize|Modrm, { Imm8, RegMMX, 0 } },
+{"pslld", 2, 0x660f72,6,CpuSSE2,NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM, 0 } },
+{"psllq", 2, 0x0ff3, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
+{"psllq", 2, 0x660ff3,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"psllq", 2, 0x0f73, 6, CpuMMX, NoSuf|IgnoreSize|Modrm, { Imm8, RegMMX, 0 } },
+{"psllq", 2, 0x660f73,6,CpuSSE2,NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM, 0 } },
+{"psraw", 2, 0x0fe1, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
+{"psraw", 2, 0x660fe1,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"psraw", 2, 0x0f71, 4, CpuMMX, NoSuf|IgnoreSize|Modrm, { Imm8, RegMMX, 0 } },
+{"psraw", 2, 0x660f71,4,CpuSSE2,NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM, 0 } },
+{"psrad", 2, 0x0fe2, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
+{"psrad", 2, 0x660fe2,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"psrad", 2, 0x0f72, 4, CpuMMX, NoSuf|IgnoreSize|Modrm, { Imm8, RegMMX, 0 } },
+{"psrad", 2, 0x660f72,4,CpuSSE2,NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM, 0 } },
+{"psrlw", 2, 0x0fd1, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
+{"psrlw", 2, 0x660fd1,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"psrlw", 2, 0x0f71, 2, CpuMMX, NoSuf|IgnoreSize|Modrm, { Imm8, RegMMX, 0 } },
+{"psrlw", 2, 0x660f71,2,CpuSSE2,NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM, 0 } },
+{"psrld", 2, 0x0fd2, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
+{"psrld", 2, 0x660fd2,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"psrld", 2, 0x0f72, 2, CpuMMX, NoSuf|IgnoreSize|Modrm, { Imm8, RegMMX, 0 } },
+{"psrld", 2, 0x660f72,2,CpuSSE2,NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM, 0 } },
+{"psrlq", 2, 0x0fd3, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
+{"psrlq", 2, 0x660fd3,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"psrlq", 2, 0x0f73, 2, CpuMMX, NoSuf|IgnoreSize|Modrm, { Imm8, RegMMX, 0 } },
+{"psrlq", 2, 0x660f73,2,CpuSSE2,NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM, 0 } },
+{"psubb", 2, 0x0ff8, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
+{"psubb", 2, 0x660ff8,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"psubw", 2, 0x0ff9, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
+{"psubw", 2, 0x660ff9,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"psubd", 2, 0x0ffa, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
+{"psubd", 2, 0x660ffa,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"psubq", 2, 0x0ffb, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
+{"psubq", 2, 0x660ffb,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"psubsb", 2, 0x0fe8, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
+{"psubsb", 2, 0x660fe8,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"psubsw", 2, 0x0fe9, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
+{"psubsw", 2, 0x660fe9,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"psubusb", 2, 0x0fd8, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
+{"psubusb", 2, 0x660fd8,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"psubusw", 2, 0x0fd9, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
+{"psubusw", 2, 0x660fd9,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"punpckhbw",2, 0x0f68, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
+{"punpckhbw",2, 0x660f68,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"punpckhwd",2, 0x0f69, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
+{"punpckhwd",2, 0x660f69,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"punpckhdq",2, 0x0f6a, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
+{"punpckhdq",2, 0x660f6a,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"punpcklbw",2, 0x0f60, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
+{"punpcklbw",2, 0x660f60,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"punpcklwd",2, 0x0f61, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
+{"punpcklwd",2, 0x660f61,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"punpckldq",2, 0x0f62, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
+{"punpckldq",2, 0x660f62,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"pxor", 2, 0x0fef, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
+{"pxor", 2, 0x660fef,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
/* PIII Katmai New Instructions / SIMD instructions. */
-{"addps", 2, 0x0f58, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"addss", 2, 0xf30f58, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
-{"andnps", 2, 0x0f55, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"andps", 2, 0x0f54, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
-{"cmpeqps", 2, 0x0fc2, 0, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },
-{"cmpeqss", 2, 0xf30fc2, 0, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },
-{"cmpleps", 2, 0x0fc2, 2, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },
-{"cmpless", 2, 0xf30fc2, 2, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },
-{"cmpltps", 2, 0x0fc2, 1, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },
-{"cmpltss", 2, 0xf30fc2, 1, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },
-{"cmpneqps", 2, 0x0fc2, 4, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },
-{"cmpneqss", 2, 0xf30fc2, 4, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },
-{"cmpnleps", 2, 0x0fc2, 6, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },
-{"cmpnless", 2, 0xf30fc2, 6, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },
-{"cmpnltps", 2, 0x0fc2, 5, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },
-{"cmpnltss", 2, 0xf30fc2, 5, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },
-{"cmpordps", 2, 0x0fc2, 7, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },
-{"cmpordss", 2, 0xf30fc2, 7, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },
-{"cmpunordps",2, 0x0fc2, 3, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },
-{"cmpunordss",2, 0xf30fc2, 3, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },
-{"cmpps", 3, 0x0fc2, X, CpuSSE, FP|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } },
-{"cmpss", 3, 0xf30fc2, X, CpuSSE, FP|Modrm, { Imm8, RegXMM|WordMem, RegXMM } },
-{"comiss", 2, 0x0f2f, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
-{"cvtpi2ps", 2, 0x0f2a, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegXMM, 0 } },
-{"cvtps2pi", 2, 0x0f2d, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegMMX, 0 } },
+{"addps", 2, 0x0f58, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"addss", 2, 0xf30f58, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
+{"andnps", 2, 0x0f55, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"andps", 2, 0x0f54, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
+{"cmpeqps", 2, 0x0fc2, 0, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },
+{"cmpeqss", 2, 0xf30fc2, 0, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },
+{"cmpleps", 2, 0x0fc2, 2, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },
+{"cmpless", 2, 0xf30fc2, 2, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },
+{"cmpltps", 2, 0x0fc2, 1, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },
+{"cmpltss", 2, 0xf30fc2, 1, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },
+{"cmpneqps", 2, 0x0fc2, 4, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },
+{"cmpneqss", 2, 0xf30fc2, 4, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },
+{"cmpnleps", 2, 0x0fc2, 6, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },
+{"cmpnless", 2, 0xf30fc2, 6, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },
+{"cmpnltps", 2, 0x0fc2, 5, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },
+{"cmpnltss", 2, 0xf30fc2, 5, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },
+{"cmpordps", 2, 0x0fc2, 7, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },
+{"cmpordss", 2, 0xf30fc2, 7, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },
+{"cmpunordps",2, 0x0fc2, 3, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },
+{"cmpunordss",2, 0xf30fc2, 3, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },
+{"cmpps", 3, 0x0fc2, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } },
+{"cmpss", 3, 0xf30fc2, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|WordMem, RegXMM } },
+{"comiss", 2, 0x0f2f, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
+{"cvtpi2ps", 2, 0x0f2a, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegXMM, 0 } },
+{"cvtps2pi", 2, 0x0f2d, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegMMX, 0 } },
{"cvtsi2ss", 2, 0xf30f2a, X, CpuSSE, lq_Suf|IgnoreSize|Modrm,{ Reg32|Reg64|WordMem|LLongMem, RegXMM, 0 } },
{"cvtss2si", 2, 0xf30f2d, X, CpuSSE, lq_Suf|IgnoreSize|Modrm,{ RegXMM|WordMem, Reg32|Reg64, 0 } },
-{"cvttps2pi", 2, 0x0f2c, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegMMX, 0 } },
+{"cvttps2pi", 2, 0x0f2c, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegMMX, 0 } },
{"cvttss2si", 2, 0xf30f2c, X, CpuSSE, lq_Suf|IgnoreSize|Modrm, { RegXMM|WordMem, Reg32|Reg64, 0 } },
-{"divps", 2, 0x0f5e, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"divss", 2, 0xf30f5e, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
-{"ldmxcsr", 1, 0x0fae, 2, CpuSSE, FP|Modrm, { WordMem, 0, 0 } },
-{"maskmovq", 2, 0x0ff7, X, CpuSSE, FP|Modrm, { RegMMX|InvMem, RegMMX, 0 } },
-{"maxps", 2, 0x0f5f, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"maxss", 2, 0xf30f5f, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
-{"minps", 2, 0x0f5d, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"minss", 2, 0xf30f5d, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
-{"movaps", 2, 0x0f28, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"movaps", 2, 0x0f29, X, CpuSSE, FP|Modrm, { RegXMM, RegXMM|LLongMem, 0 } },
-{"movhlps", 2, 0x0f12, X, CpuSSE, FP|Modrm, { RegXMM|InvMem, RegXMM, 0 } },
-{"movhps", 2, 0x0f16, X, CpuSSE, FP|Modrm, { LLongMem, RegXMM, 0 } },
-{"movhps", 2, 0x0f17, X, CpuSSE, FP|Modrm, { RegXMM, LLongMem, 0 } },
-{"movlhps", 2, 0x0f16, X, CpuSSE, FP|Modrm, { RegXMM|InvMem, RegXMM, 0 } },
-{"movlps", 2, 0x0f12, X, CpuSSE, FP|Modrm, { LLongMem, RegXMM, 0 } },
-{"movlps", 2, 0x0f13, X, CpuSSE, FP|Modrm, { RegXMM, LLongMem, 0 } },
+{"divps", 2, 0x0f5e, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"divss", 2, 0xf30f5e, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
+{"ldmxcsr", 1, 0x0fae, 2, CpuSSE, NoSuf|IgnoreSize|Modrm, { WordMem, 0, 0 } },
+{"maskmovq", 2, 0x0ff7, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX|InvMem, RegMMX, 0 } },
+{"maxps", 2, 0x0f5f, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"maxss", 2, 0xf30f5f, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
+{"minps", 2, 0x0f5d, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"minss", 2, 0xf30f5d, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
+{"movaps", 2, 0x0f28, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"movaps", 2, 0x0f29, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM|LLongMem, 0 } },
+{"movhlps", 2, 0x0f12, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|InvMem, RegXMM, 0 } },
+{"movhps", 2, 0x0f16, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { LLongMem, RegXMM, 0 } },
+{"movhps", 2, 0x0f17, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM, LLongMem, 0 } },
+{"movlhps", 2, 0x0f16, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|InvMem, RegXMM, 0 } },
+{"movlps", 2, 0x0f12, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { LLongMem, RegXMM, 0 } },
+{"movlps", 2, 0x0f13, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM, LLongMem, 0 } },
{"movmskps", 2, 0x0f50, X, CpuSSE, lq_Suf|IgnoreSize|Modrm, { RegXMM|InvMem, Reg32|Reg64, 0 } },
-{"movntps", 2, 0x0f2b, X, CpuSSE, FP|Modrm, { RegXMM, LLongMem, 0 } },
-{"movntq", 2, 0x0fe7, X, CpuSSE, FP|Modrm, { RegMMX, LLongMem, 0 } },
-{"movntdq", 2, 0x660fe7, X, CpuSSE2,FP|Modrm, { RegXMM, LLongMem, 0 } },
-{"movss", 2, 0xf30f10, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
-{"movss", 2, 0xf30f11, X, CpuSSE, FP|Modrm, { RegXMM, RegXMM|WordMem, 0 } },
-{"movups", 2, 0x0f10, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"movups", 2, 0x0f11, X, CpuSSE, FP|Modrm, { RegXMM, RegXMM|LLongMem, 0 } },
-{"mulps", 2, 0x0f59, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"mulss", 2, 0xf30f59, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
-{"orps", 2, 0x0f56, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"pavgb", 2, 0x0fe0, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
-{"pavgb", 2, 0x660fe0, X, CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"pavgw", 2, 0x0fe3, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
-{"pavgw", 2, 0x660fe3, X, CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"pextrw", 3, 0x0fc5, X, CpuSSE, lq_Suf|IgnoreSize|Modrm, { Imm8, RegMMX|InvMem, Reg32|Reg64 } },
+{"movntps", 2, 0x0f2b, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM, LLongMem, 0 } },
+{"movntq", 2, 0x0fe7, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX, LLongMem, 0 } },
+{"movntdq", 2, 0x660fe7, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM, LLongMem, 0 } },
+{"movss", 2, 0xf30f10, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
+{"movss", 2, 0xf30f11, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM|WordMem, 0 } },
+{"movups", 2, 0x0f10, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"movups", 2, 0x0f11, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM|LLongMem, 0 } },
+{"mulps", 2, 0x0f59, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"mulss", 2, 0xf30f59, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
+{"orps", 2, 0x0f56, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"pavgb", 2, 0x0fe0, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
+{"pavgb", 2, 0x660fe0, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"pavgw", 2, 0x0fe3, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
+{"pavgw", 2, 0x660fe3, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"pextrw", 3, 0x0fc5, X, CpuMMX2,lq_Suf|IgnoreSize|Modrm, { Imm8, RegMMX|InvMem, Reg32|Reg64 } },
{"pextrw", 3, 0x660fc5, X, CpuSSE2,lq_Suf|IgnoreSize|Modrm, { Imm8, RegXMM|InvMem, Reg32|Reg64 } },
-{"pinsrw", 3, 0x0fc4, X, CpuSSE, lq_Suf|IgnoreSize|Modrm, { Imm8, Reg32|Reg64|ShortMem, RegMMX } },
-{"pinsrw", 3, 0x660fc4, X, CpuSSE2, lq_Suf|IgnoreSize|Modrm, { Imm8, Reg32|Reg64|ShortMem, RegXMM } },
-{"pmaxsw", 2, 0x0fee, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
-{"pmaxsw", 2, 0x660fee, X, CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"pmaxub", 2, 0x0fde, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
-{"pmaxub", 2, 0x660fde, X, CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"pminsw", 2, 0x0fea, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
-{"pminsw", 2, 0x660fea, X, CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"pminub", 2, 0x0fda, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
-{"pminub", 2, 0x660fda, X, CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"pmovmskb", 2, 0x0fd7, X, CpuSSE, lq_Suf|IgnoreSize|Modrm, { RegMMX|InvMem, Reg32|Reg64, 0 } },
+{"pinsrw", 3, 0x0fc4, X, CpuMMX2,lq_Suf|IgnoreSize|Modrm, { Imm8, Reg32|Reg64|ShortMem, RegMMX } },
+{"pinsrw", 3, 0x660fc4, X, CpuSSE2,lq_Suf|IgnoreSize|Modrm, { Imm8, Reg32|Reg64|ShortMem, RegXMM } },
+{"pmaxsw", 2, 0x0fee, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
+{"pmaxsw", 2, 0x660fee, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"pmaxub", 2, 0x0fde, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
+{"pmaxub", 2, 0x660fde, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"pminsw", 2, 0x0fea, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
+{"pminsw", 2, 0x660fea, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"pminub", 2, 0x0fda, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
+{"pminub", 2, 0x660fda, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"pmovmskb", 2, 0x0fd7, X, CpuMMX2,lq_Suf|IgnoreSize|Modrm, { RegMMX|InvMem, Reg32|Reg64, 0 } },
{"pmovmskb", 2, 0x660fd7, X, CpuSSE2,lq_Suf|IgnoreSize|Modrm, { RegXMM|InvMem, Reg32|Reg64, 0 } },
-{"pmulhuw", 2, 0x0fe4, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
-{"pmulhuw", 2, 0x660fe4, X, CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"prefetchnta", 1, 0x0f18, 0, CpuSSE, FP|Modrm, { LLongMem, 0, 0 } },
-{"prefetcht0", 1, 0x0f18, 1, CpuSSE, FP|Modrm, { LLongMem, 0, 0 } },
-{"prefetcht1", 1, 0x0f18, 2, CpuSSE, FP|Modrm, { LLongMem, 0, 0 } },
-{"prefetcht2", 1, 0x0f18, 3, CpuSSE, FP|Modrm, { LLongMem, 0, 0 } },
-{"psadbw", 2, 0x0ff6, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
-{"psadbw", 2, 0x660ff6, X, CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"pshufw", 3, 0x0f70, X, CpuSSE, FP|Modrm, { Imm8, RegMMX|LLongMem, RegMMX } },
-{"rcpps", 2, 0x0f53, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"rcpss", 2, 0xf30f53, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
-{"rsqrtps", 2, 0x0f52, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"rsqrtss", 2, 0xf30f52, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
-{"sfence", 0, 0x0fae, 0xf8, CpuSSE, FP|ImmExt, { 0, 0, 0 } },
-{"shufps", 3, 0x0fc6, X, CpuSSE, FP|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } },
-{"sqrtps", 2, 0x0f51, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"sqrtss", 2, 0xf30f51, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
-{"stmxcsr", 1, 0x0fae, 3, CpuSSE, FP|Modrm, { WordMem, 0, 0 } },
-{"subps", 2, 0x0f5c, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"subss", 2, 0xf30f5c, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
-{"ucomiss", 2, 0x0f2e, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
-{"unpckhps", 2, 0x0f15, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"unpcklps", 2, 0x0f14, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"xorps", 2, 0x0f57, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"pmulhuw", 2, 0x0fe4, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
+{"pmulhuw", 2, 0x660fe4, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"prefetchnta", 1, 0x0f18, 0, CpuMMX2,NoSuf|IgnoreSize|Modrm, { LLongMem, 0, 0 } },
+{"prefetcht0", 1, 0x0f18, 1, CpuMMX2,NoSuf|IgnoreSize|Modrm, { LLongMem, 0, 0 } },
+{"prefetcht1", 1, 0x0f18, 2, CpuMMX2,NoSuf|IgnoreSize|Modrm, { LLongMem, 0, 0 } },
+{"prefetcht2", 1, 0x0f18, 3, CpuMMX2,NoSuf|IgnoreSize|Modrm, { LLongMem, 0, 0 } },
+{"psadbw", 2, 0x0ff6, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
+{"psadbw", 2, 0x660ff6, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"pshufw", 3, 0x0f70, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { Imm8, RegMMX|LLongMem, RegMMX } },
+{"rcpps", 2, 0x0f53, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"rcpss", 2, 0xf30f53, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
+{"rsqrtps", 2, 0x0f52, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"rsqrtss", 2, 0xf30f52, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
+{"sfence", 0, 0x0fae, 0xf8, CpuMMX2,NoSuf|IgnoreSize|ImmExt, { 0, 0, 0 } },
+{"shufps", 3, 0x0fc6, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } },
+{"sqrtps", 2, 0x0f51, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"sqrtss", 2, 0xf30f51, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
+{"stmxcsr", 1, 0x0fae, 3, CpuSSE, NoSuf|IgnoreSize|Modrm, { WordMem, 0, 0 } },
+{"subps", 2, 0x0f5c, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"subss", 2, 0xf30f5c, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
+{"ucomiss", 2, 0x0f2e, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
+{"unpckhps", 2, 0x0f15, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"unpcklps", 2, 0x0f14, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"xorps", 2, 0x0f57, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
/* SSE-2 instructions. */
-{"addpd", 2, 0x660f58, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"addsd", 2, 0xf20f58, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } },
-{"andnpd", 2, 0x660f55, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"andpd", 2, 0x660f54, X, CpuSSE2, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
-{"cmpeqpd", 2, 0x660fc2, 0, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },
-{"cmpeqsd", 2, 0xf20fc2, 0, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },
-{"cmplepd", 2, 0x660fc2, 2, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },
-{"cmplesd", 2, 0xf20fc2, 2, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },
-{"cmpltpd", 2, 0x660fc2, 1, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },
-{"cmpltsd", 2, 0xf20fc2, 1, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },
-{"cmpneqpd", 2, 0x660fc2, 4, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },
-{"cmpneqsd", 2, 0xf20fc2, 4, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },
-{"cmpnlepd", 2, 0x660fc2, 6, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },
-{"cmpnlesd", 2, 0xf20fc2, 6, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },
-{"cmpnltpd", 2, 0x660fc2, 5, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },
-{"cmpnltsd", 2, 0xf20fc2, 5, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },
-{"cmpordpd", 2, 0x660fc2, 7, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },
-{"cmpordsd", 2, 0xf20fc2, 7, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },
-{"cmpunordpd",2, 0x660fc2, 3, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },
-{"cmpunordsd",2, 0xf20fc2, 3, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },
-{"cmppd", 3, 0x660fc2, X, CpuSSE2, FP|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } },
+{"addpd", 2, 0x660f58, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"addsd", 2, 0xf20f58, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } },
+{"andnpd", 2, 0x660f55, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"andpd", 2, 0x660f54, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
+{"cmpeqpd", 2, 0x660fc2, 0, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },
+{"cmpeqsd", 2, 0xf20fc2, 0, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },
+{"cmplepd", 2, 0x660fc2, 2, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },
+{"cmplesd", 2, 0xf20fc2, 2, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },
+{"cmpltpd", 2, 0x660fc2, 1, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },
+{"cmpltsd", 2, 0xf20fc2, 1, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },
+{"cmpneqpd", 2, 0x660fc2, 4, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },
+{"cmpneqsd", 2, 0xf20fc2, 4, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },
+{"cmpnlepd", 2, 0x660fc2, 6, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },
+{"cmpnlesd", 2, 0xf20fc2, 6, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },
+{"cmpnltpd", 2, 0x660fc2, 5, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },
+{"cmpnltsd", 2, 0xf20fc2, 5, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },
+{"cmpordpd", 2, 0x660fc2, 7, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },
+{"cmpordsd", 2, 0xf20fc2, 7, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },
+{"cmpunordpd",2, 0x660fc2, 3, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },
+{"cmpunordsd",2, 0xf20fc2, 3, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },
+{"cmppd", 3, 0x660fc2, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } },
/* Intel mode string compare. */
{"cmpsd", 0, 0xa7, X, 0, NoSuf|Size32|IsString, { 0, 0, 0} },
{"cmpsd", 2, 0xa7, X, 0, NoSuf|Size32|IsString, { AnyMem, AnyMem|EsSeg, 0} },
-{"cmpsd", 3, 0xf20fc2, X, CpuSSE2, FP|Modrm, { Imm8, RegXMM|LongMem, RegXMM } },
-{"comisd", 2, 0x660f2f, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } },
-{"cvtpi2pd", 2, 0x660f2a, X, CpuSSE2, FP|Modrm, { RegMMX|LLongMem, RegXMM, 0 } },
+{"cmpsd", 3, 0xf20fc2, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LongMem, RegXMM } },
+{"comisd", 2, 0x660f2f, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } },
+{"cvtpi2pd", 2, 0x660f2a, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegXMM, 0 } },
{"cvtsi2sd", 2, 0xf20f2a, X, CpuSSE2, lq_Suf|IgnoreSize|Modrm,{ Reg32|Reg64|WordMem|LLongMem, RegXMM, 0 } },
-{"divpd", 2, 0x660f5e, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"divsd", 2, 0xf20f5e, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } },
-{"maxpd", 2, 0x660f5f, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"maxsd", 2, 0xf20f5f, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } },
-{"minpd", 2, 0x660f5d, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"minsd", 2, 0xf20f5d, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } },
-{"movapd", 2, 0x660f28, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"movapd", 2, 0x660f29, X, CpuSSE2, FP|Modrm, { RegXMM, RegXMM|LLongMem, 0 } },
-{"movhpd", 2, 0x660f16, X, CpuSSE2, FP|Modrm, { LLongMem, RegXMM, 0 } },
-{"movhpd", 2, 0x660f17, X, CpuSSE2, FP|Modrm, { RegXMM, LLongMem, 0 } },
-{"movlpd", 2, 0x660f12, X, CpuSSE2, FP|Modrm, { LLongMem, RegXMM, 0 } },
-{"movlpd", 2, 0x660f13, X, CpuSSE2, FP|Modrm, { RegXMM, LLongMem, 0 } },
+{"divpd", 2, 0x660f5e, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"divsd", 2, 0xf20f5e, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } },
+{"maxpd", 2, 0x660f5f, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"maxsd", 2, 0xf20f5f, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } },
+{"minpd", 2, 0x660f5d, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"minsd", 2, 0xf20f5d, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } },
+{"movapd", 2, 0x660f28, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"movapd", 2, 0x660f29, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM|LLongMem, 0 } },
+{"movhpd", 2, 0x660f16, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { LLongMem, RegXMM, 0 } },
+{"movhpd", 2, 0x660f17, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM, LLongMem, 0 } },
+{"movlpd", 2, 0x660f12, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { LLongMem, RegXMM, 0 } },
+{"movlpd", 2, 0x660f13, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM, LLongMem, 0 } },
{"movmskpd", 2, 0x660f50, X, CpuSSE2, lq_Suf|IgnoreSize|Modrm, { RegXMM|InvMem, Reg32|Reg64, 0 } },
-{"movntpd", 2, 0x660f2b, X, CpuSSE2, FP|Modrm, { RegXMM, LLongMem, 0 } },
+{"movntpd", 2, 0x660f2b, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM, LLongMem, 0 } },
/* Intel mode string move. */
{"movsd", 0, 0xa5, X, 0, NoSuf|Size32|IsString, { 0, 0, 0} },
{"movsd", 2, 0xa5, X, 0, NoSuf|Size32|IsString, { AnyMem, AnyMem|EsSeg, 0} },
-{"movsd", 2, 0xf20f10, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } },
-{"movsd", 2, 0xf20f11, X, CpuSSE2, FP|Modrm, { RegXMM, RegXMM|LongMem, 0 } },
-{"movupd", 2, 0x660f10, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"movupd", 2, 0x660f11, X, CpuSSE2, FP|Modrm, { RegXMM, RegXMM|LLongMem, 0 } },
-{"mulpd", 2, 0x660f59, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"mulsd", 2, 0xf20f59, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } },
-{"orpd", 2, 0x660f56, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"shufpd", 3, 0x660fc6, X, CpuSSE2, FP|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } },
-{"sqrtpd", 2, 0x660f51, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"sqrtsd", 2, 0xf20f51, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } },
-{"subpd", 2, 0x660f5c, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"subsd", 2, 0xf20f5c, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } },
-{"ucomisd", 2, 0x660f2e, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } },
-{"unpckhpd", 2, 0x660f15, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"unpcklpd", 2, 0x660f14, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"xorpd", 2, 0x660f57, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"cvtdq2pd", 2, 0xf30fe6, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"cvtpd2dq", 2, 0xf20fe6, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"cvtdq2ps", 2, 0x0f5b, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"cvtpd2pi", 2, 0x660f2d, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegMMX, 0 } },
-{"cvtpd2ps", 2, 0x660f5a, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"cvtps2pd", 2, 0x0f5a, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"cvtps2dq", 2, 0x660f5b, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"movsd", 2, 0xf20f10, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } },
+{"movsd", 2, 0xf20f11, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM|LongMem, 0 } },
+{"movupd", 2, 0x660f10, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"movupd", 2, 0x660f11, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM|LLongMem, 0 } },
+{"mulpd", 2, 0x660f59, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"mulsd", 2, 0xf20f59, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } },
+{"orpd", 2, 0x660f56, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"shufpd", 3, 0x660fc6, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } },
+{"sqrtpd", 2, 0x660f51, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"sqrtsd", 2, 0xf20f51, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } },
+{"subpd", 2, 0x660f5c, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"subsd", 2, 0xf20f5c, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } },
+{"ucomisd", 2, 0x660f2e, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } },
+{"unpckhpd", 2, 0x660f15, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"unpcklpd", 2, 0x660f14, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"xorpd", 2, 0x660f57, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"cvtdq2pd", 2, 0xf30fe6, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"cvtpd2dq", 2, 0xf20fe6, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"cvtdq2ps", 2, 0x0f5b, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"cvtpd2pi", 2, 0x660f2d, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegMMX, 0 } },
+{"cvtpd2ps", 2, 0x660f5a, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"cvtps2pd", 2, 0x0f5a, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"cvtps2dq", 2, 0x660f5b, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
{"cvtsd2si", 2, 0xf20f2d, X, CpuSSE2, lq_Suf|IgnoreSize|Modrm,{ RegXMM|LLongMem, Reg32|Reg64, 0 } },
-{"cvtsd2ss", 2, 0xf20f5a, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"cvtss2sd", 2, 0xf30f5a, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"cvttpd2pi", 2, 0x660f2c, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegMMX, 0 } },
+{"cvtsd2ss", 2, 0xf20f5a, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"cvtss2sd", 2, 0xf30f5a, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"cvttpd2pi", 2, 0x660f2c, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegMMX, 0 } },
{"cvttsd2si", 2, 0xf20f2c, X, CpuSSE2, lq_Suf|IgnoreSize|Modrm,{ RegXMM|WordMem, Reg32|Reg64, 0 } },
-{"cvttpd2dq", 2, 0x660fe6, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"cvttps2dq", 2, 0xf30f5b, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"maskmovdqu",2, 0x660ff7, X, CpuSSE2, FP|Modrm, { RegXMM|InvMem, RegXMM, 0 } },
-{"movdqa", 2, 0x660f6f, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"movdqa", 2, 0x660f7f, X, CpuSSE2, FP|Modrm, { RegXMM, RegXMM|LLongMem, 0 } },
-{"movdqu", 2, 0xf30f6f, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"movdqu", 2, 0xf30f7f, X, CpuSSE2, FP|Modrm, { RegXMM, RegXMM|LLongMem, 0 } },
-{"movdq2q", 2, 0xf20fd6, X, CpuSSE2, FP|Modrm, { RegXMM|InvMem, RegMMX, 0 } },
-{"movq2dq", 2, 0xf30fd6, X, CpuSSE2, FP|Modrm, { RegMMX|InvMem, RegXMM, 0 } },
-{"pmuludq", 2, 0x0ff4, X, CpuSSE2, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
-{"pmuludq", 2, 0x660ff4, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } },
-{"pshufd", 3, 0x660f70, X, CpuSSE2, FP|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } },
-{"pshufhw", 3, 0xf30f70, X, CpuSSE2, FP|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } },
-{"pshuflw", 3, 0xf20f70, X, CpuSSE2, FP|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } },
-{"pslldq", 2, 0x660f73, 7, CpuSSE2, FP|Modrm, { Imm8, RegXMM, 0 } },
-{"psrldq", 2, 0x660f73, 3, CpuSSE2, FP|Modrm, { Imm8, RegXMM, 0 } },
-{"punpckhqdq",2, 0x660f6d, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"punpcklqdq",2, 0x660f6c, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"cvttpd2dq", 2, 0x660fe6, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"cvttps2dq", 2, 0xf30f5b, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"maskmovdqu",2, 0x660ff7, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|InvMem, RegXMM, 0 } },
+{"movdqa", 2, 0x660f6f, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"movdqa", 2, 0x660f7f, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM|LLongMem, 0 } },
+{"movdqu", 2, 0xf30f6f, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"movdqu", 2, 0xf30f7f, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM|LLongMem, 0 } },
+{"movdq2q", 2, 0xf20fd6, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|InvMem, RegMMX, 0 } },
+{"movq2dq", 2, 0xf30fd6, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegMMX|InvMem, RegXMM, 0 } },
+{"pmuludq", 2, 0x0ff4, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
+{"pmuludq", 2, 0x660ff4, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } },
+{"pshufd", 3, 0x660f70, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } },
+{"pshufhw", 3, 0xf30f70, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } },
+{"pshuflw", 3, 0xf20f70, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } },
+{"pslldq", 2, 0x660f73, 7, CpuSSE2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM, 0 } },
+{"psrldq", 2, 0x660f73, 3, CpuSSE2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM, 0 } },
+{"punpckhqdq",2, 0x660f6d, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"punpcklqdq",2, 0x660f6c, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
/* Prescott New Instructions. */
-{"addsubpd", 2, 0x660fd0, X, CpuPNI, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"addsubps", 2, 0xf20fd0, X, CpuPNI, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"fisttp", 1, 0xdf, 1, CpuPNI, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },
-/* Intel Syntax */
-{"fisttpd", 1, 0xdd, 1, CpuPNI, FP|Modrm, { LLongMem, 0, 0} },
-{"fisttpq", 1, 0xdd, 1, CpuPNI, FP|Modrm, { LLongMem, 0, 0} },
+{"addsubpd", 2, 0x660fd0, X, CpuPNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"addsubps", 2, 0xf20fd0, X, CpuPNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"cmpxchg16b",1, 0x0fc7, 1, CpuPNI|Cpu64, NoSuf|Modrm|Rex64, { LLongMem, 0, 0} },
+{"fisttp", 1, 0xdf, 1, CpuPNI, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} },
+{"fisttp", 1, 0xdd, 1, CpuPNI, q_FP|Modrm, { LLongMem, 0, 0} },
{"fisttpll", 1, 0xdd, 1, CpuPNI, FP|Modrm, { LLongMem, 0, 0} },
-{"haddpd", 2, 0x660f7c, X, CpuPNI, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"haddps", 2, 0xf20f7c, X, CpuPNI, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"hsubpd", 2, 0x660f7d, X, CpuPNI, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"hsubps", 2, 0xf20f7d, X, CpuPNI, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"lddqu", 2, 0xf20ff0, X, CpuPNI, FP|Modrm, { LLongMem, RegXMM, 0 } },
-{"monitor", 0, 0x0f01, 0xc8, CpuPNI, FP|ImmExt, { 0, 0, 0} },
+{"haddpd", 2, 0x660f7c, X, CpuPNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"haddps", 2, 0xf20f7c, X, CpuPNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"hsubpd", 2, 0x660f7d, X, CpuPNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"hsubps", 2, 0xf20f7d, X, CpuPNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"lddqu", 2, 0xf20ff0, X, CpuPNI, NoSuf|IgnoreSize|Modrm, { LLongMem, RegXMM, 0 } },
+{"monitor", 0, 0x0f01, 0xc8, CpuPNI, NoSuf|ImmExt, { 0, 0, 0} },
/* Need to ensure only "monitor %eax,%ecx,%edx" is accepted. */
-{"monitor", 3, 0x0f01, 0xc8, CpuPNI, FP|ImmExt, { Reg32, Reg32, Reg32} },
-{"movddup", 2, 0xf20f12, X, CpuPNI, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"movshdup", 2, 0xf30f16, X, CpuPNI, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"movsldup", 2, 0xf30f12, X, CpuPNI, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"mwait", 0, 0x0f01, 0xc9, CpuPNI, FP|ImmExt, { 0, 0, 0} },
+{"monitor", 3, 0x0f01, 0xc8, CpuPNI, NoSuf|ImmExt, { Reg32, Reg32, Reg32} },
+{"movddup", 2, 0xf20f12, X, CpuPNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"movshdup", 2, 0xf30f16, X, CpuPNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"movsldup", 2, 0xf30f12, X, CpuPNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"mwait", 0, 0x0f01, 0xc9, CpuPNI, NoSuf|ImmExt, { 0, 0, 0} },
/* Need to ensure only "mwait %eax,%ecx" is accepted. */
-{"mwait", 2, 0x0f01, 0xc9, CpuPNI, FP|ImmExt, { Reg32, Reg32, 0} },
+{"mwait", 2, 0x0f01, 0xc9, CpuPNI, NoSuf|ImmExt, { Reg32, Reg32, 0} },
/* AMD 3DNow! instructions. */
-{"prefetch", 1, 0x0f0d, 0, Cpu3dnow, FP|Modrm, { ByteMem, 0, 0 } },
-{"prefetchw",1, 0x0f0d, 1, Cpu3dnow, FP|Modrm, { ByteMem, 0, 0 } },
-{"femms", 0, 0x0f0e, X, Cpu3dnow, FP, { 0, 0, 0 } },
-{"pavgusb", 2, 0x0f0f, 0xbf, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
-{"pf2id", 2, 0x0f0f, 0x1d, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
-{"pf2iw", 2, 0x0f0f, 0x1c, Cpu3dnow|Cpu686, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
-{"pfacc", 2, 0x0f0f, 0xae, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
-{"pfadd", 2, 0x0f0f, 0x9e, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
-{"pfcmpeq", 2, 0x0f0f, 0xb0, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
-{"pfcmpge", 2, 0x0f0f, 0x90, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
-{"pfcmpgt", 2, 0x0f0f, 0xa0, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
-{"pfmax", 2, 0x0f0f, 0xa4, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
-{"pfmin", 2, 0x0f0f, 0x94, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
-{"pfmul", 2, 0x0f0f, 0xb4, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
-{"pfnacc", 2, 0x0f0f, 0x8a, Cpu3dnow|Cpu686, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
-{"pfpnacc", 2, 0x0f0f, 0x8e, Cpu3dnow|Cpu686, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
-{"pfrcp", 2, 0x0f0f, 0x96, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
-{"pfrcpit1", 2, 0x0f0f, 0xa6, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
-{"pfrcpit2", 2, 0x0f0f, 0xb6, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
-{"pfrsqit1", 2, 0x0f0f, 0xa7, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
-{"pfrsqrt", 2, 0x0f0f, 0x97, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
-{"pfsub", 2, 0x0f0f, 0x9a, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
-{"pfsubr", 2, 0x0f0f, 0xaa, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
-{"pi2fd", 2, 0x0f0f, 0x0d, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
-{"pi2fw", 2, 0x0f0f, 0x0c, Cpu3dnow|Cpu686, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
-{"pmulhrw", 2, 0x0f0f, 0xb7, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
-{"pswapd", 2, 0x0f0f, 0xbb, Cpu3dnow|Cpu686, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
+{"prefetch", 1, 0x0f0d, 0, Cpu3dnow, NoSuf|IgnoreSize|Modrm, { ByteMem, 0, 0 } },
+{"prefetchw",1, 0x0f0d, 1, Cpu3dnow, NoSuf|IgnoreSize|Modrm, { ByteMem, 0, 0 } },
+{"femms", 0, 0x0f0e, X, Cpu3dnow, NoSuf, { 0, 0, 0 } },
+{"pavgusb", 2, 0x0f0f, 0xbf, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
+{"pf2id", 2, 0x0f0f, 0x1d, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
+{"pf2iw", 2, 0x0f0f, 0x1c, Cpu3dnowA,NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
+{"pfacc", 2, 0x0f0f, 0xae, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
+{"pfadd", 2, 0x0f0f, 0x9e, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
+{"pfcmpeq", 2, 0x0f0f, 0xb0, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
+{"pfcmpge", 2, 0x0f0f, 0x90, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
+{"pfcmpgt", 2, 0x0f0f, 0xa0, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
+{"pfmax", 2, 0x0f0f, 0xa4, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
+{"pfmin", 2, 0x0f0f, 0x94, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
+{"pfmul", 2, 0x0f0f, 0xb4, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
+{"pfnacc", 2, 0x0f0f, 0x8a, Cpu3dnowA,NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
+{"pfpnacc", 2, 0x0f0f, 0x8e, Cpu3dnowA,NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
+{"pfrcp", 2, 0x0f0f, 0x96, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
+{"pfrcpit1", 2, 0x0f0f, 0xa6, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
+{"pfrcpit2", 2, 0x0f0f, 0xb6, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
+{"pfrsqit1", 2, 0x0f0f, 0xa7, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
+{"pfrsqrt", 2, 0x0f0f, 0x97, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
+{"pfsub", 2, 0x0f0f, 0x9a, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
+{"pfsubr", 2, 0x0f0f, 0xaa, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
+{"pi2fd", 2, 0x0f0f, 0x0d, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
+{"pi2fw", 2, 0x0f0f, 0x0c, Cpu3dnowA,NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
+{"pmulhrw", 2, 0x0f0f, 0xb7, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
+{"pswapd", 2, 0x0f0f, 0xbb, Cpu3dnowA,NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
/* AMD extensions. */
{"syscall", 0, 0x0f05, X, CpuK6, NoSuf, { 0, 0, 0} },
{"sysret", 0, 0x0f07, X, CpuK6, lq_Suf|DefaultSize, { 0, 0, 0} },
{"swapgs", 0, 0x0f01, 0xf8, Cpu64, NoSuf|ImmExt, { 0, 0, 0} },
+{"rdtscp", 0, 0x0f01, 0xf9, CpuSledgehammer,NoSuf|ImmExt, { 0, 0, 0} },
-/* VIA PadLock extensions. */
-{"xstorerng", 0, 0x0fa7c0, X, Cpu686|CpuPadLock, NoSuf|IsString, { 0, 0, 0} },
+/* VIA PadLock extensions. */
+{"xstorerng", 0, 0x000fa7c0, X, Cpu686|CpuPadLock, NoSuf|IsString, { 0, 0, 0} },
{"xcryptecb", 0, 0xf30fa7c8, X, Cpu686|CpuPadLock, NoSuf|IsString, { 0, 0, 0} },
{"xcryptcbc", 0, 0xf30fa7d0, X, Cpu686|CpuPadLock, NoSuf|IsString, { 0, 0, 0} },
{"xcryptcfb", 0, 0xf30fa7e0, X, Cpu686|CpuPadLock, NoSuf|IsString, { 0, 0, 0} },
{"xcryptofb", 0, 0xf30fa7e8, X, Cpu686|CpuPadLock, NoSuf|IsString, { 0, 0, 0} },
-/* alias for xstorerng */
-{"xstore", 0, 0x0fa7c0, X, Cpu686|CpuPadLock, NoSuf|IsString, { 0, 0, 0} },
+{"montmul", 0, 0xf30fa6c0, X, Cpu686|CpuPadLock, NoSuf|IsString, { 0, 0, 0} },
+{"xsha1", 0, 0xf30fa6c8, X, Cpu686|CpuPadLock, NoSuf|IsString, { 0, 0, 0} },
+{"xsha256", 0, 0xf30fa6d0, X, Cpu686|CpuPadLock, NoSuf|IsString, { 0, 0, 0} },
+/* Alias for xstorerng. */
+{"xstore", 0, 0x000fa7c0, X, Cpu686|CpuPadLock, NoSuf|IsString, { 0, 0, 0} },
/* sentinel */
{NULL, 0, 0, 0, 0, 0, { 0, 0, 0} }
@@ -1389,16 +1402,17 @@ static const template i386_optab[] = {
#undef bwlq_Suf
#undef FP
#undef l_FP
+#undef q_FP
#undef x_FP
#undef sl_FP
-#define MAX_MNEM_SIZE 16 /* for parsing insn mnemonics from input */
-
+#define MAX_MNEM_SIZE 16 /* For parsing insn mnemonics from input. */
/* 386 register table. */
-static const reg_entry i386_regtab[] = {
- /* make %st first as we test for it */
+static const reg_entry i386_regtab[] =
+{
+ /* Make %st first as we test for it. */
{"st", FloatReg|FloatAcc, 0, 0},
/* 8 bit regs */
#define REGNAM_AL 1 /* Entry in i386_regtab. */
@@ -1446,7 +1460,7 @@ static const reg_entry i386_regtab[] = {
{"r15w", Reg16, RegRex, 7},
/* 32 bit regs */
#define REGNAM_EAX 41
- {"eax", Reg32|BaseIndex|Acc, 0, 0}, /* Must be in ax + 16 slot */
+ {"eax", Reg32|BaseIndex|Acc, 0, 0}, /* Must be in ax + 16 slot. */
{"ecx", Reg32|BaseIndex, 0, 1},
{"edx", Reg32|BaseIndex, 0, 2},
{"ebx", Reg32|BaseIndex, 0, 3},
@@ -1478,14 +1492,14 @@ static const reg_entry i386_regtab[] = {
{"r13", Reg64|BaseIndex, RegRex, 5},
{"r14", Reg64|BaseIndex, RegRex, 6},
{"r15", Reg64|BaseIndex, RegRex, 7},
- /* segment registers */
+ /* Segment registers. */
{"es", SReg2, 0, 0},
{"cs", SReg2, 0, 1},
{"ss", SReg2, 0, 2},
{"ds", SReg2, 0, 3},
{"fs", SReg3, 0, 4},
{"gs", SReg3, 0, 5},
- /* control registers */
+ /* Control registers. */
{"cr0", Control, 0, 0},
{"cr1", Control, 0, 1},
{"cr2", Control, 0, 2},
@@ -1502,7 +1516,7 @@ static const reg_entry i386_regtab[] = {
{"cr13", Control, RegRex, 5},
{"cr14", Control, RegRex, 6},
{"cr15", Control, RegRex, 7},
- /* debug registers */
+ /* Debug registers. */
{"db0", Debug, 0, 0},
{"db1", Debug, 0, 1},
{"db2", Debug, 0, 2},
@@ -1535,7 +1549,7 @@ static const reg_entry i386_regtab[] = {
{"dr13", Debug, RegRex, 5},
{"dr14", Debug, RegRex, 6},
{"dr15", Debug, RegRex, 7},
- /* test registers */
+ /* Test registers. */
{"tr0", Test, 0, 0},
{"tr1", Test, 0, 1},
{"tr2", Test, 0, 2},
@@ -1544,7 +1558,7 @@ static const reg_entry i386_regtab[] = {
{"tr5", Test, 0, 5},
{"tr6", Test, 0, 6},
{"tr7", Test, 0, 7},
- /* mmx and simd registers */
+ /* MMX and simd registers. */
{"mm0", RegMMX, 0, 0},
{"mm1", RegMMX, 0, 1},
{"mm2", RegMMX, 0, 2},
@@ -1569,12 +1583,13 @@ static const reg_entry i386_regtab[] = {
{"xmm13", RegXMM, RegRex, 5},
{"xmm14", RegXMM, RegRex, 6},
{"xmm15", RegXMM, RegRex, 7},
- /* no type will make this register rejected for all purposes except
+ /* No type will make this register rejected for all purposes except
for addressing. This saves creating one extra type for RIP. */
{"rip", BaseIndex, 0, 0}
};
-static const reg_entry i386_float_regtab[] = {
+static const reg_entry i386_float_regtab[] =
+{
{"st(0)", FloatReg|FloatAcc, 0, 0},
{"st(1)", FloatReg, 0, 1},
{"st(2)", FloatReg, 0, 2},
@@ -1585,9 +1600,9 @@ static const reg_entry i386_float_regtab[] = {
{"st(7)", FloatReg, 0, 7}
};
-#define MAX_REG_NAME_SIZE 8 /* for parsing register names from input */
+#define MAX_REG_NAME_SIZE 8 /* For parsing register names from input. */
-/* segment stuff */
+/* Segment stuff. */
static const seg_entry cs = { "cs", 0x2e };
static const seg_entry ds = { "ds", 0x3e };
static const seg_entry ss = { "ss", 0x36 };
@@ -1595,4 +1610,3 @@ static const seg_entry es = { "es", 0x26 };
static const seg_entry fs = { "fs", 0x64 };
static const seg_entry gs = { "gs", 0x65 };
-/* end of opcode/i386.h */
diff --git a/gnu/dist/binutils/include/opcode/i860.h b/gnu/dist/binutils/include/opcode/i860.h
index b46a5e5a4eb..fe08ee4f228 100644
--- a/gnu/dist/binutils/include/opcode/i860.h
+++ b/gnu/dist/binutils/include/opcode/i860.h
@@ -1,5 +1,5 @@
/* Table of opcodes for the i860.
- Copyright 1989, 1991, 2000, 2003 Free Software Foundation, Inc.
+ Copyright 1989, 1991, 2000, 2002, 2003 Free Software Foundation, Inc.
This file is part of GAS, the GNU Assembler, and GDB, the GNU disassembler.
diff --git a/gnu/dist/binutils/include/opcode/ia64.h b/gnu/dist/binutils/include/opcode/ia64.h
index 0d33fc61b2c..58553b3ad63 100644
--- a/gnu/dist/binutils/include/opcode/ia64.h
+++ b/gnu/dist/binutils/include/opcode/ia64.h
@@ -1,5 +1,5 @@
/* ia64.h -- Header file for ia64 opcode table
- Copyright (C) 1998, 1999, 2002 Free Software Foundation, Inc.
+ Copyright (C) 1998, 1999, 2000, 2002 Free Software Foundation, Inc.
Contributed by David Mosberger-Tang <davidm@hpl.hp.com> */
#ifndef opcode_ia64_h
diff --git a/gnu/dist/binutils/include/opcode/m68k.h b/gnu/dist/binutils/include/opcode/m68k.h
index 3f189841d8f..014495b9720 100644
--- a/gnu/dist/binutils/include/opcode/m68k.h
+++ b/gnu/dist/binutils/include/opcode/m68k.h
@@ -1,6 +1,6 @@
/* Opcode table header for m680[01234]0/m6888[12]/m68851.
Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1999, 2001,
- 2003 Free Software Foundation, Inc.
+ 2003, 2004 Free Software Foundation, Inc.
This file is part of GDB, GAS, and the GNU binutils.
@@ -35,13 +35,27 @@
#define m68881 0x040
#define m68882 m68881 /* Synonym for -m68881. otherwise unused. */
#define m68851 0x080
-#define cpu32 0x100 /* e.g., 68332 */
-#define mcf5200 0x200
-#define mcf5206e 0x400
-#define mcf5307 0x800
-#define mcf5407 0x1000
-#define mcfv4e 0x2000
-#define mcf528x 0x4000
+#define cpu32 0x100 /* e.g., 68332 */
+
+#define mcfmac 0x200 /* ColdFire MAC. */
+#define mcfemac 0x400 /* ColdFire EMAC. */
+#define cfloat 0x800 /* ColdFire FPU. */
+#define mcfhwdiv 0x1000 /* ColdFire hardware divide. */
+
+#define mcfisa_a 0x2000 /* ColdFire ISA_A. */
+#define mcfisa_aa 0x4000 /* ColdFire ISA_A+. */
+#define mcfisa_b 0x8000 /* ColdFire ISA_B. */
+#define mcfusp 0x10000 /* ColdFire USP instructions. */
+
+#define mcf5200 0x20000
+#define mcf5206e 0x40000
+#define mcf521x 0x80000
+#define mcf5249 0x100000
+#define mcf528x 0x200000
+#define mcf5307 0x400000
+#define mcf5407 0x800000
+#define mcf5470 0x1000000
+#define mcf5480 0x2000000
/* Handy aliases. */
#define m68040up (m68040 | m68060)
@@ -49,13 +63,7 @@
#define m68020up (m68020 | m68030up)
#define m68010up (m68010 | cpu32 | m68020up)
#define m68000up (m68000 | m68010up)
-#define mcf (mcf5200 | mcf5206e | mcf528x | mcf5307 | mcf5407 | mcfv4e)
-#define mcf5206eup (mcf5206e | mcf528x | mcf5307 | mcf5407 | mcfv4e)
-#define mcf5307up (mcf5307 | mcf5407 | mcfv4e)
-#define mcfv4up (mcf5407 | mcfv4e)
-#define mcfv4eup (mcfv4e)
-#define cfloat (mcfv4e)
#define mfloat (m68881 | m68882 | m68040 | m68060)
#define mmmu (m68851 | m68030 | m68040 | m68060)
@@ -65,6 +73,9 @@ struct m68k_opcode
{
/* The opcode name. */
const char *name;
+ /* The pseudo-size of the instruction(in bytes). Used to determine
+ number of bytes necessary to disassemble the instruction. */
+ unsigned int size;
/* The opcode itself. */
unsigned long opcode;
/* The mask used by the disassembler. */
@@ -99,7 +110,7 @@ struct m68k_opcode_alias
operand; the second, the place it is stored. */
/* Kinds of operands:
- Characters used: AaBbCcDdEFfGHIJkLlMmnOopQqRrSsTtU VvWwXxYyZz0123|*~%;@!&$?/<>#^+-
+ Characters used: AaBbCcDdEeFfGgHIiJkLlMmnOopQqRrSsTtU VvWwXxYyZz01234|*~%;@!&$?/<>#^+-
D data register only. Stored as 3 bits.
A address register only. Stored as 3 bits.
@@ -133,9 +144,12 @@ struct m68k_opcode_alias
C the CCR. No need to store it; this is just for filtering validity.
S the SR. No need to store, just as with CCR.
U the USP. No need to store, just as with CCR.
- E the ACC. No need to store, just as with CCR.
- G the MACSR. No need to store, just as with CCR.
+ E the MAC ACC. No need to store, just as with CCR.
+ e the EMAC ACC[0123].
+ G the MAC/EMAC MACSR. No need to store, just as with CCR.
+ g the EMAC ACCEXT{01,23}.
H the MASK. No need to store, just as with CCR.
+ i the MAC/EMAC scale factor.
I Coprocessor ID. Not printed if 1. The Coprocessor ID is always
extracted from the 'd' field of word one, which means that an extended
@@ -205,7 +219,7 @@ struct m68k_opcode_alias
! control (modes 2,5,6,7.0-3)
(not 0,1,3,4,7.4)
& alterable control (modes 2,5,6,7.0,7.1)
- (not 0,1,7.2-4)
+ (not 0,1,3,4,7.2-4)
$ alterable data (modes 0,2-6,7.0,7.1)
(not 1,7.2-4)
? alterable control, or data register (modes 0,2,5,6,7.0,7.1)
@@ -230,7 +244,9 @@ struct m68k_opcode_alias
w (modes 2-5,7.2)
y (modes 2,5)
z (modes 2,5,7.2)
- x mov3q immediate operand. */
+ x mov3q immediate operand.
+ 4 (modes 2,3,4,5)
+ */
/* For the 68851: */
/* I didn't use much imagination in choosing the
@@ -283,7 +299,7 @@ struct m68k_opcode_alias
*/
/* Places to put an operand, for non-general operands:
- Characters used: BbCcDdghijkLlMmNnostWw123456789
+ Characters used: BbCcDdFfGgHhIijkLlMmNnostWw123456789/
s source, low bits of first word.
d dest, shifted 9 in first word
@@ -348,6 +364,13 @@ struct m68k_opcode_alias
F double precision float, low bit of 1st word, immediate uses 8 bytes
x extended precision float, low bit of 1st word, immediate uses 12 bytes
p packed float, low bit of 1st word, immediate uses 12 bytes
+ G EMAC accumulator, load (bit 4 2nd word, !bit8 first word)
+ H EMAC accumulator, non load (bit 4 2nd word, bit 8 first word)
+ F EMAC ACCx
+ f EMAC ACCy
+ I MAC/EMAC scale factor
+ / Like 's', but set 2nd word, bit 5 if trailing_ampersand set
+ ] first word, bit 10
*/
extern const struct m68k_opcode m68k_opcodes[];
diff --git a/gnu/dist/binutils/include/opcode/m88k.h b/gnu/dist/binutils/include/opcode/m88k.h
index 6a163bbe934..c201349dc52 100644
--- a/gnu/dist/binutils/include/opcode/m88k.h
+++ b/gnu/dist/binutils/include/opcode/m88k.h
@@ -1,5 +1,6 @@
/* Table of opcodes for the Motorola M88k family.
- Copyright 1989, 1990, 1991, 1993, 2001 Free Software Foundation, Inc.
+ Copyright 1989, 1990, 1991, 1993, 2001, 2002
+ Free Software Foundation, Inc.
This file is part of GDB and GAS.
diff --git a/gnu/dist/binutils/include/opcode/maxq.h b/gnu/dist/binutils/include/opcode/maxq.h
new file mode 100644
index 00000000000..f4fcb30a80c
--- /dev/null
+++ b/gnu/dist/binutils/include/opcode/maxq.h
@@ -0,0 +1,1132 @@
+/* maxq.h -- Header file for MAXQ opcode table.
+
+ Copyright (C) 2004 Free Software Foundation, Inc.
+
+ This file is part of GDB, GAS, and the GNU binutils.
+
+ Written by Vineet Sharma(vineets@noida.hcltech.com)
+ Inderpreet Singh (inderpreetb@noida.hcltech.com)
+
+ GDB, GAS, and the GNU binutils are free software; you can redistribute
+ them and/or modify them under the terms of the GNU General Public License
+ as published by the Free Software Foundation; either version 2, or (at
+ your option) any later version.
+
+ GDB, GAS, and the GNU binutils are distributed in the hope that they will
+ be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General
+ Public License for more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this file; see the file COPYING. If not, write to the Free Software
+ Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+
+#ifndef _MAXQ20_H_
+#define _MAXQ20_H_
+
+/* This file contains the opcode table for the MAXQ10/20 processor. The table
+ has been designed on the lines of the SH processor with the following
+ fields:
+ (1) Instruction Name
+ (2) Instruction arguments description
+ (3) Description of the breakup of the opcode (1+7+8|8+8|1+4+4|1+7+1+3+4
+ |1+3+4+1+3+4|1+3+4+8|1+1+2+4+8)
+ (4) Architecture supported
+
+ The Register table is also defined. It contains the following fields
+ (1) Register name
+ (2) Module Number
+ (3) Module Index
+ (4) Opcode
+ (5) Regtype
+
+ The Memory access table is defined containing the various opcodes for
+ memory access containing the following fields
+ (1) Memory access Operand Name
+ (2) Memory access Operand opcode. */
+
+# define MAXQ10 0x0001
+# define MAXQ20 0x0002
+# define MAX (MAXQ10 | MAXQ20)
+
+/* This is for the NOP instruction Specify : 1st bit : NOP_FMT 1st byte:
+ NOP_DST 2nd byte: NOP_SRC. */
+# define NOP_FMT 1
+# define NOP_SRC 0x3A
+# define NOP_DST 0x5A
+
+typedef enum
+{
+ ZEROBIT = 0x1, /* A zero followed by 3 bits. */
+ ONEBIT = 0x2, /* A one followed by 3 bits. */
+ REG = 0x4, /* Register. */
+ MEM = 0x8, /* Memory access. */
+ IMM = 0x10, /* Immediate value. */
+ DISP = 0x20, /* Displacement value. */
+ BIT = 0x40, /* Bit value. */
+ FMT = 0x80, /* The format bit. */
+ IMMBIT = 0x100, /* An immediate bit. */
+ FLAG = 0x200, /* A Flag. */
+ DATA = 0x400, /* Symbol in the data section. */
+ BIT_BUCKET = 0x800, /* FOr BIT BUCKET. */
+}
+UNKNOWN_OP;
+
+typedef enum
+{
+ NO_ARG = 0,
+ A_IMM = 0x01, /* An 8 bit immediate value. */
+ A_REG = 0x2, /* An 8 bit source register. */
+ A_MEM = 0x4, /* A 7 bit destination register. */
+ FLAG_C = 0x8, /* Carry Flag. */
+ FLAG_NC = 0x10, /* No Carry (~C) flag. */
+ FLAG_Z = 0x20, /* Zero Flag. */
+ FLAG_NZ = 0x40, /* Not Zero Flag. */
+ FLAG_S = 0x80, /* Sign Flag. */
+ FLAG_E = 0x100, /* Equals Flag. */
+ FLAG_NE = 0x200, /* Not Equal Flag. */
+ ACC_BIT = 0x400, /* One of the 16 accumulator bits of the form Acc.<b>. */
+ DST_BIT = 0x800, /* One of the 8 bits of the specified SRC. */
+ SRC_BIT = 0x1000, /* One of the 8 bits of the specified source register. */
+ A_BIT_0 = 0x2000, /* #0. */
+ A_BIT_1 = 0x4000, /* #1. */
+ A_DISP = 0x8000, /* Displacement Operand. */
+ A_DATA = 0x10000, /* Data in the data section. */
+ A_BIT_BUCKET = 0x200000,
+}
+MAX_ARG_TYPE;
+
+typedef struct
+{
+ char * name; /* Name of the instruction. */
+ unsigned int op_number; /* Operand Number or the number of operands. */
+ MAX_ARG_TYPE arg[2]; /* Types of operands. */
+ int format; /* Format bit. */
+ int dst[2]; /* Destination in the move instruction. */
+ int src[2]; /* Source in the move instruction. */
+ int arch; /* The Machine architecture. */
+ unsigned int instr_id; /* Added for decode and dissassembly. */
+}
+MAXQ20_OPCODE_INFO;
+
+/* Structure for holding opcodes of the same name. */
+typedef struct
+{
+ const MAXQ20_OPCODE_INFO *start; /* The first opcode. */
+ const MAXQ20_OPCODE_INFO *end; /* The last opcode. */
+}
+MAXQ20_OPCODES;
+
+/* The entry into the hash table will be of the type MAXX_OPCODES. */
+
+/* The definition of the table. */
+const MAXQ20_OPCODE_INFO op_table[] =
+{
+ /* LOGICAL OPERATIONS */
+ /* AND src : f001 1010 ssss ssss */
+ {"AND", 1, {A_IMM | A_REG | A_MEM | A_DISP, 0}, FMT, {0x1a, 0},
+ {REG | MEM | IMM | DISP, 0}, MAX, 0x11},
+ /* AND Acc.<b> : 1111 1010 bbbb 1010 */
+ {"AND", 1, {ACC_BIT, 0}, 1, {0x1a, 0}, {BIT, 0xa}, MAX, 0x39},
+ /* OR src : f010 1010 ssss ssss */
+ {"OR", 1, {A_IMM | A_REG | A_MEM | A_DISP, 0}, FMT, {0x2a, 0},
+ {REG | MEM | IMM | DISP, 0}, MAX, 0x12},
+ /* OR Acc.<b> : 1010 1010 bbbb 1010 */
+ {"OR", 1, {ACC_BIT, 0}, 1, {0x2a, 0}, {BIT, 0xa}, MAX, 0x3A},
+ /* XOR src : f011 1010 ssss ssss */
+ {"XOR", 1, {A_IMM | A_REG | A_MEM | A_DISP, 0}, FMT, {0x3a, 0},
+ {REG | MEM | IMM | DISP, 0}, MAX, 0x13},
+ /* XOR Acc.<b> : 1011 1010 bbbb 1010 */
+ {"XOR", 1, {ACC_BIT, 0}, 1, {0x3a, 0}, {BIT, 0xa}, MAX, 0x3B},
+ /* LOGICAL OPERATIONS INVOLVING ONLY THE ACCUMULATOR */
+ /* CPL : 1000 1010 0001 1010 */
+ {"CPL", 0, {0, 0}, 1, {0x0a, 0}, {0x1a, 0}, MAX, 0x21},
+ /* CPL C : 1101 1010 0010 1010 */
+ {"CPL", 1, {FLAG_C, 0}, 1, {0x5a, 0}, {0x2a, 0}, MAX, 0x3D},
+ /* NEG : 1000 1010 1001 1010 */
+ {"NEG", 0, {0, 0}, 1, {0x0a, 0}, {0x9a, 0}, MAX, 0x29},
+ /* SLA : 1000 1010 0010 1010 */
+ {"SLA", 0, {0, 0}, 1, {0x0a, 0}, {0x2a, 0}, MAX, 0x22},
+ /* SLA2: 1000 1010 0011 1010 */
+ {"SLA2", 0, {0, 0}, 1, {0x0a, 0}, {0x3a, 0}, MAX, 0x23},
+ /* SLA4: 1000 1010 0110 1010 */
+ {"SLA4", 0, {0, 0}, 1, {0x0a, 0}, {0x6a, 0}, MAX, 0x26},
+ /* RL : 1000 1010 0100 1010 */
+ {"RL", 0, {0, 0}, 1, {0x0a, 0}, {0x4a, 0}, MAX, 0x24},
+ /* RLC : 1000 1010 0101 1010 */
+ {"RLC", 0, {0, 0}, 1, {0x0a, 0}, {0x5a, 0}, MAX, 0x25},
+ /* SRA : 1000 1010 1111 1010 */
+ {"SRA", 0, {0, 0}, 1, {0x0a, 0}, {0xfa, 0}, MAX, 0x2F},
+ /* SRA2: 1000 1010 1110 1010 */
+ {"SRA2", 0, {0, 0}, 1, {0x0a, 0}, {0xea, 0}, MAX, 0x2E},
+ /* SRA4: 1000 1010 1011 1010 */
+ {"SRA4", 0, {0, 0}, 1, {0x0a, 0}, {0xba, 0}, MAX, 0x2B},
+ /* SR : 1000 1010 1010 1010 */
+ {"SR", 0, {0, 0}, 1, {0x0a, 0}, {0xaa, 0}, MAX, 0x2A},
+ /* RR : 1000 1010 1100 1010 */
+ {"RR", 0, {0, 0}, 1, {0x0a, 0}, {0xca, 0}, MAX, 0x2C},
+ /* RRC : 1000 1010 1101 1010 */
+ {"RRC", 0, {0, 0}, 1, {0x0a, 0}, {0xda, 0}, MAX, 0x2D},
+ /* MATH OPERATIONS */
+ /* ADD src : f100 1010 ssss ssss */
+ {"ADD", 1, {A_IMM | A_REG | A_MEM | A_DISP, 0}, FMT, {0x4a, 0},
+ {IMM | REG | MEM | DISP, 0}, MAX, 0x14},
+ /* ADDC src : f110 1010 ssss ssss */
+ {"ADDC", 1, {A_IMM | A_REG | A_MEM | A_DISP, 0}, FMT, {0x6a, 0},
+ {IMM | REG | MEM | DISP, 0}, MAX, 0x16},
+ /* SUB src : f101 1010 ssss ssss */
+ {"SUB", 1, {A_IMM | A_REG | A_MEM | A_DISP, 0}, FMT, {0x5a, 0},
+ {IMM | REG | MEM | DISP, 0}, MAX, 0x15},
+ /* SUBB src : f111 1010 ssss ssss */
+ {"SUBB", 1, {A_IMM | A_REG | A_MEM | A_DISP, 0}, FMT, {0x7a, 0},
+ {IMM | REG | MEM | DISP, 0}, MAX, 0x17},
+ /* BRANCHING OPERATIONS */
+
+ /* DJNZ LC[0] src: f100 1101 ssss ssss */
+ {"DJNZ", 2, {A_REG, A_IMM | A_REG | A_MEM | A_DISP}, FMT, {0x4d, 0},
+ {IMM | REG | MEM | DISP, 0}, MAX, 0xA4},
+ /* DJNZ LC[1] src: f101 1101 ssss ssss */
+ {"DJNZ", 2, {A_REG, A_IMM | A_REG | A_MEM | A_DISP}, FMT, {0x5d, 0},
+ {IMM | REG | MEM | DISP, 0}, MAX, 0xA5},
+ /* CALL src : f011 1101 ssss ssss */
+ {"CALL", 1, {A_IMM | A_REG | A_MEM | A_DISP, 0}, FMT, {0x3d, 0},
+ {IMM | REG | MEM | DISP, 0}, MAX, 0xA3},
+ /* JUMP src : f000 1100 ssss ssss */
+ {"JUMP", 1, {A_IMM | A_REG | A_MEM | A_DISP, 0}, FMT, {0x0c, 0},
+ {IMM | REG | MEM | DISP, 0}, MAX, 0x50},
+ /* JUMP C,src : f010 1100 ssss ssss */
+ {"JUMP", 2, {FLAG_C, A_IMM | A_REG | A_MEM | A_DISP}, FMT, {0x2c, 0},
+ {IMM | REG | MEM | DISP, 0}, MAX, 0x52},
+ /* JUMP NC,src: f110 1100 ssss ssss */
+ {"JUMP", 2, {FLAG_NC, A_IMM | A_REG | A_MEM | A_DISP}, FMT, {0x6c, 0},
+ {IMM | REG | MEM | DISP, 0}, MAX, 0x56},
+ /* JUMP Z,src : f001 1100 ssss ssss */
+ {"JUMP", 2, {FLAG_Z, A_IMM | A_REG | A_MEM | A_DISP}, FMT, {0x1c, 0},
+ {IMM | REG | MEM | DISP, 0}, MAX, 0x51},
+ /* JUMP NZ,src: f101 1100 ssss ssss */
+ {"JUMP", 2, {FLAG_NZ, A_IMM | A_REG | A_MEM | A_DISP}, FMT, {0x5c, 0},
+ {IMM | REG | MEM | DISP, 0}, MAX, 0x55},
+ /* JUMP E,src : 0011 1100 ssss ssss */
+ {"JUMP", 2, {FLAG_E, A_IMM | A_DISP}, 0, {0x3c, 0}, {IMM, 0}, MAX, 0x53},
+ /* JUMP NE,src: 0111 1100 ssss ssss */
+ {"JUMP", 2, {FLAG_NE, A_IMM | A_DISP}, 0, {0x7c, 0}, {IMM, 0}, MAX, 0x57},
+ /* JUMP S,src : f100 1100 ssss ssss */
+ {"JUMP", 2, {FLAG_S, A_IMM | A_REG | A_MEM | A_DISP}, FMT, {0x4c, 0},
+ {IMM | REG | MEM | DISP, 0}, MAX, 0x54},
+ /* RET : 1000 1100 0000 1101 */
+ {"RET", 0, {0, 0}, 1, {0x0c, 0}, {0x0d, 0}, MAX, 0x68},
+ /* RET C : 1010 1100 0000 1101 */
+ {"RET", 1, {FLAG_C, 0}, 1, {0x2c, 0}, {0x0d, 0}, MAX, 0x6A},
+ /* RET NC : 1110 1100 0000 1101 */
+ {"RET", 1, {FLAG_NC, 0}, 1, {0x6c, 0}, {0x0d, 0}, MAX, 0x6E},
+ /* RET Z : 1001 1100 0000 1101 */
+ {"RET", 1, {FLAG_Z, 0}, 1, {0x1c, 0}, {0x0d, 0}, MAX, 0x69},
+ /* RET NZ : 1101 1100 0000 1101 */
+ {"RET", 1, {FLAG_NZ, 0}, 1, {0x5c, 0}, {0x0d, 0}, MAX, 0x6D},
+ /* RET S : 1100 1100 0000 1101 */
+ {"RET", 1, {FLAG_S, 0}, 1, {0x4c, 0}, {0x0d, 0}, MAX, 0x6C},
+ /* RETI : 1000 1100 1000 1101 */
+ {"RETI", 0, {0, 0}, 1, {0x0c, 0}, {0x8d, 0}, MAX, 0x78},
+ /* ADDED ACCORDING TO NEW SPECIFICATION */
+
+ /* RETI C : 1010 1100 1000 1101 */
+ {"RETI", 1, {FLAG_C, 0}, 1, {0x2c, 0}, {0x8d, 0}, MAX, 0x7A},
+ /* RETI NC : 1110 1100 1000 1101 */
+ {"RETI", 1, {FLAG_NC, 0}, 1, {0x6c, 0}, {0x8d, 0}, MAX, 0x7E},
+ /* RETI Z : 1001 1100 1000 1101 */
+ {"RETI", 1, {FLAG_Z, 0}, 1, {0x1c, 0}, {0x8d, 0}, MAX, 0x79},
+ /* RETI NZ : 1101 1100 1000 1101 */
+ {"RETI", 1, {FLAG_NZ, 0}, 1, {0x5c, 0}, {0x8d, 0}, MAX, 0x7D},
+ /* RETI S : 1100 1100 1000 1101 */
+ {"RETI", 1, {FLAG_S, 0}, 1, {0x4c, 0}, {0x8d, 0}, MAX, 0x7C},
+ /* MISCELLANEOUS INSTRUCTIONS */
+ /* CMP src : f111 1000 ssss ssss */
+ {"CMP", 1, {A_REG | A_IMM | A_MEM | A_DISP, 0}, FMT, {0x78, 0},
+ {REG | MEM | IMM | DISP, 0}, MAX, 0xD7},
+ /* DATA TRANSFER OPERATIONS */
+ /* XCH : 1000 1010 1000 1010 */
+ {"XCH", 0, {0, 0}, 1, {0x0a, 0}, {0x8a, 0}, MAXQ20, 0x28},
+ /* XCHN : 1000 1010 0111 1010 */
+ {"XCHN", 0, {0, 0}, 1, {0x0a, 0}, {0x7a, 0}, MAX, 0x27},
+ /* PUSH src : f000 1101 ssss ssss */
+ {"PUSH", 1, {A_REG | A_IMM | A_MEM | A_DISP, 0}, FMT, {0x0d, 0},
+ {IMM | REG | MEM | DISP, 0}, MAX, 0xA0},
+ /* POP dst : 1ddd dddd 0000 1101 */
+ {"POP", 1, {A_REG, 0}, 1, {REG, 0}, {0x0d, 0}, MAX, 0xB0},
+ /* Added according to new spec */
+ /* POPI dst : 1ddd dddd 1000 1101 */
+ {"POPI", 1, {A_REG, 0}, 1, {REG, 0}, {0x8d, 0}, MAX, 0xC0},
+ /* MOVE dst,src: fddd dddd ssss ssss */
+ {"MOVE", 2, {A_REG | A_MEM, A_REG | A_IMM | A_MEM | A_DATA | A_DISP}, FMT,
+ {REG | MEM, 0}, {REG | IMM | MEM | DATA | A_DISP, 0}, MAX, 0x80},
+ /* BIT OPERATIONS */
+ /* MOVE C,Acc.<b> : 1110 1010 bbbb 1010 */
+ {"MOVE", 2, {FLAG_C, ACC_BIT}, 1, {0x6a, 0}, {BIT, 0xa}, MAX, 0x3E},
+ /* MOVE C,#0 : 1101 1010 0000 1010 */
+ {"MOVE", 2, {FLAG_C, A_BIT_0}, 1, {0x5a, 0}, {0x0a, 0}, MAX, 0x3D},
+ /* MOVE C,#1 : 1101 1010 0001 1010 */
+ {"MOVE", 2, {FLAG_C, A_BIT_1}, 1, {0x5a, 0}, {0x1a, 0}, MAX, 0x3D},
+ /* MOVE Acc.<b>,C : 1111 1010 bbbb 1010 */
+ {"MOVE", 2, {ACC_BIT, FLAG_C}, 1, {0x7a, 0}, {BIT, 0xa}, MAX, 0x3F},
+ /* MOVE dst.<b>,#0 : 1ddd dddd 0bbb 0111 */
+ {"MOVE", 2, {DST_BIT, A_BIT_0}, 1, {REG, 0}, {ZEROBIT, 0x7}, MAX, 0x40},
+ /* MOVE dst.<b>,#1 : 1ddd dddd 1bbb 0111 */
+ {"MOVE", 2, {DST_BIT, A_BIT_1}, 1, {REG, 0}, {ONEBIT, 0x7}, MAX, 0x41},
+ /* MOVE C,src.<b> : fbbb 0111 ssss ssss */
+ {"MOVE", 2, {FLAG_C, SRC_BIT}, FMT, {BIT, 0x7}, {REG, 0}, MAX, 0x97},
+ /* NOP : 1101 1010 0011 1010 */
+ {"NOP", 0, {0, 0}, NOP_FMT, {NOP_DST, 0}, {NOP_SRC, 0}, MAX, 0x3D},
+ {NULL, 0, {0, 0}, 0, {0, 0}, {0, 0}, 0, 0x00}
+};
+
+/* All the modules. */
+
+#define MOD0 0x0
+#define MOD1 0x1
+#define MOD2 0x2
+#define MOD3 0x3
+#define MOD4 0x4
+#define MOD5 0x5
+#define MOD6 0x6
+#define MOD7 0x7
+#define MOD8 0x8
+#define MOD9 0x9
+#define MODA 0xa
+#define MODB 0xb
+#define MODC 0xc
+#define MODD 0xd
+#define MODE 0xe
+#define MODF 0xf
+
+/* Added according to new specification. */
+#define MOD10 0x10
+#define MOD11 0x11
+#define MOD12 0x12
+#define MOD13 0x13
+#define MOD14 0x14
+#define MOD15 0x15
+#define MOD16 0x16
+#define MOD17 0x17
+#define MOD18 0x18
+#define MOD19 0x19
+#define MOD1A 0x1a
+#define MOD1B 0x1b
+#define MOD1C 0x1c
+#define MOD1D 0x1d
+#define MOD1E 0x1e
+#define MOD1F 0x1f
+
+/* - Peripheral Register Modules - */
+/* Serial Register Modules. */
+#define CTRL MOD8 /* For the module containing the control registers. */
+#define ACC MOD9 /* For the module containing the 16 accumulators. */
+#define Act_ACC MODA /* For the module containing the active accumulator. */
+#define PFX MODB /* For the module containing the prefix registers. */
+#define IP MODC /* For the module containing the instruction pointer register. */
+#define SPIV MODD /* For the module containing the stack pointer and the interrupt vector. */
+#define LC MODD /* For the module containing the loop counters and HILO registers. */
+#define DP MODF /* For the module containig the data pointer registers. */
+
+/* Register Types. */
+typedef enum _Reg_type
+{ Reg_8R, /* 8 bit register. read only. */
+ Reg_16R, /* 16 bit register, read only. */
+ Reg_8W, /* 8 bit register, both read and write. */
+ Reg_16W /* 16 bit register, both read and write. */
+}
+Reg_type;
+
+/* Register Structure. */
+typedef struct reg
+{
+ char *reg_name; /* Register name. */
+ short int Mod_name; /* The module name. */
+ short int Mod_index; /* The module index. */
+ int opcode; /* The opcode of the register. */
+ Reg_type rtype; /* 8 bit/16 bit and read only/read write. */
+ int arch; /* The Machine architecture. */
+}
+reg_entry;
+
+reg_entry *new_reg_table = NULL;
+int num_of_reg = 0;
+
+typedef struct
+{
+ char *rname;
+ int rindex;
+}
+reg_index;
+
+/* Register Table description. */
+reg_entry system_reg_table[] =
+{
+ /* Serial Registers */
+ /* MODULE 8 Registers : I call them the control registers. */
+ /* Accumulator Pointer CTRL[0h] */
+ {
+ "AP", CTRL, 0x0, 0x00 | CTRL, Reg_8W, MAX},
+ /* Accumulator Pointer Control Register : CTRL[1h] */
+
+ {
+ "APC", CTRL, 0x1, 0x10 | CTRL, Reg_8W, MAX},
+ /* Processor Status Flag Register CTRL[4h] Note: Bits 6 and 7 read only */
+ {
+ "PSF", CTRL, 0x4, 0x40 | CTRL, Reg_8W, MAX},
+ /* Interrupt and Control Register : CTRL[5h] */
+ {
+ "IC", CTRL, 0x5, 0x50 | CTRL, Reg_8W, MAX},
+ /* Interrupt Mask Register : CTRL[6h] */
+ {
+ "IMR", CTRL, 0x6, 0x60 | CTRL, Reg_8W, MAX},
+ /* Interrupt System Control : CTRL[8h] */
+ {
+ "SC", CTRL, 0x8, 0x80 | CTRL, Reg_8W, MAX},
+ /* Interrupt Identification Register : CTRL[Bh] */
+ {
+ "IIR", CTRL, 0xb, 0xb0 | CTRL, Reg_8R, MAX},
+ /* System Clock Control Register : CTRL[Eh] Note: Bit 5 is read only */
+ {
+ "CKCN", CTRL, 0xe, 0xe0 | CTRL, Reg_8W, MAX},
+ /* Watchdog Control Register : CTRL[Fh] */
+ {
+ "WDCN", CTRL, 0xf, 0xf0 | CTRL, Reg_8W, MAX},
+ /* The 16 accumulator registers : ACC[0h-Fh] */
+ {
+ "A[0]", ACC, 0x0, 0x00 | ACC, Reg_16W, MAXQ20},
+ {
+ "A[1]", ACC, 0x1, 0x10 | ACC, Reg_16W, MAXQ20},
+ {
+ "A[2]", ACC, 0x2, 0x20 | ACC, Reg_16W, MAXQ20},
+ {
+ "A[3]", ACC, 0x3, 0x30 | ACC, Reg_16W, MAXQ20},
+ {
+ "A[4]", ACC, 0x4, 0x40 | ACC, Reg_16W, MAXQ20},
+ {
+ "A[5]", ACC, 0x5, 0x50 | ACC, Reg_16W, MAXQ20},
+ {
+ "A[6]", ACC, 0x6, 0x60 | ACC, Reg_16W, MAXQ20},
+ {
+ "A[7]", ACC, 0x7, 0x70 | ACC, Reg_16W, MAXQ20},
+ {
+ "A[8]", ACC, 0x8, 0x80 | ACC, Reg_16W, MAXQ20},
+ {
+ "A[9]", ACC, 0x9, 0x90 | ACC, Reg_16W, MAXQ20},
+ {
+ "A[10]", ACC, 0xa, 0xa0 | ACC, Reg_16W, MAXQ20},
+ {
+ "A[11]", ACC, 0xb, 0xb0 | ACC, Reg_16W, MAXQ20},
+ {
+ "A[12]", ACC, 0xc, 0xc0 | ACC, Reg_16W, MAXQ20},
+ {
+ "A[13]", ACC, 0xd, 0xd0 | ACC, Reg_16W, MAXQ20},
+ {
+ "A[14]", ACC, 0xe, 0xe0 | ACC, Reg_16W, MAXQ20},
+ {
+ "A[15]", ACC, 0xf, 0xf0 | ACC, Reg_16W, MAXQ20},
+ /* The Active Accumulators : Act_Acc[0h-1h] */
+ {
+ "ACC", Act_ACC, 0x0, 0x00 | Act_ACC, Reg_16W, MAXQ20},
+ {
+ "A[AP]", Act_ACC, 0x1, 0x10 | Act_ACC, Reg_16W, MAXQ20},
+ /* The 16 accumulator registers : ACC[0h-Fh] */
+ {
+ "A[0]", ACC, 0x0, 0x00 | ACC, Reg_8W, MAXQ10},
+ {
+ "A[1]", ACC, 0x1, 0x10 | ACC, Reg_8W, MAXQ10},
+ {
+ "A[2]", ACC, 0x2, 0x20 | ACC, Reg_8W, MAXQ10},
+ {
+ "A[3]", ACC, 0x3, 0x30 | ACC, Reg_8W, MAXQ10},
+ {
+ "A[4]", ACC, 0x4, 0x40 | ACC, Reg_8W, MAXQ10},
+ {
+ "A[5]", ACC, 0x5, 0x50 | ACC, Reg_8W, MAXQ10},
+ {
+ "A[6]", ACC, 0x6, 0x60 | ACC, Reg_8W, MAXQ10},
+ {
+ "A[7]", ACC, 0x7, 0x70 | ACC, Reg_8W, MAXQ10},
+ {
+ "A[8]", ACC, 0x8, 0x80 | ACC, Reg_8W, MAXQ10},
+ {
+ "A[9]", ACC, 0x9, 0x90 | ACC, Reg_8W, MAXQ10},
+ {
+ "A[10]", ACC, 0xa, 0xa0 | ACC, Reg_8W, MAXQ10},
+ {
+ "A[11]", ACC, 0xb, 0xb0 | ACC, Reg_8W, MAXQ10},
+ {
+ "A[12]", ACC, 0xc, 0xc0 | ACC, Reg_8W, MAXQ10},
+ {
+ "A[13]", ACC, 0xd, 0xd0 | ACC, Reg_8W, MAXQ10},
+ {
+ "A[14]", ACC, 0xe, 0xe0 | ACC, Reg_8W, MAXQ10},
+ {
+ "A[15]", ACC, 0xf, 0xf0 | ACC, Reg_8W, MAXQ10},
+ /* The Active Accumulators : Act_Acc[0h-1h] */
+ {
+ "A[AP]", Act_ACC, 0x1, 0x10 | Act_ACC, Reg_8W, MAXQ10},
+ /* The Active Accumulators : Act_Acc[0h-1h] */
+ {
+ "ACC", Act_ACC, 0x0, 0x00 | Act_ACC, Reg_8W, MAXQ10},
+ /* The Prefix Registers : PFX[0h,2h] */
+ {
+ "PFX[0]", PFX, 0x0, 0x00 | PFX, Reg_16W, MAX},
+ {
+ "PFX[1]", PFX, 0x1, 0x10 | PFX, Reg_16W, MAX},
+ {
+ "PFX[2]", PFX, 0x2, 0x20 | PFX, Reg_16W, MAX},
+ {
+ "PFX[3]", PFX, 0x3, 0x30 | PFX, Reg_16W, MAX},
+ {
+ "PFX[4]", PFX, 0x4, 0x40 | PFX, Reg_16W, MAX},
+ {
+ "PFX[5]", PFX, 0x5, 0x50 | PFX, Reg_16W, MAX},
+ {
+ "PFX[6]", PFX, 0x6, 0x60 | PFX, Reg_16W, MAX},
+ {
+ "PFX[7]", PFX, 0x7, 0x70 | PFX, Reg_16W, MAX},
+ /* The Instruction Pointer Registers : IP[0h,8h] */
+ {
+ "IP", IP, 0x0, 0x00 | IP, Reg_16W, MAX},
+ /* The Stack Pointer Registers : SPIV[1h,9h] */
+ {
+ "SP", SPIV, 0x1, 0x10 | SPIV, Reg_16W, MAX},
+ /* The Interrupt Vector Registers : SPIV[2h,Ah] */
+ {
+ "IV", SPIV, 0x2, 0x20 | SPIV, Reg_16W, MAX},
+ /* ADDED for New Specification */
+
+ /* The Loop Counter Registers : LCHILO[0h-4h,8h-Bh] */
+ {
+ "LC[0]", LC, 0x6, 0x60 | LC, Reg_16W, MAX},
+ {
+ "LC[1]", LC, 0x7, 0x70 | LC, Reg_16W, MAX},
+ /* MODULE Eh Whole Column has changed */
+
+ {
+ "OFFS", MODE, 0x3, 0x30 | MODE, Reg_8W, MAX},
+ {
+ "DPC", MODE, 0x4, 0x40 | MODE, Reg_16W, MAX},
+ {
+ "GR", MODE, 0x5, 0x50 | MODE, Reg_16W, MAX},
+ {
+ "GRL", MODE, 0x6, 0x60 | MODE, Reg_8W, MAX},
+ {
+ "BP", MODE, 0x7, 0x70 | MODE, Reg_16W, MAX},
+ {
+ "GRS", MODE, 0x8, 0x80 | MODE, Reg_16W, MAX},
+ {
+ "GRH", MODE, 0x9, 0x90 | MODE, Reg_8W, MAX},
+ {
+ "GRXL", MODE, 0xA, 0xA0 | MODE, Reg_8R, MAX},
+ {
+ "FP", MODE, 0xB, 0xB0 | MODE, Reg_16R, MAX},
+ /* The Data Pointer registers : DP[3h,7h,Bh,Fh] */
+ {
+ "DP[0]", DP, 0x3, 0x30 | DP, Reg_16W, MAX},
+ {
+ "DP[1]", DP, 0x7, 0x70 | DP, Reg_16W, MAX},
+};
+typedef struct
+{
+ char *name;
+ int type;
+}
+match_table;
+
+#define GPIO0 0x00 /* Gerneral Purpose I/O Module 0. */
+#define GPIO1 0x01 /* Gerneral Purpose I/O Module 1. */
+#define RTC 0x00 /* Real Time Clock Module. */
+#define MAC 0x02 /* Hardware Multiplier Module. */
+#define SER0 0x02 /* Contains the UART Registers. */
+#define SPI 0x03 /* Serial Pheripheral Interface Module. */
+#define OWBM 0x03 /* One Wire Bus Module. */
+#define SER1 0x03 /* Contains the UART Registers. */
+#define TIMER20 0x03 /* Timer Counter Module 2. */
+#define TIMER21 0x04 /* Timer Counter Module 2. */
+#define JTAGD 0x03 /* In-Circuit Debugging Support. */
+#define LCD 0x03 /* LCD register Modules. */
+
+/* Plugable modules register table f. */
+
+reg_entry peripheral_reg_table[] =
+{
+ /* -------- The GPIO Module Registers -------- */
+ /* Port n Output Registers : GPIO[0h-4h] */
+ {
+ "PO0", GPIO0, 0x0, 0x00 | MOD0, Reg_8W, MAX},
+ {
+ "PO1", GPIO0, 0x1, 0x10 | MOD0, Reg_8W, MAX},
+ {
+ "PO2", GPIO0, 0x2, 0x20 | MOD0, Reg_8W, MAX},
+ {
+ "PO3", GPIO0, 0x3, 0x30 | MOD0, Reg_8W, MAX},
+ /* External Interrupt Flag Register : GPIO[6h] */
+ {
+ "EIF0", GPIO0, 0x6, 0x60 | MOD0, Reg_8W, MAX},
+ /* External Interrupt Enable Register : GPIO[7h] */
+ {
+ "EIE0", GPIO0, 0x7, 0x70 | MOD0, Reg_8W, MAX},
+ /* Port n Input Registers : GPIO[8h-Bh] */
+ {
+ "PI0", GPIO0, 0x8, 0x80 | MOD0, Reg_8W, MAX},
+ {
+ "PI1", GPIO0, 0x9, 0x90 | MOD0, Reg_8W, MAX},
+ {
+ "PI2", GPIO0, 0xa, 0xa0 | MOD0, Reg_8W, MAX},
+ {
+ "PI3", GPIO0, 0xb, 0xb0 | MOD0, Reg_8W, MAX},
+ {
+ "EIES0", GPIO0, 0xc, 0xc0 | MOD0, Reg_8W, MAX},
+ /* Port n Direction Registers : GPIO[Ch-Fh] */
+ {
+ "PD0", GPIO0, 0x10, 0x10 | MOD0, Reg_8W, MAX},
+ {
+ "PD1", GPIO0, 0x11, 0x11 | MOD0, Reg_8W, MAX},
+ {
+ "PD2", GPIO0, 0x12, 0x12 | MOD0, Reg_8W, MAX},
+ {
+ "PD3", GPIO0, 0x13, 0x13 | MOD0, Reg_8W, MAX},
+ /* -------- Real Time Counter Module RTC -------- */
+ /* RTC Control Register : [01h] */
+ {
+ "RCNT", RTC, 0x19, 0x19 | MOD0, Reg_16W, MAX},
+ /* RTC Seconds High [02h] */
+ {
+ "RTSS", RTC, 0x1A, 0x1A | MOD0, Reg_8W, MAX},
+ /* RTC Seconds Low [03h] */
+ {
+ "RTSH", RTC, 0x1b, 0x1b | MOD0, Reg_16W, MAX},
+ /* RTC Subsecond Register [04h] */
+ {
+ "RTSL", RTC, 0x1C, 0x1C | MOD0, Reg_16W, MAX},
+ /* RTC Alarm seconds high [05h] */
+ {
+ "RSSA", RTC, 0x1D, 0x1D | MOD0, Reg_8W, MAX},
+ /* RTC Alarm seconds high [06h] */
+ {
+ "RASH", RTC, 0x1E, 0x1E | MOD0, Reg_8W, MAX},
+ /* RTC Subsecond Alarm Register [07h] */
+ {
+ "RASL", RTC, 0x1F, 0x1F | MOD0, Reg_16W, MAX},
+ /* -------- The GPIO Module Registers -------- */
+ /* Port n Output Registers : GPIO[0h-4h] */
+ {
+ "PO4", GPIO1, 0x0, 0x00 | MOD1, Reg_8W, MAX},
+ {
+ "PO5", GPIO1, 0x1, 0x10 | MOD1, Reg_8W, MAX},
+ {
+ "PO6", GPIO1, 0x2, 0x20 | MOD1, Reg_8W, MAX},
+ {
+ "PO7", GPIO1, 0x3, 0x30 | MOD1, Reg_8W, MAX},
+ /* External Interrupt Flag Register : GPIO[6h] */
+ {
+ "EIF1", GPIO0, 0x6, 0x60 | MOD1, Reg_8W, MAX},
+ /* External Interrupt Enable Register : GPIO[7h] */
+ {
+ "EIE1", GPIO0, 0x7, 0x70 | MOD1, Reg_8W, MAX},
+ /* Port n Input Registers : GPIO[8h-Bh] */
+ {
+ "PI4", GPIO1, 0x8, 0x80 | MOD1, Reg_8W, MAX},
+ {
+ "PI5", GPIO1, 0x9, 0x90 | MOD1, Reg_8W, MAX},
+ {
+ "PI6", GPIO1, 0xa, 0xa0 | MOD1, Reg_8W, MAX},
+ {
+ "PI7", GPIO1, 0xb, 0xb0 | MOD1, Reg_8W, MAX},
+ {
+ "EIES1", GPIO1, 0xc, 0xc0 | MOD1, Reg_8W, MAX},
+ /* Port n Direction Registers : GPIO[Ch-Fh] */
+ {
+ "PD4", GPIO1, 0x10, 0x10 | MOD1, Reg_8W, MAX},
+ {
+ "PD5", GPIO1, 0x11, 0x11 | MOD1, Reg_8W, MAX},
+ {
+ "PD6", GPIO1, 0x12, 0x12 | MOD1, Reg_8W, MAX},
+ {
+ "PD7", GPIO1, 0x13, 0x13 | MOD1, Reg_8W, MAX},
+#if 0
+ /* Supply Boltage Check Register */
+ {
+ "SVS", GPIO1, 0x1e, 0x1e | GPIO1, Reg_8W, MAX},
+ /* Wake up output register */
+ {
+ "WK0", GPIO1, 0x1f, 0x1f | GPIO1, Reg_8W, MAX},
+#endif /* */
+
+ /* -------- MAC Hardware multiplier module -------- */
+ /* MAC Hardware Multiplier control register: [01h] */
+ {
+ "MCNT", MAC, 0x1, 0x10 | MOD2, Reg_8W, MAX},
+ /* MAC Multiplier Operand A Register [02h] */
+ {
+ "MA", MAC, 0x2, 0x20 | MOD2, Reg_16W, MAX},
+ /* MAC Multiplier Operand B Register [03h] */
+ {
+ "MB", MAC, 0x3, 0x30 | MOD2, Reg_16W, MAX},
+ /* MAC Multiplier Accumulator 2 Register [04h] */
+ {
+ "MC2", MAC, 0x4, 0x40 | MOD2, Reg_16W, MAX},
+ /* MAC Multiplier Accumulator 1 Register [05h] */
+ {
+ "MC1", MAC, 0x5, 0x50 | MOD2, Reg_16W, MAX},
+ /* MAC Multiplier Accumulator 0 Register [06h] */
+ {
+ "MC0", MAC, 0x6, 0x60 | MOD2, Reg_16W, MAX},
+ /* -------- The Serial I/O module SER -------- */
+ /* UART registers */
+ /* Serial Port Control Register : SER[6h] */
+ {
+ "SCON0", SER0, 0x6, 0x60 | MOD2, Reg_8W, MAX},
+ /* Serial Data Buffer Register : SER[7h] */
+ {
+ "SBUF0", SER0, 0x7, 0x70 | MOD2, Reg_8W, MAX},
+ /* Serial Port Mode Register : SER[4h] */
+ {
+ "SMD0", SER0, 0x8, 0x80 | MOD2, Reg_8W, MAX},
+ /* Serial Port Phase Register : SER[4h] */
+ {
+ "PR0", SER1, 0x9, 0x90 | MOD2, Reg_16W, MAX},
+ /* ------ LCD Display Module ---------- */
+ {
+ "LCRA", LCD, 0xd, 0xd0 | MOD2, Reg_16W, MAX},
+ {
+ "LCFG", LCD, 0xe, 0xe0 | MOD2, Reg_8W, MAX},
+ {
+ "LCD16", LCD, 0xf, 0xf0 | MOD2, Reg_8W, MAX},
+ {
+ "LCD0", LCD, 0x10, 0x10 | MOD2, Reg_8W, MAX},
+ {
+ "LCD1", LCD, 0x11, 0x11 | MOD2, Reg_8W, MAX},
+ {
+ "LCD2", LCD, 0x12, 0x12 | MOD2, Reg_8W, MAX},
+ {
+ "LCD3", LCD, 0x13, 0x13 | MOD2, Reg_8W, MAX},
+ {
+ "LCD4", LCD, 0x14, 0x14 | MOD2, Reg_8W, MAX},
+ {
+ "LCD5", LCD, 0x15, 0x15 | MOD2, Reg_8W, MAX},
+ {
+ "LCD6", LCD, 0x16, 0x16 | MOD2, Reg_8W, MAX},
+ {
+ "LCD7", LCD, 0x17, 0x17 | MOD2, Reg_8W, MAX},
+ {
+ "LCD8", LCD, 0x18, 0x18 | MOD2, Reg_8W, MAX},
+ {
+ "LCD9", LCD, 0x19, 0x19 | MOD2, Reg_8W, MAX},
+ {
+ "LCD10", LCD, 0x1a, 0x1a | MOD2, Reg_8W, MAX},
+ {
+ "LCD11", LCD, 0x1b, 0x1b | MOD2, Reg_8W, MAX},
+ {
+ "LCD12", LCD, 0x1c, 0x1c | MOD2, Reg_8W, MAX},
+ {
+ "LCD13", LCD, 0x1d, 0x1d | MOD2, Reg_8W, MAX},
+ {
+ "LCD14", LCD, 0x1e, 0x1e | MOD2, Reg_8W, MAX},
+ {
+ "LCD15", LCD, 0x1f, 0x1f | MOD2, Reg_8W, MAX},
+ /* -------- SPI registers -------- */
+ /* SPI data buffer Register : SER[7h] */
+ {
+ "SPIB", SPI, 0x5, 0x50 | MOD3, Reg_16W, MAX},
+ /* SPI Control Register : SER[8h] Note : Bit 7 is a read only bit */
+ {
+ "SPICN", SPI, 0x15, 0x15 | MOD3, Reg_8W, MAX},
+ /* SPI Configuration Register : SER[9h] Note : Bits 4,3 and 2 are read
+ only. */
+ {
+ "SPICF", SPI, 0x16, 0x16 | MOD3, Reg_8W, MAX},
+ /* SPI Clock Register : SER[Ah] */
+ {
+ "SPICK", SPI, 0x17, 0x17 | MOD3, Reg_8W, MAX},
+ /* -------- One Wire Bus Master OWBM -------- */
+ /* OWBM One Wire address Register register: [01h] */
+ {
+ "OWA", OWBM, 0x13, 0x13 | MOD3, Reg_8W, MAX},
+ /* OWBM One Wire Data register: [02h] */
+ {
+ "OWD", OWBM, 0x14, 0x14 | MOD3, Reg_8W, MAX},
+ /* -------- The Serial I/O module SER -------- */
+ /* UART registers */
+ /* Serial Port Control Register : SER[6h] */
+ {
+ "SCON1", SER1, 0x6, 0x60 | MOD3, Reg_8W, MAX},
+ /* Serial Data Buffer Register : SER[7h] */
+ {
+ "SBUF1", SER1, 0x7, 0x70 | MOD3, Reg_8W, MAX},
+ /* Serial Port Mode Register : SER[4h] */
+ {
+ "SMD1", SER1, 0x8, 0x80 | MOD3, Reg_8W, MAX},
+ /* Serial Port Phase Register : SER[4h] */
+ {
+ "PR1", SER1, 0x9, 0x90 | MOD3, Reg_16W, MAX},
+ /* -------- Timer/Counter 2 Module -------- */
+ /* Timer 2 configuration Register : TC[3h] */
+ {
+ "T2CNA0", TIMER20, 0x0, 0x00 | MOD3, Reg_8W, MAX},
+ {
+ "T2H0", TIMER20, 0x1, 0x10 | MOD3, Reg_8W, MAX},
+ {
+ "T2RH0", TIMER20, 0x2, 0x20 | MOD3, Reg_8W, MAX},
+ {
+ "T2CH0", TIMER20, 0x3, 0x30 | MOD3, Reg_8W, MAX},
+ {
+ "T2CNB0", TIMER20, 0xc, 0xc0 | MOD3, Reg_8W, MAX},
+ {
+ "T2V0", TIMER20, 0xd, 0xd0 | MOD3, Reg_16W, MAX},
+ {
+ "T2R0", TIMER20, 0xe, 0xe0 | MOD3, Reg_16W, MAX},
+ {
+ "T2C0", TIMER20, 0xf, 0xf0 | MOD3, Reg_16W, MAX},
+ {
+ "T2CFG0", TIMER20, 0x10, 0x10 | MOD3, Reg_8W, MAX},
+ /* Timer 2-1 configuration Register : TC[4h] */
+
+ {
+ "T2CNA1", TIMER21, 0x0, 0x00 | MOD4, Reg_8W, MAX},
+ {
+ "T2H1", TIMER21, 0x1, 0x10 | MOD4, Reg_8W, MAX},
+ {
+ "T2RH1", TIMER21, 0x2, 0x20 | MOD4, Reg_8W, MAX},
+ {
+ "T2CH1", TIMER21, 0x3, 0x30 | MOD4, Reg_8W, MAX},
+ {
+ "T2CNA2", TIMER21, 0x4, 0x40 | MOD4, Reg_8W, MAX},
+ {
+ "T2H2", TIMER21, 0x5, 0x50 | MOD4, Reg_8W, MAX},
+ {
+ "T2RH2", TIMER21, 0x6, 0x60 | MOD4, Reg_8W, MAX},
+ {
+ "T2CH2", TIMER21, 0x7, 0x70 | MOD4, Reg_8W, MAX},
+ {
+ "T2CNB1", TIMER21, 0x8, 0x80 | MOD4, Reg_8W, MAX},
+ {
+ "T2V1", TIMER21, 0x9, 0x90 | MOD4, Reg_16W, MAX},
+ {
+ "T2R1", TIMER21, 0xa, 0xa0 | MOD4, Reg_16W, MAX},
+ {
+ "T2C1", TIMER21, 0xb, 0xb0 | MOD4, Reg_16W, MAX},
+ {
+ "T2CNB2", TIMER21, 0xc, 0xc0 | MOD4, Reg_8W, MAX},
+ {
+ "T2V2", TIMER21, 0xd, 0xd0 | MOD4, Reg_16W, MAX},
+ {
+ "T2R2", TIMER21, 0xe, 0xe0 | MOD4, Reg_16W, MAX},
+ {
+ "T2C2", TIMER21, 0xf, 0xf0 | MOD4, Reg_16W, MAX},
+ {
+ "T2CFG1", TIMER21, 0x10, 0x10 | MOD4, Reg_8W, MAX},
+ {
+ "T2CFG2", TIMER21, 0x11, 0x11 | MOD4, Reg_8W, MAX},
+ {
+ NULL, 0, 0, 0, 0, 0}
+};
+
+/* Memory access argument. */
+struct mem_access
+{
+ char *name; /* Name of the Memory access operand. */
+ int opcode; /* Its corresponding opcode. */
+};
+typedef struct mem_access mem_access;
+
+/* The Memory table for accessing the data memory through particular registers. */
+struct mem_access mem_table[] =
+{
+ /* The Pop Operation on the stack. */
+ {"@SP--", 0x0d},
+ /* Data Pointer 0 */
+ {"@DP[0]", 0x0f},
+ /* Data Ponter 1 */
+ {"@DP[1]", 0x4f},
+ /* Data Pointer 0 post increment */
+ {"@DP[0]++", 0x1f},
+ /* Data Pointer 1 post increment */
+ {"@DP[1]++", 0x5f},
+ /* Data Pointer 0 post decrement */
+ {"@DP[0]--", 0x2f},
+ /* Data Pointer 1 post decrement */
+ {"@DP[1]--", 0x6f},
+ /* ADDED According to New Specification. */
+
+ {"@BP[OFFS]", 0x0E},
+ {"@BP[OFFS++]", 0x1E},
+ {"@BP[OFFS--]", 0x2E},
+ {"NUL", 0x76},
+ {"@++SP", 0x0D},
+ {"@BP[++OFFS]", 0x1E},
+ {"@BP[--OFFS]", 0x2E},
+ {"@++DP[0]", 0x1F},
+ {"@++DP[1]", 0x5F}, {"@--DP[0]", 0x2F}, {"@--DP[1]", 0x6F}
+};
+
+/* Register bit argument. */
+struct reg_bit
+{
+ reg_entry *reg;
+ int bit;
+};
+typedef struct reg_bit reg_bit;
+
+/* There are certain names given to particular bits of some registers.
+ These will be taken care of here. */
+struct bit_name
+{
+ char *name;
+ char *reg_bit;
+};
+typedef struct bit_name bit_name;
+
+bit_name bit_table[] =
+{
+ {
+ "RI", "SCON.0"},
+ /* FOr APC */
+ {
+ "MOD0", "APC.0"},
+ {
+ "MOD1", "APC.1"},
+ {
+ "MOD2", "APC.2"},
+ {
+ "IDS", "APC.6"},
+ {
+ "CLR", "APC.6"},
+ /* For PSF */
+ {
+ "E", "PSF.0"},
+ {
+ "C", "PSF.1"},
+ {
+ "OV", "PSF.2"},
+ {
+ "S", "PSF.6"},
+ {
+ "Z", "PSF.7"},
+ /* For IC */
+
+ {
+ "IGE", "IC.0"},
+ {
+ "INS", "IC.1"},
+ {
+ "CGDS", "IC.5"},
+ /* For IMR */
+
+ {
+ "IM0", "IMR.0"},
+ {
+ "IM1", "IMR.1"},
+ {
+ "IM2", "IMR.2"},
+ {
+ "IM3", "IMR.3"},
+ {
+ "IM4", "IMR.4"},
+ {
+ "IM5", "IMR.5"},
+ {
+ "IMS", "IMR.7"},
+ /* For SC */
+ {
+ "PWL", "SC.1"},
+ {
+ "ROD", "SC.2"},
+ {
+ "UPA", "SC.3"},
+ {
+ "CDA0", "SC.4"},
+ {
+ "CDA1", "SC.5"},
+ /* For IIR */
+
+ {
+ "II0", "IIR.0"},
+ {
+ "II1", "IIR.1"},
+ {
+ "II2", "IIR.2"},
+ {
+ "II3", "IIR.3"},
+ {
+ "II4", "IIR.4"},
+ {
+ "II5", "IIR.5"},
+ {
+ "IIS", "IIR.7"},
+ /* For CKCN */
+
+ {
+ "CD0", "CKCN.0"},
+ {
+ "CD1", "CKCN.1"},
+ {
+ "PMME", "CKCN.2"},
+ {
+ "SWB", "CKCN.3"},
+ {
+ "STOP", "CKCN.4"},
+ {
+ "RGMD", "CKCN.5"},
+ {
+ "RGSL", "CKCN.6"},
+ /* For WDCN */
+
+ {
+ "RWT", "WDCN.0"},
+ {
+ "EWT", "WDCN.1"},
+ {
+ "WTRF", "WDCN.2"},
+ {
+ "WDIF", "WDCN.3"},
+ {
+ "WD0", "WDCN.4"},
+ {
+ "WD1", "WDCN.5"},
+ {
+ "EWDI", "WDCN.6"},
+ {
+ "POR", "WDCN.7"},
+ /* For DPC */
+
+ {
+ "DPS0", "DPC.0"},
+ {
+ "DPS1", "DPC.1"},
+ {
+ "WBS0", "DPC.2"},
+ {
+ "WBS1", "DPC.3"},
+ {
+ "WBS2", "DPC.4"},
+
+ /* For SCON */
+ {
+ "TI", "SCON.1"},
+ {
+ "RB8", "SCON.2"},
+ {
+ "TB8", "SCON.3"},
+ {
+ "REN", "SCON.4"},
+ {
+ "SM2", "SCON.5"},
+ {
+ "SM1", "SCON.6"},
+ {
+ "SM0", "SCON.7"},
+ {
+ "FE", "SCON.7"}
+};
+
+const char *LSInstr[] =
+{
+ "LJUMP", "SJUMP", "LDJNZ", "SDJNZ", "LCALL", "SCALL", "JUMP",
+ "DJNZ", "CALL", NULL
+};
+
+typedef enum
+{
+ DST,
+ SRC,
+ BOTH,
+}
+type1;
+
+struct mem_access_syntax
+{
+ char name[12]; /* Name of the Memory access operand. */
+ type1 type;
+ char *invalid_op[5];
+};
+typedef struct mem_access_syntax mem_access_syntax;
+
+/* The Memory Access table for accessing the data memory through particular
+ registers. */
+const mem_access_syntax mem_access_syntax_table[] =
+{
+ {
+ "@SP--", SRC,
+ {
+ NULL, NULL, NULL, NULL, NULL}},
+ /* Data Pointer 0 */
+ {
+ "@DP[0]", BOTH,
+ {
+ "@DP[0]--", "@DP[0]++", NULL, NULL, NULL}},
+ /* Data Ponter 1 */
+ {
+ "@DP[1]", BOTH,
+ {
+ "@DP[1]--", "@DP[1]++", NULL, NULL, NULL}},
+ /* Data Pointer 0 post increment */
+ {
+ "@DP[0]++", SRC,
+ {
+ NULL, NULL, NULL, NULL, NULL}},
+ /* Data Pointer 1 post increment */
+ {
+ "@DP[1]++", SRC,
+ {
+ NULL, NULL, NULL, NULL, NULL}},
+ /* Data Pointer 0 post decrement */
+ {
+ "@DP[0]--", SRC,
+ {
+ NULL, NULL, NULL, NULL, NULL}},
+ /* Data Pointer 1 post decrement */
+ {
+ "@DP[1]--", SRC,
+ {
+ NULL, NULL, NULL, NULL, NULL}},
+ /* ADDED According to New Specification */
+
+ {
+ "@BP[OFFS]", BOTH,
+ {
+ "@BP[OFFS++]", "@BP[OFFS--]", NULL, NULL, NULL}},
+ {
+ "@BP[OFFS++]", SRC,
+ {
+ NULL, NULL, NULL, NULL, NULL}},
+ {
+ "@BP[OFFS--]", SRC,
+ {
+ NULL, NULL, NULL, NULL, NULL}},
+ {
+ "NUL", DST,
+ {
+ NULL, NULL, NULL, NULL, NULL}},
+ {
+ "@++SP", DST,
+ {
+ NULL, NULL, NULL, NULL, NULL}},
+ {
+ "@BP[++OFFS]", DST,
+ {
+ "@BP[OFFS--]", "@BP[OFFS++]", NULL, NULL, NULL}},
+ {
+ "@BP[--OFFS]", DST,
+ {
+ "@BP[OFFS--]", "@BP[OFFS++]", NULL, NULL, NULL}},
+ {
+ "@++DP[0]", DST,
+ {
+ "@DP[0]--", "@DP[0]++", NULL, NULL, NULL}},
+ {
+ "@++DP[1]", DST,
+ {
+ "@DP[1]--", "@DP[1]++", NULL, NULL, NULL}},
+ {
+ "@--DP[0]", DST,
+ {
+ "@DP[0]++", "@DP[0]--", NULL, NULL, NULL}},
+ {
+ "@--DP[1]", DST,
+ {
+ "@DP[1]++", "@DP[1]--", NULL, NULL, NULL}}
+};
+
+#endif
diff --git a/gnu/dist/binutils/include/opcode/mips.h b/gnu/dist/binutils/include/opcode/mips.h
index 5c3ddfcd7b5..a71ca475909 100644
--- a/gnu/dist/binutils/include/opcode/mips.h
+++ b/gnu/dist/binutils/include/opcode/mips.h
@@ -1,5 +1,6 @@
/* mips.h. Mips opcode list for GDB, the GNU debugger.
- Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
+ Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
+ 2003, 2004, 2005
Free Software Foundation, Inc.
Contributed by Ralph Campbell and OSF
Commented and modified by Ian Lance Taylor, Cygnus Support
@@ -192,6 +193,8 @@ struct mips_opcode
of bits describing the instruction, notably any relevant hazard
information. */
unsigned long pinfo;
+ /* A collection of additional bits describing the instruction. */
+ unsigned long pinfo2;
/* A collection of bits describing the instruction sets of which this
instruction or macro is a member. */
unsigned long membership;
@@ -376,10 +379,16 @@ struct mips_opcode
#define INSN_MULT 0x40000000
/* Instruction synchronize shared memory. */
#define INSN_SYNC 0x80000000
-/* Instruction reads MDMX accumulator. XXX FIXME: No bits left! */
-#define INSN_READ_MDMX_ACC 0
-/* Instruction writes MDMX accumulator. XXX FIXME: No bits left! */
-#define INSN_WRITE_MDMX_ACC 0
+
+/* These are the bits which may be set in the pinfo2 field of an
+ instruction. */
+
+/* Instruction is a simple alias (I.E. "move" for daddu/addu/or) */
+#define INSN2_ALIAS 0x00000001
+/* Instruction reads MDMX accumulator. */
+#define INSN2_READ_MDMX_ACC 0x00000002
+/* Instruction writes MDMX accumulator. */
+#define INSN2_WRITE_MDMX_ACC 0x00000004
/* Instruction is actually a macro. It should be ignored by the
disassembler, and requires special treatment by the assembler. */
@@ -470,6 +479,7 @@ struct mips_opcode
#define CPU_R6000 6000
#define CPU_RM7000 7000
#define CPU_R8000 8000
+#define CPU_RM9000 9000
#define CPU_R10000 10000
#define CPU_R12000 12000
#define CPU_MIPS16 16
@@ -489,6 +499,7 @@ struct mips_opcode
(((insn)->membership & isa) != 0 \
|| (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0) \
|| (cpu == CPU_RM7000 && ((insn)->membership & INSN_4650) != 0) \
+ || (cpu == CPU_RM9000 && ((insn)->membership & INSN_4650) != 0) \
|| (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) \
|| (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0) \
|| (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0) \
diff --git a/gnu/dist/binutils/include/opcode/mn10300.h b/gnu/dist/binutils/include/opcode/mn10300.h
index bd7faa110aa..a2e7784e992 100644
--- a/gnu/dist/binutils/include/opcode/mn10300.h
+++ b/gnu/dist/binutils/include/opcode/mn10300.h
@@ -1,5 +1,5 @@
/* mn10300.h -- Header file for Matsushita 10300 opcode table
- Copyright 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
+ Copyright 1996, 1997, 1998, 1999, 2003 Free Software Foundation, Inc.
Written by Jeff Law, Cygnus Support
This file is part of GDB, GAS, and the GNU binutils.
diff --git a/gnu/dist/binutils/include/opcode/msp430.h b/gnu/dist/binutils/include/opcode/msp430.h
index 19702254eef..dc3604ce883 100644
--- a/gnu/dist/binutils/include/opcode/msp430.h
+++ b/gnu/dist/binutils/include/opcode/msp430.h
@@ -1,6 +1,6 @@
/* Opcode table for the TI MSP430 microcontrollers
- Copyright 2002 Free Software Foundation, Inc.
+ Copyright 2002, 2004 Free Software Foundation, Inc.
Contributed by Dmitry Diky <diwil@mail.ru>
This program is free software; you can redistribute it and/or modify
@@ -103,6 +103,20 @@ static struct msp430_opcode_s msp430_opcodes[] =
MSP_INSN (rra, 2, 1, 0x1100, 0xff80),
MSP_INSN (swpb, 2, 1, 0x1080, 0xffc0),
MSP_INSN (rrc, 2, 1, 0x1000, 0xff80),
+ /* Simple polymorphs. */
+ MSP_INSN (beq, 4, 0, 0, 0xffff),
+ MSP_INSN (bne, 4, 1, 0, 0xffff),
+ MSP_INSN (blt, 4, 2, 0, 0xffff),
+ MSP_INSN (bltu, 4, 3, 0, 0xffff),
+ MSP_INSN (bge, 4, 4, 0, 0xffff),
+ MSP_INSN (bgeu, 4, 5, 0, 0xffff),
+ MSP_INSN (bltn, 4, 6, 0, 0xffff),
+ MSP_INSN (jump, 4, 7, 0, 0xffff),
+ /* Long polymorphs. */
+ MSP_INSN (bgt, 5, 0, 0, 0xffff),
+ MSP_INSN (bgtu, 5, 1, 0, 0xffff),
+ MSP_INSN (bleu, 5, 2, 0, 0xffff),
+ MSP_INSN (ble, 5, 3, 0, 0xffff),
/* End of instruction set. */
{ NULL, 0, 0, 0, 0 }
diff --git a/gnu/dist/binutils/include/opcode/ppc.h b/gnu/dist/binutils/include/opcode/ppc.h
index d55caa7568f..a21cc301e82 100644
--- a/gnu/dist/binutils/include/opcode/ppc.h
+++ b/gnu/dist/binutils/include/opcode/ppc.h
@@ -249,7 +249,7 @@ extern const struct powerpc_operand powerpc_operands[];
#define PPC_OPERAND_ABSOLUTE (01000)
/* This operand is optional, and is zero if omitted. This is used for
- the optional BF and L fields in the comparison instructions. The
+ example, in the optional BF field in the comparison instructions. The
assembler must count the number of operands remaining on the line,
and the number of operands remaining for the opcode, and decide
whether this operand is present or not. The disassembler should
diff --git a/gnu/dist/binutils/include/opcode/s390.h b/gnu/dist/binutils/include/opcode/s390.h
index f582a4e5104..54648f998bf 100644
--- a/gnu/dist/binutils/include/opcode/s390.h
+++ b/gnu/dist/binutils/include/opcode/s390.h
@@ -1,5 +1,5 @@
/* s390.h -- Header file for S390 opcode table
- Copyright 2000, 2001 Free Software Foundation, Inc.
+ Copyright 2000, 2001, 2003 Free Software Foundation, Inc.
Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com).
This file is part of BFD, the Binary File Descriptor library.
diff --git a/gnu/dist/binutils/include/opcode/tic54x.h b/gnu/dist/binutils/include/opcode/tic54x.h
index ae657225d61..a7958dc9ce0 100644
--- a/gnu/dist/binutils/include/opcode/tic54x.h
+++ b/gnu/dist/binutils/include/opcode/tic54x.h
@@ -1,5 +1,5 @@
/* tic54x.h -- Header file for TI TMS320C54X opcode table
- Copyright 1999, 2000 Free Software Foundation, Inc.
+ Copyright 1999, 2000, 2001 Free Software Foundation, Inc.
Written by Timothy Wall (twall@cygnus.com)
This file is part of GDB, GAS, and the GNU binutils.
diff --git a/gnu/dist/binutils/include/splay-tree.h b/gnu/dist/binutils/include/splay-tree.h
index 86707fc1d2f..e05aeb5afb8 100644
--- a/gnu/dist/binutils/include/splay-tree.h
+++ b/gnu/dist/binutils/include/splay-tree.h
@@ -81,21 +81,21 @@ typedef void (*splay_tree_deallocate_fn) PARAMS((void *, void *));
struct splay_tree_node_s GTY(())
{
/* The key. */
- splay_tree_key GTY ((use_param1 (""))) key;
+ splay_tree_key GTY ((use_param1)) key;
/* The value. */
- splay_tree_value GTY ((use_param2 (""))) value;
+ splay_tree_value GTY ((use_param2)) value;
/* The left and right children, respectively. */
- splay_tree_node GTY ((use_params (""))) left;
- splay_tree_node GTY ((use_params (""))) right;
+ splay_tree_node GTY ((use_params)) left;
+ splay_tree_node GTY ((use_params)) right;
};
/* The splay tree itself. */
struct splay_tree_s GTY(())
{
/* The root of the tree. */
- splay_tree_node GTY ((use_params (""))) root;
+ splay_tree_node GTY ((use_params)) root;
/* The comparision function. */
splay_tree_compare_fn comp;
@@ -109,7 +109,7 @@ struct splay_tree_s GTY(())
/* Allocate/free functions, and a data pointer to pass to them. */
splay_tree_allocate_fn allocate;
splay_tree_deallocate_fn deallocate;
- PTR GTY((skip (""))) allocate_data;
+ PTR GTY((skip)) allocate_data;
};
typedef struct splay_tree_s *splay_tree;
diff --git a/gnu/dist/binutils/include/xtensa-config.h b/gnu/dist/binutils/include/xtensa-config.h
index 4191c368575..4ef5d64270f 100644
--- a/gnu/dist/binutils/include/xtensa-config.h
+++ b/gnu/dist/binutils/include/xtensa-config.h
@@ -1,5 +1,5 @@
/* Xtensa configuration settings.
- Copyright (C) 2001,2002,2003 Free Software Foundation, Inc.
+ Copyright (C) 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica.
This program is free software; you can redistribute it and/or modify
@@ -42,6 +42,9 @@
#undef XCHAL_HAVE_L32R
#define XCHAL_HAVE_L32R 1
+#undef XSHAL_USE_ABSOLUTE_LITERALS
+#define XSHAL_USE_ABSOLUTE_LITERALS 0
+
#undef XCHAL_HAVE_MAC16
#define XCHAL_HAVE_MAC16 0
@@ -87,6 +90,9 @@
#undef XCHAL_HAVE_WINDOWED
#define XCHAL_HAVE_WINDOWED 1
+#undef XCHAL_HAVE_PREDICTED_BRANCHES
+#define XCHAL_HAVE_PREDICTED_BRANCHES 0
+
#undef XCHAL_ICACHE_SIZE
#define XCHAL_ICACHE_SIZE 8192
@@ -130,10 +136,7 @@
#define XCHAL_DEBUGLEVEL 4
-#undef XCHAL_EXTRA_SA_SIZE
-#define XCHAL_EXTRA_SA_SIZE 0
-
-#undef XCHAL_EXTRA_SA_ALIGN
-#define XCHAL_EXTRA_SA_ALIGN 1
+#undef XCHAL_INST_FETCH_WIDTH
+#define XCHAL_INST_FETCH_WIDTH 4
#endif /* !XTENSA_CONFIG_H */
diff --git a/gnu/dist/binutils/include/xtensa-isa-internal.h b/gnu/dist/binutils/include/xtensa-isa-internal.h
index 7f221eae48e..7ec2b9e72ae 100644
--- a/gnu/dist/binutils/include/xtensa-isa-internal.h
+++ b/gnu/dist/binutils/include/xtensa-isa-internal.h
@@ -1,5 +1,5 @@
/* Internal definitions for configurable Xtensa ISA support.
- Copyright 2003 Free Software Foundation, Inc.
+ Copyright 2003, 2004, 2005 Free Software Foundation, Inc.
This file is part of BFD, the Binary File Descriptor library.
@@ -17,98 +17,216 @@
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
-/* Use the statically-linked version for the GNU tools. */
-#define STATIC_LIBISA 1
+#ifndef XTENSA_ISA_INTERNAL_H
+#define XTENSA_ISA_INTERNAL_H
-#define ISA_INTERFACE_VERSION 3
+/* Flags. */
-struct config_struct
-{
- char *param_name;
- char *param_value;
-};
-
-/* Encode/decode function types for immediate operands. */
-typedef uint32 (*xtensa_immed_decode_fn) (uint32);
-typedef xtensa_encode_result (*xtensa_immed_encode_fn) (uint32 *);
-
-/* Field accessor function types. */
-typedef uint32 (*xtensa_get_field_fn) (const xtensa_insnbuf);
-typedef void (*xtensa_set_field_fn) (xtensa_insnbuf, uint32);
+#define XTENSA_OPERAND_IS_REGISTER 0x00000001
+#define XTENSA_OPERAND_IS_PCRELATIVE 0x00000002
+#define XTENSA_OPERAND_IS_INVISIBLE 0x00000004
+#define XTENSA_OPERAND_IS_UNKNOWN 0x00000008
-/* PC-relative relocation function types. */
-typedef uint32 (*xtensa_do_reloc_fn) (uint32, uint32);
-typedef uint32 (*xtensa_undo_reloc_fn) (uint32, uint32);
+#define XTENSA_OPCODE_IS_BRANCH 0x00000001
+#define XTENSA_OPCODE_IS_JUMP 0x00000002
+#define XTENSA_OPCODE_IS_LOOP 0x00000004
+#define XTENSA_OPCODE_IS_CALL 0x00000008
-/* Instruction decode function type. */
-typedef int (*xtensa_insn_decode_fn) (const xtensa_insnbuf);
+#define XTENSA_STATE_IS_EXPORTED 0x00000001
-/* Instruction encoding template function type (each of these functions
- returns a constant template; they exist only to make it easier for the
- TIE compiler to generate endian-independent DLLs). */
-typedef xtensa_insnbuf (*xtensa_encoding_template_fn) (void);
+#define XTENSA_INTERFACE_HAS_SIDE_EFFECT 0x00000001
+/* Function pointer typedefs */
+typedef void (*xtensa_format_encode_fn) (xtensa_insnbuf);
+typedef void (*xtensa_get_slot_fn) (const xtensa_insnbuf, xtensa_insnbuf);
+typedef void (*xtensa_set_slot_fn) (xtensa_insnbuf, const xtensa_insnbuf);
+typedef int (*xtensa_opcode_decode_fn) (const xtensa_insnbuf);
+typedef uint32 (*xtensa_get_field_fn) (const xtensa_insnbuf);
+typedef void (*xtensa_set_field_fn) (xtensa_insnbuf, uint32);
+typedef int (*xtensa_immed_decode_fn) (uint32 *);
+typedef int (*xtensa_immed_encode_fn) (uint32 *);
+typedef int (*xtensa_do_reloc_fn) (uint32 *, uint32);
+typedef int (*xtensa_undo_reloc_fn) (uint32 *, uint32);
+typedef void (*xtensa_opcode_encode_fn) (xtensa_insnbuf);
+typedef int (*xtensa_format_decode_fn) (const xtensa_insnbuf);
+typedef int (*xtensa_length_decode_fn) (const unsigned char *);
+
+typedef struct xtensa_format_internal_struct
+{
+ const char *name; /* Instruction format name. */
+ int length; /* Instruction length in bytes. */
+ xtensa_format_encode_fn encode_fn;
+ int num_slots;
+ int *slot_id; /* Array[num_slots] of slot IDs. */
+} xtensa_format_internal;
+
+typedef struct xtensa_slot_internal_struct
+{
+ const char *name; /* Not necessarily unique. */
+ const char *format;
+ int position;
+ xtensa_get_slot_fn get_fn;
+ xtensa_set_slot_fn set_fn;
+ xtensa_get_field_fn *get_field_fns; /* Array[field_id]. */
+ xtensa_set_field_fn *set_field_fns; /* Array[field_id]. */
+ xtensa_opcode_decode_fn opcode_decode_fn;
+ const char *nop_name;
+} xtensa_slot_internal;
typedef struct xtensa_operand_internal_struct
{
- char *operand_kind; /* e.g., "a", "f", "i", "l".... */
- char inout; /* '<', '>', or '='. */
- char isPCRelative; /* Is this a PC-relative offset? */
- xtensa_get_field_fn get_field; /* Get encoded value of the field. */
- xtensa_set_field_fn set_field; /* Set field with an encoded value. */
+ const char *name;
+ int field_id;
+ xtensa_regfile regfile; /* Register file. */
+ int num_regs; /* Usually 1; 2 for reg pairs, etc. */
+ uint32 flags; /* See XTENSA_OPERAND_* flags. */
xtensa_immed_encode_fn encode; /* Encode the operand value. */
xtensa_immed_decode_fn decode; /* Decode the value from the field. */
- xtensa_do_reloc_fn do_reloc; /* Perform a PC-relative relocation. */
+ xtensa_do_reloc_fn do_reloc; /* Perform a PC-relative reloc. */
xtensa_undo_reloc_fn undo_reloc; /* Undo a PC-relative relocation. */
} xtensa_operand_internal;
+typedef struct xtensa_arg_internal_struct
+{
+ union {
+ int operand_id; /* For normal operands. */
+ xtensa_state state; /* For stateOperands. */
+ } u;
+ char inout; /* Direction: 'i', 'o', or 'm'. */
+} xtensa_arg_internal;
typedef struct xtensa_iclass_internal_struct
{
int num_operands; /* Size of "operands" array. */
- xtensa_operand_internal **operands; /* Array of operand structures. */
-} xtensa_iclass_internal;
+ xtensa_arg_internal *operands; /* Array[num_operands]. */
+ int num_stateOperands; /* Size of "stateOperands" array. */
+ xtensa_arg_internal *stateOperands; /* Array[num_stateOperands]. */
+
+ int num_interfaceOperands; /* Size of "interfaceOperands". */
+ xtensa_interface *interfaceOperands; /* Array[num_interfaceOperands]. */
+} xtensa_iclass_internal;
typedef struct xtensa_opcode_internal_struct
{
const char *name; /* Opcode mnemonic. */
- int length; /* Length in bytes of the insn. */
- xtensa_encoding_template_fn template; /* Fn returning encoding template. */
- xtensa_iclass_internal *iclass; /* Iclass for this opcode. */
+ int iclass_id; /* Iclass for this opcode. */
+ uint32 flags; /* See XTENSA_OPCODE_* flags. */
+ xtensa_opcode_encode_fn *encode_fns; /* Array[slot_id]. */
+ int num_funcUnit_uses; /* Number of funcUnit_use entries. */
+ xtensa_funcUnit_use *funcUnit_uses; /* Array[num_funcUnit_uses]. */
} xtensa_opcode_internal;
+typedef struct xtensa_regfile_internal_struct
+{
+ const char *name; /* Full name of the regfile. */
+ const char *shortname; /* Abbreviated name. */
+ xtensa_regfile parent; /* View parent (or identity). */
+ int num_bits; /* Width of the registers. */
+ int num_entries; /* Number of registers. */
+} xtensa_regfile_internal;
+
+typedef struct xtensa_interface_internal_struct
+{
+ const char *name; /* Interface name. */
+ int num_bits; /* Width of the interface. */
+ uint32 flags; /* See XTENSA_INTERFACE_* flags. */
+ int class_id; /* Class of related interfaces. */
+ char inout; /* "i" or "o". */
+} xtensa_interface_internal;
+
+typedef struct xtensa_funcUnit_internal_struct
+{
+ const char *name; /* Functional unit name. */
+ int num_copies; /* Number of instances. */
+} xtensa_funcUnit_internal;
+
+typedef struct xtensa_state_internal_struct
+{
+ const char *name; /* State name. */
+ int num_bits; /* Number of state bits. */
+ uint32 flags; /* See XTENSA_STATE_* flags. */
+} xtensa_state_internal;
-typedef struct opname_lookup_entry_struct
+typedef struct xtensa_sysreg_internal_struct
{
- const char *key; /* Opcode mnemonic. */
- xtensa_opcode opcode; /* Internal opcode number. */
-} opname_lookup_entry;
+ const char *name; /* Register name. */
+ int number; /* Register number. */
+ int is_user; /* Non-zero if a "user register". */
+} xtensa_sysreg_internal;
+typedef struct xtensa_lookup_entry_struct
+{
+ const char *key;
+ union
+ {
+ xtensa_opcode opcode; /* Internal opcode number. */
+ xtensa_sysreg sysreg; /* Internal sysreg number. */
+ xtensa_state state; /* Internal state number. */
+ xtensa_interface intf; /* Internal interface number. */
+ xtensa_funcUnit fun; /* Internal funcUnit number. */
+ } u;
+} xtensa_lookup_entry;
typedef struct xtensa_isa_internal_struct
{
int is_big_endian; /* Endianness. */
int insn_size; /* Maximum length in bytes. */
int insnbuf_size; /* Number of insnbuf_words. */
- int num_opcodes; /* Total number for all modules. */
- xtensa_opcode_internal **opcode_table;/* Indexed by internal opcode #. */
- int num_modules; /* Number of modules (DLLs) loaded. */
- int *module_opcode_base; /* Starting opcode # for each module. */
- xtensa_insn_decode_fn *module_decode_fn; /* Decode fn for each module. */
- opname_lookup_entry *opname_lookup_table; /* Lookup table for each module. */
- struct config_struct *config; /* Table of configuration parameters. */
- int has_density; /* Is density option available? */
-} xtensa_isa_internal;
+ int num_formats;
+ xtensa_format_internal *formats;
+ xtensa_format_decode_fn format_decode_fn;
+ xtensa_length_decode_fn length_decode_fn;
-typedef struct xtensa_isa_module_struct
-{
- int (*get_num_opcodes_fn) (void);
- xtensa_opcode_internal **(*get_opcodes_fn) (void);
- int (*decode_insn_fn) (const xtensa_insnbuf);
- struct config_struct *(*get_config_table_fn) (void);
-} xtensa_isa_module;
+ int num_slots;
+ xtensa_slot_internal *slots;
+
+ int num_fields;
+
+ int num_operands;
+ xtensa_operand_internal *operands;
+
+ int num_iclasses;
+ xtensa_iclass_internal *iclasses;
+
+ int num_opcodes;
+ xtensa_opcode_internal *opcodes;
+ xtensa_lookup_entry *opname_lookup_table;
+
+ int num_regfiles;
+ xtensa_regfile_internal *regfiles;
+
+ int num_states;
+ xtensa_state_internal *states;
+ xtensa_lookup_entry *state_lookup_table;
+
+ int num_sysregs;
+ xtensa_sysreg_internal *sysregs;
+ xtensa_lookup_entry *sysreg_lookup_table;
+
+ /* The current Xtensa ISA only supports 256 of each kind of sysreg so
+ we can get away with implementing lookups with tables indexed by
+ the register numbers. If we ever allow larger sysreg numbers, this
+ may have to be reimplemented. The first entry in the following
+ arrays corresponds to "special" registers and the second to "user"
+ registers. */
+ int max_sysreg_num[2];
+ xtensa_sysreg *sysreg_table[2];
+
+ int num_interfaces;
+ xtensa_interface_internal *interfaces;
+ xtensa_lookup_entry *interface_lookup_table;
+
+ int num_funcUnits;
+ xtensa_funcUnit_internal *funcUnits;
+ xtensa_lookup_entry *funcUnit_lookup_table;
+
+} xtensa_isa_internal;
+
+extern int xtensa_isa_name_compare (const void *, const void *);
-extern xtensa_isa_module xtensa_isa_modules[];
+extern xtensa_isa_status xtisa_errno;
+extern char xtisa_error_msg[];
+#endif /* !XTENSA_ISA_INTERNAL_H */
diff --git a/gnu/dist/binutils/include/xtensa-isa.h b/gnu/dist/binutils/include/xtensa-isa.h
index 54f750c9a1a..043b9cdd5d2 100644
--- a/gnu/dist/binutils/include/xtensa-isa.h
+++ b/gnu/dist/binutils/include/xtensa-isa.h
@@ -1,5 +1,5 @@
/* Interface definition for configurable Xtensa ISA support.
- Copyright 2003 Free Software Foundation, Inc.
+ Copyright 2003, 2004, 2005 Free Software Foundation, Inc.
This file is part of BFD, the Binary File Descriptor library.
@@ -20,209 +20,787 @@
#ifndef XTENSA_LIBISA_H
#define XTENSA_LIBISA_H
-/* Use the statically-linked version for the GNU tools. */
-#define STATIC_LIBISA 1
-
#ifdef __cplusplus
extern "C" {
#endif
+/* Use the statically-linked version for the GNU tools. */
+#define STATIC_LIBISA 1
+
+/* Version number: This is intended to help support code that works with
+ versions of this library from multiple Xtensa releases. */
+
+#define XTENSA_ISA_VERSION 7000
+
#ifndef uint32
#define uint32 unsigned int
#endif
-/* This file defines the interface to the Xtensa ISA library. This library
- contains most of the ISA-specific information for a particular Xtensa
- processor. For example, the set of valid instructions, their opcode
- encodings and operand fields are all included here. To support Xtensa's
- configurability and user-defined instruction extensions (i.e., TIE), the
- library is initialized by loading one or more dynamic libraries; only a
- small set of interface code is present in the statically-linked portion
- of the library.
+/* This file defines the interface to the Xtensa ISA library. This
+ library contains most of the ISA-specific information for a
+ particular Xtensa processor. For example, the set of valid
+ instructions, their opcode encodings and operand fields are all
+ included here.
- This interface basically defines four abstract data types.
+ This interface basically defines a number of abstract data types.
. an instruction buffer - for holding the raw instruction bits
. ISA info - information about the ISA as a whole
- . opcode info - information about individual instructions
- . operand info - information about specific instruction operands
-
- It would be nice to implement these as classes in C++, but the library is
- implemented in C to match the expectations of the GNU tools.
- Instead, the interface defines a set of functions to access each data
- type. With the exception of the instruction buffer, the internal
- representations of the data structures are hidden. All accesses must be
- made through the functions defined here. */
-
-typedef void* xtensa_isa;
-typedef void* xtensa_operand;
+ . instruction formats - instruction size and slot structure
+ . opcodes - information about individual instructions
+ . operands - information about register and immediate instruction operands
+ . stateOperands - information about processor state instruction operands
+ . interfaceOperands - information about interface instruction operands
+ . register files - register file information
+ . processor states - internal processor state information
+ . system registers - "special registers" and "user registers"
+ . interfaces - TIE interfaces that are external to the processor
+ . functional units - TIE shared functions
+
+ The interface defines a set of functions to access each data type.
+ With the exception of the instruction buffer, the internal
+ representations of the data structures are hidden. All accesses must
+ be made through the functions defined here. */
+
+typedef struct xtensa_isa_opaque { int unused; } *xtensa_isa;
+
+
+/* Most of the Xtensa ISA entities (e.g., opcodes, regfiles, etc.) are
+ represented here using sequential integers beginning with 0. The
+ specific values are only fixed for a particular instantiation of an
+ xtensa_isa structure, so these values should only be used
+ internally. */
-
-/* Opcodes are represented here using sequential integers beginning with 0.
- The specific value used for a particular opcode is only fixed for a
- particular instantiation of an xtensa_isa structure, so these values
- should only be used internally. */
typedef int xtensa_opcode;
-
-/* Define a unique value for undefined opcodes ("static const int" doesn't
- seem to work for this because EGCS 1.0.3 on i686-Linux without -O won't
- allow it to be used as an initializer). */
-#define XTENSA_UNDEFINED -1
+typedef int xtensa_format;
+typedef int xtensa_regfile;
+typedef int xtensa_state;
+typedef int xtensa_sysreg;
+typedef int xtensa_interface;
+typedef int xtensa_funcUnit;
-typedef int libisa_module_specifier;
+/* Define a unique value for undefined items. */
-extern xtensa_isa xtensa_isa_init (void);
+#define XTENSA_UNDEFINED -1
+/* Overview of using this interface to decode/encode instructions:
+
+ Each Xtensa instruction is associated with a particular instruction
+ format, where the format defines a fixed number of slots for
+ operations. The formats for the core Xtensa ISA have only one slot,
+ but FLIX instructions may have multiple slots. Within each slot,
+ there is a single opcode and some number of associated operands.
+
+ The encoding and decoding functions operate on instruction buffers,
+ not on the raw bytes of the instructions. The same instruction
+ buffer data structure is used for both entire instructions and
+ individual slots in those instructions -- the contents of a slot need
+ to be extracted from or inserted into the buffer for the instruction
+ as a whole.
+
+ Decoding an instruction involves first finding the format, which
+ identifies the number of slots, and then decoding each slot
+ separately. A slot is decoded by finding the opcode and then using
+ the opcode to determine how many operands there are. For example:
+
+ xtensa_insnbuf_from_chars
+ xtensa_format_decode
+ for each slot {
+ xtensa_format_get_slot
+ xtensa_opcode_decode
+ for each operand {
+ xtensa_operand_get_field
+ xtensa_operand_decode
+ }
+ }
+
+ Encoding an instruction is roughly the same procedure in reverse:
+
+ xtensa_format_encode
+ for each slot {
+ xtensa_opcode_encode
+ for each operand {
+ xtensa_operand_encode
+ xtensa_operand_set_field
+ }
+ xtensa_format_set_slot
+ }
+ xtensa_insnbuf_to_chars
+*/
+
+
+/* Error handling. */
+
+/* Error codes. The code for the most recent error condition can be
+ retrieved with the "errno" function. For any result other than
+ xtensa_isa_ok, an error message containing additional information
+ about the problem can be retrieved using the "error_msg" function.
+ The error messages are stored in an internal buffer, which should not
+ should be freed and may be overwritten by subsequent operations. */
+
+typedef enum xtensa_isa_status_enum
+{
+ xtensa_isa_ok = 0,
+ xtensa_isa_bad_format,
+ xtensa_isa_bad_slot,
+ xtensa_isa_bad_opcode,
+ xtensa_isa_bad_operand,
+ xtensa_isa_bad_field,
+ xtensa_isa_bad_iclass,
+ xtensa_isa_bad_regfile,
+ xtensa_isa_bad_sysreg,
+ xtensa_isa_bad_state,
+ xtensa_isa_bad_interface,
+ xtensa_isa_bad_funcUnit,
+ xtensa_isa_wrong_slot,
+ xtensa_isa_no_field,
+ xtensa_isa_out_of_memory,
+ xtensa_isa_buffer_overflow,
+ xtensa_isa_internal_error,
+ xtensa_isa_bad_value
+} xtensa_isa_status;
+
+extern xtensa_isa_status
+xtensa_isa_errno (xtensa_isa isa);
+
+extern char *
+xtensa_isa_error_msg (xtensa_isa isa);
+
+
+
/* Instruction buffers. */
typedef uint32 xtensa_insnbuf_word;
typedef xtensa_insnbuf_word *xtensa_insnbuf;
-/* Get the size in words of the xtensa_insnbuf array. */
-extern int xtensa_insnbuf_size (xtensa_isa);
-/* Allocate (with malloc) an xtensa_insnbuf of the right size. */
-extern xtensa_insnbuf xtensa_insnbuf_alloc (xtensa_isa);
+/* Get the size in "insnbuf_words" of the xtensa_insnbuf array. */
-/* Release (with free) an xtensa_insnbuf of the right size. */
-extern void xtensa_insnbuf_free (xtensa_insnbuf);
+extern int
+xtensa_insnbuf_size (xtensa_isa isa);
-/* Inward and outward conversion from memory images (byte streams) to our
- internal instruction representation. */
-extern void xtensa_insnbuf_to_chars (xtensa_isa, const xtensa_insnbuf,
- char *);
-extern void xtensa_insnbuf_from_chars (xtensa_isa, xtensa_insnbuf,
- const char *);
+/* Allocate an xtensa_insnbuf of the right size. */
+extern xtensa_insnbuf
+xtensa_insnbuf_alloc (xtensa_isa isa);
+
+
+/* Release an xtensa_insnbuf. */
+
+extern void
+xtensa_insnbuf_free (xtensa_isa isa, xtensa_insnbuf buf);
-/* ISA information. */
-/* Load the ISA information from a shared library. If successful, this returns
- a value which identifies the ISA for use in subsequent calls to the ISA
- library; otherwise, it returns NULL. Multiple ISAs can be loaded to support
- heterogeneous multiprocessor systems. */
-extern xtensa_isa xtensa_load_isa (libisa_module_specifier);
+/* Conversion between raw memory (char arrays) and our internal
+ instruction representation. This is complicated by the Xtensa ISA's
+ variable instruction lengths. When converting to chars, the buffer
+ must contain a valid instruction so we know how many bytes to copy;
+ thus, the "to_chars" function returns the number of bytes copied or
+ XTENSA_UNDEFINED on error. The "from_chars" function first reads the
+ minimal number of bytes required to decode the instruction length and
+ then proceeds to copy the entire instruction into the buffer; if the
+ memory does not contain a valid instruction, it copies the maximum
+ number of bytes required for the longest Xtensa instruction. The
+ "num_chars" argument may be used to limit the number of bytes that
+ can be read or written. Otherwise, if "num_chars" is zero, the
+ functions may read or write past the end of the code. */
-/* Extend an existing set of ISA information by loading an additional shared
- library of ISA information. This is primarily intended for loading TIE
- extensions. If successful, the return value is non-zero. */
-extern int xtensa_extend_isa (xtensa_isa, libisa_module_specifier);
+extern int
+xtensa_insnbuf_to_chars (xtensa_isa isa, const xtensa_insnbuf insn,
+ unsigned char *cp, int num_chars);
-/* The default ISA. This variable is set automatically to the ISA most
- recently loaded and is provided as a convenience. An exception is the GNU
- opcodes library, where there is a fixed interface that does not allow
- passing the ISA as a parameter and the ISA must be taken from this global
- variable. (Note: Since this variable is just a convenience, it is not
- exported when libisa is built as a DLL, due to the hassle of dealing with
- declspecs.) */
-extern xtensa_isa xtensa_default_isa;
+extern void
+xtensa_insnbuf_from_chars (xtensa_isa isa, xtensa_insnbuf insn,
+ const unsigned char *cp, int num_chars);
+
+
+
+/* ISA information. */
+
+/* Initialize the ISA information. */
+
+extern xtensa_isa
+xtensa_isa_init (xtensa_isa_status *errno_p, char **error_msg_p);
/* Deallocate an xtensa_isa structure. */
-extern void xtensa_isa_free (xtensa_isa);
+
+extern void
+xtensa_isa_free (xtensa_isa isa);
+
/* Get the maximum instruction size in bytes. */
-extern int xtensa_insn_maxlength (xtensa_isa);
-/* Get the total number of opcodes for this processor. */
-extern int xtensa_num_opcodes (xtensa_isa);
+extern int
+xtensa_isa_maxlength (xtensa_isa isa);
+
+
+/* Decode the length in bytes of an instruction in raw memory (not an
+ insnbuf). This function reads only the minimal number of bytes
+ required to decode the instruction length. Returns
+ XTENSA_UNDEFINED on error. */
+
+extern int
+xtensa_isa_length_from_chars (xtensa_isa isa, const unsigned char *cp);
+
+
+/* Get the number of stages in the processor's pipeline. The pipeline
+ stage values returned by other functions in this library will range
+ from 0 to N-1, where N is the value returned by this function.
+ Note that the stage numbers used here may not correspond to the
+ actual processor hardware, e.g., the hardware may have additional
+ stages before stage 0. Returns XTENSA_UNDEFINED on error. */
+
+extern int
+xtensa_isa_num_pipe_stages (xtensa_isa isa);
+
+
+/* Get the number of various entities that are defined for this processor. */
+
+extern int
+xtensa_isa_num_formats (xtensa_isa isa);
+
+extern int
+xtensa_isa_num_opcodes (xtensa_isa isa);
+
+extern int
+xtensa_isa_num_regfiles (xtensa_isa isa);
+
+extern int
+xtensa_isa_num_states (xtensa_isa isa);
+
+extern int
+xtensa_isa_num_sysregs (xtensa_isa isa);
+
+extern int
+xtensa_isa_num_interfaces (xtensa_isa isa);
+
+extern int
+xtensa_isa_num_funcUnits (xtensa_isa isa);
+
+
+
+/* Instruction formats. */
+
+/* Get the name of a format. Returns null on error. */
+
+extern const char *
+xtensa_format_name (xtensa_isa isa, xtensa_format fmt);
+
+
+/* Given a format name, return the format number. Returns
+ XTENSA_UNDEFINED if the name is not a valid format. */
+
+extern xtensa_format
+xtensa_format_lookup (xtensa_isa isa, const char *fmtname);
+
+
+/* Decode the instruction format from a binary instruction buffer.
+ Returns XTENSA_UNDEFINED if the format is not recognized. */
+
+extern xtensa_format
+xtensa_format_decode (xtensa_isa isa, const xtensa_insnbuf insn);
+
+
+/* Set the instruction format field(s) in a binary instruction buffer.
+ All the other fields are set to zero. Returns non-zero on error. */
+
+extern int
+xtensa_format_encode (xtensa_isa isa, xtensa_format fmt, xtensa_insnbuf insn);
+
+
+/* Find the length (in bytes) of an instruction. Returns
+ XTENSA_UNDEFINED on error. */
+
+extern int
+xtensa_format_length (xtensa_isa isa, xtensa_format fmt);
+
+
+/* Get the number of slots in an instruction. Returns XTENSA_UNDEFINED
+ on error. */
+
+extern int
+xtensa_format_num_slots (xtensa_isa isa, xtensa_format fmt);
+
+
+/* Get the opcode for a no-op in a particular slot.
+ Returns XTENSA_UNDEFINED on error. */
+
+extern xtensa_opcode
+xtensa_format_slot_nop_opcode (xtensa_isa isa, xtensa_format fmt, int slot);
+
+
+/* Get the bits for a specified slot out of an insnbuf for the
+ instruction as a whole and put them into an insnbuf for that one
+ slot, and do the opposite to set a slot. Return non-zero on error. */
+
+extern int
+xtensa_format_get_slot (xtensa_isa isa, xtensa_format fmt, int slot,
+ const xtensa_insnbuf insn, xtensa_insnbuf slotbuf);
+
+extern int
+xtensa_format_set_slot (xtensa_isa isa, xtensa_format fmt, int slot,
+ xtensa_insnbuf insn, const xtensa_insnbuf slotbuf);
+
+
+
+/* Opcode information. */
/* Translate a mnemonic name to an opcode. Returns XTENSA_UNDEFINED if
the name is not a valid opcode mnemonic. */
-extern xtensa_opcode xtensa_opcode_lookup (xtensa_isa, const char *);
-/* Decode a binary instruction buffer. Returns the opcode or
- XTENSA_UNDEFINED if the instruction is illegal. */
-extern xtensa_opcode xtensa_decode_insn (xtensa_isa, const xtensa_insnbuf);
+extern xtensa_opcode
+xtensa_opcode_lookup (xtensa_isa isa, const char *opname);
-/* Opcode information. */
+/* Decode the opcode for one instruction slot from a binary instruction
+ buffer. Returns the opcode or XTENSA_UNDEFINED if the opcode is
+ illegal. */
+
+extern xtensa_opcode
+xtensa_opcode_decode (xtensa_isa isa, xtensa_format fmt, int slot,
+ const xtensa_insnbuf slotbuf);
+
+
+/* Set the opcode field(s) for an instruction slot. All other fields
+ in the slot are set to zero. Returns non-zero if the opcode cannot
+ be encoded. */
+
+extern int
+xtensa_opcode_encode (xtensa_isa isa, xtensa_format fmt, int slot,
+ xtensa_insnbuf slotbuf, xtensa_opcode opc);
-/* Set the opcode field(s) in a binary instruction buffer. The operand
- fields are set to zero. */
-extern void xtensa_encode_insn (xtensa_isa, xtensa_opcode, xtensa_insnbuf);
-/* Get the mnemonic name for an opcode. */
-extern const char * xtensa_opcode_name (xtensa_isa, xtensa_opcode);
+/* Get the mnemonic name for an opcode. Returns null on error. */
-/* Find the length (in bytes) of an instruction. */
-extern int xtensa_insn_length (xtensa_isa, xtensa_opcode);
+extern const char *
+xtensa_opcode_name (xtensa_isa isa, xtensa_opcode opc);
-/* Find the length of an instruction by looking only at the first byte. */
-extern int xtensa_insn_length_from_first_byte (xtensa_isa, char);
-/* Find the number of operands for an instruction. */
-extern int xtensa_num_operands (xtensa_isa, xtensa_opcode);
+/* Check various properties of opcodes. These functions return 0 if
+ the condition is false, 1 if the condition is true, and
+ XTENSA_UNDEFINED on error. The instructions are classified as
+ follows:
-/* Get the information about operand number "opnd" of a particular opcode. */
-extern xtensa_operand xtensa_get_operand (xtensa_isa, xtensa_opcode, int);
+ branch: conditional branch; may fall through to next instruction (B*)
+ jump: unconditional branch (J, JX, RET*, RF*)
+ loop: zero-overhead loop (LOOP*)
+ call: unconditional call; control returns to next instruction (CALL*)
+ For the opcodes that affect control flow in some way, the branch
+ target may be specified by an immediate operand or it may be an
+ address stored in a register. You can distinguish these by
+ checking if the instruction has a PC-relative immediate
+ operand. */
+
+extern int
+xtensa_opcode_is_branch (xtensa_isa isa, xtensa_opcode opc);
+
+extern int
+xtensa_opcode_is_jump (xtensa_isa isa, xtensa_opcode opc);
+
+extern int
+xtensa_opcode_is_loop (xtensa_isa isa, xtensa_opcode opc);
+
+extern int
+xtensa_opcode_is_call (xtensa_isa isa, xtensa_opcode opc);
+
+
+/* Find the number of ordinary operands, state operands, and interface
+ operands for an instruction. These return XTENSA_UNDEFINED on
+ error. */
+
+extern int
+xtensa_opcode_num_operands (xtensa_isa isa, xtensa_opcode opc);
+
+extern int
+xtensa_opcode_num_stateOperands (xtensa_isa isa, xtensa_opcode opc);
+
+extern int
+xtensa_opcode_num_interfaceOperands (xtensa_isa isa, xtensa_opcode opc);
+
+
+/* Get functional unit usage requirements for an opcode. Each "use"
+ is identified by a <functional unit, pipeline stage> pair. The
+ "num_funcUnit_uses" function returns the number of these "uses" or
+ XTENSA_UNDEFINED on error. The "funcUnit_use" function returns
+ a pointer to a "use" pair or null on error. */
+
+typedef struct xtensa_funcUnit_use_struct
+{
+ xtensa_funcUnit unit;
+ int stage;
+} xtensa_funcUnit_use;
+
+extern int
+xtensa_opcode_num_funcUnit_uses (xtensa_isa isa, xtensa_opcode opc);
+
+extern xtensa_funcUnit_use *
+xtensa_opcode_funcUnit_use (xtensa_isa isa, xtensa_opcode opc, int u);
+
+
+
/* Operand information. */
-/* Find the kind of operand. There are three possibilities:
- 1) PC-relative immediates (e.g., "l", "L"). These can be identified with
- the xtensa_operand_isPCRelative function.
- 2) non-PC-relative immediates ("i").
- 3) register-file short names (e.g., "a", "b", "m" and others defined
- via TIE). */
-extern char * xtensa_operand_kind (xtensa_operand);
+/* Get the name of an operand. Returns null on error. */
+
+extern const char *
+xtensa_operand_name (xtensa_isa isa, xtensa_opcode opc, int opnd);
-/* Check if an operand is an input ('<'), output ('>'), or inout ('=')
+
+/* Some operands are "invisible", i.e., not explicitly specified in
+ assembly language. When assembling an instruction, you need not set
+ the values of invisible operands, since they are either hardwired or
+ derived from other field values. The values of invisible operands
+ can be examined in the same way as other operands, but remember that
+ an invisible operand may get its value from another visible one, so
+ the entire instruction must be available before examining the
+ invisible operand values. This function returns 1 if an operand is
+ visible, 0 if it is invisible, or XTENSA_UNDEFINED on error. Note
+ that whether an operand is visible is orthogonal to whether it is
+ "implicit", i.e., whether it is encoded in a field in the
+ instruction. */
+
+extern int
+xtensa_operand_is_visible (xtensa_isa isa, xtensa_opcode opc, int opnd);
+
+
+/* Check if an operand is an input ('i'), output ('o'), or inout ('m')
operand. Note: The output operand of a conditional assignment
- (e.g., movnez) appears here as an inout ('=') even if it is declared
- in the TIE code as an output ('>'); this allows the compiler to
- properly handle register allocation for conditional assignments. */
-extern char xtensa_operand_inout (xtensa_operand);
+ (e.g., movnez) appears here as an inout ('m') even if it is declared
+ in the TIE code as an output ('o'); this allows the compiler to
+ properly handle register allocation for conditional assignments.
+ Returns 0 on error. */
+
+extern char
+xtensa_operand_inout (xtensa_isa isa, xtensa_opcode opc, int opnd);
+
/* Get and set the raw (encoded) value of the field for the specified
operand. The "set" function does not check if the value fits in the
- field; that is done by the "encode" function below. */
-extern uint32 xtensa_operand_get_field (xtensa_operand, const xtensa_insnbuf);
+ field; that is done by the "encode" function below. Both of these
+ functions return non-zero on error, e.g., if the field is not defined
+ for the specified slot. */
+
+extern int
+xtensa_operand_get_field (xtensa_isa isa, xtensa_opcode opc, int opnd,
+ xtensa_format fmt, int slot,
+ const xtensa_insnbuf slotbuf, uint32 *valp);
-extern void xtensa_operand_set_field (xtensa_operand, xtensa_insnbuf, uint32);
+extern int
+xtensa_operand_set_field (xtensa_isa isa, xtensa_opcode opc, int opnd,
+ xtensa_format fmt, int slot,
+ xtensa_insnbuf slotbuf, uint32 val);
-/* Encode and decode operands. The raw bits in the operand field
- may be encoded in a variety of different ways. These functions hide the
- details of that encoding. The encode function has a special return type
- (xtensa_encode_result) to indicate success or the reason for failure; the
- encoded value is returned through the argument pointer. The decode function
- has no possibility of failure and returns the decoded value. */
+/* Encode and decode operands. The raw bits in the operand field may
+ be encoded in a variety of different ways. These functions hide
+ the details of that encoding. The result values are returned through
+ the argument pointer. The return value is non-zero on error. */
-typedef enum
-{
- xtensa_encode_result_ok,
- xtensa_encode_result_align,
- xtensa_encode_result_not_in_table,
- xtensa_encode_result_too_low,
- xtensa_encode_result_too_high,
- xtensa_encode_result_not_ok,
- xtensa_encode_result_max = xtensa_encode_result_not_ok
-} xtensa_encode_result;
+extern int
+xtensa_operand_encode (xtensa_isa isa, xtensa_opcode opc, int opnd,
+ uint32 *valp);
+
+extern int
+xtensa_operand_decode (xtensa_isa isa, xtensa_opcode opc, int opnd,
+ uint32 *valp);
+
+
+/* An operand may be either a register operand or an immediate of some
+ sort (e.g., PC-relative or not). The "is_register" function returns
+ 0 if the operand is an immediate, 1 if it is a register, and
+ XTENSA_UNDEFINED on error. The "regfile" function returns the
+ regfile for a register operand, or XTENSA_UNDEFINED on error. */
+
+extern int
+xtensa_operand_is_register (xtensa_isa isa, xtensa_opcode opc, int opnd);
+
+extern xtensa_regfile
+xtensa_operand_regfile (xtensa_isa isa, xtensa_opcode opc, int opnd);
+
+
+/* Register operands may span multiple consecutive registers, e.g., a
+ 64-bit data type may occupy two 32-bit registers. Only the first
+ register is encoded in the operand field. This function specifies
+ the number of consecutive registers occupied by this operand. For
+ non-register operands, the return value is undefined. Returns
+ XTENSA_UNDEFINED on error. */
+
+extern int
+xtensa_operand_num_regs (xtensa_isa isa, xtensa_opcode opc, int opnd);
+
+
+/* Some register operands do not completely identify the register being
+ accessed. For example, the operand value may be added to an internal
+ state value. By definition, this implies that the corresponding
+ regfile is not allocatable. Unknown registers should generally be
+ treated with worst-case assumptions. The function returns 0 if the
+ register value is unknown, 1 if known, and XTENSA_UNDEFINED on
+ error. */
+
+extern int
+xtensa_operand_is_known_reg (xtensa_isa isa, xtensa_opcode opc, int opnd);
+
+
+/* Check if an immediate operand is PC-relative. Returns 0 for register
+ operands and non-PC-relative immediates, 1 for PC-relative
+ immediates, and XTENSA_UNDEFINED on error. */
+
+extern int
+xtensa_operand_is_PCrelative (xtensa_isa isa, xtensa_opcode opc, int opnd);
+
+
+/* For PC-relative offset operands, the interpretation of the offset may
+ vary between opcodes, e.g., is it relative to the current PC or that
+ of the next instruction? The following functions are defined to
+ perform PC-relative relocations and to undo them (as in the
+ disassembler). The "do_reloc" function takes the desired address
+ value and the PC of the current instruction and sets the value to the
+ corresponding PC-relative offset (which can then be encoded and
+ stored into the operand field). The "undo_reloc" function takes the
+ unencoded offset value and the current PC and sets the value to the
+ appropriate address. The return values are non-zero on error. Note
+ that these functions do not replace the encode/decode functions; the
+ operands must be encoded/decoded separately and the encode functions
+ are responsible for detecting invalid operand values. */
+
+extern int
+xtensa_operand_do_reloc (xtensa_isa isa, xtensa_opcode opc, int opnd,
+ uint32 *valp, uint32 pc);
+
+extern int
+xtensa_operand_undo_reloc (xtensa_isa isa, xtensa_opcode opc, int opnd,
+ uint32 *valp, uint32 pc);
+
+
+
+/* State Operands. */
+
+/* Get the state accessed by a state operand. Returns XTENSA_UNDEFINED
+ on error. */
+
+extern xtensa_state
+xtensa_stateOperand_state (xtensa_isa isa, xtensa_opcode opc, int stOp);
+
+
+/* Check if a state operand is an input ('i'), output ('o'), or inout
+ ('m') operand. Returns 0 on error. */
+
+extern char
+xtensa_stateOperand_inout (xtensa_isa isa, xtensa_opcode opc, int stOp);
+
+
+
+/* Interface Operands. */
+
+/* Get the external interface accessed by an interface operand.
+ Returns XTENSA_UNDEFINED on error. */
+
+extern xtensa_interface
+xtensa_interfaceOperand_interface (xtensa_isa isa, xtensa_opcode opc,
+ int ifOp);
+
+
+
+/* Register Files. */
+
+/* Regfiles include both "real" regfiles and "views", where a view
+ allows a group of adjacent registers in a real "parent" regfile to be
+ viewed as a single register. A regfile view has all the same
+ properties as its parent except for its (long) name, bit width, number
+ of entries, and default ctype. You can use the parent function to
+ distinguish these two classes. */
+
+/* Look up a regfile by either its name or its abbreviated "short name".
+ Returns XTENSA_UNDEFINED on error. The "lookup_shortname" function
+ ignores "view" regfiles since they always have the same shortname as
+ their parents. */
+
+extern xtensa_regfile
+xtensa_regfile_lookup (xtensa_isa isa, const char *name);
+
+extern xtensa_regfile
+xtensa_regfile_lookup_shortname (xtensa_isa isa, const char *shortname);
+
+
+/* Get the name or abbreviated "short name" of a regfile.
+ Returns null on error. */
+
+extern const char *
+xtensa_regfile_name (xtensa_isa isa, xtensa_regfile rf);
+
+extern const char *
+xtensa_regfile_shortname (xtensa_isa isa, xtensa_regfile rf);
+
+
+/* Get the parent regfile of a "view" regfile. If the regfile is not a
+ view, the result is the same as the input parameter. Returns
+ XTENSA_UNDEFINED on error. */
+
+extern xtensa_regfile
+xtensa_regfile_view_parent (xtensa_isa isa, xtensa_regfile rf);
+
+
+/* Get the bit width of a regfile or regfile view.
+ Returns XTENSA_UNDEFINED on error. */
+
+extern int
+xtensa_regfile_num_bits (xtensa_isa isa, xtensa_regfile rf);
+
+
+/* Get the number of regfile entries. Returns XTENSA_UNDEFINED on
+ error. */
+
+extern int
+xtensa_regfile_num_entries (xtensa_isa isa, xtensa_regfile rf);
+
+
+
+/* Processor States. */
+
+/* Look up a state by name. Returns XTENSA_UNDEFINED on error. */
+
+extern xtensa_state
+xtensa_state_lookup (xtensa_isa isa, const char *name);
+
+
+/* Get the name for a processor state. Returns null on error. */
+
+extern const char *
+xtensa_state_name (xtensa_isa isa, xtensa_state st);
+
+
+/* Get the bit width for a processor state.
+ Returns XTENSA_UNDEFINED on error. */
+
+extern int
+xtensa_state_num_bits (xtensa_isa isa, xtensa_state st);
+
+
+/* Check if a state is exported from the processor core. Returns 0 if
+ the condition is false, 1 if the condition is true, and
+ XTENSA_UNDEFINED on error. */
+
+extern int
+xtensa_state_is_exported (xtensa_isa isa, xtensa_state st);
+
+
+
+/* Sysregs ("special registers" and "user registers"). */
+
+/* Look up a register by its number and whether it is a "user register"
+ or a "special register". Returns XTENSA_UNDEFINED if the sysreg does
+ not exist. */
+
+extern xtensa_sysreg
+xtensa_sysreg_lookup (xtensa_isa isa, int num, int is_user);
+
+
+/* Check if there exists a sysreg with a given name.
+ If not, this function returns XTENSA_UNDEFINED. */
+
+extern xtensa_sysreg
+xtensa_sysreg_lookup_name (xtensa_isa isa, const char *name);
+
+
+/* Get the name of a sysreg. Returns null on error. */
+
+extern const char *
+xtensa_sysreg_name (xtensa_isa isa, xtensa_sysreg sysreg);
+
+
+/* Get the register number. Returns XTENSA_UNDEFINED on error. */
+
+extern int
+xtensa_sysreg_number (xtensa_isa isa, xtensa_sysreg sysreg);
+
+
+/* Check if a sysreg is a "special register" or a "user register".
+ Returns 0 for special registers, 1 for user registers and
+ XTENSA_UNDEFINED on error. */
+
+extern int
+xtensa_sysreg_is_user (xtensa_isa isa, xtensa_sysreg sysreg);
+
+
+
+/* Interfaces. */
+
+/* Find an interface by name. The return value is XTENSA_UNDEFINED if
+ the specified interface is not found. */
+
+extern xtensa_interface
+xtensa_interface_lookup (xtensa_isa isa, const char *ifname);
+
+
+/* Get the name of an interface. Returns null on error. */
+
+extern const char *
+xtensa_interface_name (xtensa_isa isa, xtensa_interface intf);
+
+
+/* Get the bit width for an interface.
+ Returns XTENSA_UNDEFINED on error. */
+
+extern int
+xtensa_interface_num_bits (xtensa_isa isa, xtensa_interface intf);
+
+
+/* Check if an interface is an input ('i') or output ('o') with respect
+ to the Xtensa processor core. Returns 0 on error. */
+
+extern char
+xtensa_interface_inout (xtensa_isa isa, xtensa_interface intf);
+
+
+/* Check if accessing an interface has potential side effects.
+ Currently "data" interfaces have side effects and "control"
+ interfaces do not. Returns 1 if there are side effects, 0 if not,
+ and XTENSA_UNDEFINED on error. */
+
+extern int
+xtensa_interface_has_side_effect (xtensa_isa isa, xtensa_interface intf);
+
+
+/* Some interfaces may be related such that accessing one interface
+ has side effects on a set of related interfaces. The interfaces
+ are partitioned into equivalence classes of related interfaces, and
+ each class is assigned a unique identifier number. This function
+ returns the class identifier for an interface, or XTENSA_UNDEFINED
+ on error. These identifiers can be compared to determine if two
+ interfaces are related; the specific values of the identifiers have
+ no particular meaning otherwise. */
+
+extern int
+xtensa_interface_class_id (xtensa_isa isa, xtensa_interface intf);
+
+
+
+/* Functional Units. */
+
+/* Find a functional unit by name. The return value is XTENSA_UNDEFINED if
+ the specified unit is not found. */
+
+extern xtensa_funcUnit
+xtensa_funcUnit_lookup (xtensa_isa isa, const char *fname);
-extern xtensa_encode_result xtensa_operand_encode (xtensa_operand, uint32 *);
-extern uint32 xtensa_operand_decode (xtensa_operand, uint32);
+/* Get the name of a functional unit. Returns null on error. */
+extern const char *
+xtensa_funcUnit_name (xtensa_isa isa, xtensa_funcUnit fun);
-/* For PC-relative offset operands, the interpretation of the offset may vary
- between opcodes, e.g., is it relative to the current PC or that of the next
- instruction? The following functions are defined to perform PC-relative
- relocations and to undo them (as in the disassembler). The first function
- takes the desired address and the PC of the current instruction and returns
- the unencoded value to be stored in the offset field. The second function
- takes the unencoded offset value and the current PC and returns the address.
- Note that these functions do not replace the encode/decode functions; the
- operands must be encoded/decoded separately. */
-extern int xtensa_operand_isPCRelative (xtensa_operand);
+/* Functional units may be replicated. See how many instances of a
+ particular function unit exist. Returns XTENSA_UNDEFINED on error. */
-extern uint32 xtensa_operand_do_reloc (xtensa_operand, uint32, uint32);
+extern int
+xtensa_funcUnit_num_copies (xtensa_isa isa, xtensa_funcUnit fun);
-extern uint32 xtensa_operand_undo_reloc (xtensa_operand, uint32, uint32);
#ifdef __cplusplus
}