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authorchristos <christos@NetBSD.org>2013-03-30 02:53:00 +0000
committerchristos <christos@NetBSD.org>2013-03-30 02:53:00 +0000
commite480ee86d302e9e66f483136d059e823d5bb9880 (patch)
tree23dd43b5009ad333e4975c36de9cdd672e47df80 /sys/dev
parent294b62c5052a547fee06a8f2dbb59d23620819f4 (diff)
This is the initial port of OpenBSD's athn(4) driver. It supports
quite a few Atheros 802.11n devices. See the athn(4) manpage for a list. This port has only been tested with a TP-LINK TL-WN722N USB adapter which has an AR9271 chipset (VENDOR: 0x0cf3, PRODUCT: 0x9271). The BSS, Monitor, and HostAP modes all seem to work on that adapter, though the later has not been tested much. The driver also supports PCI and CardBUS devices, but those interfaces are completely untested and probably won't work at this point. If someone can provide me with other adapters that should be supported, particularly PCI or CardBUS adapters, or tell me where I can get one cheaply, I would be happy to try to get the driver working on those devices as well.
Diffstat (limited to 'sys/dev')
-rw-r--r--sys/dev/cardbus/if_athn_cardbus.c366
-rw-r--r--sys/dev/ic/arn5008.c2780
-rw-r--r--sys/dev/ic/arn5008.h45
-rw-r--r--sys/dev/ic/arn5008reg.h1028
-rw-r--r--sys/dev/ic/arn5416.c963
-rw-r--r--sys/dev/ic/arn5416.h44
-rw-r--r--sys/dev/ic/arn5416reg.h852
-rw-r--r--sys/dev/ic/arn9003.c3447
-rw-r--r--sys/dev/ic/arn9003.h42
-rw-r--r--sys/dev/ic/arn9003reg.h1205
-rw-r--r--sys/dev/ic/arn9280.c627
-rw-r--r--sys/dev/ic/arn9280.h42
-rw-r--r--sys/dev/ic/arn9280reg.h630
-rw-r--r--sys/dev/ic/arn9285.c887
-rw-r--r--sys/dev/ic/arn9285.h38
-rw-r--r--sys/dev/ic/arn9285reg.h1093
-rw-r--r--sys/dev/ic/arn9287.c628
-rw-r--r--sys/dev/ic/arn9287.h35
-rw-r--r--sys/dev/ic/arn9287reg.h539
-rw-r--r--sys/dev/ic/arn9380.c917
-rw-r--r--sys/dev/ic/arn9380.h33
-rw-r--r--sys/dev/ic/arn9380reg.h1926
-rw-r--r--sys/dev/ic/athn.c2969
-rw-r--r--sys/dev/ic/athnreg.h1489
-rw-r--r--sys/dev/ic/athnvar.h674
-rw-r--r--sys/dev/pci/if_athn_pci.c339
-rw-r--r--sys/dev/usb/if_athn_usb.c2815
-rw-r--r--sys/dev/usb/if_athn_usb.h493
28 files changed, 26946 insertions, 0 deletions
diff --git a/sys/dev/cardbus/if_athn_cardbus.c b/sys/dev/cardbus/if_athn_cardbus.c
new file mode 100644
index 00000000000..be4f145aa5a
--- /dev/null
+++ b/sys/dev/cardbus/if_athn_cardbus.c
@@ -0,0 +1,366 @@
+/* $NetBSD: if_athn_cardbus.c,v 1.1 2013/03/30 02:53:00 christos Exp $ */
+/* $OpenBSD: if_athn_cardbus.c,v 1.13 2011/01/08 10:02:32 damien Exp $ */
+
+/*-
+ * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr>
+ *
+ * Permission to use, copy, modify, and distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+/*
+ * CardBus front-end for Atheros 802.11a/g/n chipsets.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: if_athn_cardbus.c,v 1.1 2013/03/30 02:53:00 christos Exp $");
+
+#include "opt_inet.h"
+
+#include <sys/param.h>
+#include <sys/sockio.h>
+#include <sys/mbuf.h>
+#include <sys/kernel.h>
+#include <sys/socket.h>
+#include <sys/systm.h>
+#include <sys/malloc.h>
+#include <sys/callout.h>
+#include <sys/device.h>
+
+#include <sys/bus.h>
+#include <sys/intr.h>
+
+#include <net/if.h>
+#include <net/if_media.h>
+
+#include <net80211/ieee80211_var.h>
+#include <net80211/ieee80211_amrr.h>
+#include <net80211/ieee80211_radiotap.h>
+
+#include <dev/ic/athnreg.h>
+#include <dev/ic/athnvar.h>
+
+#include <dev/pci/pcireg.h>
+#include <dev/pci/pcivar.h>
+#include <dev/pci/pcidevs.h>
+
+#include <dev/cardbus/cardbusvar.h>
+
+/*
+ * PCI configuration space registers
+ */
+#define ATHN_PCI_MMBA PCI_BAR(0) /* memory mapped base */
+
+struct athn_cardbus_softc {
+ struct athn_softc csc_sc;
+
+ /* CardBus specific goo. */
+ cardbus_devfunc_t csc_ct;
+ pcitag_t csc_tag;
+ void *csc_ih;
+ bus_space_tag_t csc_iot;
+ bus_space_handle_t csc_ioh;
+ bus_size_t csc_mapsz;
+ pcireg_t csc_bar_val;
+};
+
+#define Static static
+
+Static int athn_cardbus_match(device_t, cfdata_t, void *);
+Static void athn_cardbus_attach(device_t, device_t, void *);
+Static int athn_cardbus_detach(device_t, int);
+
+CFATTACH_DECL_NEW(athn_cardbus, sizeof(struct athn_cardbus_softc),
+ athn_cardbus_match, athn_cardbus_attach, athn_cardbus_detach, NULL);
+
+Static uint32_t athn_cardbus_read(struct athn_softc *, uint32_t);
+Static bool athn_cardbus_resume(device_t, const pmf_qual_t *l);
+Static void athn_cardbus_setup(struct athn_cardbus_softc *);
+Static bool athn_cardbus_suspend(device_t, const pmf_qual_t *);
+Static void athn_cardbus_write(struct athn_softc *, uint32_t, uint32_t);
+Static void athn_cardbus_write_barrier(struct athn_softc *);
+
+#ifdef openbsd_power_management
+Static int athn_cardbus_enable(struct athn_softc *);
+Static void athn_cardbus_disable(struct athn_softc *);
+Static void athn_cardbus_power(struct athn_softc *, int);
+#endif /* openbsd_power_management */
+
+Static int
+athn_cardbus_match(device_t parent, cfdata_t match, void *aux)
+{
+ static const struct {
+ pci_vendor_id_t vendor;
+ pci_product_id_t product;
+ } athn_cardbus_devices[] = {
+ { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5416 },
+ { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5418 },
+ { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR9160 },
+ { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR9280 },
+ { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR9281 },
+ { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR9285 },
+ { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR2427 },
+ { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR9227 },
+ { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR9287 },
+ { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR9300 }
+ };
+ struct cardbus_attach_args *ca = aux;
+ size_t i;
+
+ for (i = 0; i < __arraycount(athn_cardbus_devices); i++) {
+ if (PCI_VENDOR(ca->ca_id) == athn_cardbus_devices[i].vendor &&
+ PCI_VENDOR(ca->ca_id) == athn_cardbus_devices[i].product)
+ return 1;
+ }
+ return 0;
+}
+
+Static void
+athn_cardbus_attach(device_t parent, device_t self, void *aux)
+{
+ struct athn_cardbus_softc *csc = device_private(self);
+ struct athn_softc *sc = &csc->csc_sc;
+ struct ieee80211com *ic = &sc->sc_ic;
+ struct cardbus_attach_args *ca = aux;
+ cardbus_devfunc_t ct = ca->ca_ct;
+ bus_addr_t base;
+ int error;
+
+ sc->sc_dmat = ca->ca_dmat;
+ csc->csc_ct = ct;
+ csc->csc_tag = ca->ca_tag;
+
+ aprint_normal("\n");
+ aprint_naive("\n");
+
+#ifdef openbsd_power_management
+ /* Power management hooks. */
+ sc->sc_enable = athn_cardbus_enable;
+ sc->sc_disable = athn_cardbus_disable;
+ sc->sc_power = athn_cardbus_power;
+#endif
+ sc->sc_ops.read = athn_cardbus_read;
+ sc->sc_ops.write = athn_cardbus_write;
+ sc->sc_ops.write_barrier = athn_cardbus_write_barrier;
+
+ /*
+ * Map control/status registers.
+ */
+ error = Cardbus_mapreg_map(ct, ATHN_PCI_MMBA, PCI_MAPREG_TYPE_MEM, 0,
+ &csc->csc_iot, &csc->csc_ioh, &base, &csc->csc_mapsz);
+ if (error != 0) {
+ aprint_error_dev(self, "unable to map device (%d)\n", error);
+ return;
+ }
+ csc->csc_bar_val = base | PCI_MAPREG_TYPE_MEM;
+
+ /*
+ * Set up the PCI configuration registers.
+ */
+ athn_cardbus_setup(csc);
+
+ if (athn_attach(sc) != 0) {
+ Cardbus_mapreg_unmap(ct, ATHN_PCI_MMBA, csc->csc_iot,
+ csc->csc_ioh, csc->csc_mapsz);
+ return;
+ }
+
+ if (pmf_device_register(self,
+ athn_cardbus_suspend, athn_cardbus_resume)) {
+ pmf_class_network_register(self, &sc->sc_if);
+ pmf_device_suspend(self, &sc->sc_qual);
+ } else
+ aprint_error_dev(self, "couldn't establish power handler\n");
+
+// Cardbus_function_disable(ct);
+
+ ieee80211_announce(ic);
+}
+
+Static int
+athn_cardbus_detach(device_t self, int flags)
+{
+ struct athn_cardbus_softc *csc = device_private(self);
+ struct athn_softc *sc = &csc->csc_sc;
+ cardbus_devfunc_t ct = csc->csc_ct;
+ cardbus_chipset_tag_t cc = ct->ct_cc;
+ cardbus_function_tag_t cf = ct->ct_cf;
+
+ athn_detach(sc);
+
+ pmf_device_deregister(self);
+
+ /* Unhook the interrupt handler. */
+ if (csc->csc_ih != NULL)
+ cardbus_intr_disestablish(cc, cf, csc->csc_ih);
+
+ /* Release bus space and close window. */
+ Cardbus_mapreg_unmap(ct, ATHN_PCI_MMBA, csc->csc_iot, csc->csc_ioh,
+ csc->csc_mapsz);
+
+ return 0;
+}
+
+Static void
+athn_cardbus_setup(struct athn_cardbus_softc *csc)
+{
+ cardbus_devfunc_t ct = csc->csc_ct;
+#ifdef unneeded /* XXX */
+ pci_chipset_tag_t pc = csc->csc_pc;
+ cardbus_chipset_tag_t cc = ct->ct_cc;
+ cardbus_function_tag_t cf = ct->ct_cf;
+#endif
+ pcireg_t reg;
+ int rc;
+
+ if ((rc = cardbus_set_powerstate(ct, csc->csc_tag, PCI_PWR_D0)) != 0)
+ aprint_debug("%s: cardbus_set_powerstate %d\n", __func__, rc);
+
+ /* Program the BAR. */
+ Cardbus_conf_write(ct, csc->csc_tag, ATHN_PCI_MMBA, csc->csc_bar_val);
+
+#ifdef unneeded /* XXX */
+ /* Make sure the right access type is on the cardbus bridge. */
+ (*cf->cardbus_ctrl)(cc, CARDBUS_MEM_ENABLE);
+ (*cf->cardbus_ctrl)(cc, CARDBUS_BM_ENABLE);
+#endif
+ /* Enable the appropriate bits in the PCI CSR. */
+ reg = Cardbus_conf_read(ct, csc->csc_tag, PCI_COMMAND_STATUS_REG);
+ reg |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_MEM_ENABLE;
+ Cardbus_conf_write(ct, csc->csc_tag, PCI_COMMAND_STATUS_REG, reg);
+
+ /*
+ * Noone knows why this shit is necessary but there are claims that
+ * not doing this may cause very frequent PCI FATAL interrupts from
+ * the card: http://bugzilla.kernel.org/show_bug.cgi?id=13483
+ */
+ reg = Cardbus_conf_read(ct, csc->csc_tag, 0x40);
+ if (reg & 0xff00)
+ Cardbus_conf_write(ct, csc->csc_tag, 0x40, reg & ~0xff00);
+
+ /* Change latency timer; default value yields poor results. */
+ reg = Cardbus_conf_read(ct, csc->csc_tag, PCI_BHLC_REG);
+ reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT);
+ reg |= 168 << PCI_LATTIMER_SHIFT;
+ Cardbus_conf_write(ct, csc->csc_tag, PCI_BHLC_REG, reg);
+}
+
+Static uint32_t
+athn_cardbus_read(struct athn_softc *sc, uint32_t addr)
+{
+ struct athn_cardbus_softc *csc = (struct athn_cardbus_softc *)sc;
+
+ return bus_space_read_4(csc->csc_iot, csc->csc_ioh, addr);
+}
+
+Static void
+athn_cardbus_write(struct athn_softc *sc, uint32_t addr, uint32_t val)
+{
+ struct athn_cardbus_softc *csc = (struct athn_cardbus_softc *)sc;
+
+ bus_space_write_4(csc->csc_iot, csc->csc_ioh, addr, val);
+}
+
+Static void
+athn_cardbus_write_barrier(struct athn_softc *sc)
+{
+ struct athn_cardbus_softc *csc = (struct athn_cardbus_softc *)sc;
+
+ bus_space_barrier(csc->csc_iot, csc->csc_ioh, 0, csc->csc_mapsz,
+ BUS_SPACE_BARRIER_WRITE);
+}
+
+Static bool
+athn_cardbus_suspend(device_t self, const pmf_qual_t *qual)
+{
+ struct athn_cardbus_softc *csc = device_private(self);
+
+ athn_suspend(&csc->csc_sc);
+ if (csc->csc_ih != NULL) {
+ Cardbus_intr_disestablish(csc->csc_ct, csc->csc_ih);
+ csc->csc_ih = NULL;
+ }
+ return true;
+}
+
+Static bool
+athn_cardbus_resume(device_t self, const pmf_qual_t *qual)
+{
+ struct athn_cardbus_softc *csc = device_private(self);
+
+ csc->csc_ih = Cardbus_intr_establish(csc->csc_ct, IPL_NET, athn_intr,
+ &csc->csc_sc);
+
+ if (csc->csc_ih == NULL) {
+ aprint_error_dev(self,
+ "unable to establish interrupt\n");
+ return false;
+ }
+ return athn_resume(&csc->csc_sc);
+}
+
+/************************************************************************
+ * XXX: presumably the pmf_* stuff handles this.
+ */
+#ifdef openbsd_power_management
+Static int
+athn_cardbus_enable(struct athn_softc *sc)
+{
+ struct athn_cardbus_softc *csc = (struct athn_cardbus_softc *)sc;
+ cardbus_devfunc_t ct = csc->csc_ct;
+ cardbus_chipset_tag_t cc = ct->ct_cc;
+ cardbus_function_tag_t cf = ct->ct_cf;
+
+ /* Power on the socket. */
+ Cardbus_function_enable(ct);
+
+ /* Setup the PCI configuration registers. */
+ athn_cardbus_setup(csc);
+
+ /* Map and establish the interrupt handler. */
+ csc->csc_ih = cardbus_intr_establish(cc, cf, IPL_NET, athn_intr, sc);
+ if (csc->csc_ih == NULL) {
+ printf("%s: could not establish interrupt at %d\n",
+ device_xname(sc->sc_dev), csc->csc_intrline);
+ Cardbus_function_disable(ct);
+ return 1;
+ }
+ return 0;
+}
+
+Static void
+athn_cardbus_disable(struct athn_softc *sc)
+{
+ struct athn_cardbus_softc *csc = (struct athn_cardbus_softc *)sc;
+ cardbus_devfunc_t ct = csc->csc_ct;
+ cardbus_chipset_tag_t cc = ct->ct_cc;
+ cardbus_function_tag_t cf = ct->ct_cf;
+
+ /* Unhook the interrupt handler. */
+ cardbus_intr_disestablish(cc, cf, csc->csc_ih);
+ csc->csc_ih = NULL;
+
+ /* Power down the socket. */
+ Cardbus_function_disable(ct);
+}
+
+Static void
+athn_cardbus_power(struct athn_softc *sc, int why)
+{
+ struct athn_cardbus_softc *csc = (struct athn_cardbus_softc *)sc;
+
+ if (why == DVACT_RESUME) {
+ /* Restore the PCI configuration registers. */
+ athn_cardbus_setup(csc);
+ }
+}
+#endif /* openbsd_power_management */
diff --git a/sys/dev/ic/arn5008.c b/sys/dev/ic/arn5008.c
new file mode 100644
index 00000000000..725f9128edc
--- /dev/null
+++ b/sys/dev/ic/arn5008.c
@@ -0,0 +1,2780 @@
+/* $NetBSD: arn5008.c,v 1.1 2013/03/30 02:53:00 christos Exp $ */
+/* $OpenBSD: ar5008.c,v 1.21 2012/08/25 12:14:31 kettenis Exp $ */
+
+/*-
+ * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr>
+ * Copyright (c) 2008-2009 Atheros Communications Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+/*
+ * Driver for Atheros 802.11a/g/n chipsets.
+ * Routines common to AR5008, AR9001 and AR9002 families.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: arn5008.c,v 1.1 2013/03/30 02:53:00 christos Exp $");
+
+#include <sys/param.h>
+#include <sys/sockio.h>
+#include <sys/mbuf.h>
+#include <sys/kernel.h>
+#include <sys/socket.h>
+#include <sys/systm.h>
+#include <sys/malloc.h>
+#include <sys/queue.h>
+#include <sys/conf.h>
+#include <sys/device.h>
+
+#include <sys/bus.h>
+#include <sys/endian.h>
+#include <sys/intr.h>
+
+#include <net/bpf.h>
+#include <net/if.h>
+#include <net/if_arp.h>
+#include <net/if_dl.h>
+#include <net/if_media.h>
+#include <net/if_types.h>
+
+#include <netinet/in.h>
+#include <netinet/in_systm.h>
+#include <netinet/in_var.h>
+#include <netinet/ip.h>
+
+#include <net80211/ieee80211_var.h>
+#include <net80211/ieee80211_amrr.h>
+#include <net80211/ieee80211_radiotap.h>
+
+#include <dev/ic/athnreg.h>
+#include <dev/ic/athnvar.h>
+
+#include <dev/ic/arn5008reg.h>
+#include <dev/ic/arn5008.h>
+#include <dev/ic/arn5416.h>
+#include <dev/ic/arn9280.h>
+
+#define Static static
+
+Static void ar5008_calib_adc_dc_off(struct athn_softc *);
+Static void ar5008_calib_adc_gain(struct athn_softc *);
+Static void ar5008_calib_iq(struct athn_softc *);
+Static void ar5008_disable_ofdm_weak_signal(struct athn_softc *);
+Static void ar5008_disable_phy(struct athn_softc *);
+Static int ar5008_dma_alloc(struct athn_softc *);
+Static void ar5008_dma_free(struct athn_softc *);
+Static void ar5008_do_calib(struct athn_softc *);
+Static void ar5008_do_noisefloor_calib(struct athn_softc *);
+Static void ar5008_enable_antenna_diversity(struct athn_softc *);
+Static void ar5008_enable_ofdm_weak_signal(struct athn_softc *);
+Static uint8_t ar5008_get_vpd(uint8_t, const uint8_t *, const uint8_t *, int);
+Static void ar5008_gpio_config_input(struct athn_softc *, int);
+Static void ar5008_gpio_config_output(struct athn_softc *, int, int);
+Static int ar5008_gpio_read(struct athn_softc *, int);
+Static void ar5008_gpio_write(struct athn_softc *, int, int);
+Static void ar5008_hw_init(struct athn_softc *, struct ieee80211_channel *,
+ struct ieee80211_channel *);
+Static void ar5008_init_baseband(struct athn_softc *);
+Static void ar5008_init_chains(struct athn_softc *);
+Static int ar5008_intr(struct athn_softc *);
+Static void ar5008_next_calib(struct athn_softc *);
+Static int ar5008_read_eep_word(struct athn_softc *, uint32_t,
+ uint16_t *);
+Static int ar5008_read_rom(struct athn_softc *);
+Static void ar5008_rf_bus_release(struct athn_softc *);
+Static int ar5008_rf_bus_request(struct athn_softc *);
+Static void ar5008_rfsilent_init(struct athn_softc *);
+Static int ar5008_rx_alloc(struct athn_softc *);
+Static void ar5008_rx_enable(struct athn_softc *);
+Static void ar5008_rx_free(struct athn_softc *);
+Static void ar5008_rx_intr(struct athn_softc *);
+Static void ar5008_rx_radiotap(struct athn_softc *, struct mbuf *,
+ struct ar_rx_desc *);
+Static void ar5008_set_cck_weak_signal(struct athn_softc *, int);
+Static void ar5008_set_delta_slope(struct athn_softc *,
+ struct ieee80211_channel *, struct ieee80211_channel *);
+Static void ar5008_set_firstep_level(struct athn_softc *, int);
+Static void ar5008_set_noise_immunity_level(struct athn_softc *, int);
+Static void ar5008_set_phy(struct athn_softc *, struct ieee80211_channel *,
+ struct ieee80211_channel *);
+Static void ar5008_set_rf_mode(struct athn_softc *,
+ struct ieee80211_channel *);
+Static void ar5008_set_rxchains(struct athn_softc *);
+Static void ar5008_set_spur_immunity_level(struct athn_softc *, int);
+Static void ar5008_swap_rom(struct athn_softc *);
+Static int ar5008_swba_intr(struct athn_softc *);
+Static int ar5008_tx(struct athn_softc *, struct mbuf *,
+ struct ieee80211_node *, int);
+Static int ar5008_tx_alloc(struct athn_softc *);
+Static void ar5008_tx_free(struct athn_softc *);
+Static void ar5008_tx_intr(struct athn_softc *);
+Static int ar5008_tx_process(struct athn_softc *, int);
+
+#ifdef notused
+Static void ar5008_bb_load_noisefloor(struct athn_softc *);
+Static void ar5008_get_noisefloor(struct athn_softc *,
+ struct ieee80211_channel *);
+Static void ar5008_noisefloor_calib(struct athn_softc *);
+Static void ar5008_read_noisefloor(struct athn_softc *, int16_t *,
+ int16_t *);
+Static void ar5008_write_noisefloor(struct athn_softc *, int16_t *,
+ int16_t *);
+#endif /* notused */
+
+// bf->bf_m = MCLGETI(NULL, M_DONTWAIT, NULL, ATHN_RXBUFSZ);
+
+/*
+ * XXX: see if_iwn.c:MCLGETIalt() for a better solution.
+ */
+static struct mbuf *
+MCLGETI(struct athn_softc *sc __unused, int how,
+ struct ifnet *ifp __unused, u_int size)
+{
+ struct mbuf *m;
+
+ MGETHDR(m, how, MT_DATA);
+ if (m == NULL)
+ return NULL;
+
+ MEXTMALLOC(m, size, how);
+ if ((m->m_flags & M_EXT) == 0) {
+ m_freem(m);
+ return NULL;
+ }
+ return m;
+}
+
+PUBLIC int
+ar5008_attach(struct athn_softc *sc)
+{
+ struct athn_ops *ops = &sc->sc_ops;
+ struct ieee80211com *ic = &sc->sc_ic;
+ struct ar_base_eep_header *base;
+ uint8_t eep_ver, kc_entries_log;
+ int error;
+
+ /* Set callbacks for AR5008, AR9001 and AR9002 families. */
+ ops->gpio_read = ar5008_gpio_read;
+ ops->gpio_write = ar5008_gpio_write;
+ ops->gpio_config_input = ar5008_gpio_config_input;
+ ops->gpio_config_output = ar5008_gpio_config_output;
+ ops->rfsilent_init = ar5008_rfsilent_init;
+
+ ops->dma_alloc = ar5008_dma_alloc;
+ ops->dma_free = ar5008_dma_free;
+ ops->rx_enable = ar5008_rx_enable;
+ ops->intr = ar5008_intr;
+ ops->tx = ar5008_tx;
+
+ ops->set_rf_mode = ar5008_set_rf_mode;
+ ops->rf_bus_request = ar5008_rf_bus_request;
+ ops->rf_bus_release = ar5008_rf_bus_release;
+ ops->set_phy = ar5008_set_phy;
+ ops->set_delta_slope = ar5008_set_delta_slope;
+ ops->enable_antenna_diversity = ar5008_enable_antenna_diversity;
+ ops->init_baseband = ar5008_init_baseband;
+ ops->disable_phy = ar5008_disable_phy;
+ ops->set_rxchains = ar5008_set_rxchains;
+ ops->noisefloor_calib = ar5008_do_noisefloor_calib;
+ ops->do_calib = ar5008_do_calib;
+ ops->next_calib = ar5008_next_calib;
+ ops->hw_init = ar5008_hw_init;
+
+ ops->set_noise_immunity_level = ar5008_set_noise_immunity_level;
+ ops->enable_ofdm_weak_signal = ar5008_enable_ofdm_weak_signal;
+ ops->disable_ofdm_weak_signal = ar5008_disable_ofdm_weak_signal;
+ ops->set_cck_weak_signal = ar5008_set_cck_weak_signal;
+ ops->set_firstep_level = ar5008_set_firstep_level;
+ ops->set_spur_immunity_level = ar5008_set_spur_immunity_level;
+
+ /* Set MAC registers offsets. */
+ sc->sc_obs_off = AR_OBS;
+ sc->sc_gpio_input_en_off = AR_GPIO_INPUT_EN_VAL;
+
+ if (!(sc->sc_flags & ATHN_FLAG_PCIE))
+ athn_config_nonpcie(sc);
+ else
+ athn_config_pcie(sc);
+
+ /* Read entire ROM content in memory. */
+ if ((error = ar5008_read_rom(sc)) != 0) {
+ printf("%s: could not read ROM\n", device_xname(sc->sc_dev));
+ return error;
+ }
+
+ /* Get RF revision. */
+ sc->sc_rf_rev = ar5416_get_rf_rev(sc);
+
+ base = sc->sc_eep;
+ eep_ver = (base->version >> 12) & 0xf;
+ sc->sc_eep_rev = (base->version & 0xfff);
+ if (eep_ver != AR_EEP_VER || sc->sc_eep_rev == 0) {
+ printf("%s: unsupported ROM version %d.%d\n",
+ device_xname(sc->sc_dev), eep_ver, sc->sc_eep_rev);
+ return EINVAL;
+ }
+
+ if (base->opCapFlags & AR_OPFLAGS_11A)
+ sc->sc_flags |= ATHN_FLAG_11A;
+ if (base->opCapFlags & AR_OPFLAGS_11G)
+ sc->sc_flags |= ATHN_FLAG_11G;
+ if (base->opCapFlags & AR_OPFLAGS_11N)
+ sc->sc_flags |= ATHN_FLAG_11N;
+
+ IEEE80211_ADDR_COPY(ic->ic_myaddr, base->macAddr);
+
+ /* Check if we have a hardware radio switch. */
+ if (base->rfSilent & AR_EEP_RFSILENT_ENABLED) {
+ sc->sc_flags |= ATHN_FLAG_RFSILENT;
+ /* Get GPIO pin used by hardware radio switch. */
+ sc->sc_rfsilent_pin = MS(base->rfSilent,
+ AR_EEP_RFSILENT_GPIO_SEL);
+ /* Get polarity of hardware radio switch. */
+ if (base->rfSilent & AR_EEP_RFSILENT_POLARITY)
+ sc->sc_flags |= ATHN_FLAG_RFSILENT_REVERSED;
+ }
+
+ /* Get the number of HW key cache entries. */
+ kc_entries_log = MS(base->deviceCap, AR_EEP_DEVCAP_KC_ENTRIES);
+ sc->sc_kc_entries = kc_entries_log != 0 ?
+ 1 << kc_entries_log : AR_KEYTABLE_SIZE;
+
+ sc->sc_txchainmask = base->txMask;
+ if (sc->sc_mac_ver == AR_SREV_VERSION_5416_PCI &&
+ !(base->opCapFlags & AR_OPFLAGS_11A)) {
+ /* For single-band AR5416 PCI, use GPIO pin 0. */
+ sc->sc_rxchainmask = ar5008_gpio_read(sc, 0) ? 0x5 : 0x7;
+ }
+ else
+ sc->sc_rxchainmask = base->rxMask;
+
+ ops->setup(sc);
+ return 0;
+}
+
+/*
+ * Read 16-bit word from ROM.
+ */
+Static int
+ar5008_read_eep_word(struct athn_softc *sc, uint32_t addr, uint16_t *val)
+{
+ uint32_t reg;
+ int ntries;
+
+ reg = AR_READ(sc, AR_EEPROM_OFFSET(addr));
+ for (ntries = 0; ntries < 1000; ntries++) {
+ reg = AR_READ(sc, AR_EEPROM_STATUS_DATA);
+ if (!(reg & (AR_EEPROM_STATUS_DATA_BUSY |
+ AR_EEPROM_STATUS_DATA_PROT_ACCESS))) {
+ *val = MS(reg, AR_EEPROM_STATUS_DATA_VAL);
+ return 0;
+ }
+ DELAY(10);
+ }
+ *val = 0xffff;
+ return ETIMEDOUT;
+}
+
+Static int
+ar5008_read_rom(struct athn_softc *sc)
+{
+ uint32_t addr, end;
+ uint16_t magic, sum, *eep;
+ int need_swap = 0;
+ int error;
+
+ /* Determine ROM endianness. */
+ error = ar5008_read_eep_word(sc, AR_EEPROM_MAGIC_OFFSET, &magic);
+ if (error != 0)
+ return error;
+ if (magic != AR_EEPROM_MAGIC) {
+ if (magic != bswap16(AR_EEPROM_MAGIC)) {
+ DPRINTFN(DBG_INIT, sc,
+ "invalid ROM magic 0x%x != 0x%x\n",
+ magic, AR_EEPROM_MAGIC);
+ return EIO;
+ }
+ DPRINTFN(DBG_INIT, sc, "non-native ROM endianness\n");
+ need_swap = 1;
+ }
+
+ /* Allocate space to store ROM in host memory. */
+ sc->sc_eep = malloc(sc->sc_eep_size, M_DEVBUF, M_NOWAIT);
+ if (sc->sc_eep == NULL)
+ return ENOMEM;
+
+ /* Read entire ROM and compute checksum. */
+ sum = 0;
+ eep = sc->sc_eep;
+ end = sc->sc_eep_base + sc->sc_eep_size / sizeof(uint16_t);
+ for (addr = sc->sc_eep_base; addr < end; addr++, eep++) {
+ if ((error = ar5008_read_eep_word(sc, addr, eep)) != 0) {
+ DPRINTFN(DBG_INIT, sc,
+ "could not read ROM at 0x%x\n", addr);
+ return error;
+ }
+ if (need_swap)
+ *eep = bswap16(*eep);
+ sum ^= *eep;
+ }
+ if (sum != 0xffff) {
+ printf("%s: bad ROM checksum 0x%04x\n",
+ device_xname(sc->sc_dev), sum);
+ return EIO;
+ }
+ if (need_swap)
+ ar5008_swap_rom(sc);
+
+ return 0;
+}
+
+Static void
+ar5008_swap_rom(struct athn_softc *sc)
+{
+ struct ar_base_eep_header *base = sc->sc_eep;
+
+ /* Swap common fields first. */
+ base->length = bswap16(base->length);
+ base->version = bswap16(base->version);
+ base->regDmn[0] = bswap16(base->regDmn[0]);
+ base->regDmn[1] = bswap16(base->regDmn[1]);
+ base->rfSilent = bswap16(base->rfSilent);
+ base->blueToothOptions = bswap16(base->blueToothOptions);
+ base->deviceCap = bswap16(base->deviceCap);
+
+ /* Swap device-dependent fields. */
+ sc->sc_ops.swap_rom(sc);
+}
+
+/*
+ * Access to General Purpose Input/Output ports.
+ */
+Static int
+ar5008_gpio_read(struct athn_softc *sc, int pin)
+{
+
+ KASSERT(pin < sc->sc_ngpiopins);
+ if ((sc->sc_flags & ATHN_FLAG_USB) && !AR_SREV_9271(sc))
+ return !((AR_READ(sc, AR7010_GPIO_IN) >> pin) & 1);
+ return (AR_READ(sc, AR_GPIO_IN_OUT) >> (sc->sc_ngpiopins + pin)) & 1;
+}
+
+Static void
+ar5008_gpio_write(struct athn_softc *sc, int pin, int set)
+{
+ uint32_t reg;
+
+ KASSERT(pin < sc->sc_ngpiopins);
+
+ if (sc->sc_flags & ATHN_FLAG_USB)
+ set = !set; /* AR9271/AR7010 is reversed. */
+
+ if ((sc->sc_flags & ATHN_FLAG_USB) && !AR_SREV_9271(sc)) {
+ /* Special case for AR7010. */
+ reg = AR_READ(sc, AR7010_GPIO_OUT);
+ if (set)
+ reg |= 1 << pin;
+ else
+ reg &= ~(1 << pin);
+ AR_WRITE(sc, AR7010_GPIO_OUT, reg);
+ }
+ else {
+ reg = AR_READ(sc, AR_GPIO_IN_OUT);
+ if (set)
+ reg |= 1 << pin;
+ else
+ reg &= ~(1 << pin);
+ AR_WRITE(sc, AR_GPIO_IN_OUT, reg);
+ }
+ AR_WRITE_BARRIER(sc);
+}
+
+Static void
+ar5008_gpio_config_input(struct athn_softc *sc, int pin)
+{
+ uint32_t reg;
+
+ if ((sc->sc_flags & ATHN_FLAG_USB) && !AR_SREV_9271(sc)) {
+ /* Special case for AR7010. */
+ AR_SETBITS(sc, AR7010_GPIO_OE, 1 << pin);
+ }
+ else {
+ reg = AR_READ(sc, AR_GPIO_OE_OUT);
+ reg &= ~(AR_GPIO_OE_OUT_DRV_M << (pin * 2));
+ reg |= AR_GPIO_OE_OUT_DRV_NO << (pin * 2);
+ AR_WRITE(sc, AR_GPIO_OE_OUT, reg);
+ }
+ AR_WRITE_BARRIER(sc);
+}
+
+Static void
+ar5008_gpio_config_output(struct athn_softc *sc, int pin, int type)
+{
+ uint32_t reg;
+ int mux, off;
+
+ if ((sc->sc_flags & ATHN_FLAG_USB) && !AR_SREV_9271(sc)) {
+ /* Special case for AR7010. */
+ AR_CLRBITS(sc, AR7010_GPIO_OE, 1 << pin);
+ AR_WRITE_BARRIER(sc);
+ return;
+ }
+ mux = pin / 6;
+ off = pin % 6;
+
+ reg = AR_READ(sc, AR_GPIO_OUTPUT_MUX(mux));
+ if (!AR_SREV_9280_20_OR_LATER(sc) && mux == 0)
+ reg = (reg & ~0x1f0) | (reg & 0x1f0) << 1;
+ reg &= ~(0x1f << (off * 5));
+ reg |= (type & 0x1f) << (off * 5);
+ AR_WRITE(sc, AR_GPIO_OUTPUT_MUX(mux), reg);
+
+ reg = AR_READ(sc, AR_GPIO_OE_OUT);
+ reg &= ~(AR_GPIO_OE_OUT_DRV_M << (pin * 2));
+ reg |= AR_GPIO_OE_OUT_DRV_ALL << (pin * 2);
+ AR_WRITE(sc, AR_GPIO_OE_OUT, reg);
+ AR_WRITE_BARRIER(sc);
+}
+
+Static void
+ar5008_rfsilent_init(struct athn_softc *sc)
+{
+ uint32_t reg;
+
+ /* Configure hardware radio switch. */
+ AR_SETBITS(sc, AR_GPIO_INPUT_EN_VAL, AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
+ reg = AR_READ(sc, AR_GPIO_INPUT_MUX2);
+ reg = RW(reg, AR_GPIO_INPUT_MUX2_RFSILENT, 0);
+ AR_WRITE(sc, AR_GPIO_INPUT_MUX2, reg);
+ ar5008_gpio_config_input(sc, sc->sc_rfsilent_pin);
+ AR_SETBITS(sc, AR_PHY_TEST, AR_PHY_TEST_RFSILENT_BB);
+ if (!(sc->sc_flags & ATHN_FLAG_RFSILENT_REVERSED)) {
+ AR_SETBITS(sc, AR_GPIO_INTR_POL,
+ AR_GPIO_INTR_POL_PIN(sc->sc_rfsilent_pin));
+ }
+ AR_WRITE_BARRIER(sc);
+}
+
+Static int
+ar5008_dma_alloc(struct athn_softc *sc)
+{
+ int error;
+
+ error = ar5008_tx_alloc(sc);
+ if (error != 0)
+ return error;
+
+ error = ar5008_rx_alloc(sc);
+ if (error != 0)
+ return error;
+
+ return 0;
+}
+
+Static void
+ar5008_dma_free(struct athn_softc *sc)
+{
+
+ ar5008_tx_free(sc);
+ ar5008_rx_free(sc);
+}
+
+Static int
+ar5008_tx_alloc(struct athn_softc *sc)
+{
+ struct athn_tx_buf *bf;
+ bus_size_t size;
+ int error, nsegs, i;
+
+ /*
+ * Allocate a pool of Tx descriptors shared between all Tx queues.
+ */
+ size = ATHN_NTXBUFS * AR5008_MAX_SCATTER * sizeof(struct ar_tx_desc);
+
+ error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0,
+ BUS_DMA_NOWAIT, &sc->sc_map);
+ if (error != 0)
+ goto fail;
+
+ error = bus_dmamem_alloc(sc->sc_dmat, size, 4, 0, &sc->sc_seg, 1,
+// XXX &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO);
+ &nsegs, BUS_DMA_NOWAIT);
+ if (error != 0)
+ goto fail;
+
+ error = bus_dmamem_map(sc->sc_dmat, &sc->sc_seg, 1, size,
+ (void **)&sc->sc_descs, BUS_DMA_NOWAIT | BUS_DMA_COHERENT);
+ if (error != 0)
+ goto fail;
+
+ error = bus_dmamap_load_raw(sc->sc_dmat, sc->sc_map, &sc->sc_seg, 1, size,
+ BUS_DMA_NOWAIT);
+ if (error != 0)
+ goto fail;
+
+ SIMPLEQ_INIT(&sc->sc_txbufs);
+ for (i = 0; i < ATHN_NTXBUFS; i++) {
+ bf = &sc->sc_txpool[i];
+
+ error = bus_dmamap_create(sc->sc_dmat, ATHN_TXBUFSZ,
+ AR5008_MAX_SCATTER, ATHN_TXBUFSZ, 0, BUS_DMA_NOWAIT,
+ &bf->bf_map);
+ if (error != 0) {
+ printf("%s: could not create Tx buf DMA map\n",
+ device_xname(sc->sc_dev));
+ goto fail;
+ }
+
+ bf->bf_descs =
+ &((struct ar_tx_desc *)sc->sc_descs)[i * AR5008_MAX_SCATTER];
+ bf->bf_daddr = sc->sc_map->dm_segs[0].ds_addr +
+ i * AR5008_MAX_SCATTER * sizeof(struct ar_tx_desc);
+
+ SIMPLEQ_INSERT_TAIL(&sc->sc_txbufs, bf, bf_list);
+ }
+ return 0;
+ fail:
+ ar5008_tx_free(sc);
+ return error;
+}
+
+Static void
+ar5008_tx_free(struct athn_softc *sc)
+{
+ struct athn_tx_buf *bf;
+ int i;
+
+ for (i = 0; i < ATHN_NTXBUFS; i++) {
+ bf = &sc->sc_txpool[i];
+
+ if (bf->bf_map != NULL)
+ bus_dmamap_destroy(sc->sc_dmat, bf->bf_map);
+ }
+ /* Free Tx descriptors. */
+ if (sc->sc_map != NULL) {
+ if (sc->sc_descs != NULL) {
+ bus_dmamap_unload(sc->sc_dmat, sc->sc_map);
+ bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_descs,
+ ATHN_NTXBUFS * AR5008_MAX_SCATTER *
+ sizeof(struct ar_tx_desc));
+ bus_dmamem_free(sc->sc_dmat, &sc->sc_seg, 1);
+ }
+ bus_dmamap_destroy(sc->sc_dmat, sc->sc_map);
+ }
+}
+
+Static int
+ar5008_rx_alloc(struct athn_softc *sc)
+{
+ struct athn_rxq *rxq = &sc->sc_rxq[0];
+ struct athn_rx_buf *bf;
+ struct ar_rx_desc *ds;
+ bus_size_t size;
+ int error, nsegs, i;
+
+ rxq->bf = malloc(ATHN_NRXBUFS * sizeof(*bf), M_DEVBUF,
+ M_NOWAIT | M_ZERO);
+ if (rxq->bf == NULL)
+ return ENOMEM;
+
+ size = ATHN_NRXBUFS * sizeof(struct ar_rx_desc);
+
+ error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0,
+ BUS_DMA_NOWAIT, &rxq->map);
+ if (error != 0)
+ goto fail;
+
+ error = bus_dmamem_alloc(sc->sc_dmat, size, 0, 0, &rxq->seg, 1,
+// &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO);
+ &nsegs, BUS_DMA_NOWAIT);
+ if (error != 0)
+ goto fail;
+
+ error = bus_dmamem_map(sc->sc_dmat, &rxq->seg, 1, size,
+ (void **)&rxq->descs, BUS_DMA_NOWAIT | BUS_DMA_COHERENT);
+ if (error != 0)
+ goto fail;
+
+ error = bus_dmamap_load_raw(sc->sc_dmat, rxq->map, &rxq->seg, 1,
+ size, BUS_DMA_NOWAIT);
+ if (error != 0)
+ goto fail;
+
+ for (i = 0; i < ATHN_NRXBUFS; i++) {
+ bf = &rxq->bf[i];
+ ds = &((struct ar_rx_desc *)rxq->descs)[i];
+
+ error = bus_dmamap_create(sc->sc_dmat, ATHN_RXBUFSZ, 1,
+ ATHN_RXBUFSZ, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW,
+ &bf->bf_map);
+ if (error != 0) {
+ printf("%s: could not create Rx buf DMA map\n",
+ device_xname(sc->sc_dev));
+ goto fail;
+ }
+ /*
+ * Assumes MCLGETI returns cache-line-size aligned buffers.
+ * XXX: does ours?
+ */
+ bf->bf_m = MCLGETI(NULL, M_DONTWAIT, NULL, ATHN_RXBUFSZ);
+ if (bf->bf_m == NULL) {
+ printf("%s: could not allocate Rx mbuf\n",
+ device_xname(sc->sc_dev));
+ error = ENOBUFS;
+ goto fail;
+ }
+
+ error = bus_dmamap_load(sc->sc_dmat, bf->bf_map,
+ mtod(bf->bf_m, void *), ATHN_RXBUFSZ, NULL,
+ BUS_DMA_NOWAIT | BUS_DMA_READ);
+ if (error != 0) {
+ printf("%s: could not DMA map Rx buffer\n",
+ device_xname(sc->sc_dev));
+ goto fail;
+ }
+
+ bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, ATHN_RXBUFSZ,
+ BUS_DMASYNC_PREREAD);
+
+ bf->bf_desc = ds;
+ bf->bf_daddr = rxq->map->dm_segs[0].ds_addr +
+ i * sizeof(struct ar_rx_desc);
+ }
+ return 0;
+ fail:
+ ar5008_rx_free(sc);
+ return error;
+}
+
+Static void
+ar5008_rx_free(struct athn_softc *sc)
+{
+ struct athn_rxq *rxq = &sc->sc_rxq[0];
+ struct athn_rx_buf *bf;
+ int i;
+
+ if (rxq->bf == NULL)
+ return;
+ for (i = 0; i < ATHN_NRXBUFS; i++) {
+ bf = &rxq->bf[i];
+
+ if (bf->bf_map != NULL)
+ bus_dmamap_destroy(sc->sc_dmat, bf->bf_map);
+ if (bf->bf_m != NULL)
+ m_freem(bf->bf_m);
+ }
+ free(rxq->bf, M_DEVBUF);
+
+ /* Free Rx descriptors. */
+ if (rxq->map != NULL) {
+ if (rxq->descs != NULL) {
+ bus_dmamap_unload(sc->sc_dmat, rxq->map);
+ bus_dmamem_unmap(sc->sc_dmat, (void *)rxq->descs,
+ ATHN_NRXBUFS * sizeof(struct ar_rx_desc));
+ bus_dmamem_free(sc->sc_dmat, &rxq->seg, 1);
+ }
+ bus_dmamap_destroy(sc->sc_dmat, rxq->map);
+ }
+}
+
+Static void
+ar5008_rx_enable(struct athn_softc *sc)
+{
+ struct athn_rxq *rxq = &sc->sc_rxq[0];
+ struct athn_rx_buf *bf;
+ struct ar_rx_desc *ds;
+ int i;
+
+ /* Setup and link Rx descriptors. */
+ SIMPLEQ_INIT(&rxq->head);
+ rxq->lastds = NULL;
+ for (i = 0; i < ATHN_NRXBUFS; i++) {
+ bf = &rxq->bf[i];
+ ds = bf->bf_desc;
+
+ memset(ds, 0, sizeof(*ds));
+ ds->ds_data = bf->bf_map->dm_segs[0].ds_addr;
+ ds->ds_ctl1 = SM(AR_RXC1_BUF_LEN, ATHN_RXBUFSZ);
+
+ if (rxq->lastds != NULL) {
+ ((struct ar_rx_desc *)rxq->lastds)->ds_link =
+ bf->bf_daddr;
+ }
+ SIMPLEQ_INSERT_TAIL(&rxq->head, bf, bf_list);
+ rxq->lastds = ds;
+ }
+ bus_dmamap_sync(sc->sc_dmat, rxq->map, 0, rxq->map->dm_mapsize,
+ BUS_DMASYNC_PREREAD);
+
+ /* Enable Rx. */
+ AR_WRITE(sc, AR_RXDP, SIMPLEQ_FIRST(&rxq->head)->bf_daddr);
+ AR_WRITE(sc, AR_CR, AR_CR_RXE);
+ AR_WRITE_BARRIER(sc);
+}
+
+Static void
+ar5008_rx_radiotap(struct athn_softc *sc, struct mbuf *m,
+ struct ar_rx_desc *ds)
+{
+ struct athn_rx_radiotap_header *tap = &sc->sc_rxtap;
+ struct ieee80211com *ic = &sc->sc_ic;
+ uint64_t tsf;
+ uint32_t tstamp;
+ uint8_t rate;
+
+ /* Extend the 15-bit timestamp from Rx descriptor to 64-bit TSF. */
+ tstamp = ds->ds_status2;
+ tsf = AR_READ(sc, AR_TSF_U32);
+ tsf = tsf << 32 | AR_READ(sc, AR_TSF_L32);
+ if ((tsf & 0x7fff) < tstamp)
+ tsf -= 0x8000;
+ tsf = (tsf & ~0x7fff) | tstamp;
+
+ tap->wr_flags = IEEE80211_RADIOTAP_F_FCS;
+ tap->wr_tsft = htole64(tsf);
+ tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq);
+ tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags);
+ tap->wr_dbm_antsignal = MS(ds->ds_status4, AR_RXS4_RSSI_COMBINED);
+ /* XXX noise. */
+ tap->wr_antenna = MS(ds->ds_status3, AR_RXS3_ANTENNA);
+ tap->wr_rate = 0; /* In case it can't be found below. */
+ if (AR_SREV_5416_20_OR_LATER(sc))
+ rate = MS(ds->ds_status0, AR_RXS0_RATE);
+ else
+ rate = MS(ds->ds_status3, AR_RXS3_RATE);
+ if (rate & 0x80) { /* HT. */
+ /* Bit 7 set means HT MCS instead of rate. */
+ tap->wr_rate = rate;
+ if (!(ds->ds_status3 & AR_RXS3_GI))
+ tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTGI;
+
+ }
+ else if (rate & 0x10) { /* CCK. */
+ if (rate & 0x04)
+ tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
+ switch (rate & ~0x14) {
+ case 0xb: tap->wr_rate = 2; break;
+ case 0xa: tap->wr_rate = 4; break;
+ case 0x9: tap->wr_rate = 11; break;
+ case 0x8: tap->wr_rate = 22; break;
+ }
+ }
+ else { /* OFDM. */
+ switch (rate) {
+ case 0xb: tap->wr_rate = 12; break;
+ case 0xf: tap->wr_rate = 18; break;
+ case 0xa: tap->wr_rate = 24; break;
+ case 0xe: tap->wr_rate = 36; break;
+ case 0x9: tap->wr_rate = 48; break;
+ case 0xd: tap->wr_rate = 72; break;
+ case 0x8: tap->wr_rate = 96; break;
+ case 0xc: tap->wr_rate = 108; break;
+ }
+ }
+ bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m);
+}
+
+static __inline int
+ar5008_rx_process(struct athn_softc *sc)
+{
+ struct ieee80211com *ic = &sc->sc_ic;
+ struct ifnet *ifp = &sc->sc_if;
+ struct athn_rxq *rxq = &sc->sc_rxq[0];
+ struct athn_rx_buf *bf, *nbf;
+ struct ar_rx_desc *ds;
+ struct ieee80211_frame *wh;
+ struct ieee80211_node *ni;
+ struct mbuf *m, *m1;
+ u_int32_t rstamp;
+ int error, len, rssi;
+
+ bf = SIMPLEQ_FIRST(&rxq->head);
+ if (__predict_false(bf == NULL)) { /* Should not happen. */
+ printf("%s: Rx queue is empty!\n", device_xname(sc->sc_dev));
+ return ENOENT;
+ }
+ ds = bf->bf_desc;
+
+ if (!(ds->ds_status8 & AR_RXS8_DONE)) {
+ /*
+ * On some parts, the status words can get corrupted
+ * (including the "done" bit), so we check the next
+ * descriptor "done" bit. If it is set, it is a good
+ * indication that the status words are corrupted, so
+ * we skip this descriptor and drop the frame.
+ */
+ nbf = SIMPLEQ_NEXT(bf, bf_list);
+ if (nbf != NULL &&
+ (((struct ar_rx_desc *)nbf->bf_desc)->ds_status8 &
+ AR_RXS8_DONE)) {
+ DPRINTFN(DBG_RX, sc,
+ "corrupted descriptor status=0x%x\n",
+ ds->ds_status8);
+ /* HW will not "move" RXDP in this case, so do it. */
+ AR_WRITE(sc, AR_RXDP, nbf->bf_daddr);
+ AR_WRITE_BARRIER(sc);
+ ifp->if_ierrors++;
+ goto skip;
+ }
+ return EBUSY;
+ }
+
+ if (__predict_false(ds->ds_status1 & AR_RXS1_MORE)) {
+ /* Drop frames that span multiple Rx descriptors. */
+ DPRINTFN(DBG_RX, sc, "dropping split frame\n");
+ ifp->if_ierrors++;
+ goto skip;
+ }
+ if (!(ds->ds_status8 & AR_RXS8_FRAME_OK)) {
+ if (ds->ds_status8 & AR_RXS8_CRC_ERR)
+ DPRINTFN(DBG_RX, sc, "CRC error\n");
+ else if (ds->ds_status8 & AR_RXS8_PHY_ERR)
+ DPRINTFN(DBG_RX, sc, "PHY error=0x%x\n",
+ MS(ds->ds_status8, AR_RXS8_PHY_ERR_CODE));
+ else if (ds->ds_status8 & AR_RXS8_DECRYPT_CRC_ERR)
+ DPRINTFN(DBG_RX, sc, "Decryption CRC error\n");
+ else if (ds->ds_status8 & AR_RXS8_MICHAEL_ERR) {
+ DPRINTFN(DBG_RX, sc, "Michael MIC failure\n");
+
+ len = MS(ds->ds_status1, AR_RXS1_DATA_LEN);
+ m = bf->bf_m;
+ m->m_pkthdr.rcvif = ifp;
+ m->m_pkthdr.len = m->m_len = len;
+ wh = mtod(m, struct ieee80211_frame *);
+
+ /* Report Michael MIC failures to net80211. */
+ ieee80211_notify_michael_failure(ic, wh, 0 /* XXX: keyix */);
+ }
+ ifp->if_ierrors++;
+ goto skip;
+ }
+
+ len = MS(ds->ds_status1, AR_RXS1_DATA_LEN);
+ if (__predict_false(len < (int)IEEE80211_MIN_LEN || len > ATHN_RXBUFSZ)) {
+ DPRINTFN(DBG_RX, sc, "corrupted descriptor length=%d\n", len);
+ ifp->if_ierrors++;
+ goto skip;
+ }
+
+ /* Allocate a new Rx buffer. */
+ m1 = MCLGETI(NULL, M_DONTWAIT, NULL, ATHN_RXBUFSZ);
+ if (__predict_false(m1 == NULL)) {
+ ic->ic_stats.is_rx_nobuf++;
+ ifp->if_ierrors++;
+ goto skip;
+ }
+
+ /* Sync and unmap the old Rx buffer. */
+ bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, ATHN_RXBUFSZ,
+ BUS_DMASYNC_POSTREAD);
+ bus_dmamap_unload(sc->sc_dmat, bf->bf_map);
+
+ /* Map the new Rx buffer. */
+ error = bus_dmamap_load(sc->sc_dmat, bf->bf_map, mtod(m1, void *),
+ ATHN_RXBUFSZ, NULL, BUS_DMA_NOWAIT | BUS_DMA_READ);
+ if (__predict_false(error != 0)) {
+ m_freem(m1);
+
+ /* Remap the old Rx buffer or panic. */
+ error = bus_dmamap_load(sc->sc_dmat, bf->bf_map,
+ mtod(bf->bf_m, void *), ATHN_RXBUFSZ, NULL,
+ BUS_DMA_NOWAIT | BUS_DMA_READ);
+ KASSERT(error != 0);
+ ifp->if_ierrors++;
+ goto skip;
+ }
+
+ bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, ATHN_RXBUFSZ,
+ BUS_DMASYNC_PREREAD);
+
+ /* Write physical address of new Rx buffer. */
+ ds->ds_data = bf->bf_map->dm_segs[0].ds_addr;
+
+ m = bf->bf_m;
+ bf->bf_m = m1;
+
+ /* Finalize mbuf. */
+ m->m_pkthdr.rcvif = ifp;
+ m->m_pkthdr.len = m->m_len = len;
+
+ /* Grab a reference to the source node. */
+ wh = mtod(m, struct ieee80211_frame *);
+ ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh);
+
+ /* Remove any HW padding after the 802.11 header. */
+ if (!(wh->i_fc[0] & IEEE80211_FC0_TYPE_CTL)) {
+ u_int hdrlen = ieee80211_anyhdrsize(wh);
+ if (hdrlen & 3) {
+ ovbcopy(wh, (uint8_t *)wh + 2, hdrlen);
+ m_adj(m, 2);
+ }
+ }
+ if (__predict_false(sc->sc_drvbpf != NULL))
+ ar5008_rx_radiotap(sc, m, ds);
+
+ /* Trim 802.11 FCS after radiotap. */
+ m_adj(m, -IEEE80211_CRC_LEN);
+
+ /* Send the frame to the 802.11 layer. */
+ rssi = MS(ds->ds_status4, AR_RXS4_RSSI_COMBINED);
+ rstamp = ds->ds_status2;
+ ieee80211_input(ic, m, ni, rssi, rstamp);
+
+ /* Node is no longer needed. */
+ ieee80211_free_node(ni);
+
+ skip:
+ /* Unlink this descriptor from head. */
+ SIMPLEQ_REMOVE_HEAD(&rxq->head, bf_list);
+ memset(&ds->ds_status0, 0, 36); /* XXX Really needed? */
+ ds->ds_status8 &= ~AR_RXS8_DONE;
+ ds->ds_link = 0;
+
+ /* Re-use this descriptor and link it to tail. */
+ if (__predict_true(!SIMPLEQ_EMPTY(&rxq->head)))
+ ((struct ar_rx_desc *)rxq->lastds)->ds_link = bf->bf_daddr;
+ else
+ AR_WRITE(sc, AR_RXDP, bf->bf_daddr);
+ SIMPLEQ_INSERT_TAIL(&rxq->head, bf, bf_list);
+ rxq->lastds = ds;
+
+ /* Re-enable Rx. */
+ AR_WRITE(sc, AR_CR, AR_CR_RXE);
+ AR_WRITE_BARRIER(sc);
+ return 0;
+}
+
+Static void
+ar5008_rx_intr(struct athn_softc *sc)
+{
+
+ while (ar5008_rx_process(sc) == 0)
+ continue;
+}
+
+Static int
+ar5008_tx_process(struct athn_softc *sc, int qid)
+{
+ struct ifnet *ifp = &sc->sc_if;
+ struct athn_txq *txq = &sc->sc_txq[qid];
+ struct athn_node *an;
+ struct athn_tx_buf *bf;
+ struct ar_tx_desc *ds;
+ uint8_t failcnt;
+
+ bf = SIMPLEQ_FIRST(&txq->head);
+ if (bf == NULL)
+ return ENOENT;
+ /* Get descriptor of last DMA segment. */
+ ds = &((struct ar_tx_desc *)bf->bf_descs)[bf->bf_map->dm_nsegs - 1];
+
+ if (!(ds->ds_status9 & AR_TXS9_DONE))
+ return EBUSY;
+
+ SIMPLEQ_REMOVE_HEAD(&txq->head, bf_list);
+ ifp->if_opackets++;
+
+ sc->sc_tx_timer = 0;
+
+ if (ds->ds_status1 & AR_TXS1_EXCESSIVE_RETRIES)
+ ifp->if_oerrors++;
+
+ if (ds->ds_status1 & AR_TXS1_UNDERRUN)
+ athn_inc_tx_trigger_level(sc);
+
+ an = (struct athn_node *)bf->bf_ni;
+ /*
+ * NB: the data fail count contains the number of un-acked tries
+ * for the final series used. We must add the number of tries for
+ * each series that was fully processed.
+ */
+ failcnt = MS(ds->ds_status1, AR_TXS1_DATA_FAIL_CNT);
+ /* NB: Assume two tries per series. */
+ failcnt += MS(ds->ds_status9, AR_TXS9_FINAL_IDX) * 2;
+
+ /* Update rate control statistics. */
+ an->amn.amn_txcnt++;
+ if (failcnt > 0)
+ an->amn.amn_retrycnt++;
+
+ DPRINTFN(DBG_TX, sc, "Tx done qid=%d status1=%d fail count=%d\n",
+ qid, ds->ds_status1, failcnt);
+
+ bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, bf->bf_map->dm_mapsize,
+ BUS_DMASYNC_POSTWRITE);
+ bus_dmamap_unload(sc->sc_dmat, bf->bf_map);
+
+ m_freem(bf->bf_m);
+ bf->bf_m = NULL;
+ ieee80211_free_node(bf->bf_ni);
+ bf->bf_ni = NULL;
+
+ /* Link Tx buffer back to global free list. */
+ SIMPLEQ_INSERT_TAIL(&sc->sc_txbufs, bf, bf_list);
+ return 0;
+}
+
+Static void
+ar5008_tx_intr(struct athn_softc *sc)
+{
+ struct ifnet *ifp = &sc->sc_if;
+ uint16_t mask = 0;
+ uint32_t reg;
+ int qid;
+
+ reg = AR_READ(sc, AR_ISR_S0_S);
+ mask |= MS(reg, AR_ISR_S0_QCU_TXOK);
+ mask |= MS(reg, AR_ISR_S0_QCU_TXDESC);
+
+ reg = AR_READ(sc, AR_ISR_S1_S);
+ mask |= MS(reg, AR_ISR_S1_QCU_TXERR);
+ mask |= MS(reg, AR_ISR_S1_QCU_TXEOL);
+
+ DPRINTFN(DBG_TX, sc, "Tx interrupt mask=0x%x\n", mask);
+ for (qid = 0; mask != 0; mask >>= 1, qid++) {
+ if (mask & 1)
+ while (ar5008_tx_process(sc, qid) == 0);
+ }
+ if (!SIMPLEQ_EMPTY(&sc->sc_txbufs)) {
+ ifp->if_flags &= ~IFF_OACTIVE;
+ ifp->if_start(ifp);
+ }
+}
+
+#ifndef IEEE80211_STA_ONLY
+/*
+ * Process Software Beacon Alert interrupts.
+ */
+Static int
+ar5008_swba_intr(struct athn_softc *sc)
+{
+ struct ieee80211com *ic = &sc->sc_ic;
+ struct ifnet *ifp = &sc->sc_if;
+ struct ieee80211_node *ni = ic->ic_bss;
+ struct athn_tx_buf *bf = sc->sc_bcnbuf;
+ struct ieee80211_frame *wh;
+ struct ieee80211_beacon_offsets bo;
+ struct ar_tx_desc *ds;
+ struct mbuf *m;
+ uint8_t ridx, hwrate;
+ int error, totlen;
+
+#if notyet
+ if (ic->ic_tim_mcast_pending &&
+ IF_IS_EMPTY(&ni->ni_savedq) &&
+ SIMPLEQ_EMPTY(&sc->sc_txq[ATHN_QID_CAB].head))
+ ic->ic_tim_mcast_pending = 0;
+#endif
+ if (ic->ic_dtim_count == 0)
+ ic->ic_dtim_count = ic->ic_dtim_period - 1;
+ else
+ ic->ic_dtim_count--;
+
+ /* Make sure previous beacon has been sent. */
+ if (athn_tx_pending(sc, ATHN_QID_BEACON)) {
+ DPRINTFN(DBG_INTR, sc, "beacon stuck\n");
+ return EBUSY;
+ }
+ /* Get new beacon. */
+ m = ieee80211_beacon_alloc(ic, ic->ic_bss, &bo);
+ if (__predict_false(m == NULL))
+ return ENOBUFS;
+ /* Assign sequence number. */
+ /* XXX: use non-QoS tid? */
+ wh = mtod(m, struct ieee80211_frame *);
+ *(uint16_t *)&wh->i_seq[0] =
+ htole16(ic->ic_bss->ni_txseqs[0] << IEEE80211_SEQ_SEQ_SHIFT);
+ ic->ic_bss->ni_txseqs[0]++;
+
+ /* Unmap and free old beacon if any. */
+ if (__predict_true(bf->bf_m != NULL)) {
+ bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0,
+ bf->bf_map->dm_mapsize, BUS_DMASYNC_POSTWRITE);
+ bus_dmamap_unload(sc->sc_dmat, bf->bf_map);
+ m_freem(bf->bf_m);
+ bf->bf_m = NULL;
+ }
+ /* DMA map new beacon. */
+ error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_map, m,
+ BUS_DMA_NOWAIT | BUS_DMA_WRITE);
+ if (__predict_false(error != 0)) {
+ m_freem(m);
+ return error;
+ }
+ bf->bf_m = m;
+
+ /* Setup Tx descriptor (simplified ar5008_tx()). */
+ ds = bf->bf_descs;
+ memset(ds, 0, sizeof(*ds));
+
+ totlen = m->m_pkthdr.len + IEEE80211_CRC_LEN;
+ ds->ds_ctl0 = SM(AR_TXC0_FRAME_LEN, totlen);
+ ds->ds_ctl0 |= SM(AR_TXC0_XMIT_POWER, AR_MAX_RATE_POWER);
+ ds->ds_ctl1 = SM(AR_TXC1_FRAME_TYPE, AR_FRAME_TYPE_BEACON);
+ ds->ds_ctl1 |= AR_TXC1_NO_ACK;
+ ds->ds_ctl6 = SM(AR_TXC6_ENCR_TYPE, AR_ENCR_TYPE_CLEAR);
+
+ /* Write number of tries. */
+ ds->ds_ctl2 = SM(AR_TXC2_XMIT_DATA_TRIES0, 1);
+
+ /* Write Tx rate. */
+ ridx = (ic->ic_curmode == IEEE80211_MODE_11A) ?
+ ATHN_RIDX_OFDM6 : ATHN_RIDX_CCK1;
+ hwrate = athn_rates[ridx].hwrate;
+ ds->ds_ctl3 = SM(AR_TXC3_XMIT_RATE0, hwrate);
+
+ /* Write Tx chains. */
+ ds->ds_ctl7 = SM(AR_TXC7_CHAIN_SEL0, sc->sc_txchainmask);
+
+ ds->ds_data = bf->bf_map->dm_segs[0].ds_addr;
+ /* Segment length must be a multiple of 4. */
+ ds->ds_ctl1 |= SM(AR_TXC1_BUF_LEN,
+ (bf->bf_map->dm_segs[0].ds_len + 3) & ~3);
+
+ bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, bf->bf_map->dm_mapsize,
+ BUS_DMASYNC_PREWRITE);
+
+ /* Stop Tx DMA before putting the new beacon on the queue. */
+ athn_stop_tx_dma(sc, ATHN_QID_BEACON);
+
+ AR_WRITE(sc, AR_QTXDP(ATHN_QID_BEACON), bf->bf_daddr);
+
+ for(;;) {
+ if (SIMPLEQ_EMPTY(&sc->sc_txbufs))
+ break;
+
+ IF_DEQUEUE(&ni->ni_savedq, m);
+ if (m == NULL)
+ break;
+ if (!IF_IS_EMPTY(&ni->ni_savedq)) {
+ /* more queued frames, set the more data bit */
+ wh = mtod(m, struct ieee80211_frame *);
+ wh->i_fc[1] |= IEEE80211_FC1_MORE_DATA;
+ }
+
+ if (sc->sc_ops.tx(sc, m, ni, ATHN_TXFLAG_CAB) != 0) {
+ ieee80211_free_node(ni);
+ ifp->if_oerrors++;
+ break;
+ }
+ }
+
+ /* Kick Tx. */
+ AR_WRITE(sc, AR_Q_TXE, 1 << ATHN_QID_BEACON);
+ AR_WRITE_BARRIER(sc);
+ return 0;
+}
+#endif
+
+Static int
+ar5008_intr(struct athn_softc *sc)
+{
+ uint32_t intr, intr2, intr5, sync;
+
+ /* Get pending interrupts. */
+ intr = AR_READ(sc, AR_INTR_ASYNC_CAUSE);
+ if (!(intr & AR_INTR_MAC_IRQ) || intr == AR_INTR_SPURIOUS) {
+ intr = AR_READ(sc, AR_INTR_SYNC_CAUSE);
+ if (intr == AR_INTR_SPURIOUS || (intr & sc->sc_isync) == 0)
+ return 0; /* Not for us. */
+ }
+
+ if ((AR_READ(sc, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) &&
+ (AR_READ(sc, AR_RTC_STATUS) & AR_RTC_STATUS_M) == AR_RTC_STATUS_ON)
+ intr = AR_READ(sc, AR_ISR);
+ else
+ intr = 0;
+ sync = AR_READ(sc, AR_INTR_SYNC_CAUSE) & sc->sc_isync;
+ if (intr == 0 && sync == 0)
+ return 0; /* Not for us. */
+
+ if (intr != 0) {
+ if (intr & AR_ISR_BCNMISC) {
+ intr2 = AR_READ(sc, AR_ISR_S2);
+#if notyet
+ if (intr2 & AR_ISR_S2_TIM)
+ /* TBD */;
+ if (intr2 & AR_ISR_S2_TSFOOR)
+ /* TBD */;
+#endif
+ }
+ intr = AR_READ(sc, AR_ISR_RAC);
+ if (intr == AR_INTR_SPURIOUS)
+ return 1;
+
+#ifndef IEEE80211_STA_ONLY
+ if (intr & AR_ISR_SWBA)
+ ar5008_swba_intr(sc);
+#endif
+ if (intr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
+ ar5008_rx_intr(sc);
+ if (intr & (AR_ISR_RXOK | AR_ISR_RXERR | AR_ISR_RXORN))
+ ar5008_rx_intr(sc);
+
+ if (intr & (AR_ISR_TXOK | AR_ISR_TXDESC |
+ AR_ISR_TXERR | AR_ISR_TXEOL))
+ ar5008_tx_intr(sc);
+
+ intr5 = AR_READ(sc, AR_ISR_S5_S);
+ if (intr & AR_ISR_GENTMR) {
+ if (intr5 & AR_ISR_GENTMR) {
+ DPRINTFN(DBG_INTR, sc,
+ "GENTMR trigger=%d thresh=%d\n",
+ MS(intr5, AR_ISR_S5_GENTIMER_TRIG),
+ MS(intr5, AR_ISR_S5_GENTIMER_THRESH));
+ }
+ }
+#if notyet
+ if (intr5 & AR_ISR_S5_TIM_TIMER) {
+ /* TBD */;
+ }
+#endif
+ }
+ if (sync != 0) {
+#if notyet
+ if (sync &
+ (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR)) {
+ /* TBD */;
+ }
+#endif
+ if (sync & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
+ AR_WRITE(sc, AR_RC, AR_RC_HOSTIF);
+ AR_WRITE(sc, AR_RC, 0);
+ }
+
+ if ((sc->sc_flags & ATHN_FLAG_RFSILENT) &&
+ (sync & AR_INTR_SYNC_GPIO_PIN(sc->sc_rfsilent_pin))) {
+ struct ifnet *ifp = &sc->sc_if;
+
+ printf("%s: radio switch turned off\n",
+ device_xname(sc->sc_dev));
+ /* Turn the interface down. */
+ ifp->if_flags &= ~IFF_UP;
+ athn_stop(ifp, 1);
+ return 1;
+ }
+
+ AR_WRITE(sc, AR_INTR_SYNC_CAUSE, sync);
+ (void)AR_READ(sc, AR_INTR_SYNC_CAUSE);
+ }
+ return 1;
+}
+
+Static int
+ar5008_tx(struct athn_softc *sc, struct mbuf *m, struct ieee80211_node *ni,
+ int txflags)
+{
+ struct ieee80211com *ic = &sc->sc_ic;
+ struct ieee80211_key *k = NULL;
+ struct ieee80211_frame *wh;
+ struct athn_series series[4];
+ struct ar_tx_desc *ds, *lastds;
+ struct athn_txq *txq;
+ struct athn_tx_buf *bf;
+ struct athn_node *an = (void *)ni;
+ struct mbuf *m1;
+ uint16_t qos;
+ uint8_t txpower, type, encrtype, ridx[4];
+ int i, error, totlen, hasqos, qid;
+
+ /* Grab a Tx buffer from our global free list. */
+ bf = SIMPLEQ_FIRST(&sc->sc_txbufs);
+ KASSERT(bf != NULL);
+
+ /* Map 802.11 frame type to hardware frame type. */
+ wh = mtod(m, struct ieee80211_frame *);
+ if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) ==
+ IEEE80211_FC0_TYPE_MGT) {
+ /* NB: Beacons do not use ar5008_tx(). */
+ if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) ==
+ IEEE80211_FC0_SUBTYPE_PROBE_RESP)
+ type = AR_FRAME_TYPE_PROBE_RESP;
+ else if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) ==
+ IEEE80211_FC0_SUBTYPE_ATIM)
+ type = AR_FRAME_TYPE_ATIM;
+ else
+ type = AR_FRAME_TYPE_NORMAL;
+ }
+ else if ((wh->i_fc[0] &
+ (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) ==
+ (IEEE80211_FC0_TYPE_CTL | IEEE80211_FC0_SUBTYPE_PS_POLL)) {
+ type = AR_FRAME_TYPE_PSPOLL;
+ }
+ else
+ type = AR_FRAME_TYPE_NORMAL;
+
+ if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) {
+ k = ieee80211_crypto_encap(ic, ni, m);
+ if (k == NULL)
+ return ENOBUFS;
+
+ /* packet header may have moved, reset our local pointer */
+ wh = mtod(m, struct ieee80211_frame *);
+ }
+
+ /* XXX 2-byte padding for QoS and 4-addr headers. */
+
+ /* Select the HW Tx queue to use for this frame. */
+ if ((hasqos = ieee80211_has_qos(wh))) {
+#ifdef notyet_edca
+ uint8_t tid;
+
+ qos = ieee80211_get_qos(wh);
+ tid = qos & IEEE80211_QOS_TID;
+ qid = athn_ac2qid[ieee80211_up_to_ac(ic, tid)];
+#else
+ qos = ieee80211_get_qos(wh);
+ qid = ATHN_QID_AC_BE;
+#endif /* notyet_edca */
+ }
+ else if (type == AR_FRAME_TYPE_PSPOLL) {
+ qos = 0;
+ qid = ATHN_QID_PSPOLL;
+ }
+ else if (txflags & ATHN_TXFLAG_CAB) {
+ qos = 0;
+ qid = ATHN_QID_CAB;
+ }
+ else {
+ qos = 0;
+ qid = ATHN_QID_AC_BE;
+ }
+ txq = &sc->sc_txq[qid];
+
+ /* Select the transmit rates to use for this frame. */
+ if (IEEE80211_IS_MULTICAST(wh->i_addr1) ||
+ (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) !=
+ IEEE80211_FC0_TYPE_DATA) {
+ /* Use lowest rate for all tries. */
+ ridx[0] = ridx[1] = ridx[2] = ridx[3] =
+ (ic->ic_curmode == IEEE80211_MODE_11A) ?
+ ATHN_RIDX_OFDM6 : ATHN_RIDX_CCK1;
+ }
+ else if (ic->ic_fixed_rate != -1) {
+ /* Use same fixed rate for all tries. */
+ ridx[0] = ridx[1] = ridx[2] = ridx[3] =
+ sc->sc_fixed_ridx;
+ }
+ else {
+ int txrate = ni->ni_txrate;
+ /* Use fallback table of the node. */
+ for (i = 0; i < 4; i++) {
+ ridx[i] = an->ridx[txrate];
+ txrate = an->fallback[txrate];
+ }
+ }
+
+ if (__predict_false(sc->sc_drvbpf != NULL)) {
+ struct athn_tx_radiotap_header *tap = &sc->sc_txtap;
+
+ tap->wt_flags = 0;
+ /* Use initial transmit rate. */
+ tap->wt_rate = athn_rates[ridx[0]].rate;
+ tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq);
+ tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags);
+// XXX tap->wt_hwqueue = qid;
+ if (ridx[0] != ATHN_RIDX_CCK1 &&
+ (ic->ic_flags & IEEE80211_F_SHPREAMBLE))
+ tap->wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
+
+ bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m);
+ }
+
+ /* DMA map mbuf. */
+ error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_map, m,
+ BUS_DMA_NOWAIT | BUS_DMA_WRITE);
+ if (__predict_false(error != 0)) {
+ if (error != EFBIG) {
+ printf("%s: can't map mbuf (error %d)\n",
+ device_xname(sc->sc_dev), error);
+ m_freem(m);
+ return error;
+ }
+ /*
+ * DMA mapping requires too many DMA segments; linearize
+ * mbuf in kernel virtual address space and retry.
+ */
+ MGETHDR(m1, M_DONTWAIT, MT_DATA);
+ if (m1 == NULL) {
+ m_freem(m);
+ return ENOBUFS;
+ }
+ if (m->m_pkthdr.len > (int)MHLEN) {
+ MCLGET(m1, M_DONTWAIT);
+ if (!(m1->m_flags & M_EXT)) {
+ m_freem(m);
+ m_freem(m1);
+ return ENOBUFS;
+ }
+ }
+ m_copydata(m, 0, m->m_pkthdr.len, mtod(m1, void *));
+ m1->m_pkthdr.len = m1->m_len = m->m_pkthdr.len;
+ m_freem(m);
+ m = m1;
+
+ error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_map, m,
+ BUS_DMA_NOWAIT | BUS_DMA_WRITE);
+ if (error != 0) {
+ printf("%s: can't map mbuf (error %d)\n",
+ device_xname(sc->sc_dev), error);
+ m_freem(m);
+ return error;
+ }
+ }
+ bf->bf_m = m;
+ bf->bf_ni = ni;
+ bf->bf_txflags = txflags;
+
+ wh = mtod(m, struct ieee80211_frame *);
+
+ totlen = m->m_pkthdr.len + IEEE80211_CRC_LEN;
+
+ /* Clear all Tx descriptors that we will use. */
+ memset(bf->bf_descs, 0, bf->bf_map->dm_nsegs * sizeof(*ds));
+
+ /* Setup first Tx descriptor. */
+ ds = bf->bf_descs;
+
+ ds->ds_ctl0 = AR_TXC0_INTR_REQ | AR_TXC0_CLR_DEST_MASK;
+ txpower = AR_MAX_RATE_POWER; /* Get from per-rate registers. */
+ ds->ds_ctl0 |= SM(AR_TXC0_XMIT_POWER, txpower);
+
+ ds->ds_ctl1 = SM(AR_TXC1_FRAME_TYPE, type);
+
+ if (IEEE80211_IS_MULTICAST(wh->i_addr1) ||
+ (hasqos && (qos & IEEE80211_QOS_ACKPOLICY_MASK) ==
+ IEEE80211_QOS_ACKPOLICY_NOACK))
+ ds->ds_ctl1 |= AR_TXC1_NO_ACK;
+#if notyet
+ if (0 && k != NULL) {
+ uintptr_t entry;
+
+ /*
+ * Map 802.11 cipher to hardware encryption type and
+ * compute MIC+ICV overhead.
+ */
+ totlen += k->wk_keylen;
+ switch (k->wk_cipher->ic_cipher) {
+ case IEEE80211_CIPHER_WEP:
+ encrtype = AR_ENCR_TYPE_WEP;
+ break;
+ case IEEE80211_CIPHER_TKIP:
+ encrtype = AR_ENCR_TYPE_TKIP;
+ break;
+ case IEEE80211_CIPHER_AES_OCB:
+ case IEEE80211_CIPHER_AES_CCM:
+ encrtype = AR_ENCR_TYPE_AES;
+ break;
+ default:
+ panic("unsupported cipher");
+ }
+ /*
+ * NB: The key cache entry index is stored in the key
+ * private field when the key is installed.
+ */
+ entry = (uintptr_t)k->k_priv;
+ ds->ds_ctl1 |= SM(AR_TXC1_DEST_IDX, entry);
+ ds->ds_ctl0 |= AR_TXC0_DEST_IDX_VALID;
+ }
+ else
+#endif
+ encrtype = AR_ENCR_TYPE_CLEAR;
+ ds->ds_ctl6 = SM(AR_TXC6_ENCR_TYPE, encrtype);
+
+ /* Check if frame must be protected using RTS/CTS or CTS-to-self. */
+ if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) {
+ /* NB: Group frames are sent using CCK in 802.11b/g. */
+ if (totlen > ic->ic_rtsthreshold) {
+ ds->ds_ctl0 |= AR_TXC0_RTS_ENABLE;
+ }
+ else if ((ic->ic_flags & IEEE80211_F_USEPROT) &&
+ athn_rates[ridx[0]].phy == IEEE80211_T_OFDM) {
+ if (ic->ic_protmode == IEEE80211_PROT_RTSCTS)
+ ds->ds_ctl0 |= AR_TXC0_RTS_ENABLE;
+ else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY)
+ ds->ds_ctl0 |= AR_TXC0_CTS_ENABLE;
+ }
+ }
+ if (ds->ds_ctl0 & (AR_TXC0_RTS_ENABLE | AR_TXC0_CTS_ENABLE)) {
+ /* Disable multi-rate retries when protection is used. */
+ ridx[1] = ridx[2] = ridx[3] = ridx[0];
+ }
+ /* Setup multi-rate retries. */
+ for (i = 0; i < 4; i++) {
+ series[i].hwrate = athn_rates[ridx[i]].hwrate;
+ if (athn_rates[ridx[i]].phy == IEEE80211_T_DS &&
+ ridx[i] != ATHN_RIDX_CCK1 &&
+ (ic->ic_flags & IEEE80211_F_SHPREAMBLE))
+ series[i].hwrate |= 0x04;
+ series[i].dur = 0;
+ }
+ if (!(ds->ds_ctl1 & AR_TXC1_NO_ACK)) {
+ /* Compute duration for each series. */
+ for (i = 0; i < 4; i++) {
+ series[i].dur = athn_txtime(sc, IEEE80211_ACK_LEN,
+ athn_rates[ridx[i]].rspridx, ic->ic_flags);
+ }
+ }
+
+ /* Write number of tries for each series. */
+ ds->ds_ctl2 =
+ SM(AR_TXC2_XMIT_DATA_TRIES0, 2) |
+ SM(AR_TXC2_XMIT_DATA_TRIES1, 2) |
+ SM(AR_TXC2_XMIT_DATA_TRIES2, 2) |
+ SM(AR_TXC2_XMIT_DATA_TRIES3, 4);
+
+ /* Tell HW to update duration field in 802.11 header. */
+ if (type != AR_FRAME_TYPE_PSPOLL)
+ ds->ds_ctl2 |= AR_TXC2_DUR_UPDATE_ENA;
+
+ /* Write Tx rate for each series. */
+ ds->ds_ctl3 =
+ SM(AR_TXC3_XMIT_RATE0, series[0].hwrate) |
+ SM(AR_TXC3_XMIT_RATE1, series[1].hwrate) |
+ SM(AR_TXC3_XMIT_RATE2, series[2].hwrate) |
+ SM(AR_TXC3_XMIT_RATE3, series[3].hwrate);
+
+ /* Write duration for each series. */
+ ds->ds_ctl4 =
+ SM(AR_TXC4_PACKET_DUR0, series[0].dur) |
+ SM(AR_TXC4_PACKET_DUR1, series[1].dur);
+ ds->ds_ctl5 =
+ SM(AR_TXC5_PACKET_DUR2, series[2].dur) |
+ SM(AR_TXC5_PACKET_DUR3, series[3].dur);
+
+ /* Use the same Tx chains for all tries. */
+ ds->ds_ctl7 =
+ SM(AR_TXC7_CHAIN_SEL0, sc->sc_txchainmask) |
+ SM(AR_TXC7_CHAIN_SEL1, sc->sc_txchainmask) |
+ SM(AR_TXC7_CHAIN_SEL2, sc->sc_txchainmask) |
+ SM(AR_TXC7_CHAIN_SEL3, sc->sc_txchainmask);
+#ifdef notyet
+#ifndef IEEE80211_NO_HT
+ /* Use the same short GI setting for all tries. */
+ if (ic->ic_flags & IEEE80211_F_SHGI)
+ ds->ds_ctl7 |= AR_TXC7_GI0123;
+ /* Use the same channel width for all tries. */
+ if (ic->ic_flags & IEEE80211_F_CBW40)
+ ds->ds_ctl7 |= AR_TXC7_2040_0123;
+#endif
+#endif
+
+ if (ds->ds_ctl0 & (AR_TXC0_RTS_ENABLE | AR_TXC0_CTS_ENABLE)) {
+ uint8_t protridx, hwrate;
+ uint16_t dur = 0;
+
+ /* Use the same protection mode for all tries. */
+ if (ds->ds_ctl0 & AR_TXC0_RTS_ENABLE) {
+ ds->ds_ctl4 |= AR_TXC4_RTSCTS_QUAL01;
+ ds->ds_ctl5 |= AR_TXC5_RTSCTS_QUAL23;
+ }
+ /* Select protection rate (suboptimal but ok). */
+ protridx = (ic->ic_curmode == IEEE80211_MODE_11A) ?
+ ATHN_RIDX_OFDM6 : ATHN_RIDX_CCK2;
+ if (ds->ds_ctl0 & AR_TXC0_RTS_ENABLE) {
+ /* Account for CTS duration. */
+ dur += athn_txtime(sc, IEEE80211_ACK_LEN,
+ athn_rates[protridx].rspridx, ic->ic_flags);
+ }
+ dur += athn_txtime(sc, totlen, ridx[0], ic->ic_flags);
+ if (!(ds->ds_ctl1 & AR_TXC1_NO_ACK)) {
+ /* Account for ACK duration. */
+ dur += athn_txtime(sc, IEEE80211_ACK_LEN,
+ athn_rates[ridx[0]].rspridx, ic->ic_flags);
+ }
+ /* Write protection frame duration and rate. */
+ ds->ds_ctl2 |= SM(AR_TXC2_BURST_DUR, dur);
+ hwrate = athn_rates[protridx].hwrate;
+ if (protridx == ATHN_RIDX_CCK2 &&
+ (ic->ic_flags & IEEE80211_F_SHPREAMBLE))
+ hwrate |= 0x04;
+ ds->ds_ctl7 |= SM(AR_TXC7_RTSCTS_RATE, hwrate);
+ }
+
+ /* Finalize first Tx descriptor and fill others (if any). */
+ ds->ds_ctl0 |= SM(AR_TXC0_FRAME_LEN, totlen);
+
+ lastds = NULL; /* XXX: gcc */
+ for (i = 0; i < bf->bf_map->dm_nsegs; i++, ds++) {
+ ds->ds_data = bf->bf_map->dm_segs[i].ds_addr;
+ ds->ds_ctl1 |= SM(AR_TXC1_BUF_LEN,
+ bf->bf_map->dm_segs[i].ds_len);
+
+ if (i != bf->bf_map->dm_nsegs - 1)
+ ds->ds_ctl1 |= AR_TXC1_MORE;
+ ds->ds_link = 0;
+
+ /* Chain Tx descriptor. */
+ if (i != 0)
+ lastds->ds_link = bf->bf_daddr + i * sizeof(*ds);
+ lastds = ds;
+ }
+ bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, bf->bf_map->dm_mapsize,
+ BUS_DMASYNC_PREWRITE);
+
+ if (!SIMPLEQ_EMPTY(&txq->head))
+ ((struct ar_tx_desc *)txq->lastds)->ds_link = bf->bf_daddr;
+ else
+ AR_WRITE(sc, AR_QTXDP(qid), bf->bf_daddr);
+ txq->lastds = lastds;
+ SIMPLEQ_REMOVE_HEAD(&sc->sc_txbufs, bf_list);
+ SIMPLEQ_INSERT_TAIL(&txq->head, bf, bf_list);
+
+ ds = bf->bf_descs;
+ DPRINTFN(DBG_TX, sc,
+ "Tx qid=%d nsegs=%d ctl0=0x%x ctl1=0x%x ctl3=0x%x\n",
+ qid, bf->bf_map->dm_nsegs, ds->ds_ctl0, ds->ds_ctl1, ds->ds_ctl3);
+
+ /* Kick Tx. */
+ AR_WRITE(sc, AR_Q_TXE, 1 << qid);
+ AR_WRITE_BARRIER(sc);
+ return 0;
+}
+
+Static void
+ar5008_set_rf_mode(struct athn_softc *sc, struct ieee80211_channel *c)
+{
+ uint32_t reg;
+
+ reg = IEEE80211_IS_CHAN_2GHZ(c) ?
+ AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
+ if (!AR_SREV_9280_10_OR_LATER(sc)) {
+ reg |= IEEE80211_IS_CHAN_2GHZ(c) ?
+ AR_PHY_MODE_RF2GHZ : AR_PHY_MODE_RF5GHZ;
+ }
+ else if (IEEE80211_IS_CHAN_5GHZ(c) &&
+ (sc->sc_flags & ATHN_FLAG_FAST_PLL_CLOCK)) {
+ reg |= AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE;
+ }
+ AR_WRITE(sc, AR_PHY_MODE, reg);
+ AR_WRITE_BARRIER(sc);
+}
+
+static __inline uint32_t
+ar5008_synth_delay(struct athn_softc *sc)
+{
+ uint32_t delay;
+
+ delay = MS(AR_READ(sc, AR_PHY_RX_DELAY), AR_PHY_RX_DELAY_DELAY);
+ if (sc->sc_ic.ic_curmode == IEEE80211_MODE_11B)
+ delay = (delay * 4) / 22;
+ else
+ delay = delay / 10; /* in 100ns steps */
+ return delay;
+}
+
+Static int
+ar5008_rf_bus_request(struct athn_softc *sc)
+{
+ int ntries;
+
+ /* Request RF Bus grant. */
+ AR_WRITE(sc, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
+ for (ntries = 0; ntries < 10000; ntries++) {
+ if (AR_READ(sc, AR_PHY_RFBUS_GRANT) & AR_PHY_RFBUS_GRANT_EN)
+ return 0;
+ DELAY(10);
+ }
+ DPRINTFN(DBG_RF, sc, "could not kill baseband Rx");
+ return ETIMEDOUT;
+}
+
+Static void
+ar5008_rf_bus_release(struct athn_softc *sc)
+{
+
+ /* Wait for the synthesizer to settle. */
+ DELAY(AR_BASE_PHY_ACTIVE_DELAY + ar5008_synth_delay(sc));
+
+ /* Release the RF Bus grant. */
+ AR_WRITE(sc, AR_PHY_RFBUS_REQ, 0);
+ AR_WRITE_BARRIER(sc);
+}
+
+Static void
+ar5008_set_phy(struct athn_softc *sc, struct ieee80211_channel *c,
+ struct ieee80211_channel *extc)
+{
+ uint32_t phy;
+
+ if (AR_SREV_9285_10_OR_LATER(sc))
+ phy = AR_READ(sc, AR_PHY_TURBO) & AR_PHY_FC_ENABLE_DAC_FIFO;
+ else
+ phy = 0;
+ phy |= AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40 |
+ AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH;
+#ifndef IEEE80211_NO_HT
+ if (extc != NULL) {
+ phy |= AR_PHY_FC_DYN2040_EN;
+ if (extc > c) /* XXX */
+ phy |= AR_PHY_FC_DYN2040_PRI_CH;
+ }
+#endif
+ AR_WRITE(sc, AR_PHY_TURBO, phy);
+
+ AR_WRITE(sc, AR_2040_MODE,
+ (extc != NULL) ? AR_2040_JOINED_RX_CLEAR : 0);
+
+ /* Set global transmit timeout. */
+ AR_WRITE(sc, AR_GTXTO, SM(AR_GTXTO_TIMEOUT_LIMIT, 25));
+ /* Set carrier sense timeout. */
+ AR_WRITE(sc, AR_CST, SM(AR_CST_TIMEOUT_LIMIT, 15));
+ AR_WRITE_BARRIER(sc);
+}
+
+Static void
+ar5008_set_delta_slope(struct athn_softc *sc, struct ieee80211_channel *c,
+ struct ieee80211_channel *extc)
+{
+ uint32_t coeff, exp, man, reg;
+
+ /* Set Delta Slope (exponent and mantissa). */
+ coeff = (100 << 24) / c->ic_freq;
+ athn_get_delta_slope(coeff, &exp, &man);
+ DPRINTFN(DBG_RX, sc, "delta slope coeff exp=%u man=%u\n", exp, man);
+
+ reg = AR_READ(sc, AR_PHY_TIMING3);
+ reg = RW(reg, AR_PHY_TIMING3_DSC_EXP, exp);
+ reg = RW(reg, AR_PHY_TIMING3_DSC_MAN, man);
+ AR_WRITE(sc, AR_PHY_TIMING3, reg);
+
+ /* For Short GI, coeff is 9/10 that of normal coeff. */
+ coeff = (9 * coeff) / 10;
+ athn_get_delta_slope(coeff, &exp, &man);
+ DPRINTFN(DBG_RX, sc, "delta slope coeff exp=%u man=%u\n", exp, man);
+
+ reg = AR_READ(sc, AR_PHY_HALFGI);
+ reg = RW(reg, AR_PHY_HALFGI_DSC_EXP, exp);
+ reg = RW(reg, AR_PHY_HALFGI_DSC_MAN, man);
+ AR_WRITE(sc, AR_PHY_HALFGI, reg);
+ AR_WRITE_BARRIER(sc);
+}
+
+Static void
+ar5008_enable_antenna_diversity(struct athn_softc *sc)
+{
+
+ AR_SETBITS(sc, AR_PHY_CCK_DETECT,
+ AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);
+ AR_WRITE_BARRIER(sc);
+}
+
+Static void
+ar5008_init_baseband(struct athn_softc *sc)
+{
+ uint32_t synth_delay;
+
+ synth_delay = ar5008_synth_delay(sc);
+ /* Activate the PHY (includes baseband activate and synthesizer on). */
+ AR_WRITE(sc, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
+ AR_WRITE_BARRIER(sc);
+ DELAY(AR_BASE_PHY_ACTIVE_DELAY + synth_delay);
+}
+
+Static void
+ar5008_disable_phy(struct athn_softc *sc)
+{
+
+ AR_WRITE(sc, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
+ AR_WRITE_BARRIER(sc);
+}
+
+Static void
+ar5008_init_chains(struct athn_softc *sc)
+{
+
+ if (sc->sc_rxchainmask == 0x5 || sc->sc_txchainmask == 0x5)
+ AR_SETBITS(sc, AR_PHY_ANALOG_SWAP, AR_PHY_SWAP_ALT_CHAIN);
+
+ /* Setup chain masks. */
+ if (sc->sc_mac_ver <= AR_SREV_VERSION_9160 &&
+ (sc->sc_rxchainmask == 0x3 || sc->sc_rxchainmask == 0x5)) {
+ AR_WRITE(sc, AR_PHY_RX_CHAINMASK, 0x7);
+ AR_WRITE(sc, AR_PHY_CAL_CHAINMASK, 0x7);
+ }
+ else {
+ AR_WRITE(sc, AR_PHY_RX_CHAINMASK, sc->sc_rxchainmask);
+ AR_WRITE(sc, AR_PHY_CAL_CHAINMASK, sc->sc_rxchainmask);
+ }
+ AR_WRITE(sc, AR_SELFGEN_MASK, sc->sc_txchainmask);
+ AR_WRITE_BARRIER(sc);
+}
+
+Static void
+ar5008_set_rxchains(struct athn_softc *sc)
+{
+
+ if (sc->sc_rxchainmask == 0x3 || sc->sc_rxchainmask == 0x5) {
+ AR_WRITE(sc, AR_PHY_RX_CHAINMASK, sc->sc_rxchainmask);
+ AR_WRITE(sc, AR_PHY_CAL_CHAINMASK, sc->sc_rxchainmask);
+ AR_WRITE_BARRIER(sc);
+ }
+}
+
+#ifdef notused
+Static void
+ar5008_read_noisefloor(struct athn_softc *sc, int16_t *nf, int16_t *nf_ext)
+{
+/* Sign-extends 9-bit value (assumes upper bits are zeroes). */
+#define SIGN_EXT(v) (((v) ^ 0x100) - 0x100)
+ uint32_t reg;
+ int i;
+
+ for (i = 0; i < sc->sc_nrxchains; i++) {
+ reg = AR_READ(sc, AR_PHY_CCA(i));
+ if (AR_SREV_9280_10_OR_LATER(sc))
+ nf[i] = MS(reg, AR9280_PHY_MINCCA_PWR);
+ else
+ nf[i] = MS(reg, AR_PHY_MINCCA_PWR);
+ nf[i] = SIGN_EXT(nf[i]);
+
+ reg = AR_READ(sc, AR_PHY_EXT_CCA(i));
+ if (AR_SREV_9280_10_OR_LATER(sc))
+ nf_ext[i] = MS(reg, AR9280_PHY_EXT_MINCCA_PWR);
+ else
+ nf_ext[i] = MS(reg, AR_PHY_EXT_MINCCA_PWR);
+ nf_ext[i] = SIGN_EXT(nf_ext[i]);
+ }
+#undef SIGN_EXT
+}
+#endif /* notused */
+
+#ifdef notused
+Static void
+ar5008_write_noisefloor(struct athn_softc *sc, int16_t *nf, int16_t *nf_ext)
+{
+ uint32_t reg;
+ int i;
+
+ for (i = 0; i < sc->sc_nrxchains; i++) {
+ reg = AR_READ(sc, AR_PHY_CCA(i));
+ reg = RW(reg, AR_PHY_MAXCCA_PWR, nf[i]);
+ AR_WRITE(sc, AR_PHY_CCA(i), reg);
+
+ reg = AR_READ(sc, AR_PHY_EXT_CCA(i));
+ reg = RW(reg, AR_PHY_EXT_MAXCCA_PWR, nf_ext[i]);
+ AR_WRITE(sc, AR_PHY_EXT_CCA(i), reg);
+ }
+ AR_WRITE_BARRIER(sc);
+}
+#endif /* notused */
+
+#ifdef notused
+Static void
+ar5008_get_noisefloor(struct athn_softc *sc, struct ieee80211_channel *c)
+{
+ int16_t nf[AR_MAX_CHAINS], nf_ext[AR_MAX_CHAINS];
+ int i;
+
+ if (AR_READ(sc, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) {
+ /* Noisefloor calibration not finished. */
+ return;
+ }
+ /* Noisefloor calibration is finished. */
+ ar5008_read_noisefloor(sc, nf, nf_ext);
+
+ /* Update noisefloor history. */
+ for (i = 0; i < sc->sc_nrxchains; i++) {
+ sc->sc_nf_hist[sc->sc_nf_hist_cur].nf[i] = nf[i];
+ sc->sc_nf_hist[sc->sc_nf_hist_cur].nf_ext[i] = nf_ext[i];
+ }
+ if (++sc->sc_nf_hist_cur >= ATHN_NF_CAL_HIST_MAX)
+ sc->sc_nf_hist_cur = 0;
+}
+#endif /* notused */
+
+#ifdef notused
+Static void
+ar5008_bb_load_noisefloor(struct athn_softc *sc)
+{
+ int16_t nf[AR_MAX_CHAINS], nf_ext[AR_MAX_CHAINS];
+ int i, ntries;
+
+ /* Write filtered noisefloor values. */
+ for (i = 0; i < sc->sc_nrxchains; i++) {
+ nf[i] = sc->sc_nf_priv[i] * 2;
+ nf_ext[i] = sc->sc_nf_ext_priv[i] * 2;
+ }
+ ar5008_write_noisefloor(sc, nf, nf_ext);
+
+ /* Load filtered noisefloor values into baseband. */
+ AR_CLRBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF);
+ AR_CLRBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
+ AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
+ /* Wait for load to complete. */
+ for (ntries = 0; ntries < 1000; ntries++) {
+ if (!(AR_READ(sc, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF))
+ break;
+ DELAY(50);
+ }
+ if (ntries == 1000) {
+ DPRINTFN(DBG_RF, sc, "failed to load noisefloor values\n");
+ return;
+ }
+
+ /* Restore noisefloor values to initial (max) values. */
+ for (i = 0; i < AR_MAX_CHAINS; i++)
+ nf[i] = nf_ext[i] = -50 * 2;
+ ar5008_write_noisefloor(sc, nf, nf_ext);
+}
+#endif /* notused */
+
+#ifdef notused
+Static void
+ar5008_noisefloor_calib(struct athn_softc *sc)
+{
+
+ AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF);
+ AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
+ AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
+ AR_WRITE_BARRIER(sc);
+}
+#endif /* notused */
+
+Static void
+ar5008_do_noisefloor_calib(struct athn_softc *sc)
+{
+
+ AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
+ AR_WRITE_BARRIER(sc);
+}
+
+Static void
+ar5008_do_calib(struct athn_softc *sc)
+{
+ uint32_t mode, reg;
+ int log;
+
+ reg = AR_READ(sc, AR_PHY_TIMING_CTRL4_0);
+ log = AR_SREV_9280_10_OR_LATER(sc) ? 10 : 2;
+ reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX, log);
+ AR_WRITE(sc, AR_PHY_TIMING_CTRL4_0, reg);
+
+ if (sc->sc_cur_calib_mask & ATHN_CAL_ADC_GAIN)
+ mode = AR_PHY_CALMODE_ADC_GAIN;
+ else if (sc->sc_cur_calib_mask & ATHN_CAL_ADC_DC)
+ mode = AR_PHY_CALMODE_ADC_DC_PER;
+ else /* ATHN_CAL_IQ */
+ mode = AR_PHY_CALMODE_IQ;
+ AR_WRITE(sc, AR_PHY_CALMODE, mode);
+
+ DPRINTFN(DBG_RF, sc, "starting calibration mode=0x%x\n", mode);
+ AR_SETBITS(sc, AR_PHY_TIMING_CTRL4_0, AR_PHY_TIMING_CTRL4_DO_CAL);
+ AR_WRITE_BARRIER(sc);
+}
+
+Static void
+ar5008_next_calib(struct athn_softc *sc)
+{
+
+ /* Check if we have any calibration in progress. */
+ if (sc->sc_cur_calib_mask != 0) {
+ if (!(AR_READ(sc, AR_PHY_TIMING_CTRL4_0) &
+ AR_PHY_TIMING_CTRL4_DO_CAL)) {
+ /* Calibration completed for current sample. */
+ if (sc->sc_cur_calib_mask & ATHN_CAL_ADC_GAIN)
+ ar5008_calib_adc_gain(sc);
+ else if (sc->sc_cur_calib_mask & ATHN_CAL_ADC_DC)
+ ar5008_calib_adc_dc_off(sc);
+ else /* ATHN_CAL_IQ */
+ ar5008_calib_iq(sc);
+ }
+ }
+}
+
+Static void
+ar5008_calib_iq(struct athn_softc *sc)
+{
+ struct athn_iq_cal *cal;
+ uint32_t reg, i_coff_denom, q_coff_denom;
+ int32_t i_coff, q_coff;
+ int i, iq_corr_neg;
+
+ for (i = 0; i < AR_MAX_CHAINS; i++) {
+ cal = &sc->sc_calib.iq[i];
+
+ /* Accumulate IQ calibration measures (clear on read). */
+ cal->pwr_meas_i += AR_READ(sc, AR_PHY_CAL_MEAS_0(i));
+ cal->pwr_meas_q += AR_READ(sc, AR_PHY_CAL_MEAS_1(i));
+ cal->iq_corr_meas +=
+ (int32_t)AR_READ(sc, AR_PHY_CAL_MEAS_2(i));
+ }
+ if (!AR_SREV_9280_10_OR_LATER(sc) &&
+ ++sc->sc_calib.nsamples < AR_CAL_SAMPLES) {
+ /* Not enough samples accumulated, continue. */
+ ar5008_do_calib(sc);
+ return;
+ }
+
+ for (i = 0; i < sc->sc_nrxchains; i++) {
+ cal = &sc->sc_calib.iq[i];
+
+ if (cal->pwr_meas_q == 0)
+ continue;
+
+ if ((iq_corr_neg = cal->iq_corr_meas < 0))
+ cal->iq_corr_meas = -cal->iq_corr_meas;
+
+ i_coff_denom =
+ (cal->pwr_meas_i / 2 + cal->pwr_meas_q / 2) / 128;
+ q_coff_denom = cal->pwr_meas_q / 64;
+
+ if (i_coff_denom == 0 || q_coff_denom == 0)
+ continue; /* Prevents division by zero. */
+
+ i_coff = cal->iq_corr_meas / i_coff_denom;
+ q_coff = (cal->pwr_meas_i / q_coff_denom) - 64;
+
+ /* Negate i_coff if iq_corr_meas is positive. */
+ if (!iq_corr_neg)
+ i_coff = 0x40 - (i_coff & 0x3f);
+ if (q_coff > 15)
+ q_coff = 15;
+ else if (q_coff <= -16)
+ q_coff = -16; /* XXX Linux has a bug here? */
+
+ DPRINTFN(DBG_RF, sc, "IQ calibration for chain %d\n", i);
+ reg = AR_READ(sc, AR_PHY_TIMING_CTRL4(i));
+ reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, i_coff);
+ reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, q_coff);
+ AR_WRITE(sc, AR_PHY_TIMING_CTRL4(i), reg);
+ }
+
+ /* Apply new settings. */
+ AR_SETBITS(sc, AR_PHY_TIMING_CTRL4_0,
+ AR_PHY_TIMING_CTRL4_IQCORR_ENABLE);
+ AR_WRITE_BARRIER(sc);
+
+ /* IQ calibration done. */
+ sc->sc_cur_calib_mask &= ~ATHN_CAL_IQ;
+ memset(&sc->sc_calib, 0, sizeof(sc->sc_calib));
+}
+
+Static void
+ar5008_calib_adc_gain(struct athn_softc *sc)
+{
+ struct athn_adc_cal *cal;
+ uint32_t reg, gain_mismatch_i, gain_mismatch_q;
+ int i;
+
+ for (i = 0; i < AR_MAX_CHAINS; i++) {
+ cal = &sc->sc_calib.adc_gain[i];
+
+ /* Accumulate ADC gain measures (clear on read). */
+ cal->pwr_meas_odd_i += AR_READ(sc, AR_PHY_CAL_MEAS_0(i));
+ cal->pwr_meas_even_i += AR_READ(sc, AR_PHY_CAL_MEAS_1(i));
+ cal->pwr_meas_odd_q += AR_READ(sc, AR_PHY_CAL_MEAS_2(i));
+ cal->pwr_meas_even_q += AR_READ(sc, AR_PHY_CAL_MEAS_3(i));
+ }
+ if (!AR_SREV_9280_10_OR_LATER(sc) &&
+ ++sc->sc_calib.nsamples < AR_CAL_SAMPLES) {
+ /* Not enough samples accumulated, continue. */
+ ar5008_do_calib(sc);
+ return;
+ }
+
+ for (i = 0; i < sc->sc_nrxchains; i++) {
+ cal = &sc->sc_calib.adc_gain[i];
+
+ if (cal->pwr_meas_odd_i == 0 || cal->pwr_meas_even_q == 0)
+ continue; /* Prevents division by zero. */
+
+ gain_mismatch_i =
+ (cal->pwr_meas_even_i * 32) / cal->pwr_meas_odd_i;
+ gain_mismatch_q =
+ (cal->pwr_meas_odd_q * 32) / cal->pwr_meas_even_q;
+
+ DPRINTFN(DBG_RF, sc, "ADC gain calibration for chain %d\n", i);
+ reg = AR_READ(sc, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
+ reg = RW(reg, AR_PHY_NEW_ADC_DC_GAIN_IGAIN, gain_mismatch_i);
+ reg = RW(reg, AR_PHY_NEW_ADC_DC_GAIN_QGAIN, gain_mismatch_q);
+ AR_WRITE(sc, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), reg);
+ }
+
+ /* Apply new settings. */
+ AR_SETBITS(sc, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
+ AR_PHY_NEW_ADC_GAIN_CORR_ENABLE);
+ AR_WRITE_BARRIER(sc);
+
+ /* ADC gain calibration done. */
+ sc->sc_cur_calib_mask &= ~ATHN_CAL_ADC_GAIN;
+ memset(&sc->sc_calib, 0, sizeof(sc->sc_calib));
+}
+
+Static void
+ar5008_calib_adc_dc_off(struct athn_softc *sc)
+{
+ struct athn_adc_cal *cal;
+ int32_t dc_offset_mismatch_i, dc_offset_mismatch_q;
+ uint32_t reg;
+ int count, i;
+
+ for (i = 0; i < AR_MAX_CHAINS; i++) {
+ cal = &sc->sc_calib.adc_dc_offset[i];
+
+ /* Accumulate ADC DC offset measures (clear on read). */
+ cal->pwr_meas_odd_i += AR_READ(sc, AR_PHY_CAL_MEAS_0(i));
+ cal->pwr_meas_even_i += AR_READ(sc, AR_PHY_CAL_MEAS_1(i));
+ cal->pwr_meas_odd_q += AR_READ(sc, AR_PHY_CAL_MEAS_2(i));
+ cal->pwr_meas_even_q += AR_READ(sc, AR_PHY_CAL_MEAS_3(i));
+ }
+ if (!AR_SREV_9280_10_OR_LATER(sc) &&
+ ++sc->sc_calib.nsamples < AR_CAL_SAMPLES) {
+ /* Not enough samples accumulated, continue. */
+ ar5008_do_calib(sc);
+ return;
+ }
+
+ if (AR_SREV_9280_10_OR_LATER(sc))
+ count = (1 << (10 + 5));
+ else
+ count = (1 << ( 2 + 5)) * AR_CAL_SAMPLES;
+ for (i = 0; i < sc->sc_nrxchains; i++) {
+ cal = &sc->sc_calib.adc_dc_offset[i];
+
+ dc_offset_mismatch_i =
+ (cal->pwr_meas_even_i - cal->pwr_meas_odd_i * 2) / count;
+ dc_offset_mismatch_q =
+ (cal->pwr_meas_odd_q - cal->pwr_meas_even_q * 2) / count;
+
+ DPRINTFN(DBG_RF, sc, "ADC DC offset calibration for chain %d\n", i);
+ reg = AR_READ(sc, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
+ reg = RW(reg, AR_PHY_NEW_ADC_DC_GAIN_QDC,
+ dc_offset_mismatch_q);
+ reg = RW(reg, AR_PHY_NEW_ADC_DC_GAIN_IDC,
+ dc_offset_mismatch_i);
+ AR_WRITE(sc, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), reg);
+ }
+
+ /* Apply new settings. */
+ AR_SETBITS(sc, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
+ AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE);
+ AR_WRITE_BARRIER(sc);
+
+ /* ADC DC offset calibration done. */
+ sc->sc_cur_calib_mask &= ~ATHN_CAL_ADC_DC;
+ memset(&sc->sc_calib, 0, sizeof(sc->sc_calib));
+}
+
+PUBLIC void
+ar5008_write_txpower(struct athn_softc *sc, int16_t power[ATHN_POWER_COUNT])
+{
+
+ AR_WRITE(sc, AR_PHY_POWER_TX_RATE1,
+ (power[ATHN_POWER_OFDM18 ] & 0x3f) << 24 |
+ (power[ATHN_POWER_OFDM12 ] & 0x3f) << 16 |
+ (power[ATHN_POWER_OFDM9 ] & 0x3f) << 8 |
+ (power[ATHN_POWER_OFDM6 ] & 0x3f));
+ AR_WRITE(sc, AR_PHY_POWER_TX_RATE2,
+ (power[ATHN_POWER_OFDM54 ] & 0x3f) << 24 |
+ (power[ATHN_POWER_OFDM48 ] & 0x3f) << 16 |
+ (power[ATHN_POWER_OFDM36 ] & 0x3f) << 8 |
+ (power[ATHN_POWER_OFDM24 ] & 0x3f));
+ AR_WRITE(sc, AR_PHY_POWER_TX_RATE3,
+ (power[ATHN_POWER_CCK2_SP ] & 0x3f) << 24 |
+ (power[ATHN_POWER_CCK2_LP ] & 0x3f) << 16 |
+ (power[ATHN_POWER_XR ] & 0x3f) << 8 |
+ (power[ATHN_POWER_CCK1_LP ] & 0x3f));
+ AR_WRITE(sc, AR_PHY_POWER_TX_RATE4,
+ (power[ATHN_POWER_CCK11_SP] & 0x3f) << 24 |
+ (power[ATHN_POWER_CCK11_LP] & 0x3f) << 16 |
+ (power[ATHN_POWER_CCK55_SP] & 0x3f) << 8 |
+ (power[ATHN_POWER_CCK55_LP] & 0x3f));
+#ifndef IEEE80211_NO_HT
+ AR_WRITE(sc, AR_PHY_POWER_TX_RATE5,
+ (power[ATHN_POWER_HT20(3) ] & 0x3f) << 24 |
+ (power[ATHN_POWER_HT20(2) ] & 0x3f) << 16 |
+ (power[ATHN_POWER_HT20(1) ] & 0x3f) << 8 |
+ (power[ATHN_POWER_HT20(0) ] & 0x3f));
+ AR_WRITE(sc, AR_PHY_POWER_TX_RATE6,
+ (power[ATHN_POWER_HT20(7) ] & 0x3f) << 24 |
+ (power[ATHN_POWER_HT20(6) ] & 0x3f) << 16 |
+ (power[ATHN_POWER_HT20(5) ] & 0x3f) << 8 |
+ (power[ATHN_POWER_HT20(4) ] & 0x3f));
+ AR_WRITE(sc, AR_PHY_POWER_TX_RATE7,
+ (power[ATHN_POWER_HT40(3) ] & 0x3f) << 24 |
+ (power[ATHN_POWER_HT40(2) ] & 0x3f) << 16 |
+ (power[ATHN_POWER_HT40(1) ] & 0x3f) << 8 |
+ (power[ATHN_POWER_HT40(0) ] & 0x3f));
+ AR_WRITE(sc, AR_PHY_POWER_TX_RATE8,
+ (power[ATHN_POWER_HT40(7) ] & 0x3f) << 24 |
+ (power[ATHN_POWER_HT40(6) ] & 0x3f) << 16 |
+ (power[ATHN_POWER_HT40(5) ] & 0x3f) << 8 |
+ (power[ATHN_POWER_HT40(4) ] & 0x3f));
+ AR_WRITE(sc, AR_PHY_POWER_TX_RATE9,
+ (power[ATHN_POWER_OFDM_EXT] & 0x3f) << 24 |
+ (power[ATHN_POWER_CCK_EXT ] & 0x3f) << 16 |
+ (power[ATHN_POWER_OFDM_DUP] & 0x3f) << 8 |
+ (power[ATHN_POWER_CCK_DUP ] & 0x3f));
+#endif
+ AR_WRITE_BARRIER(sc);
+}
+
+PUBLIC void
+ar5008_set_viterbi_mask(struct athn_softc *sc, int bin)
+{
+ uint32_t mask[4], reg;
+ uint8_t m[62], p[62]; /* XXX use bit arrays? */
+ int i, bit, cur;
+
+ /* Compute pilot mask. */
+ cur = -6000;
+ for (i = 0; i < 4; i++) {
+ mask[i] = 0;
+ for (bit = 0; bit < 30; bit++) {
+ if (abs(cur - bin) < 100)
+ mask[i] |= 1 << bit;
+ cur += 100;
+ }
+ if (cur == 0) /* Skip entry "0". */
+ cur = 100;
+ }
+ /* Write entries from -6000 to -3100. */
+ AR_WRITE(sc, AR_PHY_TIMING7, mask[0]);
+ AR_WRITE(sc, AR_PHY_TIMING9, mask[0]);
+ /* Write entries from -3000 to -100. */
+ AR_WRITE(sc, AR_PHY_TIMING8, mask[1]);
+ AR_WRITE(sc, AR_PHY_TIMING10, mask[1]);
+ /* Write entries from 100 to 3000. */
+ AR_WRITE(sc, AR_PHY_PILOT_MASK_01_30, mask[2]);
+ AR_WRITE(sc, AR_PHY_CHANNEL_MASK_01_30, mask[2]);
+ /* Write entries from 3100 to 6000. */
+ AR_WRITE(sc, AR_PHY_PILOT_MASK_31_60, mask[3]);
+ AR_WRITE(sc, AR_PHY_CHANNEL_MASK_31_60, mask[3]);
+
+ /* Compute viterbi mask. */
+ for (cur = 6100; cur >= 0; cur -= 100)
+ p[+cur / 100] = abs(cur - bin) < 75;
+ for (cur = -100; cur >= -6100; cur -= 100)
+ m[-cur / 100] = abs(cur - bin) < 75;
+
+ /* Write viterbi mask (XXX needs to be reworked). */
+ reg =
+ m[46] << 30 | m[47] << 28 | m[48] << 26 | m[49] << 24 |
+ m[50] << 22 | m[51] << 20 | m[52] << 18 | m[53] << 16 |
+ m[54] << 14 | m[55] << 12 | m[56] << 10 | m[57] << 8 |
+ m[58] << 6 | m[59] << 4 | m[60] << 2 | m[61] << 0;
+ AR_WRITE(sc, AR_PHY_BIN_MASK_1, reg);
+ AR_WRITE(sc, AR_PHY_VIT_MASK2_M_46_61, reg);
+
+ /* XXX m[48] should be m[38] ? */
+ reg = m[31] << 28 | m[32] << 26 | m[33] << 24 |
+ m[34] << 22 | m[35] << 20 | m[36] << 18 | m[37] << 16 |
+ m[48] << 14 | m[39] << 12 | m[40] << 10 | m[41] << 8 |
+ m[42] << 6 | m[43] << 4 | m[44] << 2 | m[45] << 0;
+ AR_WRITE(sc, AR_PHY_BIN_MASK_2, reg);
+ AR_WRITE(sc, AR_PHY_VIT_MASK2_M_31_45, reg);
+
+ /* XXX This one is weird too. */
+ reg =
+ m[16] << 30 | m[16] << 28 | m[18] << 26 | m[18] << 24 |
+ m[20] << 22 | m[20] << 20 | m[22] << 18 | m[22] << 16 |
+ m[24] << 14 | m[24] << 12 | m[25] << 10 | m[26] << 8 |
+ m[27] << 6 | m[28] << 4 | m[29] << 2 | m[30] << 0;
+ AR_WRITE(sc, AR_PHY_BIN_MASK_3, reg);
+ AR_WRITE(sc, AR_PHY_VIT_MASK2_M_16_30, reg);
+
+ reg =
+ m[ 0] << 30 | m[ 1] << 28 | m[ 2] << 26 | m[ 3] << 24 |
+ m[ 4] << 22 | m[ 5] << 20 | m[ 6] << 18 | m[ 7] << 16 |
+ m[ 8] << 14 | m[ 9] << 12 | m[10] << 10 | m[11] << 8 |
+ m[12] << 6 | m[13] << 4 | m[14] << 2 | m[15] << 0;
+ AR_WRITE(sc, AR_PHY_MASK_CTL, reg);
+ AR_WRITE(sc, AR_PHY_VIT_MASK2_M_00_15, reg);
+
+ reg = p[15] << 28 | p[14] << 26 | p[13] << 24 |
+ p[12] << 22 | p[11] << 20 | p[10] << 18 | p[ 9] << 16 |
+ p[ 8] << 14 | p[ 7] << 12 | p[ 6] << 10 | p[ 5] << 8 |
+ p[ 4] << 6 | p[ 3] << 4 | p[ 2] << 2 | p[ 1] << 0;
+ AR_WRITE(sc, AR_PHY_BIN_MASK2_1, reg);
+ AR_WRITE(sc, AR_PHY_VIT_MASK2_P_15_01, reg);
+
+ reg = p[30] << 28 | p[29] << 26 | p[28] << 24 |
+ p[27] << 22 | p[26] << 20 | p[25] << 18 | p[24] << 16 |
+ p[23] << 14 | p[22] << 12 | p[21] << 10 | p[20] << 8 |
+ p[19] << 6 | p[18] << 4 | p[17] << 2 | p[16] << 0;
+ AR_WRITE(sc, AR_PHY_BIN_MASK2_2, reg);
+ AR_WRITE(sc, AR_PHY_VIT_MASK2_P_30_16, reg);
+
+ reg = p[45] << 28 | p[44] << 26 | p[43] << 24 |
+ p[42] << 22 | p[41] << 20 | p[40] << 18 | p[39] << 16 |
+ p[38] << 14 | p[37] << 12 | p[36] << 10 | p[35] << 8 |
+ p[34] << 6 | p[33] << 4 | p[32] << 2 | p[31] << 0;
+ AR_WRITE(sc, AR_PHY_BIN_MASK2_3, reg);
+ AR_WRITE(sc, AR_PHY_VIT_MASK2_P_45_31, reg);
+
+ reg =
+ p[61] << 30 | p[60] << 28 | p[59] << 26 | p[58] << 24 |
+ p[57] << 22 | p[56] << 20 | p[55] << 18 | p[54] << 16 |
+ p[53] << 14 | p[52] << 12 | p[51] << 10 | p[50] << 8 |
+ p[49] << 6 | p[48] << 4 | p[47] << 2 | p[46] << 0;
+ AR_WRITE(sc, AR_PHY_BIN_MASK2_4, reg);
+ AR_WRITE(sc, AR_PHY_VIT_MASK2_P_61_46, reg);
+ AR_WRITE_BARRIER(sc);
+}
+
+Static void
+ar5008_hw_init(struct athn_softc *sc, struct ieee80211_channel *c,
+ struct ieee80211_channel *extc)
+{
+ struct athn_ops *ops = &sc->sc_ops;
+ const struct athn_ini *ini = sc->sc_ini;
+ const uint32_t *pvals;
+ uint32_t reg;
+ int i;
+
+ AR_WRITE(sc, AR_PHY(0), 0x00000007);
+ AR_WRITE(sc, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
+
+ if (!AR_SINGLE_CHIP(sc))
+ ar5416_reset_addac(sc, c);
+
+ AR_WRITE(sc, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
+
+ /* First initialization step (depends on channel band/bandwidth). */
+#ifndef IEEE80211_NO_HT
+ if (extc != NULL) {
+ if (IEEE80211_IS_CHAN_2GHZ(c))
+ pvals = ini->vals_2g40;
+ else
+ pvals = ini->vals_5g40;
+ }
+ else
+#endif
+ {
+ if (IEEE80211_IS_CHAN_2GHZ(c))
+ pvals = ini->vals_2g20;
+ else
+ pvals = ini->vals_5g20;
+ }
+ DPRINTFN(DBG_INIT, sc, "writing modal init vals\n");
+ for (i = 0; i < ini->nregs; i++) {
+ uint32_t val = pvals[i];
+
+ /* Fix AR_AN_TOP2 initialization value if required. */
+ if (ini->regs[i] == AR_AN_TOP2 &&
+ (sc->sc_flags & ATHN_FLAG_AN_TOP2_FIXUP))
+ val &= ~AR_AN_TOP2_PWDCLKIND;
+ AR_WRITE(sc, ini->regs[i], val);
+ if (AR_IS_ANALOG_REG(ini->regs[i])) {
+ AR_WRITE_BARRIER(sc);
+ DELAY(100);
+ }
+ if ((i & 0x1f) == 0)
+ DELAY(1);
+ }
+ AR_WRITE_BARRIER(sc);
+
+ if (sc->sc_rx_gain != NULL)
+ ar9280_reset_rx_gain(sc, c);
+ if (sc->sc_tx_gain != NULL)
+ ar9280_reset_tx_gain(sc, c);
+
+ if (AR_SREV_9271_10(sc)) {
+ AR_WRITE(sc, AR_PHY(68), 0x30002311);
+ AR_WRITE(sc, AR_PHY_RF_CTL3, 0x0a020001);
+ }
+ AR_WRITE_BARRIER(sc);
+
+ /* Second initialization step (common to all channels). */
+ DPRINTFN(DBG_INIT, sc, "writing common init vals\n");
+ for (i = 0; i < ini->ncmregs; i++) {
+ AR_WRITE(sc, ini->cmregs[i], ini->cmvals[i]);
+ if (AR_IS_ANALOG_REG(ini->cmregs[i])) {
+ AR_WRITE_BARRIER(sc);
+ DELAY(100);
+ }
+ if ((i & 0x1f) == 0)
+ DELAY(1);
+ }
+ AR_WRITE_BARRIER(sc);
+
+ if (!AR_SINGLE_CHIP(sc))
+ ar5416_reset_bb_gain(sc, c);
+
+ if (IEEE80211_IS_CHAN_5GHZ(c) &&
+ (sc->sc_flags & ATHN_FLAG_FAST_PLL_CLOCK)) {
+ /* Update modal values for fast PLL clock. */
+#ifndef IEEE80211_NO_HT
+ if (extc != NULL)
+ pvals = ini->fastvals_5g40;
+ else
+#endif
+ pvals = ini->fastvals_5g20;
+ DPRINTFN(DBG_INIT, sc, "writing fast pll clock init vals\n");
+ for (i = 0; i < ini->nfastregs; i++) {
+ AR_WRITE(sc, ini->fastregs[i], pvals[i]);
+ if (AR_IS_ANALOG_REG(ini->fastregs[i])) {
+ AR_WRITE_BARRIER(sc);
+ DELAY(100);
+ }
+ if ((i & 0x1f) == 0)
+ DELAY(1);
+ }
+ }
+
+ /*
+ * Set the RX_ABORT and RX_DIS bits to prevent frames with corrupted
+ * descriptor status.
+ */
+ AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT);
+
+ /* Hardware workarounds for occasional Rx data corruption. */
+ if (AR_SREV_9280_10_OR_LATER(sc)) {
+ reg = AR_READ(sc, AR_PCU_MISC_MODE2);
+ if (!AR_SREV_9271(sc))
+ reg &= ~AR_PCU_MISC_MODE2_HWWAR1;
+ if (AR_SREV_9287_10_OR_LATER(sc))
+ reg &= ~AR_PCU_MISC_MODE2_HWWAR2;
+ AR_WRITE(sc, AR_PCU_MISC_MODE2, reg);
+
+ }
+ else if (AR_SREV_5416_20_OR_LATER(sc)) {
+ /* Disable baseband clock gating. */
+ AR_WRITE(sc, AR_PHY(651), 0x11);
+
+ if (AR_SREV_9160(sc)) {
+ /* Disable RIFS search to fix baseband hang. */
+ AR_CLRBITS(sc, AR_PHY_HEAVY_CLIP_FACTOR_RIFS,
+ AR_PHY_RIFS_INIT_DELAY_M);
+ }
+ }
+ AR_WRITE_BARRIER(sc);
+
+ ar5008_set_phy(sc, c, extc);
+ ar5008_init_chains(sc);
+
+ if (sc->sc_flags & ATHN_FLAG_OLPC) {
+ extern int ticks;
+ sc->sc_olpc_ticks = ticks;
+ ops->olpc_init(sc);
+ }
+
+ ops->set_txpower(sc, c, extc);
+
+ if (!AR_SINGLE_CHIP(sc))
+ ar5416_rf_reset(sc, c);
+}
+
+Static uint8_t
+ar5008_get_vpd(uint8_t pwr, const uint8_t *pwrPdg, const uint8_t *vpdPdg,
+ int nicepts)
+{
+ uint8_t vpd;
+ int i, lo, hi;
+
+ for (i = 0; i < nicepts; i++)
+ if (pwrPdg[i] > pwr)
+ break;
+ hi = i;
+ lo = hi - 1;
+ if (lo == -1)
+ lo = hi;
+ else if (hi == nicepts)
+ hi = lo;
+
+ vpd = athn_interpolate(pwr, pwrPdg[lo], vpdPdg[lo],
+ pwrPdg[hi], vpdPdg[hi]);
+ return vpd;
+}
+
+PUBLIC void
+ar5008_get_pdadcs(struct athn_softc *sc, uint8_t fbin,
+ struct athn_pier *lopier, struct athn_pier *hipier, int nxpdgains,
+ int nicepts, uint8_t overlap, uint8_t *boundaries, uint8_t *pdadcs)
+{
+#define DB(x) ((x) / 2) /* Convert half dB to dB. */
+ uint8_t minpwr[AR_PD_GAINS_IN_MASK], maxpwr[AR_PD_GAINS_IN_MASK];
+ uint8_t vpd[AR_MAX_PWR_RANGE_IN_HALF_DB], pwr;
+ uint8_t lovpd, hivpd, boundary;
+ int16_t ss, delta, vpdstep, val;
+ int i, j, npdadcs, nvpds, maxidx, tgtidx;
+
+ /* Compute min and max power in half dB for each pdGain. */
+ for (i = 0; i < nxpdgains; i++) {
+ minpwr[i] = MAX(lopier->pwr[i][0], hipier->pwr[i][0]);
+ maxpwr[i] = MIN(lopier->pwr[i][nicepts - 1],
+ hipier->pwr[i][nicepts - 1]);
+ }
+
+ /* Fill phase domain analog-to-digital converter (PDADC) table. */
+ npdadcs = 0;
+ for (i = 0; i < nxpdgains; i++) {
+ if (i != nxpdgains - 1)
+ boundaries[i] = DB(maxpwr[i] + minpwr[i + 1]) / 2;
+ else
+ boundaries[i] = DB(maxpwr[i]);
+ if (boundaries[i] > AR_MAX_RATE_POWER)
+ boundaries[i] = AR_MAX_RATE_POWER;
+
+ if (i == 0 && !AR_SREV_5416_20_OR_LATER(sc)) {
+ /* Fix the gain delta (AR5416 1.0 only). */
+ delta = boundaries[0] - 23;
+ boundaries[0] = 23;
+ }
+ else
+ delta = 0;
+
+ /* Find starting index for this pdGain. */
+ if (i != 0) {
+ ss = boundaries[i - 1] - DB(minpwr[i]) -
+ overlap + 1 + delta;
+ }
+ else if (AR_SREV_9280_10_OR_LATER(sc))
+ ss = -DB(minpwr[i]);
+ else
+ ss = 0;
+
+ /* Compute Vpd table for this pdGain. */
+ nvpds = DB(maxpwr[i] - minpwr[i]) + 1;
+ memset(vpd, 0, sizeof(vpd));
+ pwr = minpwr[i];
+ for (j = 0; j < nvpds; j++) {
+ /* Get lower and higher Vpd. */
+ lovpd = ar5008_get_vpd(pwr, lopier->pwr[i],
+ lopier->vpd[i], nicepts);
+ hivpd = ar5008_get_vpd(pwr, hipier->pwr[i],
+ hipier->vpd[i], nicepts);
+
+ /* Interpolate the final Vpd. */
+ vpd[j] = athn_interpolate(fbin,
+ lopier->fbin, lovpd, hipier->fbin, hivpd);
+
+ pwr += 2; /* In half dB. */
+ }
+
+ /* Extrapolate data for ss < 0. */
+ if (vpd[1] > vpd[0])
+ vpdstep = vpd[1] - vpd[0];
+ else
+ vpdstep = 1;
+ while (ss < 0 && npdadcs < AR_NUM_PDADC_VALUES - 1) {
+ val = vpd[0] + ss * vpdstep;
+ pdadcs[npdadcs++] = MAX(val, 0);
+ ss++;
+ }
+
+ tgtidx = boundaries[i] + overlap - DB(minpwr[i]);
+ maxidx = MIN(tgtidx, nvpds);
+ while (ss < maxidx && npdadcs < AR_NUM_PDADC_VALUES - 1)
+ pdadcs[npdadcs++] = vpd[ss++];
+
+ if (tgtidx < maxidx)
+ continue;
+
+ /* Extrapolate data for maxidx <= ss <= tgtidx. */
+ if (vpd[nvpds - 1] > vpd[nvpds - 2])
+ vpdstep = vpd[nvpds - 1] - vpd[nvpds - 2];
+ else
+ vpdstep = 1;
+ while (ss <= tgtidx && npdadcs < AR_NUM_PDADC_VALUES - 1) {
+ val = vpd[nvpds - 1] + (ss - maxidx + 1) * vpdstep;
+ pdadcs[npdadcs++] = MIN(val, 255);
+ ss++;
+ }
+ }
+
+ /* Fill remaining PDADC and boundaries entries. */
+ if (AR_SREV_9285(sc))
+ boundary = AR9285_PD_GAIN_BOUNDARY_DEFAULT;
+ else /* Fill with latest. */
+ boundary = boundaries[nxpdgains - 1];
+
+ for (; nxpdgains < AR_PD_GAINS_IN_MASK; nxpdgains++)
+ boundaries[nxpdgains] = boundary;
+
+ for (; npdadcs < AR_NUM_PDADC_VALUES; npdadcs++)
+ pdadcs[npdadcs] = pdadcs[npdadcs - 1];
+#undef DB
+}
+
+PUBLIC void
+ar5008_get_lg_tpow(struct athn_softc *sc, struct ieee80211_channel *c,
+ uint8_t ctl, const struct ar_cal_target_power_leg *tgt, int nchans,
+ uint8_t tpow[4])
+{
+ uint8_t fbin;
+ int i, lo, hi;
+
+ /* Find interval (lower and upper indices). */
+ fbin = athn_chan2fbin(c);
+ for (i = 0; i < nchans; i++) {
+ if (tgt[i].bChannel == AR_BCHAN_UNUSED ||
+ tgt[i].bChannel > fbin)
+ break;
+ }
+ hi = i;
+ lo = hi - 1;
+ if (lo == -1)
+ lo = hi;
+ else if (hi == nchans || tgt[hi].bChannel == AR_BCHAN_UNUSED)
+ hi = lo;
+
+ /* Interpolate values. */
+ for (i = 0; i < 4; i++) {
+ tpow[i] = athn_interpolate(fbin,
+ tgt[lo].bChannel, tgt[lo].tPow2x[i],
+ tgt[hi].bChannel, tgt[hi].tPow2x[i]);
+ }
+ /* XXX Apply conformance testing limit. */
+}
+
+#ifndef IEEE80211_NO_HT
+PUBLIC void
+ar5008_get_ht_tpow(struct athn_softc *sc, struct ieee80211_channel *c,
+ uint8_t ctl, const struct ar_cal_target_power_ht *tgt, int nchans,
+ uint8_t tpow[8])
+{
+ uint8_t fbin;
+ int i, lo, hi;
+
+ /* Find interval (lower and upper indices). */
+ fbin = athn_chan2fbin(c);
+ for (i = 0; i < nchans; i++) {
+ if (tgt[i].bChannel == AR_BCHAN_UNUSED ||
+ tgt[i].bChannel > fbin)
+ break;
+ }
+ hi = i;
+ lo = hi - 1;
+ if (lo == -1)
+ lo = hi;
+ else if (hi == nchans || tgt[hi].bChannel == AR_BCHAN_UNUSED)
+ hi = lo;
+
+ /* Interpolate values. */
+ for (i = 0; i < 8; i++) {
+ tpow[i] = athn_interpolate(fbin,
+ tgt[lo].bChannel, tgt[lo].tPow2x[i],
+ tgt[hi].bChannel, tgt[hi].tPow2x[i]);
+ }
+ /* XXX Apply conformance testing limit. */
+}
+#endif
+
+/*
+ * Adaptive noise immunity.
+ */
+Static void
+ar5008_set_noise_immunity_level(struct athn_softc *sc, int level)
+{
+ int high = level == 4;
+ uint32_t reg;
+
+ reg = AR_READ(sc, AR_PHY_DESIRED_SZ);
+ reg = RW(reg, AR_PHY_DESIRED_SZ_TOT_DES, high ? -62 : -55);
+ AR_WRITE(sc, AR_PHY_DESIRED_SZ, reg);
+
+ reg = AR_READ(sc, AR_PHY_AGC_CTL1);
+ reg = RW(reg, AR_PHY_AGC_CTL1_COARSE_LOW, high ? -70 : -64);
+ reg = RW(reg, AR_PHY_AGC_CTL1_COARSE_HIGH, high ? -12 : -14);
+ AR_WRITE(sc, AR_PHY_AGC_CTL1, reg);
+
+ reg = AR_READ(sc, AR_PHY_FIND_SIG);
+ reg = RW(reg, AR_PHY_FIND_SIG_FIRPWR, high ? -80 : -78);
+ AR_WRITE(sc, AR_PHY_FIND_SIG, reg);
+
+ AR_WRITE_BARRIER(sc);
+}
+
+Static void
+ar5008_enable_ofdm_weak_signal(struct athn_softc *sc)
+{
+ uint32_t reg;
+
+ reg = AR_READ(sc, AR_PHY_SFCORR_LOW);
+ reg = RW(reg, AR_PHY_SFCORR_LOW_M1_THRESH_LOW, 50);
+ reg = RW(reg, AR_PHY_SFCORR_LOW_M2_THRESH_LOW, 40);
+ reg = RW(reg, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, 48);
+ AR_WRITE(sc, AR_PHY_SFCORR_LOW, reg);
+
+ reg = AR_READ(sc, AR_PHY_SFCORR);
+ reg = RW(reg, AR_PHY_SFCORR_M1_THRESH, 77);
+ reg = RW(reg, AR_PHY_SFCORR_M2_THRESH, 64);
+ reg = RW(reg, AR_PHY_SFCORR_M2COUNT_THR, 16);
+ AR_WRITE(sc, AR_PHY_SFCORR, reg);
+
+ reg = AR_READ(sc, AR_PHY_SFCORR_EXT);
+ reg = RW(reg, AR_PHY_SFCORR_EXT_M1_THRESH_LOW, 50);
+ reg = RW(reg, AR_PHY_SFCORR_EXT_M2_THRESH_LOW, 40);
+ reg = RW(reg, AR_PHY_SFCORR_EXT_M1_THRESH, 77);
+ reg = RW(reg, AR_PHY_SFCORR_EXT_M2_THRESH, 64);
+ AR_WRITE(sc, AR_PHY_SFCORR_EXT, reg);
+
+ AR_SETBITS(sc, AR_PHY_SFCORR_LOW,
+ AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
+ AR_WRITE_BARRIER(sc);
+}
+
+Static void
+ar5008_disable_ofdm_weak_signal(struct athn_softc *sc)
+{
+ uint32_t reg;
+
+ reg = AR_READ(sc, AR_PHY_SFCORR_LOW);
+ reg = RW(reg, AR_PHY_SFCORR_LOW_M1_THRESH_LOW, 127);
+ reg = RW(reg, AR_PHY_SFCORR_LOW_M2_THRESH_LOW, 127);
+ reg = RW(reg, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, 63);
+ AR_WRITE(sc, AR_PHY_SFCORR_LOW, reg);
+
+ reg = AR_READ(sc, AR_PHY_SFCORR);
+ reg = RW(reg, AR_PHY_SFCORR_M1_THRESH, 127);
+ reg = RW(reg, AR_PHY_SFCORR_M2_THRESH, 127);
+ reg = RW(reg, AR_PHY_SFCORR_M2COUNT_THR, 31);
+ AR_WRITE(sc, AR_PHY_SFCORR, reg);
+
+ reg = AR_READ(sc, AR_PHY_SFCORR_EXT);
+ reg = RW(reg, AR_PHY_SFCORR_EXT_M1_THRESH_LOW, 127);
+ reg = RW(reg, AR_PHY_SFCORR_EXT_M2_THRESH_LOW, 127);
+ reg = RW(reg, AR_PHY_SFCORR_EXT_M1_THRESH, 127);
+ reg = RW(reg, AR_PHY_SFCORR_EXT_M2_THRESH, 127);
+ AR_WRITE(sc, AR_PHY_SFCORR_EXT, reg);
+
+ AR_CLRBITS(sc, AR_PHY_SFCORR_LOW,
+ AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
+ AR_WRITE_BARRIER(sc);
+}
+
+Static void
+ar5008_set_cck_weak_signal(struct athn_softc *sc, int high)
+{
+ uint32_t reg;
+
+ reg = AR_READ(sc, AR_PHY_CCK_DETECT);
+ reg = RW(reg, AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK, high ? 6 : 8);
+ AR_WRITE(sc, AR_PHY_CCK_DETECT, reg);
+ AR_WRITE_BARRIER(sc);
+}
+
+Static void
+ar5008_set_firstep_level(struct athn_softc *sc, int level)
+{
+ uint32_t reg;
+
+ reg = AR_READ(sc, AR_PHY_FIND_SIG);
+ reg = RW(reg, AR_PHY_FIND_SIG_FIRSTEP, level * 4);
+ AR_WRITE(sc, AR_PHY_FIND_SIG, reg);
+ AR_WRITE_BARRIER(sc);
+}
+
+Static void
+ar5008_set_spur_immunity_level(struct athn_softc *sc, int level)
+{
+ uint32_t reg;
+
+ reg = AR_READ(sc, AR_PHY_TIMING5);
+ reg = RW(reg, AR_PHY_TIMING5_CYCPWR_THR1, (level + 1) * 2);
+ AR_WRITE(sc, AR_PHY_TIMING5, reg);
+ AR_WRITE_BARRIER(sc);
+}
diff --git a/sys/dev/ic/arn5008.h b/sys/dev/ic/arn5008.h
new file mode 100644
index 00000000000..2cb91e2da1a
--- /dev/null
+++ b/sys/dev/ic/arn5008.h
@@ -0,0 +1,45 @@
+/* $NetBSD: arn5008.h,v 1.1 2013/03/30 02:53:00 christos Exp $ */
+/*
+ * Copyright (c) 2001, 2004 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _IF_ARN5008_H_
+#define _IF_ARN5008_H_
+
+#include <dev/ic/arn5008reg.h>
+
+int ar5008_attach(struct athn_softc *);
+void ar5008_write_txpower(struct athn_softc *, int16_t power[]);
+void ar5008_set_viterbi_mask(struct athn_softc *, int);
+void ar5008_get_pdadcs(struct athn_softc *, uint8_t, struct athn_pier *,
+ struct athn_pier *, int, int, uint8_t, uint8_t *, uint8_t *);
+
+void ar5008_get_ht_tpow(struct athn_softc *, struct ieee80211_channel *,
+ uint8_t, const struct ar_cal_target_power_ht *, int, uint8_t[]);
+void ar5008_get_lg_tpow(struct athn_softc *, struct ieee80211_channel *,
+ uint8_t, const struct ar_cal_target_power_leg *, int, uint8_t[]);
+
+
+#endif /* _IF_ARN5008_H_ */
diff --git a/sys/dev/ic/arn5008reg.h b/sys/dev/ic/arn5008reg.h
new file mode 100644
index 00000000000..43c98eaa8e5
--- /dev/null
+++ b/sys/dev/ic/arn5008reg.h
@@ -0,0 +1,1028 @@
+/* $NetBSD: arn5008reg.h,v 1.1 2013/03/30 02:53:00 christos Exp $ */
+/* $OpenBSD: ar5008reg.h,v 1.3 2010/12/31 17:50:48 damien Exp $ */
+
+/*-
+ * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr>
+ * Copyright (c) 2008-2009 Atheros Communications Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _ARN5008REG_H_
+#define _ARN5008REG_H_
+
+/*
+ * MAC registers.
+ */
+#define AR_ISR_S2_S 0x00cc
+#define AR_ISR_S3_S 0x00d0
+#define AR_ISR_S4_S 0x00d4
+#define AR_ISR_S5_S 0x00d8
+#define AR_GPIO_IN_OUT 0x4048
+#define AR_GPIO_OE_OUT 0x404c
+#define AR_GPIO_INTR_POL 0x4050
+#define AR_GPIO_INPUT_EN_VAL 0x4054
+#define AR_GPIO_INPUT_MUX1 0x4058
+#define AR_GPIO_INPUT_MUX2 0x405c
+#define AR_GPIO_OUTPUT_MUX(i) (0x4060 + (i) * 4)
+#define AR_INPUT_STATE 0x406c
+#define AR_EEPROM_STATUS_DATA 0x407c
+#define AR_OBS 0x4080
+#define AR_GPIO_PDPU 0x4088
+#define AR_PCIE_MSI 0x4094
+
+/*
+ * Analog registers.
+ */
+#define AR_IS_ANALOG_REG(reg) ((reg) >= 0x7800 && (reg) <= 0x78b4)
+#define AR_AN_RF2G1_CH0 0x7810
+#define AR_AN_RF5G1_CH0 0x7818
+#define AR_AN_RF2G1_CH1 0x7834
+#define AR_AN_RF5G1_CH1 0x783c
+#define AR_AN_SYNTH9 0x7868
+#define AR_AN_TOP1 0x7890
+#define AR_AN_TOP2 0x7894
+
+/*
+ * PHY registers.
+ */
+#define AR_PHY_BASE 0x9800
+#define AR_PHY(i) (AR_PHY_BASE + (i) * 4)
+#define AR_PHY_TEST 0x9800
+#define AR_PHY_TURBO 0x9804
+#define AR_PHY_TEST2 0x9808
+#define AR_PHY_TIMING2 0x9810
+#define AR_PHY_TIMING3 0x9814
+#define AR_PHY_CHIP_ID 0x9818
+#define AR_PHY_ACTIVE 0x981c
+#define AR_PHY_RF_CTL2 0x9824
+#define AR_PHY_RF_CTL3 0x9828
+#define AR_PHY_ADC_CTL 0x982c
+#define AR_PHY_ADC_SERIAL_CTL 0x9830
+#define AR_PHY_RF_CTL4 0x9834
+#define AR_PHY_TSTDAC_CONST 0x983c
+#define AR_PHY_SETTLING 0x9844
+#define AR_PHY_RXGAIN 0x9848
+#define AR_PHY_DESIRED_SZ 0x9850
+#define AR_PHY_FIND_SIG 0x9858
+#define AR_PHY_AGC_CTL1 0x985c
+#define AR_PHY_AGC_CONTROL 0x9860
+#define AR_PHY_CCA(i) (0x9864 + (i) * 0x1000)
+#define AR_PHY_SFCORR 0x9868
+#define AR_PHY_SFCORR_LOW 0x986c
+#define AR_PHY_SLEEP_CTR_CONTROL 0x9870
+#define AR_PHY_SLEEP_CTR_LIMIT 0x9874
+#define AR_PHY_SLEEP_SCAL 0x9878
+#define AR_PHY_PLL_CTL 0x987c
+#define AR_PHY_BIN_MASK_1 0x9900
+#define AR_PHY_BIN_MASK_2 0x9904
+#define AR_PHY_BIN_MASK_3 0x9908
+#define AR_PHY_MASK_CTL 0x990c
+#define AR_PHY_RX_DELAY 0x9914
+#define AR_PHY_SEARCH_START_DELAY 0x9918
+#define AR_PHY_TIMING_CTRL4_0 0x9920
+#define AR_PHY_TIMING_CTRL4(i) (0x9920 + (i) * 0x1000)
+#define AR_PHY_TIMING5 0x9924
+#define AR_PHY_POWER_TX_RATE1 0x9934
+#define AR_PHY_POWER_TX_RATE2 0x9938
+#define AR_PHY_POWER_TX_RATE_MAX 0x993c
+#define AR_PHY_RADAR_EXT 0x9940
+#define AR_PHY_FRAME_CTL 0x9944
+#define AR_PHY_SPUR_REG 0x994c
+#define AR_PHY_RADAR_0 0x9954
+#define AR_PHY_RADAR_1 0x9958
+#define AR_PHY_SWITCH_CHAIN_0 0x9960
+#define AR_PHY_SWITCH_COM 0x9964
+#define AR_PHY_SIGMA_DELTA 0x996c
+#define AR_PHY_RESTART 0x9970
+#define AR_PHY_RFBUS_REQ 0x997c
+#define AR_PHY_TIMING7 0x9980
+#define AR_PHY_TIMING8 0x9984
+#define AR_PHY_BIN_MASK2_1 0x9988
+#define AR_PHY_BIN_MASK2_2 0x998c
+#define AR_PHY_BIN_MASK2_3 0x9990
+#define AR_PHY_BIN_MASK2_4 0x9994
+#define AR_PHY_TIMING9 0x9998
+#define AR_PHY_TIMING10 0x999c
+#define AR_PHY_TIMING11 0x99a0
+#define AR_PHY_RX_CHAINMASK 0x99a4
+#define AR_PHY_MULTICHAIN_GAIN_CTL 0x99ac
+#define AR_PHY_NEW_ADC_DC_GAIN_CORR(i) (0x99b4 + (i) * 0x1000)
+#define AR_PHY_EXT_CCA0 0x99b8
+#define AR_PHY_EXT_CCA(i) (0x99bc + (i) * 0x1000)
+#define AR_PHY_SFCORR_EXT 0x99c0
+#define AR_PHY_HALFGI 0x99d0
+#define AR_PHY_CHANNEL_MASK_01_30 0x99d4
+#define AR_PHY_CHANNEL_MASK_31_60 0x99d8
+#define AR_PHY_CHAN_INFO_MEMORY 0x99dc
+#define AR_PHY_HEAVY_CLIP_ENABLE 0x99e0
+#define AR_PHY_HEAVY_CLIP_FACTOR_RIFS 0x99ec
+#define AR_PHY_CALMODE 0x99f0
+#define AR_PHY_REFCLKDLY 0x99f4
+#define AR_PHY_REFCLKPD 0x99f8
+#define AR_PHY_BB_RFGAIN(i) (0x9a00 + (i) * 4)
+#define AR_PHY_CAL_MEAS_0(i) (0x9c10 + (i) * 0x1000)
+#define AR_PHY_CAL_MEAS_1(i) (0x9c14 + (i) * 0x1000)
+#define AR_PHY_CAL_MEAS_2(i) (0x9c18 + (i) * 0x1000)
+#define AR_PHY_CAL_MEAS_3(i) (0x9c1c + (i) * 0x1000)
+#define AR_PHY_CURRENT_RSSI 0x9c1c
+#define AR_PHY_RFBUS_GRANT 0x9c20
+#define AR9280_PHY_CURRENT_RSSI 0x9c3c
+#define AR_PHY_CHAN_INFO_GAIN_DIFF 0x9cf4
+#define AR_PHY_CHAN_INFO_GAIN 0x9cfc
+#define AR_PHY_MODE 0xa200
+#define AR_PHY_CCK_TX_CTRL 0xa204
+#define AR_PHY_CCK_DETECT 0xa208
+#define AR_PHY_GAIN_2GHZ 0xa20c
+#define AR_PHY_CCK_RXCTRL4 0xa21c
+#define AR_PHY_DAG_CTRLCCK 0xa228
+#define AR_PHY_FORCE_CLKEN_CCK 0xa22c
+#define AR_PHY_POWER_TX_RATE3 0xa234
+#define AR_PHY_POWER_TX_RATE4 0xa238
+#define AR_PHY_SCRM_SEQ_XR 0xa23c
+#define AR_PHY_HEADER_DETECT_XR 0xa240
+#define AR_PHY_CHIRP_DETECTED_XR 0xa244
+#define AR_PHY_BLUETOOTH 0xa254
+#define AR_PHY_TPCRG1 0xa258
+#define AR_PHY_TX_PWRCTRL4 0xa264
+#define AR_PHY_ANALOG_SWAP 0xa268
+#define AR_PHY_TPCRG5 0xa26c
+#define AR_PHY_TX_PWRCTRL6_0 0xa270
+#define AR_PHY_TX_PWRCTRL7 0xa274
+#define AR_PHY_TX_PWRCTRL9 0xa27c
+#define AR_PHY_PDADC_TBL_BASE 0xa280
+#define AR_PHY_TX_GAIN_TBL(i) (0xa300 + (i) * 4)
+#define AR_PHY_CL_CAL_CTL 0xa358
+#define AR_PHY_CLC_TBL(i) (0xa35c + (i) * 4)
+#define AR_PHY_POWER_TX_RATE5 0xa38c
+#define AR_PHY_POWER_TX_RATE6 0xa390
+#define AR_PHY_CH0_TX_PWRCTRL11 0xa398
+#define AR_PHY_CAL_CHAINMASK 0xa39c
+#define AR_PHY_VIT_MASK2_M_46_61 0xa3a0
+#define AR_PHY_VIT_MASK2_M_31_45 0xa3a4
+#define AR_PHY_VIT_MASK2_M_16_30 0xa3a8
+#define AR_PHY_VIT_MASK2_M_00_15 0xa3ac
+#define AR_PHY_PILOT_MASK_01_30 0xa3b0
+#define AR_PHY_PILOT_MASK_31_60 0xa3b4
+#define AR_PHY_VIT_MASK2_P_15_01 0xa3b8
+#define AR_PHY_VIT_MASK2_P_30_16 0xa3bc
+#define AR_PHY_VIT_MASK2_P_45_31 0xa3c0
+#define AR_PHY_VIT_MASK2_P_61_46 0xa3c4
+#define AR_PHY_POWER_TX_SUB 0xa3c8
+#define AR_PHY_POWER_TX_RATE7 0xa3cc
+#define AR_PHY_POWER_TX_RATE8 0xa3d0
+#define AR_PHY_POWER_TX_RATE9 0xa3d4
+#define AR_PHY_XPA_CFG 0xa3d8
+#define AR_PHY_TX_PWRCTRL6_1 0xb270
+#define AR_PHY_CH1_TX_PWRCTRL11 0xb398
+
+/*
+ * AR7010 registers.
+ */
+#define AR7010_GPIO_OE 0x52000
+#define AR7010_GPIO_IN 0x52004
+#define AR7010_GPIO_OUT 0x52008
+
+
+/* Bits for AR_AN_RF2G1_CH0. */
+#define AR_AN_RF2G1_CH0_OB_M 0x03800000
+#define AR_AN_RF2G1_CH0_OB_S 23
+#define AR_AN_RF2G1_CH0_DB_M 0x1c000000
+#define AR_AN_RF2G1_CH0_DB_S 26
+
+/* Bits for AR_AN_RF5G1_CH0. */
+#define AR_AN_RF5G1_CH0_OB5_M 0x00070000
+#define AR_AN_RF5G1_CH0_OB5_S 16
+#define AR_AN_RF5G1_CH0_DB5_M 0x00380000
+#define AR_AN_RF5G1_CH0_DB5_S 19
+
+/* Bits for AR_AN_RF2G1_CH1. */
+#define AR_AN_RF2G1_CH1_OB_M 0x03800000
+#define AR_AN_RF2G1_CH1_OB_S 23
+#define AR_AN_RF2G1_CH1_DB_M 0x1c000000
+#define AR_AN_RF2G1_CH1_DB_S 26
+
+/* Bits for AR_AN_RF5G1_CH1. */
+#define AR_AN_RF5G1_CH1_OB5_M 0x00070000
+#define AR_AN_RF5G1_CH1_OB5_S 16
+#define AR_AN_RF5G1_CH1_DB5_M 0x00380000
+#define AR_AN_RF5G1_CH1_DB5_S 19
+
+/* Bits for AR_AN_SYNTH9. */
+#define AR_AN_SYNTH9_REFDIVA_M 0xf8000000
+#define AR_AN_SYNTH9_REFDIVA_S 27
+
+/* Bits for AR_AN_TOP1. */
+#define AR_AN_TOP1_DACLPMODE 0x00040000
+
+/* Bits for AR_AN_TOP2. */
+#define AR_AN_TOP2_XPABIAS_LVL_M 0xc0000000
+#define AR_AN_TOP2_XPABIAS_LVL_S 30
+#define AR_AN_TOP2_LOCALBIAS 0x00200000
+#define AR_AN_TOP2_PWDCLKIND 0x00400000
+
+/* Bits for AR_PHY_TEST. */
+#define AR_PHY_TEST_RFSILENT_BB 0x00002000
+#define AR_PHY_TEST_AGC_CLR 0x10000000
+
+/* Bits for AR_PHY_TURBO. */
+#define AR_PHY_FC_TURBO_MODE 0x00000001
+#define AR_PHY_FC_TURBO_SHORT 0x00000002
+#define AR_PHY_FC_DYN2040_EN 0x00000004
+#define AR_PHY_FC_DYN2040_PRI_ONLY 0x00000008
+#define AR_PHY_FC_DYN2040_PRI_CH 0x00000010
+#define AR_PHY_FC_DYN2040_EXT_CH 0x00000020
+#define AR_PHY_FC_HT_EN 0x00000040
+#define AR_PHY_FC_SHORT_GI_40 0x00000080
+#define AR_PHY_FC_WALSH 0x00000100
+#define AR_PHY_FC_SINGLE_HT_LTF1 0x00000200
+#define AR_PHY_FC_ENABLE_DAC_FIFO 0x00000800
+
+/* Bits for AR_PHY_TIMING3. */
+#define AR_PHY_TIMING3_DSC_MAN_M 0xfffe0000
+#define AR_PHY_TIMING3_DSC_MAN_S 17
+#define AR_PHY_TIMING3_DSC_EXP_M 0x0001e000
+#define AR_PHY_TIMING3_DSC_EXP_S 13
+
+/* Bits for AR_PHY_CHIP_ID. */
+#define AR_PHY_CHIP_ID_REV_0 0x00000080
+#define AR_PHY_CHIP_ID_REV_1 0x00000081
+#define AR_PHY_CHIP_ID_9160_REV_0 0x000000b0
+
+/* Bits for AR_PHY_ACTIVE. */
+#define AR_PHY_ACTIVE_EN 0x00000001
+#define AR_PHY_ACTIVE_DIS 0x00000000
+
+/* Bits for AR_PHY_RF_CTL2. */
+#define AR_PHY_TX_END_DATA_START_M 0x000000ff
+#define AR_PHY_TX_END_DATA_START_S 0
+#define AR_PHY_TX_END_PA_ON_M 0x0000ff00
+#define AR_PHY_TX_END_PA_ON_S 8
+
+/* Bits for AR_PHY_RF_CTL3. */
+#define AR_PHY_TX_END_TO_A2_RX_ON_M 0x00ff0000
+#define AR_PHY_TX_END_TO_A2_RX_ON_S 16
+
+/* Bits for AR_PHY_ADC_CTL. */
+#define AR_PHY_ADC_CTL_OFF_INBUFGAIN_M 0x00000003
+#define AR_PHY_ADC_CTL_OFF_INBUFGAIN_S 0
+#define AR_PHY_ADC_CTL_OFF_PWDDAC 0x00002000
+#define AR_PHY_ADC_CTL_OFF_PWDBANDGAP 0x00004000
+#define AR_PHY_ADC_CTL_OFF_PWDADC 0x00008000
+#define AR_PHY_ADC_CTL_ON_INBUFGAIN_M 0x00030000
+#define AR_PHY_ADC_CTL_ON_INBUFGAIN_S 16
+
+/* Bits for AR_PHY_ADC_SERIAL_CTL. */
+#define AR_PHY_SEL_INTERNAL_ADDAC 0x00000000
+#define AR_PHY_SEL_EXTERNAL_RADIO 0x00000001
+
+/* Bits for AR_PHY_RF_CTL4. */
+#define AR_PHY_RF_CTL4_TX_END_XPAB_OFF_M 0xff000000
+#define AR_PHY_RF_CTL4_TX_END_XPAB_OFF_S 24
+#define AR_PHY_RF_CTL4_TX_END_XPAA_OFF_M 0x00ff0000
+#define AR_PHY_RF_CTL4_TX_END_XPAA_OFF_S 16
+#define AR_PHY_RF_CTL4_FRAME_XPAB_ON_M 0x0000ff00
+#define AR_PHY_RF_CTL4_FRAME_XPAB_ON_S 8
+#define AR_PHY_RF_CTL4_FRAME_XPAA_ON_M 0x000000ff
+#define AR_PHY_RF_CTL4_FRAME_XPAA_ON_S 0
+
+/* Bits for AR_PHY_SETTLING. */
+#define AR_PHY_SETTLING_SWITCH_M 0x00003f80
+#define AR_PHY_SETTLING_SWITCH_S 7
+
+/* Bits for AR_PHY_RXGAIN. */
+#define AR_PHY_RXGAIN_TXRX_ATTEN_M 0x0003f000
+#define AR_PHY_RXGAIN_TXRX_ATTEN_S 12
+#define AR_PHY_RXGAIN_TXRX_RF_MAX_M 0x007c0000
+#define AR_PHY_RXGAIN_TXRX_RF_MAX_S 18
+#define AR9280_PHY_RXGAIN_TXRX_ATTEN_M 0x00003f80
+#define AR9280_PHY_RXGAIN_TXRX_ATTEN_S 7
+#define AR9280_PHY_RXGAIN_TXRX_MARGIN_M 0x001fc000
+#define AR9280_PHY_RXGAIN_TXRX_MARGIN_S 14
+
+/* Bits for AR_PHY_DESIRED_SZ. */
+#define AR_PHY_DESIRED_SZ_ADC_M 0x000000ff
+#define AR_PHY_DESIRED_SZ_ADC_S 0
+#define AR_PHY_DESIRED_SZ_PGA_M 0x0000ff00
+#define AR_PHY_DESIRED_SZ_PGA_S 8
+#define AR_PHY_DESIRED_SZ_TOT_DES_M 0x0ff00000
+#define AR_PHY_DESIRED_SZ_TOT_DES_S 20
+
+/* Bits for AR_PHY_FIND_SIG. */
+#define AR_PHY_FIND_SIG_FIRSTEP_M 0x0003f000
+#define AR_PHY_FIND_SIG_FIRSTEP_S 12
+#define AR_PHY_FIND_SIG_FIRPWR_M 0x03fc0000
+#define AR_PHY_FIND_SIG_FIRPWR_S 18
+
+/* Bits for AR_PHY_AGC_CTL1. */
+#define AR_PHY_AGC_CTL1_COARSE_LOW_M 0x00007f80
+#define AR_PHY_AGC_CTL1_COARSE_LOW_S 7
+#define AR_PHY_AGC_CTL1_COARSE_HIGH_M 0x003f8000
+#define AR_PHY_AGC_CTL1_COARSE_HIGH_S 15
+
+/* Bits for AR_PHY_AGC_CONTROL. */
+#define AR_PHY_AGC_CONTROL_CAL 0x00000001
+#define AR_PHY_AGC_CONTROL_NF 0x00000002
+#define AR_PHY_AGC_CONTROL_ENABLE_NF 0x00008000
+#define AR_PHY_AGC_CONTROL_FLTR_CAL 0x00010000
+#define AR_PHY_AGC_CONTROL_NO_UPDATE_NF 0x00020000
+
+/* Bits for AR_PHY_CCA. */
+#define AR_PHY_MAXCCA_PWR_M 0x000001ff
+#define AR_PHY_MAXCCA_PWR_S 0
+#define AR_PHY_CCA_THRESH62_M 0x0007f000
+#define AR_PHY_CCA_THRESH62_S 12
+#define AR_PHY_MINCCA_PWR_M 0x0ff80000
+#define AR_PHY_MINCCA_PWR_S 19
+#define AR9280_PHY_CCA_THRESH62_M 0x000ff000
+#define AR9280_PHY_CCA_THRESH62_S 12
+#define AR9280_PHY_MINCCA_PWR_M 0x1ff00000
+#define AR9280_PHY_MINCCA_PWR_S 20
+
+/* Bits for AR_PHY_SFCORR_LOW. */
+#define AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW 0x00000001
+#define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW_M 0x00003f00
+#define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW_S 8
+#define AR_PHY_SFCORR_LOW_M1_THRESH_LOW_M 0x001fc000
+#define AR_PHY_SFCORR_LOW_M1_THRESH_LOW_S 14
+#define AR_PHY_SFCORR_LOW_M2_THRESH_LOW_M 0x0fe00000
+#define AR_PHY_SFCORR_LOW_M2_THRESH_LOW_S 21
+
+/* Bits for AR_PHY_SFCORR. */
+#define AR_PHY_SFCORR_M2COUNT_THR_M 0x0000001f
+#define AR_PHY_SFCORR_M2COUNT_THR_S 0
+#define AR_PHY_SFCORR_M1_THRESH_M 0x00fe0000
+#define AR_PHY_SFCORR_M1_THRESH_S 17
+#define AR_PHY_SFCORR_M2_THRESH_M 0x7f000000
+#define AR_PHY_SFCORR_M2_THRESH_S 24
+
+/* Bits for AR_PHY_RX_DELAY. */
+#define AR_PHY_RX_DELAY_DELAY_M 0x00003fff
+#define AR_PHY_RX_DELAY_DELAY_S 0
+
+/* Bits for AR_PHY_TIMING_CTRL4_0. */
+#define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF_M 0x0000001f
+#define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF_S 0
+#define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF_M 0x000007e0
+#define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF_S 5
+#define AR_PHY_TIMING_CTRL4_IQCORR_ENABLE 0x00000800
+#define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX_M 0x0000f000
+#define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX_S 12
+#define AR_PHY_TIMING_CTRL4_DO_CAL 0x00010000
+#define AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK 0x10000000
+#define AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK 0x20000000
+#define AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER 0x40000000
+#define AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI 0x80000000
+
+/* Bits for AR_PHY_TIMING5. */
+#define AR_PHY_TIMING5_CYCPWR_THR1_M 0x000000fe
+#define AR_PHY_TIMING5_CYCPWR_THR1_S 1
+
+/* Bits for AR_PHY_POWER_TX_RATE_MAX. */
+#define AR_PHY_POWER_TX_RATE_MAX_TPC_ENABLE 0x00000040
+
+/* Bits for AR_PHY_FRAME_CTL. */
+#define AR_PHY_FRAME_CTL_TX_CLIP_M 0x00000038
+#define AR_PHY_FRAME_CTL_TX_CLIP_S 3
+
+/* Bits for AR_PHY_TXPWRADJ. */
+#define AR_PHY_TXPWRADJ_CCK_GAIN_DELTA_M 0x00000fc0
+#define AR_PHY_TXPWRADJ_CCK_GAIN_DELTA_S 6
+#define AR_PHY_TXPWRADJ_CCK_PCDAC_INDEX_M 0x00fc0000
+#define AR_PHY_TXPWRADJ_CCK_PCDAC_INDEX_S 18
+
+/* Bits for AR_PHY_RADAR_EXT. */
+#define AR_PHY_RADAR_EXT_ENA 0x00004000
+
+/* Bits for AR_PHY_RADAR_0. */
+#define AR_PHY_RADAR_0_ENA 0x00000001
+#define AR_PHY_RADAR_0_INBAND_M 0x0000003e
+#define AR_PHY_RADAR_0_INBAND_S 1
+#define AR_PHY_RADAR_0_PRSSI_M 0x00000fc0
+#define AR_PHY_RADAR_0_PRSSI_S 6
+#define AR_PHY_RADAR_0_HEIGHT_M 0x0003f000
+#define AR_PHY_RADAR_0_HEIGHT_S 12
+#define AR_PHY_RADAR_0_RRSSI_M 0x00fc0000
+#define AR_PHY_RADAR_0_RRSSI_S 18
+#define AR_PHY_RADAR_0_FIRPWR_M 0x7f000000
+#define AR_PHY_RADAR_0_FIRPWR_S 24
+#define AR_PHY_RADAR_0_FFT_ENA 0x80000000
+
+/* Bits for AR_PHY_RADAR_1. */
+#define AR_PHY_RADAR_1_MAXLEN_M 0x000000ff
+#define AR_PHY_RADAR_1_MAXLEN_S 0
+#define AR_PHY_RADAR_1_RELSTEP_THRESH_M 0x00001f00
+#define AR_PHY_RADAR_1_RELSTEP_THRESH_S 8
+#define AR_PHY_RADAR_1_RELSTEP_CHECK 0x00002000
+#define AR_PHY_RADAR_1_MAX_RRSSI 0x00004000
+#define AR_PHY_RADAR_1_BLOCK_CHECK 0x00008000
+#define AR_PHY_RADAR_1_RELPWR_THRESH_M 0x003f0000
+#define AR_PHY_RADAR_1_RELPWR_THRESH_S 16
+#define AR_PHY_RADAR_1_USE_FIR128 0x00400000
+#define AR_PHY_RADAR_1_RELPWR_ENA 0x00800000
+
+/* Bits for AR_PHY_SIGMA_DELTA. */
+#define AR_PHY_SIGMA_DELTA_ADC_SEL_M 0x00000003
+#define AR_PHY_SIGMA_DELTA_ADC_SEL_S 0
+#define AR_PHY_SIGMA_DELTA_FILT2_M 0x000000f8
+#define AR_PHY_SIGMA_DELTA_FILT2_S 3
+#define AR_PHY_SIGMA_DELTA_FILT1_M 0x00001f00
+#define AR_PHY_SIGMA_DELTA_FILT1_S 8
+#define AR_PHY_SIGMA_DELTA_ADC_CLIP_M 0x01ffe000
+#define AR_PHY_SIGMA_DELTA_ADC_CLIP_S 13
+
+/* Bits for AR_PHY_RESTART. */
+#define AR_PHY_RESTART_DIV_GC_M 0x001c0000
+#define AR_PHY_RESTART_DIV_GC_S 18
+
+/* Bits for AR_PHY_RFBUS_REQ. */
+#define AR_PHY_RFBUS_REQ_EN 0x00000001
+
+/* Bits for AR_PHY_TIMING11. */
+#define AR_PHY_TIMING11_SPUR_DELTA_PHASE_M 0x000fffff
+#define AR_PHY_TIMING11_SPUR_DELTA_PHASE_S 0
+#define AR_PHY_TIMING11_SPUR_FREQ_SD_M 0x3ff00000
+#define AR_PHY_TIMING11_SPUR_FREQ_SD_S 20
+#define AR_PHY_TIMING11_USE_SPUR_IN_AGC 0x40000000
+#define AR_PHY_TIMING11_USE_SPUR_IN_SELFCOR 0x80000000
+
+/* Bits for AR_PHY_NEW_ADC_DC_GAIN_CORR(). */
+#define AR_PHY_NEW_ADC_GAIN_CORR_ENABLE 0x40000000
+#define AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE 0x80000000
+
+/* Bits for AR_PHY_EXT_CCA0. */
+#define AR_PHY_EXT_CCA0_THRESH62_M 0x000000ff
+#define AR_PHY_EXT_CCA0_THRESH62_S 0
+
+/* Bits for AR_PHY_EXT_CCA. */
+#define AR_PHY_EXT_MAXCCA_PWR_M 0x000001ff
+#define AR_PHY_EXT_MAXCCA_PWR_S 0
+#define AR_PHY_EXT_CCA_CYCPWR_THR1_M 0x0000fe00
+#define AR_PHY_EXT_CCA_CYCPWR_THR1_S 9
+#define AR_PHY_EXT_CCA_THRESH62_M 0x007f0000
+#define AR_PHY_EXT_CCA_THRESH62_S 16
+#define AR_PHY_EXT_MINCCA_PWR_M 0xff800000
+#define AR_PHY_EXT_MINCCA_PWR_S 23
+#define AR9280_PHY_EXT_MINCCA_PWR_M 0x01ff0000
+#define AR9280_PHY_EXT_MINCCA_PWR_S 16
+
+/* Bits for AR_PHY_SFCORR_EXT. */
+#define AR_PHY_SFCORR_EXT_M1_THRESH_M 0x0000007f
+#define AR_PHY_SFCORR_EXT_M1_THRESH_S 0
+#define AR_PHY_SFCORR_EXT_M2_THRESH_M 0x00003f80
+#define AR_PHY_SFCORR_EXT_M2_THRESH_S 7
+#define AR_PHY_SFCORR_EXT_M1_THRESH_LOW_M 0x001fc000
+#define AR_PHY_SFCORR_EXT_M1_THRESH_LOW_S 14
+#define AR_PHY_SFCORR_EXT_M2_THRESH_LOW_M 0x0fe00000
+#define AR_PHY_SFCORR_EXT_M2_THRESH_LOW_S 21
+#define AR_PHY_SFCORR_SPUR_SUBCHNL_SD_M 0xf0000000
+#define AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S 28
+
+/* Bits for AR_PHY_HALFGI. */
+#define AR_PHY_HALFGI_DSC_EXP_M 0x0000000f
+#define AR_PHY_HALFGI_DSC_EXP_S 0
+#define AR_PHY_HALFGI_DSC_MAN_M 0x0007fff0
+#define AR_PHY_HALFGI_DSC_MAN_S 4
+
+/* Bits for AR_PHY_CHAN_INFO_MEMORY. */
+#define AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK 0x00000001
+
+/* Bits for AR_PHY_HEAVY_CLIP_FACTOR_RIFS. */
+#define AR_PHY_RIFS_INIT_DELAY_M 0x03ff0000
+#define AR_PHY_RIFS_INIT_DELAY_S 16
+
+/* Bits for AR_PHY_CALMODE. */
+#define AR_PHY_CALMODE_IQ 0x00000000
+#define AR_PHY_CALMODE_ADC_GAIN 0x00000001
+#define AR_PHY_CALMODE_ADC_DC_PER 0x00000002
+#define AR_PHY_CALMODE_ADC_DC_INIT 0x00000003
+
+/* Bits for AR_PHY_RFBUS_GRANT. */
+#define AR_PHY_RFBUS_GRANT_EN 0x00000001
+
+/* Bits for AR_PHY_CHAN_INFO_GAIN_DIFF. */
+#define AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT 320
+
+/* Bits for AR_PHY_MODE. */
+#define AR_PHY_MODE_ASYNCFIFO 0x00000080
+#define AR_PHY_MODE_AR2133 0x00000008
+#define AR_PHY_MODE_AR5111 0x00000000
+#define AR_PHY_MODE_AR5112 0x00000008
+#define AR_PHY_MODE_DYNAMIC 0x00000004
+#define AR_PHY_MODE_RF2GHZ 0x00000002
+#define AR_PHY_MODE_RF5GHZ 0x00000000
+#define AR_PHY_MODE_CCK 0x00000001
+#define AR_PHY_MODE_OFDM 0x00000000
+#define AR_PHY_MODE_DYN_CCK_DISABLE 0x00000100
+
+/* Bits for AR_PHY_CCK_TX_CTRL. */
+#define AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK_M 0x0000000c
+#define AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK_S 2
+#define AR_PHY_CCK_TX_CTRL_JAPAN 0x00000010
+
+/* Bits for AR_PHY_CCK_DETECT. */
+#define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_M 0x0000003f
+#define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S 0
+#define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME_M 0x00001fc0
+#define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME_S 6
+#define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV 0x00002000
+
+/* Bits for AR_PHY_GAIN_2GHZ. */
+#define AR_PHY_GAIN_2GHZ_XATTEN1_DB_M 0x0000003f
+#define AR_PHY_GAIN_2GHZ_XATTEN1_DB_S 0
+#define AR_PHY_GAIN_2GHZ_BSW_ATTEN_M 0x0000001f
+#define AR_PHY_GAIN_2GHZ_BSW_ATTEN_S 0
+#define AR_PHY_GAIN_2GHZ_XATTEN2_DB_M 0x00000fc0
+#define AR_PHY_GAIN_2GHZ_XATTEN2_DB_S 6
+#define AR_PHY_GAIN_2GHZ_BSW_MARGIN_M 0x00003c00
+#define AR_PHY_GAIN_2GHZ_BSW_MARGIN_S 10
+#define AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN_M 0x0001f000
+#define AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN_S 12
+#define AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN_M 0x003e0000
+#define AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN_S 17
+#define AR_PHY_GAIN_2GHZ_RXTX_MARGIN_M 0x00fc0000
+#define AR_PHY_GAIN_2GHZ_RXTX_MARGIN_S 18
+
+/* Bit for AR_PHY_CCK_RXCTRL4. */
+#define AR_PHY_CCK_RXCTRL4_FREQ_EST_SHORT_M 0x01f80000
+#define AR_PHY_CCK_RXCTRL4_FREQ_EST_SHORT_S 19
+
+/* Bits for AR_PHY_DAG_CTRLCCK. */
+#define AR_PHY_DAG_CTRLCCK_EN_RSSI_THR 0x00000200
+#define AR_PHY_DAG_CTRLCCK_RSSI_THR_M 0x0001fc00
+#define AR_PHY_DAG_CTRLCCK_RSSI_THR_S 10
+
+/* Bits for AR_PHY_FORCE_CLKEN_CCK. */
+#define AR_PHY_FORCE_CLKEN_CCK_MRC_MUX 0x00000040
+
+/* Bits for AR_PHY_TPCRG1. */
+#define AR_PHY_TPCRG1_NUM_PD_GAIN_M 0x0000c000
+#define AR_PHY_TPCRG1_NUM_PD_GAIN_S 14
+#define AR_PHY_TPCRG1_PD_GAIN_1_M 0x00030000
+#define AR_PHY_TPCRG1_PD_GAIN_1_S 16
+#define AR_PHY_TPCRG1_PD_GAIN_2_M 0x000c0000
+#define AR_PHY_TPCRG1_PD_GAIN_2_S 18
+#define AR_PHY_TPCRG1_PD_GAIN_3_M 0x00300000
+#define AR_PHY_TPCRG1_PD_GAIN_3_S 20
+#define AR_PHY_TPCRG1_PD_CAL_ENABLE 0x00400000
+
+/* Bits for AR_PHY_TX_PWRCTRL4. */
+#define AR_PHY_TX_PWRCTRL_PD_AVG_VALID 0x00000001
+#define AR_PHY_TX_PWRCTRL_PD_AVG_OUT_M 0x000001fe
+#define AR_PHY_TX_PWRCTRL_PD_AVG_OUT_S 1
+
+/* Bits for AR_PHY_TX_PWRCTRL6_[01]. */
+#define AR_PHY_TX_PWRCTRL_ERR_EST_MODE_M 0x03000000
+#define AR_PHY_TX_PWRCTRL_ERR_EST_MODE_S 24
+
+/* Bits for AR_PHY_TX_PWRCTRL7. */
+#define AR_PHY_TX_PWRCTRL_TX_GAIN_TAB_MAX_M 0x0007e000
+#define AR_PHY_TX_PWRCTRL_TX_GAIN_TAB_MAX_S 13
+#define AR_PHY_TX_PWRCTRL_INIT_TX_GAIN_M 0x01f80000
+#define AR_PHY_TX_PWRCTRL_INIT_TX_GAIN_S 19
+
+/* Bits for AR_PHY_TX_PWRCTRL9. */
+#define AR_PHY_TX_DESIRED_SCALE_CCK_M 0x00007c00
+#define AR_PHY_TX_DESIRED_SCALE_CCK_S 10 /* XXX should be 9? */
+#define AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL 0x80000000
+
+/* Bits for AR_PHY_TX_GAIN_TBL. */
+#define AR_PHY_TX_GAIN_CLC_M 0x0000001e
+#define AR_PHY_TX_GAIN_CLC_S 1
+#define AR_PHY_TX_GAIN_M 0x0007f000
+#define AR_PHY_TX_GAIN_S 12
+
+/* Bits for AR_PHY_SPUR_REG. */
+#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_M 0x0000007f
+#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_S 0
+#define AR_SPUR_RSSI_THRESH 40
+#define AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI 0x00000100
+#define AR_PHY_SPUR_REG_MASK_RATE_SELECT 0x0001fe00
+#define AR_PHY_SPUR_REG_ENABLE_MASK_PPM 0x00020000
+#define AR_PHY_SPUR_REG_MASK_RATE_CNTL 0x03fc0000
+
+/* Bits for AR_PHY_ANALOG_SWAP. */
+#define AR_PHY_SWAP_ALT_CHAIN 0x00000040
+
+/* Bits for AR_PHY_TPCRG5. */
+#define AR_PHY_TPCRG5_PD_GAIN_OVERLAP_M 0x0000000f
+#define AR_PHY_TPCRG5_PD_GAIN_OVERLAP_S 0
+#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1_M 0x000003f0
+#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1_S 4
+#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2_M 0x0000fc00
+#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2_S 10
+#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3_M 0x003f0000
+#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3_S 16
+#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4_M 0x0fc00000
+#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4_S 22
+
+/* Bits for AR_PHY_CL_CAL_CTL. */
+#define AR_PHY_PARALLEL_CAL_ENABLE 0x00000001
+#define AR_PHY_CL_CAL_ENABLE 0x00000002
+
+/* Bits for AR_PHY_CLC_TBL. */
+#define AR_PHY_CLC_Q0_M 0x0000ffd0
+#define AR_PHY_CLC_Q0_S 5
+#define AR_PHY_CLC_I0_M 0x07ff0000
+#define AR_PHY_CLC_I0_S 16
+
+/* Bits for AR_PHY_XPA_CFG. */
+#define AR_PHY_FORCE_XPA_CFG 0x000000001
+
+/* Bits for AR_PHY_CH[01]_TX_PWRCTRL11. */
+#define AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP_M 0x0000fc00
+#define AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP_S 10
+#define AR_PHY_TX_PWRCTRL_OLPC_PWR_M 0x00ff0000
+#define AR_PHY_TX_PWRCTRL_OLPC_PWR_S 16
+
+/* Bits for AR_PHY_NEW_ADC_DC_GAIN_CORR. */
+#define AR_PHY_NEW_ADC_DC_GAIN_QGAIN_M 0x0000003f
+#define AR_PHY_NEW_ADC_DC_GAIN_QGAIN_S 0
+#define AR_PHY_NEW_ADC_DC_GAIN_IGAIN_M 0x00000fc0
+#define AR_PHY_NEW_ADC_DC_GAIN_IGAIN_S 6
+#define AR_PHY_NEW_ADC_DC_GAIN_QDC_M 0x001ff000
+#define AR_PHY_NEW_ADC_DC_GAIN_QDC_S 12
+#define AR_PHY_NEW_ADC_DC_GAIN_IDC_M 0x3fe00000
+#define AR_PHY_NEW_ADC_DC_GAIN_IDC_S 21
+
+/* Bits for AR_PHY(0x37). */
+#define AR5416_BMODE_SYNTH 0x00000002
+#define AR5416_AMODE_REFSEL_M 0x0000000c
+#define AR5416_AMODE_REFSEL_S 2
+
+
+#define AR5008_MAX_SCATTER 16 /* NB: not a hardware limit. */
+
+/*
+ * Tx DMA descriptor.
+ */
+struct ar_tx_desc {
+ uint32_t ds_link;
+ uint32_t ds_data;
+ uint32_t ds_ctl0;
+ uint32_t ds_ctl1;
+ uint32_t ds_ctl2;
+ uint32_t ds_ctl3;
+ uint32_t ds_ctl4;
+ uint32_t ds_ctl5;
+ uint32_t ds_ctl6;
+ uint32_t ds_ctl7;
+ uint32_t ds_ctl8;
+ uint32_t ds_ctl9;
+ uint32_t ds_ctl10;
+ uint32_t ds_ctl11;
+ uint32_t ds_status0;
+ uint32_t ds_status1;
+ uint32_t ds_tstamp;
+ uint32_t ds_ba_bitmap_lo;
+ uint32_t ds_ba_bitmap_hi;
+ uint32_t ds_evm0;
+ uint32_t ds_evm1;
+ uint32_t ds_evm2;
+ uint32_t ds_status8;
+ uint32_t ds_status9;
+ /*
+ * Padding to make Tx descriptors 128 bytes such that they will
+ * not cross a 4KB boundary.
+ */
+ uint32_t pad[8];
+} __packed __attribute__((aligned(4)));
+
+/* Bits for ds_ctl0. */
+#define AR_TXC0_FRAME_LEN_M 0x00000fff
+#define AR_TXC0_FRAME_LEN_S 0
+#define AR_TXC0_VIRT_MORE_FRAG 0x00001000
+#define AR_TXC0_XMIT_POWER_M 0x003f0000
+#define AR_TXC0_XMIT_POWER_S 16
+#define AR_TXC0_RTS_ENABLE 0x00400000
+#define AR_TXC0_VEOL 0x00800000
+#define AR_TXC0_CLR_DEST_MASK 0x01000000
+#define AR_TXC0_INTR_REQ 0x20000000
+#define AR_TXC0_DEST_IDX_VALID 0x40000000
+#define AR_TXC0_CTS_ENABLE 0x80000000
+
+/* Bits for ds_ctl1. */
+#define AR_TXC1_BUF_LEN_M 0x00000fff
+#define AR_TXC1_BUF_LEN_S 0
+#define AR_TXC1_MORE 0x00001000
+#define AR_TXC1_DEST_IDX_M 0x000fe000
+#define AR_TXC1_DEST_IDX_S 13
+#define AR_TXC1_FRAME_TYPE_M 0x00f00000
+#define AR_TXC1_FRAME_TYPE_S 20
+#define AR_FRAME_TYPE_NORMAL 0
+#define AR_FRAME_TYPE_ATIM 1
+#define AR_FRAME_TYPE_PSPOLL 2
+#define AR_FRAME_TYPE_BEACON 3
+#define AR_FRAME_TYPE_PROBE_RESP 4
+#define AR_TXC1_NO_ACK 0x01000000
+#define AR_TXC1_INSERT_TS 0x02000000
+#define AR_TXC1_EXT_ONLY 0x08000000
+#define AR_TXC1_EXT_AND_CTL 0x10000000
+#define AR_TXC1_MORE_AGGR 0x20000000
+#define AR_TXC1_IS_AGGR 0x40000000
+
+/* Bits for ds_ctl2. */
+#define AR_TXC2_BURST_DUR_M 0x00007fff
+#define AR_TXC2_BURST_DUR_S 0
+#define AR_TXC2_DUR_UPDATE_ENA 0x00008000
+#define AR_TXC2_XMIT_DATA_TRIES0_M 0x000f0000
+#define AR_TXC2_XMIT_DATA_TRIES0_S 16
+#define AR_TXC2_XMIT_DATA_TRIES1_M 0x00f00000
+#define AR_TXC2_XMIT_DATA_TRIES1_S 20
+#define AR_TXC2_XMIT_DATA_TRIES2_M 0x0f000000
+#define AR_TXC2_XMIT_DATA_TRIES2_S 24
+#define AR_TXC2_XMIT_DATA_TRIES3_M 0xf0000000
+#define AR_TXC2_XMIT_DATA_TRIES3_S 28
+
+/* Bits for ds_ctl3. */
+#define AR_TXC3_XMIT_RATE0_M 0x000000ff
+#define AR_TXC3_XMIT_RATE0_S 0
+#define AR_TXC3_XMIT_RATE1_M 0x0000ff00
+#define AR_TXC3_XMIT_RATE1_S 8
+#define AR_TXC3_XMIT_RATE2_M 0x00ff0000
+#define AR_TXC3_XMIT_RATE2_S 16
+#define AR_TXC3_XMIT_RATE3_M 0xff000000
+#define AR_TXC3_XMIT_RATE3_S 24
+
+/* Bits for ds_ctl4. */
+#define AR_TXC4_PACKET_DUR0_M 0x00007fff
+#define AR_TXC4_PACKET_DUR0_S 0
+#define AR_TXC4_RTSCTS_QUAL0 0x00008000
+#define AR_TXC4_PACKET_DUR1_M 0x7fff0000
+#define AR_TXC4_PACKET_DUR1_S 16
+#define AR_TXC4_RTSCTS_QUAL1 0x80000000
+/* Shortcut. */
+#define AR_TXC4_RTSCTS_QUAL01 \
+ (AR_TXC4_RTSCTS_QUAL0 | AR_TXC4_RTSCTS_QUAL1)
+
+/* Bits for ds_ctl5. */
+#define AR_TXC5_PACKET_DUR2_M 0x00007fff
+#define AR_TXC5_PACKET_DUR2_S 0
+#define AR_TXC5_RTSCTS_QUAL2 0x00008000
+#define AR_TXC5_PACKET_DUR3_M 0x7fff0000
+#define AR_TXC5_PACKET_DUR3_S 16
+#define AR_TXC5_RTSCTS_QUAL3 0x80000000
+/* Shortcut. */
+#define AR_TXC5_RTSCTS_QUAL23 \
+ (AR_TXC5_RTSCTS_QUAL2 | AR_TXC5_RTSCTS_QUAL3)
+
+/* Bits for ds_ctl6. */
+#define AR_TXC6_AGGR_LEN_M 0x0000ffff
+#define AR_TXC6_AGGR_LEN_S 0
+#define AR_TXC6_PAD_DELIM_M 0x03fc0000
+#define AR_TXC6_PAD_DELIM_S 18
+#define AR_TXC6_ENCR_TYPE_M 0x0c000000
+#define AR_TXC6_ENCR_TYPE_S 26
+#define AR_ENCR_TYPE_CLEAR 0
+#define AR_ENCR_TYPE_WEP 1
+#define AR_ENCR_TYPE_AES 2
+#define AR_ENCR_TYPE_TKIP 3
+
+/* Bits for ds_ctl7. */
+#define AR_TXC7_2040_0 0x00000001
+#define AR_TXC7_GI0 0x00000002
+#define AR_TXC7_CHAIN_SEL0_M 0x0000001c
+#define AR_TXC7_CHAIN_SEL0_S 2
+#define AR_TXC7_2040_1 0x00000020
+#define AR_TXC7_GI1 0x00000040
+#define AR_TXC7_CHAIN_SEL1_M 0x00000380
+#define AR_TXC7_CHAIN_SEL1_S 7
+#define AR_TXC7_2040_2 0x00000400
+#define AR_TXC7_GI2 0x00000800
+#define AR_TXC7_CHAIN_SEL2_M 0x00007000
+#define AR_TXC7_CHAIN_SEL2_S 12
+#define AR_TXC7_2040_3 0x00008000
+#define AR_TXC7_GI3 0x00010000
+#define AR_TXC7_CHAIN_SEL3_M 0x000e0000
+#define AR_TXC7_CHAIN_SEL3_S 17
+#define AR_TXC7_RTSCTS_RATE_M 0x0ff00000
+#define AR_TXC7_RTSCTS_RATE_S 20
+/* Shortcuts. */
+#define AR_TXC7_2040_0123 \
+ (AR_TXC7_2040_0 | AR_TXC7_2040_1 | AR_TXC7_2040_2 | AR_TXC7_2040_3)
+#define AR_TXC7_GI0123 \
+ (AR_TXC7_GI0 | AR_TXC7_GI1 | AR_TXC7_GI2 | AR_TXC7_GI3)
+
+/* Bits for ds_status0. */
+#define AR_TXS0_RSSI_ANT0(i) (((x) >> ((i) * 8)) & 0xff)
+#define AR_TXS0_BA_STATUS 0x40000000
+
+/* Bits for ds_status1. */
+#define AR_TXS1_FRM_XMIT_OK 0x00000001
+#define AR_TXS1_EXCESSIVE_RETRIES 0x00000002
+#define AR_TXS1_FIFO_UNDERRUN 0x00000004
+#define AR_TXS1_FILTERED 0x00000008
+#define AR_TXS1_RTS_FAIL_CNT_M 0x000000f0
+#define AR_TXS1_RTS_FAIL_CNT_S 4
+#define AR_TXS1_DATA_FAIL_CNT_M 0x00000f00
+#define AR_TXS1_DATA_FAIL_CNT_S 8
+#define AR_TXS1_VIRT_RETRY_CNT_M 0x0000f000
+#define AR_TXS1_VIRT_RETRY_CNT_S 12
+#define AR_TXS1_TX_DELIM_UNDERRUN 0x00010000
+#define AR_TXS1_TX_DATA_UNDERRUN 0x00020000
+#define AR_TXS1_DESC_CFG_ERR 0x00040000
+#define AR_TXS1_TX_TIMER_EXPIRED 0x00080000
+/* Shortcut. */
+#define AR_TXS1_UNDERRUN \
+ (AR_TXS1_FIFO_UNDERRUN | \
+ AR_TXS1_TX_DELIM_UNDERRUN | \
+ AR_TXS1_TX_DATA_UNDERRUN)
+
+/* Bits for ds_status9. */
+#define AR_TXS9_DONE 0x00000001
+#define AR_TXS9_SEQNUM_M 0x00001ffe
+#define AR_TXS9_SEQNUM_S 1
+#define AR_TXS9_TXOP_EXCEEDED 0x00020000
+#define AR_TXS9_FINAL_IDX_M 0x00600000
+#define AR_TXS9_FINAL_IDX_S 21
+#define AR_TXS9_POWER_MGMT 0x02000000
+
+/*
+ * Rx DMA descriptor.
+ */
+struct ar_rx_desc {
+ uint32_t ds_link;
+ uint32_t ds_data;
+ uint32_t ds_ctl0;
+ uint32_t ds_ctl1;
+ uint32_t ds_status0;
+ uint32_t ds_status1;
+ uint32_t ds_status2;
+ uint32_t ds_status3;
+ uint32_t ds_status4;
+ uint32_t ds_status5;
+ uint32_t ds_status6;
+ uint32_t ds_status7;
+ uint32_t ds_status8;
+ /*
+ * Padding to make Rx descriptors 64 bytes such that they will
+ * not cross a 4KB boundary.
+ */
+ uint32_t pad[3];
+} __packed __attribute__((aligned(4)));
+
+/* Bits for ds_ctl1. */
+#define AR_RXC1_BUF_LEN_M 0x00000fff
+#define AR_RXC1_BUF_LEN_S 0
+#define AR_RXC1_INTR_REQ 0x00002000
+
+/* Bits for ds_ctl2. */
+#define AR_RXS0_RSSI_ANT00(x) (((x) >> 0) & 0xff)
+#define AR_RXS0_RSSI_ANT01(x) (((x) >> 8) & 0xff)
+#define AR_RXS0_RSSI_ANT02(x) (((x) >> 16) & 0xff)
+#define AR_RXS0_RATE_M 0xff000000
+#define AR_RXS0_RATE_S 24
+
+/* Bits for ds_status1. */
+#define AR_RXS1_DATA_LEN_M 0x00000fff
+#define AR_RXS1_DATA_LEN_S 0
+#define AR_RXS1_MORE 0x00001000
+
+/* Bits for ds_status3. */
+#define AR_RXS3_GI 0x00000001
+#define AR_RXS3_2040 0x00000002
+#define AR_RXS3_PARALLEL_40 0x00000004
+#define AR_RXS3_ANTENNA_M 0xffffff00
+#define AR_RXS3_ANTENNA_S 8
+#define AR_RXS3_RATE_M 0x000003fc
+#define AR_RXS3_RATE_S 2
+
+/* Bits for ds_status4. */
+#define AR_RXS4_RSSI_COMBINED_M 0xff000000
+#define AR_RXS4_RSSI_COMBINED_S 24
+
+/* Bits for ds_status8. */
+#define AR_RXS8_DONE 0x00000001
+#define AR_RXS8_FRAME_OK 0x00000002
+#define AR_RXS8_CRC_ERR 0x00000004
+#define AR_RXS8_DECRYPT_CRC_ERR 0x00000008
+#define AR_RXS8_PHY_ERR 0x00000010
+#define AR_RXS8_MICHAEL_ERR 0x00000020
+#define AR_RXS8_PRE_DELIM_CRC_ERR 0x00000040
+#define AR_RXS8_PHY_ERR_CODE_M 0x0000ff00
+#define AR_RXS8_PHY_ERR_CODE_S 8
+#define AR_RXS8_KEY_IDX_VALID 0x00000100
+#define AR_RXS8_KEY_IDX_M 0x0000fe00
+#define AR_RXS8_KEY_IDX_S 9
+#define AR_RXS8_POST_DELIM_CRC_ERR 0x00040000
+#define AR_RXS8_DECRYPT_BUSY_ERR 0x40000000
+
+#define AR_MAX_PWR_RANGE_IN_HALF_DB 64
+#define AR9285_PD_GAIN_BOUNDARY_DEFAULT 58
+
+/*
+ * AR5008 family common ROM header.
+ */
+#define AR_EEPROM_MAGIC_OFFSET 0x0000
+#if BYTE_ORDER == BIG_ENDIAN
+#define AR_EEPROM_MAGIC 0x5aa5
+#else
+#define AR_EEPROM_MAGIC 0xa55a
+#endif
+
+#define AR_NO_SPUR 0x8000
+#define AR_NUM_PDADC_VALUES 128
+
+struct ar_base_eep_header {
+ uint16_t length;
+ uint16_t checksum;
+ uint16_t version;
+#define AR_EEP_VER 0xe
+#define AR_EEP_VER_MINOR_MASK 0x0fff
+#define AR_EEP_MINOR_VER_2 2
+#define AR_EEP_MINOR_VER_3 3
+#define AR_EEP_MINOR_VER_7 7
+#define AR_EEP_MINOR_VER_9 9
+#define AR_EEP_MINOR_VER_10 10
+#define AR_EEP_MINOR_VER_16 16
+#define AR_EEP_MINOR_VER_17 17
+#define AR_EEP_MINOR_VER_19 19
+#define AR_EEP_MINOR_VER_20 20
+#define AR_EEP_MINOR_VER_21 21
+#define AR_EEP_MINOR_VER_22 22
+
+ uint8_t opCapFlags;
+#define AR_OPFLAGS_11A 0x01
+#define AR_OPFLAGS_11G 0x02
+#define AR_OPFLAGS_11N_5G40 0x04
+#define AR_OPFLAGS_11N_2G40 0x08
+#define AR_OPFLAGS_11N_5G20 0x10
+#define AR_OPFLAGS_11N_2G20 0x20
+/* Shortcut. */
+#define AR_OPFLAGS_11N 0x3c
+
+ uint8_t eepMisc;
+ uint16_t regDmn[2];
+ uint8_t macAddr[6];
+ uint8_t rxMask;
+ uint8_t txMask;
+ uint16_t rfSilent;
+#define AR_EEP_RFSILENT_ENABLED 0x0001
+#define AR_EEP_RFSILENT_GPIO_SEL_M 0x001c
+#define AR_EEP_RFSILENT_GPIO_SEL_S 2
+#define AR_EEP_RFSILENT_POLARITY 0x0002
+
+ uint16_t blueToothOptions;
+ uint16_t deviceCap;
+#define AR_EEP_DEVCAP_COMPRESS_DIS 0x0001
+#define AR_EEP_DEVCAP_AES_DIS 0x0002
+#define AR_EEP_DEVCAP_FASTFRAME_DIS 0x0004
+#define AR_EEP_DEVCAP_BURST_DIS 0x0008
+#define AR_EEP_DEVCAP_MAXQCU_M 0x01f0
+#define AR_EEP_DEVCAP_MAXQCU_S 4
+#define AR_EEP_DEVCAP_HEAVY_CLIP_EN 0x0200
+#define AR_EEP_DEVCAP_KC_ENTRIES_M 0xf000
+#define AR_EEP_DEVCAP_KC_ENTRIES_S 12
+
+ uint32_t binBuildNumber;
+ uint8_t deviceType;
+} __packed;
+
+#define AR_EEP_TXGAIN_ORIGINAL 0
+#define AR_EEP_TXGAIN_HIGH_POWER 1
+
+#define AR_EEPROM_MODAL_SPURS 5
+
+struct ar_spur_chan {
+ uint16_t spurChan;
+ uint8_t spurRangeLow;
+ uint8_t spurRangeHigh;
+} __packed;
+
+struct ar_cal_data_per_freq_olpc {
+ uint8_t pwrPdg[2][5];
+ uint8_t vpdPdg[2][5];
+ uint8_t pcdac[2][5];
+ uint8_t empty[2][5];
+} __packed;
+
+struct ar_cal_target_power_leg {
+ uint8_t bChannel;
+ uint8_t tPow2x[4];
+} __packed;
+
+struct ar_cal_target_power_ht {
+ uint8_t bChannel;
+ uint8_t tPow2x[8];
+} __packed;
+
+struct ar_cal_ctl_edges {
+ uint8_t bChannel;
+ uint8_t tPowerFlag;
+#define AR_CAL_CTL_EDGES_POWER_M 0x3f
+#define AR_CAL_CTL_EDGES_POWER_S 0
+#define AR_CAL_CTL_EDGES_FLAG_M 0xc0
+#define AR_CAL_CTL_EDGES_FLAG_S 6
+} __packed;
+
+#endif /* _ARN5008REG_H_ */
diff --git a/sys/dev/ic/arn5416.c b/sys/dev/ic/arn5416.c
new file mode 100644
index 00000000000..7b321327e82
--- /dev/null
+++ b/sys/dev/ic/arn5416.c
@@ -0,0 +1,963 @@
+/* $NetBSD: arn5416.c,v 1.1 2013/03/30 02:53:00 christos Exp $ */
+/* $OpenBSD: ar5416.c,v 1.12 2012/06/10 21:23:36 kettenis Exp $ */
+
+/*-
+ * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr>
+ * Copyright (c) 2008-2009 Atheros Communications Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+/*
+ * Driver for Atheros 802.11a/g/n chipsets.
+ * Routines for AR5416, AR5418 and AR9160 chipsets.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: arn5416.c,v 1.1 2013/03/30 02:53:00 christos Exp $");
+
+#include <sys/param.h>
+#include <sys/sockio.h>
+#include <sys/mbuf.h>
+#include <sys/kernel.h>
+#include <sys/socket.h>
+#include <sys/systm.h>
+#include <sys/malloc.h>
+#include <sys/queue.h>
+#include <sys/callout.h>
+#include <sys/conf.h>
+#include <sys/device.h>
+
+#include <sys/bus.h>
+#include <sys/endian.h>
+#include <sys/intr.h>
+
+#include <net/bpf.h>
+#include <net/if.h>
+#include <net/if_arp.h>
+#include <net/if_dl.h>
+#include <net/if_media.h>
+#include <net/if_types.h>
+
+#include <netinet/in.h>
+#include <netinet/in_systm.h>
+#include <netinet/in_var.h>
+#include <netinet/ip.h>
+
+#include <net80211/ieee80211_var.h>
+#include <net80211/ieee80211_amrr.h>
+#include <net80211/ieee80211_radiotap.h>
+
+#include <dev/ic/athnreg.h>
+#include <dev/ic/athnvar.h>
+
+#include <dev/ic/arn5008reg.h>
+#include <dev/ic/arn5008.h>
+#include <dev/ic/arn5416reg.h>
+#include <dev/ic/arn5416.h>
+#include <dev/ic/arn9280.h>
+
+#define Static static
+
+Static void ar5416_force_bias(struct athn_softc *,
+ struct ieee80211_channel *);
+Static void ar5416_get_pdadcs(struct athn_softc *,
+ struct ieee80211_channel *, int, int, uint8_t, uint8_t *,
+ uint8_t *);
+Static void ar5416_init_from_rom(struct athn_softc *,
+ struct ieee80211_channel *, struct ieee80211_channel *);
+Static uint8_t ar5416_reverse_bits(uint8_t, int);
+Static void ar5416_rw_bank6tpc(struct athn_softc *,
+ struct ieee80211_channel *, uint32_t *);
+Static void ar5416_rw_rfbits(uint32_t *, int, int, uint32_t, int);
+Static void ar5416_set_power_calib(struct athn_softc *,
+ struct ieee80211_channel *);
+Static int ar5416_set_synth(struct athn_softc *,
+ struct ieee80211_channel *, struct ieee80211_channel *);
+Static void ar5416_setup(struct athn_softc *);
+Static void ar5416_spur_mitigate(struct athn_softc *,
+ struct ieee80211_channel *, struct ieee80211_channel *);
+Static void ar9160_rw_addac(struct athn_softc *,
+ struct ieee80211_channel *, uint32_t *);
+
+PUBLIC int
+ar5416_attach(struct athn_softc *sc)
+{
+ sc->sc_eep_base = AR5416_EEP_START_LOC;
+ sc->sc_eep_size = sizeof(struct ar5416_eeprom);
+ sc->sc_def_nf = AR5416_PHY_CCA_MAX_GOOD_VALUE;
+ sc->sc_ngpiopins = 14;
+ sc->sc_led_pin = 1;
+ sc->sc_workaround = AR5416_WA_DEFAULT;
+ sc->sc_ops.setup = ar5416_setup;
+ sc->sc_ops.swap_rom = ar5416_swap_rom;
+ sc->sc_ops.init_from_rom = ar5416_init_from_rom;
+ sc->sc_ops.set_txpower = ar5416_set_txpower;
+ sc->sc_ops.set_synth = ar5416_set_synth;
+ sc->sc_ops.spur_mitigate = ar5416_spur_mitigate;
+ sc->sc_ops.get_spur_chans = ar5416_get_spur_chans;
+ if (AR_SREV_9160_10_OR_LATER(sc))
+ sc->sc_ini = &ar9160_ini;
+ else
+ sc->sc_ini = &ar5416_ini;
+ sc->sc_serdes = &ar5416_serdes;
+
+ return ar5008_attach(sc);
+}
+
+Static void
+ar5416_setup(struct athn_softc *sc)
+{
+ /* Select ADDAC programming. */
+ if (AR_SREV_9160_11(sc))
+ sc->sc_addac = &ar9160_1_1_addac;
+ else if (AR_SREV_9160_10_OR_LATER(sc))
+ sc->sc_addac = &ar9160_1_0_addac;
+ else if (AR_SREV_5416_22_OR_LATER(sc))
+ sc->sc_addac = &ar5416_2_2_addac;
+ else
+ sc->sc_addac = &ar5416_2_1_addac;
+}
+
+PUBLIC void
+ar5416_swap_rom(struct athn_softc *sc)
+{
+ struct ar5416_eeprom *eep = sc->sc_eep;
+ struct ar5416_modal_eep_header *modal;
+ int i, j;
+
+ for (i = 0; i < 2; i++) { /* Dual-band. */
+ modal = &eep->modalHeader[i];
+
+ modal->antCtrlCommon = bswap32(modal->antCtrlCommon);
+ for (j = 0; j < AR5416_MAX_CHAINS; j++) {
+ modal->antCtrlChain[j] =
+ bswap32(modal->antCtrlChain[j]);
+ }
+ for (j = 0; j < AR_EEPROM_MODAL_SPURS; j++) {
+ modal->spurChans[j].spurChan =
+ bswap16(modal->spurChans[j].spurChan);
+ }
+ }
+}
+
+PUBLIC const struct ar_spur_chan *
+ar5416_get_spur_chans(struct athn_softc *sc, int is2ghz)
+{
+ const struct ar5416_eeprom *eep = sc->sc_eep;
+
+ return eep->modalHeader[is2ghz].spurChans;
+}
+
+Static int
+ar5416_set_synth(struct athn_softc *sc, struct ieee80211_channel *c,
+ struct ieee80211_channel *extc)
+{
+ uint32_t phy, reg;
+ uint32_t freq = c->ic_freq;
+ uint8_t chansel;
+
+ phy = 0;
+ if (IEEE80211_IS_CHAN_2GHZ(c)) {
+ if (((freq - 2192) % 5) == 0) {
+ chansel = ((freq - 672) * 2 - 3040) / 10;
+ }
+ else if (((freq - 2224) % 5) == 0) {
+ chansel = ((freq - 704) * 2 - 3040) / 10;
+ phy |= AR5416_BMODE_SYNTH;
+ }
+ else
+ return EINVAL;
+ chansel <<= 2;
+
+ reg = AR_READ(sc, AR_PHY_CCK_TX_CTRL);
+ if (freq == 2484) /* Channel 14. */
+ reg |= AR_PHY_CCK_TX_CTRL_JAPAN;
+ else
+ reg &= ~AR_PHY_CCK_TX_CTRL_JAPAN;
+ AR_WRITE(sc, AR_PHY_CCK_TX_CTRL, reg);
+
+ /* Fix for orientation sensitivity issue. */
+ if (AR_SREV_5416(sc))
+ ar5416_force_bias(sc, c);
+ }
+ else {
+ if (freq >= 5120 && (freq % 20) == 0) {
+ chansel = (freq - 4800) / 20;
+ chansel <<= 2;
+ phy |= SM(AR5416_AMODE_REFSEL, 2);
+ }
+ else if ((freq % 10) == 0) {
+ chansel = (freq - 4800) / 10;
+ chansel <<= 1;
+ if (AR_SREV_9160_10_OR_LATER(sc))
+ phy |= SM(AR5416_AMODE_REFSEL, 1);
+ else
+ phy |= SM(AR5416_AMODE_REFSEL, 2);
+ }
+ else if ((freq % 5) == 0) {
+ chansel = (freq - 4800) / 5;
+ phy |= SM(AR5416_AMODE_REFSEL, 2);
+ }
+ else
+ return EINVAL;
+ }
+ chansel = ar5416_reverse_bits(chansel, 8);
+ phy |= chansel << 8 | 1 << 5 | 1;
+ DPRINTFN(DBG_RF, sc, "AR_PHY(0x37)=0x%08x\n", phy);
+ AR_WRITE(sc, AR_PHY(0x37), phy);
+ return 0;
+}
+
+Static void
+ar5416_init_from_rom(struct athn_softc *sc, struct ieee80211_channel *c,
+ struct ieee80211_channel *extc)
+{
+ static const uint32_t chainoffset[] = { 0x0000, 0x2000, 0x1000 };
+ const struct ar5416_eeprom *eep = sc->sc_eep;
+ const struct ar5416_modal_eep_header *modal;
+ uint32_t reg, offset;
+ uint8_t txRxAtten;
+ int i;
+
+ modal = &eep->modalHeader[IEEE80211_IS_CHAN_2GHZ(c)];
+
+ AR_WRITE(sc, AR_PHY_SWITCH_COM, modal->antCtrlCommon);
+
+ for (i = 0; i < AR5416_MAX_CHAINS; i++) {
+ if (AR_SREV_5416_20_OR_LATER(sc) &&
+ (sc->sc_rxchainmask == 0x5 || sc->sc_txchainmask == 0x5))
+ offset = chainoffset[i];
+ else
+ offset = i * 0x1000;
+
+ AR_WRITE(sc, AR_PHY_SWITCH_CHAIN_0 + offset,
+ modal->antCtrlChain[i]);
+
+ reg = AR_READ(sc, AR_PHY_TIMING_CTRL4_0 + offset);
+ reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF,
+ modal->iqCalICh[i]);
+ reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF,
+ modal->iqCalQCh[i]);
+ AR_WRITE(sc, AR_PHY_TIMING_CTRL4_0 + offset, reg);
+
+ if (i > 0 && !AR_SREV_5416_20_OR_LATER(sc))
+ continue;
+
+ if (sc->sc_eep_rev >= AR_EEP_MINOR_VER_3) {
+ reg = AR_READ(sc, AR_PHY_GAIN_2GHZ + offset);
+ reg = RW(reg, AR_PHY_GAIN_2GHZ_BSW_MARGIN,
+ modal->bswMargin[i]);
+ reg = RW(reg, AR_PHY_GAIN_2GHZ_BSW_ATTEN,
+ modal->bswAtten[i]);
+ AR_WRITE(sc, AR_PHY_GAIN_2GHZ + offset, reg);
+ }
+ if (sc->sc_eep_rev >= AR_EEP_MINOR_VER_3)
+ txRxAtten = modal->txRxAttenCh[i];
+ else /* Workaround for ROM versions < 14.3. */
+ txRxAtten = IEEE80211_IS_CHAN_2GHZ(c) ? 23 : 44;
+ reg = AR_READ(sc, AR_PHY_RXGAIN + offset);
+ reg = RW(reg, AR_PHY_RXGAIN_TXRX_ATTEN, txRxAtten);
+ AR_WRITE(sc, AR_PHY_RXGAIN + offset, reg);
+
+ reg = AR_READ(sc, AR_PHY_GAIN_2GHZ + offset);
+ reg = RW(reg, AR_PHY_GAIN_2GHZ_RXTX_MARGIN,
+ modal->rxTxMarginCh[i]);
+ AR_WRITE(sc, AR_PHY_GAIN_2GHZ + offset, reg);
+ }
+ reg = AR_READ(sc, AR_PHY_SETTLING);
+ reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->switchSettling);
+ AR_WRITE(sc, AR_PHY_SETTLING, reg);
+
+ reg = AR_READ(sc, AR_PHY_DESIRED_SZ);
+ reg = RW(reg, AR_PHY_DESIRED_SZ_ADC, modal->adcDesiredSize);
+ reg = RW(reg, AR_PHY_DESIRED_SZ_PGA, modal->pgaDesiredSize);
+ AR_WRITE(sc, AR_PHY_DESIRED_SZ, reg);
+
+ reg = SM(AR_PHY_RF_CTL4_TX_END_XPAA_OFF, modal->txEndToXpaOff);
+ reg |= SM(AR_PHY_RF_CTL4_TX_END_XPAB_OFF, modal->txEndToXpaOff);
+ reg |= SM(AR_PHY_RF_CTL4_FRAME_XPAA_ON, modal->txFrameToXpaOn);
+ reg |= SM(AR_PHY_RF_CTL4_FRAME_XPAB_ON, modal->txFrameToXpaOn);
+ AR_WRITE(sc, AR_PHY_RF_CTL4, reg);
+
+ reg = AR_READ(sc, AR_PHY_RF_CTL3);
+ reg = RW(reg, AR_PHY_TX_END_TO_A2_RX_ON, modal->txEndToRxOn);
+ AR_WRITE(sc, AR_PHY_RF_CTL3, reg);
+
+ reg = AR_READ(sc, AR_PHY_CCA(0));
+ reg = RW(reg, AR_PHY_CCA_THRESH62, modal->thresh62);
+ AR_WRITE(sc, AR_PHY_CCA(0), reg);
+
+ reg = AR_READ(sc, AR_PHY_EXT_CCA(0));
+ reg = RW(reg, AR_PHY_EXT_CCA_THRESH62, modal->thresh62);
+ AR_WRITE(sc, AR_PHY_EXT_CCA(0), reg);
+
+ if (sc->sc_eep_rev >= AR_EEP_MINOR_VER_2) {
+ reg = AR_READ(sc, AR_PHY_RF_CTL2);
+ reg = RW(reg, AR_PHY_TX_END_DATA_START,
+ modal->txFrameToDataStart);
+ reg = RW(reg, AR_PHY_TX_END_PA_ON, modal->txFrameToPaOn);
+ AR_WRITE(sc, AR_PHY_RF_CTL2, reg);
+ }
+#ifndef IEEE80211_NO_HT
+ if (sc->sc_eep_rev >= AR_EEP_MINOR_VER_3 && extc != NULL) {
+ /* Overwrite switch settling with HT-40 value. */
+ reg = AR_READ(sc, AR_PHY_SETTLING);
+ reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->swSettleHt40);
+ AR_WRITE(sc, AR_PHY_SETTLING, reg);
+ }
+#endif
+}
+
+PUBLIC int
+ar5416_init_calib(struct athn_softc *sc, struct ieee80211_channel *c,
+ struct ieee80211_channel *extc)
+{
+ int ntries;
+
+ if (AR_SREV_9280_10_OR_LATER(sc)) {
+ /* XXX Linux tests AR9287?! */
+ AR_CLRBITS(sc, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
+ AR_SETBITS(sc, AR_PHY_AGC_CONTROL,
+ AR_PHY_AGC_CONTROL_FLTR_CAL);
+ }
+ /* Calibrate the AGC. */
+ AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
+ /* Poll for offset calibration completion. */
+ for (ntries = 0; ntries < 10000; ntries++) {
+ if (!(AR_READ(sc, AR_PHY_AGC_CONTROL) &
+ AR_PHY_AGC_CONTROL_CAL))
+ break;
+ DELAY(10);
+ }
+ if (ntries == 10000)
+ return ETIMEDOUT;
+ if (AR_SREV_9280_10_OR_LATER(sc)) {
+ AR_SETBITS(sc, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
+ AR_CLRBITS(sc, AR_PHY_AGC_CONTROL,
+ AR_PHY_AGC_CONTROL_FLTR_CAL);
+ }
+ return 0;
+}
+
+Static void
+ar5416_get_pdadcs(struct athn_softc *sc, struct ieee80211_channel *c,
+ int chain, int nxpdgains, uint8_t overlap, uint8_t *boundaries,
+ uint8_t *pdadcs)
+{
+ const struct ar5416_eeprom *eep = sc->sc_eep;
+ const struct ar5416_cal_data_per_freq *pierdata;
+ const uint8_t *pierfreq;
+ struct athn_pier lopier, hipier;
+ int16_t delta;
+ uint8_t fbin, pwroff;
+ int i, lo, hi, npiers;
+
+ if (IEEE80211_IS_CHAN_2GHZ(c)) {
+ pierfreq = eep->calFreqPier2G;
+ pierdata = eep->calPierData2G[chain];
+ npiers = AR5416_NUM_2G_CAL_PIERS;
+ }
+ else {
+ pierfreq = eep->calFreqPier5G;
+ pierdata = eep->calPierData5G[chain];
+ npiers = AR5416_NUM_5G_CAL_PIERS;
+ }
+ /* Find channel in ROM pier table. */
+ fbin = athn_chan2fbin(c);
+ athn_get_pier_ival(fbin, pierfreq, npiers, &lo, &hi);
+
+ lopier.fbin = pierfreq[lo];
+ hipier.fbin = pierfreq[hi];
+ for (i = 0; i < nxpdgains; i++) {
+ lopier.pwr[i] = pierdata[lo].pwrPdg[i];
+ lopier.vpd[i] = pierdata[lo].vpdPdg[i];
+ hipier.pwr[i] = pierdata[lo].pwrPdg[i];
+ hipier.vpd[i] = pierdata[lo].vpdPdg[i];
+ }
+ ar5008_get_pdadcs(sc, fbin, &lopier, &hipier, nxpdgains,
+ AR5416_PD_GAIN_ICEPTS, overlap, boundaries, pdadcs);
+
+ if (!AR_SREV_9280_20_OR_LATER(sc))
+ return;
+
+ if (sc->sc_eep_rev >= AR_EEP_MINOR_VER_21)
+ pwroff = eep->baseEepHeader.pwrTableOffset;
+ else
+ pwroff = AR_PWR_TABLE_OFFSET_DB;
+ delta = (pwroff - AR_PWR_TABLE_OFFSET_DB) * 2; /* In half dB. */
+
+ /* Change the original gain boundaries setting. */
+ for (i = 0; i < nxpdgains; i++) {
+ /* XXX Possible overflows? */
+ boundaries[i] -= delta;
+ if (boundaries[i] > AR_MAX_RATE_POWER - overlap)
+ boundaries[i] = AR_MAX_RATE_POWER - overlap;
+ }
+ if (delta != 0) {
+ /* Shift the PDADC table to start at the new offset. */
+ for (i = 0; i < AR_NUM_PDADC_VALUES; i++)
+ pdadcs[i] = pdadcs[MIN(i + delta,
+ AR_NUM_PDADC_VALUES - 1)];
+ }
+}
+
+Static void
+ar5416_set_power_calib(struct athn_softc *sc, struct ieee80211_channel *c)
+{
+ static const uint32_t chainoffset[] = { 0x0000, 0x2000, 0x1000 };
+ const struct ar5416_eeprom *eep = sc->sc_eep;
+ const struct ar5416_modal_eep_header *modal;
+ uint8_t boundaries[AR_PD_GAINS_IN_MASK];
+ uint8_t pdadcs[AR_NUM_PDADC_VALUES];
+ uint8_t xpdgains[AR5416_NUM_PD_GAINS];
+ uint8_t overlap, txgain;
+ uint32_t reg, offset;
+ int i, j, nxpdgains;
+
+ modal = &eep->modalHeader[IEEE80211_IS_CHAN_2GHZ(c)];
+
+ if (sc->sc_eep_rev < AR_EEP_MINOR_VER_2) {
+ overlap = MS(AR_READ(sc, AR_PHY_TPCRG5),
+ AR_PHY_TPCRG5_PD_GAIN_OVERLAP);
+ }
+ else
+ overlap = modal->pdGainOverlap;
+
+ if ((sc->sc_flags & ATHN_FLAG_OLPC) && IEEE80211_IS_CHAN_2GHZ(c)) {
+ /* XXX not here. */
+ sc->sc_pdadc =
+ ((const struct ar_cal_data_per_freq_olpc *)
+ eep->calPierData2G[0])->vpdPdg[0][0];
+ }
+
+ nxpdgains = 0;
+ memset(xpdgains, 0, sizeof(xpdgains));
+ for (i = AR5416_PD_GAINS_IN_MASK - 1; i >= 0; i--) {
+ if (nxpdgains >= AR5416_NUM_PD_GAINS)
+ break; /* Can't happen. */
+ if (modal->xpdGain & (1 << i))
+ xpdgains[nxpdgains++] = i;
+ }
+ reg = AR_READ(sc, AR_PHY_TPCRG1);
+ reg = RW(reg, AR_PHY_TPCRG1_NUM_PD_GAIN, nxpdgains - 1);
+ reg = RW(reg, AR_PHY_TPCRG1_PD_GAIN_1, xpdgains[0]);
+ reg = RW(reg, AR_PHY_TPCRG1_PD_GAIN_2, xpdgains[1]);
+ reg = RW(reg, AR_PHY_TPCRG1_PD_GAIN_3, xpdgains[2]);
+ AR_WRITE(sc, AR_PHY_TPCRG1, reg);
+
+ for (i = 0; i < AR5416_MAX_CHAINS; i++) {
+ if (!(sc->sc_txchainmask & (1 << i)))
+ continue;
+
+ if (AR_SREV_5416_20_OR_LATER(sc) &&
+ (sc->sc_rxchainmask == 0x5 || sc->sc_txchainmask == 0x5))
+ offset = chainoffset[i];
+ else
+ offset = i * 0x1000;
+
+ if (sc->sc_flags & ATHN_FLAG_OLPC) {
+ ar9280_olpc_get_pdadcs(sc, c, i, boundaries,
+ pdadcs, &txgain);
+
+ reg = AR_READ(sc, AR_PHY_TX_PWRCTRL6_0);
+ reg = RW(reg, AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3);
+ AR_WRITE(sc, AR_PHY_TX_PWRCTRL6_0, reg);
+
+ reg = AR_READ(sc, AR_PHY_TX_PWRCTRL6_1);
+ reg = RW(reg, AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3);
+ AR_WRITE(sc, AR_PHY_TX_PWRCTRL6_1, reg);
+
+ reg = AR_READ(sc, AR_PHY_TX_PWRCTRL7);
+ reg = RW(reg, AR_PHY_TX_PWRCTRL_INIT_TX_GAIN, txgain);
+ AR_WRITE(sc, AR_PHY_TX_PWRCTRL7, reg);
+
+ overlap = 6;
+ }
+ else {
+ ar5416_get_pdadcs(sc, c, i, nxpdgains, overlap,
+ boundaries, pdadcs);
+ }
+ /* Write boundaries. */
+ if (i == 0 || AR_SREV_5416_20_OR_LATER(sc)) {
+ reg = SM(AR_PHY_TPCRG5_PD_GAIN_OVERLAP,
+ overlap);
+ reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1,
+ boundaries[0]);
+ reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2,
+ boundaries[1]);
+ reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3,
+ boundaries[2]);
+ reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4,
+ boundaries[3]);
+ AR_WRITE(sc, AR_PHY_TPCRG5 + offset, reg);
+ }
+ /* Write PDADC values. */
+ for (j = 0; j < AR_NUM_PDADC_VALUES; j += 4) {
+ AR_WRITE(sc, AR_PHY_PDADC_TBL_BASE + offset + j,
+ pdadcs[j + 0] << 0 |
+ pdadcs[j + 1] << 8 |
+ pdadcs[j + 2] << 16 |
+ pdadcs[j + 3] << 24);
+ }
+ }
+}
+
+PUBLIC void
+ar5416_set_txpower(struct athn_softc *sc, struct ieee80211_channel *c,
+ struct ieee80211_channel *extc)
+{
+ const struct ar5416_eeprom *eep = sc->sc_eep;
+ const struct ar5416_modal_eep_header *modal;
+ uint8_t tpow_cck[4], tpow_ofdm[4];
+#ifndef IEEE80211_NO_HT
+ uint8_t tpow_cck_ext[4], tpow_ofdm_ext[4];
+ uint8_t tpow_ht20[8], tpow_ht40[8];
+ uint8_t ht40inc;
+#endif
+ int16_t pwr = 0, pwroff, max_ant_gain, power[ATHN_POWER_COUNT];
+ uint8_t cckinc;
+ int i;
+
+ ar5416_set_power_calib(sc, c);
+
+ modal = &eep->modalHeader[IEEE80211_IS_CHAN_2GHZ(c)];
+
+ /* Compute transmit power reduction due to antenna gain. */
+ max_ant_gain = MAX(modal->antennaGainCh[0], modal->antennaGainCh[1]);
+ max_ant_gain = MAX(modal->antennaGainCh[2], max_ant_gain);
+ /* XXX */
+
+ /*
+ * Reduce scaled power by number of active chains to get per-chain
+ * transmit power level.
+ */
+ if (sc->sc_ntxchains == 2)
+ pwr -= AR_PWR_DECREASE_FOR_2_CHAIN;
+ else if (sc->sc_ntxchains == 3)
+ pwr -= AR_PWR_DECREASE_FOR_3_CHAIN;
+ if (pwr < 0)
+ pwr = 0;
+
+ if (IEEE80211_IS_CHAN_2GHZ(c)) {
+ /* Get CCK target powers. */
+ ar5008_get_lg_tpow(sc, c, AR_CTL_11B, eep->calTargetPowerCck,
+ AR5416_NUM_2G_CCK_TARGET_POWERS, tpow_cck);
+
+ /* Get OFDM target powers. */
+ ar5008_get_lg_tpow(sc, c, AR_CTL_11G, eep->calTargetPower2G,
+ AR5416_NUM_2G_20_TARGET_POWERS, tpow_ofdm);
+
+#ifndef IEEE80211_NO_HT
+ /* Get HT-20 target powers. */
+ ar5008_get_ht_tpow(sc, c, AR_CTL_2GHT20,
+ eep->calTargetPower2GHT20, AR5416_NUM_2G_20_TARGET_POWERS,
+ tpow_ht20);
+
+ if (extc != NULL) {
+ /* Get HT-40 target powers. */
+ ar5008_get_ht_tpow(sc, c, AR_CTL_2GHT40,
+ eep->calTargetPower2GHT40,
+ AR5416_NUM_2G_40_TARGET_POWERS, tpow_ht40);
+
+ /* Get secondary channel CCK target powers. */
+ ar5008_get_lg_tpow(sc, extc, AR_CTL_11B,
+ eep->calTargetPowerCck,
+ AR5416_NUM_2G_CCK_TARGET_POWERS, tpow_cck_ext);
+
+ /* Get secondary channel OFDM target powers. */
+ ar5008_get_lg_tpow(sc, extc, AR_CTL_11G,
+ eep->calTargetPower2G,
+ AR5416_NUM_2G_20_TARGET_POWERS, tpow_ofdm_ext);
+ }
+#endif
+ }
+ else {
+ /* Get OFDM target powers. */
+ ar5008_get_lg_tpow(sc, c, AR_CTL_11A, eep->calTargetPower5G,
+ AR5416_NUM_5G_20_TARGET_POWERS, tpow_ofdm);
+
+#ifndef IEEE80211_NO_HT
+ /* Get HT-20 target powers. */
+ ar5008_get_ht_tpow(sc, c, AR_CTL_5GHT20,
+ eep->calTargetPower5GHT20, AR5416_NUM_5G_20_TARGET_POWERS,
+ tpow_ht20);
+
+ if (extc != NULL) {
+ /* Get HT-40 target powers. */
+ ar5008_get_ht_tpow(sc, c, AR_CTL_5GHT40,
+ eep->calTargetPower5GHT40,
+ AR5416_NUM_5G_40_TARGET_POWERS, tpow_ht40);
+
+ /* Get secondary channel OFDM target powers. */
+ ar5008_get_lg_tpow(sc, extc, AR_CTL_11A,
+ eep->calTargetPower5G,
+ AR5416_NUM_5G_20_TARGET_POWERS, tpow_ofdm_ext);
+ }
+#endif
+ }
+
+ /* Compute CCK/OFDM delta. */
+ cckinc = (sc->sc_flags & ATHN_FLAG_OLPC) ? -2 : 0;
+
+ memset(power, 0, sizeof(power));
+ /* Shuffle target powers accross transmit rates. */
+ power[ATHN_POWER_OFDM6 ] =
+ power[ATHN_POWER_OFDM9 ] =
+ power[ATHN_POWER_OFDM12] =
+ power[ATHN_POWER_OFDM18] =
+ power[ATHN_POWER_OFDM24] = tpow_ofdm[0];
+ power[ATHN_POWER_OFDM36] = tpow_ofdm[1];
+ power[ATHN_POWER_OFDM48] = tpow_ofdm[2];
+ power[ATHN_POWER_OFDM54] = tpow_ofdm[3];
+ power[ATHN_POWER_XR ] = tpow_ofdm[0];
+ if (IEEE80211_IS_CHAN_2GHZ(c)) {
+ power[ATHN_POWER_CCK1_LP ] = tpow_cck[0] + cckinc;
+ power[ATHN_POWER_CCK2_LP ] =
+ power[ATHN_POWER_CCK2_SP ] = tpow_cck[1] + cckinc;
+ power[ATHN_POWER_CCK55_LP] =
+ power[ATHN_POWER_CCK55_SP] = tpow_cck[2] + cckinc;
+ power[ATHN_POWER_CCK11_LP] =
+ power[ATHN_POWER_CCK11_SP] = tpow_cck[3] + cckinc;
+ }
+#ifndef IEEE80211_NO_HT
+ for (i = 0; i < nitems(tpow_ht20); i++)
+ power[ATHN_POWER_HT20(i)] = tpow_ht20[i];
+ if (extc != NULL) {
+ /* Correct PAR difference between HT40 and HT20/Legacy. */
+ if (sc->sc_eep_rev >= AR_EEP_MINOR_VER_2)
+ ht40inc = modal->ht40PowerIncForPdadc;
+ else
+ ht40inc = AR_HT40_POWER_INC_FOR_PDADC;
+ for (i = 0; i < nitems(tpow_ht40); i++)
+ power[ATHN_POWER_HT40(i)] = tpow_ht40[i] + ht40inc;
+ power[ATHN_POWER_OFDM_DUP] = tpow_ht40[0];
+ power[ATHN_POWER_CCK_DUP ] = tpow_ht40[0] + cckinc;
+ power[ATHN_POWER_OFDM_EXT] = tpow_ofdm_ext[0];
+ if (IEEE80211_IS_CHAN_2GHZ(c))
+ power[ATHN_POWER_CCK_EXT] = tpow_cck_ext[0] + cckinc;
+ }
+#endif
+
+ if (AR_SREV_9280_10_OR_LATER(sc)) {
+ if (sc->sc_eep_rev >= AR_EEP_MINOR_VER_21)
+ pwroff = eep->baseEepHeader.pwrTableOffset;
+ else
+ pwroff = AR_PWR_TABLE_OFFSET_DB;
+ for (i = 0; i < ATHN_POWER_COUNT; i++)
+ power[i] -= pwroff * 2; /* In half dB. */
+ }
+ for (i = 0; i < ATHN_POWER_COUNT; i++) {
+ if (power[i] > AR_MAX_RATE_POWER)
+ power[i] = AR_MAX_RATE_POWER;
+ }
+
+ /* Write transmit power values to hardware. */
+ ar5008_write_txpower(sc, power);
+
+ /*
+ * Write transmit power substraction for dynamic chain changing
+ * and per-packet transmit power.
+ */
+ AR_WRITE(sc, AR_PHY_POWER_TX_SUB,
+ (modal->pwrDecreaseFor3Chain & 0x3f) << 6 |
+ (modal->pwrDecreaseFor2Chain & 0x3f));
+}
+
+Static void
+ar5416_spur_mitigate(struct athn_softc *sc, struct ieee80211_channel *c,
+ struct ieee80211_channel *extc)
+{
+ const struct ar_spur_chan *spurchans;
+ int i, spur, bin, spur_delta_phase, spur_freq_sd;
+
+ spurchans = sc->sc_ops.get_spur_chans(sc, IEEE80211_IS_CHAN_2GHZ(c));
+ for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
+ spur = spurchans[i].spurChan;
+ if (spur == AR_NO_SPUR)
+ return; /* XXX disable if it was enabled! */
+ spur -= c->ic_freq * 10;
+ /* Verify range +/-9.5MHz */
+ if (abs(spur) < 95)
+ break;
+ }
+ if (i == AR_EEPROM_MODAL_SPURS)
+ return; /* XXX disable if it was enabled! */
+ DPRINTFN(DBG_RF, sc, "enabling spur mitigation\n");
+
+ AR_SETBITS(sc, AR_PHY_TIMING_CTRL4_0,
+ AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
+ AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
+ AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
+ AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
+
+ AR_WRITE(sc, AR_PHY_SPUR_REG,
+ AR_PHY_SPUR_REG_MASK_RATE_CNTL |
+ AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
+ AR_PHY_SPUR_REG_MASK_RATE_SELECT |
+ AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
+ SM(AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, AR_SPUR_RSSI_THRESH));
+
+ spur_delta_phase = (spur * 524288) / 100;
+ if (IEEE80211_IS_CHAN_2GHZ(c))
+ spur_freq_sd = (spur * 2048) / 440;
+ else
+ spur_freq_sd = (spur * 2048) / 400;
+
+ AR_WRITE(sc, AR_PHY_TIMING11,
+ AR_PHY_TIMING11_USE_SPUR_IN_AGC |
+ SM(AR_PHY_TIMING11_SPUR_FREQ_SD, spur_freq_sd) |
+ SM(AR_PHY_TIMING11_SPUR_DELTA_PHASE, spur_delta_phase));
+
+ bin = spur * 32;
+ ar5008_set_viterbi_mask(sc, bin);
+}
+
+Static uint8_t
+ar5416_reverse_bits(uint8_t v, int nbits)
+{
+ KASSERT(nbits <= 8);
+ v = ((v >> 1) & 0x55) | ((v & 0x55) << 1);
+ v = ((v >> 2) & 0x33) | ((v & 0x33) << 2);
+ v = ((v >> 4) & 0x0f) | ((v & 0x0f) << 4);
+ return v >> (8 - nbits);
+}
+
+PUBLIC uint8_t
+ar5416_get_rf_rev(struct athn_softc *sc)
+{
+ uint8_t rev, reg;
+ int i;
+
+ /* Allow access to analog chips. */
+ AR_WRITE(sc, AR_PHY(0), 0x00000007);
+
+ AR_WRITE(sc, AR_PHY(0x36), 0x00007058);
+ for (i = 0; i < 8; i++)
+ AR_WRITE(sc, AR_PHY(0x20), 0x00010000);
+ reg = (AR_READ(sc, AR_PHY(256)) >> 24) & 0xff;
+ reg = (reg & 0xf0) >> 4 | (reg & 0x0f) << 4;
+
+ rev = ar5416_reverse_bits(reg, 8);
+ if ((rev & AR_RADIO_SREV_MAJOR) == 0)
+ rev = AR_RAD5133_SREV_MAJOR;
+ return rev;
+}
+
+/*
+ * Replace bits "off" to "off+nbits-1" in column "col" with the specified
+ * value.
+ */
+Static void
+ar5416_rw_rfbits(uint32_t *buf, int col, int off, uint32_t val, int nbits)
+{
+ int idx, bit;
+
+ KASSERT(off >= 1 && col < 4 && nbits <= 32);
+
+ off--; /* Starts at 1. */
+ while (nbits-- > 0) {
+ idx = off / 8;
+ bit = off % 8;
+ buf[idx] &= ~(1 << (bit + col * 8));
+ buf[idx] |= ((val >> nbits) & 1) << (bit + col * 8);
+ off++;
+ }
+}
+
+/*
+ * Overwrite db and ob based on ROM settings.
+ */
+Static void
+ar5416_rw_bank6tpc(struct athn_softc *sc, struct ieee80211_channel *c,
+ uint32_t *rwbank6tpc)
+{
+ const struct ar5416_eeprom *eep = sc->sc_eep;
+ const struct ar5416_modal_eep_header *modal;
+
+ if (IEEE80211_IS_CHAN_5GHZ(c)) {
+ modal = &eep->modalHeader[0];
+ /* 5GHz db in column 0, bits [200-202]. */
+ ar5416_rw_rfbits(rwbank6tpc, 0, 200, modal->db, 3);
+ /* 5GHz ob in column 0, bits [203-205]. */
+ ar5416_rw_rfbits(rwbank6tpc, 0, 203, modal->ob, 3);
+ }
+ else {
+ modal = &eep->modalHeader[1];
+ /* 2GHz db in column 0, bits [194-196]. */
+ ar5416_rw_rfbits(rwbank6tpc, 0, 194, modal->db, 3);
+ /* 2GHz ob in column 0, bits [197-199]. */
+ ar5416_rw_rfbits(rwbank6tpc, 0, 197, modal->ob, 3);
+ }
+}
+
+/*
+ * Program analog RF.
+ */
+PUBLIC void
+ar5416_rf_reset(struct athn_softc *sc, struct ieee80211_channel *c)
+{
+ const uint32_t *bank6tpc;
+ int i;
+
+ /* Bank 0. */
+ AR_WRITE(sc, 0x98b0, 0x1e5795e5);
+ AR_WRITE(sc, 0x98e0, 0x02008020);
+
+ /* Bank 1. */
+ AR_WRITE(sc, 0x98b0, 0x02108421);
+ AR_WRITE(sc, 0x98ec, 0x00000008);
+
+ /* Bank 2. */
+ AR_WRITE(sc, 0x98b0, 0x0e73ff17);
+ AR_WRITE(sc, 0x98e0, 0x00000420);
+
+ /* Bank 3. */
+ if (IEEE80211_IS_CHAN_5GHZ(c))
+ AR_WRITE(sc, 0x98f0, 0x01400018);
+ else
+ AR_WRITE(sc, 0x98f0, 0x01c00018);
+
+ /* Select the Bank 6 TPC values to use. */
+ if (AR_SREV_9160_10_OR_LATER(sc))
+ bank6tpc = ar9160_bank6tpc_vals;
+ else
+ bank6tpc = ar5416_bank6tpc_vals;
+ if (sc->sc_eep_rev >= AR_EEP_MINOR_VER_2) {
+ uint32_t *rwbank6tpc = sc->sc_rwbuf;
+
+ /* Copy values from .rodata to writable buffer. */
+ memcpy(rwbank6tpc, bank6tpc, 32 * sizeof(uint32_t));
+ ar5416_rw_bank6tpc(sc, c, rwbank6tpc);
+ bank6tpc = rwbank6tpc;
+ }
+ /* Bank 6 TPC. */
+ for (i = 0; i < 32; i++)
+ AR_WRITE(sc, 0x989c, bank6tpc[i]);
+ if (IEEE80211_IS_CHAN_5GHZ(c))
+ AR_WRITE(sc, 0x98d0, 0x0000000f);
+ else
+ AR_WRITE(sc, 0x98d0, 0x0010000f);
+
+ /* Bank 7. */
+ AR_WRITE(sc, 0x989c, 0x00000500);
+ AR_WRITE(sc, 0x989c, 0x00000800);
+ AR_WRITE(sc, 0x98cc, 0x0000000e);
+}
+
+PUBLIC void
+ar5416_reset_bb_gain(struct athn_softc *sc, struct ieee80211_channel *c)
+{
+ const uint32_t *pvals;
+ int i;
+
+ if (IEEE80211_IS_CHAN_2GHZ(c))
+ pvals = ar5416_bb_rfgain_vals_2g;
+ else
+ pvals = ar5416_bb_rfgain_vals_5g;
+ for (i = 0; i < 64; i++)
+ AR_WRITE(sc, AR_PHY_BB_RFGAIN(i), pvals[i]);
+}
+
+/*
+ * Fix orientation sensitivity issue on AR5416/2GHz by increasing
+ * rf_pwd_icsyndiv.
+ */
+Static void
+ar5416_force_bias(struct athn_softc *sc, struct ieee80211_channel *c)
+{
+ uint32_t *rwbank6 = sc->sc_rwbuf;
+ uint8_t bias;
+ int i;
+
+ KASSERT(IEEE80211_IS_CHAN_2GHZ(c));
+
+ /* Copy values from .rodata to writable buffer. */
+ memcpy(rwbank6, ar5416_bank6_vals, sizeof(ar5416_bank6_vals));
+
+ if (c->ic_freq < 2412)
+ bias = 0;
+ else if (c->ic_freq < 2422)
+ bias = 1;
+ else
+ bias = 2;
+ ar5416_reverse_bits(bias, 3);
+
+ /* Overwrite "rf_pwd_icsyndiv" (column 3, bits [181-183].) */
+ ar5416_rw_rfbits(rwbank6, 3, 181, bias, 3);
+
+ /* Write Bank 6. */
+ for (i = 0; i < 32; i++)
+ AR_WRITE(sc, 0x989c, rwbank6[i]);
+ AR_WRITE(sc, 0x98d0, 0x0010000f);
+}
+
+/*
+ * Overwrite XPA bias level based on ROM setting.
+ */
+Static void
+ar9160_rw_addac(struct athn_softc *sc, struct ieee80211_channel *c,
+ uint32_t *addac)
+{
+ struct ar5416_eeprom *eep = sc->sc_eep;
+ struct ar5416_modal_eep_header *modal;
+ uint8_t fbin, bias;
+ int i;
+
+ /* XXX xpaBiasLvlFreq values have not been endian-swapped? */
+
+ /* Get the XPA bias level to use for the specified channel. */
+ modal = &eep->modalHeader[IEEE80211_IS_CHAN_2GHZ(c)];
+ if (modal->xpaBiasLvl == 0xff) {
+ bias = modal->xpaBiasLvlFreq[0] >> 14;
+ fbin = athn_chan2fbin(c);
+ for (i = 1; i < 3; i++) {
+ if (modal->xpaBiasLvlFreq[i] == 0)
+ break;
+ if ((modal->xpaBiasLvlFreq[i] & 0xff) < fbin)
+ break;
+ bias = modal->xpaBiasLvlFreq[i] >> 14;
+ }
+ }
+ else
+ bias = modal->xpaBiasLvl & 0x3;
+
+ bias = ar5416_reverse_bits(bias, 2); /* Put in host bit-order. */
+ DPRINTFN(DBG_RF, sc, "bias level=%d\n", bias);
+ if (IEEE80211_IS_CHAN_2GHZ(c))
+ ar5416_rw_rfbits(addac, 0, 60, bias, 2);
+ else
+ ar5416_rw_rfbits(addac, 0, 55, bias, 2);
+}
+
+PUBLIC void
+ar5416_reset_addac(struct athn_softc *sc, struct ieee80211_channel *c)
+{
+ const struct athn_addac *addac = sc->sc_addac;
+ const uint32_t *pvals;
+ int i;
+
+ if (AR_SREV_9160(sc) && sc->sc_eep_rev >= AR_EEP_MINOR_VER_7) {
+ uint32_t *rwaddac = sc->sc_rwbuf;
+
+ /* Copy values from .rodata to writable buffer. */
+ memcpy(rwaddac, addac->vals, addac->nvals * sizeof(uint32_t));
+ ar9160_rw_addac(sc, c, rwaddac);
+ pvals = rwaddac;
+ }
+ else
+ pvals = addac->vals;
+ for (i = 0; i < addac->nvals; i++)
+ AR_WRITE(sc, 0x989c, pvals[i]);
+ AR_WRITE(sc, 0x98cc, 0); /* Finalize. */
+}
diff --git a/sys/dev/ic/arn5416.h b/sys/dev/ic/arn5416.h
new file mode 100644
index 00000000000..95889ce2ac7
--- /dev/null
+++ b/sys/dev/ic/arn5416.h
@@ -0,0 +1,44 @@
+/* $NetBSD: arn5416.h,v 1.1 2013/03/30 02:53:01 christos Exp $ */
+/*
+ * Copyright (c) 2001, 2004 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _IF_ARN5416_H_
+#define _IF_ARN5416_H_
+
+int ar5416_attach(struct athn_softc *);
+int ar5416_init_calib(struct athn_softc *,
+ struct ieee80211_channel *, struct ieee80211_channel *);
+uint8_t ar5416_get_rf_rev(struct athn_softc *);
+void ar5416_reset_addac(struct athn_softc *, struct ieee80211_channel *);
+void ar5416_rf_reset(struct athn_softc *, struct ieee80211_channel *);
+void ar5416_reset_bb_gain(struct athn_softc *, struct ieee80211_channel *);
+void ar5416_swap_rom(struct athn_softc *);
+void ar5416_set_txpower(struct athn_softc *, struct ieee80211_channel *,
+ struct ieee80211_channel *);
+const struct ar_spur_chan *
+ ar5416_get_spur_chans(struct athn_softc *, int);
+
+#endif /* _IF_ARN5416_H_ */
diff --git a/sys/dev/ic/arn5416reg.h b/sys/dev/ic/arn5416reg.h
new file mode 100644
index 00000000000..520fdce18cc
--- /dev/null
+++ b/sys/dev/ic/arn5416reg.h
@@ -0,0 +1,852 @@
+/* $NetBSD: arn5416reg.h,v 1.1 2013/03/30 02:53:01 christos Exp $ */
+/* $OpenBSD: ar5416reg.h,v 1.5 2012/10/20 09:54:20 stsp Exp $ */
+
+/*-
+ * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr>
+ * Copyright (c) 2008-2009 Atheros Communications Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _ARN5416REG_H_
+#define _ARN5416REG_H_
+
+#define AR5416_MAX_CHAINS 3
+
+#define AR5416_PHY_CCA_MAX_GOOD_VALUE ( -85)
+
+/*
+ * ROM layout used by AR5416, AR9160 and AR9280.
+ */
+#define AR5416_EEP_START_LOC 256
+#define AR5416_NUM_5G_CAL_PIERS 8
+#define AR5416_NUM_2G_CAL_PIERS 4
+#define AR5416_NUM_5G_20_TARGET_POWERS 8
+#define AR5416_NUM_5G_40_TARGET_POWERS 8
+#define AR5416_NUM_2G_CCK_TARGET_POWERS 3
+#define AR5416_NUM_2G_20_TARGET_POWERS 4
+#define AR5416_NUM_2G_40_TARGET_POWERS 4
+#define AR5416_NUM_CTLS 24
+#define AR5416_NUM_BAND_EDGES 8
+#define AR5416_NUM_PD_GAINS 4
+#define AR5416_PD_GAINS_IN_MASK 4
+#define AR5416_PD_GAIN_ICEPTS 5
+
+struct ar5416_base_eep_header {
+ uint16_t length;
+ uint16_t checksum;
+ uint16_t version;
+ uint8_t opCapFlags;
+ uint8_t eepMisc;
+ uint16_t regDmn[2];
+ uint8_t macAddr[6];
+ uint8_t rxMask;
+ uint8_t txMask;
+ uint16_t rfSilent;
+ uint16_t blueToothOptions;
+ uint16_t deviceCap;
+ uint32_t binBuildNumber;
+ uint8_t deviceType;
+ /* End of common header. */
+ uint8_t pwdclkind;
+ uint8_t fastClk5g;
+ uint8_t divChain;
+ uint8_t rxGainType;
+#define AR5416_EEP_RXGAIN_23DB_BACKOFF 0
+#define AR5416_EEP_RXGAIN_13DB_BACKOFF 1
+#define AR5416_EEP_RXGAIN_ORIG 2
+
+ uint8_t dacHiPwrMode_5G;
+ uint8_t openLoopPwrCntl;
+ uint8_t dacLpMode;
+ uint8_t txGainType;
+ uint8_t rcChainMask;
+ uint8_t desiredScaleCCK;
+ uint8_t pwrTableOffset;
+ uint8_t frac_n_5g;
+ uint8_t futureBase[21];
+} __packed;
+
+struct ar5416_modal_eep_header {
+ uint32_t antCtrlChain[AR5416_MAX_CHAINS];
+ uint32_t antCtrlCommon;
+ uint8_t antennaGainCh[AR5416_MAX_CHAINS];
+ uint8_t switchSettling;
+ uint8_t txRxAttenCh[AR5416_MAX_CHAINS];
+ uint8_t rxTxMarginCh[AR5416_MAX_CHAINS];
+ uint8_t adcDesiredSize;
+ uint8_t pgaDesiredSize;
+ uint8_t xlnaGainCh[AR5416_MAX_CHAINS];
+ uint8_t txEndToXpaOff;
+ uint8_t txEndToRxOn;
+ uint8_t txFrameToXpaOn;
+ uint8_t thresh62;
+ uint8_t noiseFloorThreshCh[AR5416_MAX_CHAINS];
+ uint8_t xpdGain;
+ uint8_t xpd;
+ uint8_t iqCalICh[AR5416_MAX_CHAINS];
+ uint8_t iqCalQCh[AR5416_MAX_CHAINS];
+ uint8_t pdGainOverlap;
+ uint8_t ob;
+ uint8_t db;
+ uint8_t xpaBiasLvl;
+ uint8_t pwrDecreaseFor2Chain;
+ uint8_t pwrDecreaseFor3Chain;
+ uint8_t txFrameToDataStart;
+ uint8_t txFrameToPaOn;
+ uint8_t ht40PowerIncForPdadc;
+ uint8_t bswAtten[AR5416_MAX_CHAINS];
+ uint8_t bswMargin[AR5416_MAX_CHAINS];
+ uint8_t swSettleHt40;
+ uint8_t xatten2Db[AR5416_MAX_CHAINS];
+ uint8_t xatten2Margin[AR5416_MAX_CHAINS];
+ uint8_t ob_ch1;
+ uint8_t db_ch1;
+ uint8_t flagBits;
+#define AR5416_EEP_FLAG_USEANT1 0x01
+#define AR5416_EEP_FLAG_FORCEXPAON 0x02
+#define AR5416_EEP_FLAG_LOCALBIAS 0x04
+#define AR5416_EEP_FLAG_FEMBANDSELECT 0x08
+#define AR5416_EEP_FLAG_XLNABUFIN 0x10
+#define AR5416_EEP_FLAG_XLNAISEL_M 0x60
+#define AR5416_EEP_FLAG_XLNAISEL_S 5
+#define AR5416_EEP_FLAG_XLNABUFMODE 0x80
+
+ uint8_t miscBits;
+#define AR5416_EEP_MISC_TX_DAC_SCALE_CCK_M 0x03
+#define AR5416_EEP_MISC_TX_DAC_SCALE_CCK_S 0
+#define AR5416_EEP_MISC_TX_CLIP_M 0xfc
+#define AR5416_EEP_MISC_TX_CLIP_S 2
+
+ uint16_t xpaBiasLvlFreq[3];
+ uint8_t futureModal[6];
+ struct ar_spur_chan spurChans[AR_EEPROM_MODAL_SPURS];
+} __packed;
+
+struct ar5416_cal_data_per_freq {
+ uint8_t pwrPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
+ uint8_t vpdPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
+} __packed;
+
+struct ar5416_cal_ctl_data {
+ struct ar_cal_ctl_edges
+ ctlEdges[AR5416_MAX_CHAINS][AR5416_NUM_BAND_EDGES];
+} __packed;
+
+struct ar5416_eeprom {
+ struct ar5416_base_eep_header baseEepHeader;
+ uint8_t custData[64];
+ struct ar5416_modal_eep_header modalHeader[2];
+ uint8_t calFreqPier5G[AR5416_NUM_5G_CAL_PIERS];
+ uint8_t calFreqPier2G[AR5416_NUM_2G_CAL_PIERS];
+ struct ar5416_cal_data_per_freq
+ calPierData5G[AR5416_MAX_CHAINS][AR5416_NUM_5G_CAL_PIERS];
+ struct ar5416_cal_data_per_freq
+ calPierData2G[AR5416_MAX_CHAINS][AR5416_NUM_2G_CAL_PIERS];
+ struct ar_cal_target_power_leg
+ calTargetPower5G[AR5416_NUM_5G_20_TARGET_POWERS];
+ struct ar_cal_target_power_ht
+ calTargetPower5GHT20[AR5416_NUM_5G_20_TARGET_POWERS];
+ struct ar_cal_target_power_ht
+ calTargetPower5GHT40[AR5416_NUM_5G_40_TARGET_POWERS];
+ struct ar_cal_target_power_leg
+ calTargetPowerCck[AR5416_NUM_2G_CCK_TARGET_POWERS];
+ struct ar_cal_target_power_leg
+ calTargetPower2G[AR5416_NUM_2G_20_TARGET_POWERS];
+ struct ar_cal_target_power_ht
+ calTargetPower2GHT20[AR5416_NUM_2G_20_TARGET_POWERS];
+ struct ar_cal_target_power_ht
+ calTargetPower2GHT40[AR5416_NUM_2G_40_TARGET_POWERS];
+ uint8_t ctlIndex[AR5416_NUM_CTLS];
+ struct ar5416_cal_ctl_data ctlData[AR5416_NUM_CTLS];
+ uint8_t padding;
+} __packed;
+
+/* Macro to "pack" registers to 16-bit to save some .rodata space. */
+#define P(x) (x)
+
+/*
+ * AR5416 initialization values.
+ */
+static const uint16_t ar5416_regs[] = {
+ P(0x01030), P(0x01070), P(0x010b0), P(0x010f0), P(0x08014),
+ P(0x0801c), P(0x08120), P(0x081d0), P(0x09804), P(0x09820),
+ P(0x09824), P(0x09828), P(0x09834), P(0x09838), P(0x09844),
+ P(0x09848), P(0x0a848), P(0x0b848), P(0x09850), P(0x09858),
+ P(0x0985c), P(0x09860), P(0x09864), P(0x09868), P(0x0986c),
+ P(0x09914), P(0x09918), P(0x09924), P(0x09944), P(0x09960),
+ P(0x0a960), P(0x0b960), P(0x09964), P(0x099bc), P(0x099c0),
+ P(0x099c4), P(0x099c8), P(0x099cc), P(0x099d0), P(0x099d4),
+ P(0x099d8), P(0x0a204), P(0x0a208), P(0x0a20c), P(0x0b20c),
+ P(0x0c20c), P(0x0a21c), P(0x0a230), P(0x0a274), P(0x0a300),
+ P(0x0a304), P(0x0a308), P(0x0a30c), P(0x0a310), P(0x0a314),
+ P(0x0a318), P(0x0a31c), P(0x0a320), P(0x0a324), P(0x0a328),
+ P(0x0a32c), P(0x0a330), P(0x0a334)
+};
+
+static const uint32_t ar5416_vals_5g20[] = {
+ 0x00000230, 0x00000168, 0x00000e60, 0x0000a000, 0x03e803e8,
+ 0x128d93a7, 0x08f04800, 0x00003210, 0x00000300, 0x02020200,
+ 0x00000e0e, 0x0a020001, 0x00000e0e, 0x00000007, 0x1372161e,
+ 0x001a6a65, 0x001a6a65, 0x001a6a65, 0x6c48b4e0, 0x7ec82d2e,
+ 0x31395d5e, 0x00049d18, 0x0001ce00, 0x409a4190, 0x050cb081,
+ 0x000007d0, 0x000001b8, 0xd0058a0b, 0xffb81020, 0x00000900,
+ 0x00000900, 0x00000900, 0x00000000, 0x001a0a00, 0x038919be,
+ 0x06336f77, 0x6af6532c, 0x08f186c8, 0x00046384, 0x00000000,
+ 0x00000000, 0x00000880, 0xd6be4788, 0x002ec1e0, 0x002ec1e0,
+ 0x002ec1e0, 0x1883800a, 0x00000000, 0x0a1a9caa, 0x18010000,
+ 0x30032602, 0x48073e06, 0x560b4c0a, 0x641a600f, 0x7a4f6e1b,
+ 0x8c5b7e5a, 0x9d0f96cf, 0xb51fa69f, 0xcb3fbd07, 0x0000d7bf,
+ 0x00000000, 0x00000000, 0x00000000
+};
+
+#ifndef IEEE80211_NO_HT
+static const uint32_t ar5416_vals_5g40[] = {
+ 0x00000460, 0x000002d0, 0x00001cc0, 0x00014000, 0x07d007d0,
+ 0x128d93cf, 0x08f04800, 0x00003210, 0x000003c4, 0x02020200,
+ 0x00000e0e, 0x0a020001, 0x00000e0e, 0x00000007, 0x1372161e,
+ 0x001a6a65, 0x001a6a65, 0x001a6a65, 0x6d48b4e0, 0x7ec82d2e,
+ 0x3139605e, 0x00049d18, 0x0001ce00, 0x409a4190, 0x050cb081,
+ 0x00000fa0, 0x00000370, 0xd0058a0b, 0xffb81020, 0x00000900,
+ 0x00000900, 0x00000900, 0x00000000, 0x001a0a00, 0x038919be,
+ 0x06336f77, 0x6af6532c, 0x08f186c8, 0x00046384, 0x00000000,
+ 0x00000000, 0x00000880, 0xd6be4788, 0x002ec1e0, 0x002ec1e0,
+ 0x002ec1e0, 0x1883800a, 0x00000000, 0x0a1a9caa, 0x18010000,
+ 0x30032602, 0x48073e06, 0x560b4c0a, 0x641a600f, 0x7a4f6e1b,
+ 0x8c5b7e5a, 0x9d0f96cf, 0xb51fa69f, 0xcb3fbcbf, 0x0000d7bf,
+ 0x00000000, 0x00000000, 0x00000000
+};
+
+static const uint32_t ar5416_vals_2g40[] = {
+ 0x000002c0, 0x00000318, 0x00007c70, 0x00016000, 0x10801600,
+ 0x12e013d7, 0x08f04810, 0x0000320a, 0x000003c4, 0x02020200,
+ 0x00000e0e, 0x0a020001, 0x00000e0e, 0x00000007, 0x137216a0,
+ 0x00197a68, 0x00197a68, 0x00197a68, 0x6d48b0de, 0x7ec82d2e,
+ 0x3139605e, 0x00049d18, 0x0001ce00, 0x409a4190, 0x050cb081,
+ 0x00001130, 0x00000268, 0xd0058a0b, 0xffb81020, 0x00012d80,
+ 0x00012d80, 0x00012d80, 0x00001120, 0x001a0a00, 0x038919be,
+ 0x06336f77, 0x6af6532c, 0x08f186c8, 0x00046384, 0x00000000,
+ 0x00000000, 0x00000880, 0xd03e4788, 0x002ac120, 0x002ac120,
+ 0x002ac120, 0x1883800a, 0x00000210, 0x0a1a7caa, 0x18010000,
+ 0x2e032402, 0x4a0a3c06, 0x621a540b, 0x764f6c1b, 0x845b7a5a,
+ 0x950f8ccf, 0xa5cf9b4f, 0xbddfaf1f, 0xd1ffc93f, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000
+};
+#endif
+
+static const uint32_t ar5416_vals_2g20[] = {
+ 0x00000160, 0x0000018c, 0x00003e38, 0x0000b000, 0x08400b00,
+ 0x12e013ab, 0x08f04810, 0x0000320a, 0x00000300, 0x02020200,
+ 0x00000e0e, 0x0a020001, 0x00000e0e, 0x00000007, 0x137216a0,
+ 0x00197a68, 0x00197a68, 0x00197a68, 0x6c48b0de, 0x7ec82d2e,
+ 0x31395d5e, 0x00049d18, 0x0001ce00, 0x409a4190, 0x050cb081,
+ 0x00000898, 0x00000134, 0xd0058a0b, 0xffb81020, 0x00012d80,
+ 0x00012d80, 0x00012d80, 0x00001120, 0x001a0a00, 0x038919be,
+ 0x06336f77, 0x6af6532c, 0x08f186c8, 0x00046384, 0x00000000,
+ 0x00000000, 0x00000880, 0xd03e4788, 0x002ac120, 0x002ac120,
+ 0x002ac120, 0x1883800a, 0x00000108, 0x0a1a7caa, 0x18010000,
+ 0x2e032402, 0x4a0a3c06, 0x621a540b, 0x764f6c1b, 0x845b7a5a,
+ 0x950f8ccf, 0xa5cf9b4f, 0xbddfaf1f, 0xd1ffc93f, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000
+};
+
+static const uint16_t ar5416_cm_regs[] = {
+ P(0x0000c), P(0x00030), P(0x00034), P(0x00040), P(0x00044),
+ P(0x00048), P(0x0004c), P(0x00050), P(0x00054), P(0x00800),
+ P(0x00804), P(0x00808), P(0x0080c), P(0x00810), P(0x00814),
+ P(0x00818), P(0x0081c), P(0x00820), P(0x00824), P(0x01040),
+ P(0x01044), P(0x01048), P(0x0104c), P(0x01050), P(0x01054),
+ P(0x01058), P(0x0105c), P(0x01060), P(0x01064), P(0x01230),
+ P(0x01270), P(0x01038), P(0x01078), P(0x010b8), P(0x010f8),
+ P(0x01138), P(0x01178), P(0x011b8), P(0x011f8), P(0x01238),
+ P(0x01278), P(0x012b8), P(0x012f8), P(0x01338), P(0x01378),
+ P(0x013b8), P(0x013f8), P(0x01438), P(0x01478), P(0x014b8),
+ P(0x014f8), P(0x01538), P(0x01578), P(0x015b8), P(0x015f8),
+ P(0x01638), P(0x01678), P(0x016b8), P(0x016f8), P(0x01738),
+ P(0x01778), P(0x017b8), P(0x017f8), P(0x0103c), P(0x0107c),
+ P(0x010bc), P(0x010fc), P(0x0113c), P(0x0117c), P(0x011bc),
+ P(0x011fc), P(0x0123c), P(0x0127c), P(0x012bc), P(0x012fc),
+ P(0x0133c), P(0x0137c), P(0x013bc), P(0x013fc), P(0x0143c),
+ P(0x0147c), P(0x04030), P(0x0403c), P(0x07010), P(0x07038),
+ P(0x08004), P(0x08008), P(0x0800c), P(0x08018), P(0x08020),
+ P(0x08038), P(0x0803c), P(0x08048), P(0x08054), P(0x08058),
+ P(0x0805c), P(0x08060), P(0x08064), P(0x080c0), P(0x080c4),
+ P(0x080c8), P(0x080cc), P(0x080d0), P(0x080d4), P(0x080d8),
+ P(0x080e0), P(0x080e4), P(0x080e8), P(0x080ec), P(0x080f0),
+ P(0x080f4), P(0x080f8), P(0x080fc), P(0x08100), P(0x08104),
+ P(0x08108), P(0x0810c), P(0x08110), P(0x08118), P(0x0811c),
+ P(0x08124), P(0x08128), P(0x0812c), P(0x08130), P(0x08134),
+ P(0x08138), P(0x0813c), P(0x08144), P(0x08168), P(0x0816c),
+ P(0x08170), P(0x08174), P(0x08178), P(0x0817c), P(0x081c4),
+ P(0x081ec), P(0x081f0), P(0x081f4), P(0x081f8), P(0x081fc),
+ P(0x08200), P(0x08204), P(0x08208), P(0x0820c), P(0x08210),
+ P(0x08214), P(0x08218), P(0x0821c), P(0x08220), P(0x08224),
+ P(0x08228), P(0x0822c), P(0x08230), P(0x08234), P(0x08238),
+ P(0x0823c), P(0x08240), P(0x08244), P(0x08248), P(0x0824c),
+ P(0x08250), P(0x08254), P(0x08258), P(0x0825c), P(0x08260),
+ P(0x08264), P(0x08270), P(0x08274), P(0x08278), P(0x0827c),
+ P(0x08284), P(0x08288), P(0x0828c), P(0x08294), P(0x08298),
+ P(0x08300), P(0x08304), P(0x08308), P(0x0830c), P(0x08310),
+ P(0x08314), P(0x08318), P(0x08328), P(0x0832c), P(0x08330),
+ P(0x08334), P(0x08338), P(0x0833c), P(0x08340), P(0x09808),
+ P(0x0980c), P(0x09810), P(0x09814), P(0x0981c), P(0x0982c),
+ P(0x09830), P(0x0983c), P(0x09840), P(0x0984c), P(0x09854),
+ P(0x09900), P(0x09904), P(0x09908), P(0x0990c), P(0x0991c),
+ P(0x09920), P(0x0a920), P(0x0b920), P(0x09928), P(0x0992c),
+ P(0x09934), P(0x09938), P(0x0993c), P(0x09948), P(0x0994c),
+ P(0x09954), P(0x09958), P(0x0c95c), P(0x0c968), P(0x09970),
+ P(0x09974), P(0x09978), P(0x0997c), P(0x09980), P(0x09984),
+ P(0x09988), P(0x0998c), P(0x09990), P(0x09994), P(0x09998),
+ P(0x0999c), P(0x099a0), P(0x099a4), P(0x099a8), P(0x099ac),
+ P(0x099b0), P(0x099dc), P(0x099e0), P(0x099e4), P(0x099e8),
+ P(0x099ec), P(0x099fc), P(0x09b00), P(0x09b04), P(0x09b08),
+ P(0x09b0c), P(0x09b10), P(0x09b14), P(0x09b18), P(0x09b1c),
+ P(0x09b20), P(0x09b24), P(0x09b28), P(0x09b2c), P(0x09b30),
+ P(0x09b34), P(0x09b38), P(0x09b3c), P(0x09b40), P(0x09b44),
+ P(0x09b48), P(0x09b4c), P(0x09b50), P(0x09b54), P(0x09b58),
+ P(0x09b5c), P(0x09b60), P(0x09b64), P(0x09b68), P(0x09b6c),
+ P(0x09b70), P(0x09b74), P(0x09b78), P(0x09b7c), P(0x09b80),
+ P(0x09b84), P(0x09b88), P(0x09b8c), P(0x09b90), P(0x09b94),
+ P(0x09b98), P(0x09b9c), P(0x09ba0), P(0x09ba4), P(0x09ba8),
+ P(0x09bac), P(0x09bb0), P(0x09bb4), P(0x09bb8), P(0x09bbc),
+ P(0x09bc0), P(0x09bc4), P(0x09bc8), P(0x09bcc), P(0x09bd0),
+ P(0x09bd4), P(0x09bd8), P(0x09bdc), P(0x09be0), P(0x09be4),
+ P(0x09be8), P(0x09bec), P(0x09bf0), P(0x09bf4), P(0x09bf8),
+ P(0x09bfc), P(0x0a210), P(0x0a214), P(0x0a218), P(0x0a220),
+ P(0x0a224), P(0x0a228), P(0x0a22c), P(0x0a234), P(0x0a238),
+ P(0x0a23c), P(0x0a240), P(0x0a244), P(0x0a248), P(0x0a24c),
+ P(0x0a250), P(0x0a254), P(0x0a258), P(0x0a25c), P(0x0a260),
+ P(0x0a268), P(0x0a26c), P(0x0b26c), P(0x0c26c), P(0x0d270),
+ P(0x0a278), P(0x0a27c), P(0x0a338), P(0x0a33c), P(0x0a340),
+ P(0x0a344), P(0x0a348), P(0x0a34c), P(0x0a350), P(0x0a354),
+ P(0x0a358), P(0x0d35c), P(0x0d360), P(0x0d364), P(0x0d368),
+ P(0x0d36c), P(0x0d370), P(0x0d374), P(0x0d378), P(0x0d37c),
+ P(0x0d380), P(0x0d384), P(0x0a388), P(0x0a38c), P(0x0a390),
+ P(0x0a394), P(0x0a398), P(0x0a39c), P(0x0a3a0), P(0x0a3a4),
+ P(0x0a3a8), P(0x0a3ac), P(0x0a3b0), P(0x0a3b4), P(0x0a3b8),
+ P(0x0a3bc), P(0x0a3c0), P(0x0a3c4), P(0x0a3c8), P(0x0a3cc),
+ P(0x0a3d0), P(0x0a3d4), P(0x0a3dc), P(0x0a3e0)
+};
+
+static const uint32_t ar5416_cm_vals[] = {
+ 0x00000000, 0x00020015, 0x00000005, 0x00000000, 0x00000008,
+ 0x00000008, 0x00000010, 0x00000000, 0x0000001f, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x002ffc0f,
+ 0x002ffc0f, 0x002ffc0f, 0x002ffc0f, 0x002ffc0f, 0x002ffc0f,
+ 0x002ffc0f, 0x002ffc0f, 0x002ffc0f, 0x002ffc0f, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000002, 0x00000002, 0x00000000, 0x000004c2,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000700, 0x00000000,
+ 0x00000000, 0x00000000, 0x40000000, 0x00000000, 0x00000000,
+ 0x000fc78f, 0x0000000f, 0x00000000, 0x2a82301a, 0x05dc01e0,
+ 0x1f402710, 0x01f40000, 0x00001e00, 0x00000000, 0x00400000,
+ 0xffffffff, 0x0000ffff, 0x003f3f3f, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00020000, 0x00020000, 0x00000001,
+ 0x00000052, 0x00000000, 0x00000168, 0x000100aa, 0x00003210,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0xffffffff, 0x00000000, 0x00000000,
+ 0x32143320, 0xfaa4fa50, 0x00000100, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00100000, 0x0010f400, 0x00000100, 0x0001e800,
+ 0x00000000, 0x00000000, 0x00000000, 0x400000ff, 0x00080922,
+ 0x88000010, 0x00000000, 0x40000000, 0x003e4180, 0x00000000,
+ 0x0000002c, 0x0000002c, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000007, 0x00000302,
+ 0x00000e00, 0x00070000, 0x00000000, 0x000107ff, 0x00000000,
+ 0xad848e19, 0x7d14e000, 0x9c0a9f6b, 0x00000000, 0x0000a000,
+ 0x00000000, 0x00200400, 0x206a002e, 0x1284233c, 0x00000859,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x10000fff,
+ 0x05100000, 0x05100000, 0x05100000, 0x00000001, 0x00000004,
+ 0x1e1f2022, 0x0a0b0c0d, 0x00000000, 0x9280b212, 0x00020028,
+ 0x5d50e188, 0x00081fff, 0x004b6a8e, 0x000003ce, 0x190fb515,
+ 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000001, 0x001fff00, 0x00000000,
+ 0x03051000, 0x00000000, 0x00000200, 0xaaaaaaaa, 0x3c466478,
+ 0x000000aa, 0x00001042, 0x00000000, 0x00000001, 0x00000002,
+ 0x00000003, 0x00000004, 0x00000005, 0x00000008, 0x00000009,
+ 0x0000000a, 0x0000000b, 0x0000000c, 0x0000000d, 0x00000010,
+ 0x00000011, 0x00000012, 0x00000013, 0x00000014, 0x00000015,
+ 0x00000018, 0x00000019, 0x0000001a, 0x0000001b, 0x0000001c,
+ 0x0000001d, 0x00000020, 0x00000021, 0x00000022, 0x00000023,
+ 0x00000024, 0x00000025, 0x00000028, 0x00000029, 0x0000002a,
+ 0x0000002b, 0x0000002c, 0x0000002d, 0x00000030, 0x00000031,
+ 0x00000032, 0x00000033, 0x00000034, 0x00000035, 0x00000035,
+ 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035,
+ 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035,
+ 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035,
+ 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000010,
+ 0x0000001a, 0x40806333, 0x00106c10, 0x009c4060, 0x018830c6,
+ 0x00000400, 0x00000bb5, 0x00000011, 0x20202020, 0x20202020,
+ 0x13c889af, 0x38490a20, 0x00007bb6, 0x0fff3ffc, 0x00000001,
+ 0x0000a000, 0x00000000, 0x0cc75380, 0x0f0f0f01, 0xdfa91f01,
+ 0x00000000, 0x0e79e5c6, 0x0e79e5c6, 0x0e79e5c6, 0x00820820,
+ 0x1ce739ce, 0x051701ce, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x3fffffff, 0x3fffffff, 0x3fffffff, 0x0003ffff,
+ 0x79a8aa1f, 0x07ffffef, 0x0fffffe7, 0x17ffffe5, 0x1fffffe4,
+ 0x37ffffe3, 0x3fffffe3, 0x57ffffe3, 0x5fffffe2, 0x7fffffe2,
+ 0x7f3c7bba, 0xf3307ff0, 0x08000000, 0x20202020, 0x20202020,
+ 0x1ce739ce, 0x000001ce, 0x00000001, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000246, 0x20202020,
+ 0x20202020, 0x20202020, 0x1ce739ce, 0x000001ce
+};
+
+static const struct athn_ini ar5416_ini = {
+ .nregs = __arraycount(ar5416_regs),
+ .regs = ar5416_regs,
+ .vals_5g20 = ar5416_vals_5g20,
+#ifndef IEEE80211_NO_HT
+ .vals_5g40 = ar5416_vals_5g40,
+ .vals_2g40 = ar5416_vals_2g40,
+#endif
+ .vals_2g20 = ar5416_vals_2g20,
+ .ncmregs = __arraycount(ar5416_cm_regs),
+ .cmregs = ar5416_cm_regs,
+ .cmvals = ar5416_cm_vals
+};
+
+/*
+ * AR9160 initialization values.
+ */
+static const uint16_t ar9160_regs[] = {
+ P(0x01030), P(0x01070), P(0x010b0), P(0x010f0), P(0x08014),
+ P(0x0801c), P(0x08120), P(0x081d0), P(0x09804), P(0x09820),
+ P(0x09824), P(0x09828), P(0x09834), P(0x09838), P(0x09844),
+ P(0x09848), P(0x0a848), P(0x0b848), P(0x09850), P(0x09858),
+ P(0x0985c), P(0x09860), P(0x09864), P(0x09868), P(0x0986c),
+ P(0x09914), P(0x09918), P(0x09924), P(0x09944), P(0x09960),
+ P(0x0a960), P(0x0b960), P(0x09964), P(0x0c968), P(0x099bc),
+ P(0x099c0), P(0x099c4), P(0x099c8), P(0x099cc), P(0x099d0),
+ P(0x099d4), P(0x099d8), P(0x0a204), P(0x0a208), P(0x0a20c),
+ P(0x0b20c), P(0x0c20c), P(0x0a21c), P(0x0a230), P(0x0a274),
+ P(0x0a300), P(0x0a304), P(0x0a308), P(0x0a30c), P(0x0a310),
+ P(0x0a314), P(0x0a318), P(0x0a31c), P(0x0a320), P(0x0a324),
+ P(0x0a328), P(0x0a32c), P(0x0a330), P(0x0a334)
+};
+
+static const uint32_t ar9160_vals_5g20[] = {
+ 0x00000230, 0x00000168, 0x00000e60, 0x0000a000, 0x03e803e8,
+ 0x128d93a7, 0x08f04800, 0x00003210, 0x00000300, 0x02020200,
+ 0x00000e0e, 0x0a020001, 0x00000e0e, 0x00000007, 0x0372161e,
+ 0x001a6a65, 0x001a6a65, 0x001a6a65, 0x6c48b4e2, 0x7ec82d2e,
+ 0x31395d5e, 0x00048d18, 0x0001ce00, 0x409a40d0, 0x050cb081,
+ 0x000007d0, 0x0000000a, 0xd00a8a07, 0xffb81020, 0x00009b40,
+ 0x00009b40, 0x00009b40, 0x00001120, 0x000003b5, 0x001a0600,
+ 0x038919be, 0x06336f77, 0x6af65329, 0x08f186c8, 0x00046384,
+ 0x00000000, 0x00000000, 0x00000880, 0xd6be4788, 0x002fc160,
+ 0x002fc160, 0x002fc160, 0x1883800a, 0x00000000, 0x0a1a9caa,
+ 0x18010000, 0x30032602, 0x48073e06, 0x560b4c0a, 0x641a600f,
+ 0x7a4f6e1b, 0x8c5b7e5a, 0x9d0f96cf, 0xb51fa69f, 0xcb3fbd07,
+ 0x0000d7bf, 0x00000000, 0x00000000, 0x00000000
+};
+
+#ifndef IEEE80211_NO_HT
+static const uint32_t ar9160_vals_5g40[] = {
+ 0x00000460, 0x000002d0, 0x00001cc0, 0x00014000, 0x07d007d0,
+ 0x128d93cf, 0x08f04800, 0x00003210, 0x000003c4, 0x02020200,
+ 0x00000e0e, 0x0a020001, 0x00000e0e, 0x00000007, 0x0372161e,
+ 0x001a6a65, 0x001a6a65, 0x001a6a65, 0x6d48b4e2, 0x7ec82d2e,
+ 0x3139605e, 0x00048d18, 0x0001ce00, 0x409a40d0, 0x050cb081,
+ 0x00000fa0, 0x00000014, 0xd00a8a07, 0xffb81020, 0x00009b40,
+ 0x00009b40, 0x00009b40, 0x00001120, 0x000003b5, 0x001a0600,
+ 0x038919be, 0x06336f77, 0x6af65329, 0x08f186c8, 0x00046384,
+ 0x00000000, 0x00000000, 0x00000880, 0xd6be4788, 0x002fc160,
+ 0x002fc160, 0x002fc160, 0x1883800a, 0x00000000, 0x0a1a9caa,
+ 0x18010000, 0x30032602, 0x48073e06, 0x560b4c0a, 0x641a600f,
+ 0x7a4f6e1b, 0x8c5b7e5a, 0x9d0f96cf, 0xb51fa69f, 0xcb3fbcbf,
+ 0x0000d7bf, 0x00000000, 0x00000000, 0x00000000
+};
+
+static const uint32_t ar9160_vals_2g40[] = {
+ 0x000002c0, 0x00000318, 0x00007c70, 0x00016000, 0x10801600,
+ 0x12e013d7, 0x08f04810, 0x0000320a, 0x000003c4, 0x02020200,
+ 0x00000e0e, 0x0a020001, 0x00000e0e, 0x00000007, 0x037216a0,
+ 0x00197a68, 0x00197a68, 0x00197a68, 0x6d48b0e2, 0x7ec82d2e,
+ 0x3139605e, 0x00048d20, 0x0001ce00, 0x409a40d0, 0x050cb081,
+ 0x00001130, 0x00000016, 0xd00a8a0d, 0xffb81020, 0x00009b40,
+ 0x00009b40, 0x00009b40, 0x00001120, 0x000003ce, 0x001a0c00,
+ 0x038919be, 0x06336f77, 0x6af65329, 0x08f186c8, 0x00046384,
+ 0x00000000, 0x00000000, 0x00000880, 0xd03e4788, 0x002ac120,
+ 0x002ac120, 0x002ac120, 0x1883800a, 0x00000210, 0x0a1a7caa,
+ 0x18010000, 0x2e032402, 0x4a0a3c06, 0x621a540b, 0x764f6c1b,
+ 0x845b7a5a, 0x950f8ccf, 0xa5cf9b4f, 0xbddfaf1f, 0xd1ffc93f,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000
+};
+#endif
+
+static const uint32_t ar9160_vals_2g20[] = {
+ 0x00000160, 0x0000018c, 0x00003e38, 0x0000b000, 0x08400b00,
+ 0x12e013ab, 0x08f04810, 0x0000320a, 0x00000300, 0x02020200,
+ 0x00000e0e, 0x0a020001, 0x00000e0e, 0x00000007, 0x037216a0,
+ 0x00197a68, 0x00197a68, 0x00197a68, 0x6c48b0e2, 0x7ec82d2e,
+ 0x31395d5e, 0x00048d20, 0x0001ce00, 0x409a40d0, 0x050cb081,
+ 0x00000898, 0x0000000b, 0xd00a8a0d, 0xffb81020, 0x00009b40,
+ 0x00009b40, 0x00009b40, 0x00001120, 0x000003ce, 0x001a0c00,
+ 0x038919be, 0x06336f77, 0x6af65329, 0x08f186c8, 0x00046384,
+ 0x00000000, 0x00000000, 0x00000880, 0xd03e4788, 0x002ac120,
+ 0x002ac120, 0x002ac120, 0x1883800a, 0x00000108, 0x0a1a7caa,
+ 0x18010000, 0x2e032402, 0x4a0a3c06, 0x621a540b, 0x764f6c1b,
+ 0x845b7a5a, 0x950f8ccf, 0xa5cf9b4f, 0xbddfaf1f, 0xd1ffc93f,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000
+};
+
+static const uint16_t ar9160_cm_regs[] = {
+ P(0x0000c), P(0x00030), P(0x00034), P(0x00040), P(0x00044),
+ P(0x00048), P(0x0004c), P(0x00050), P(0x00054), P(0x00800),
+ P(0x00804), P(0x00808), P(0x0080c), P(0x00810), P(0x00814),
+ P(0x00818), P(0x0081c), P(0x00820), P(0x00824), P(0x01040),
+ P(0x01044), P(0x01048), P(0x0104c), P(0x01050), P(0x01054),
+ P(0x01058), P(0x0105c), P(0x01060), P(0x01064), P(0x01230),
+ P(0x01270), P(0x01038), P(0x01078), P(0x010b8), P(0x010f8),
+ P(0x01138), P(0x01178), P(0x011b8), P(0x011f8), P(0x01238),
+ P(0x01278), P(0x012b8), P(0x012f8), P(0x01338), P(0x01378),
+ P(0x013b8), P(0x013f8), P(0x01438), P(0x01478), P(0x014b8),
+ P(0x014f8), P(0x01538), P(0x01578), P(0x015b8), P(0x015f8),
+ P(0x01638), P(0x01678), P(0x016b8), P(0x016f8), P(0x01738),
+ P(0x01778), P(0x017b8), P(0x017f8), P(0x0103c), P(0x0107c),
+ P(0x010bc), P(0x010fc), P(0x0113c), P(0x0117c), P(0x011bc),
+ P(0x011fc), P(0x0123c), P(0x0127c), P(0x012bc), P(0x012fc),
+ P(0x0133c), P(0x0137c), P(0x013bc), P(0x013fc), P(0x0143c),
+ P(0x0147c), P(0x04030), P(0x0403c), P(0x07010), P(0x07038),
+ P(0x08004), P(0x08008), P(0x0800c), P(0x08018), P(0x08020),
+ P(0x08038), P(0x0803c), P(0x08048), P(0x08054), P(0x08058),
+ P(0x0805c), P(0x08060), P(0x08064), P(0x080c0), P(0x080c4),
+ P(0x080c8), P(0x080cc), P(0x080d0), P(0x080d4), P(0x080d8),
+ P(0x080e0), P(0x080e4), P(0x080e8), P(0x080ec), P(0x080f0),
+ P(0x080f4), P(0x080f8), P(0x080fc), P(0x08100), P(0x08104),
+ P(0x08108), P(0x0810c), P(0x08110), P(0x08118), P(0x0811c),
+ P(0x08124), P(0x08128), P(0x0812c), P(0x08130), P(0x08134),
+ P(0x08138), P(0x0813c), P(0x08144), P(0x08168), P(0x0816c),
+ P(0x08170), P(0x08174), P(0x08178), P(0x0817c), P(0x081c4),
+ P(0x081ec), P(0x081f0), P(0x081f4), P(0x081f8), P(0x081fc),
+ P(0x08200), P(0x08204), P(0x08208), P(0x0820c), P(0x08210),
+ P(0x08214), P(0x08218), P(0x0821c), P(0x08220), P(0x08224),
+ P(0x08228), P(0x0822c), P(0x08230), P(0x08234), P(0x08238),
+ P(0x0823c), P(0x08240), P(0x08244), P(0x08248), P(0x0824c),
+ P(0x08250), P(0x08254), P(0x08258), P(0x0825c), P(0x08260),
+ P(0x08264), P(0x08270), P(0x08274), P(0x08278), P(0x0827c),
+ P(0x08284), P(0x08288), P(0x0828c), P(0x08294), P(0x08298),
+ P(0x08300), P(0x08304), P(0x08308), P(0x0830c), P(0x08310),
+ P(0x08314), P(0x08318), P(0x08328), P(0x0832c), P(0x08330),
+ P(0x08334), P(0x08338), P(0x0833c), P(0x08340), P(0x09808),
+ P(0x0980c), P(0x09810), P(0x09814), P(0x0981c), P(0x0982c),
+ P(0x09830), P(0x0983c), P(0x09840), P(0x0984c), P(0x09854),
+ P(0x09900), P(0x09904), P(0x09908), P(0x0990c), P(0x0991c),
+ P(0x09920), P(0x0a920), P(0x0b920), P(0x09928), P(0x0992c),
+ P(0x09934), P(0x09938), P(0x0993c), P(0x09948), P(0x0994c),
+ P(0x09954), P(0x09958), P(0x09940), P(0x0c95c), P(0x09970),
+ P(0x09974), P(0x09978), P(0x0997c), P(0x09980), P(0x09984),
+ P(0x09988), P(0x0998c), P(0x09990), P(0x09994), P(0x09998),
+ P(0x0999c), P(0x099a0), P(0x099a4), P(0x099a8), P(0x099ac),
+ P(0x099b0), P(0x099dc), P(0x099e0), P(0x099e4), P(0x099e8),
+ P(0x099ec), P(0x099fc), P(0x09b00), P(0x09b04), P(0x09b08),
+ P(0x09b0c), P(0x09b10), P(0x09b14), P(0x09b18), P(0x09b1c),
+ P(0x09b20), P(0x09b24), P(0x09b28), P(0x09b2c), P(0x09b30),
+ P(0x09b34), P(0x09b38), P(0x09b3c), P(0x09b40), P(0x09b44),
+ P(0x09b48), P(0x09b4c), P(0x09b50), P(0x09b54), P(0x09b58),
+ P(0x09b5c), P(0x09b60), P(0x09b64), P(0x09b68), P(0x09b6c),
+ P(0x09b70), P(0x09b74), P(0x09b78), P(0x09b7c), P(0x09b80),
+ P(0x09b84), P(0x09b88), P(0x09b8c), P(0x09b90), P(0x09b94),
+ P(0x09b98), P(0x09b9c), P(0x09ba0), P(0x09ba4), P(0x09ba8),
+ P(0x09bac), P(0x09bb0), P(0x09bb4), P(0x09bb8), P(0x09bbc),
+ P(0x09bc0), P(0x09bc4), P(0x09bc8), P(0x09bcc), P(0x09bd0),
+ P(0x09bd4), P(0x09bd8), P(0x09bdc), P(0x09be0), P(0x09be4),
+ P(0x09be8), P(0x09bec), P(0x09bf0), P(0x09bf4), P(0x09bf8),
+ P(0x09bfc), P(0x0a210), P(0x0a214), P(0x0a218), P(0x0a220),
+ P(0x0a224), P(0x0a228), P(0x0a22c), P(0x0a234), P(0x0a238),
+ P(0x0a23c), P(0x0a240), P(0x0a244), P(0x0a248), P(0x0a24c),
+ P(0x0a250), P(0x0a254), P(0x0a258), P(0x0a25c), P(0x0a260),
+ P(0x0a268), P(0x0a26c), P(0x0b26c), P(0x0c26c), P(0x0d270),
+ P(0x0a278), P(0x0a27c), P(0x0a338), P(0x0a33c), P(0x0a340),
+ P(0x0a344), P(0x0a348), P(0x0a34c), P(0x0a350), P(0x0a354),
+ P(0x0a358), P(0x0d35c), P(0x0d360), P(0x0d364), P(0x0d368),
+ P(0x0d36c), P(0x0d370), P(0x0d374), P(0x0d378), P(0x0d37c),
+ P(0x0d380), P(0x0d384), P(0x0a388), P(0x0a38c), P(0x0a390),
+ P(0x0a394), P(0x0a398), P(0x0a39c), P(0x0a3a0), P(0x0a3a4),
+ P(0x0a3a8), P(0x0a3ac), P(0x0a3b0), P(0x0a3b4), P(0x0a3b8),
+ P(0x0a3bc), P(0x0a3c0), P(0x0a3c4), P(0x0a3c8), P(0x0a3cc),
+ P(0x0a3d0), P(0x0a3d4), P(0x0a3dc), P(0x0a3e0)
+};
+
+static const uint32_t ar9160_cm_vals[] = {
+ 0x00000000, 0x00020015, 0x00000005, 0x00000000, 0x00000008,
+ 0x00000008, 0x00000010, 0x00000000, 0x0000001f, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x002ffc0f,
+ 0x002ffc0f, 0x002ffc0f, 0x002ffc0f, 0x002ffc0f, 0x002ffc0f,
+ 0x002ffc0f, 0x002ffc0f, 0x002ffc0f, 0x002ffc0f, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000002, 0x00000002, 0x00000020, 0x000004c2,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000700, 0x00000000,
+ 0x00000000, 0x00000000, 0x40000000, 0x00000000, 0x00000000,
+ 0x000fc78f, 0x0000000f, 0x00000000, 0x2a82301a, 0x05dc01e0,
+ 0x1f402710, 0x01f40000, 0x00001e00, 0x00000000, 0x00400000,
+ 0xffffffff, 0x0000ffff, 0x003f3f3f, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00020000, 0x00020000, 0x00000001,
+ 0x00000052, 0x00000000, 0x00000168, 0x000100aa, 0x00003210,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0xffffffff, 0x00000000, 0x00000000,
+ 0x32143320, 0xfaa4fa50, 0x00000100, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00100000, 0x0010f400, 0x00000100, 0x0001e800,
+ 0x00000000, 0x00000000, 0x00000000, 0x400000ff, 0x00080922,
+ 0x88a00010, 0x00000000, 0x40000000, 0x003e4180, 0x00000000,
+ 0x0000002c, 0x0000002c, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000007, 0x00000302,
+ 0x00000e00, 0x00ff0000, 0x00000000, 0x000107ff, 0x00000000,
+ 0xad848e19, 0x7d14e000, 0x9c0a9f6b, 0x00000000, 0x0000a000,
+ 0x00000000, 0x00200400, 0x206a01ae, 0x1284233c, 0x00000859,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x10000fff,
+ 0x05100000, 0x05100000, 0x05100000, 0x00000001, 0x00000004,
+ 0x1e1f2022, 0x0a0b0c0d, 0x00000000, 0x9280b212, 0x00020028,
+ 0x5f3ca3de, 0x2108ecff, 0x00750604, 0x004b6a8e, 0x190fb515,
+ 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000001, 0x201fff00, 0x006f0000,
+ 0x03051000, 0x00000000, 0x00000200, 0xaaaaaaaa, 0x3c466478,
+ 0x0cc80caa, 0x00001042, 0x00000000, 0x00000001, 0x00000002,
+ 0x00000003, 0x00000004, 0x00000005, 0x00000008, 0x00000009,
+ 0x0000000a, 0x0000000b, 0x0000000c, 0x0000000d, 0x00000010,
+ 0x00000011, 0x00000012, 0x00000013, 0x00000014, 0x00000015,
+ 0x00000018, 0x00000019, 0x0000001a, 0x0000001b, 0x0000001c,
+ 0x0000001d, 0x00000020, 0x00000021, 0x00000022, 0x00000023,
+ 0x00000024, 0x00000025, 0x00000028, 0x00000029, 0x0000002a,
+ 0x0000002b, 0x0000002c, 0x0000002d, 0x00000030, 0x00000031,
+ 0x00000032, 0x00000033, 0x00000034, 0x00000035, 0x00000035,
+ 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035,
+ 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035,
+ 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000035,
+ 0x00000035, 0x00000035, 0x00000035, 0x00000035, 0x00000010,
+ 0x0000001a, 0x40806333, 0x00106c10, 0x009c4060, 0x018830c6,
+ 0x00000400, 0x001a0bb5, 0x00000000, 0x20202020, 0x20202020,
+ 0x13c889af, 0x38490a20, 0x00007bb6, 0x0fff3ffc, 0x00000001,
+ 0x0000e000, 0x00000000, 0x0cc75380, 0x0f0f0f01, 0xdfa91f01,
+ 0x00000001, 0x0e79e5c6, 0x0e79e5c6, 0x0e79e5c6, 0x00820820,
+ 0x1ce739ce, 0x050701ce, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x3fffffff, 0x3fffffff, 0x3fffffff, 0x0003ffff,
+ 0x79bfaa03, 0x07ffffef, 0x0fffffe7, 0x17ffffe5, 0x1fffffe4,
+ 0x37ffffe3, 0x3fffffe3, 0x57ffffe3, 0x5fffffe2, 0x7fffffe2,
+ 0x7f3c7bba, 0xf3307ff0, 0x0c000000, 0x20202020, 0x20202020,
+ 0x1ce739ce, 0x000001ce, 0x00000001, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000246, 0x20202020,
+ 0x20202020, 0x20202020, 0x1ce739ce, 0x000001ce
+};
+
+static const struct athn_ini ar9160_ini = {
+ .nregs = __arraycount(ar9160_regs),
+ .regs = ar9160_regs,
+ .vals_5g20 = ar9160_vals_5g20,
+#ifndef IEEE80211_NO_HT
+ .vals_5g40 = ar9160_vals_5g40,
+ .vals_2g40 = ar9160_vals_2g40,
+#endif
+ .vals_2g20 = ar9160_vals_2g20,
+ .ncmregs = __arraycount(ar9160_cm_regs),
+ .cmregs = ar9160_cm_regs,
+ .cmvals = ar9160_cm_vals
+};
+
+/*
+ * BB/RF Gains common to AR5416 and AR9160.
+ */
+static const uint32_t ar5416_bb_rfgain_vals_5g[] = {
+ 0x00000000, 0x00000040, 0x00000080, 0x000001a1, 0x000001e1,
+ 0x00000021, 0x00000061, 0x00000168, 0x000001a8, 0x000001e8,
+ 0x00000028, 0x00000068, 0x00000189, 0x000001c9, 0x00000009,
+ 0x00000049, 0x00000089, 0x00000170, 0x000001b0, 0x000001f0,
+ 0x00000030, 0x00000070, 0x00000191, 0x000001d1, 0x00000011,
+ 0x00000051, 0x00000091, 0x000001b8, 0x000001f8, 0x00000038,
+ 0x00000078, 0x00000199, 0x000001d9, 0x00000019, 0x00000059,
+ 0x00000099, 0x000000d9, 0x000000f9, 0x000000f9, 0x000000f9,
+ 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9,
+ 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9,
+ 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9,
+ 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9,
+ 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9
+};
+
+static const uint32_t ar5416_bb_rfgain_vals_2g[] = {
+ 0x00000000, 0x00000040, 0x00000080, 0x00000141, 0x00000181,
+ 0x000001c1, 0x00000001, 0x00000041, 0x000001a8, 0x000001e8,
+ 0x00000028, 0x00000068, 0x000000a8, 0x00000169, 0x000001a9,
+ 0x000001e9, 0x00000029, 0x00000069, 0x00000190, 0x000001d0,
+ 0x00000010, 0x00000050, 0x00000090, 0x00000151, 0x00000191,
+ 0x000001d1, 0x00000011, 0x00000051, 0x00000198, 0x000001d8,
+ 0x00000018, 0x00000058, 0x00000098, 0x00000159, 0x00000199,
+ 0x000001d9, 0x00000019, 0x00000059, 0x00000099, 0x000000d9,
+ 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9,
+ 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9,
+ 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9,
+ 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9,
+ 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9
+};
+
+static const uint32_t ar5416_2_1_addac_vals[] = {
+ 0x00000000, 0x00000003, 0x00000000, 0x0000000c, 0x00000000,
+ 0x00000030, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000060, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000
+};
+
+static const struct athn_addac ar5416_2_1_addac = {
+ __arraycount(ar5416_2_1_addac_vals),
+ ar5416_2_1_addac_vals
+};
+
+static const uint32_t ar5416_2_2_addac_vals[] = {
+ 0x00000000, 0x00000003, 0x00000000, 0x0000000c, 0x00000000,
+ 0x00000030, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000060, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000058, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000
+};
+
+static const struct athn_addac ar5416_2_2_addac = {
+ __arraycount(ar5416_2_2_addac_vals),
+ ar5416_2_2_addac_vals
+};
+
+static const uint32_t ar9160_1_0_addac_vals[] = {
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x000000c0, 0x00000018, 0x00000004, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x000000c0, 0x00000019, 0x00000004, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000004, 0x00000003, 0x00000008,
+ 0x00000000
+};
+
+static const struct athn_addac ar9160_1_0_addac = {
+ __arraycount(ar9160_1_0_addac_vals),
+ ar9160_1_0_addac_vals
+};
+
+static const uint32_t ar9160_1_1_addac_vals[] = {
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x000000c0, 0x00000018, 0x00000004, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x000000c0, 0x00000019, 0x00000004, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000
+};
+
+static const struct athn_addac ar9160_1_1_addac = {
+ __arraycount(ar9160_1_1_addac_vals),
+ ar9160_1_1_addac_vals
+};
+
+static const uint32_t ar5416_bank6tpc_vals[] = {
+ 0x00000000, 0x00000000, 0x00000000, 0x00e00000, 0x005e0000,
+ 0x00120000, 0x00620000, 0x00020000, 0x00ff0000, 0x00ff0000,
+ 0x00ff0000, 0x40ff0000, 0x005f0000, 0x00870000, 0x00f90000,
+ 0x007b0000, 0x00ff0000, 0x00f50000, 0x00dc0000, 0x00110000,
+ 0x006100a8, 0x00423022, 0x201400df, 0x00c40002, 0x003000f2,
+ 0x00440016, 0x00410040, 0x0001805e, 0x0000c0ab, 0x000000e1,
+ 0x00007081, 0x000000d4
+};
+
+static const uint32_t ar9160_bank6tpc_vals[] = {
+ 0x00000000, 0x00000000, 0x00000000, 0x00e00000, 0x005e0000,
+ 0x00120000, 0x00620000, 0x00020000, 0x00ff0000, 0x00ff0000,
+ 0x00ff0000, 0x40ff0000, 0x005f0000, 0x00870000, 0x00f90000,
+ 0x007b0000, 0x00ff0000, 0x00f50000, 0x00dc0000, 0x00110000,
+ 0x006100a8, 0x00423022, 0x2014008f, 0x00c40002, 0x003000f2,
+ 0x00440016, 0x00410040, 0x0001805e, 0x0000c0ab, 0x000000e1,
+ 0x00007080, 0x000000d4
+};
+
+static const uint32_t ar5416_bank6_vals[] = {
+ 0x00000000, 0x00000000, 0x00000000, 0x00e00000, 0x005e0000,
+ 0x00120000, 0x00620000, 0x00020000, 0x00ff0000, 0x00ff0000,
+ 0x00ff0000, 0x40ff0000, 0x005f0000, 0x00870000, 0x00f90000,
+ 0x007b0000, 0x00ff0000, 0x00f50000, 0x00dc0000, 0x00110000,
+ 0x006100a8, 0x004210a2, 0x0014008f, 0x00c40003, 0x003000f2,
+ 0x00440016, 0x00410040, 0x0001805e, 0x0000c0ab, 0x000000f1,
+ 0x00002081, 0x000000d4
+};
+
+/*
+ * Serializer/Deserializer programming.
+ */
+
+static const uint32_t ar5416_serdes_regs[] = {
+ AR_PCIE_SERDES,
+ AR_PCIE_SERDES,
+ AR_PCIE_SERDES,
+ AR_PCIE_SERDES,
+ AR_PCIE_SERDES,
+ AR_PCIE_SERDES,
+ AR_PCIE_SERDES,
+ AR_PCIE_SERDES,
+ AR_PCIE_SERDES,
+ AR_PCIE_SERDES2
+};
+
+static const uint32_t ar5416_serdes_vals[] = {
+ 0x9248fc00,
+ 0x24924924,
+ /* RX shut off when elecidle is asserted. */
+ 0x28000039,
+ 0x53160824,
+ 0xe5980579,
+ 0x001defff,
+ 0x1aaabe40,
+ 0xbe105554,
+ 0x000e3007,
+ 0x00000000
+};
+
+static const struct athn_serdes ar5416_serdes = {
+ __arraycount(ar5416_serdes_vals),
+ ar5416_serdes_regs,
+ ar5416_serdes_vals,
+};
+
+#endif /* _ARN5416REG_H_ */
diff --git a/sys/dev/ic/arn9003.c b/sys/dev/ic/arn9003.c
new file mode 100644
index 00000000000..32f41078476
--- /dev/null
+++ b/sys/dev/ic/arn9003.c
@@ -0,0 +1,3447 @@
+/* $NetBSD: arn9003.c,v 1.1 2013/03/30 02:53:01 christos Exp $ */
+/* $OpenBSD: ar9003.c,v 1.25 2012/10/20 09:53:32 stsp Exp $ */
+
+/*-
+ * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr>
+ * Copyright (c) 2010 Atheros Communications Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+/*
+ * Driver for Atheros 802.11a/g/n chipsets.
+ * Routines for AR9003 family.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: arn9003.c,v 1.1 2013/03/30 02:53:01 christos Exp $");
+
+#include <sys/param.h>
+#include <sys/sockio.h>
+#include <sys/mbuf.h>
+#include <sys/kernel.h>
+#include <sys/socket.h>
+#include <sys/systm.h>
+#include <sys/malloc.h>
+#include <sys/queue.h>
+#include <sys/callout.h>
+#include <sys/conf.h>
+#include <sys/device.h>
+
+#include <sys/bus.h>
+#include <sys/endian.h>
+#include <sys/intr.h>
+
+#include <net/bpf.h>
+#include <net/if.h>
+#include <net/if_arp.h>
+#include <net/if_dl.h>
+#include <net/if_media.h>
+#include <net/if_types.h>
+
+#include <netinet/in.h>
+#include <netinet/in_systm.h>
+#include <netinet/in_var.h>
+#include <netinet/ip.h>
+
+#include <net80211/ieee80211_var.h>
+#include <net80211/ieee80211_amrr.h>
+#include <net80211/ieee80211_radiotap.h>
+
+#include <dev/ic/athnreg.h>
+#include <dev/ic/athnvar.h>
+#include <dev/ic/arn9003reg.h>
+#include <dev/ic/arn9003.h>
+
+#define Static static
+
+Static void ar9003_calib_iq(struct athn_softc *);
+Static int ar9003_calib_tx_iq(struct athn_softc *);
+Static int ar9003_compute_predistortion(struct athn_softc *,
+ const uint32_t *, const uint32_t *);
+Static void ar9003_disable_ofdm_weak_signal(struct athn_softc *);
+Static void ar9003_disable_phy(struct athn_softc *);
+Static int ar9003_dma_alloc(struct athn_softc *);
+Static void ar9003_dma_free(struct athn_softc *);
+Static void ar9003_do_calib(struct athn_softc *);
+Static void ar9003_do_noisefloor_calib(struct athn_softc *);
+Static void ar9003_enable_antenna_diversity(struct athn_softc *);
+Static void ar9003_enable_ofdm_weak_signal(struct athn_softc *);
+Static void ar9003_enable_predistorter(struct athn_softc *, int);
+Static int ar9003_find_rom(struct athn_softc *);
+Static void ar9003_force_txgain(struct athn_softc *, uint32_t);
+Static int ar9003_get_desired_txgain(struct athn_softc *, int, int);
+Static int ar9003_get_iq_corr(struct athn_softc *, int32_t[], int32_t[]);
+Static void ar9003_gpio_config_input(struct athn_softc *, int);
+Static void ar9003_gpio_config_output(struct athn_softc *, int, int);
+Static int ar9003_gpio_read(struct athn_softc *, int);
+Static void ar9003_gpio_write(struct athn_softc *, int, int);
+Static void ar9003_hw_init(struct athn_softc *, struct ieee80211_channel *,
+ struct ieee80211_channel *);
+Static void ar9003_init_baseband(struct athn_softc *);
+Static void ar9003_init_chains(struct athn_softc *);
+Static int ar9003_intr(struct athn_softc *);
+Static void ar9003_next_calib(struct athn_softc *);
+Static void ar9003_paprd_enable(struct athn_softc *);
+Static int ar9003_paprd_tx_tone(struct athn_softc *);
+Static void ar9003_paprd_tx_tone_done(struct athn_softc *);
+Static int ar9003_read_eep_data(struct athn_softc *, uint32_t, void *,
+ int);
+Static int ar9003_read_eep_word(struct athn_softc *, uint32_t,
+ uint16_t *);
+Static int ar9003_read_otp_data(struct athn_softc *, uint32_t, void *,
+ int);
+Static int ar9003_read_otp_word(struct athn_softc *, uint32_t,
+ uint32_t *);
+Static int ar9003_read_rom(struct athn_softc *);
+Static void ar9003_reset_rx_gain(struct athn_softc *,
+ struct ieee80211_channel *);
+Static void ar9003_reset_tx_gain(struct athn_softc *,
+ struct ieee80211_channel *);
+Static int ar9003_restore_rom_block(struct athn_softc *, uint8_t,
+ uint8_t, const uint8_t *, size_t);
+Static void ar9003_rf_bus_release(struct athn_softc *);
+Static int ar9003_rf_bus_request(struct athn_softc *);
+Static void ar9003_rfsilent_init(struct athn_softc *);
+Static int ar9003_rx_alloc(struct athn_softc *, int, int);
+Static void ar9003_rx_enable(struct athn_softc *);
+Static void ar9003_rx_free(struct athn_softc *, int);
+Static void ar9003_rx_intr(struct athn_softc *, int);
+Static int ar9003_rx_process(struct athn_softc *, int);
+Static void ar9003_rx_radiotap(struct athn_softc *, struct mbuf *,
+ struct ar_rx_status *);
+Static void ar9003_set_cck_weak_signal(struct athn_softc *, int);
+Static void ar9003_set_delta_slope(struct athn_softc *,
+ struct ieee80211_channel *, struct ieee80211_channel *);
+Static void ar9003_set_firstep_level(struct athn_softc *, int);
+Static void ar9003_set_noise_immunity_level(struct athn_softc *, int);
+Static void ar9003_set_phy(struct athn_softc *, struct ieee80211_channel *,
+ struct ieee80211_channel *);
+Static void ar9003_set_rf_mode(struct athn_softc *,
+ struct ieee80211_channel *);
+Static void ar9003_set_rxchains(struct athn_softc *);
+Static void ar9003_set_spur_immunity_level(struct athn_softc *, int);
+Static void ar9003_set_training_gain(struct athn_softc *, int);
+Static int ar9003_swba_intr(struct athn_softc *);
+Static int ar9003_tx(struct athn_softc *, struct mbuf *,
+ struct ieee80211_node *, int);
+Static int ar9003_tx_alloc(struct athn_softc *);
+Static void ar9003_tx_free(struct athn_softc *);
+Static void ar9003_tx_intr(struct athn_softc *);
+Static int ar9003_tx_process(struct athn_softc *);
+
+#ifdef notused
+Static void ar9003_bb_load_noisefloor(struct athn_softc *);
+Static void ar9003_get_noisefloor(struct athn_softc *,
+ struct ieee80211_channel *);
+Static void ar9003_paprd_calib(struct athn_softc *,
+ struct ieee80211_channel *);
+Static void ar9003_read_noisefloor(struct athn_softc *, int16_t *,
+ int16_t *);
+Static void ar9003_write_noisefloor(struct athn_softc *, int16_t *,
+ int16_t *);
+Static void ar9300_noisefloor_calib(struct athn_softc *);
+#endif /* notused */
+
+/*
+ * XXX: See if_iwn.c:MCLGETIalt() for a better solution.
+ * XXX: Put this in a header or in athn.c so it can be shared between
+ * ar5008.c and ar9003.c?
+ */
+static struct mbuf *
+MCLGETI(struct athn_softc *sc __unused, int how,
+ struct ifnet *ifp __unused, u_int size)
+{
+ struct mbuf *m;
+
+ MGETHDR(m, how, MT_DATA);
+ if (m == NULL)
+ return NULL;
+
+ MEXTMALLOC(m, size, how);
+ if ((m->m_flags & M_EXT) == 0) {
+ m_freem(m);
+ return NULL;
+ }
+ return m;
+}
+
+PUBLIC int
+ar9003_attach(struct athn_softc *sc)
+{
+ struct athn_ops *ops = &sc->sc_ops;
+ int error;
+
+ /* Set callbacks for AR9003 family. */
+ ops->gpio_read = ar9003_gpio_read;
+ ops->gpio_write = ar9003_gpio_write;
+ ops->gpio_config_input = ar9003_gpio_config_input;
+ ops->gpio_config_output = ar9003_gpio_config_output;
+ ops->rfsilent_init = ar9003_rfsilent_init;
+
+ ops->dma_alloc = ar9003_dma_alloc;
+ ops->dma_free = ar9003_dma_free;
+ ops->rx_enable = ar9003_rx_enable;
+ ops->intr = ar9003_intr;
+ ops->tx = ar9003_tx;
+
+ ops->set_rf_mode = ar9003_set_rf_mode;
+ ops->rf_bus_request = ar9003_rf_bus_request;
+ ops->rf_bus_release = ar9003_rf_bus_release;
+ ops->set_phy = ar9003_set_phy;
+ ops->set_delta_slope = ar9003_set_delta_slope;
+ ops->enable_antenna_diversity = ar9003_enable_antenna_diversity;
+ ops->init_baseband = ar9003_init_baseband;
+ ops->disable_phy = ar9003_disable_phy;
+ ops->set_rxchains = ar9003_set_rxchains;
+ ops->noisefloor_calib = ar9003_do_noisefloor_calib;
+ ops->do_calib = ar9003_do_calib;
+ ops->next_calib = ar9003_next_calib;
+ ops->hw_init = ar9003_hw_init;
+
+ ops->set_noise_immunity_level = ar9003_set_noise_immunity_level;
+ ops->enable_ofdm_weak_signal = ar9003_enable_ofdm_weak_signal;
+ ops->disable_ofdm_weak_signal = ar9003_disable_ofdm_weak_signal;
+ ops->set_cck_weak_signal = ar9003_set_cck_weak_signal;
+ ops->set_firstep_level = ar9003_set_firstep_level;
+ ops->set_spur_immunity_level = ar9003_set_spur_immunity_level;
+
+ /* Set MAC registers offsets. */
+ sc->sc_obs_off = AR_OBS;
+ sc->sc_gpio_input_en_off = AR_GPIO_INPUT_EN_VAL;
+
+ if (!(sc->sc_flags & ATHN_FLAG_PCIE))
+ athn_config_nonpcie(sc);
+ else
+ athn_config_pcie(sc);
+
+ /* Determine ROM type and location. */
+ if ((error = ar9003_find_rom(sc)) != 0) {
+ printf("%s: could not find ROM\n", device_xname(sc->sc_dev));
+ return error;
+ }
+ /* Read entire ROM content in memory. */
+ if ((error = ar9003_read_rom(sc)) != 0) {
+ printf("%s: could not read ROM\n", device_xname(sc->sc_dev));
+ return error;
+ }
+
+ /* Determine if it is a non-enterprise AR9003 card. */
+ if (AR_READ(sc, AR_ENT_OTP) & AR_ENT_OTP_MPSD)
+ sc->sc_flags |= ATHN_FLAG_NON_ENTERPRISE;
+
+ ops->setup(sc);
+ return 0;
+}
+
+/*
+ * Read 16-bit word from EEPROM.
+ */
+Static int
+ar9003_read_eep_word(struct athn_softc *sc, uint32_t addr, uint16_t *val)
+{
+ uint32_t reg;
+ int ntries;
+
+ reg = AR_READ(sc, AR_EEPROM_OFFSET(addr));
+ for (ntries = 0; ntries < 1000; ntries++) {
+ reg = AR_READ(sc, AR_EEPROM_STATUS_DATA);
+ if (!(reg & (AR_EEPROM_STATUS_DATA_BUSY |
+ AR_EEPROM_STATUS_DATA_PROT_ACCESS))) {
+ *val = MS(reg, AR_EEPROM_STATUS_DATA_VAL);
+ return 0;
+ }
+ DELAY(10);
+ }
+ *val = 0xffff;
+ return ETIMEDOUT;
+}
+
+/*
+ * Read an arbitrary number of bytes at a specified address in EEPROM.
+ * NB: The address may not be 16-bit aligned.
+ */
+Static int
+ar9003_read_eep_data(struct athn_softc *sc, uint32_t addr, void *buf, int len)
+{
+ uint8_t *dst = buf;
+ uint16_t val;
+ int error;
+
+ if (len > 0 && (addr & 1)) {
+ /* Deal with non-aligned reads. */
+ addr >>= 1;
+ error = ar9003_read_eep_word(sc, addr, &val);
+ if (error != 0)
+ return error;
+ *dst++ = val & 0xff;
+ addr--;
+ len--;
+ }
+ else
+ addr >>= 1;
+ for (; len >= 2; addr--, len -= 2) {
+ error = ar9003_read_eep_word(sc, addr, &val);
+ if (error != 0)
+ return error;
+ *dst++ = val >> 8;
+ *dst++ = val & 0xff;
+ }
+ if (len > 0) {
+ error = ar9003_read_eep_word(sc, addr, &val);
+ if (error != 0)
+ return error;
+ *dst++ = val >> 8;
+ }
+ return 0;
+}
+
+/*
+ * Read 32-bit word from OTPROM.
+ */
+Static int
+ar9003_read_otp_word(struct athn_softc *sc, uint32_t addr, uint32_t *val)
+{
+ uint32_t reg;
+ int ntries;
+
+ reg = AR_READ(sc, AR_OTP_BASE(addr));
+ for (ntries = 0; ntries < 1000; ntries++) {
+ reg = AR_READ(sc, AR_OTP_STATUS);
+ if (MS(reg, AR_OTP_STATUS_TYPE) == AR_OTP_STATUS_VALID) {
+ *val = AR_READ(sc, AR_OTP_READ_DATA);
+ return 0;
+ }
+ DELAY(10);
+ }
+ return ETIMEDOUT;
+}
+
+/*
+ * Read an arbitrary number of bytes at a specified address in OTPROM.
+ * NB: The address may not be 32-bit aligned.
+ */
+Static int
+ar9003_read_otp_data(struct athn_softc *sc, uint32_t addr, void *buf, int len)
+{
+ uint8_t *dst = buf;
+ uint32_t val;
+ int error;
+
+ /* NB: not optimal for non-aligned reads, but correct. */
+ for (; len > 0; addr--, len--) {
+ error = ar9003_read_otp_word(sc, addr >> 2, &val);
+ if (error != 0)
+ return error;
+ *dst++ = (val >> ((addr & 3) * 8)) & 0xff;
+ }
+ return 0;
+}
+
+/*
+ * Determine if the chip has an external EEPROM or an OTPROM and its size.
+ */
+Static int
+ar9003_find_rom(struct athn_softc *sc)
+{
+ struct athn_ops *ops = &sc->sc_ops;
+ uint32_t hdr;
+ int error;
+
+ /* Try EEPROM. */
+ ops->read_rom_data = ar9003_read_eep_data;
+
+ sc->sc_eep_size = AR_SREV_9485(sc) ? 4096 : 1024;
+ sc->sc_eep_base = sc->sc_eep_size - 1;
+ error = ops->read_rom_data(sc, sc->sc_eep_base, &hdr, sizeof(hdr));
+ if (error == 0 && hdr != 0 && hdr != 0xffffffff)
+ return 0;
+
+ sc->sc_eep_size = 512;
+ sc->sc_eep_base = sc->sc_eep_size - 1;
+ error = ops->read_rom_data(sc, sc->sc_eep_base, &hdr, sizeof(hdr));
+ if (error == 0 && hdr != 0 && hdr != 0xffffffff)
+ return 0;
+
+ /* Try OTPROM. */
+ ops->read_rom_data = ar9003_read_otp_data;
+
+ sc->sc_eep_size = 1024;
+ sc->sc_eep_base = sc->sc_eep_size - 1;
+ error = ops->read_rom_data(sc, sc->sc_eep_base, &hdr, sizeof(hdr));
+ if (error == 0 && hdr != 0 && hdr != 0xffffffff)
+ return 0;
+
+ sc->sc_eep_size = 512;
+ sc->sc_eep_base = sc->sc_eep_size - 1;
+ error = ops->read_rom_data(sc, sc->sc_eep_base, &hdr, sizeof(hdr));
+ if (error == 0 && hdr != 0 && hdr != 0xffffffff)
+ return 0;
+
+ return EIO; /* Not found. */
+}
+
+Static int
+ar9003_restore_rom_block(struct athn_softc *sc, uint8_t alg, uint8_t ref,
+ const uint8_t *buf, size_t len)
+{
+ const uint8_t *def, *ptr, *end;
+ uint8_t *eep = sc->sc_eep;
+ size_t off, clen;
+
+ if (alg == AR_EEP_COMPRESS_BLOCK) {
+ /* Block contains chunks that shadow ROM template. */
+ def = sc->sc_ops.get_rom_template(sc, ref);
+ if (def == NULL) {
+ DPRINTFN(DBG_INIT, sc, "unknown template image %d\n",
+ ref);
+ return EINVAL;
+ }
+ /* Start with template. */
+ memcpy(eep, def, sc->sc_eep_size);
+ /* Shadow template with chunks. */
+ off = 0; /* Offset in ROM image. */
+ ptr = buf; /* Offset in block. */
+ end = buf + len;
+ /* Process chunks. */
+ while (ptr + 2 <= end) {
+ off += *ptr++; /* Gap with previous chunk. */
+ clen = *ptr++; /* Chunk length. */
+ /* Make sure block is large enough. */
+ if (ptr + clen > end)
+ return EINVAL;
+ /* Make sure chunk fits in ROM image. */
+ if (off + clen > sc->sc_eep_size)
+ return EINVAL;
+ /* Restore chunk. */
+ DPRINTFN(DBG_INIT, sc, "ROM chunk @%zd/%zd\n",
+ off, clen);
+ memcpy(&eep[off], ptr, clen);
+ ptr += clen;
+ off += clen;
+ }
+ }
+ else if (alg == AR_EEP_COMPRESS_NONE) {
+ /* Block contains full ROM image. */
+ if (len != sc->sc_eep_size) {
+ DPRINTFN(DBG_INIT, sc, "block length mismatch %zd\n",
+ len);
+ return EINVAL;
+ }
+ memcpy(eep, buf, len);
+ }
+ return 0;
+}
+
+Static int
+ar9003_read_rom(struct athn_softc *sc)
+{
+ struct athn_ops *ops = &sc->sc_ops;
+ uint8_t *buf, *ptr, alg, ref;
+ uint16_t sum, rsum;
+ uint32_t hdr;
+ int error, addr;
+ size_t len, i, j;
+
+ /* Allocate space to store ROM in host memory. */
+ sc->sc_eep = malloc(sc->sc_eep_size, M_DEVBUF, M_NOWAIT);
+ if (sc->sc_eep == NULL)
+ return ENOMEM;
+
+ /* Allocate temporary buffer to store ROM blocks. */
+ buf = malloc(2048, M_DEVBUF, M_NOWAIT);
+ if (buf == NULL)
+ return ENOMEM;
+
+ /* Restore vendor-specified ROM blocks. */
+ addr = sc->sc_eep_base;
+ for (i = 0; i < 100; i++) {
+ /* Read block header. */
+ error = ops->read_rom_data(sc, addr, &hdr, sizeof(hdr));
+ if (error != 0)
+ break;
+ if (hdr == 0 || hdr == 0xffffffff)
+ break;
+ addr -= sizeof(hdr);
+
+ /* Extract bits from header. */
+ ptr = (uint8_t *)&hdr;
+ alg = (ptr[0] & 0xe0) >> 5;
+ ref = (ptr[1] & 0x80) >> 2 | (ptr[0] & 0x1f);
+ len = (ptr[1] & 0x7f) << 4 | (ptr[2] & 0xf0) >> 4;
+ DPRINTFN(DBG_INIT, sc,
+ "ROM block %zd: alg=%d ref=%d len=%zd\n",
+ i, alg, ref, len);
+
+ /* Read block data (len <= 0x7ff). */
+ error = ops->read_rom_data(sc, addr, buf, len);
+ if (error != 0)
+ break;
+ addr -= len;
+
+ /* Read block checksum. */
+ error = ops->read_rom_data(sc, addr, &sum, sizeof(sum));
+ if (error != 0)
+ break;
+ addr -= sizeof(sum);
+
+ /* Compute block checksum. */
+ rsum = 0;
+ for (j = 0; j < len; j++)
+ rsum += buf[j];
+ /* Compare to that in ROM. */
+ if (le16toh(sum) != rsum) {
+ DPRINTFN(DBG_INIT, sc,
+ "bad block checksum 0x%x/0x%x\n",
+ le16toh(sum), rsum);
+ continue; /* Skip bad block. */
+ }
+ /* Checksum is correct, restore block. */
+ ar9003_restore_rom_block(sc, alg, ref, buf, len);
+ }
+#if BYTE_ORDER == BIG_ENDIAN
+ /* NB: ROM is always little endian. */
+ if (error == 0)
+ ops->swap_rom(sc);
+#endif
+ free(buf, M_DEVBUF);
+ return error;
+}
+
+/*
+ * Access to General Purpose Input/Output ports.
+ */
+Static int
+ar9003_gpio_read(struct athn_softc *sc, int pin)
+{
+
+ KASSERT(pin < sc->sc_ngpiopins);
+ return ((AR_READ(sc, AR_GPIO_IN) & AR9300_GPIO_IN_VAL) &
+ (1 << pin)) != 0;
+}
+
+Static void
+ar9003_gpio_write(struct athn_softc *sc, int pin, int set)
+{
+ uint32_t reg;
+
+ KASSERT(pin < sc->sc_ngpiopins);
+ reg = AR_READ(sc, AR_GPIO_IN_OUT);
+ if (set)
+ reg |= 1 << pin;
+ else
+ reg &= ~(1 << pin);
+ AR_WRITE(sc, AR_GPIO_IN_OUT, reg);
+ AR_WRITE_BARRIER(sc);
+}
+
+Static void
+ar9003_gpio_config_input(struct athn_softc *sc, int pin)
+{
+ uint32_t reg;
+
+ reg = AR_READ(sc, AR_GPIO_OE_OUT);
+ reg &= ~(AR_GPIO_OE_OUT_DRV_M << (pin * 2));
+ reg |= AR_GPIO_OE_OUT_DRV_NO << (pin * 2);
+ AR_WRITE(sc, AR_GPIO_OE_OUT, reg);
+ AR_WRITE_BARRIER(sc);
+}
+
+Static void
+ar9003_gpio_config_output(struct athn_softc *sc, int pin, int type)
+{
+ uint32_t reg;
+ int mux, off;
+
+ mux = pin / 6;
+ off = pin % 6;
+
+ reg = AR_READ(sc, AR_GPIO_OUTPUT_MUX(mux));
+ reg &= ~(0x1f << (off * 5));
+ reg |= (type & 0x1f) << (off * 5);
+ AR_WRITE(sc, AR_GPIO_OUTPUT_MUX(mux), reg);
+
+ reg = AR_READ(sc, AR_GPIO_OE_OUT);
+ reg &= ~(AR_GPIO_OE_OUT_DRV_M << (pin * 2));
+ reg |= AR_GPIO_OE_OUT_DRV_ALL << (pin * 2);
+ AR_WRITE(sc, AR_GPIO_OE_OUT, reg);
+ AR_WRITE_BARRIER(sc);
+}
+
+Static void
+ar9003_rfsilent_init(struct athn_softc *sc)
+{
+ uint32_t reg;
+
+ /* Configure hardware radio switch. */
+ AR_SETBITS(sc, AR_GPIO_INPUT_EN_VAL, AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
+ reg = AR_READ(sc, AR_GPIO_INPUT_MUX2);
+ reg = RW(reg, AR_GPIO_INPUT_MUX2_RFSILENT, 0);
+ AR_WRITE(sc, AR_GPIO_INPUT_MUX2, reg);
+ ar9003_gpio_config_input(sc, sc->sc_rfsilent_pin);
+ AR_SETBITS(sc, AR_PHY_TEST, AR_PHY_TEST_RFSILENT_BB);
+ if (!(sc->sc_flags & ATHN_FLAG_RFSILENT_REVERSED)) {
+ AR_SETBITS(sc, AR_GPIO_INTR_POL,
+ AR_GPIO_INTR_POL_PIN(sc->sc_rfsilent_pin));
+ }
+ AR_WRITE_BARRIER(sc);
+}
+
+Static int
+ar9003_dma_alloc(struct athn_softc *sc)
+{
+ int error;
+
+ error = ar9003_tx_alloc(sc);
+ if (error != 0)
+ return error;
+
+ error = ar9003_rx_alloc(sc, ATHN_QID_LP, AR9003_RX_LP_QDEPTH);
+ if (error != 0)
+ return error;
+
+ error = ar9003_rx_alloc(sc, ATHN_QID_HP, AR9003_RX_HP_QDEPTH);
+ if (error != 0)
+ return error;
+
+ return 0;
+}
+
+Static void
+ar9003_dma_free(struct athn_softc *sc)
+{
+
+ ar9003_tx_free(sc);
+ ar9003_rx_free(sc, ATHN_QID_LP);
+ ar9003_rx_free(sc, ATHN_QID_HP);
+}
+
+Static int
+ar9003_tx_alloc(struct athn_softc *sc)
+{
+ struct athn_tx_buf *bf;
+ bus_size_t size;
+ int error, nsegs, i;
+
+ /*
+ * Allocate Tx status ring.
+ */
+ size = AR9003_NTXSTATUS * sizeof(struct ar_tx_status);
+
+ error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0,
+ BUS_DMA_NOWAIT, &sc->sc_txsmap);
+ if (error != 0)
+ goto fail;
+
+ error = bus_dmamem_alloc(sc->sc_dmat, size, 4, 0, &sc->sc_txsseg, 1,
+// XXX &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO);
+ &nsegs, BUS_DMA_NOWAIT);
+ if (error != 0)
+ goto fail;
+
+ error = bus_dmamem_map(sc->sc_dmat, &sc->sc_txsseg, 1, size,
+ (void **)&sc->sc_txsring, BUS_DMA_NOWAIT | BUS_DMA_COHERENT);
+ if (error != 0)
+ goto fail;
+
+ error = bus_dmamap_load_raw(sc->sc_dmat, sc->sc_txsmap, &sc->sc_txsseg,
+ 1, size, BUS_DMA_NOWAIT | BUS_DMA_READ);
+ if (error != 0)
+ goto fail;
+
+ /*
+ * Allocate a pool of Tx descriptors shared between all Tx queues.
+ */
+ size = ATHN_NTXBUFS * sizeof(struct ar_tx_desc);
+
+ error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0,
+ BUS_DMA_NOWAIT, &sc->sc_map);
+ if (error != 0)
+ goto fail;
+
+ error = bus_dmamem_alloc(sc->sc_dmat, size, 4, 0, &sc->sc_seg, 1,
+// XXX &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO);
+ &nsegs, BUS_DMA_NOWAIT);
+ if (error != 0)
+ goto fail;
+
+ error = bus_dmamem_map(sc->sc_dmat, &sc->sc_seg, 1, size,
+ (void **)&sc->sc_descs, BUS_DMA_NOWAIT | BUS_DMA_COHERENT);
+ if (error != 0)
+ goto fail;
+
+ error = bus_dmamap_load_raw(sc->sc_dmat, sc->sc_map, &sc->sc_seg, 1, size,
+ BUS_DMA_NOWAIT | BUS_DMA_WRITE);
+ if (error != 0)
+ goto fail;
+
+ SIMPLEQ_INIT(&sc->sc_txbufs);
+ for (i = 0; i < ATHN_NTXBUFS; i++) {
+ bf = &sc->sc_txpool[i];
+
+ error = bus_dmamap_create(sc->sc_dmat, ATHN_TXBUFSZ,
+ AR9003_MAX_SCATTER, ATHN_TXBUFSZ, 0, BUS_DMA_NOWAIT,
+ &bf->bf_map);
+ if (error != 0) {
+ printf("%s: could not create Tx buf DMA map\n",
+ device_xname(sc->sc_dev));
+ goto fail;
+ }
+
+ bf->bf_descs = &((struct ar_tx_desc *)sc->sc_descs)[i];
+ bf->bf_daddr = sc->sc_map->dm_segs[0].ds_addr +
+ i * sizeof(struct ar_tx_desc);
+
+ SIMPLEQ_INSERT_TAIL(&sc->sc_txbufs, bf, bf_list);
+ }
+ return 0;
+ fail:
+ ar9003_tx_free(sc);
+ return error;
+}
+
+Static void
+ar9003_tx_free(struct athn_softc *sc)
+{
+ struct athn_tx_buf *bf;
+ int i;
+
+ for (i = 0; i < ATHN_NTXBUFS; i++) {
+ bf = &sc->sc_txpool[i];
+
+ if (bf->bf_map != NULL)
+ bus_dmamap_destroy(sc->sc_dmat, bf->bf_map);
+ }
+ /* Free Tx descriptors. */
+ if (sc->sc_map != NULL) {
+ if (sc->sc_descs != NULL) {
+ bus_dmamap_unload(sc->sc_dmat, sc->sc_map);
+ bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_descs,
+ ATHN_NTXBUFS * sizeof(struct ar_tx_desc));
+ bus_dmamem_free(sc->sc_dmat, &sc->sc_seg, 1);
+ }
+ bus_dmamap_destroy(sc->sc_dmat, sc->sc_map);
+ }
+ /* Free Tx status ring. */
+ if (sc->sc_txsmap != NULL) {
+ if (sc->sc_txsring != NULL) {
+ bus_dmamap_unload(sc->sc_dmat, sc->sc_txsmap);
+ bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_txsring,
+ AR9003_NTXSTATUS * sizeof(struct ar_tx_status));
+ bus_dmamem_free(sc->sc_dmat, &sc->sc_txsseg, 1);
+ }
+ bus_dmamap_destroy(sc->sc_dmat, sc->sc_txsmap);
+ }
+}
+
+Static int
+ar9003_rx_alloc(struct athn_softc *sc, int qid, int count)
+{
+ struct athn_rxq *rxq = &sc->sc_rxq[qid];
+ struct athn_rx_buf *bf;
+ struct ar_rx_status *ds;
+ int error, i;
+
+ rxq->bf = malloc(count * sizeof(*bf), M_DEVBUF, M_NOWAIT | M_ZERO);
+ if (rxq->bf == NULL)
+ return ENOMEM;
+
+ rxq->count = count;
+
+ for (i = 0; i < rxq->count; i++) {
+ bf = &rxq->bf[i];
+
+ error = bus_dmamap_create(sc->sc_dmat, ATHN_RXBUFSZ, 1,
+ ATHN_RXBUFSZ, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW,
+ &bf->bf_map);
+ if (error != 0) {
+ printf("%s: could not create Rx buf DMA map\n",
+ device_xname(sc->sc_dev));
+ goto fail;
+ }
+ /*
+ * Assumes MCLGETI returns cache-line-size aligned buffers.
+ */
+ bf->bf_m = MCLGETI(NULL, M_DONTWAIT, NULL, ATHN_RXBUFSZ);
+ if (bf->bf_m == NULL) {
+ printf("%s: could not allocate Rx mbuf\n",
+ device_xname(sc->sc_dev));
+ error = ENOBUFS;
+ goto fail;
+ }
+
+ error = bus_dmamap_load(sc->sc_dmat, bf->bf_map,
+ mtod(bf->bf_m, void *), ATHN_RXBUFSZ, NULL,
+ BUS_DMA_NOWAIT);
+ if (error != 0) {
+ printf("%s: could not DMA map Rx buffer\n",
+ device_xname(sc->sc_dev));
+ goto fail;
+ }
+
+ ds = mtod(bf->bf_m, struct ar_rx_status *);
+ memset(ds, 0, sizeof(*ds));
+ bf->bf_desc = ds;
+ bf->bf_daddr = bf->bf_map->dm_segs[0].ds_addr;
+
+ bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, ATHN_RXBUFSZ,
+ BUS_DMASYNC_PREREAD);
+ }
+ return 0;
+ fail:
+ ar9003_rx_free(sc, qid);
+ return error;
+}
+
+Static void
+ar9003_rx_free(struct athn_softc *sc, int qid)
+{
+ struct athn_rxq *rxq = &sc->sc_rxq[qid];
+ struct athn_rx_buf *bf;
+ int i;
+
+ if (rxq->bf == NULL)
+ return;
+ for (i = 0; i < rxq->count; i++) {
+ bf = &rxq->bf[i];
+
+ if (bf->bf_map != NULL)
+ bus_dmamap_destroy(sc->sc_dmat, bf->bf_map);
+ if (bf->bf_m != NULL)
+ m_freem(bf->bf_m);
+ }
+ free(rxq->bf, M_DEVBUF);
+}
+
+PUBLIC void
+ar9003_reset_txsring(struct athn_softc *sc)
+{
+
+ sc->sc_txscur = 0;
+ memset(sc->sc_txsring, 0, AR9003_NTXSTATUS * sizeof(struct ar_tx_status));
+ AR_WRITE(sc, AR_Q_STATUS_RING_START,
+ sc->sc_txsmap->dm_segs[0].ds_addr);
+ AR_WRITE(sc, AR_Q_STATUS_RING_END,
+ sc->sc_txsmap->dm_segs[0].ds_addr + sc->sc_txsmap->dm_segs[0].ds_len);
+ AR_WRITE_BARRIER(sc);
+}
+
+Static void
+ar9003_rx_enable(struct athn_softc *sc)
+{
+ struct athn_rxq *rxq;
+ struct athn_rx_buf *bf;
+ struct ar_rx_status *ds;
+ uint32_t reg;
+ int qid, i;
+
+ reg = AR_READ(sc, AR_RXBP_THRESH);
+ reg = RW(reg, AR_RXBP_THRESH_HP, 1);
+ reg = RW(reg, AR_RXBP_THRESH_LP, 1);
+ AR_WRITE(sc, AR_RXBP_THRESH, reg);
+
+ /* Set Rx buffer size. */
+ AR_WRITE(sc, AR_DATABUF_SIZE, ATHN_RXBUFSZ - sizeof(*ds));
+
+ for (qid = 0; qid < 2; qid++) {
+ rxq = &sc->sc_rxq[qid];
+
+ /* Setup Rx status descriptors. */
+ SIMPLEQ_INIT(&rxq->head);
+ for (i = 0; i < rxq->count; i++) {
+ bf = &rxq->bf[i];
+ ds = bf->bf_desc;
+
+ memset(ds, 0, sizeof(*ds));
+ if (qid == ATHN_QID_LP)
+ AR_WRITE(sc, AR_LP_RXDP, bf->bf_daddr);
+ else
+ AR_WRITE(sc, AR_HP_RXDP, bf->bf_daddr);
+ AR_WRITE_BARRIER(sc);
+ SIMPLEQ_INSERT_TAIL(&rxq->head, bf, bf_list);
+ }
+ }
+ /* Enable Rx. */
+ AR_WRITE(sc, AR_CR, 0);
+ AR_WRITE_BARRIER(sc);
+}
+
+Static void
+ar9003_rx_radiotap(struct athn_softc *sc, struct mbuf *m,
+ struct ar_rx_status *ds)
+{
+ struct athn_rx_radiotap_header *tap = &sc->sc_rxtap;
+ struct ieee80211com *ic = &sc->sc_ic;
+ uint64_t tsf;
+ uint32_t tstamp;
+ uint8_t rate;
+
+ /* Extend the 15-bit timestamp from Rx status to 64-bit TSF. */
+ tstamp = ds->ds_status3;
+ tsf = AR_READ(sc, AR_TSF_U32);
+ tsf = tsf << 32 | AR_READ(sc, AR_TSF_L32);
+ if ((tsf & 0x7fff) < tstamp)
+ tsf -= 0x8000;
+ tsf = (tsf & ~0x7fff) | tstamp;
+
+ tap->wr_flags = IEEE80211_RADIOTAP_F_FCS;
+ tap->wr_tsft = htole64(tsf);
+ tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq);
+ tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags);
+ tap->wr_dbm_antsignal = MS(ds->ds_status5, AR_RXS5_RSSI_COMBINED);
+ /* XXX noise. */
+ tap->wr_antenna = MS(ds->ds_status4, AR_RXS4_ANTENNA);
+ tap->wr_rate = 0; /* In case it can't be found below. */
+ rate = MS(ds->ds_status1, AR_RXS1_RATE);
+ if (rate & 0x80) { /* HT. */
+ /* Bit 7 set means HT MCS instead of rate. */
+ tap->wr_rate = rate;
+ if (!(ds->ds_status4 & AR_RXS4_GI))
+ tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTGI;
+
+ }
+ else if (rate & 0x10) { /* CCK. */
+ if (rate & 0x04)
+ tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
+ switch (rate & ~0x14) {
+ case 0xb: tap->wr_rate = 2; break;
+ case 0xa: tap->wr_rate = 4; break;
+ case 0x9: tap->wr_rate = 11; break;
+ case 0x8: tap->wr_rate = 22; break;
+ }
+ }
+ else { /* OFDM. */
+ switch (rate) {
+ case 0xb: tap->wr_rate = 12; break;
+ case 0xf: tap->wr_rate = 18; break;
+ case 0xa: tap->wr_rate = 24; break;
+ case 0xe: tap->wr_rate = 36; break;
+ case 0x9: tap->wr_rate = 48; break;
+ case 0xd: tap->wr_rate = 72; break;
+ case 0x8: tap->wr_rate = 96; break;
+ case 0xc: tap->wr_rate = 108; break;
+ }
+ }
+ bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m);
+}
+
+Static int
+ar9003_rx_process(struct athn_softc *sc, int qid)
+{
+ struct ieee80211com *ic = &sc->sc_ic;
+ struct ifnet *ifp = &sc->sc_if;
+ struct athn_rxq *rxq = &sc->sc_rxq[qid];
+ struct athn_rx_buf *bf;
+ struct ar_rx_status *ds;
+ struct ieee80211_frame *wh;
+ struct ieee80211_node *ni;
+ struct mbuf *m, *m1;
+ size_t len;
+ u_int32_t rstamp;
+ int error, rssi;
+
+ bf = SIMPLEQ_FIRST(&rxq->head);
+ if (__predict_false(bf == NULL)) { /* Should not happen. */
+ printf("%s: Rx queue is empty!\n", device_xname(sc->sc_dev));
+ return ENOENT;
+ }
+ bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, ATHN_RXBUFSZ,
+ BUS_DMASYNC_POSTREAD);
+
+ ds = mtod(bf->bf_m, struct ar_rx_status *);
+ if (!(ds->ds_status1 & AR_RXS1_DONE))
+ return EBUSY;
+
+ /* Check that it is a valid Rx status descriptor. */
+ if ((ds->ds_info & (AR_RXI_DESC_ID_M | AR_RXI_DESC_TX |
+ AR_RXI_CTRL_STAT)) != SM(AR_RXI_DESC_ID, AR_VENDOR_ATHEROS))
+ goto skip;
+
+ if (!(ds->ds_status11 & AR_RXS11_FRAME_OK)) {
+ if (ds->ds_status11 & AR_RXS11_CRC_ERR)
+ DPRINTFN(DBG_RX, sc, "CRC error\n");
+ else if (ds->ds_status11 & AR_RXS11_PHY_ERR)
+ DPRINTFN(DBG_RX, sc, "PHY error=0x%x\n",
+ MS(ds->ds_status11, AR_RXS11_PHY_ERR_CODE));
+ else if (ds->ds_status11 & AR_RXS11_DECRYPT_CRC_ERR)
+ DPRINTFN(DBG_RX, sc, "Decryption CRC error\n");
+ else if (ds->ds_status11 & AR_RXS11_MICHAEL_ERR) {
+ DPRINTFN(DBG_RX, sc, "Michael MIC failure\n");
+ /* Report Michael MIC failures to net80211. */
+
+ len = MS(ds->ds_status2, AR_RXS2_DATA_LEN);
+ m = bf->bf_m;
+ m->m_pkthdr.rcvif = ifp;
+ m->m_data = (void *)&ds[1];
+ m->m_pkthdr.len = m->m_len = len;
+ wh = mtod(m, struct ieee80211_frame *);
+
+ ieee80211_notify_michael_failure(ic, wh,
+ 0 /* XXX: keyix */);
+ }
+ ifp->if_ierrors++;
+ goto skip;
+ }
+
+ len = MS(ds->ds_status2, AR_RXS2_DATA_LEN);
+ if (__predict_false(len < IEEE80211_MIN_LEN ||
+ len > ATHN_RXBUFSZ - sizeof(*ds))) {
+ DPRINTFN(DBG_RX, sc, "corrupted descriptor length=%zd\n",
+ len);
+ ifp->if_ierrors++;
+ goto skip;
+ }
+
+ /* Allocate a new Rx buffer. */
+ m1 = MCLGETI(NULL, M_DONTWAIT, NULL, ATHN_RXBUFSZ);
+ if (__predict_false(m1 == NULL)) {
+ ic->ic_stats.is_rx_nobuf++;
+ ifp->if_ierrors++;
+ goto skip;
+ }
+
+ /* Unmap the old Rx buffer. */
+ bus_dmamap_unload(sc->sc_dmat, bf->bf_map);
+
+ /* Map the new Rx buffer. */
+ error = bus_dmamap_load(sc->sc_dmat, bf->bf_map, mtod(m1, void *),
+ ATHN_RXBUFSZ, NULL, BUS_DMA_NOWAIT | BUS_DMA_READ);
+ if (__predict_false(error != 0)) {
+ m_freem(m1);
+
+ /* Remap the old Rx buffer or panic. */
+ error = bus_dmamap_load(sc->sc_dmat, bf->bf_map,
+ mtod(bf->bf_m, void *), ATHN_RXBUFSZ, NULL,
+ BUS_DMA_NOWAIT | BUS_DMA_READ);
+ KASSERT(error != 0);
+ bf->bf_daddr = bf->bf_map->dm_segs[0].ds_addr;
+ ifp->if_ierrors++;
+ goto skip;
+ }
+ bf->bf_desc = mtod(m1, struct ar_rx_status *);
+ bf->bf_daddr = bf->bf_map->dm_segs[0].ds_addr;
+
+ m = bf->bf_m;
+ bf->bf_m = m1;
+
+ /* Finalize mbuf. */
+ m->m_pkthdr.rcvif = ifp;
+ /* Strip Rx status descriptor from head. */
+ m->m_data = (void *)&ds[1];
+ m->m_pkthdr.len = m->m_len = len;
+
+ /* Grab a reference to the source node. */
+ wh = mtod(m, struct ieee80211_frame *);
+ ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh);
+
+ /* Remove any HW padding after the 802.11 header. */
+ if (!(wh->i_fc[0] & IEEE80211_FC0_TYPE_CTL)) {
+ u_int hdrlen = ieee80211_anyhdrsize(wh);
+ if (hdrlen & 3) {
+ ovbcopy(wh, (uint8_t *)wh + 2, hdrlen);
+ m_adj(m, 2);
+ }
+ }
+ if (__predict_false(sc->sc_drvbpf != NULL))
+ ar9003_rx_radiotap(sc, m, ds);
+ /* Trim 802.11 FCS after radiotap. */
+ m_adj(m, -IEEE80211_CRC_LEN);
+
+ /* Send the frame to the 802.11 layer. */
+ rssi = MS(ds->ds_status5, AR_RXS5_RSSI_COMBINED);
+ rstamp = ds->ds_status3;
+ ieee80211_input(ic, m, ni, rssi, rstamp);
+
+ /* Node is no longer needed. */
+ ieee80211_free_node(ni);
+
+ skip:
+ /* Unlink this descriptor from head. */
+ SIMPLEQ_REMOVE_HEAD(&rxq->head, bf_list);
+ memset(bf->bf_desc, 0, sizeof(*ds));
+
+ /* Re-use this descriptor and link it to tail. */
+ bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, ATHN_RXBUFSZ,
+ BUS_DMASYNC_PREREAD);
+
+ if (qid == ATHN_QID_LP)
+ AR_WRITE(sc, AR_LP_RXDP, bf->bf_daddr);
+ else
+ AR_WRITE(sc, AR_HP_RXDP, bf->bf_daddr);
+ AR_WRITE_BARRIER(sc);
+ SIMPLEQ_INSERT_TAIL(&rxq->head, bf, bf_list);
+
+ /* Re-enable Rx. */
+ AR_WRITE(sc, AR_CR, 0);
+ AR_WRITE_BARRIER(sc);
+ return 0;
+}
+
+Static void
+ar9003_rx_intr(struct athn_softc *sc, int qid)
+{
+
+ while (ar9003_rx_process(sc, qid) == 0)
+ continue;
+}
+
+Static int
+ar9003_tx_process(struct athn_softc *sc)
+{
+ struct ifnet *ifp = &sc->sc_if;
+ struct athn_txq *txq;
+ struct athn_node *an;
+ struct athn_tx_buf *bf;
+ struct ar_tx_status *ds;
+ uint8_t qid, failcnt;
+
+ ds = &((struct ar_tx_status *)sc->sc_txsring)[sc->sc_txscur];
+ if (!(ds->ds_status8 & AR_TXS8_DONE))
+ return EBUSY;
+
+ sc->sc_txscur = (sc->sc_txscur + 1) % AR9003_NTXSTATUS;
+
+ /* Check that it is a valid Tx status descriptor. */
+ if ((ds->ds_info & (AR_TXI_DESC_ID_M | AR_TXI_DESC_TX)) !=
+ (SM(AR_TXI_DESC_ID, AR_VENDOR_ATHEROS) | AR_TXI_DESC_TX)) {
+ memset(ds, 0, sizeof(*ds));
+ return 0;
+ }
+ /* Retrieve the queue that was used to send this PDU. */
+ qid = MS(ds->ds_info, AR_TXI_QCU_NUM);
+ txq = &sc->sc_txq[qid];
+
+ bf = SIMPLEQ_FIRST(&txq->head);
+ if (bf == NULL || bf == txq->wait) {
+ memset(ds, 0, sizeof(*ds));
+ return 0;
+ }
+ SIMPLEQ_REMOVE_HEAD(&txq->head, bf_list);
+ ifp->if_opackets++;
+
+ sc->sc_tx_timer = 0;
+
+ if (ds->ds_status3 & AR_TXS3_EXCESSIVE_RETRIES)
+ ifp->if_oerrors++;
+
+ if (ds->ds_status3 & AR_TXS3_UNDERRUN)
+ athn_inc_tx_trigger_level(sc);
+
+ /* Wakeup PA predistortion state machine. */
+ if (bf->bf_txflags & ATHN_TXFLAG_PAPRD)
+ ar9003_paprd_tx_tone_done(sc);
+
+ an = (struct athn_node *)bf->bf_ni;
+ /*
+ * NB: the data fail count contains the number of un-acked tries
+ * for the final series used. We must add the number of tries for
+ * each series that was fully processed.
+ */
+ failcnt = MS(ds->ds_status3, AR_TXS3_DATA_FAIL_CNT);
+ /* NB: Assume two tries per series. */
+ failcnt += MS(ds->ds_status8, AR_TXS8_FINAL_IDX) * 2;
+
+ /* Update rate control statistics. */
+ an->amn.amn_txcnt++;
+ if (failcnt > 0)
+ an->amn.amn_retrycnt++;
+
+ DPRINTFN(DBG_TX, sc, "Tx done qid=%d status3=%d fail count=%d\n",
+ qid, ds->ds_status3, failcnt);
+
+ /* Reset Tx status descriptor. */
+ memset(ds, 0, sizeof(*ds));
+
+ /* Unmap Tx buffer. */
+ bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, bf->bf_map->dm_mapsize,
+ BUS_DMASYNC_POSTWRITE);
+ bus_dmamap_unload(sc->sc_dmat, bf->bf_map);
+
+ m_freem(bf->bf_m);
+ bf->bf_m = NULL;
+ ieee80211_free_node(bf->bf_ni);
+ bf->bf_ni = NULL;
+
+ /* Link Tx buffer back to global free list. */
+ SIMPLEQ_INSERT_TAIL(&sc->sc_txbufs, bf, bf_list);
+
+ /* Queue buffers that are waiting if there is new room. */
+ if (--txq->queued < AR9003_TX_QDEPTH && txq->wait != NULL) {
+ AR_WRITE(sc, AR_QTXDP(qid), txq->wait->bf_daddr);
+ AR_WRITE_BARRIER(sc);
+ txq->wait = SIMPLEQ_NEXT(txq->wait, bf_list);
+ }
+ return 0;
+}
+
+Static void
+ar9003_tx_intr(struct athn_softc *sc)
+{
+ struct ifnet *ifp = &sc->sc_if;
+
+ while (ar9003_tx_process(sc) == 0);
+
+ if (!SIMPLEQ_EMPTY(&sc->sc_txbufs)) {
+ ifp->if_flags &= ~IFF_OACTIVE;
+ ifp->if_start(ifp);
+ }
+}
+
+#ifndef IEEE80211_STA_ONLY
+/*
+ * Process Software Beacon Alert interrupts.
+ */
+Static int
+ar9003_swba_intr(struct athn_softc *sc)
+{
+ struct ieee80211com *ic = &sc->sc_ic;
+ struct ifnet *ifp = &sc->sc_if;
+ struct ieee80211_node *ni = ic->ic_bss;
+ struct athn_tx_buf *bf = sc->sc_bcnbuf;
+ struct ieee80211_frame *wh;
+ struct ieee80211_beacon_offsets bo;
+ struct ar_tx_desc *ds;
+ struct mbuf *m;
+ uint32_t sum;
+ uint8_t ridx, hwrate;
+ int error, totlen;
+
+#if notyet
+ if (ic->ic_tim_mcast_pending &&
+ IF_IS_EMPTY(&ni->ni_savedq) &&
+ SIMPLEQ_EMPTY(&sc->sc_txq[ATHN_QID_CAB].head))
+ ic->ic_tim_mcast_pending = 0;
+#endif
+ if (ic->ic_dtim_count == 0)
+ ic->ic_dtim_count = ic->ic_dtim_period - 1;
+ else
+ ic->ic_dtim_count--;
+
+ /* Make sure previous beacon has been sent. */
+ if (athn_tx_pending(sc, ATHN_QID_BEACON)) {
+ DPRINTFN(DBG_INTR, sc, "beacon stuck\n");
+ return EBUSY;
+ }
+ /* Get new beacon. */
+ m = ieee80211_beacon_alloc(ic, ic->ic_bss, &bo);
+ if (__predict_false(m == NULL))
+ return ENOBUFS;
+ /* Assign sequence number. */
+ /* XXX: use non-QoS tid? */
+ wh = mtod(m, struct ieee80211_frame *);
+ *(uint16_t *)&wh->i_seq[0] =
+ htole16(ic->ic_bss->ni_txseqs[0] << IEEE80211_SEQ_SEQ_SHIFT);
+ ic->ic_bss->ni_txseqs[0]++;
+
+ /* Unmap and free old beacon if any. */
+ if (__predict_true(bf->bf_m != NULL)) {
+ bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0,
+ bf->bf_map->dm_mapsize, BUS_DMASYNC_POSTWRITE);
+ bus_dmamap_unload(sc->sc_dmat, bf->bf_map);
+ m_freem(bf->bf_m);
+ bf->bf_m = NULL;
+ }
+ /* DMA map new beacon. */
+ error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_map, m,
+ BUS_DMA_NOWAIT | BUS_DMA_WRITE);
+ if (__predict_false(error != 0)) {
+ m_freem(m);
+ return error;
+ }
+ bf->bf_m = m;
+
+ /* Setup Tx descriptor (simplified ar9003_tx()). */
+ ds = bf->bf_descs;
+ memset(ds, 0, sizeof(*ds));
+
+ ds->ds_info =
+ SM(AR_TXI_DESC_ID, AR_VENDOR_ATHEROS) |
+ SM(AR_TXI_DESC_NDWORDS, 23) |
+ SM(AR_TXI_QCU_NUM, ATHN_QID_BEACON) |
+ AR_TXI_DESC_TX | AR_TXI_CTRL_STAT;
+
+ totlen = m->m_pkthdr.len + IEEE80211_CRC_LEN;
+ ds->ds_ctl11 = SM(AR_TXC11_FRAME_LEN, totlen);
+ ds->ds_ctl11 |= SM(AR_TXC11_XMIT_POWER, AR_MAX_RATE_POWER);
+ ds->ds_ctl12 = SM(AR_TXC12_FRAME_TYPE, AR_FRAME_TYPE_BEACON);
+ ds->ds_ctl12 |= AR_TXC12_NO_ACK;
+ ds->ds_ctl17 = SM(AR_TXC17_ENCR_TYPE, AR_ENCR_TYPE_CLEAR);
+
+ /* Write number of tries. */
+ ds->ds_ctl13 = SM(AR_TXC13_XMIT_DATA_TRIES0, 1);
+
+ /* Write Tx rate. */
+ ridx = (ic->ic_curmode == IEEE80211_MODE_11A) ?
+ ATHN_RIDX_OFDM6 : ATHN_RIDX_CCK1;
+ hwrate = athn_rates[ridx].hwrate;
+ ds->ds_ctl14 = SM(AR_TXC14_XMIT_RATE0, hwrate);
+
+ /* Write Tx chains. */
+ ds->ds_ctl18 = SM(AR_TXC18_CHAIN_SEL0, sc->sc_txchainmask);
+
+ ds->ds_segs[0].ds_data = bf->bf_map->dm_segs[0].ds_addr;
+ /* Segment length must be a multiple of 4. */
+ ds->ds_segs[0].ds_ctl |= SM(AR_TXC_BUF_LEN,
+ (bf->bf_map->dm_segs[0].ds_len + 3) & ~3);
+ /* Compute Tx descriptor checksum. */
+ sum = ds->ds_info;
+ sum += ds->ds_segs[0].ds_data;
+ sum += ds->ds_segs[0].ds_ctl;
+ sum = (sum >> 16) + (sum & 0xffff);
+ ds->ds_ctl10 = SM(AR_TXC10_PTR_CHK_SUM, sum);
+
+ bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, bf->bf_map->dm_mapsize,
+ BUS_DMASYNC_PREWRITE);
+
+ /* Stop Tx DMA before putting the new beacon on the queue. */
+ athn_stop_tx_dma(sc, ATHN_QID_BEACON);
+
+ AR_WRITE(sc, AR_QTXDP(ATHN_QID_BEACON), bf->bf_daddr);
+
+ for(;;) {
+ if (SIMPLEQ_EMPTY(&sc->sc_txbufs))
+ break;
+
+ IF_DEQUEUE(&ni->ni_savedq, m);
+ if (m == NULL)
+ break;
+ if (!IF_IS_EMPTY(&ni->ni_savedq)) {
+ /* more queued frames, set the more data bit */
+ wh = mtod(m, struct ieee80211_frame *);
+ wh->i_fc[1] |= IEEE80211_FC1_MORE_DATA;
+ }
+
+ if (sc->sc_ops.tx(sc, m, ni, ATHN_TXFLAG_CAB) != 0) {
+ ieee80211_free_node(ni);
+ ifp->if_oerrors++;
+ break;
+ }
+ }
+
+ /* Kick Tx. */
+ AR_WRITE(sc, AR_Q_TXE, 1 << ATHN_QID_BEACON);
+ AR_WRITE_BARRIER(sc);
+ return 0;
+}
+#endif
+
+Static int
+ar9003_intr(struct athn_softc *sc)
+{
+ uint32_t intr, intr2, intr5, sync;
+
+ /* Get pending interrupts. */
+ intr = AR_READ(sc, AR_INTR_ASYNC_CAUSE);
+ if (!(intr & AR_INTR_MAC_IRQ) || intr == AR_INTR_SPURIOUS) {
+ intr = AR_READ(sc, AR_INTR_SYNC_CAUSE);
+ if (intr == AR_INTR_SPURIOUS || (intr & sc->sc_isync) == 0)
+ return 0; /* Not for us. */
+ }
+
+ if ((AR_READ(sc, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) &&
+ (AR_READ(sc, AR_RTC_STATUS) & AR_RTC_STATUS_M) == AR_RTC_STATUS_ON)
+ intr = AR_READ(sc, AR_ISR);
+ else
+ intr = 0;
+ sync = AR_READ(sc, AR_INTR_SYNC_CAUSE) & sc->sc_isync;
+ if (intr == 0 && sync == 0)
+ return 0; /* Not for us. */
+
+ if (intr != 0) {
+ if (intr & AR_ISR_BCNMISC) {
+ intr2 = AR_READ(sc, AR_ISR_S2);
+#ifdef notyet
+ if (intr2 & AR_ISR_S2_TIM)
+ /* TBD */;
+ if (intr2 & AR_ISR_S2_TSFOOR)
+ /* TBD */;
+ if (intr2 & AR_ISR_S2_BB_WATCHDOG)
+ /* TBD */;
+#endif
+ }
+ intr = AR_READ(sc, AR_ISR_RAC);
+ if (intr == AR_INTR_SPURIOUS)
+ return 1;
+
+#ifndef IEEE80211_STA_ONLY
+ if (intr & AR_ISR_SWBA)
+ ar9003_swba_intr(sc);
+#endif
+ if (intr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
+ ar9003_rx_intr(sc, ATHN_QID_LP);
+ if (intr & (AR_ISR_LP_RXOK | AR_ISR_RXERR))
+ ar9003_rx_intr(sc, ATHN_QID_LP);
+ if (intr & AR_ISR_HP_RXOK)
+ ar9003_rx_intr(sc, ATHN_QID_HP);
+
+ if (intr & (AR_ISR_TXMINTR | AR_ISR_TXINTM))
+ ar9003_tx_intr(sc);
+ if (intr & (AR_ISR_TXOK | AR_ISR_TXERR | AR_ISR_TXEOL))
+ ar9003_tx_intr(sc);
+
+ if (intr & AR_ISR_GENTMR) {
+ intr5 = AR_READ(sc, AR_ISR_S5_S);
+ DPRINTFN(DBG_INTR, sc,
+ "GENTMR trigger=%d thresh=%d\n",
+ MS(intr5, AR_ISR_S5_GENTIMER_TRIG),
+ MS(intr5, AR_ISR_S5_GENTIMER_THRESH));
+ }
+ }
+ if (sync != 0) {
+ if (sync & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
+ AR_WRITE(sc, AR_RC, AR_RC_HOSTIF);
+ AR_WRITE(sc, AR_RC, 0);
+ }
+
+ if ((sc->sc_flags & ATHN_FLAG_RFSILENT) &&
+ (sync & AR_INTR_SYNC_GPIO_PIN(sc->sc_rfsilent_pin))) {
+ struct ifnet *ifp = &sc->sc_if;
+
+ printf("%s: radio switch turned off\n",
+ device_xname(sc->sc_dev));
+ /* Turn the interface down. */
+ ifp->if_flags &= ~IFF_UP;
+ athn_stop(ifp, 1);
+ return 1;
+ }
+
+ AR_WRITE(sc, AR_INTR_SYNC_CAUSE, sync);
+ (void)AR_READ(sc, AR_INTR_SYNC_CAUSE);
+ }
+ return 1;
+}
+
+Static int
+ar9003_tx(struct athn_softc *sc, struct mbuf *m, struct ieee80211_node *ni,
+ int txflags)
+{
+ struct ieee80211com *ic = &sc->sc_ic;
+ struct ieee80211_key *k = NULL;
+ struct ieee80211_frame *wh;
+ struct athn_series series[4];
+ struct ar_tx_desc *ds;
+ struct athn_txq *txq;
+ struct athn_tx_buf *bf;
+ struct athn_node *an = (void *)ni;
+ struct mbuf *m1;
+ uint32_t sum;
+ uint16_t qos;
+ uint8_t txpower, type, encrtype, ridx[4];
+ int i, error, totlen, hasqos, qid;
+
+ /* Grab a Tx buffer from our global free list. */
+ bf = SIMPLEQ_FIRST(&sc->sc_txbufs);
+ KASSERT(bf != NULL);
+
+ /* Map 802.11 frame type to hardware frame type. */
+ wh = mtod(m, struct ieee80211_frame *);
+ if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) ==
+ IEEE80211_FC0_TYPE_MGT) {
+ /* NB: Beacons do not use ar9003_tx(). */
+ if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) ==
+ IEEE80211_FC0_SUBTYPE_PROBE_RESP)
+ type = AR_FRAME_TYPE_PROBE_RESP;
+ else if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) ==
+ IEEE80211_FC0_SUBTYPE_ATIM)
+ type = AR_FRAME_TYPE_ATIM;
+ else
+ type = AR_FRAME_TYPE_NORMAL;
+ }
+ else if ((wh->i_fc[0] &
+ (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) ==
+ (IEEE80211_FC0_TYPE_CTL | IEEE80211_FC0_SUBTYPE_PS_POLL)) {
+ type = AR_FRAME_TYPE_PSPOLL;
+ }
+ else
+ type = AR_FRAME_TYPE_NORMAL;
+
+ if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) {
+ k = ieee80211_crypto_encap(ic, ni, m);
+ if (k == NULL)
+ return ENOBUFS;
+
+ /* packet header may have moved, reset our local pointer */
+ wh = mtod(m, struct ieee80211_frame *);
+ }
+
+ /* XXX 2-byte padding for QoS and 4-addr headers. */
+
+ /* Select the HW Tx queue to use for this frame. */
+ if ((hasqos = ieee80211_has_qos(wh))) {
+#ifdef notyet_edca
+ uint8_t tid;
+
+ qos = ieee80211_get_qos(wh);
+ tid = qos & IEEE80211_QOS_TID;
+ qid = athn_ac2qid[ieee80211_up_to_ac(ic, tid)];
+#else
+ qos = ieee80211_get_qos(wh);
+ qid = ATHN_QID_AC_BE;
+#endif /* notyet_edca */
+ }
+ else if (type == AR_FRAME_TYPE_PSPOLL) {
+ qos = 0;
+ qid = ATHN_QID_PSPOLL;
+ }
+ else if (txflags & ATHN_TXFLAG_CAB) {
+ qos = 0;
+ qid = ATHN_QID_CAB;
+ }
+ else {
+ qos = 0;
+ qid = ATHN_QID_AC_BE;
+ }
+ txq = &sc->sc_txq[qid];
+
+ /* Select the transmit rates to use for this frame. */
+ if (IEEE80211_IS_MULTICAST(wh->i_addr1) ||
+ (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) !=
+ IEEE80211_FC0_TYPE_DATA) {
+ /* Use lowest rate for all tries. */
+ ridx[0] = ridx[1] = ridx[2] = ridx[3] =
+ (ic->ic_curmode == IEEE80211_MODE_11A) ?
+ ATHN_RIDX_OFDM6 : ATHN_RIDX_CCK1;
+ }
+ else if (ic->ic_fixed_rate != -1) {
+ /* Use same fixed rate for all tries. */
+ ridx[0] = ridx[1] = ridx[2] = ridx[3] =
+ sc->sc_fixed_ridx;
+ }
+ else {
+ int txrate = ni->ni_txrate;
+ /* Use fallback table of the node. */
+ for (i = 0; i < 4; i++) {
+ ridx[i] = an->ridx[txrate];
+ txrate = an->fallback[txrate];
+ }
+ }
+
+ if (__predict_false(sc->sc_drvbpf != NULL)) {
+ struct athn_tx_radiotap_header *tap = &sc->sc_txtap;
+
+ tap->wt_flags = 0;
+ /* Use initial transmit rate. */
+ tap->wt_rate = athn_rates[ridx[0]].rate;
+ tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq);
+ tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags);
+// XXX tap->wt_hwqueue = qid;
+ if (ridx[0] != ATHN_RIDX_CCK1 &&
+ (ic->ic_flags & IEEE80211_F_SHPREAMBLE))
+ tap->wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
+
+ bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m);
+ }
+
+ /* DMA map mbuf. */
+ error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_map, m,
+ BUS_DMA_NOWAIT | BUS_DMA_WRITE);
+ if (__predict_false(error != 0)) {
+ if (error != EFBIG) {
+ printf("%s: can't map mbuf (error %d)\n",
+ device_xname(sc->sc_dev), error);
+ m_freem(m);
+ return error;
+ }
+ /*
+ * DMA mapping requires too many DMA segments; linearize
+ * mbuf in kernel virtual address space and retry.
+ */
+ MGETHDR(m1, M_DONTWAIT, MT_DATA);
+ if (m1 == NULL) {
+ m_freem(m);
+ return ENOBUFS;
+ }
+ if (m->m_pkthdr.len > (int)MHLEN) {
+ MCLGET(m1, M_DONTWAIT);
+ if (!(m1->m_flags & M_EXT)) {
+ m_freem(m);
+ m_freem(m1);
+ return ENOBUFS;
+ }
+ }
+ m_copydata(m, 0, m->m_pkthdr.len, mtod(m1, void *));
+ m1->m_pkthdr.len = m1->m_len = m->m_pkthdr.len;
+ m_freem(m);
+ m = m1;
+
+ error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_map, m,
+ BUS_DMA_NOWAIT | BUS_DMA_WRITE);
+ if (error != 0) {
+ printf("%s: can't map mbuf (error %d)\n",
+ device_xname(sc->sc_dev), error);
+ m_freem(m);
+ return error;
+ }
+ }
+ bf->bf_m = m;
+ bf->bf_ni = ni;
+ bf->bf_txflags = txflags;
+
+ wh = mtod(m, struct ieee80211_frame *);
+
+ totlen = m->m_pkthdr.len + IEEE80211_CRC_LEN;
+
+ /* Setup Tx descriptor. */
+ ds = bf->bf_descs;
+ memset(ds, 0, sizeof(*ds));
+
+ ds->ds_info =
+ SM(AR_TXI_DESC_ID, AR_VENDOR_ATHEROS) |
+ SM(AR_TXI_DESC_NDWORDS, 23) |
+ SM(AR_TXI_QCU_NUM, qid) |
+ AR_TXI_DESC_TX | AR_TXI_CTRL_STAT;
+
+ ds->ds_ctl11 = AR_TXC11_CLR_DEST_MASK;
+ txpower = AR_MAX_RATE_POWER; /* Get from per-rate registers. */
+ ds->ds_ctl11 |= SM(AR_TXC11_XMIT_POWER, txpower);
+
+ ds->ds_ctl12 = SM(AR_TXC12_FRAME_TYPE, type);
+
+ if (IEEE80211_IS_MULTICAST(wh->i_addr1) ||
+ (hasqos && (qos & IEEE80211_QOS_ACKPOLICY_MASK) ==
+ IEEE80211_QOS_ACKPOLICY_NOACK))
+ ds->ds_ctl12 |= AR_TXC12_NO_ACK;
+
+#if notyet
+ if (0 && k != NULL) {
+ uintptr_t entry;
+
+ /*
+ * Map 802.11 cipher to hardware encryption type and
+ * compute MIC+ICV overhead.
+ */
+ switch (k->k_cipher) {
+ case IEEE80211_CIPHER_WEP40:
+ case IEEE80211_CIPHER_WEP104:
+ encrtype = AR_ENCR_TYPE_WEP;
+ totlen += 4;
+ break;
+ case IEEE80211_CIPHER_TKIP:
+ encrtype = AR_ENCR_TYPE_TKIP;
+ totlen += 12;
+ break;
+ case IEEE80211_CIPHER_CCMP:
+ encrtype = AR_ENCR_TYPE_AES;
+ totlen += 8;
+ break;
+ default:
+ panic("unsupported cipher");
+ }
+ /*
+ * NB: The key cache entry index is stored in the key
+ * private field when the key is installed.
+ */
+ entry = (uintptr_t)k->k_priv;
+ ds->ds_ctl12 |= SM(AR_TXC12_DEST_IDX, entry);
+ ds->ds_ctl11 |= AR_TXC11_DEST_IDX_VALID;
+ }
+ else
+#endif
+ encrtype = AR_ENCR_TYPE_CLEAR;
+ ds->ds_ctl17 = SM(AR_TXC17_ENCR_TYPE, encrtype);
+
+ /* Check if frame must be protected using RTS/CTS or CTS-to-self. */
+ if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) {
+ /* NB: Group frames are sent using CCK in 802.11b/g. */
+ if (totlen > ic->ic_rtsthreshold) {
+ ds->ds_ctl11 |= AR_TXC11_RTS_ENABLE;
+ }
+ else if ((ic->ic_flags & IEEE80211_F_USEPROT) &&
+ athn_rates[ridx[0]].phy == IEEE80211_T_OFDM) {
+ if (ic->ic_protmode == IEEE80211_PROT_RTSCTS)
+ ds->ds_ctl11 |= AR_TXC11_RTS_ENABLE;
+ else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY)
+ ds->ds_ctl11 |= AR_TXC11_CTS_ENABLE;
+ }
+ }
+ if (ds->ds_ctl11 & (AR_TXC11_RTS_ENABLE | AR_TXC11_CTS_ENABLE)) {
+ /* Disable multi-rate retries when protection is used. */
+ ridx[1] = ridx[2] = ridx[3] = ridx[0];
+ }
+ /* Setup multi-rate retries. */
+ for (i = 0; i < 4; i++) {
+ series[i].hwrate = athn_rates[ridx[i]].hwrate;
+ if (athn_rates[ridx[i]].phy == IEEE80211_T_DS &&
+ ridx[i] != ATHN_RIDX_CCK1 &&
+ (ic->ic_flags & IEEE80211_F_SHPREAMBLE))
+ series[i].hwrate |= 0x04;
+ series[i].dur = 0;
+ }
+ if (!(ds->ds_ctl12 & AR_TXC12_NO_ACK)) {
+ /* Compute duration for each series. */
+ for (i = 0; i < 4; i++) {
+ series[i].dur = athn_txtime(sc, IEEE80211_ACK_LEN,
+ athn_rates[ridx[i]].rspridx, ic->ic_flags);
+ }
+ }
+ /* If this is a PA training frame, select the Tx chain to use. */
+ if (__predict_false(txflags & ATHN_TXFLAG_PAPRD)) {
+ ds->ds_ctl12 |= SM(AR_TXC12_PAPRD_CHAIN_MASK,
+ 1 << sc->sc_paprd_curchain);
+ }
+
+ /* Write number of tries for each series. */
+ ds->ds_ctl13 =
+ SM(AR_TXC13_XMIT_DATA_TRIES0, 2) |
+ SM(AR_TXC13_XMIT_DATA_TRIES1, 2) |
+ SM(AR_TXC13_XMIT_DATA_TRIES2, 2) |
+ SM(AR_TXC13_XMIT_DATA_TRIES3, 4);
+
+ /* Tell HW to update duration field in 802.11 header. */
+ if (type != AR_FRAME_TYPE_PSPOLL)
+ ds->ds_ctl13 |= AR_TXC13_DUR_UPDATE_ENA;
+
+ /* Write Tx rate for each series. */
+ ds->ds_ctl14 =
+ SM(AR_TXC14_XMIT_RATE0, series[0].hwrate) |
+ SM(AR_TXC14_XMIT_RATE1, series[1].hwrate) |
+ SM(AR_TXC14_XMIT_RATE2, series[2].hwrate) |
+ SM(AR_TXC14_XMIT_RATE3, series[3].hwrate);
+
+ /* Write duration for each series. */
+ ds->ds_ctl15 =
+ SM(AR_TXC15_PACKET_DUR0, series[0].dur) |
+ SM(AR_TXC15_PACKET_DUR1, series[1].dur);
+ ds->ds_ctl16 =
+ SM(AR_TXC16_PACKET_DUR2, series[2].dur) |
+ SM(AR_TXC16_PACKET_DUR3, series[3].dur);
+
+ if ((sc->sc_flags & ATHN_FLAG_3TREDUCE_CHAIN) &&
+ ic->ic_curmode == IEEE80211_MODE_11A) {
+ /*
+ * In order to not exceed PCIe power requirements, we only
+ * use two Tx chains for MCS0~15 on 5GHz band on these chips.
+ */
+ ds->ds_ctl18 =
+ SM(AR_TXC18_CHAIN_SEL0,
+ (ridx[0] <= ATHN_RIDX_MCS15) ? 0x3 : sc->sc_txchainmask) |
+ SM(AR_TXC18_CHAIN_SEL1,
+ (ridx[1] <= ATHN_RIDX_MCS15) ? 0x3 : sc->sc_txchainmask) |
+ SM(AR_TXC18_CHAIN_SEL2,
+ (ridx[2] <= ATHN_RIDX_MCS15) ? 0x3 : sc->sc_txchainmask) |
+ SM(AR_TXC18_CHAIN_SEL3,
+ (ridx[3] <= ATHN_RIDX_MCS15) ? 0x3 : sc->sc_txchainmask);
+ }
+ else {
+ /* Use the same Tx chains for all tries. */
+ ds->ds_ctl18 =
+ SM(AR_TXC18_CHAIN_SEL0, sc->sc_txchainmask) |
+ SM(AR_TXC18_CHAIN_SEL1, sc->sc_txchainmask) |
+ SM(AR_TXC18_CHAIN_SEL2, sc->sc_txchainmask) |
+ SM(AR_TXC18_CHAIN_SEL3, sc->sc_txchainmask);
+ }
+#ifdef notyet
+#ifndef IEEE80211_NO_HT
+ /* Use the same short GI setting for all tries. */
+ if (ic->ic_flags & IEEE80211_F_SHGI)
+ ds->ds_ctl18 |= AR_TXC18_GI0123;
+ /* Use the same channel width for all tries. */
+ if (ic->ic_flags & IEEE80211_F_CBW40)
+ ds->ds_ctl18 |= AR_TXC18_2040_0123;
+#endif
+#endif
+
+ if (ds->ds_ctl11 & (AR_TXC11_RTS_ENABLE | AR_TXC11_CTS_ENABLE)) {
+ uint8_t protridx, hwrate;
+ uint16_t dur = 0;
+
+ /* Use the same protection mode for all tries. */
+ if (ds->ds_ctl11 & AR_TXC11_RTS_ENABLE) {
+ ds->ds_ctl15 |= AR_TXC15_RTSCTS_QUAL01;
+ ds->ds_ctl16 |= AR_TXC16_RTSCTS_QUAL23;
+ }
+ /* Select protection rate (suboptimal but ok). */
+ protridx = (ic->ic_curmode == IEEE80211_MODE_11A) ?
+ ATHN_RIDX_OFDM6 : ATHN_RIDX_CCK2;
+ if (ds->ds_ctl11 & AR_TXC11_RTS_ENABLE) {
+ /* Account for CTS duration. */
+ dur += athn_txtime(sc, IEEE80211_ACK_LEN,
+ athn_rates[protridx].rspridx, ic->ic_flags);
+ }
+ dur += athn_txtime(sc, totlen, ridx[0], ic->ic_flags);
+ if (!(ds->ds_ctl12 & AR_TXC12_NO_ACK)) {
+ /* Account for ACK duration. */
+ dur += athn_txtime(sc, IEEE80211_ACK_LEN,
+ athn_rates[ridx[0]].rspridx, ic->ic_flags);
+ }
+ /* Write protection frame duration and rate. */
+ ds->ds_ctl13 |= SM(AR_TXC13_BURST_DUR, dur);
+ hwrate = athn_rates[protridx].hwrate;
+ if (protridx == ATHN_RIDX_CCK2 &&
+ (ic->ic_flags & IEEE80211_F_SHPREAMBLE))
+ hwrate |= 0x04;
+ ds->ds_ctl18 |= SM(AR_TXC18_RTSCTS_RATE, hwrate);
+ }
+
+ ds->ds_ctl11 |= SM(AR_TXC11_FRAME_LEN, totlen);
+ ds->ds_ctl19 = AR_TXC19_NOT_SOUNDING;
+
+ for (i = 0; i < bf->bf_map->dm_nsegs; i++) {
+ ds->ds_segs[i].ds_data = bf->bf_map->dm_segs[i].ds_addr;
+ ds->ds_segs[i].ds_ctl = SM(AR_TXC_BUF_LEN,
+ bf->bf_map->dm_segs[i].ds_len);
+ }
+ /* Compute Tx descriptor checksum. */
+ sum = ds->ds_info + ds->ds_link;
+ for (i = 0; i < 4; i++) {
+ sum += ds->ds_segs[i].ds_data;
+ sum += ds->ds_segs[i].ds_ctl;
+ }
+ sum = (sum >> 16) + (sum & 0xffff);
+ ds->ds_ctl10 = SM(AR_TXC10_PTR_CHK_SUM, sum);
+
+ bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, bf->bf_map->dm_mapsize,
+ BUS_DMASYNC_PREWRITE);
+
+ DPRINTFN(DBG_TX, sc,
+ "Tx qid=%d nsegs=%d ctl11=0x%x ctl12=0x%x ctl14=0x%x\n",
+ qid, bf->bf_map->dm_nsegs, ds->ds_ctl11, ds->ds_ctl12,
+ ds->ds_ctl14);
+
+ SIMPLEQ_REMOVE_HEAD(&sc->sc_txbufs, bf_list);
+ SIMPLEQ_INSERT_TAIL(&txq->head, bf, bf_list);
+
+ /* Queue buffer unless hardware FIFO is already full. */
+ if (++txq->queued <= AR9003_TX_QDEPTH) {
+ AR_WRITE(sc, AR_QTXDP(qid), bf->bf_daddr);
+ AR_WRITE_BARRIER(sc);
+ }
+ else if (txq->wait == NULL)
+ txq->wait = bf;
+ return 0;
+}
+
+Static void
+ar9003_set_rf_mode(struct athn_softc *sc, struct ieee80211_channel *c)
+{
+ uint32_t reg;
+
+ reg = IEEE80211_IS_CHAN_2GHZ(c) ?
+ AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
+ if (IEEE80211_IS_CHAN_5GHZ(c) &&
+ (sc->sc_flags & ATHN_FLAG_FAST_PLL_CLOCK)) {
+ reg |= AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE;
+ }
+ AR_WRITE(sc, AR_PHY_MODE, reg);
+ AR_WRITE_BARRIER(sc);
+}
+
+static __inline uint32_t
+ar9003_synth_delay(struct athn_softc *sc)
+{
+ uint32_t delay;
+
+ delay = MS(AR_READ(sc, AR_PHY_RX_DELAY), AR_PHY_RX_DELAY_DELAY);
+ if (sc->sc_ic.ic_curmode == IEEE80211_MODE_11B)
+ delay = (delay * 4) / 22;
+ else
+ delay = delay / 10; /* in 100ns steps */
+ return delay;
+}
+
+Static int
+ar9003_rf_bus_request(struct athn_softc *sc)
+{
+ int ntries;
+
+ /* Request RF Bus grant. */
+ AR_WRITE(sc, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
+ for (ntries = 0; ntries < 10000; ntries++) {
+ if (AR_READ(sc, AR_PHY_RFBUS_GRANT) & AR_PHY_RFBUS_GRANT_EN)
+ return 0;
+ DELAY(10);
+ }
+ DPRINTFN(DBG_RF, sc, "could not kill baseband Rx");
+ return ETIMEDOUT;
+}
+
+Static void
+ar9003_rf_bus_release(struct athn_softc *sc)
+{
+ /* Wait for the synthesizer to settle. */
+ DELAY(AR_BASE_PHY_ACTIVE_DELAY + ar9003_synth_delay(sc));
+
+ /* Release the RF Bus grant. */
+ AR_WRITE(sc, AR_PHY_RFBUS_REQ, 0);
+ AR_WRITE_BARRIER(sc);
+}
+
+Static void
+ar9003_set_phy(struct athn_softc *sc, struct ieee80211_channel *c,
+ struct ieee80211_channel *extc)
+{
+ uint32_t phy;
+
+ phy = AR_READ(sc, AR_PHY_GEN_CTRL);
+ phy |= AR_PHY_GC_HT_EN | AR_PHY_GC_SHORT_GI_40 |
+ AR_PHY_GC_SINGLE_HT_LTF1 | AR_PHY_GC_WALSH;
+#ifndef IEEE80211_NO_HT
+ if (extc != NULL) {
+ phy |= AR_PHY_GC_DYN2040_EN;
+ if (extc > c) /* XXX */
+ phy |= AR_PHY_GC_DYN2040_PRI_CH;
+ }
+#endif
+ /* Turn off Green Field detection for now. */
+ phy &= ~AR_PHY_GC_GF_DETECT_EN;
+ AR_WRITE(sc, AR_PHY_GEN_CTRL, phy);
+
+ AR_WRITE(sc, AR_2040_MODE,
+ (extc != NULL) ? AR_2040_JOINED_RX_CLEAR : 0);
+
+ /* Set global transmit timeout. */
+ AR_WRITE(sc, AR_GTXTO, SM(AR_GTXTO_TIMEOUT_LIMIT, 25));
+ /* Set carrier sense timeout. */
+ AR_WRITE(sc, AR_CST, SM(AR_CST_TIMEOUT_LIMIT, 15));
+ AR_WRITE_BARRIER(sc);
+}
+
+Static void
+ar9003_set_delta_slope(struct athn_softc *sc, struct ieee80211_channel *c,
+ struct ieee80211_channel *extc)
+{
+ uint32_t coeff, exp, man, reg;
+
+ /* Set Delta Slope (exponent and mantissa). */
+ coeff = (100 << 24) / c->ic_freq;
+ athn_get_delta_slope(coeff, &exp, &man);
+ DPRINTFN(DBG_RF, sc, "delta slope coeff exp=%u man=%u\n", exp, man);
+
+ reg = AR_READ(sc, AR_PHY_TIMING3);
+ reg = RW(reg, AR_PHY_TIMING3_DSC_EXP, exp);
+ reg = RW(reg, AR_PHY_TIMING3_DSC_MAN, man);
+ AR_WRITE(sc, AR_PHY_TIMING3, reg);
+
+ /* For Short GI, coeff is 9/10 that of normal coeff. */
+ coeff = (9 * coeff) / 10;
+ athn_get_delta_slope(coeff, &exp, &man);
+ DPRINTFN(DBG_RF, sc, "delta slope coeff exp=%u man=%u\n", exp, man);
+
+ reg = AR_READ(sc, AR_PHY_SGI_DELTA);
+ reg = RW(reg, AR_PHY_SGI_DSC_EXP, exp);
+ reg = RW(reg, AR_PHY_SGI_DSC_MAN, man);
+ AR_WRITE(sc, AR_PHY_SGI_DELTA, reg);
+ AR_WRITE_BARRIER(sc);
+}
+
+Static void
+ar9003_enable_antenna_diversity(struct athn_softc *sc)
+{
+ AR_SETBITS(sc, AR_PHY_CCK_DETECT,
+ AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);
+ AR_WRITE_BARRIER(sc);
+}
+
+Static void
+ar9003_init_baseband(struct athn_softc *sc)
+{
+ uint32_t synth_delay;
+
+ synth_delay = ar9003_synth_delay(sc);
+ /* Activate the PHY (includes baseband activate and synthesizer on). */
+ AR_WRITE(sc, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
+ AR_WRITE_BARRIER(sc);
+ DELAY(AR_BASE_PHY_ACTIVE_DELAY + synth_delay);
+}
+
+Static void
+ar9003_disable_phy(struct athn_softc *sc)
+{
+ AR_WRITE(sc, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
+ AR_WRITE_BARRIER(sc);
+}
+
+Static void
+ar9003_init_chains(struct athn_softc *sc)
+{
+ if (sc->sc_rxchainmask == 0x5 || sc->sc_txchainmask == 0x5)
+ AR_SETBITS(sc, AR_PHY_ANALOG_SWAP, AR_PHY_SWAP_ALT_CHAIN);
+
+ /* Setup chain masks. */
+ AR_WRITE(sc, AR_PHY_RX_CHAINMASK, sc->sc_rxchainmask);
+ AR_WRITE(sc, AR_PHY_CAL_CHAINMASK, sc->sc_rxchainmask);
+
+ if (sc->sc_flags & ATHN_FLAG_3TREDUCE_CHAIN) {
+ /*
+ * All self-generated frames are sent using two Tx chains
+ * on these chips to not exceed PCIe power requirements.
+ */
+ AR_WRITE(sc, AR_SELFGEN_MASK, 0x3);
+ }
+ else
+ AR_WRITE(sc, AR_SELFGEN_MASK, sc->sc_txchainmask);
+ AR_WRITE_BARRIER(sc);
+}
+
+Static void
+ar9003_set_rxchains(struct athn_softc *sc)
+{
+ if (sc->sc_rxchainmask == 0x3 || sc->sc_rxchainmask == 0x5) {
+ AR_WRITE(sc, AR_PHY_RX_CHAINMASK, sc->sc_rxchainmask);
+ AR_WRITE(sc, AR_PHY_CAL_CHAINMASK, sc->sc_rxchainmask);
+ AR_WRITE_BARRIER(sc);
+ }
+}
+
+#ifdef notused
+Static void
+ar9003_read_noisefloor(struct athn_softc *sc, int16_t *nf, int16_t *nf_ext)
+{
+/* Sign-extends 9-bit value (assumes upper bits are zeroes). */
+#define SIGN_EXT(v) (((v) ^ 0x100) - 0x100)
+ uint32_t reg;
+ int i;
+
+ for (i = 0; i < sc->sc_nrxchains; i++) {
+ reg = AR_READ(sc, AR_PHY_CCA(i));
+ nf[i] = MS(reg, AR_PHY_MINCCA_PWR);
+ nf[i] = SIGN_EXT(nf[i]);
+
+ reg = AR_READ(sc, AR_PHY_EXT_CCA(i));
+ nf_ext[i] = MS(reg, AR_PHY_EXT_MINCCA_PWR);
+ nf_ext[i] = SIGN_EXT(nf_ext[i]);
+ }
+#undef SIGN_EXT
+}
+#endif /* notused */
+
+#ifdef notused
+Static void
+ar9003_write_noisefloor(struct athn_softc *sc, int16_t *nf, int16_t *nf_ext)
+{
+ uint32_t reg;
+ int i;
+
+ for (i = 0; i < sc->sc_nrxchains; i++) {
+ reg = AR_READ(sc, AR_PHY_CCA(i));
+ reg = RW(reg, AR_PHY_MAXCCA_PWR, nf[i]);
+ AR_WRITE(sc, AR_PHY_CCA(i), reg);
+
+ reg = AR_READ(sc, AR_PHY_EXT_CCA(i));
+ reg = RW(reg, AR_PHY_EXT_MAXCCA_PWR, nf_ext[i]);
+ AR_WRITE(sc, AR_PHY_EXT_CCA(i), reg);
+ }
+ AR_WRITE_BARRIER(sc);
+}
+#endif /* notused */
+
+#ifdef notused
+Static void
+ar9003_get_noisefloor(struct athn_softc *sc, struct ieee80211_channel *c)
+{
+ int16_t nf[AR_MAX_CHAINS], nf_ext[AR_MAX_CHAINS];
+ int16_t cca_min, cca_max;
+ int i;
+
+ if (AR_READ(sc, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) {
+ /* Noisefloor calibration not finished. */
+ return;
+ }
+ /* Noisefloor calibration is finished. */
+ ar9003_read_noisefloor(sc, nf, nf_ext);
+
+ if (IEEE80211_IS_CHAN_2GHZ(c)) {
+ cca_min = sc->sc_cca_min_2g;
+ cca_max = sc->sc_cca_max_2g;
+ }
+ else {
+ cca_min = sc->sc_cca_min_5g;
+ cca_max = sc->sc_cca_max_5g;
+ }
+ /* Update noisefloor history. */
+ for (i = 0; i < sc->sc_nrxchains; i++) {
+ if (nf[i] < cca_min)
+ nf[i] = cca_min;
+ else if (nf[i] > cca_max)
+ nf[i] = cca_max;
+ if (nf_ext[i] < cca_min)
+ nf_ext[i] = cca_min;
+ else if (nf_ext[i] > cca_max)
+ nf_ext[i] = cca_max;
+
+ sc->sc_nf_hist[sc->sc_nf_hist_cur].nf[i] = nf[i];
+ sc->sc_nf_hist[sc->sc_nf_hist_cur].nf_ext[i] = nf_ext[i];
+ }
+ if (++sc->sc_nf_hist_cur >= ATHN_NF_CAL_HIST_MAX)
+ sc->sc_nf_hist_cur = 0;
+}
+#endif /* notused */
+
+#ifdef notused
+Static void
+ar9003_bb_load_noisefloor(struct athn_softc *sc)
+{
+ int16_t nf[AR_MAX_CHAINS], nf_ext[AR_MAX_CHAINS];
+ int i, ntries;
+
+ /* Write filtered noisefloor values. */
+ for (i = 0; i < sc->sc_nrxchains; i++) {
+ nf[i] = sc->sc_nf_priv[i] * 2;
+ nf_ext[i] = sc->sc_nf_ext_priv[i] * 2;
+ }
+ ar9003_write_noisefloor(sc, nf, nf_ext);
+
+ /* Load filtered noisefloor values into baseband. */
+ AR_CLRBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF);
+ AR_CLRBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
+ AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
+ /* Wait for load to complete. */
+ for (ntries = 0; ntries < 1000; ntries++) {
+ if (!(AR_READ(sc, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF))
+ break;
+ DELAY(10);
+ }
+ if (ntries == 1000) {
+ DPRINTFN(DBG_RF, sc, "failed to load noisefloor values\n");
+ return;
+ }
+
+ /* Restore noisefloor values to initial (max) values. */
+ for (i = 0; i < AR_MAX_CHAINS; i++)
+ nf[i] = nf_ext[i] = -50 * 2;
+ ar9003_write_noisefloor(sc, nf, nf_ext);
+}
+#endif /* notused */
+
+#ifdef notused
+Static void
+ar9300_noisefloor_calib(struct athn_softc *sc)
+{
+
+ AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF);
+ AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
+ AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
+}
+#endif /* notused */
+
+Static void
+ar9003_do_noisefloor_calib(struct athn_softc *sc)
+{
+
+ AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
+}
+
+PUBLIC int
+ar9003_init_calib(struct athn_softc *sc)
+{
+ uint8_t txchainmask, rxchainmask;
+ uint32_t reg;
+ int ntries;
+
+ /* Save chains masks. */
+ txchainmask = sc->sc_txchainmask;
+ rxchainmask = sc->sc_rxchainmask;
+ /* Configure hardware before calibration. */
+ if (AR_READ(sc, AR_ENT_OTP) & AR_ENT_OTP_CHAIN2_DISABLE)
+ txchainmask = rxchainmask = 0x3;
+ else
+ txchainmask = rxchainmask = 0x7;
+ ar9003_init_chains(sc);
+
+ /* Perform Tx IQ calibration. */
+ ar9003_calib_tx_iq(sc);
+ /* Disable and re-enable the PHY chips. */
+ AR_WRITE(sc, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
+ AR_WRITE_BARRIER(sc);
+ DELAY(5);
+ AR_WRITE(sc, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
+
+ /* Calibrate the AGC. */
+ AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
+ /* Poll for offset calibration completion. */
+ for (ntries = 0; ntries < 10000; ntries++) {
+ reg = AR_READ(sc, AR_PHY_AGC_CONTROL);
+ if (!(reg & AR_PHY_AGC_CONTROL_CAL))
+ break;
+ DELAY(10);
+ }
+ if (ntries == 10000)
+ return ETIMEDOUT;
+
+ /* Restore chains masks. */
+ sc->sc_txchainmask = txchainmask;
+ sc->sc_rxchainmask = rxchainmask;
+ ar9003_init_chains(sc);
+
+ return 0;
+}
+
+Static void
+ar9003_do_calib(struct athn_softc *sc)
+{
+ uint32_t reg;
+
+ if (sc->sc_cur_calib_mask & ATHN_CAL_IQ) {
+ reg = AR_READ(sc, AR_PHY_TIMING4);
+ reg = RW(reg, AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX, 10);
+ AR_WRITE(sc, AR_PHY_TIMING4, reg);
+ AR_WRITE(sc, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ);
+ AR_SETBITS(sc, AR_PHY_TIMING4, AR_PHY_TIMING4_DO_CAL);
+ AR_WRITE_BARRIER(sc);
+ }
+ else if (sc->sc_cur_calib_mask & ATHN_CAL_TEMP) {
+ AR_SETBITS(sc, AR_PHY_65NM_CH0_THERM,
+ AR_PHY_65NM_CH0_THERM_LOCAL);
+ AR_SETBITS(sc, AR_PHY_65NM_CH0_THERM,
+ AR_PHY_65NM_CH0_THERM_START);
+ AR_WRITE_BARRIER(sc);
+ }
+}
+
+Static void
+ar9003_next_calib(struct athn_softc *sc)
+{
+ /* Check if we have any calibration in progress. */
+ if (sc->sc_cur_calib_mask != 0) {
+ if (!(AR_READ(sc, AR_PHY_TIMING4) & AR_PHY_TIMING4_DO_CAL)) {
+ /* Calibration completed for current sample. */
+ ar9003_calib_iq(sc);
+ }
+ }
+}
+
+Static void
+ar9003_calib_iq(struct athn_softc *sc)
+{
+ struct athn_iq_cal *cal;
+ uint32_t reg, i_coff_denom, q_coff_denom;
+ int32_t i_coff, q_coff;
+ int i, iq_corr_neg;
+
+ for (i = 0; i < AR_MAX_CHAINS; i++) {
+ cal = &sc->sc_calib.iq[i];
+
+ /* Read IQ calibration measures (clear on read). */
+ cal->pwr_meas_i = AR_READ(sc, AR_PHY_IQ_ADC_MEAS_0_B(i));
+ cal->pwr_meas_q = AR_READ(sc, AR_PHY_IQ_ADC_MEAS_1_B(i));
+ cal->iq_corr_meas =
+ (int32_t)AR_READ(sc, AR_PHY_IQ_ADC_MEAS_2_B(i));
+ }
+
+ for (i = 0; i < sc->sc_nrxchains; i++) {
+ cal = &sc->sc_calib.iq[i];
+
+ if (cal->pwr_meas_q == 0)
+ continue;
+
+ if ((iq_corr_neg = cal->iq_corr_meas < 0))
+ cal->iq_corr_meas = -cal->iq_corr_meas;
+
+ i_coff_denom =
+ (cal->pwr_meas_i / 2 + cal->pwr_meas_q / 2) / 256;
+ q_coff_denom = cal->pwr_meas_q / 64;
+
+ if (i_coff_denom == 0 || q_coff_denom == 0)
+ continue; /* Prevents division by zero. */
+
+ i_coff = cal->iq_corr_meas / i_coff_denom;
+ q_coff = (cal->pwr_meas_i / q_coff_denom) - 64;
+
+ if (i_coff > 63)
+ i_coff = 63;
+ else if (i_coff < -63)
+ i_coff = -63;
+ /* Negate i_coff if iq_corr_meas is positive. */
+ if (!iq_corr_neg)
+ i_coff = -i_coff;
+ if (q_coff > 63)
+ q_coff = 63;
+ else if (q_coff < -63)
+ q_coff = -63;
+
+ DPRINTFN(DBG_RF, sc, "IQ calibration for chain %d\n", i);
+ reg = AR_READ(sc, AR_PHY_RX_IQCAL_CORR_B(i));
+ reg = RW(reg, AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF, i_coff);
+ reg = RW(reg, AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF, q_coff);
+ AR_WRITE(sc, AR_PHY_RX_IQCAL_CORR_B(i), reg);
+ }
+
+ /* Apply new settings. */
+ AR_SETBITS(sc, AR_PHY_RX_IQCAL_CORR_B(0),
+ AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE);
+ AR_WRITE_BARRIER(sc);
+
+ /* IQ calibration done. */
+ sc->sc_cur_calib_mask &= ~ATHN_CAL_IQ;
+ memset(&sc->sc_calib, 0, sizeof(sc->sc_calib));
+}
+
+#define DELPT 32
+Static int
+ar9003_get_iq_corr(struct athn_softc *sc, int32_t res[6], int32_t coeff[2])
+{
+/* Sign-extends 12-bit value (assumes upper bits are zeroes). */
+#define SIGN_EXT(v) (((v) ^ 0x800) - 0x800)
+#define SCALE (1 << 15)
+#define SHIFT (1 << 8)
+ struct {
+ int32_t m, p, c;
+ } val[2][2];
+ int32_t mag[2][2], phs[2][2], cos[2], sin[2];
+ int32_t div, f1, f2, f3, m, p, c;
+ int32_t txmag, txphs, rxmag, rxphs;
+ int32_t q_coff, i_coff;
+ int i, j;
+
+ /* Extract our twelve signed 12-bit values from res[] array. */
+ val[0][0].m = res[0] & 0xfff;
+ val[0][0].p = (res[0] >> 12) & 0xfff;
+ val[0][0].c = ((res[0] >> 24) & 0xff) | (res[1] & 0xf) << 8;
+
+ val[0][1].m = (res[1] >> 4) & 0xfff;
+ val[0][1].p = res[2] & 0xfff;
+ val[0][1].c = (res[2] >> 12) & 0xfff;
+
+ val[1][0].m = ((res[2] >> 24) & 0xff) | (res[3] & 0xf) << 8;
+ val[1][0].p = (res[3] >> 4) & 0xfff;
+ val[1][0].c = res[4] & 0xfff;
+
+ val[1][1].m = (res[4] >> 12) & 0xfff;
+ val[1][1].p = ((res[4] >> 24) & 0xff) | (res[5] & 0xf) << 8;
+ val[1][1].c = (res[5] >> 4) & 0xfff;
+
+ for (i = 0; i < 2; i++) {
+ int32_t ymin, ymax;
+ for (j = 0; j < 2; j++) {
+ m = SIGN_EXT(val[i][j].m);
+ p = SIGN_EXT(val[i][j].p);
+ c = SIGN_EXT(val[i][j].c);
+
+ if (p == 0)
+ return 1; /* Prevent division by 0. */
+
+ mag[i][j] = (m * SCALE) / p;
+ phs[i][j] = (c * SCALE) / p;
+ }
+ sin[i] = ((mag[i][0] - mag[i][1]) * SHIFT) / DELPT;
+ cos[i] = ((phs[i][0] - phs[i][1]) * SHIFT) / DELPT;
+ /* Find magnitude by approximation. */
+ ymin = MIN(abs(sin[i]), abs(cos[i]));
+ ymax = MAX(abs(sin[i]), abs(cos[i]));
+ div = ymax - (ymax / 32) + (ymin / 8) + (ymin / 4);
+ if (div == 0)
+ return 1; /* Prevent division by 0. */
+ /* Normalize sin and cos by magnitude. */
+ sin[i] = (sin[i] * SCALE) / div;
+ cos[i] = (cos[i] * SCALE) / div;
+ }
+
+ /* Compute IQ mismatch (solve 4x4 linear equation). */
+ f1 = cos[0] - cos[1];
+ f3 = sin[0] - sin[1];
+ f2 = (f1 * f1 + f3 * f3) / SCALE;
+ if (f2 == 0)
+ return 1; /* Prevent division by 0. */
+
+ /* Compute Tx magnitude mismatch. */
+ txmag = (f1 * ( mag[0][0] - mag[1][0]) +
+ f3 * ( phs[0][0] - phs[1][0])) / f2;
+ /* Compute Tx phase mismatch. */
+ txphs = (f3 * (-mag[0][0] + mag[1][0]) +
+ f1 * ( phs[0][0] - phs[1][0])) / f2;
+
+ if (txmag == SCALE)
+ return 1; /* Prevent division by 0. */
+
+ /* Compute Rx magnitude mismatch. */
+ rxmag = mag[0][0] - (cos[0] * txmag + sin[0] * txphs) / SCALE;
+ /* Compute Rx phase mismatch. */
+ rxphs = phs[0][0] + (sin[0] * txmag - cos[0] * txphs) / SCALE;
+
+ if (-rxmag == SCALE)
+ return 1; /* Prevent division by 0. */
+
+ txmag = (txmag * SCALE) / (SCALE - txmag);
+ txphs = -txphs;
+
+ q_coff = (txmag * 128) / SCALE;
+ if (q_coff < -63)
+ q_coff = -63;
+ else if (q_coff > 63)
+ q_coff = 63;
+ i_coff = (txphs * 256) / SCALE;
+ if (i_coff < -63)
+ i_coff = -63;
+ else if (i_coff > 63)
+ i_coff = 63;
+ coeff[0] = q_coff * 128 + i_coff;
+
+ rxmag = (-rxmag * SCALE) / (SCALE + rxmag);
+ rxphs = -rxphs;
+
+ q_coff = (rxmag * 128) / SCALE;
+ if (q_coff < -63)
+ q_coff = -63;
+ else if (q_coff > 63)
+ q_coff = 63;
+ i_coff = (rxphs * 256) / SCALE;
+ if (i_coff < -63)
+ i_coff = -63;
+ else if (i_coff > 63)
+ i_coff = 63;
+ coeff[1] = q_coff * 128 + i_coff;
+
+ return 0;
+#undef SHIFT
+#undef SCALE
+#undef SIGN_EXT
+}
+
+Static int
+ar9003_calib_tx_iq(struct athn_softc *sc)
+{
+ uint32_t reg;
+ int32_t res[6], coeff[2];
+ int i, j, ntries;
+
+ reg = AR_READ(sc, AR_PHY_TX_IQCAL_CONTROL_1);
+ reg = RW(reg, AR_PHY_TX_IQCAQL_CONTROL_1_IQCORR_I_Q_COFF_DELPT, DELPT);
+ AR_WRITE(sc, AR_PHY_TX_IQCAL_CONTROL_1, reg);
+
+ /* Start Tx IQ calibration. */
+ AR_SETBITS(sc, AR_PHY_TX_IQCAL_START, AR_PHY_TX_IQCAL_START_DO_CAL);
+ /* Wait for completion. */
+ for (ntries = 0; ntries < 10000; ntries++) {
+ reg = AR_READ(sc, AR_PHY_TX_IQCAL_START);
+ if (!(reg & AR_PHY_TX_IQCAL_START_DO_CAL))
+ break;
+ DELAY(10);
+ }
+ if (ntries == 10000)
+ return ETIMEDOUT;
+
+ for (i = 0; i < sc->sc_ntxchains; i++) {
+ /* Read Tx IQ calibration status for this chain. */
+ reg = AR_READ(sc, AR_PHY_TX_IQCAL_STATUS_B(i));
+ if (reg & AR_PHY_TX_IQCAL_STATUS_FAILED)
+ return EIO;
+ /*
+ * Read Tx IQ calibration results for this chain.
+ * This consists in twelve signed 12-bit values.
+ */
+ for (j = 0; j < 3; j++) {
+ AR_CLRBITS(sc, AR_PHY_CHAN_INFO_MEMORY,
+ AR_PHY_CHAN_INFO_TAB_S2_READ);
+ reg = AR_READ(sc, AR_PHY_CHAN_INFO_TAB(i, j));
+ res[j * 2 + 0] = reg;
+
+ AR_SETBITS(sc, AR_PHY_CHAN_INFO_MEMORY,
+ AR_PHY_CHAN_INFO_TAB_S2_READ);
+ reg = AR_READ(sc, AR_PHY_CHAN_INFO_TAB(i, j));
+ res[j * 2 + 1] = reg & 0xffff;
+ }
+
+ /* Compute Tx IQ correction. */
+ if (ar9003_get_iq_corr(sc, res, coeff) != 0)
+ return EIO;
+
+ /* Write Tx IQ correction coefficients. */
+ reg = AR_READ(sc, AR_PHY_TX_IQCAL_CORR_COEFF_01_B(i));
+ reg = RW(reg, AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE,
+ coeff[0]);
+ AR_WRITE(sc, AR_PHY_TX_IQCAL_CORR_COEFF_01_B(i), reg);
+
+ reg = AR_READ(sc, AR_PHY_RX_IQCAL_CORR_B(i));
+ reg = RW(reg, AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_Q_COFF,
+ coeff[1] >> 7);
+ reg = RW(reg, AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_I_COFF,
+ coeff[1]);
+ AR_WRITE(sc, AR_PHY_RX_IQCAL_CORR_B(i), reg);
+ AR_WRITE_BARRIER(sc);
+ }
+
+ /* Enable Tx IQ correction. */
+ AR_SETBITS(sc, AR_PHY_TX_IQCAL_CONTROL_3,
+ AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN);
+ AR_SETBITS(sc, AR_PHY_RX_IQCAL_CORR_B(0),
+ AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN);
+ AR_WRITE_BARRIER(sc);
+ return 0;
+}
+#undef DELPT
+
+/*-
+ * The power amplifier predistortion state machine works as follows:
+ * 1) Disable digital predistorters for all Tx chains
+ * 2) Repeat steps 3~7 for all Tx chains
+ * 3) Force Tx gain to that of training signal
+ * 4) Send training signal (asynchronous)
+ * 5) Wait for training signal to complete (asynchronous)
+ * 6) Read PA measurements (input power, output power, output phase)
+ * 7) Compute the predistortion function that linearizes PA output
+ * 8) Write predistortion functions to hardware tables for all Tx chains
+ * 9) Enable digital predistorters for all Tx chains
+ */
+#ifdef notused
+Static void
+ar9003_paprd_calib(struct athn_softc *sc, struct ieee80211_channel *c)
+{
+ static const int scaling[] = {
+ 261376, 248079, 233759, 220464,
+ 208194, 196949, 185706, 175487
+ };
+ struct athn_ops *ops = &sc->sc_ops;
+ uint32_t reg, ht20mask, ht40mask;
+ int i;
+
+ /* Read PA predistortion masks from ROM. */
+ ops->get_paprd_masks(sc, c, &ht20mask, &ht40mask);
+
+ /* AM-to-AM: amplifier's amplitude characteristic. */
+ reg = AR_READ(sc, AR_PHY_PAPRD_AM2AM);
+ reg = RW(reg, AR_PHY_PAPRD_AM2AM_MASK, ht20mask);
+ AR_WRITE(sc, AR_PHY_PAPRD_AM2AM, reg);
+
+ /* AM-to-PM: amplifier's phase transfer characteristic. */
+ reg = AR_READ(sc, AR_PHY_PAPRD_AM2PM);
+ reg = RW(reg, AR_PHY_PAPRD_AM2PM_MASK, ht20mask);
+ AR_WRITE(sc, AR_PHY_PAPRD_AM2PM, reg);
+
+ reg = AR_READ(sc, AR_PHY_PAPRD_HT40);
+ reg = RW(reg, AR_PHY_PAPRD_HT40_MASK, ht40mask);
+ AR_WRITE(sc, AR_PHY_PAPRD_HT40, reg);
+
+ for (i = 0; i < AR9003_MAX_CHAINS; i++) {
+ AR_SETBITS(sc, AR_PHY_PAPRD_CTRL0_B(i),
+ AR_PHY_PAPRD_CTRL0_USE_SINGLE_TABLE);
+
+ reg = AR_READ(sc, AR_PHY_PAPRD_CTRL1_B(i));
+ reg = RW(reg, AR_PHY_PAPRD_CTRL1_PA_GAIN_SCALE_FACT, 181);
+ reg = RW(reg, AR_PHY_PAPRD_CTRL1_MAG_SCALE_FACT, 361);
+ reg &= ~AR_PHY_PAPRD_CTRL1_ADAPTIVE_SCALING_ENA;
+ reg |= AR_PHY_PAPRD_CTRL1_ADAPTIVE_AM2AM_ENA;
+ reg |= AR_PHY_PAPRD_CTRL1_ADAPTIVE_AM2PM_ENA;
+ AR_WRITE(sc, AR_PHY_PAPRD_CTRL1_B(i), reg);
+
+ reg = AR_READ(sc, AR_PHY_PAPRD_CTRL0_B(i));
+ reg = RW(reg, AR_PHY_PAPRD_CTRL0_PAPRD_MAG_THRSH, 3);
+ AR_WRITE(sc, AR_PHY_PAPRD_CTRL0_B(i), reg);
+ }
+
+ /* Disable all digital predistorters during calibration. */
+ for (i = 0; i < AR9003_MAX_CHAINS; i++) {
+ AR_CLRBITS(sc, AR_PHY_PAPRD_CTRL0_B(i),
+ AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE);
+ }
+ AR_WRITE_BARRIER(sc);
+
+ /*
+ * Configure training signal.
+ */
+ reg = AR_READ(sc, AR_PHY_PAPRD_TRAINER_CNTL1);
+ reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL1_AGC2_SETTLING, 28);
+ reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL1_LB_SKIP, 0x30);
+ reg &= ~AR_PHY_PAPRD_TRAINER_CNTL1_RX_BB_GAIN_FORCE;
+ reg &= ~AR_PHY_PAPRD_TRAINER_CNTL1_IQCORR_ENABLE;
+ reg |= AR_PHY_PAPRD_TRAINER_CNTL1_LB_ENABLE;
+ reg |= AR_PHY_PAPRD_TRAINER_CNTL1_TX_GAIN_FORCE;
+ reg |= AR_PHY_PAPRD_TRAINER_CNTL1_TRAIN_ENABLE;
+ AR_WRITE(sc, AR_PHY_PAPRD_TRAINER_CNTL1, reg);
+
+ AR_WRITE(sc, AR_PHY_PAPRD_TRAINER_CNTL2, 147);
+
+ reg = AR_READ(sc, AR_PHY_PAPRD_TRAINER_CNTL3);
+ reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL3_FINE_CORR_LEN, 4);
+ reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL3_COARSE_CORR_LEN, 4);
+ reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL3_NUM_CORR_STAGES, 7);
+ reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL3_MIN_LOOPBACK_DEL, 1);
+ if (AR_SREV_9485(sc))
+ reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL3_QUICK_DROP, -3);
+ else
+ reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL3_QUICK_DROP, -6);
+ reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL3_ADC_DESIRED_SIZE, -15);
+ reg |= AR_PHY_PAPRD_TRAINER_CNTL3_BBTXMIX_DISABLE;
+ AR_WRITE(sc, AR_PHY_PAPRD_TRAINER_CNTL3, reg);
+
+ reg = AR_READ(sc, AR_PHY_PAPRD_TRAINER_CNTL4);
+ reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL4_SAFETY_DELTA, 0);
+ reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL4_MIN_CORR, 400);
+ reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL4_NUM_TRAIN_SAMPLES, 100);
+ AR_WRITE(sc, AR_PHY_PAPRD_TRAINER_CNTL4, reg);
+
+ for (i = 0; i < __arraycount(scaling); i++) {
+ reg = AR_READ(sc, AR_PHY_PAPRD_PRE_POST_SCALE_B0(i));
+ reg = RW(reg, AR_PHY_PAPRD_PRE_POST_SCALING, scaling[i]);
+ AR_WRITE(sc, AR_PHY_PAPRD_PRE_POST_SCALE_B0(i), reg);
+ }
+
+ /* Save Tx gain table. */
+ for (i = 0; i < AR9003_TX_GAIN_TABLE_SIZE; i++)
+ sc->sc_txgain[i] = AR_READ(sc, AR_PHY_TXGAIN_TABLE(i));
+
+ /* Set Tx power of training signal (use setting for MCS0). */
+ sc->sc_trainpow = MS(AR_READ(sc, AR_PHY_PWRTX_RATE5),
+ AR_PHY_PWRTX_RATE5_POWERTXHT20_0) - 4;
+
+ /*
+ * Start PA predistortion calibration state machine.
+ */
+ /* Find first available Tx chain. */
+ sc->sc_paprd_curchain = 0;
+ while (!(sc->sc_txchainmask & (1 << sc->sc_paprd_curchain)))
+ sc->sc_paprd_curchain++;
+
+ /* Make sure training done bit is clear. */
+ AR_CLRBITS(sc, AR_PHY_PAPRD_TRAINER_STAT1,
+ AR_PHY_PAPRD_TRAINER_STAT1_TRAIN_DONE);
+ AR_WRITE_BARRIER(sc);
+
+ /* Transmit training signal. */
+ ar9003_paprd_tx_tone(sc);
+}
+#endif /* notused */
+
+Static int
+ar9003_get_desired_txgain(struct athn_softc *sc, int chain, int pow)
+{
+ int32_t scale, atemp, avolt, tempcal, voltcal, temp, volt;
+ int32_t tempcorr, voltcorr;
+ uint32_t reg;
+ int8_t delta;
+
+ scale = MS(AR_READ(sc, AR_PHY_TPC_12),
+ AR_PHY_TPC_12_DESIRED_SCALE_HT40_5);
+
+ reg = AR_READ(sc, AR_PHY_TPC_19);
+ atemp = MS(reg, AR_PHY_TPC_19_ALPHA_THERM);
+ avolt = MS(reg, AR_PHY_TPC_19_ALPHA_VOLT);
+
+ reg = AR_READ(sc, AR_PHY_TPC_18);
+ tempcal = MS(reg, AR_PHY_TPC_18_THERM_CAL);
+ voltcal = MS(reg, AR_PHY_TPC_18_VOLT_CAL);
+
+ reg = AR_READ(sc, AR_PHY_BB_THERM_ADC_4);
+ temp = MS(reg, AR_PHY_BB_THERM_ADC_4_LATEST_THERM);
+ volt = MS(reg, AR_PHY_BB_THERM_ADC_4_LATEST_VOLT);
+
+ delta = (int8_t)MS(AR_READ(sc, AR_PHY_TPC_11_B(chain)),
+ AR_PHY_TPC_11_OLPC_GAIN_DELTA);
+
+ /* Compute temperature and voltage correction. */
+ tempcorr = (atemp * (temp - tempcal) + 128) / 256;
+ voltcorr = (avolt * (volt - voltcal) + 64) / 128;
+
+ /* Compute desired Tx gain. */
+ return pow - delta - tempcorr - voltcorr + scale;
+}
+
+Static void
+ar9003_force_txgain(struct athn_softc *sc, uint32_t txgain)
+{
+ uint32_t reg;
+
+ reg = AR_READ(sc, AR_PHY_TX_FORCED_GAIN);
+ reg = RW(reg, AR_PHY_TX_FORCED_GAIN_TXBB1DBGAIN,
+ MS(txgain, AR_PHY_TXGAIN_TXBB1DBGAIN));
+ reg = RW(reg, AR_PHY_TX_FORCED_GAIN_TXBB6DBGAIN,
+ MS(txgain, AR_PHY_TXGAIN_TXBB6DBGAIN));
+ reg = RW(reg, AR_PHY_TX_FORCED_GAIN_TXMXRGAIN,
+ MS(txgain, AR_PHY_TXGAIN_TXMXRGAIN));
+ reg = RW(reg, AR_PHY_TX_FORCED_GAIN_PADRVGNA,
+ MS(txgain, AR_PHY_TXGAIN_PADRVGNA));
+ reg = RW(reg, AR_PHY_TX_FORCED_GAIN_PADRVGNB,
+ MS(txgain, AR_PHY_TXGAIN_PADRVGNB));
+ reg = RW(reg, AR_PHY_TX_FORCED_GAIN_PADRVGNC,
+ MS(txgain, AR_PHY_TXGAIN_PADRVGNC));
+ reg = RW(reg, AR_PHY_TX_FORCED_GAIN_PADRVGND,
+ MS(txgain, AR_PHY_TXGAIN_PADRVGND));
+ reg &= ~AR_PHY_TX_FORCED_GAIN_ENABLE_PAL;
+ reg &= ~AR_PHY_TX_FORCED_GAIN_FORCE_TX_GAIN;
+ AR_WRITE(sc, AR_PHY_TX_FORCED_GAIN, reg);
+
+ reg = AR_READ(sc, AR_PHY_TPC_1);
+ reg = RW(reg, AR_PHY_TPC_1_FORCED_DAC_GAIN, 0);
+ reg &= ~AR_PHY_TPC_1_FORCE_DAC_GAIN;
+ AR_WRITE(sc, AR_PHY_TPC_1, reg);
+ AR_WRITE_BARRIER(sc);
+}
+
+Static void
+ar9003_set_training_gain(struct athn_softc *sc, int chain)
+{
+ size_t i;
+ int gain;
+
+ /*
+ * Get desired gain for training signal power (take into account
+ * current temperature/voltage).
+ */
+ gain = ar9003_get_desired_txgain(sc, chain, sc->sc_trainpow);
+ /* Find entry in table. */
+ for (i = 0; i < AR9003_TX_GAIN_TABLE_SIZE - 1; i++)
+ if ((int)MS(sc->sc_txgain[i], AR_PHY_TXGAIN_INDEX) >= gain)
+ break;
+ ar9003_force_txgain(sc, sc->sc_txgain[i]);
+}
+
+Static int
+ar9003_paprd_tx_tone(struct athn_softc *sc)
+{
+#define TONE_LEN 1800
+ struct ieee80211com *ic = &sc->sc_ic;
+ struct ieee80211_frame *wh;
+ struct ieee80211_node *ni;
+ struct mbuf *m;
+ int error;
+
+ /* Build a Null (no data) frame of TONE_LEN bytes. */
+ m = MCLGETI(NULL, M_DONTWAIT, NULL, TONE_LEN);
+ if (m == NULL)
+ return ENOBUFS;
+ memset(mtod(m, void *), 0, TONE_LEN);
+ wh = mtod(m, struct ieee80211_frame *);
+ wh->i_fc[0] = IEEE80211_FC0_TYPE_DATA | IEEE80211_FC0_SUBTYPE_NODATA;
+ wh->i_fc[1] = IEEE80211_FC1_DIR_NODS;
+ *(uint16_t *)wh->i_dur = htole16(10); /* XXX */
+ IEEE80211_ADDR_COPY(wh->i_addr1, ic->ic_myaddr);
+ IEEE80211_ADDR_COPY(wh->i_addr2, ic->ic_myaddr);
+ IEEE80211_ADDR_COPY(wh->i_addr3, ic->ic_myaddr);
+ m->m_pkthdr.len = m->m_len = TONE_LEN;
+
+ /* Set gain of training signal. */
+ ar9003_set_training_gain(sc, sc->sc_paprd_curchain);
+
+ /* Transmit training signal. */
+ ni = ieee80211_ref_node(ic->ic_bss);
+ if ((error = ar9003_tx(sc, m, ni, ATHN_TXFLAG_PAPRD)) != 0)
+ ieee80211_free_node(ni);
+ return error;
+#undef TONE_LEN
+}
+
+static __inline int
+get_scale(int val)
+{
+ int log = 0;
+
+ /* Find the log base 2 (position of highest bit set). */
+ while (val >>= 1)
+ log++;
+
+ return (log > 10) ? log - 10 : 0;
+}
+
+/*
+ * Compute predistortion function to linearize power amplifier output based
+ * on feedback from training signal.
+ */
+Static int
+ar9003_compute_predistortion(struct athn_softc *sc, const uint32_t *lo,
+ const uint32_t *hi)
+{
+#define NBINS 23
+ int chain = sc->sc_paprd_curchain;
+ int x[NBINS + 1], y[NBINS + 1], t[NBINS + 1];
+ int b1[NBINS + 1], b2[NBINS + 1], xtilde[NBINS + 1];
+ int nsamples, txsum, rxsum, rosum, maxidx;
+ int order, order5x, order5xrem, order3x, order3xrem, y5, y3;
+ int icept, G, I, L, M, angle, xnonlin, y2, y4, sumy2, sumy4;
+ int alpha, beta, scale, Qalpha, Qbeta, Qscale, Qx, Qb1, Qb2;
+ int tavg, ttilde, maxb1abs, maxb2abs, maxxtildeabs, in;
+ int tmp, i;
+
+ /* Set values at origin. */
+ x[0] = y[0] = t[0] = 0;
+
+#define SCALE 32
+ maxidx = 0;
+ for (i = 0; i < NBINS; i++) {
+ nsamples = lo[i] & 0xffff;
+ /* Skip bins that contain 16 or less samples. */
+ if (nsamples <= 16) {
+ x[i + 1] = y[i + 1] = t[i + 1] = 0;
+ continue;
+ }
+ txsum = (hi[i] & 0x7ff) << 16 | lo[i] >> 16;
+ rxsum = (lo[i + NBINS] & 0xffff) << 5 |
+ ((hi[i] >> 11) & 0x1f);
+ rosum = (hi[i + NBINS] & 0x7ff) << 16 | hi[i + NBINS] >> 16;
+ /* Sign-extend 27-bit value. */
+ rosum = (rosum ^ 0x4000000) - 0x4000000;
+
+ txsum *= SCALE;
+ rxsum *= SCALE;
+ rosum *= SCALE;
+
+ x[i + 1] = ((txsum + nsamples) / nsamples + SCALE) / SCALE;
+ y[i + 1] = ((rxsum + nsamples) / nsamples + SCALE) / SCALE +
+ SCALE * maxidx + SCALE / 2;
+ t[i + 1] = (rosum + nsamples) / nsamples;
+ maxidx++;
+ }
+#undef SCALE
+
+#define SCALE_LOG 8
+#define SCALE (1 << SCALE_LOG)
+ if (x[6] == x[3])
+ return 1; /* Prevent division by 0. */
+ G = ((y[6] - y[3]) * SCALE + (x[6] - x[3])) / (x[6] - x[3]);
+ if (G == 0)
+ return 1; /* Prevent division by 0. */
+
+ sc->sc_gain1[chain] = G; /* Save low signal gain. */
+
+ /* Find interception point. */
+ icept = (G * (x[0] - x[3]) + SCALE) / SCALE + y[3];
+ for (i = 0; i <= 3; i++) {
+ y[i] = i * 32;
+ x[i] = (y[i] * SCALE + G) / G;
+ }
+ for (i = 4; i <= maxidx; i++)
+ y[i] -= icept;
+
+ xnonlin = x[maxidx] - (y[maxidx] * SCALE + G) / G;
+ order = (xnonlin + y[maxidx]) / y[maxidx];
+ if (order == 0)
+ M = 10;
+ else if (order == 1)
+ M = 9;
+ else
+ M = 8;
+
+ I = (maxidx >= 16) ? 7 : maxidx / 2;
+ L = maxidx - I;
+
+ sumy2 = sumy4 = y2 = y4 = 0;
+ for (i = 0; i <= L; i++) {
+ if (y[i + I] == 0)
+ return 1; /* Prevent division by 0. */
+
+ xnonlin = x[i + I] - ((y[i + I] * SCALE) + G) / G;
+ xtilde[i] = ((xnonlin << M) + y[i + I]) / y[i + I];
+ xtilde[i] = ((xtilde[i] << M) + y[i + I]) / y[i + I];
+ xtilde[i] = ((xtilde[i] << M) + y[i + I]) / y[i + I];
+
+ y2 = (y[i + I] * y[i + I] + SCALE * SCALE) / (SCALE * SCALE);
+
+ sumy2 += y2;
+ sumy4 += y2 * y2;
+
+ b1[i] = y2 * (L + 1);
+ b2[i] = y2;
+ }
+ for (i = 0; i <= L; i++) {
+ b1[i] -= sumy2;
+ b2[i] = sumy4 - sumy2 * b2[i];
+ }
+
+ maxxtildeabs = maxb1abs = maxb2abs = 0;
+ for (i = 0; i <= L; i++) {
+ tmp = abs(xtilde[i]);
+ if (tmp > maxxtildeabs)
+ maxxtildeabs = tmp;
+
+ tmp = abs(b1[i]);
+ if (tmp > maxb1abs)
+ maxb1abs = tmp;
+
+ tmp = abs(b2[i]);
+ if (tmp > maxb2abs)
+ maxb2abs = tmp;
+ }
+ Qx = get_scale(maxxtildeabs);
+ Qb1 = get_scale(maxb1abs);
+ Qb2 = get_scale(maxb2abs);
+ for (i = 0; i <= L; i++) {
+ xtilde[i] /= 1 << Qx;
+ b1[i] /= 1 << Qb1;
+ b2[i] /= 1 << Qb2;
+ }
+
+ alpha = beta = 0;
+ for (i = 0; i <= L; i++) {
+ alpha += b1[i] * xtilde[i];
+ beta += b2[i] * xtilde[i];
+ }
+
+ scale = ((y4 / SCALE_LOG) * (L + 1) -
+ (y2 / SCALE_LOG) * sumy2) * SCALE_LOG;
+
+ Qscale = get_scale(abs(scale));
+ scale /= 1 << Qscale;
+ Qalpha = get_scale(abs(alpha));
+ alpha /= 1 << Qalpha;
+ Qbeta = get_scale(abs(beta));
+ beta /= 1 << Qbeta;
+
+ order = 3 * M - Qx - Qb1 - Qbeta + 10 + Qscale;
+ order5x = 1 << (order / 5);
+ order5xrem = 1 << (order % 5);
+
+ order = 3 * M - Qx - Qb2 - Qalpha + 10 + Qscale;
+ order3x = 1 << (order / 3);
+ order3xrem = 1 << (order % 3);
+
+ for (i = 0; i < AR9003_PAPRD_MEM_TAB_SIZE; i++) {
+ tmp = i * 32;
+
+ /* Fifth order. */
+ y5 = ((beta * tmp) / 64) / order5x;
+ y5 = (y5 * tmp) / order5x;
+ y5 = (y5 * tmp) / order5x;
+ y5 = (y5 * tmp) / order5x;
+ y5 = (y5 * tmp) / order5x;
+ y5 = y5 / order5xrem;
+
+ /* Third oder. */
+ y3 = (alpha * tmp) / order3x;
+ y3 = (y3 * tmp) / order3x;
+ y3 = (y3 * tmp) / order3x;
+ y3 = y3 / order3xrem;
+
+ in = y5 + y3 + (SCALE * tmp) / G;
+ if (i >= 2 && in < sc->sc_pa_in[chain][i - 1]) {
+ in = sc->sc_pa_in[chain][i - 1] +
+ (sc->sc_pa_in[chain][i - 1] -
+ sc->sc_pa_in[chain][i - 2]);
+ }
+ if (in > 1400)
+ in = 1400;
+ sc->sc_pa_in[chain][i] = in;
+ }
+
+ /* Compute average theta of first 5 bins (linear region). */
+ tavg = 0;
+ for (i = 1; i <= 5; i++)
+ tavg += t[i];
+ tavg /= 5;
+ for (i = 1; i <= 5; i++)
+ t[i] = 0;
+ for (i = 6; i <= maxidx; i++)
+ t[i] -= tavg;
+
+ alpha = beta = 0;
+ for (i = 0; i <= L; i++) {
+ ttilde = ((t[i + I] << M) + y[i + I]) / y[i + I];
+ ttilde = ((ttilde << M) + y[i + I]) / y[i + I];
+ ttilde = ((ttilde << M) + y[i + I]) / y[i + I];
+
+ alpha += b2[i] * ttilde;
+ beta += b1[i] * ttilde;
+ }
+
+ Qalpha = get_scale(abs(alpha));
+ alpha /= 1 << Qalpha;
+ Qbeta = get_scale(abs(beta));
+ beta /= 1 << Qbeta;
+
+ order = 3 * M - Qx - Qb1 - Qbeta + 10 + Qscale + 5;
+ order5x = 1 << (order / 5);
+ order5xrem = 1 << (order % 5);
+
+ order = 3 * M - Qx - Qb2 - Qalpha + 10 + Qscale + 5;
+ order3x = 1 << (order / 3);
+ order3xrem = 1 << (order % 3);
+
+ for (i = 0; i <= 4; i++)
+ sc->sc_angle[chain][i] = 0; /* Linear at that range. */
+ for (i = 5; i < AR9003_PAPRD_MEM_TAB_SIZE; i++) {
+ tmp = i * 32;
+
+ /* Fifth order. */
+ if (beta > 0)
+ y5 = (((beta * tmp - 64) / 64) - order5x) / order5x;
+ else
+ y5 = (((beta * tmp - 64) / 64) + order5x) / order5x;
+ y5 = (y5 * tmp) / order5x;
+ y5 = (y5 * tmp) / order5x;
+ y5 = (y5 * tmp) / order5x;
+ y5 = (y5 * tmp) / order5x;
+ y5 = y5 / order5xrem;
+
+ /* Third oder. */
+ if (beta > 0) /* XXX alpha? */
+ y3 = (alpha * tmp - order3x) / order3x;
+ else
+ y3 = (alpha * tmp + order3x) / order3x;
+ y3 = (y3 * tmp) / order3x;
+ y3 = (y3 * tmp) / order3x;
+ y3 = y3 / order3xrem;
+
+ angle = y5 + y3;
+ if (angle < -150)
+ angle = -150;
+ else if (angle > 150)
+ angle = 150;
+ sc->sc_angle[chain][i] = angle;
+ }
+ /* Angle for entry 4 is derived from angle for entry 5. */
+ sc->sc_angle[chain][4] = (sc->sc_angle[chain][5] + 2) / 2;
+
+ return 0;
+#undef SCALE
+#undef SCALE_LOG
+#undef NBINS
+}
+
+Static void
+ar9003_enable_predistorter(struct athn_softc *sc, int chain)
+{
+ uint32_t reg;
+ int i;
+
+ /* Write digital predistorter lookup table. */
+ for (i = 0; i < AR9003_PAPRD_MEM_TAB_SIZE; i++) {
+ AR_WRITE(sc, AR_PHY_PAPRD_MEM_TAB_B(chain, i),
+ SM(AR_PHY_PAPRD_PA_IN, sc->sc_pa_in[chain][i]) |
+ SM(AR_PHY_PAPRD_ANGLE, sc->sc_angle[chain][i]));
+ }
+
+ reg = AR_READ(sc, AR_PHY_PA_GAIN123_B(chain));
+ reg = RW(reg, AR_PHY_PA_GAIN123_PA_GAIN1, sc->sc_gain1[chain]);
+ AR_WRITE(sc, AR_PHY_PA_GAIN123_B(chain), reg);
+
+ /* Indicate Tx power used for calibration (training signal). */
+ reg = AR_READ(sc, AR_PHY_PAPRD_CTRL1_B(chain));
+ reg = RW(reg, AR_PHY_PAPRD_CTRL1_POWER_AT_AM2AM_CAL, sc->sc_trainpow);
+ AR_WRITE(sc, AR_PHY_PAPRD_CTRL1_B(chain), reg);
+
+ /* Enable digital predistorter for this chain. */
+ AR_SETBITS(sc, AR_PHY_PAPRD_CTRL0_B(chain),
+ AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE);
+ AR_WRITE_BARRIER(sc);
+}
+
+Static void
+ar9003_paprd_enable(struct athn_softc *sc)
+{
+ int i;
+
+ /* Enable digital predistorters for all Tx chains. */
+ for (i = 0; i < AR9003_MAX_CHAINS; i++)
+ if (sc->sc_txchainmask & (1 << i))
+ ar9003_enable_predistorter(sc, i);
+}
+
+/*
+ * This function is called when our training signal has been sent.
+ */
+Static void
+ar9003_paprd_tx_tone_done(struct athn_softc *sc)
+{
+ uint32_t lo[48], hi[48];
+ size_t i;
+
+ /* Make sure training is complete. */
+ if (!(AR_READ(sc, AR_PHY_PAPRD_TRAINER_STAT1) &
+ AR_PHY_PAPRD_TRAINER_STAT1_TRAIN_DONE))
+ return;
+
+ /* Read feedback from training signal. */
+ AR_CLRBITS(sc, AR_PHY_CHAN_INFO_MEMORY, AR_PHY_CHAN_INFO_TAB_S2_READ);
+ for (i = 0; i < __arraycount(lo); i++)
+ lo[i] = AR_READ(sc, AR_PHY_CHAN_INFO_TAB(0, i));
+ AR_SETBITS(sc, AR_PHY_CHAN_INFO_MEMORY, AR_PHY_CHAN_INFO_TAB_S2_READ);
+ for (i = 0; i < __arraycount(hi); i++)
+ hi[i] = AR_READ(sc, AR_PHY_CHAN_INFO_TAB(0, i));
+
+ AR_CLRBITS(sc, AR_PHY_PAPRD_TRAINER_STAT1,
+ AR_PHY_PAPRD_TRAINER_STAT1_TRAIN_DONE);
+
+ /* Compute predistortion function based on this feedback. */
+ if (ar9003_compute_predistortion(sc, lo, hi) != 0)
+ return;
+
+ /* Get next available Tx chain. */
+ while (++sc->sc_paprd_curchain < AR9003_MAX_CHAINS)
+ if (sc->sc_txchainmask & (1 << sc->sc_paprd_curchain))
+ break;
+ if (sc->sc_paprd_curchain == AR9003_MAX_CHAINS) {
+ /* All Tx chains measured; enable digital predistortion. */
+ ar9003_paprd_enable(sc);
+ }
+ else /* Measure next Tx chain. */
+ ar9003_paprd_tx_tone(sc);
+}
+
+PUBLIC void
+ar9003_write_txpower(struct athn_softc *sc, int16_t power[ATHN_POWER_COUNT])
+{
+
+ /* Make sure forced gain is disabled. */
+ AR_WRITE(sc, AR_PHY_TX_FORCED_GAIN, 0);
+
+ AR_WRITE(sc, AR_PHY_PWRTX_RATE1,
+ (power[ATHN_POWER_OFDM18 ] & 0x3f) << 24 |
+ (power[ATHN_POWER_OFDM12 ] & 0x3f) << 16 |
+ (power[ATHN_POWER_OFDM9 ] & 0x3f) << 8 |
+ (power[ATHN_POWER_OFDM6 ] & 0x3f));
+ AR_WRITE(sc, AR_PHY_PWRTX_RATE2,
+ (power[ATHN_POWER_OFDM54 ] & 0x3f) << 24 |
+ (power[ATHN_POWER_OFDM48 ] & 0x3f) << 16 |
+ (power[ATHN_POWER_OFDM36 ] & 0x3f) << 8 |
+ (power[ATHN_POWER_OFDM24 ] & 0x3f));
+ AR_WRITE(sc, AR_PHY_PWRTX_RATE3,
+ (power[ATHN_POWER_CCK2_SP ] & 0x3f) << 24 |
+ (power[ATHN_POWER_CCK2_LP ] & 0x3f) << 16 |
+ /* NB: No eXtended Range for AR9003. */
+ (power[ATHN_POWER_CCK1_LP ] & 0x3f));
+ AR_WRITE(sc, AR_PHY_PWRTX_RATE4,
+ (power[ATHN_POWER_CCK11_SP] & 0x3f) << 24 |
+ (power[ATHN_POWER_CCK11_LP] & 0x3f) << 16 |
+ (power[ATHN_POWER_CCK55_SP] & 0x3f) << 8 |
+ (power[ATHN_POWER_CCK55_LP] & 0x3f));
+ /*
+ * NB: AR_PHY_PWRTX_RATE5 needs to be written even if HT is disabled
+ * because it is read by PA predistortion functions.
+ */
+ AR_WRITE(sc, AR_PHY_PWRTX_RATE5,
+ (power[ATHN_POWER_HT20( 5)] & 0x3f) << 24 |
+ (power[ATHN_POWER_HT20( 4)] & 0x3f) << 16 |
+ (power[ATHN_POWER_HT20( 1)] & 0x3f) << 8 |
+ (power[ATHN_POWER_HT20( 0)] & 0x3f));
+#ifndef IEEE80211_NO_HT
+ AR_WRITE(sc, AR_PHY_PWRTX_RATE6,
+ (power[ATHN_POWER_HT20(13)] & 0x3f) << 24 |
+ (power[ATHN_POWER_HT20(12)] & 0x3f) << 16 |
+ (power[ATHN_POWER_HT20( 7)] & 0x3f) << 8 |
+ (power[ATHN_POWER_HT20( 6)] & 0x3f));
+ AR_WRITE(sc, AR_PHY_PWRTX_RATE7,
+ (power[ATHN_POWER_HT40( 5)] & 0x3f) << 24 |
+ (power[ATHN_POWER_HT40( 4)] & 0x3f) << 16 |
+ (power[ATHN_POWER_HT40( 1)] & 0x3f) << 8 |
+ (power[ATHN_POWER_HT40( 0)] & 0x3f));
+ AR_WRITE(sc, AR_PHY_PWRTX_RATE8,
+ (power[ATHN_POWER_HT40(13)] & 0x3f) << 24 |
+ (power[ATHN_POWER_HT40(12)] & 0x3f) << 16 |
+ (power[ATHN_POWER_HT40( 7)] & 0x3f) << 8 |
+ (power[ATHN_POWER_HT40( 6)] & 0x3f));
+ AR_WRITE(sc, AR_PHY_PWRTX_RATE10,
+ (power[ATHN_POWER_HT20(21)] & 0x3f) << 24 |
+ (power[ATHN_POWER_HT20(20)] & 0x3f) << 16 |
+ (power[ATHN_POWER_HT20(15)] & 0x3f) << 8 |
+ (power[ATHN_POWER_HT20(14)] & 0x3f));
+ AR_WRITE(sc, AR_PHY_PWRTX_RATE11,
+ (power[ATHN_POWER_HT40(23)] & 0x3f) << 24 |
+ (power[ATHN_POWER_HT40(22)] & 0x3f) << 16 |
+ (power[ATHN_POWER_HT20(23)] & 0x3f) << 8 |
+ (power[ATHN_POWER_HT20(22)] & 0x3f));
+ AR_WRITE(sc, AR_PHY_PWRTX_RATE12,
+ (power[ATHN_POWER_HT40(21)] & 0x3f) << 24 |
+ (power[ATHN_POWER_HT40(20)] & 0x3f) << 16 |
+ (power[ATHN_POWER_HT40(15)] & 0x3f) << 8 |
+ (power[ATHN_POWER_HT40(14)] & 0x3f));
+#endif
+ AR_WRITE_BARRIER(sc);
+}
+
+Static void
+ar9003_reset_rx_gain(struct athn_softc *sc, struct ieee80211_channel *c)
+{
+#define X(x) ((uint32_t)(x) << 2)
+ const struct athn_gain *prog = sc->sc_rx_gain;
+ const uint32_t *pvals;
+ int i;
+
+ if (IEEE80211_IS_CHAN_2GHZ(c))
+ pvals = prog->vals_2g;
+ else
+ pvals = prog->vals_5g;
+ for (i = 0; i < prog->nregs; i++)
+ AR_WRITE(sc, X(prog->regs[i]), pvals[i]);
+ AR_WRITE_BARRIER(sc);
+#undef X
+}
+
+Static void
+ar9003_reset_tx_gain(struct athn_softc *sc, struct ieee80211_channel *c)
+{
+#define X(x) ((uint32_t)(x) << 2)
+ const struct athn_gain *prog = sc->sc_tx_gain;
+ const uint32_t *pvals;
+ int i;
+
+ if (IEEE80211_IS_CHAN_2GHZ(c))
+ pvals = prog->vals_2g;
+ else
+ pvals = prog->vals_5g;
+ for (i = 0; i < prog->nregs; i++)
+ AR_WRITE(sc, X(prog->regs[i]), pvals[i]);
+ AR_WRITE_BARRIER(sc);
+#undef X
+}
+
+Static void
+ar9003_hw_init(struct athn_softc *sc, struct ieee80211_channel *c,
+ struct ieee80211_channel *extc)
+{
+#define X(x) ((uint32_t)(x) << 2)
+ struct athn_ops *ops = &sc->sc_ops;
+ const struct athn_ini *ini = sc->sc_ini;
+ const uint32_t *pvals;
+ uint32_t reg;
+ int i;
+
+ /*
+ * The common init values include the pre and core phases for the
+ * SoC, MAC, BB and Radio subsystems.
+ */
+ DPRINTFN(DBG_INIT, sc, "writing pre and core init vals\n");
+ for (i = 0; i < ini->ncmregs; i++) {
+ AR_WRITE(sc, X(ini->cmregs[i]), ini->cmvals[i]);
+ if (AR_IS_ANALOG_REG(X(ini->cmregs[i])))
+ DELAY(100);
+ if ((i & 0x1f) == 0)
+ DELAY(1);
+ }
+
+ /*
+ * The modal init values include the post phase for the SoC, MAC,
+ * BB and Radio subsystems.
+ */
+#ifndef IEEE80211_NO_HT
+ if (extc != NULL) {
+ if (IEEE80211_IS_CHAN_2GHZ(c))
+ pvals = ini->vals_2g40;
+ else
+ pvals = ini->vals_5g40;
+ }
+ else
+#endif
+ {
+ if (IEEE80211_IS_CHAN_2GHZ(c))
+ pvals = ini->vals_2g20;
+ else
+ pvals = ini->vals_5g20;
+ }
+ DPRINTFN(DBG_INIT, sc, "writing post init vals\n");
+ for (i = 0; i < ini->nregs; i++) {
+ AR_WRITE(sc, X(ini->regs[i]), pvals[i]);
+ if (AR_IS_ANALOG_REG(X(ini->regs[i])))
+ DELAY(100);
+ if ((i & 0x1f) == 0)
+ DELAY(1);
+ }
+
+ if (sc->sc_rx_gain != NULL)
+ ar9003_reset_rx_gain(sc, c);
+ if (sc->sc_tx_gain != NULL)
+ ar9003_reset_tx_gain(sc, c);
+
+ if (IEEE80211_IS_CHAN_5GHZ(c) &&
+ (sc->sc_flags & ATHN_FLAG_FAST_PLL_CLOCK)) {
+ /* Update modal values for fast PLL clock. */
+#ifndef IEEE80211_NO_HT
+ if (extc != NULL)
+ pvals = ini->fastvals_5g40;
+ else
+#endif
+ pvals = ini->fastvals_5g20;
+ DPRINTFN(DBG_INIT, sc, "writing fast pll clock init vals\n");
+ for (i = 0; i < ini->nfastregs; i++) {
+ AR_WRITE(sc, X(ini->fastregs[i]), pvals[i]);
+ if (AR_IS_ANALOG_REG(X(ini->fastregs[i])))
+ DELAY(100);
+ if ((i & 0x1f) == 0)
+ DELAY(1);
+ }
+ }
+
+ /*
+ * Set the RX_ABORT and RX_DIS bits to prevent frames with corrupted
+ * descriptor status.
+ */
+ AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT);
+
+ reg = AR_READ(sc, AR_PCU_MISC_MODE2);
+ reg &= ~AR_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE;
+ reg |= AR_PCU_MISC_MODE2_AGG_WEP_ENABLE_FIX;
+ reg |= AR_PCU_MISC_MODE2_ENABLE_AGGWEP;
+ AR_WRITE(sc, AR_PCU_MISC_MODE2, reg);
+ AR_WRITE_BARRIER(sc);
+
+ ar9003_set_phy(sc, c, extc);
+ ar9003_init_chains(sc);
+
+ ops->set_txpower(sc, c, extc);
+#undef X
+}
+
+PUBLIC void
+ar9003_get_lg_tpow(struct athn_softc *sc, struct ieee80211_channel *c,
+ uint8_t ctl, const uint8_t *fbins,
+ const struct ar_cal_target_power_leg *tgt, int nchans, uint8_t tpow[4])
+{
+ uint8_t fbin;
+ int i, delta, lo, hi;
+
+ lo = hi = -1;
+ fbin = athn_chan2fbin(c);
+ for (i = 0; i < nchans; i++) {
+ delta = fbin - fbins[i];
+ /* Find the largest sample that is <= our frequency. */
+ if (delta >= 0 && (lo == -1 || delta < fbin - fbins[lo]))
+ lo = i;
+ /* Find the smallest sample that is >= our frequency. */
+ if (delta <= 0 && (hi == -1 || delta > fbin - fbins[hi]))
+ hi = i;
+ }
+ if (lo == -1)
+ lo = hi;
+ else if (hi == -1)
+ hi = lo;
+ /* Interpolate values. */
+ for (i = 0; i < 4; i++) {
+ tpow[i] = athn_interpolate(fbin,
+ fbins[lo], tgt[lo].tPow2x[i],
+ fbins[hi], tgt[hi].tPow2x[i]);
+ }
+ /* XXX Apply conformance test limit. */
+}
+
+PUBLIC void
+ar9003_get_ht_tpow(struct athn_softc *sc, struct ieee80211_channel *c,
+ uint8_t ctl, const uint8_t *fbins,
+ const struct ar_cal_target_power_ht *tgt, int nchans, uint8_t tpow[14])
+{
+ uint8_t fbin;
+ int i, delta, lo, hi;
+
+ lo = hi = -1;
+ fbin = athn_chan2fbin(c);
+ for (i = 0; i < nchans; i++) {
+ delta = fbin - fbins[i];
+ /* Find the largest sample that is <= our frequency. */
+ if (delta >= 0 && (lo == -1 || delta < fbin - fbins[lo]))
+ lo = i;
+ /* Find the smallest sample that is >= our frequency. */
+ if (delta <= 0 && (hi == -1 || delta > fbin - fbins[hi]))
+ hi = i;
+ }
+ if (lo == -1)
+ lo = hi;
+ else if (hi == -1)
+ hi = lo;
+ /* Interpolate values. */
+ for (i = 0; i < 14; i++) {
+ tpow[i] = athn_interpolate(fbin,
+ fbins[lo], tgt[lo].tPow2x[i],
+ fbins[hi], tgt[hi].tPow2x[i]);
+ }
+ /* XXX Apply conformance test limit. */
+}
+
+/*
+ * Adaptive noise immunity.
+ */
+Static void
+ar9003_set_noise_immunity_level(struct athn_softc *sc, int level)
+{
+ int high = level == 4;
+ uint32_t reg;
+
+ reg = AR_READ(sc, AR_PHY_DESIRED_SZ);
+ reg = RW(reg, AR_PHY_DESIRED_SZ_TOT_DES, high ? -62 : -55);
+ AR_WRITE(sc, AR_PHY_DESIRED_SZ, reg);
+
+ reg = AR_READ(sc, AR_PHY_AGC);
+ reg = RW(reg, AR_PHY_AGC_COARSE_LOW, high ? -70 : -64);
+ reg = RW(reg, AR_PHY_AGC_COARSE_HIGH, high ? -12 : -14);
+ AR_WRITE(sc, AR_PHY_AGC, reg);
+
+ reg = AR_READ(sc, AR_PHY_FIND_SIG);
+ reg = RW(reg, AR_PHY_FIND_SIG_FIRPWR, high ? -80 : -78);
+ AR_WRITE(sc, AR_PHY_FIND_SIG, reg);
+ AR_WRITE_BARRIER(sc);
+}
+
+Static void
+ar9003_enable_ofdm_weak_signal(struct athn_softc *sc)
+{
+ uint32_t reg;
+
+ reg = AR_READ(sc, AR_PHY_SFCORR_LOW);
+ reg = RW(reg, AR_PHY_SFCORR_LOW_M1_THRESH_LOW, 50);
+ reg = RW(reg, AR_PHY_SFCORR_LOW_M2_THRESH_LOW, 40);
+ reg = RW(reg, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, 48);
+ AR_WRITE(sc, AR_PHY_SFCORR_LOW, reg);
+
+ reg = AR_READ(sc, AR_PHY_SFCORR);
+ reg = RW(reg, AR_PHY_SFCORR_M1_THRESH, 77);
+ reg = RW(reg, AR_PHY_SFCORR_M2_THRESH, 64);
+ reg = RW(reg, AR_PHY_SFCORR_M2COUNT_THR, 16);
+ AR_WRITE(sc, AR_PHY_SFCORR, reg);
+
+ reg = AR_READ(sc, AR_PHY_SFCORR_EXT);
+ reg = RW(reg, AR_PHY_SFCORR_EXT_M1_THRESH_LOW, 50);
+ reg = RW(reg, AR_PHY_SFCORR_EXT_M2_THRESH_LOW, 40);
+ reg = RW(reg, AR_PHY_SFCORR_EXT_M1_THRESH, 77);
+ reg = RW(reg, AR_PHY_SFCORR_EXT_M2_THRESH, 64);
+ AR_WRITE(sc, AR_PHY_SFCORR_EXT, reg);
+
+ AR_SETBITS(sc, AR_PHY_SFCORR_LOW,
+ AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
+ AR_WRITE_BARRIER(sc);
+}
+
+Static void
+ar9003_disable_ofdm_weak_signal(struct athn_softc *sc)
+{
+ uint32_t reg;
+
+ reg = AR_READ(sc, AR_PHY_SFCORR_LOW);
+ reg = RW(reg, AR_PHY_SFCORR_LOW_M1_THRESH_LOW, 127);
+ reg = RW(reg, AR_PHY_SFCORR_LOW_M2_THRESH_LOW, 127);
+ reg = RW(reg, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, 63);
+ AR_WRITE(sc, AR_PHY_SFCORR_LOW, reg);
+
+ reg = AR_READ(sc, AR_PHY_SFCORR);
+ reg = RW(reg, AR_PHY_SFCORR_M1_THRESH, 127);
+ reg = RW(reg, AR_PHY_SFCORR_M2_THRESH, 127);
+ reg = RW(reg, AR_PHY_SFCORR_M2COUNT_THR, 31);
+ AR_WRITE(sc, AR_PHY_SFCORR, reg);
+
+ reg = AR_READ(sc, AR_PHY_SFCORR_EXT);
+ reg = RW(reg, AR_PHY_SFCORR_EXT_M1_THRESH_LOW, 127);
+ reg = RW(reg, AR_PHY_SFCORR_EXT_M2_THRESH_LOW, 127);
+ reg = RW(reg, AR_PHY_SFCORR_EXT_M1_THRESH, 127);
+ reg = RW(reg, AR_PHY_SFCORR_EXT_M2_THRESH, 127);
+ AR_WRITE(sc, AR_PHY_SFCORR_EXT, reg);
+
+ AR_CLRBITS(sc, AR_PHY_SFCORR_LOW,
+ AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
+ AR_WRITE_BARRIER(sc);
+}
+
+Static void
+ar9003_set_cck_weak_signal(struct athn_softc *sc, int high)
+{
+ uint32_t reg;
+
+ reg = AR_READ(sc, AR_PHY_CCK_DETECT);
+ reg = RW(reg, AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK, high ? 6 : 8);
+ AR_WRITE(sc, AR_PHY_CCK_DETECT, reg);
+ AR_WRITE_BARRIER(sc);
+}
+
+Static void
+ar9003_set_firstep_level(struct athn_softc *sc, int level)
+{
+ uint32_t reg;
+
+ reg = AR_READ(sc, AR_PHY_FIND_SIG);
+ reg = RW(reg, AR_PHY_FIND_SIG_FIRSTEP, level * 4);
+ AR_WRITE(sc, AR_PHY_FIND_SIG, reg);
+ AR_WRITE_BARRIER(sc);
+}
+
+Static void
+ar9003_set_spur_immunity_level(struct athn_softc *sc, int level)
+{
+ uint32_t reg;
+
+ reg = AR_READ(sc, AR_PHY_TIMING5);
+ reg = RW(reg, AR_PHY_TIMING5_CYCPWR_THR1, (level + 1) * 2);
+ AR_WRITE(sc, AR_PHY_TIMING5, reg);
+ AR_WRITE_BARRIER(sc);
+}
diff --git a/sys/dev/ic/arn9003.h b/sys/dev/ic/arn9003.h
new file mode 100644
index 00000000000..f9e15bda1e6
--- /dev/null
+++ b/sys/dev/ic/arn9003.h
@@ -0,0 +1,42 @@
+/* $NetBSD: arn9003.h,v 1.1 2013/03/30 02:53:01 christos Exp $ */
+/*
+ * Copyright (c) 2001, 2004 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _IF_ARN9003_H_
+#define _IF_ARN9003_H_
+
+int ar9003_attach(struct athn_softc *);
+int ar9003_init_calib(struct athn_softc *);
+void ar9003_reset_txsring(struct athn_softc *);
+void ar9003_get_lg_tpow(struct athn_softc *, struct ieee80211_channel *,
+ uint8_t, const uint8_t *, const struct ar_cal_target_power_leg *,
+ int, uint8_t[]);
+void ar9003_get_ht_tpow(struct athn_softc *, struct ieee80211_channel *,
+ uint8_t, const uint8_t *, const struct ar_cal_target_power_ht *,
+ int, uint8_t[]);
+void ar9003_write_txpower(struct athn_softc *, int16_t power[]);
+
+#endif /* _IF_ARN9003_H_ */
diff --git a/sys/dev/ic/arn9003reg.h b/sys/dev/ic/arn9003reg.h
new file mode 100644
index 00000000000..b2aff4856c3
--- /dev/null
+++ b/sys/dev/ic/arn9003reg.h
@@ -0,0 +1,1205 @@
+/* $NetBSD: arn9003reg.h,v 1.1 2013/03/30 02:53:01 christos Exp $ */
+/* $OpenBSD: ar9003reg.h,v 1.8 2012/10/20 09:53:32 stsp Exp $ */
+
+/*-
+ * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr>
+ * Copyright (c) 2010 Atheros Communications Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _ARN9003REG_H_
+#define _ARN9003REG_H_
+
+/*
+ * MAC registers.
+ */
+#define AR_ISR_S2_S 0x00d0
+#define AR_ISR_S3_S 0x00d4
+#define AR_ISR_S4_S 0x00d8
+#define AR_ISR_S5_S 0x00dc
+#define AR_GPIO_IN_OUT 0x4048
+#define AR_GPIO_IN 0x404c
+#define AR9300_GPIO_IN_VAL 0x0001FFFF
+#define AR_GPIO_OE_OUT 0x4050
+#define AR_GPIO_INTR_POL 0x4058
+#define AR_GPIO_INPUT_EN_VAL 0x405c
+#define AR_GPIO_INPUT_MUX1 0x4060
+#define AR_GPIO_INPUT_MUX2 0x4064
+#define AR_GPIO_OUTPUT_MUX(i) (0x4068 + (i) * 4)
+#define AR_INPUT_STATE 0x4074
+#define AR_EEPROM_STATUS_DATA 0x4084
+#define AR_OBS 0x4088
+#define AR_GPIO_PDPU 0x4090
+#define AR_PCIE_MSI 0x40a4
+#define AR_ENT_OTP 0x40d8
+
+/* Bits for AR_ENT_OTP. */
+#define AR_ENT_OTP_CHAIN2_DISABLE 0x00020000
+#define AR_ENT_OTP_MPSD 0x00800000
+
+/*
+ * PHY registers.
+ */
+#define AR_PHY_TIMING1 0x09800
+#define AR_PHY_TIMING2 0x09804
+#define AR_PHY_TIMING3 0x09808
+#define AR_PHY_TIMING4 0x0980c
+#define AR_PHY_TIMING5 0x09810
+#define AR_PHY_TIMING6 0x09814
+#define AR_PHY_TIMING11 0x09818
+#define AR_PHY_SPUR_REG 0x0981c
+#define AR_PHY_FIND_SIG_LOW 0x09820
+#define AR_PHY_SFCORR 0x09824
+#define AR_PHY_SFCORR_LOW 0x09828
+#define AR_PHY_SFCORR_EXT 0x0982c
+#define AR_PHY_EXT_CCA(i) (0x09830 + (i) * 0x1000)
+#define AR_PHY_RADAR_0 0x09834
+#define AR_PHY_RADAR_1 0x09838
+#define AR_PHY_RADAR_EXT 0x0983c
+#define AR_PHY_MULTICHAIN_CTRL 0x09880
+#define AR_PHY_PERCHAIN_CSD 0x09884
+#define AR_PHY_TX_CRC 0x098a0
+#define AR_PHY_TST_DAC_CONST 0x098a4
+#define AR_PHY_SPUR_REPORT_0 0x098a8
+#define AR_PHY_TX_IQCAL_CONTROL_3 0x098b0
+#define AR_PHY_IQ_ADC_MEAS_0_B(i) (0x098c0 + (i) * 0x1000)
+#define AR_PHY_IQ_ADC_MEAS_1_B(i) (0x098c4 + (i) * 0x1000)
+#define AR_PHY_IQ_ADC_MEAS_2_B(i) (0x098c8 + (i) * 0x1000)
+#define AR_PHY_IQ_ADC_MEAS_3_B(i) (0x098cc + (i) * 0x1000)
+#define AR_PHY_TX_PHASE_RAMP_0 0x098d0
+#define AR_PHY_ADC_DC_GAIN_CORR(i) (0x098d4 + (i) * 0x1000)
+#define AR_PHY_RX_IQCAL_CORR_B(i) (0x098dc + (i) * 0x1000)
+#define AR_PHY_PAPRD_AM2AM 0x098e4
+#define AR_PHY_PAPRD_AM2PM 0x098e8
+#define AR_PHY_PAPRD_HT40 0x098ec
+#define AR_PHY_PAPRD_CTRL0_B(i) (0x098f0 + (i) * 0x1000)
+#define AR_PHY_PAPRD_CTRL1_B(i) (0x098f4 + (i) * 0x1000)
+#define AR_PHY_PA_GAIN123_B(i) (0x098f8 + (i) * 0x1000)
+#define AR_PHY_PAPRD_PRE_POST_SCALE_B0(i) \
+ (0x09900 + (i) * 4)
+#define AR_PHY_PAPRD_MEM_TAB_B(i, j) (0x09920 + (i) * 0x1000 + (j) * 4)
+#define AR_PHY_CHAN_INFO_TAB(i, j) (0x09b00 + (i) * 0x1000 + (j) * 4)
+#define AR_PHY_TIMING_3A 0x09c00
+#define AR_PHY_LDPC_CNTL1 0x09c04
+#define AR_PHY_LDPC_CNTL2 0x09c08
+#define AR_PHY_PILOT_SPUR_MASK 0x09c0c
+#define AR_PHY_CHAN_SPUR_MASK 0x09c10
+#define AR_PHY_SGI_DELTA 0x09c14
+#define AR_PHY_ML_CNTL_1 0x09c18
+#define AR_PHY_ML_CNTL_2 0x09c1c
+#define AR_PHY_TST_ADC 0x09c20
+#define AR_PHY_SETTLING 0x09e00
+#define AR_PHY_RXGAIN(i) (0x09e04 + (i) * 0x1000)
+#define AR_PHY_GAINS_MINOFF0 0x09e08
+#define AR_PHY_DESIRED_SZ 0x09e0c
+#define AR_PHY_FIND_SIG 0x09e10
+#define AR_PHY_AGC 0x09e14
+#define AR_PHY_EXT_ATTEN_CTL(i) (0x09e18 + (i) * 0x1000)
+#define AR_PHY_CCA(i) (0x09e1c + (i) * 0x1000)
+#define AR_PHY_CCA_CTRL(i) (0x09e20 + (i) * 0x1000)
+#define AR_PHY_RESTART 0x09e24
+#define AR_PHY_MC_GAIN_CTRL 0x09e28
+#define AR_PHY_EXTCHN_PWRTHR1 0x09e2c
+#define AR_PHY_EXT_CHN_WIN 0x09e30
+#define AR_PHY_20_40_DET_THR 0x09e34
+#define AR_PHY_RIFS_SRCH 0x09e38
+#define AR_PHY_PEAK_DET_CTRL_1 0x09e3c
+#define AR_PHY_PEAK_DET_CTRL_2 0x09e40
+#define AR_PHY_RX_GAIN_BOUNDS_1 0x09e44
+#define AR_PHY_RX_GAIN_BOUNDS_2 0x09e48
+#define AR_PHY_RSSI(i) (0x09f80 + (i) * 0x1000)
+#define AR_PHY_SPUR_CCK_REP0 0x09f84
+#define AR_PHY_CCK_DETECT 0x09fc0
+#define AR_PHY_DAG_CTRLCCK 0x09fc4
+#define AR_PHY_IQCORR_CTRL_CCK 0x09fc8
+#define AR_PHY_CCK_SPUR_MIT 0x09fcc
+#define AR_PHY_RX_OCGAIN 0x0a000
+#define AR_PHY_D2_CHIP_ID 0x0a200
+#define AR_PHY_GEN_CTRL 0x0a204
+#define AR_PHY_MODE 0x0a208
+#define AR_PHY_ACTIVE 0x0a20c
+#define AR_PHY_SPUR_MASK_A 0x0a220
+#define AR_PHY_SPUR_MASK_B 0x0a224
+#define AR_PHY_SPECTRAL_SCAN 0x0a228
+#define AR_PHY_RADAR_BW_FILTER 0x0a22c
+#define AR_PHY_SEARCH_START_DELAY 0x0a230
+#define AR_PHY_MAX_RX_LEN 0x0a234
+#define AR_PHY_FRAME_CTL 0x0a238
+#define AR_PHY_RFBUS_REQ 0x0a23c
+#define AR_PHY_RFBUS_GRANT 0x0a240
+#define AR_PHY_RIFS 0x0a244
+#define AR_PHY_RX_CLR_DELAY 0x0a250
+#define AR_PHY_RX_DELAY 0x0a254
+#define AR_PHY_XPA_TIMING_CTL 0x0a264
+#define AR_PHY_MISC_PA_CTL 0x0a280
+#define AR_PHY_SWITCH_CHAIN(i) (0x0a284 + (i) * 0x1000)
+#define AR_PHY_SWITCH_COM 0x0a288
+#define AR_PHY_SWITCH_COM_2 0x0a28c
+#define AR_PHY_RX_CHAINMASK 0x0a2a0
+#define AR_PHY_CAL_CHAINMASK 0x0a2c0
+#define AR_PHY_AGC_CONTROL 0x0a2c4
+#define AR_PHY_CALMODE 0x0a2c8
+#define AR_PHY_FCAL_1 0x0a2cc
+#define AR_PHY_FCAL_2_0 0x0a2d0
+#define AR_PHY_DFT_TONE_CTL_0 0x0a2d4
+#define AR_PHY_CL_CAL_CTL 0x0a2d8
+#define AR_PHY_CL_TAB_0 0x0a300
+#define AR_PHY_SYNTH_CONTROL 0x0a340
+#define AR_PHY_ADDAC_CLK_SEL 0x0a344
+#define AR_PHY_PLL_CTL 0x0a348
+#define AR_PHY_ANALOG_SWAP 0x0a34c
+#define AR_PHY_ADDAC_PARA_CTL 0x0a350
+#define AR_PHY_XPA_CFG 0x0a358
+#define AR_PHY_TEST 0x0a360
+#define AR_PHY_TEST_CTL_STATUS 0x0a364
+#define AR_PHY_TSTDAC 0x0a368
+#define AR_PHY_CHAN_STATUS 0x0a36c
+#define AR_PHY_CHAN_INFO_MEMORY 0x0a370
+#define AR_PHY_CHNINFO_NOISEPWR 0x0a374
+#define AR_PHY_CHNINFO_GAINDIFF 0x0a378
+#define AR_PHY_CHNINFO_FINETIM 0x0a37c
+#define AR_PHY_CHAN_INFO_GAIN_0 0x0a380
+#define AR_PHY_SCRAMBLER_SEED 0x0a390
+#define AR_PHY_CCK_TX_CTRL 0x0a394
+#define AR_PHY_HEAVYCLIP_CTL 0x0a3a4
+#define AR_PHY_HEAVYCLIP_20 0x0a3a8
+#define AR_PHY_HEAVYCLIP_40 0x0a3ac
+#define AR_PHY_ILLEGAL_TXRATE 0x0a3b0
+#define AR_PHY_PWRTX_RATE1 0x0a3c0
+#define AR_PHY_PWRTX_RATE2 0x0a3c4
+#define AR_PHY_PWRTX_RATE3 0x0a3c8
+#define AR_PHY_PWRTX_RATE4 0x0a3cc
+#define AR_PHY_PWRTX_RATE5 0x0a3d0
+#define AR_PHY_PWRTX_RATE6 0x0a3d4
+#define AR_PHY_PWRTX_RATE7 0x0a3d8
+#define AR_PHY_PWRTX_RATE8 0x0a3dc
+#define AR_PHY_PWRTX_RATE10 0x0a3e4
+#define AR_PHY_PWRTX_RATE11 0x0a3e8
+#define AR_PHY_PWRTX_RATE12 0x0a3ec
+#define AR_PHY_PWRTX_MAX 0x0a3f0
+#define AR_PHY_POWER_TX_SUB 0x0a3f4
+#define AR_PHY_TPC_1 0x0a3f8
+#define AR_PHY_TPC_4_B(i) (0x0a404 + (i) * 0x1000)
+#define AR_PHY_TPC_5_B(i) (0x0a408 + (i) * 0x1000)
+#define AR_PHY_TPC_6_B(i) (0x0a40c + (i) * 0x1000)
+#define AR_PHY_TPC_11_B(i) (0x0a420 + (i) * 0x1000)
+#define AR_PHY_TPC_12 0x0a424
+#define AR_PHY_TPC_18 0x0a43c
+#define AR_PHY_TPC_19 0x0a440
+#define AR_PHY_BB_THERM_ADC_1 0x0a448
+#define AR_PHY_BB_THERM_ADC_4 0x0a454
+#define AR_PHY_TX_FORCED_GAIN 0x0a458
+#define AR_PHY_PDADC_TAB(i) (0x0a480 + (i) * 0x1000)
+#define AR_PHY_TXGAIN_TABLE(i) (0x0a500 + (i) * 4)
+#define AR_PHY_TX_IQCAL_CONTROL_1 0x0a648
+#define AR_PHY_TX_IQCAL_START 0x0a640
+#define AR_PHY_TX_IQCAL_CORR_COEFF_01_B(i) \
+ (0x0a650 + (i) * 0x1000)
+#define AR_PHY_TX_IQCAL_STATUS_B(i) (0x0a68c + (i) * 0x1000)
+#define AR_PHY_PAPRD_TRAINER_CNTL1 0x0a690
+#define AR_PHY_PAPRD_TRAINER_CNTL2 0x0a694
+#define AR_PHY_PAPRD_TRAINER_CNTL3 0x0a698
+#define AR_PHY_PAPRD_TRAINER_CNTL4 0x0a69c
+#define AR_PHY_PAPRD_TRAINER_STAT1 0x0a6a0
+#define AR_PHY_PAPRD_TRAINER_STAT2 0x0a6a4
+#define AR_PHY_PAPRD_TRAINER_STAT3 0x0a6a8
+#define AR_PHY_PANIC_WD_STATUS 0x0a7c0
+#define AR_PHY_PANIC_WD_CTL_1 0x0a7c4
+#define AR_PHY_PANIC_WD_CTL_2 0x0a7c8
+#define AR_PHY_BT_CTL 0x0a7cc
+#define AR_PHY_ONLY_WARMRESET 0x0a7d0
+#define AR_PHY_ONLY_CTL 0x0a7d4
+#define AR_PHY_ECO_CTRL 0x0a7dc
+
+/*
+ * Analog registers.
+ */
+#define AR_IS_ANALOG_REG(reg) ((reg) >= 0x16000 && (reg) <= 0x17000)
+#define AR_PHY_65NM_CH0_SYNTH4 0x1608c
+#define AR_PHY_65NM_CH0_SYNTH7 0x16098
+#define AR_PHY_65NM_CH0_BIAS1 0x160c0
+#define AR_PHY_65NM_CH0_BIAS2 0x160c4
+#define AR_PHY_65NM_CH0_BIAS4 0x160cc
+#define AR_PHY_65NM_CH0_RXTX1 0x16100
+#define AR_PHY_65NM_CH0_RXTX2 0x16104
+#define AR_PHY_65NM_CH0_RXTX4 0x1610c
+#define AR9485_PHY_65NM_CH0_TOP2 0x16284
+#define AR_PHY_65NM_CH0_TOP 0x16288
+#define AR_PHY_65NM_CH0_THERM 0x16290
+#define AR9485_PHY_CH0_XTAL 0x16290
+#define AR_PHY_65NM_CH1_RXTX1 0x16500
+#define AR_PHY_65NM_CH1_RXTX2 0x16504
+#define AR_PHY_65NM_CH2_RXTX1 0x16900
+#define AR_PHY_65NM_CH2_RXTX2 0x16904
+#define AR_PHY_PMU1 0x16c40
+#define AR_PHY_PMU2 0x16c44
+
+
+/* Bits for AR_PHY_TIMING2. */
+#define AR_PHY_TIMING2_FORCE_PPM_VAL_M 0x00000fff
+#define AR_PHY_TIMING2_FORCE_PPM_VAL_S 0
+#define AR_PHY_TIMING2_USE_FORCE_PPM 0x00001000
+
+/* Bits for AR_PHY_TIMING3. */
+#define AR_PHY_TIMING3_DSC_EXP_M 0x0001e000
+#define AR_PHY_TIMING3_DSC_EXP_S 13
+#define AR_PHY_TIMING3_DSC_MAN_M 0xfffe0000
+#define AR_PHY_TIMING3_DSC_MAN_S 17
+
+/* Bits for AR_PHY_TIMING4. */
+#define AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX_M 0x0000f000
+#define AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX_S 12
+#define AR_PHY_TIMING4_DO_CAL 0x00010000
+#define AR_PHY_TIMING4_ENABLE_PILOT_MASK 0x10000000
+#define AR_PHY_TIMING4_ENABLE_CHAN_MASK 0x20000000
+#define AR_PHY_TIMING4_ENABLE_SPUR_FILTER 0x40000000
+#define AR_PHY_TIMING4_ENABLE_SPUR_RSSI 0x80000000
+
+/* Bits for AR_PHY_TIMING5. */
+#define AR_PHY_TIMING5_CYCPWR_THR1_ENABLE 0x00000001
+#define AR_PHY_TIMING5_CYCPWR_THR1_M 0x000000fe
+#define AR_PHY_TIMING5_CYCPWR_THR1_S 1
+#define AR_PHY_TIMING5_RSSI_THR1A_ENA 0x00008000
+#define AR_PHY_TIMING5_CYCPWR_THR1A_M 0x007f0000
+#define AR_PHY_TIMING5_CYCPWR_THR1A_S 16
+#define AR_PHY_TIMING5_RSSI_THR1A_M 0x007f0000
+#define AR_PHY_TIMING5_RSSI_THR1A_S 16
+
+/* Bits for AR_PHY_TIMING11. */
+#define AR_PHY_TIMING11_SPUR_DELTA_PHASE_M 0x000fffff
+#define AR_PHY_TIMING11_SPUR_DELTA_PHASE_S 0
+#define AR_PHY_TIMING11_SPUR_FREQ_SD_M 0x3ff00000
+#define AR_PHY_TIMING11_SPUR_FREQ_SD_S 20
+#define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC 0x40000000
+#define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR 0x80000000
+
+/* Bits for AR_PHY_SPUR_REG. */
+#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_M 0x000000ff
+#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_S 0
+#define AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI 0x00000100
+#define AR_PHY_SPUR_REG_ENABLE_MASK_PPM 0x00020000
+#define AR_PHY_SPUR_REG_MASK_RATE_CNTL_M 0x03fc0000
+#define AR_PHY_SPUR_REG_MASK_RATE_CNTL_S 18
+#define AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT 0x04000000
+
+/* Bits for AR_PHY_FIND_SIG_LOW. */
+#define AR_PHY_FIND_SIG_LOW_RELSTEP_M 0x0000001f
+#define AR_PHY_FIND_SIG_LOW_RELSTEP_S 0
+#define AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW_M 0x00000fc0
+#define AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW_S 6
+#define AR_PHY_FIND_SIG_LOW_FIRPWR_M 0x0007f000
+#define AR_PHY_FIND_SIG_LOW_FIRPWR_S 12
+
+/* Bits for AR_PHY_SFCORR. */
+#define AR_PHY_SFCORR_M2COUNT_THR_M 0x0000001f
+#define AR_PHY_SFCORR_M2COUNT_THR_S 0
+#define AR_PHY_SFCORR_M1_THRESH_M 0x00fe0000
+#define AR_PHY_SFCORR_M1_THRESH_S 17
+#define AR_PHY_SFCORR_M2_THRESH_M 0x7f000000
+#define AR_PHY_SFCORR_M2_THRESH_S 24
+
+/* Bits for AR_PHY_SFCORR_LOW. */
+#define AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW 0x00000001
+#define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW_M 0x00003f00
+#define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW_S 8
+#define AR_PHY_SFCORR_LOW_M1_THRESH_LOW_M 0x001fc000
+#define AR_PHY_SFCORR_LOW_M1_THRESH_LOW_S 14
+#define AR_PHY_SFCORR_LOW_M2_THRESH_LOW_M 0x0fe00000
+#define AR_PHY_SFCORR_LOW_M2_THRESH_LOW_S 21
+
+/* Bits for AR_PHY_SFCORR_EXT. */
+#define AR_PHY_SFCORR_EXT_M1_THRESH_M 0x0000007f
+#define AR_PHY_SFCORR_EXT_M1_THRESH_S 0
+#define AR_PHY_SFCORR_EXT_M2_THRESH_M 0x00003f80
+#define AR_PHY_SFCORR_EXT_M2_THRESH_S 7
+#define AR_PHY_SFCORR_EXT_M1_THRESH_LOW_M 0x001fc000
+#define AR_PHY_SFCORR_EXT_M1_THRESH_LOW_S 14
+#define AR_PHY_SFCORR_EXT_M2_THRESH_LOW_M 0x0fe00000
+#define AR_PHY_SFCORR_EXT_M2_THRESH_LOW_S 21
+#define AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD 0x10000000
+
+/* Bits for AR_PHY_RADAR_0. */
+#define AR_PHY_RADAR_0_ENA 0x00000001
+#define AR_PHY_RADAR_0_INBAND_M 0x0000003e
+#define AR_PHY_RADAR_0_INBAND_S 1
+#define AR_PHY_RADAR_0_PRSSI_M 0x00000fc0
+#define AR_PHY_RADAR_0_PRSSI_S 6
+#define AR_PHY_RADAR_0_HEIGHT_M 0x0003f000
+#define AR_PHY_RADAR_0_HEIGHT_S 12
+#define AR_PHY_RADAR_0_RRSSI_M 0x00fc0000
+#define AR_PHY_RADAR_0_RRSSI_S 18
+#define AR_PHY_RADAR_0_FIRPWR_M 0x7f000000
+#define AR_PHY_RADAR_0_FIRPWR_S 24
+#define AR_PHY_RADAR_0_FFT_ENA 0x80000000
+
+/* Bits for AR_PHY_RADAR_1. */
+#define AR_PHY_RADAR_1_MAXLEN_M 0x000000ff
+#define AR_PHY_RADAR_1_MAXLEN_S 0
+#define AR_PHY_RADAR_1_RELSTEP_THRESH_M 0x00001f00
+#define AR_PHY_RADAR_1_RELSTEP_THRESH_S 8
+#define AR_PHY_RADAR_1_RELSTEP_CHECK 0x00002000
+#define AR_PHY_RADAR_1_MAX_RRSSI 0x00004000
+#define AR_PHY_RADAR_1_BLOCK_CHECK 0x00008000
+#define AR_PHY_RADAR_1_RELPWR_THRESH_M 0x003f0000
+#define AR_PHY_RADAR_1_RELPWR_THRESH_S 16
+#define AR_PHY_RADAR_1_USE_FIR128 0x00400000
+#define AR_PHY_RADAR_1_RELPWR_ENA 0x00800000
+
+/* Bits for AR_PHY_RADAR_EXT. */
+#define AR_PHY_RADAR_EXT_ENA 0x00004000
+#define AR_PHY_RADAR_DC_PWR_THRESH_M 0x007f8000
+#define AR_PHY_RADAR_DC_PWR_THRESH_S 15
+#define AR_PHY_RADAR_LB_DC_CAP_M 0x7f800000
+#define AR_PHY_RADAR_LB_DC_CAP_S 23
+
+/* Bits for AR_PHY_TX_IQCAL_CONTROL_3. */
+#define AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN 0x80000000
+
+/* Bits for AR_PHY_RX_IQCAL_CORR_B(0). */
+#define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF_M 0x0000007f
+#define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF_S 0
+#define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF_M 0x00003f80
+#define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF_S 7
+#define AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE 0x00004000
+#define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_Q_COFF_M 0x003f8000
+#define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_Q_COFF_S 15
+#define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_I_COFF_M 0x1fc00000
+#define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_I_COFF_S 22
+#define AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN 0x20000000
+
+/* Bits for AR_PHY_PAPRD_AM2AM. */
+#define AR_PHY_PAPRD_AM2AM_MASK_M 0x01ffffff
+#define AR_PHY_PAPRD_AM2AM_MASK_S 0
+
+/* Bits for AR_PHY_PAPRD_AM2PM. */
+#define AR_PHY_PAPRD_AM2PM_MASK_M 0x01ffffff
+#define AR_PHY_PAPRD_AM2PM_MASK_S 0
+
+/* Bits for AR_PHY_PAPRD_HT40. */
+#define AR_PHY_PAPRD_HT40_MASK_M 0x01ffffff
+#define AR_PHY_PAPRD_HT40_MASK_S 0
+
+/* Bits for AR_PHY_PAPRD_CTRL0_B(i). */
+#define AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE 0x00000001
+#define AR_PHY_PAPRD_CTRL0_USE_SINGLE_TABLE 0x00000002
+#define AR_PHY_PAPRD_CTRL0_PAPRD_MAG_THRSH_M 0xf8000000
+#define AR_PHY_PAPRD_CTRL0_PAPRD_MAG_THRSH_S 27
+
+/* Bits for AR_PHY_PAPRD_CTRL1_B(i). */
+#define AR_PHY_PAPRD_CTRL1_ADAPTIVE_SCALING_ENA 0x00000001
+#define AR_PHY_PAPRD_CTRL1_ADAPTIVE_AM2AM_ENA 0x00000002
+#define AR_PHY_PAPRD_CTRL1_ADAPTIVE_AM2PM_ENA 0x00000004
+#define AR_PHY_PAPRD_CTRL1_POWER_AT_AM2AM_CAL_M 0x000001f8
+#define AR_PHY_PAPRD_CTRL1_POWER_AT_AM2AM_CAL_S 3
+#define AR_PHY_PAPRD_CTRL1_PA_GAIN_SCALE_FACT_M 0x0001fe00
+#define AR_PHY_PAPRD_CTRL1_PA_GAIN_SCALE_FACT_S 9
+#define AR_PHY_PAPRD_CTRL1_MAG_SCALE_FACT_M 0x0ffe0000
+#define AR_PHY_PAPRD_CTRL1_MAG_SCALE_FACT_S 17
+
+/* Bits for AR_PHY_PA_GAIN123_B(i). */
+#define AR_PHY_PA_GAIN123_PA_GAIN1_M 0x000003ff
+#define AR_PHY_PA_GAIN123_PA_GAIN1_S 0
+
+/* Bits for AR_PHY_PAPRD_PRE_POST_SCALE_B0(i). */
+#define AR_PHY_PAPRD_PRE_POST_SCALING_M 0x0003ffff
+#define AR_PHY_PAPRD_PRE_POST_SCALING_S 0
+
+/* Bits for AR_PHY_PAPRD_MEM_TAB_B(i). */
+#define AR_PHY_PAPRD_ANGLE_M 0x000007ff
+#define AR_PHY_PAPRD_ANGLE_S 0
+#define AR_PHY_PAPRD_PA_IN_M 0x003ff800
+#define AR_PHY_PAPRD_PA_IN_S 11
+
+/* Bits for AR_PHY_PILOT_SPUR_MASK. */
+#define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A_M 0x0000001f
+#define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A_S 0
+#define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A_M 0x00000fe0
+#define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A_S 5
+
+/* Bits for AR_PHY_CHAN_SPUR_MASK. */
+#define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A_M 0x0000001f
+#define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A_S 0
+#define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A_M 0x00000fe0
+#define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A_S 5
+
+/* Bits for AR_PHY_SGI_DELTA. */
+#define AR_PHY_SGI_DSC_EXP_M 0x0000000f
+#define AR_PHY_SGI_DSC_EXP_S 0
+#define AR_PHY_SGI_DSC_MAN_M 0x0007fff0
+#define AR_PHY_SGI_DSC_MAN_S 4
+
+/* Bits for AR_PHY_SETTLING. */
+#define AR_PHY_SETTLING_SWITCH_M 0x00003f80
+#define AR_PHY_SETTLING_SWITCH_S 7
+
+/* Bits for AR_PHY_RXGAIN(i). */
+#define AR_PHY_RXGAIN_TXRX_ATTEN_M 0x0003f000
+#define AR_PHY_RXGAIN_TXRX_ATTEN_S 12
+#define AR_PHY_RXGAIN_TXRX_RF_MAX_M 0x007c0000
+#define AR_PHY_RXGAIN_TXRX_RF_MAX_S 18
+
+/* Bits for AR_PHY_DESIRED_SZ. */
+#define AR_PHY_DESIRED_SZ_ADC_M 0x000000ff
+#define AR_PHY_DESIRED_SZ_ADC_S 0
+#define AR_PHY_DESIRED_SZ_PGA_M 0x0000ff00
+#define AR_PHY_DESIRED_SZ_PGA_S 8
+#define AR_PHY_DESIRED_SZ_TOT_DES_M 0x0ff00000
+#define AR_PHY_DESIRED_SZ_TOT_DES_S 20
+
+/* Bits for AR_PHY_FIND_SIG. */
+#define AR_PHY_FIND_SIG_RELSTEP_M 0x0000001f
+#define AR_PHY_FIND_SIG_RELSTEP_S 0
+#define AR_PHY_FIND_SIG_RELPWR_M 0x000007c0
+#define AR_PHY_FIND_SIG_RELPWR_S 6
+#define AR_PHY_FIND_SIG_FIRSTEP_M 0x0003f000
+#define AR_PHY_FIND_SIG_FIRSTEP_S 12
+#define AR_PHY_FIND_SIG_FIRPWR_M 0x03fc0000
+#define AR_PHY_FIND_SIG_FIRPWR_S 18
+
+/* Bits for AR_PHY_AGC. */
+#define AR_PHY_AGC_COARSE_PWR_CONST_M 0x0000007f
+#define AR_PHY_AGC_COARSE_PWR_CONST_S 0
+#define AR_PHY_AGC_COARSE_LOW_M 0x00007f80
+#define AR_PHY_AGC_COARSE_LOW_S 7
+#define AR_PHY_AGC_COARSE_HIGH_M 0x003f8000
+#define AR_PHY_AGC_COARSE_HIGH_S 15
+
+/* Bits for AR_PHY_EXT_ATTEN_CTL(i). */
+#define AR_PHY_EXT_ATTEN_CTL_BSW_ATTEN_M 0x0000001f
+#define AR_PHY_EXT_ATTEN_CTL_BSW_ATTEN_S 0
+#define AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB_M 0x0000003f
+#define AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB_S 0
+#define AR_PHY_EXT_ATTEN_CTL_XATTEN2_DB_M 0x00000fc0
+#define AR_PHY_EXT_ATTEN_CTL_XATTEN2_DB_S 6
+#define AR_PHY_EXT_ATTEN_CTL_BSW_MARGIN_M 0x00003c00
+#define AR_PHY_EXT_ATTEN_CTL_BSW_MARGIN_S 10
+#define AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN_M 0x0001f000
+#define AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN_S 12
+#define AR_PHY_EXT_ATTEN_CTL_XATTEN2_MARGIN_M 0x003e0000
+#define AR_PHY_EXT_ATTEN_CTL_XATTEN2_MARGIN_S 17
+#define AR_PHY_EXT_ATTEN_CTL_RXTX_MARGIN_M 0x00fc0000
+#define AR_PHY_EXT_ATTEN_CTL_RXTX_MARGIN_S 18
+
+/* Bits for AR_PHY_CCA(i). */
+#define AR_PHY_MAXCCA_PWR_M 0x000001ff
+#define AR_PHY_MAXCCA_PWR_S 0
+#define AR_PHY_MINCCA_PWR_M 0x1ff00000
+#define AR_PHY_MINCCA_PWR_S 20
+
+/* Bits for AR_PHY_EXT_CCA(i). */
+#define AR_PHY_EXT_MAXCCA_PWR_M 0x000001ff
+#define AR_PHY_EXT_MAXCCA_PWR_S 0
+#define AR_PHY_EXT_MINCCA_PWR_M 0x01ff0000
+#define AR_PHY_EXT_MINCCA_PWR_S 16
+
+/* Bits for AR_PHY_RESTART. */
+#define AR_PHY_RESTART_ENA 0x00000001
+#define AR_PHY_RESTART_DIV_GC_M 0x001c0000
+#define AR_PHY_RESTART_DIV_GC_S 18
+
+/* Bits for AR_PHY_MC_GAIN_CTRL. */
+#define AR_PHY_MC_GAIN_CTRL_ENABLE_ANT_DIV 0x01000000
+#define AR_PHY_MC_GAIN_CTRL_ANT_DIV_CTRL_ALL_M 0x7e000000
+#define AR_PHY_MC_GAIN_CTRL_ANT_DIV_CTRL_ALL_S 25
+
+/* Bits for AR_PHY_CCK_DETECT. */
+#define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_M 0x0000003f
+#define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S 0
+#define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME_M 0x00001fc0
+#define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME_S 6
+#define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV 0x00002000
+
+/* Bits for AR_PHY_DAG_CTRLCCK. */
+#define AR_PHY_DAG_CTRLCCK_EN_RSSI_THR 0x00000200
+#define AR_PHY_DAG_CTRLCCK_RSSI_THR_M 0x0001fc00
+#define AR_PHY_DAG_CTRLCCK_RSSI_THR_S 10
+
+/* Bits for AR_PHY_CCK_SPUR_MIT. */
+#define AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT 0x00000001
+#define AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR_M 0x000001fe
+#define AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR_S 1
+#define AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ_M 0x1ffffe00
+#define AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ_S 9
+#define AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE_M 0x60000000
+#define AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE_S 29
+
+/* Bits for AR_PHY_GEN_CTRL. */
+#define AR_PHY_GC_TURBO_MODE 0x00000001
+#define AR_PHY_GC_TURBO_SHORT 0x00000002
+#define AR_PHY_GC_DYN2040_EN 0x00000004
+#define AR_PHY_GC_DYN2040_PRI_ONLY 0x00000008
+#define AR_PHY_GC_DYN2040_PRI_CH 0x00000010
+#define AR_PHY_GC_DYN2040_EXT_CH 0x00000020
+#define AR_PHY_GC_HT_EN 0x00000040
+#define AR_PHY_GC_SHORT_GI_40 0x00000080
+#define AR_PHY_GC_WALSH 0x00000100
+#define AR_PHY_GC_SINGLE_HT_LTF1 0x00000200
+#define AR_PHY_GC_GF_DETECT_EN 0x00000400
+#define AR_PHY_GC_ENABLE_DAC_FIFO 0x00000800
+
+/* Bits for AR_PHY_MODE. */
+#define AR_PHY_MODE_OFDM 0x00000000
+#define AR_PHY_MODE_CCK 0x00000001
+#define AR_PHY_MODE_DYNAMIC 0x00000004
+#define AR_PHY_MODE_HALF 0x00000020
+#define AR_PHY_MODE_QUARTER 0x00000040
+#define AR_PHY_MODE_DYN_CCK_DISABLE 0x00000100
+#define AR_PHY_MODE_SVD_HALF 0x00000200
+
+/* Bits for AR_PHY_ACTIVE. */
+#define AR_PHY_ACTIVE_DIS 0x00000000
+#define AR_PHY_ACTIVE_EN 0x00000001
+
+/* Bits for AR_PHY_SPUR_MASK_A. */
+#define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A_M 0x000003ff
+#define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A_S 0
+#define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A_M 0x0001fc00
+#define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A_S 10
+
+/* Bits for AR_PHY_SPECTRAL_SCAN. */
+#define AR_PHY_SPECTRAL_SCAN_ENABLE 0x00000001
+#define AR_PHY_SPECTRAL_SCAN_ACTIVE 0x00000002
+#define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD_M 0x000000f0
+#define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD_S 4
+#define AR_PHY_SPECTRAL_SCAN_PERIOD_M 0x0000ff00
+#define AR_PHY_SPECTRAL_SCAN_PERIOD_S 8
+#define AR_PHY_SPECTRAL_SCAN_COUNT_M 0x00ff0000
+#define AR_PHY_SPECTRAL_SCAN_COUNT_S 16
+#define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT 0x01000000
+
+/* Bits for AR_PHY_RFBUS_REQ. */
+#define AR_PHY_RFBUS_REQ_EN 0x00000001
+
+/* Bits for AR_PHY_RFBUS_GRANT. */
+#define AR_PHY_RFBUS_GRANT_EN 0x00000001
+
+/* Bits for AR_PHY_RIFS. */
+#define AR_PHY_RIFS_INIT_DELAY 0x3ff0000
+
+/* Bits for AR_PHY_RX_DELAY. */
+#define AR_PHY_RX_DELAY_DELAY_M 0x00003fff
+#define AR_PHY_RX_DELAY_DELAY_S 0
+
+/* Bits for AR_PHY_XPA_TIMING_CTL. */
+#define AR_PHY_XPA_TIMING_CTL_FRAME_XPAA_ON_M 0x000000ff
+#define AR_PHY_XPA_TIMING_CTL_FRAME_XPAA_ON_S 0
+#define AR_PHY_XPA_TIMING_CTL_FRAME_XPAB_ON_M 0x0000ff00
+#define AR_PHY_XPA_TIMING_CTL_FRAME_XPAB_ON_S 8
+#define AR_PHY_XPA_TIMING_CTL_TX_END_XPAA_OFF_M 0x00ff0000
+#define AR_PHY_XPA_TIMING_CTL_TX_END_XPAA_OFF_S 16
+#define AR_PHY_XPA_TIMING_CTL_TX_END_XPAB_OFF_M 0xff000000
+#define AR_PHY_XPA_TIMING_CTL_TX_END_XPAB_OFF_S 24
+
+/* Bits for AR_PHY_SWITCH_CHAIN. */
+#define AR_SWITCH_TABLE_ALL_M 0x00000fff
+#define AR_SWITCH_TABLE_ALL_S 0
+
+/* Bits for AR_PHY_SWITCH_COM. */
+#define AR_SWITCH_TABLE_COM_ALL_M 0x0000ffff
+#define AR_SWITCH_TABLE_COM_ALL_S 0
+
+/* Bits for AR_SWITCH_TABLE_COM_2. */
+#define AR_SWITCH_TABLE_COM_2_ALL_M 0x00ffffff
+#define AR_SWITCH_TABLE_COM_2_ALL_S 0
+
+/* Bits for AR_PHY_AGC_CONTROL. */
+#define AR_PHY_AGC_CONTROL_CAL 0x00000001
+#define AR_PHY_AGC_CONTROL_NF 0x00000002
+#define AR_PHY_AGC_CONTROL_YCOK_MAX_M 0x000003c0
+#define AR_PHY_AGC_CONTROL_YCOK_MAX_S 6
+#define AR_PHY_AGC_CONTROL_OFFSET_CAL 0x00000800
+#define AR_PHY_AGC_CONTROL_ENABLE_NF 0x00008000
+#define AR_PHY_AGC_CONTROL_FLTR_CAL 0x00010000
+#define AR_PHY_AGC_CONTROL_NO_UPDATE_NF 0x00020000
+#define AR_PHY_AGC_CONTROL_EXT_NF_PWR_MEAS 0x00040000
+#define AR_PHY_AGC_CONTROL_CLC_SUCCESS 0x00080000
+
+/* Bits for AR_PHY_CALMODE. */
+#define AR_PHY_CALMODE_IQ 0x00000000
+#define AR_PHY_CALMODE_ADC_GAIN 0x00000001
+#define AR_PHY_CALMODE_ADC_DC_PER 0x00000002
+#define AR_PHY_CALMODE_ADC_DC_INIT 0x00000003
+
+/* Bits for AR_PHY_FCAL_2_0. */
+#define AR_PHY_FCAL20_CAP_STATUS_0_M 0x01f00000
+#define AR_PHY_FCAL20_CAP_STATUS_0_S 20
+
+/* Bits for AR_PHY_SYNTH_CONTROL. */
+#define AR9380_BMODE 0x20000000
+
+/* Bits for AR_PHY_ANALOG_SWAP. */
+#define AR_PHY_SWAP_ALT_CHAIN 0x00000040
+
+/* Bits for AR_PHY_ADDAC_PARA_CTL. */
+#define AR_PHY_ADDAC_PARACTL_OFF_PWDADC 0x00008000
+
+/* Bits for AR_PHY_TEST. */
+#define AR_PHY_TEST_RFSILENT_BB 0x00002000
+#define AR_PHY_TEST_BBB_OBS_SEL_M 0x00780000
+#define AR_PHY_TEST_BBB_OBS_SEL_S 19
+#define AR_PHY_TEST_RX_OBS_SEL_BIT5 0x00800000
+#define AR_PHY_TEST_CHAIN_SEL_M 0xc0000000
+#define AR_PHY_TEST_CHAIN_SEL_S 30
+
+/* Bits for AR_PHY_TEST_CTL_STATUS. */
+#define AR_PHY_TEST_CTL_TSTDAC_EN 0x00000001
+#define AR_PHY_TEST_CTL_TX_OBS_SEL_M 0x0000001c
+#define AR_PHY_TEST_CTL_TX_OBS_SEL_S 2
+#define AR_PHY_TEST_CTL_TX_OBS_MUX_SEL_M 0x00000060
+#define AR_PHY_TEST_CTL_TX_OBS_MUX_SEL_S 5
+#define AR_PHY_TEST_CTL_TSTADC_EN 0x00000100
+#define AR_PHY_TEST_CTL_RX_OBS_SEL_M 0x00003c00
+#define AR_PHY_TEST_CTL_RX_OBS_SEL_S 10
+
+/* Bits for AR_PHY_CHAN_INFO_MEMORY. */
+#define AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK 0x00000001
+#define AR_PHY_CHAN_INFO_TAB_S2_READ 0x00000008
+
+/* Bits for AR_PHY_CHAN_INFO_GAIN_0. */
+#define AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_MASK 0x00000fff
+#define AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT 320
+
+/* Bits for AR_PHY_CCK_TX_CTRL. */
+#define AR_PHY_CCK_TX_CTRL_JAPAN 0x00000010
+
+/* Bits for AR_PHY_PWRTX_RATE5. */
+#define AR_PHY_PWRTX_RATE5_POWERTXHT20_0_M 0x0000003f
+#define AR_PHY_PWRTX_RATE5_POWERTXHT20_0_S 0
+
+/* Bits for AR_PHY_PWRTX_MAX. */
+#define AR_PHY_POWER_TX_RATE_MAX_TPC_ENABLE 0x00000040
+
+/* Bits for AR_PHY_TPC_1. */
+#define AR_PHY_TPC_1_FORCE_DAC_GAIN 0x00000001
+#define AR_PHY_TPC_1_FORCED_DAC_GAIN_M 0x0000003e
+#define AR_PHY_TPC_1_FORCED_DAC_GAIN_S 1
+
+/* Bits for AR_PHY_TPC_5_B(i). */
+#define AR_PHY_TPC_5_PD_GAIN_OVERLAP_M 0x0000000f
+#define AR_PHY_TPC_5_PD_GAIN_OVERLAP_S 0
+#define AR_PHY_TPC_5_PD_GAIN_BOUNDARY_1_M 0x000003f0
+#define AR_PHY_TPC_5_PD_GAIN_BOUNDARY_1_S 4
+#define AR_PHY_TPC_5_PD_GAIN_BOUNDARY_2_M 0x0000fc00
+#define AR_PHY_TPC_5_PD_GAIN_BOUNDARY_2_S 10
+#define AR_PHY_TPC_5_PD_GAIN_BOUNDARY_3_M 0x003f0000
+#define AR_PHY_TPC_5_PD_GAIN_BOUNDARY_3_S 16
+#define AR_PHY_TPC_5_PD_GAIN_BOUNDARY_4_M 0x0fc00000
+#define AR_PHY_TPC_5_PD_GAIN_BOUNDARY_4_S 22
+
+/* Bits for AR_PHY_TPC_6_B(i). */
+#define AR_PHY_TPC_6_ERROR_EST_MODE_M 0x03000000
+#define AR_PHY_TPC_6_ERROR_EST_MODE_S 24
+
+/* Bits for AR_PHY_TPC_11_B(i). */
+#define AR_PHY_TPC_11_OLPC_GAIN_DELTA_M 0x00ff0000
+#define AR_PHY_TPC_11_OLPC_GAIN_DELTA_S 16
+#define AR_PHY_TPC_11_OLPC_GAIN_DELTA_PAL_ON_M 0xff000000
+#define AR_PHY_TPC_11_OLPC_GAIN_DELTA_PAL_ON_S 24
+
+/* Bits for AR_PHY_TPC_12. */
+#define AR_PHY_TPC_12_DESIRED_SCALE_HT40_5_M 0x3e000000
+#define AR_PHY_TPC_12_DESIRED_SCALE_HT40_5_S 25
+
+/* Bits for AR_PHY_TPC_18. */
+#define AR_PHY_TPC_18_THERM_CAL_M 0x000000ff
+#define AR_PHY_TPC_18_THERM_CAL_S 0
+#define AR_PHY_TPC_18_VOLT_CAL_M 0x0000ff00
+#define AR_PHY_TPC_18_VOLT_CAL_S 8
+
+/* Bits for AR_PHY_TPC_19. */
+#define AR_PHY_TPC_19_ALPHA_THERM_M 0x000000ff
+#define AR_PHY_TPC_19_ALPHA_THERM_S 0
+#define AR_PHY_TPC_19_ALPHA_VOLT_M 0x001f0000
+#define AR_PHY_TPC_19_ALPHA_VOLT_S 16
+
+/* Bits for AR_PHY_BB_THERM_ADC_1. */
+#define AR_PHY_BB_THERM_ADC_1_INIT_THERM_M 0x000000ff
+#define AR_PHY_BB_THERM_ADC_1_INIT_THERM_S 0
+
+/* Bits for AR_PHY_BB_THERM_ADC_4. */
+#define AR_PHY_BB_THERM_ADC_4_LATEST_THERM_M 0x000000ff
+#define AR_PHY_BB_THERM_ADC_4_LATEST_THERM_S 0
+#define AR_PHY_BB_THERM_ADC_4_LATEST_VOLT_M 0x0000ff00
+#define AR_PHY_BB_THERM_ADC_4_LATEST_VOLT_S 8
+
+/* Bits for AR_PHY_TX_FORCED_GAIN. */
+#define AR_PHY_TX_FORCED_GAIN_FORCE_TX_GAIN 0x00000001
+#define AR_PHY_TX_FORCED_GAIN_TXBB1DBGAIN_M 0x0000000e
+#define AR_PHY_TX_FORCED_GAIN_TXBB1DBGAIN_S 1
+#define AR_PHY_TX_FORCED_GAIN_TXBB6DBGAIN_M 0x00000030
+#define AR_PHY_TX_FORCED_GAIN_TXBB6DBGAIN_S 4
+#define AR_PHY_TX_FORCED_GAIN_TXMXRGAIN_M 0x000003c0
+#define AR_PHY_TX_FORCED_GAIN_TXMXRGAIN_S 6
+#define AR_PHY_TX_FORCED_GAIN_PADRVGNA_M 0x00003c00
+#define AR_PHY_TX_FORCED_GAIN_PADRVGNA_S 10
+#define AR_PHY_TX_FORCED_GAIN_PADRVGNB_M 0x0003c000
+#define AR_PHY_TX_FORCED_GAIN_PADRVGNB_S 14
+#define AR_PHY_TX_FORCED_GAIN_PADRVGNC_M 0x003c0000
+#define AR_PHY_TX_FORCED_GAIN_PADRVGNC_S 18
+#define AR_PHY_TX_FORCED_GAIN_PADRVGND_M 0x00c00000
+#define AR_PHY_TX_FORCED_GAIN_PADRVGND_S 22
+#define AR_PHY_TX_FORCED_GAIN_ENABLE_PAL 0x01000000
+
+/* Bits for AR_PHY_TXGAIN_TABLE(i). */
+#define AR_PHY_TXGAIN_TXBB1DBGAIN_M 0x00000007
+#define AR_PHY_TXGAIN_TXBB1DBGAIN_S 0
+#define AR_PHY_TXGAIN_TXBB6DBGAIN_M 0x00000018
+#define AR_PHY_TXGAIN_TXBB6DBGAIN_S 3
+#define AR_PHY_TXGAIN_TXMXRGAIN_M 0x000001e0
+#define AR_PHY_TXGAIN_TXMXRGAIN_S 5
+#define AR_PHY_TXGAIN_PADRVGNA_M 0x00001e00
+#define AR_PHY_TXGAIN_PADRVGNA_S 9
+#define AR_PHY_TXGAIN_PADRVGNB_M 0x0001e000
+#define AR_PHY_TXGAIN_PADRVGNB_S 13
+#define AR_PHY_TXGAIN_PADRVGNC_M 0x001e0000
+#define AR_PHY_TXGAIN_PADRVGNC_S 17
+#define AR_PHY_TXGAIN_PADRVGND_M 0x00600000
+#define AR_PHY_TXGAIN_PADRVGND_S 21
+#define AR_PHY_TXGAIN_INDEX_M 0xff000000
+#define AR_PHY_TXGAIN_INDEX_S 24
+
+/* Bits for AR_PHY_TX_IQCAL_CONTROL_1. */
+#define AR_PHY_TX_IQCAQL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_M 0x01fc0000
+#define AR_PHY_TX_IQCAQL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_S 18
+
+/* Bits for AR_PHY_TX_IQCAL_START. */
+#define AR_PHY_TX_IQCAL_START_DO_CAL 0x00000001
+
+/* Bits for AR_PHY_TX_IQCAL_CORR_COEFF_01_B(i). */
+#define AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE_M 0x00003fff
+#define AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE_S 0
+
+/* Bits for AR_PHY_TX_IQCAL_STATUS_B(i). */
+#define AR_PHY_TX_IQCAL_STATUS_FAILED 0x00000001
+
+/* Bits for AR_PHY_PAPRD_TRAINER_CNTL1. */
+#define AR_PHY_PAPRD_TRAINER_CNTL1_TRAIN_ENABLE 0x00000001
+#define AR_PHY_PAPRD_TRAINER_CNTL1_AGC2_SETTLING_M 0x0000007e
+#define AR_PHY_PAPRD_TRAINER_CNTL1_AGC2_SETTLING_S 1
+#define AR_PHY_PAPRD_TRAINER_CNTL1_IQCORR_ENABLE 0x00000100
+#define AR_PHY_PAPRD_TRAINER_CNTL1_RX_BB_GAIN_FORCE 0x00000200
+#define AR_PHY_PAPRD_TRAINER_CNTL1_TX_GAIN_FORCE 0x00000400
+#define AR_PHY_PAPRD_TRAINER_CNTL1_LB_ENABLE 0x00000800
+#define AR_PHY_PAPRD_TRAINER_CNTL1_LB_SKIP_M 0x0003f000
+#define AR_PHY_PAPRD_TRAINER_CNTL1_LB_SKIP_S 12
+
+/* Bits for AR_PHY_PAPRD_TRAINER_CNTL3. */
+#define AR_PHY_PAPRD_TRAINER_CNTL3_ADC_DESIRED_SIZE_M 0x0000003f
+#define AR_PHY_PAPRD_TRAINER_CNTL3_ADC_DESIRED_SIZE_S 0
+#define AR_PHY_PAPRD_TRAINER_CNTL3_QUICK_DROP_M 0x00000fc0
+#define AR_PHY_PAPRD_TRAINER_CNTL3_QUICK_DROP_S 6
+#define AR_PHY_PAPRD_TRAINER_CNTL3_MIN_LOOPBACK_DEL_M 0x0001f000
+#define AR_PHY_PAPRD_TRAINER_CNTL3_MIN_LOOPBACK_DEL_S 12
+#define AR_PHY_PAPRD_TRAINER_CNTL3_NUM_CORR_STAGES_M 0x000e0000
+#define AR_PHY_PAPRD_TRAINER_CNTL3_NUM_CORR_STAGES_S 17
+#define AR_PHY_PAPRD_TRAINER_CNTL3_COARSE_CORR_LEN_M 0x00f00000
+#define AR_PHY_PAPRD_TRAINER_CNTL3_COARSE_CORR_LEN_S 20
+#define AR_PHY_PAPRD_TRAINER_CNTL3_FINE_CORR_LEN_M 0x0f000000
+#define AR_PHY_PAPRD_TRAINER_CNTL3_FINE_CORR_LEN_S 24
+#define AR_PHY_PAPRD_TRAINER_CNTL3_BBTXMIX_DISABLE 0x20000000
+
+/* Bits for AR_PHY_PAPRD_TRAINER_CNTL4. */
+#define AR_PHY_PAPRD_TRAINER_CNTL4_MIN_CORR_M 0x00000fff
+#define AR_PHY_PAPRD_TRAINER_CNTL4_MIN_CORR_S 0
+#define AR_PHY_PAPRD_TRAINER_CNTL4_SAFETY_DELTA_M 0x0000f000
+#define AR_PHY_PAPRD_TRAINER_CNTL4_SAFETY_DELTA_S 12
+#define AR_PHY_PAPRD_TRAINER_CNTL4_NUM_TRAIN_SAMPLES_M 0x03ff0000
+#define AR_PHY_PAPRD_TRAINER_CNTL4_NUM_TRAIN_SAMPLES_S 16
+
+/* Bits for AR_PHY_PAPRD_TRAINER_STAT1. */
+#define AR_PHY_PAPRD_TRAINER_STAT1_TRAIN_DONE 0x00000001
+#define AR_PHY_PAPRD_TRAINER_STAT1_TRAIN_INCOMPLETE 0x00000002
+#define AR_PHY_PAPRD_TRAINER_STAT1_CORR_ERR 0x00000004
+#define AR_PHY_PAPRD_TRAINER_STAT1_TRAIN_ACTIVE 0x00000008
+#define AR_PHY_PAPRD_TRAINER_STAT1_RX_GAIN_IDX_M 0x000001f0
+#define AR_PHY_PAPRD_TRAINER_STAT1_RX_GAIN_IDX_S 4
+#define AR_PHY_PAPRD_TRAINER_STAT1_AGC2_PWR_M 0x0001fe00
+#define AR_PHY_PAPRD_TRAINER_STAT1_AGC2_PWR_S 9
+
+/* Bits for AR_PHY_PAPRD_TRAINER_STAT2. */
+#define AR_PHY_PAPRD_TRAINER_STAT2_FINE_VAL_M 0x0000ffff
+#define AR_PHY_PAPRD_TRAINER_STAT2_FINE_VAL_S 0
+#define AR_PHY_PAPRD_TRAINER_STAT2_COARSE_IDX_M 0x001f0000
+#define AR_PHY_PAPRD_TRAINER_STAT2_COARSE_IDX_S 16
+#define AR_PHY_PAPRD_TRAINER_STAT2_FINE_IDX_M 0x00600000
+#define AR_PHY_PAPRD_TRAINER_STAT2_FINE_IDX_S 21
+
+/* Bits for AR_PHY_PAPRD_TRAINER_STAT3. */
+#define AR_PHY_PAPRD_TRAINER_STAT3_TRAIN_SAMPLES_CNT_M 0x000fffff
+#define AR_PHY_PAPRD_TRAINER_STAT3_TRAIN_SAMPLES_CNT_S 0
+
+/* Bits for AR_PHY_65NM_CH0_SYNTH4. */
+#define AR_PHY_SYNTH4_LONG_SHIFT_SELECT 0x00000002
+
+/* Bits for AR_PHY_65NM_CH0_SYNTH7. */
+#define AR9380_FRACMODE 0x40000000
+#define AR9380_LOAD_SYNTH 0x80000000
+
+/* Bits for AR_PHY_65NM_CH0_BIAS1. */
+#define AR_PHY_65NM_CH0_BIAS1_0_M 0x000001c0
+#define AR_PHY_65NM_CH0_BIAS1_0_S 6
+#define AR_PHY_65NM_CH0_BIAS1_1_M 0x00000e00
+#define AR_PHY_65NM_CH0_BIAS1_1_S 9
+#define AR_PHY_65NM_CH0_BIAS1_2_M 0x00007000
+#define AR_PHY_65NM_CH0_BIAS1_2_S 12
+#define AR_PHY_65NM_CH0_BIAS1_3_M 0x00038000
+#define AR_PHY_65NM_CH0_BIAS1_3_S 15
+#define AR_PHY_65NM_CH0_BIAS1_4_M 0x001c0000
+#define AR_PHY_65NM_CH0_BIAS1_4_S 18
+#define AR_PHY_65NM_CH0_BIAS1_5_M 0x00e00000
+#define AR_PHY_65NM_CH0_BIAS1_5_S 21
+
+/* Bits for AR_PHY_65NM_CH0_BIAS2. */
+#define AR_PHY_65NM_CH0_BIAS2_0_M 0x000000e0
+#define AR_PHY_65NM_CH0_BIAS2_0_S 5
+#define AR_PHY_65NM_CH0_BIAS2_1_M 0x00000700
+#define AR_PHY_65NM_CH0_BIAS2_1_S 8
+#define AR_PHY_65NM_CH0_BIAS2_2_M 0x00003800
+#define AR_PHY_65NM_CH0_BIAS2_2_S 11
+#define AR_PHY_65NM_CH0_BIAS2_3_M 0x0001c000
+#define AR_PHY_65NM_CH0_BIAS2_3_S 14
+#define AR_PHY_65NM_CH0_BIAS2_4_M 0x000e0000
+#define AR_PHY_65NM_CH0_BIAS2_4_S 17
+#define AR_PHY_65NM_CH0_BIAS2_5_M 0x00700000
+#define AR_PHY_65NM_CH0_BIAS2_5_S 20
+#define AR_PHY_65NM_CH0_BIAS2_6_M 0x03800000
+#define AR_PHY_65NM_CH0_BIAS2_6_S 23
+#define AR_PHY_65NM_CH0_BIAS2_7_M 0x1c000000
+#define AR_PHY_65NM_CH0_BIAS2_7_S 26
+#define AR_PHY_65NM_CH0_BIAS2_8_M 0xe0000000
+#define AR_PHY_65NM_CH0_BIAS2_8_S 29
+
+/* Bits for AR_PHY_65NM_CH0_BIAS4. */
+#define AR_PHY_65NM_CH0_BIAS4_0_M 0x03800000
+#define AR_PHY_65NM_CH0_BIAS4_0_S 23
+#define AR_PHY_65NM_CH0_BIAS4_1_M 0x1c000000
+#define AR_PHY_65NM_CH0_BIAS4_1_S 26
+#define AR_PHY_65NM_CH0_BIAS4_2_M 0xe0000000
+#define AR_PHY_65NM_CH0_BIAS4_2_S 29
+
+/* Bits for AR_PHY_65NM_CH0_RXTX4. */
+#define AR_PHY_65NM_CH0_RXTX4_THERM_ON 0x10000000
+
+/* Bits for AR9485_PHY_65NM_CH0_TOP2. */
+#define AR9485_PHY_65NM_CH0_TOP2_XPABIASLVL_M 0x0000f000
+#define AR9485_PHY_65NM_CH0_TOP2_XPABIASLVL_S 12
+
+/* Bits for AR_PHY_65NM_CH0_TOP. */
+#define AR_PHY_65NM_CH0_TOP_XPABIASLVL_M 0x00000300
+#define AR_PHY_65NM_CH0_TOP_XPABIASLVL_S 8
+
+/* Bits for AR_PHY_65NM_CH0_THERM. */
+#define AR_PHY_65NM_CH0_THERM_XPABIASLVL_MSB_M 0x00000003
+#define AR_PHY_65NM_CH0_THERM_XPABIASLVL_MSB_S 0
+#define AR_PHY_65NM_CH0_THERM_XPASHORT2GND 0x00000004
+#define AR_PHY_65NM_CH0_THERM_SAR_ADC_OUT_M 0x0000ff00
+#define AR_PHY_65NM_CH0_THERM_SAR_ADC_OUT_S 8
+#define AR_PHY_65NM_CH0_THERM_START 0x20000000
+#define AR_PHY_65NM_CH0_THERM_LOCAL 0x80000000
+
+/* Bits for AR9485_PHY_CH0_XTAL. */
+#define AR9485_PHY_CH0_XTAL_CAPINDAC_M 0x7f000000
+#define AR9485_PHY_CH0_XTAL_CAPINDAC_S 24
+#define AR9485_PHY_CH0_XTAL_CAPOUTDAC_M 0x00fe0000
+#define AR9485_PHY_CH0_XTAL_CAPOUTDAC_S 17
+
+/* Bits for AR_PHY_PMU1. */
+#define AR_PHY_PMU1_PWD 0x00000001
+
+/* Bits for AR_PHY_PMU2. */
+#define AR_PHY_PMU2_PGM 0x00200000
+
+/*
+ * OTP registers.
+ */
+#define AR_OTP_BASE(i) (0x14000 + (i) * 4)
+#define AR_OTP_STATUS 0x15f18
+#define AR_OTP_READ_DATA 0x15f1c
+
+/* Bits for AR_OTP_STATUS. */
+#define AR_OTP_STATUS_TYPE_M 0x00000007
+#define AR_OTP_STATUS_TYPE_S 0
+#define AR_OTP_STATUS_SM_BUSY 0x1
+#define AR_OTP_STATUS_ACCESS_BUSY 0x2
+#define AR_OTP_STATUS_VALID 0x4
+
+
+#define AR9003_MAX_CHAINS 3
+
+#define AR9003_TX_QDEPTH 8
+#define AR9003_RX_LP_QDEPTH 128
+#define AR9003_RX_HP_QDEPTH 16
+
+#define AR9003_NTXSTATUS 64
+
+/* Maximum number of DMA segments per Tx descriptor. */
+#define AR9003_MAX_SCATTER 4
+
+/*
+ * Tx DMA descriptor.
+ */
+struct ar_tx_desc {
+ uint32_t ds_info;
+ uint32_t ds_link;
+ struct {
+ uint32_t ds_data;
+ uint32_t ds_ctl;
+ } __packed ds_segs[AR9003_MAX_SCATTER];
+ uint32_t ds_ctl10;
+ uint32_t ds_ctl11;
+ uint32_t ds_ctl12;
+ uint32_t ds_ctl13;
+ uint32_t ds_ctl14;
+ uint32_t ds_ctl15;
+ uint32_t ds_ctl16;
+ uint32_t ds_ctl17;
+ uint32_t ds_ctl18;
+ uint32_t ds_ctl19;
+ uint32_t ds_ctl20;
+ uint32_t ds_ctl21;
+ uint32_t ds_ctl22;
+ /*
+ * Padding to make Tx descriptors 128 bytes such that they will
+ * not cross a 4KB boundary.
+ */
+ uint32_t pad[9];
+} __packed __attribute__((aligned(4)));
+
+/* Bits for ds_info. */
+#define AR_TXI_DESC_NDWORDS_M 0x000000ff
+#define AR_TXI_DESC_NDWORDS_S 0
+#define AR_TXI_QCU_NUM_M 0x00000f00
+#define AR_TXI_QCU_NUM_S 8
+#define AR_TXI_CTRL_STAT 0x00004000
+#define AR_TXI_DESC_TX 0x00008000
+#define AR_TXI_DESC_ID_M 0xffff0000
+#define AR_TXI_DESC_ID_S 16
+#define AR_VENDOR_ATHEROS 0x168c /* NB: PCI_VENDOR_ATHEROS */
+
+/* Bits for ds_ctl. */
+#define AR_TXC_BUF_LEN_M 0x0fff0000
+#define AR_TXC_BUF_LEN_S 16
+
+/* Bits for ds_ctl10. */
+#define AR_TXC10_PTR_CHK_SUM_M 0x0000ffff
+#define AR_TXC10_PTR_CHK_SUM_S 0
+
+/* Bits for ds_ctl11. */
+#define AR_TXC11_FRAME_LEN_M 0x00000fff
+#define AR_TXC11_FRAME_LEN_S 0
+#define AR_TXC11_XMIT_POWER_M 0x003f0000
+#define AR_TXC11_XMIT_POWER_S 16
+#define AR_TXC11_RTS_ENABLE 0x00400000
+#define AR_TXC11_CLR_DEST_MASK 0x01000000
+#define AR_TXC11_DEST_IDX_VALID 0x40000000
+#define AR_TXC11_CTS_ENABLE 0x80000000
+
+/* Bits for ds_ctl12. */
+#define AR_TXC12_PAPRD_CHAIN_MASK_M 0x00000e00
+#define AR_TXC12_PAPRD_CHAIN_MASK_S 9
+#define AR_TXC12_DEST_IDX_M 0x000fe000
+#define AR_TXC12_DEST_IDX_S 13
+#define AR_TXC12_FRAME_TYPE_M 0x00f00000
+#define AR_TXC12_FRAME_TYPE_S 20
+#define AR_FRAME_TYPE_NORMAL 0
+#define AR_FRAME_TYPE_ATIM 1
+#define AR_FRAME_TYPE_PSPOLL 2
+#define AR_FRAME_TYPE_BEACON 3
+#define AR_FRAME_TYPE_PROBE_RESP 4
+#define AR_TXC12_NO_ACK 0x01000000
+
+/* Bits for ds_ctl13. */
+#define AR_TXC13_BURST_DUR_M 0x00007fff
+#define AR_TXC13_BURST_DUR_S 0
+#define AR_TXC13_DUR_UPDATE_ENA 0x00008000
+#define AR_TXC13_XMIT_DATA_TRIES0_M 0x000f0000
+#define AR_TXC13_XMIT_DATA_TRIES0_S 16
+#define AR_TXC13_XMIT_DATA_TRIES1_M 0x00f00000
+#define AR_TXC13_XMIT_DATA_TRIES1_S 20
+#define AR_TXC13_XMIT_DATA_TRIES2_M 0x0f000000
+#define AR_TXC13_XMIT_DATA_TRIES2_S 24
+#define AR_TXC13_XMIT_DATA_TRIES3_M 0xf0000000
+#define AR_TXC13_XMIT_DATA_TRIES3_S 28
+
+/* Bits for ds_ctl14. */
+#define AR_TXC14_XMIT_RATE0_M 0x000000ff
+#define AR_TXC14_XMIT_RATE0_S 0
+#define AR_TXC14_XMIT_RATE1_M 0x0000ff00
+#define AR_TXC14_XMIT_RATE1_S 8
+#define AR_TXC14_XMIT_RATE2_M 0x00ff0000
+#define AR_TXC14_XMIT_RATE2_S 16
+#define AR_TXC14_XMIT_RATE3_M 0xff000000
+#define AR_TXC14_XMIT_RATE3_S 24
+
+/* Bits for ds_ctl15. */
+#define AR_TXC15_PACKET_DUR0_M 0x00007fff
+#define AR_TXC15_PACKET_DUR0_S 0
+#define AR_TXC15_RTSCTS_QUAL0 0x00008000
+#define AR_TXC15_PACKET_DUR1_M 0x7fff0000
+#define AR_TXC15_PACKET_DUR1_S 16
+#define AR_TXC15_RTSCTS_QUAL1 0x80000000
+/* Shortcut. */
+#define AR_TXC15_RTSCTS_QUAL01 \
+ (AR_TXC15_RTSCTS_QUAL0 | AR_TXC15_RTSCTS_QUAL1)
+
+/* Bits for ds_ctl16. */
+#define AR_TXC16_PACKET_DUR2_M 0x00007fff
+#define AR_TXC16_PACKET_DUR2_S 0
+#define AR_TXC16_RTSCTS_QUAL2 0x00008000
+#define AR_TXC16_PACKET_DUR3_M 0x7fff0000
+#define AR_TXC16_PACKET_DUR3_S 16
+#define AR_TXC16_RTSCTS_QUAL3 0x80000000
+/* Shortcut. */
+#define AR_TXC16_RTSCTS_QUAL23 \
+ (AR_TXC16_RTSCTS_QUAL2 | AR_TXC16_RTSCTS_QUAL3)
+
+/* Bits for ds_ctl17. */
+#define AR_TXC17_ENCR_TYPE_M 0x0c000000
+#define AR_TXC17_ENCR_TYPE_S 26
+#define AR_ENCR_TYPE_CLEAR 0
+#define AR_ENCR_TYPE_WEP 1
+#define AR_ENCR_TYPE_AES 2
+#define AR_ENCR_TYPE_TKIP 3
+
+/* Bits for ds_ctl18. */
+#define AR_TXC18_2040_0 0x00000001
+#define AR_TXC18_GI0 0x00000002
+#define AR_TXC18_CHAIN_SEL0_M 0x0000001c
+#define AR_TXC18_CHAIN_SEL0_S 2
+#define AR_TXC18_2040_1 0x00000020
+#define AR_TXC18_GI1 0x00000040
+#define AR_TXC18_CHAIN_SEL1_M 0x00000380
+#define AR_TXC18_CHAIN_SEL1_S 7
+#define AR_TXC18_2040_2 0x00000400
+#define AR_TXC18_GI2 0x00000800
+#define AR_TXC18_CHAIN_SEL2_M 0x00007000
+#define AR_TXC18_CHAIN_SEL2_S 12
+#define AR_TXC18_2040_3 0x00008000
+#define AR_TXC18_GI3 0x00010000
+#define AR_TXC18_CHAIN_SEL3_M 0x000e0000
+#define AR_TXC18_CHAIN_SEL3_S 17
+#define AR_TXC18_RTSCTS_RATE_M 0x0ff00000
+#define AR_TXC18_RTSCTS_RATE_S 20
+/* Shortcuts. */
+#define AR_TXC18_2040_0123 \
+ (AR_TXC18_2040_0 | AR_TXC18_2040_1 | AR_TXC18_2040_2 | AR_TXC18_2040_3)
+#define AR_TXC18_GI0123 \
+ (AR_TXC18_GI0 | AR_TXC18_GI1 | AR_TXC18_GI2 | AR_TXC18_GI3)
+
+/* Bits for ds_ctl19. */
+#define AR_TXC19_NOT_SOUNDING 0x20000000
+
+/*
+ * Tx status DMA descriptor.
+ */
+struct ar_tx_status {
+ uint32_t ds_info;
+ uint32_t ds_status1;
+ uint32_t ds_status2;
+ uint32_t ds_status3;
+ uint32_t ds_status4;
+ uint32_t ds_status5;
+ uint32_t ds_status6;
+ uint32_t ds_status7;
+ uint32_t ds_status8;
+} __packed __attribute__((aligned(4)));
+
+/* Bits for ds_status3. */
+#define AR_TXS3_EXCESSIVE_RETRIES 0x00000002
+#define AR_TXS3_FIFO_UNDERRUN 0x00000004
+#define AR_TXS3_RTS_FAIL_CNT_M 0x000000f0
+#define AR_TXS3_RTS_FAIL_CNT_S 4
+#define AR_TXS3_DATA_FAIL_CNT_M 0x00000f00
+#define AR_TXS3_DATA_FAIL_CNT_S 8
+#define AR_TXS3_TX_DELIM_UNDERRUN 0x00010000
+#define AR_TXS3_TX_DATA_UNDERRUN 0x00020000
+/* Shortcut. */
+#define AR_TXS3_UNDERRUN \
+ (AR_TXS3_FIFO_UNDERRUN | \
+ AR_TXS3_TX_DELIM_UNDERRUN | \
+ AR_TXS3_TX_DATA_UNDERRUN)
+
+/* Bits for ds_status8. */
+#define AR_TXS8_DONE 0x00000001
+#define AR_TXS8_FINAL_IDX_M 0x00600000
+#define AR_TXS8_FINAL_IDX_S 21
+
+/*
+ * Rx status DMA descriptor.
+ */
+struct ar_rx_status {
+ uint32_t ds_info;
+ uint32_t ds_status1;
+ uint32_t ds_status2;
+ uint32_t ds_status3;
+ uint32_t ds_status4;
+ uint32_t ds_status5;
+ uint32_t ds_status6;
+ uint32_t ds_status7;
+ uint32_t ds_status8;
+ uint32_t ds_status9;
+ uint32_t ds_status10;
+ uint32_t ds_status11;
+} __packed __attribute__((aligned(4)));
+
+/* Bits for ds_info. */
+#define AR_RXI_CTRL_STAT 0x00004000
+#define AR_RXI_DESC_TX 0x00008000
+#define AR_RXI_DESC_ID_M 0xffff0000
+#define AR_RXI_DESC_ID_S 16
+
+/* Bits for ds_status1. */
+#define AR_RXS1_DONE 0x00000001
+#define AR_RXS1_RATE_M 0x000003fc
+#define AR_RXS1_RATE_S 2
+
+/* Bits for ds_status2. */
+#define AR_RXS2_DATA_LEN_M 0x00000fff
+#define AR_RXS2_DATA_LEN_S 0
+
+/* Bits for ds_status4. */
+#define AR_RXS4_GI 0x00000001
+#define AR_RXS4_ANTENNA_M 0xffffff00
+#define AR_RXS4_ANTENNA_S 8
+
+/* Bits for ds_status5. */
+#define AR_RXS5_RSSI_COMBINED_M 0xff000000
+#define AR_RXS5_RSSI_COMBINED_S 24
+
+/* Bits for ds_status11. */
+#define AR_RXS11_FRAME_OK 0x00000002
+#define AR_RXS11_CRC_ERR 0x00000004
+#define AR_RXS11_DECRYPT_CRC_ERR 0x00000008
+#define AR_RXS11_PHY_ERR 0x00000010
+#define AR_RXS11_PHY_ERR_CODE_M 0x0000ff00
+#define AR_RXS11_PHY_ERR_CODE_S 8
+#define AR_RXS11_MICHAEL_ERR 0x00000020
+
+/*
+ * AR9003 family common ROM structures.
+ */
+#define AR_EEP_COMPRESS_NONE 0
+#define AR_EEP_COMPRESS_LZMA 1
+#define AR_EEP_COMPRESS_PAIRS 2
+#define AR_EEP_COMPRESS_BLOCK 3
+
+struct ar_cal_target_power_leg {
+ uint8_t tPow2x[4];
+} __packed;
+
+struct ar_cal_target_power_ht {
+ uint8_t tPow2x[14];
+} __packed;
+
+#endif /* _ARN9003REG_H_ */
diff --git a/sys/dev/ic/arn9280.c b/sys/dev/ic/arn9280.c
new file mode 100644
index 00000000000..e1bf7b1b535
--- /dev/null
+++ b/sys/dev/ic/arn9280.c
@@ -0,0 +1,627 @@
+/* $NetBSD: arn9280.c,v 1.1 2013/03/30 02:53:01 christos Exp $ */
+/* $OpenBSD: ar9280.c,v 1.18 2012/06/10 21:23:36 kettenis Exp $ */
+
+/*-
+ * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr>
+ * Copyright (c) 2008-2009 Atheros Communications Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+/*
+ * Driver for Atheros 802.11a/g/n chipsets.
+ * Routines for AR9220, AR9223, AR9280 and AR9281 chipsets.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: arn9280.c,v 1.1 2013/03/30 02:53:01 christos Exp $");
+
+#include <sys/param.h>
+#include <sys/sockio.h>
+#include <sys/mbuf.h>
+#include <sys/kernel.h>
+#include <sys/socket.h>
+#include <sys/systm.h>
+#include <sys/malloc.h>
+#include <sys/queue.h>
+#include <sys/callout.h>
+#include <sys/conf.h>
+#include <sys/device.h>
+
+#include <sys/bus.h>
+#include <sys/endian.h>
+#include <sys/intr.h>
+
+#include <net/bpf.h>
+#include <net/if.h>
+#include <net/if_arp.h>
+#include <net/if_dl.h>
+#include <net/if_media.h>
+#include <net/if_types.h>
+
+#include <netinet/in.h>
+#include <netinet/in_systm.h>
+#include <netinet/in_var.h>
+#include <netinet/ip.h>
+
+#include <net80211/ieee80211_var.h>
+#include <net80211/ieee80211_amrr.h>
+#include <net80211/ieee80211_radiotap.h>
+
+#include <dev/ic/athnreg.h>
+#include <dev/ic/athnvar.h>
+
+#include <dev/ic/arn5008reg.h>
+#include <dev/ic/arn5008.h>
+#include <dev/ic/arn5416reg.h> /* We share the ROM layout. */
+#include <dev/ic/arn5416.h> /* We share the ROM layout. */
+#include <dev/ic/arn9280reg.h>
+#include <dev/ic/arn9280.h>
+
+#define Static static
+
+Static void ar9280_init_from_rom(struct athn_softc *,
+ struct ieee80211_channel *, struct ieee80211_channel *);
+Static void ar9280_olpc_init(struct athn_softc *);
+Static void ar9280_olpc_temp_compensation(struct athn_softc *);
+Static void ar9280_setup(struct athn_softc *);
+
+PUBLIC int
+ar9280_attach(struct athn_softc *sc)
+{
+
+ sc->sc_eep_base = AR5416_EEP_START_LOC;
+ sc->sc_eep_size = sizeof(struct ar5416_eeprom);
+ sc->sc_def_nf = AR9280_PHY_CCA_MAX_GOOD_VALUE;
+ sc->sc_ngpiopins = (sc->sc_flags & ATHN_FLAG_USB) ? 16 : 10;
+ sc->sc_led_pin = 1;
+ sc->sc_workaround = AR9280_WA_DEFAULT;
+ sc->sc_ops.setup = ar9280_setup;
+ sc->sc_ops.swap_rom = ar5416_swap_rom;
+ sc->sc_ops.init_from_rom = ar9280_init_from_rom;
+ sc->sc_ops.set_txpower = ar5416_set_txpower;
+ sc->sc_ops.set_synth = ar9280_set_synth;
+ sc->sc_ops.spur_mitigate = ar9280_spur_mitigate;
+ sc->sc_ops.get_spur_chans = ar5416_get_spur_chans;
+ sc->sc_ops.olpc_init = ar9280_olpc_init;
+ sc->sc_ops.olpc_temp_compensation = ar9280_olpc_temp_compensation;
+ sc->sc_ini = &ar9280_2_0_ini;
+ sc->sc_serdes = &ar9280_2_0_serdes;
+
+ return ar5008_attach(sc);
+}
+
+Static void
+ar9280_setup(struct athn_softc *sc)
+{
+ const struct ar5416_eeprom *eep = sc->sc_eep;
+ uint8_t type;
+
+ /* Determine if open loop power control should be used. */
+ if (sc->sc_eep_rev >= AR_EEP_MINOR_VER_19 &&
+ eep->baseEepHeader.openLoopPwrCntl)
+ sc->sc_flags |= ATHN_FLAG_OLPC;
+
+ /* Determine if fast PLL clock is supported. */
+ if (AR_SREV_9280_20(sc) &&
+ (sc->sc_eep_rev <= AR_EEP_MINOR_VER_16 ||
+ eep->baseEepHeader.fastClk5g))
+ sc->sc_flags |= ATHN_FLAG_FAST_PLL_CLOCK;
+
+ /*
+ * Determine if initialization value for AR_AN_TOP2 must be fixed.
+ * This is required for some AR9220 devices such as Ubiquiti SR71-12.
+ */
+ if (AR_SREV_9280_20(sc) &&
+ sc->sc_eep_rev > AR_EEP_MINOR_VER_10 &&
+ !eep->baseEepHeader.pwdclkind) {
+ DPRINTFN(DBG_INIT, sc, "AR_AN_TOP2 fixup required\n");
+ sc->sc_flags |= ATHN_FLAG_AN_TOP2_FIXUP;
+ }
+
+ if (AR_SREV_9280_20(sc)) {
+ /* Check if we have a valid rxGainType field in ROM. */
+ if (sc->sc_eep_rev >= AR_EEP_MINOR_VER_17) {
+ /* Select initialization values based on ROM. */
+ type = eep->baseEepHeader.rxGainType;
+ DPRINTFN(DBG_INIT, sc, "Rx gain type=0x%x\n", type);
+ if (type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
+ sc->sc_rx_gain = &ar9280_2_0_rx_gain_23db_backoff;
+ else if (type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
+ sc->sc_rx_gain = &ar9280_2_0_rx_gain_13db_backoff;
+ else
+ sc->sc_rx_gain = &ar9280_2_0_rx_gain;
+ }
+ else
+ sc->sc_rx_gain = &ar9280_2_0_rx_gain;
+
+ /* Check if we have a valid txGainType field in ROM. */
+ if (sc->sc_eep_rev >= AR_EEP_MINOR_VER_19) {
+ /* Select initialization values based on ROM. */
+ type = eep->baseEepHeader.txGainType;
+ DPRINTFN(DBG_INIT, sc, "Tx gain type=0x%x\n", type);
+ if (type == AR_EEP_TXGAIN_HIGH_POWER)
+ sc->sc_tx_gain = &ar9280_2_0_tx_gain_high_power;
+ else
+ sc->sc_tx_gain = &ar9280_2_0_tx_gain;
+ }
+ else
+ sc->sc_tx_gain = &ar9280_2_0_tx_gain;
+ }
+}
+
+PUBLIC int
+ar9280_set_synth(struct athn_softc *sc, struct ieee80211_channel *c,
+ struct ieee80211_channel *extc)
+{
+ uint32_t phy, reg, ndiv = 0;
+ uint32_t freq = c->ic_freq;
+
+ phy = AR_READ(sc, AR9280_PHY_SYNTH_CONTROL) & ~0x3fffffff;
+
+ if (IEEE80211_IS_CHAN_2GHZ(c)) {
+ phy |= (freq << 16) / 15;
+ phy |= AR9280_BMODE | AR9280_FRACMODE;
+
+ if (AR_SREV_9287_11_OR_LATER(sc)) {
+ /* NB: Magic values from the Linux driver. */
+ if (freq == 2484) { /* Channel 14. */
+ /* Japanese regulatory requirements. */
+ AR_WRITE(sc, AR_PHY(637), 0x00000000);
+ AR_WRITE(sc, AR_PHY(638), 0xefff0301);
+ AR_WRITE(sc, AR_PHY(639), 0xca9228ee);
+ }
+ else {
+ AR_WRITE(sc, AR_PHY(637), 0x00fffeff);
+ AR_WRITE(sc, AR_PHY(638), 0x00f5f9ff);
+ AR_WRITE(sc, AR_PHY(639), 0xb79f6427);
+ }
+ }
+ else {
+ reg = AR_READ(sc, AR_PHY_CCK_TX_CTRL);
+ if (freq == 2484) /* Channel 14. */
+ reg |= AR_PHY_CCK_TX_CTRL_JAPAN;
+ else
+ reg &= ~AR_PHY_CCK_TX_CTRL_JAPAN;
+ AR_WRITE(sc, AR_PHY_CCK_TX_CTRL, reg);
+ }
+ }
+ else {
+ if (AR_SREV_9285_10_OR_LATER(sc) ||
+ sc->sc_eep_rev < AR_EEP_MINOR_VER_22 ||
+ !((struct ar5416_base_eep_header *)sc->sc_eep)->frac_n_5g) {
+ if ((freq % 20) == 0) {
+ ndiv = (freq * 3) / 60;
+ phy |= SM(AR9280_AMODE_REFSEL, 3);
+ }
+ else if ((freq % 10) == 0) {
+ ndiv = (freq * 6) / 60;
+ phy |= SM(AR9280_AMODE_REFSEL, 2);
+ }
+ }
+ if (ndiv != 0) {
+ phy |= (ndiv & 0x1ff) << 17;
+ phy |= (ndiv & ~0x1ff) * 2;
+ }
+ else {
+ phy |= (freq << 15) / 15;
+ phy |= AR9280_FRACMODE;
+
+ reg = AR_READ(sc, AR_AN_SYNTH9);
+ reg = RW(reg, AR_AN_SYNTH9_REFDIVA, 1);
+ AR_WRITE(sc, AR_AN_SYNTH9, reg);
+ }
+ }
+ AR_WRITE_BARRIER(sc);
+ DPRINTFN(DBG_RF, sc, "AR9280_PHY_SYNTH_CONTROL=0x%08x\n", phy);
+ AR_WRITE(sc, AR9280_PHY_SYNTH_CONTROL, phy);
+ AR_WRITE_BARRIER(sc);
+ return 0;
+}
+
+Static void
+ar9280_init_from_rom(struct athn_softc *sc, struct ieee80211_channel *c,
+ struct ieee80211_channel *extc)
+{
+ static const uint32_t chainoffset[] = { 0x0000, 0x2000, 0x1000 };
+ const struct ar5416_eeprom *eep = sc->sc_eep;
+ const struct ar5416_modal_eep_header *modal;
+ uint32_t reg, offset;
+ uint8_t txRxAtten;
+ int i;
+
+ modal = &eep->modalHeader[IEEE80211_IS_CHAN_2GHZ(c)];
+
+ AR_WRITE(sc, AR_PHY_SWITCH_COM, modal->antCtrlCommon);
+
+ for (i = 0; i < AR9280_MAX_CHAINS; i++) {
+ if (sc->sc_rxchainmask == 0x5 || sc->sc_txchainmask == 0x5)
+ offset = chainoffset[i];
+ else
+ offset = i * 0x1000;
+
+ AR_WRITE(sc, AR_PHY_SWITCH_CHAIN_0 + offset,
+ modal->antCtrlChain[i]);
+
+ reg = AR_READ(sc, AR_PHY_TIMING_CTRL4_0 + offset);
+ reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF,
+ modal->iqCalICh[i]);
+ reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF,
+ modal->iqCalQCh[i]);
+ AR_WRITE(sc, AR_PHY_TIMING_CTRL4_0 + offset, reg);
+
+ if (sc->sc_eep_rev >= AR_EEP_MINOR_VER_3) {
+ reg = AR_READ(sc, AR_PHY_GAIN_2GHZ + offset);
+ reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
+ modal->bswMargin[i]);
+ reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_DB,
+ modal->bswAtten[i]);
+ reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
+ modal->xatten2Margin[i]);
+ reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_DB,
+ modal->xatten2Db[i]);
+ AR_WRITE(sc, AR_PHY_GAIN_2GHZ + offset, reg);
+ }
+ if (sc->sc_eep_rev >= AR_EEP_MINOR_VER_3)
+ txRxAtten = modal->txRxAttenCh[i];
+ else /* Workaround for ROM versions < 14.3. */
+ txRxAtten = IEEE80211_IS_CHAN_2GHZ(c) ? 23 : 44;
+ reg = AR_READ(sc, AR_PHY_RXGAIN + offset);
+ reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_ATTEN,
+ txRxAtten);
+ reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_MARGIN,
+ modal->rxTxMarginCh[i]);
+ AR_WRITE(sc, AR_PHY_RXGAIN + offset, reg);
+ }
+ if (IEEE80211_IS_CHAN_2GHZ(c)) {
+ reg = AR_READ(sc, AR_AN_RF2G1_CH0);
+ reg = RW(reg, AR_AN_RF2G1_CH0_OB, modal->ob);
+ reg = RW(reg, AR_AN_RF2G1_CH0_DB, modal->db);
+ AR_WRITE(sc, AR_AN_RF2G1_CH0, reg);
+ AR_WRITE_BARRIER(sc);
+ DELAY(100);
+
+ reg = AR_READ(sc, AR_AN_RF2G1_CH1);
+ reg = RW(reg, AR_AN_RF2G1_CH1_OB, modal->ob_ch1);
+ reg = RW(reg, AR_AN_RF2G1_CH1_DB, modal->db_ch1);
+ AR_WRITE(sc, AR_AN_RF2G1_CH1, reg);
+ AR_WRITE_BARRIER(sc);
+ DELAY(100);
+ }
+ else {
+ reg = AR_READ(sc, AR_AN_RF5G1_CH0);
+ reg = RW(reg, AR_AN_RF5G1_CH0_OB5, modal->ob);
+ reg = RW(reg, AR_AN_RF5G1_CH0_DB5, modal->db);
+ AR_WRITE(sc, AR_AN_RF5G1_CH0, reg);
+ AR_WRITE_BARRIER(sc);
+ DELAY(100);
+
+ reg = AR_READ(sc, AR_AN_RF5G1_CH1);
+ reg = RW(reg, AR_AN_RF5G1_CH1_OB5, modal->ob_ch1);
+ reg = RW(reg, AR_AN_RF5G1_CH1_DB5, modal->db_ch1);
+ AR_WRITE(sc, AR_AN_RF5G1_CH1, reg);
+ AR_WRITE_BARRIER(sc);
+ DELAY(100);
+ }
+ reg = AR_READ(sc, AR_AN_TOP2);
+ if ((sc->sc_flags & ATHN_FLAG_USB) && IEEE80211_IS_CHAN_5GHZ(c)) {
+ /*
+ * Hardcode the output voltage of x-PA bias LDO to the
+ * lowest value for UB94 such that the card doesn't get
+ * too hot.
+ */
+ reg = RW(reg, AR_AN_TOP2_XPABIAS_LVL, 0);
+ }
+ else
+ reg = RW(reg, AR_AN_TOP2_XPABIAS_LVL, modal->xpaBiasLvl);
+ if (modal->flagBits & AR5416_EEP_FLAG_LOCALBIAS)
+ reg |= AR_AN_TOP2_LOCALBIAS;
+ else
+ reg &= ~AR_AN_TOP2_LOCALBIAS;
+ AR_WRITE(sc, AR_AN_TOP2, reg);
+ AR_WRITE_BARRIER(sc);
+ DELAY(100);
+
+ reg = AR_READ(sc, AR_PHY_XPA_CFG);
+ if (modal->flagBits & AR5416_EEP_FLAG_FORCEXPAON)
+ reg |= AR_PHY_FORCE_XPA_CFG;
+ else
+ reg &= ~AR_PHY_FORCE_XPA_CFG;
+ AR_WRITE(sc, AR_PHY_XPA_CFG, reg);
+
+ reg = AR_READ(sc, AR_PHY_SETTLING);
+ reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->switchSettling);
+ AR_WRITE(sc, AR_PHY_SETTLING, reg);
+
+ reg = AR_READ(sc, AR_PHY_DESIRED_SZ);
+ reg = RW(reg, AR_PHY_DESIRED_SZ_ADC, modal->adcDesiredSize);
+ AR_WRITE(sc, AR_PHY_DESIRED_SZ, reg);
+
+ reg = SM(AR_PHY_RF_CTL4_TX_END_XPAA_OFF, modal->txEndToXpaOff);
+ reg |= SM(AR_PHY_RF_CTL4_TX_END_XPAB_OFF, modal->txEndToXpaOff);
+ reg |= SM(AR_PHY_RF_CTL4_FRAME_XPAA_ON, modal->txFrameToXpaOn);
+ reg |= SM(AR_PHY_RF_CTL4_FRAME_XPAB_ON, modal->txFrameToXpaOn);
+ AR_WRITE(sc, AR_PHY_RF_CTL4, reg);
+
+ reg = AR_READ(sc, AR_PHY_RF_CTL3);
+ reg = RW(reg, AR_PHY_TX_END_TO_A2_RX_ON, modal->txEndToRxOn);
+ AR_WRITE(sc, AR_PHY_RF_CTL3, reg);
+
+ reg = AR_READ(sc, AR_PHY_CCA(0));
+ reg = RW(reg, AR9280_PHY_CCA_THRESH62, modal->thresh62);
+ AR_WRITE(sc, AR_PHY_CCA(0), reg);
+
+ reg = AR_READ(sc, AR_PHY_EXT_CCA0);
+ reg = RW(reg, AR_PHY_EXT_CCA0_THRESH62, modal->thresh62);
+ AR_WRITE(sc, AR_PHY_EXT_CCA0, reg);
+
+ if (sc->sc_eep_rev >= AR_EEP_MINOR_VER_2) {
+ reg = AR_READ(sc, AR_PHY_RF_CTL2);
+ reg = RW(reg, AR_PHY_TX_END_DATA_START,
+ modal->txFrameToDataStart);
+ reg = RW(reg, AR_PHY_TX_END_PA_ON, modal->txFrameToPaOn);
+ AR_WRITE(sc, AR_PHY_RF_CTL2, reg);
+ }
+#ifndef IEEE80211_NO_HT
+ if (sc->sc_eep_rev >= AR_EEP_MINOR_VER_3 && extc != NULL) {
+ /* Overwrite switch settling with HT-40 value. */
+ reg = AR_READ(sc, AR_PHY_SETTLING);
+ reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->swSettleHt40);
+ AR_WRITE(sc, AR_PHY_SETTLING, reg);
+ }
+#endif
+ if (sc->sc_eep_rev >= AR_EEP_MINOR_VER_19) {
+ reg = AR_READ(sc, AR_PHY_CCK_TX_CTRL);
+ reg = RW(reg, AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK,
+ MS(modal->miscBits, AR5416_EEP_MISC_TX_DAC_SCALE_CCK));
+ AR_WRITE(sc, AR_PHY_CCK_TX_CTRL, reg);
+ }
+ if (AR_SREV_9280_20(sc) &&
+ sc->sc_eep_rev >= AR_EEP_MINOR_VER_20) {
+ reg = AR_READ(sc, AR_AN_TOP1);
+ if (eep->baseEepHeader.dacLpMode &&
+ (IEEE80211_IS_CHAN_2GHZ(c) ||
+ !eep->baseEepHeader.dacHiPwrMode_5G))
+ reg |= AR_AN_TOP1_DACLPMODE;
+ else
+ reg &= ~AR_AN_TOP1_DACLPMODE;
+ AR_WRITE(sc, AR_AN_TOP1, reg);
+ AR_WRITE_BARRIER(sc);
+ DELAY(100);
+
+ reg = AR_READ(sc, AR_PHY_FRAME_CTL);
+ reg = RW(reg, AR_PHY_FRAME_CTL_TX_CLIP,
+ MS(modal->miscBits, AR5416_EEP_MISC_TX_CLIP));
+ AR_WRITE(sc, AR_PHY_FRAME_CTL, reg);
+
+ reg = AR_READ(sc, AR_PHY_TX_PWRCTRL9);
+ reg = RW(reg, AR_PHY_TX_DESIRED_SCALE_CCK,
+ eep->baseEepHeader.desiredScaleCCK);
+ AR_WRITE(sc, AR_PHY_TX_PWRCTRL9, reg);
+ }
+ AR_WRITE_BARRIER(sc);
+}
+
+PUBLIC void
+ar9280_olpc_get_pdadcs(struct athn_softc *sc, struct ieee80211_channel *c,
+ int chain, uint8_t *boundaries, uint8_t *pdadcs, uint8_t *txgain)
+{
+ const struct ar5416_eeprom *eep = sc->sc_eep;
+ const struct ar_cal_data_per_freq_olpc *pierdata;
+ const uint8_t *pierfreq;
+ uint8_t fbin, pcdac, pwr, idx;
+ int i, lo, hi, npiers;
+
+ if (IEEE80211_IS_CHAN_2GHZ(c)) {
+ pierfreq = eep->calFreqPier2G;
+ pierdata = (const struct ar_cal_data_per_freq_olpc *)
+ eep->calPierData2G[chain];
+ npiers = AR5416_NUM_2G_CAL_PIERS;
+ }
+ else {
+ pierfreq = eep->calFreqPier5G;
+ pierdata = (const struct ar_cal_data_per_freq_olpc *)
+ eep->calPierData5G[chain];
+ npiers = AR5416_NUM_5G_CAL_PIERS;
+ }
+ /* Find channel in ROM pier table. */
+ fbin = athn_chan2fbin(c);
+ athn_get_pier_ival(fbin, pierfreq, npiers, &lo, &hi);
+
+ /* Get average. */
+ pwr = (pierdata[lo].pwrPdg[0][0] + pierdata[hi].pwrPdg[0][0]) / 2;
+ pwr /= 2; /* Convert to dB. */
+
+ /* Find power control digital-to-analog converter (PCDAC) value. */
+ pcdac = pierdata[hi].pcdac[0][0];
+ for (idx = 0; idx < AR9280_TX_GAIN_TABLE_SIZE - 1; idx++)
+ if (pcdac <= sc->sc_tx_gain_tbl[idx])
+ break;
+ *txgain = idx;
+
+ DPRINTFN(DBG_RF, sc,
+ "fbin=%d lo=%d hi=%d pwr=%d pcdac=%d txgain=%d\n",
+ fbin, lo, hi, pwr, pcdac, idx);
+
+ /* Fill phase domain analog-to-digital converter (PDADC) table. */
+ for (i = 0; i < AR_NUM_PDADC_VALUES; i++)
+ pdadcs[i] = (i < pwr) ? 0x00 : 0xff;
+
+ for (i = 0; i < AR_PD_GAINS_IN_MASK; i++)
+ boundaries[i] = AR9280_PD_GAIN_BOUNDARY_DEFAULT;
+}
+
+PUBLIC void
+ar9280_spur_mitigate(struct athn_softc *sc, struct ieee80211_channel *c,
+ struct ieee80211_channel *extc)
+{
+ const struct ar_spur_chan *spurchans;
+ int spur, bin, spur_delta_phase, spur_freq_sd, spur_subchannel_sd;
+ int spur_off, range, i;
+
+ /* NB: Always clear. */
+ AR_CLRBITS(sc, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
+
+ range = (extc != NULL) ? 19 : 10;
+
+ spurchans = sc->sc_ops.get_spur_chans(sc, IEEE80211_IS_CHAN_2GHZ(c));
+ for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
+ spur = spurchans[i].spurChan;
+ if (spur == AR_NO_SPUR)
+ return; /* XXX disable if it was enabled! */
+ spur /= 10;
+ if (IEEE80211_IS_CHAN_2GHZ(c))
+ spur += AR_BASE_FREQ_2GHZ;
+ else
+ spur += AR_BASE_FREQ_5GHZ;
+ spur -= c->ic_freq;
+ if (abs(spur) < range)
+ break;
+ }
+ if (i == AR_EEPROM_MODAL_SPURS)
+ return; /* XXX disable if it was enabled! */
+ DPRINTFN(DBG_RF, sc, "enabling spur mitigation\n");
+
+ AR_SETBITS(sc, AR_PHY_TIMING_CTRL4_0,
+ AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
+ AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
+ AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
+ AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
+
+ AR_WRITE(sc, AR_PHY_SPUR_REG,
+ AR_PHY_SPUR_REG_MASK_RATE_CNTL |
+ AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
+ AR_PHY_SPUR_REG_MASK_RATE_SELECT |
+ AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
+ SM(AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, AR_SPUR_RSSI_THRESH));
+
+#ifndef IEEE80211_NO_HT
+ if (extc != NULL) {
+ spur_delta_phase = (spur * 262144) / 10;
+ if (spur < 0) {
+ spur_subchannel_sd = 1;
+ spur_off = spur + 10;
+ }
+ else {
+ spur_subchannel_sd = 0;
+ spur_off = spur - 10;
+ }
+ }
+ else
+#endif
+ {
+ spur_delta_phase = (spur * 524288) / 10;
+ spur_subchannel_sd = 0;
+ spur_off = spur;
+ }
+ if (IEEE80211_IS_CHAN_2GHZ(c))
+ spur_freq_sd = (spur_off * 2048) / 44;
+ else
+ spur_freq_sd = (spur_off * 2048) / 40;
+
+ AR_WRITE(sc, AR_PHY_TIMING11,
+ AR_PHY_TIMING11_USE_SPUR_IN_AGC |
+ SM(AR_PHY_TIMING11_SPUR_FREQ_SD, spur_freq_sd) |
+ SM(AR_PHY_TIMING11_SPUR_DELTA_PHASE, spur_delta_phase));
+
+ AR_WRITE(sc, AR_PHY_SFCORR_EXT,
+ SM(AR_PHY_SFCORR_SPUR_SUBCHNL_SD, spur_subchannel_sd));
+ AR_WRITE_BARRIER(sc);
+
+ bin = spur * 320;
+ ar5008_set_viterbi_mask(sc, bin);
+}
+
+PUBLIC void
+ar9280_reset_rx_gain(struct athn_softc *sc, struct ieee80211_channel *c)
+{
+ const struct athn_gain *prog = sc->sc_rx_gain;
+ const uint32_t *pvals;
+ int i;
+
+ if (IEEE80211_IS_CHAN_2GHZ(c))
+ pvals = prog->vals_2g;
+ else
+ pvals = prog->vals_5g;
+ for (i = 0; i < prog->nregs; i++)
+ AR_WRITE(sc, prog->regs[i], pvals[i]);
+}
+
+PUBLIC void
+ar9280_reset_tx_gain(struct athn_softc *sc, struct ieee80211_channel *c)
+{
+ const struct athn_gain *prog = sc->sc_tx_gain;
+ const uint32_t *pvals;
+ int i;
+
+ if (IEEE80211_IS_CHAN_2GHZ(c))
+ pvals = prog->vals_2g;
+ else
+ pvals = prog->vals_5g;
+ for (i = 0; i < prog->nregs; i++)
+ AR_WRITE(sc, prog->regs[i], pvals[i]);
+}
+
+Static void
+ar9280_olpc_init(struct athn_softc *sc)
+{
+ uint32_t reg;
+ int i;
+
+ /* Save original Tx gain values. */
+ for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++) {
+ reg = AR_READ(sc, AR_PHY_TX_GAIN_TBL(i));
+ sc->sc_tx_gain_tbl[i] = MS(reg, AR_PHY_TX_GAIN);
+ }
+ /* Initial Tx gain temperature compensation. */
+ sc->sc_tcomp = 0;
+}
+
+Static void
+ar9280_olpc_temp_compensation(struct athn_softc *sc)
+{
+ const struct ar5416_eeprom *eep = sc->sc_eep;
+ int8_t pdadc, txgain, tcomp;
+ uint32_t reg;
+ int i;
+
+ reg = AR_READ(sc, AR_PHY_TX_PWRCTRL4);
+ pdadc = MS(reg, AR_PHY_TX_PWRCTRL_PD_AVG_OUT);
+ DPRINTFN(DBG_RF, sc, "PD Avg Out=%d\n", pdadc);
+
+ if (sc->sc_pdadc == 0 || pdadc == 0)
+ return; /* No frames transmitted yet. */
+
+ /* Compute Tx gain temperature compensation. */
+ if (sc->sc_eep_rev >= AR_EEP_MINOR_VER_20 &&
+ eep->baseEepHeader.dacHiPwrMode_5G)
+ tcomp = (pdadc - sc->sc_pdadc + 4) / 8;
+ else
+ tcomp = (pdadc - sc->sc_pdadc + 5) / 10;
+ DPRINTFN(DBG_RF, sc, "OLPC temp compensation=%d\n", tcomp);
+
+ if (tcomp == sc->sc_tcomp)
+ return; /* Don't rewrite the same values. */
+ sc->sc_tcomp = tcomp;
+
+ /* Adjust Tx gain values. */
+ for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++) {
+ txgain = sc->sc_tx_gain_tbl[i] - tcomp;
+ if (txgain < 0)
+ txgain = 0;
+ reg = AR_READ(sc, AR_PHY_TX_GAIN_TBL(i));
+ reg = RW(reg, AR_PHY_TX_GAIN, txgain);
+ AR_WRITE(sc, AR_PHY_TX_GAIN_TBL(i), reg);
+ }
+ AR_WRITE_BARRIER(sc);
+}
diff --git a/sys/dev/ic/arn9280.h b/sys/dev/ic/arn9280.h
new file mode 100644
index 00000000000..cba0aecfd3a
--- /dev/null
+++ b/sys/dev/ic/arn9280.h
@@ -0,0 +1,42 @@
+/* $NetBSD: arn9280.h,v 1.1 2013/03/30 02:53:01 christos Exp $ */
+/*
+ * Copyright (c) 2001, 2004 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _IF_ARN9280_H_
+#define _IF_ARN9280_H_
+
+int ar9280_attach(struct athn_softc *);
+void ar9280_reset_rx_gain(struct athn_softc *, struct ieee80211_channel *);
+void ar9280_reset_tx_gain(struct athn_softc *, struct ieee80211_channel *);
+void ar9280_olpc_get_pdadcs(struct athn_softc *, struct ieee80211_channel *,
+ int, uint8_t *, uint8_t *, uint8_t *);
+
+int ar9280_set_synth(struct athn_softc *, struct ieee80211_channel *,
+ struct ieee80211_channel *);
+void ar9280_spur_mitigate(struct athn_softc *, struct ieee80211_channel *,
+ struct ieee80211_channel *);
+
+#endif /* _IF_ARN9280_H_ */
diff --git a/sys/dev/ic/arn9280reg.h b/sys/dev/ic/arn9280reg.h
new file mode 100644
index 00000000000..fc635bcd74e
--- /dev/null
+++ b/sys/dev/ic/arn9280reg.h
@@ -0,0 +1,630 @@
+/* $NetBSD: arn9280reg.h,v 1.1 2013/03/30 02:53:01 christos Exp $ */
+/* $OpenBSD: ar9280reg.h,v 1.6 2012/10/20 09:54:20 stsp Exp $ */
+
+/*-
+ * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr>
+ * Copyright (c) 2008-2009 Atheros Communications Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _ARN9280REG_H_
+#define _ARN9280REG_H_
+
+#define AR9280_MAX_CHAINS 2
+
+#define AR9280_PD_GAIN_BOUNDARY_DEFAULT 56
+#define AR9280_PHY_CCA_MAX_GOOD_VALUE (-112)
+
+#define AR9280_PHY_SYNTH_CONTROL 0x9874
+
+/* Bits for AR9280_PHY_SYNTH_CONTROL. */
+#define AR9280_BMODE 0x20000000
+#define AR9280_FRACMODE 0x10000000
+#define AR9280_AMODE_REFSEL_M 0x0c000000
+#define AR9280_AMODE_REFSEL_S 26
+
+/*
+ * NB: The AR9280 uses the same ROM layout than the AR5416.
+ */
+
+/* Macro to "pack" registers to 16-bit to save some .rodata space. */
+#define P(x) (x)
+
+/*
+ * AR9280 2.0 initialization values.
+ */
+static const uint16_t ar9280_2_0_regs[] = {
+ P(0x01030), P(0x01070), P(0x010b0), P(0x010f0), P(0x08014),
+ P(0x0801c), P(0x08120), P(0x081d0), P(0x08318), P(0x09804),
+ P(0x09820), P(0x09824), P(0x09828), P(0x09834), P(0x09838),
+ P(0x09840), P(0x09844), P(0x09850), P(0x09858), P(0x0985c),
+ P(0x09860), P(0x09864), P(0x09868), P(0x0986c), P(0x09914),
+ P(0x09918), P(0x09924), P(0x09944), P(0x09960), P(0x0a960),
+ P(0x09964), P(0x0c968), P(0x099b8), P(0x099bc), P(0x099c0),
+ P(0x0a204), P(0x0a20c), P(0x0b20c), P(0x0a21c), P(0x0a230),
+ P(0x0a23c), P(0x0a250), P(0x0a358), P(0x0a388), P(0x0a3d8),
+ P(0x07894)
+};
+
+static const uint32_t ar9280_2_0_vals_5g20[] = {
+ 0x00000230, 0x00000168, 0x00000e60, 0x00000000, 0x03e803e8,
+ 0x128d8027, 0x08f04800, 0x00003210, 0x00003e80, 0x00000300,
+ 0x02020200, 0x01000e0e, 0x0a020001, 0x00000e0e, 0x00000007,
+ 0x206a022e, 0x0372161e, 0x6c4000e2, 0x7ec88d2e, 0x31395d5e,
+ 0x00048d18, 0x0001ce00, 0x5ac640d0, 0x06903081, 0x000007d0,
+ 0x0000000a, 0xd00a8a0b, 0xffbc1010, 0x00000010, 0x00000010,
+ 0x00000210, 0x000003b5, 0x0000001c, 0x00000a00, 0x05eea6d4,
+ 0x00000444, 0x00000014, 0x00000014, 0x1883800a, 0x00000000,
+ 0x13c88000, 0x001ff000, 0x7999aa02, 0x0c000000, 0x00000000,
+ 0x5a508000
+};
+
+#ifndef IEEE80211_NO_HT
+static const uint32_t ar9280_2_0_vals_5g40[] = {
+ 0x00000460, 0x000002d0, 0x00001cc0, 0x00000000, 0x07d007d0,
+ 0x128d804f, 0x08f04800, 0x00003210, 0x00007d00, 0x000003c4,
+ 0x02020200, 0x01000e0e, 0x0a020001, 0x00000e0e, 0x00000007,
+ 0x206a022e, 0x0372161e, 0x6d4000e2, 0x7ec88d2e, 0x3139605e,
+ 0x00048d18, 0x0001ce00, 0x5ac640d0, 0x06903081, 0x00000fa0,
+ 0x00000014, 0xd00a8a0b, 0xffbc1010, 0x00000010, 0x00000010,
+ 0x00000210, 0x000003b5, 0x0000001c, 0x00000a00, 0x05eea6d4,
+ 0x00000444, 0x00000014, 0x00000014, 0x1883800a, 0x00000000,
+ 0x13c88000, 0x001ff000, 0x7999aa02, 0x0c000000, 0x00000000,
+ 0x5a508000
+};
+
+static const uint32_t ar9280_2_0_vals_2g40[] = {
+ 0x000002c0, 0x00000318, 0x00007c70, 0x00000000, 0x10801600,
+ 0x12e00057, 0x08f04810, 0x0000320a, 0x00006880, 0x000003c4,
+ 0x02020200, 0x01000e0e, 0x0a020001, 0x00000e0e, 0x00000007,
+ 0x206a012e, 0x037216a0, 0x6d4000e2, 0x7ec84d2e, 0x3139605e,
+ 0x00048d20, 0x0001ce00, 0x5ac640d0, 0x06903881, 0x00001130,
+ 0x00000268, 0xd00a8a0d, 0xffbc1010, 0x00000010, 0x00000010,
+ 0x00000210, 0x000003ce, 0x0000001c, 0x00000c00, 0x05eea6d4,
+ 0x00000444, 0x0001f019, 0x0001f019, 0x1883800a, 0x00000210,
+ 0x13c88001, 0x0004a000, 0x7999aa0e, 0x08000000, 0x00000000,
+ 0x5a508000
+};
+#endif
+
+static const uint32_t ar9280_2_0_vals_2g20[] = {
+ 0x00000160, 0x0000018c, 0x00003e38, 0x00000000, 0x08400b00,
+ 0x12e0002b, 0x08f04810, 0x0000320a, 0x00003440, 0x00000300,
+ 0x02020200, 0x01000e0e, 0x0a020001, 0x00000e0e, 0x00000007,
+ 0x206a012e, 0x037216a0, 0x6c4000e2, 0x7ec84d2e, 0x31395d5e,
+ 0x00048d20, 0x0001ce00, 0x5ac640d0, 0x06903881, 0x00000898,
+ 0x0000000b, 0xd00a8a0d, 0xffbc1010, 0x00000010, 0x00000010,
+ 0x00000210, 0x000003ce, 0x0000001c, 0x00000c00, 0x05eea6d4,
+ 0x00000444, 0x0001f019, 0x0001f019, 0x1883800a, 0x00000108,
+ 0x13c88000, 0x0004a000, 0x7999aa0e, 0x0c000000, 0x00000000,
+ 0x5a508000
+};
+
+static const uint16_t ar9280_2_0_cm_regs[] = {
+ P(0x0000c), P(0x00030), P(0x00034), P(0x00040), P(0x00044),
+ P(0x00048), P(0x0004c), P(0x00050), P(0x00054), P(0x00800),
+ P(0x00804), P(0x00808), P(0x0080c), P(0x00810), P(0x00814),
+ P(0x00818), P(0x0081c), P(0x00820), P(0x00824), P(0x01040),
+ P(0x01044), P(0x01048), P(0x0104c), P(0x01050), P(0x01054),
+ P(0x01058), P(0x0105c), P(0x01060), P(0x01064), P(0x01230),
+ P(0x01270), P(0x01038), P(0x01078), P(0x010b8), P(0x010f8),
+ P(0x01138), P(0x01178), P(0x011b8), P(0x011f8), P(0x01238),
+ P(0x01278), P(0x012b8), P(0x012f8), P(0x01338), P(0x01378),
+ P(0x013b8), P(0x013f8), P(0x01438), P(0x01478), P(0x014b8),
+ P(0x014f8), P(0x01538), P(0x01578), P(0x015b8), P(0x015f8),
+ P(0x01638), P(0x01678), P(0x016b8), P(0x016f8), P(0x01738),
+ P(0x01778), P(0x017b8), P(0x017f8), P(0x0103c), P(0x0107c),
+ P(0x010bc), P(0x010fc), P(0x0113c), P(0x0117c), P(0x011bc),
+ P(0x011fc), P(0x0123c), P(0x0127c), P(0x012bc), P(0x012fc),
+ P(0x0133c), P(0x0137c), P(0x013bc), P(0x013fc), P(0x0143c),
+ P(0x0147c), P(0x04030), P(0x0403c), P(0x04024), P(0x04060),
+ P(0x04064), P(0x07010), P(0x07034), P(0x07038), P(0x08004),
+ P(0x08008), P(0x0800c), P(0x08018), P(0x08020), P(0x08038),
+ P(0x0803c), P(0x08048), P(0x08054), P(0x08058), P(0x0805c),
+ P(0x08060), P(0x08064), P(0x08070), P(0x080c0), P(0x080c4),
+ P(0x080c8), P(0x080cc), P(0x080d0), P(0x080d4), P(0x080d8),
+ P(0x080e0), P(0x080e4), P(0x080e8), P(0x080ec), P(0x080f0),
+ P(0x080f4), P(0x080f8), P(0x080fc), P(0x08100), P(0x08104),
+ P(0x08108), P(0x0810c), P(0x08110), P(0x08118), P(0x0811c),
+ P(0x08124), P(0x08128), P(0x0812c), P(0x08130), P(0x08134),
+ P(0x08138), P(0x0813c), P(0x08144), P(0x08168), P(0x0816c),
+ P(0x08170), P(0x08174), P(0x08178), P(0x0817c), P(0x081c0),
+ P(0x081ec), P(0x081f0), P(0x081f4), P(0x081f8), P(0x081fc),
+ P(0x08200), P(0x08204), P(0x08208), P(0x0820c), P(0x08210),
+ P(0x08214), P(0x08218), P(0x0821c), P(0x08220), P(0x08224),
+ P(0x08228), P(0x0822c), P(0x08230), P(0x08234), P(0x08238),
+ P(0x0823c), P(0x08240), P(0x08244), P(0x08248), P(0x0824c),
+ P(0x08250), P(0x08254), P(0x08258), P(0x0825c), P(0x08260),
+ P(0x08264), P(0x08270), P(0x08274), P(0x08278), P(0x0827c),
+ P(0x08284), P(0x08288), P(0x0828c), P(0x08294), P(0x08298),
+ P(0x0829c), P(0x08300), P(0x08314), P(0x08328), P(0x0832c),
+ P(0x08330), P(0x08334), P(0x08338), P(0x0833c), P(0x08340),
+ P(0x08344), P(0x09808), P(0x0980c), P(0x09810), P(0x09814),
+ P(0x0981c), P(0x0982c), P(0x09830), P(0x0983c), P(0x0984c),
+ P(0x0a84c), P(0x09854), P(0x09900), P(0x09904), P(0x09908),
+ P(0x0990c), P(0x09910), P(0x0991c), P(0x09920), P(0x0a920),
+ P(0x09928), P(0x0992c), P(0x09934), P(0x09938), P(0x0993c),
+ P(0x09948), P(0x0994c), P(0x09954), P(0x09958), P(0x09940),
+ P(0x0c95c), P(0x09970), P(0x09974), P(0x09978), P(0x0997c),
+ P(0x09980), P(0x09984), P(0x09988), P(0x0998c), P(0x09990),
+ P(0x09994), P(0x09998), P(0x0999c), P(0x099a0), P(0x099a4),
+ P(0x099a8), P(0x099ac), P(0x099b0), P(0x099b4), P(0x099c4),
+ P(0x099c8), P(0x099cc), P(0x099d0), P(0x099d4), P(0x099d8),
+ P(0x099dc), P(0x099e0), P(0x099e4), P(0x099e8), P(0x099ec),
+ P(0x099f0), P(0x099fc), P(0x0a208), P(0x0a210), P(0x0a214),
+ P(0x0a218), P(0x0a220), P(0x0a224), P(0x0a228), P(0x0a22c),
+ P(0x0a234), P(0x0a238), P(0x0a240), P(0x0a244), P(0x0a248),
+ P(0x0a24c), P(0x0a254), P(0x0a258), P(0x0a25c), P(0x0a260),
+ P(0x0a268), P(0x0a26c), P(0x0b26c), P(0x0d270), P(0x0a278),
+ P(0x0d35c), P(0x0d360), P(0x0d364), P(0x0d368), P(0x0d36c),
+ P(0x0d370), P(0x0d374), P(0x0d378), P(0x0d37c), P(0x0d380),
+ P(0x0d384), P(0x0a38c), P(0x0a390), P(0x0a394), P(0x0a398),
+ P(0x0a39c), P(0x0a3a0), P(0x0a3a4), P(0x0a3a8), P(0x0a3ac),
+ P(0x0a3b0), P(0x0a3b4), P(0x0a3b8), P(0x0a3bc), P(0x0a3c0),
+ P(0x0a3c4), P(0x0a3c8), P(0x0a3cc), P(0x0a3d0), P(0x0a3d4),
+ P(0x0a3dc), P(0x0a3e0), P(0x0a3e4), P(0x0a3e8), P(0x07800),
+ P(0x07804), P(0x07808), P(0x0780c), P(0x07810), P(0x07818),
+ P(0x07824), P(0x07828), P(0x0782c), P(0x07830), P(0x07834),
+ P(0x0783c), P(0x07848), P(0x0784c), P(0x07850), P(0x07854),
+ P(0x07858), P(0x07860), P(0x07864), P(0x07868), P(0x0786c),
+ P(0x07870), P(0x07874), P(0x07878), P(0x0787c), P(0x07880),
+ P(0x07884), P(0x07888), P(0x0788c), P(0x07890), P(0x07898)
+};
+
+static const uint32_t ar9280_2_0_cm_vals[] = {
+ 0x00000000, 0x00020015, 0x00000005, 0x00000000, 0x00000008,
+ 0x00000008, 0x00000010, 0x00000000, 0x0000001f, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x002ffc0f,
+ 0x002ffc0f, 0x002ffc0f, 0x002ffc0f, 0x002ffc0f, 0x002ffc0f,
+ 0x002ffc0f, 0x002ffc0f, 0x002ffc0f, 0x002ffc0f, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000002, 0x00000002, 0x0000001f, 0x00000000,
+ 0x00000000, 0x00000033, 0x00000002, 0x000004c2, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000700, 0x00000000, 0x00000000,
+ 0x00000000, 0x40000000, 0x00000000, 0x00000000, 0x000fc78f,
+ 0x0000000f, 0x00000000, 0x00000000, 0x2a80001a, 0x05dc01e0,
+ 0x1f402710, 0x01f40000, 0x00001e00, 0x00000000, 0x00400000,
+ 0xffffffff, 0x0000ffff, 0x003f3f3f, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00020000, 0x00020000, 0x00000001,
+ 0x00000052, 0x00000000, 0x00000168, 0x000100aa, 0x00003210,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0xffffffff, 0x00000000, 0x00000000,
+ 0x32143320, 0xfaa4fa50, 0x00000100, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00100000, 0x0010f400, 0x00000100, 0x0001e800,
+ 0x00000000, 0x00000000, 0x00000000, 0x400000ff, 0x00080922,
+ 0x88a00010, 0x00000000, 0x40000000, 0x003e4180, 0x00000000,
+ 0x0000002c, 0x0000002c, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000040, 0x00000000, 0x00000000, 0x00000007,
+ 0x00000302, 0x00000e00, 0x00ff0000, 0x00000000, 0x000107ff,
+ 0x00481043, 0x00000000, 0xafa68e30, 0xfd14e000, 0x9c0a9f6b,
+ 0x00000000, 0x0000a000, 0x00000000, 0x00200400, 0x0040233c,
+ 0x0040233c, 0x00000044, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x01002310, 0x10000fff, 0x04900000, 0x04900000,
+ 0x00000001, 0x00000004, 0x1e1f2022, 0x0a0b0c0d, 0x00000000,
+ 0x9280c00a, 0x00020028, 0x5f3ca3de, 0x2108ecff, 0x14750604,
+ 0x004b6a8e, 0x190fb514, 0x00000000, 0x00000001, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000001,
+ 0x201fff00, 0x006f0000, 0x03051000, 0x00000820, 0x06336f77,
+ 0x6af6532f, 0x08f186c8, 0x00046384, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0xaaaaaaaa, 0x3c466478, 0x0cc80caa,
+ 0x00000000, 0x00001042, 0x803e4788, 0x4080a333, 0x40206c10,
+ 0x009c4060, 0x01834061, 0x00000400, 0x000003b5, 0x233f7180,
+ 0x20202020, 0x20202020, 0x38490a20, 0x00007bb6, 0x0fff3ffc,
+ 0x00000000, 0x00000000, 0x0cdbd380, 0x0f0f0f01, 0xdfa91f01,
+ 0x00000000, 0x0e79e5c6, 0x0e79e5c6, 0x00820820, 0x1ce739ce,
+ 0x07ffffef, 0x0fffffe7, 0x17ffffe5, 0x1fffffe4, 0x37ffffe3,
+ 0x3fffffe3, 0x57ffffe3, 0x5fffffe2, 0x7fffffe2, 0x7f3c7bba,
+ 0xf3307ff0, 0x20202020, 0x20202020, 0x1ce739ce, 0x000001ce,
+ 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000246, 0x20202020, 0x20202020, 0x20202020,
+ 0x1ce739ce, 0x000001ce, 0x00000000, 0x18c43433, 0x00040000,
+ 0xdb005012, 0x04924914, 0x21084210, 0x6d801300, 0x07e41000,
+ 0x00040000, 0xdb005012, 0x04924914, 0x21084210, 0x6d801300,
+ 0x07e40000, 0x00100000, 0x773f0567, 0x54214514, 0x12035828,
+ 0x9259269a, 0x52802000, 0x0a8e370e, 0xc0102850, 0x812d4000,
+ 0x807ec400, 0x001b6db0, 0x00376b63, 0x06db6db6, 0x006d8000,
+ 0xffeffffe, 0xffeffffe, 0x00010000, 0x02060aeb, 0x2a850160
+};
+
+static const uint16_t ar9280_2_0_fast_clock_regs[] = {
+ P(0x01030), P(0x01070), P(0x010b0), P(0x08014), P(0x0801c),
+ P(0x08318), P(0x09820), P(0x09824), P(0x09828), P(0x09834),
+ P(0x09844), P(0x09914), P(0x09918)
+};
+
+static const uint32_t ar9280_2_0_fast_clock_vals_5g20[] = {
+ 0x00000268, 0x0000018c, 0x00000fd0, 0x044c044c, 0x148ec02b,
+ 0x000044c0, 0x02020200, 0x01000f0f, 0x0b020001, 0x00000f0f,
+ 0x03721821, 0x00000898, 0x0000000b
+};
+
+#ifndef IEEE80211_NO_HT
+static const uint32_t ar9280_2_0_fast_clock_vals_5g40[] = {
+ 0x000004d0, 0x00000318, 0x00001fa0, 0x08980898, 0x148ec057,
+ 0x00008980, 0x02020200, 0x01000f0f, 0x0b020001, 0x00000f0f,
+ 0x03721821, 0x00001130, 0x00000016
+};
+#endif
+
+static const struct athn_ini ar9280_2_0_ini = {
+ __arraycount(ar9280_2_0_regs),
+ ar9280_2_0_regs,
+ ar9280_2_0_vals_5g20,
+#ifndef IEEE80211_NO_HT
+ ar9280_2_0_vals_5g40,
+ ar9280_2_0_vals_2g40,
+#endif
+ ar9280_2_0_vals_2g20,
+ __arraycount(ar9280_2_0_cm_regs),
+ ar9280_2_0_cm_regs,
+ ar9280_2_0_cm_vals,
+ __arraycount(ar9280_2_0_fast_clock_regs),
+ ar9280_2_0_fast_clock_regs,
+ ar9280_2_0_fast_clock_vals_5g20,
+#ifndef IEEE80211_NO_HT
+ ar9280_2_0_fast_clock_vals_5g40
+#endif
+};
+
+/*
+ * AR9280 2.0 Tx gains.
+ */
+static const uint16_t ar9280_2_0_tx_gain_regs[] = {
+ P(0x0a274), P(0x0a27c), P(0x0a300), P(0x0a304), P(0x0a308),
+ P(0x0a30c), P(0x0a310), P(0x0a314), P(0x0a318), P(0x0a31c),
+ P(0x0a320), P(0x0a324), P(0x0a328), P(0x0a32c), P(0x0a330),
+ P(0x0a334), P(0x0a338), P(0x0a33c), P(0x0a340), P(0x0a344),
+ P(0x0a348), P(0x0a34c), P(0x0a350), P(0x0a354), P(0x0a3ec),
+ P(0x07814), P(0x07838), P(0x0781c), P(0x07840), P(0x07820),
+ P(0x07844)
+};
+
+static const uint32_t ar9280_2_0_tx_gain_vals_5g[] = {
+ 0x0a19c652, 0x050701ce, 0x00000000, 0x00003002, 0x00006004,
+ 0x0000a006, 0x0000e012, 0x00011014, 0x0001504a, 0x0001904c,
+ 0x0001c04e, 0x00020092, 0x0002410a, 0x0002710c, 0x0002b18b,
+ 0x0002e1cc, 0x000321ec, 0x000321ec, 0x000321ec, 0x000321ec,
+ 0x000321ec, 0x000321ec, 0x000321ec, 0x000321ec, 0x00f70081,
+ 0x0019beff, 0x0019beff, 0x00392000, 0x00392000, 0x92592480,
+ 0x92592480
+};
+
+static const uint32_t ar9280_2_0_tx_gain_vals_2g[] = {
+ 0x0a1aa652, 0x050701ce, 0x00000000, 0x00003002, 0x00008009,
+ 0x0000b00b, 0x0000e012, 0x00012048, 0x0001604a, 0x0001a211,
+ 0x0001e213, 0x0002121b, 0x00024412, 0x00028414, 0x0002b44a,
+ 0x00030649, 0x0003364b, 0x00038a49, 0x0003be48, 0x0003ee4a,
+ 0x00042e88, 0x00046e8a, 0x00049ec9, 0x0004bf42, 0x00f70081,
+ 0x0019beff, 0x0019beff, 0x00392000, 0x00392000, 0x92592480,
+ 0x92592480
+};
+
+static const struct athn_gain ar9280_2_0_tx_gain = {
+ __arraycount(ar9280_2_0_tx_gain_regs),
+ ar9280_2_0_tx_gain_regs,
+ ar9280_2_0_tx_gain_vals_5g,
+ ar9280_2_0_tx_gain_vals_2g
+};
+
+static const uint32_t ar9280_2_0_tx_gain_high_power_vals_5g[] = {
+ 0x0a19e652, 0x050739ce, 0x00000000, 0x00003002, 0x00006004,
+ 0x0000a006, 0x0000e012, 0x00011014, 0x0001504a, 0x0001904c,
+ 0x0001c04e, 0x00021092, 0x0002510a, 0x0002910c, 0x0002c18b,
+ 0x0002f1cc, 0x000321eb, 0x000341ec, 0x000341ec, 0x000341ec,
+ 0x000341ec, 0x000341ec, 0x000341ec, 0x000341ec, 0x00f70081,
+ 0x00198eff, 0x00198eff, 0x00172000, 0x00172000, 0xf258a480,
+ 0xf258a480
+};
+
+static const uint32_t ar9280_2_0_tx_gain_high_power_vals_2g[] = {
+ 0x0a1aa652, 0x050739ce, 0x00000000, 0x00004002, 0x00007008,
+ 0x0000c010, 0x00010012, 0x00013014, 0x0001820a, 0x0001b211,
+ 0x0001e213, 0x00022411, 0x00025413, 0x00029811, 0x0002c813,
+ 0x00030a14, 0x00035a50, 0x00039c4c, 0x0003de8a, 0x00042e92,
+ 0x00046ed2, 0x0004bed5, 0x0004ff54, 0x00055fd5, 0x00f70081,
+ 0x00198eff, 0x00198eff, 0x00172000, 0x00172000, 0xf258a480,
+ 0xf258a480
+};
+
+static const struct athn_gain ar9280_2_0_tx_gain_high_power = {
+ __arraycount(ar9280_2_0_tx_gain_regs),
+ ar9280_2_0_tx_gain_regs,
+ ar9280_2_0_tx_gain_high_power_vals_5g,
+ ar9280_2_0_tx_gain_high_power_vals_2g
+};
+
+/*
+ * AR9280 2.0 Rx gains.
+ */
+static const uint16_t ar9280_2_0_rx_gain_regs[] = {
+ P(0x09a00), P(0x09a04), P(0x09a08), P(0x09a0c), P(0x09a10),
+ P(0x09a14), P(0x09a18), P(0x09a1c), P(0x09a20), P(0x09a24),
+ P(0x09a28), P(0x09a2c), P(0x09a30), P(0x09a34), P(0x09a38),
+ P(0x09a3c), P(0x09a40), P(0x09a44), P(0x09a48), P(0x09a4c),
+ P(0x09a50), P(0x09a54), P(0x09a58), P(0x09a5c), P(0x09a60),
+ P(0x09a64), P(0x09a68), P(0x09a6c), P(0x09a70), P(0x09a74),
+ P(0x09a78), P(0x09a7c), P(0x09a80), P(0x09a84), P(0x09a88),
+ P(0x09a8c), P(0x09a90), P(0x09a94), P(0x09a98), P(0x09a9c),
+ P(0x09aa0), P(0x09aa4), P(0x09aa8), P(0x09aac), P(0x09ab0),
+ P(0x09ab4), P(0x09ab8), P(0x09abc), P(0x09ac0), P(0x09ac4),
+ P(0x09ac8), P(0x09acc), P(0x09ad0), P(0x09ad4), P(0x09ad8),
+ P(0x09adc), P(0x09ae0), P(0x09ae4), P(0x09ae8), P(0x09aec),
+ P(0x09af0), P(0x09af4), P(0x09af8), P(0x09afc), P(0x09b00),
+ P(0x09b04), P(0x09b08), P(0x09b0c), P(0x09b10), P(0x09b14),
+ P(0x09b18), P(0x09b1c), P(0x09b20), P(0x09b24), P(0x09b28),
+ P(0x09b2c), P(0x09b30), P(0x09b34), P(0x09b38), P(0x09b3c),
+ P(0x09b40), P(0x09b44), P(0x09b48), P(0x09b4c), P(0x09b50),
+ P(0x09b54), P(0x09b58), P(0x09b5c), P(0x09b60), P(0x09b64),
+ P(0x09b68), P(0x09b6c), P(0x09b70), P(0x09b74), P(0x09b78),
+ P(0x09b7c), P(0x09b80), P(0x09b84), P(0x09b88), P(0x09b8c),
+ P(0x09b90), P(0x09b94), P(0x09b98), P(0x09b9c), P(0x09ba0),
+ P(0x09ba4), P(0x09ba8), P(0x09bac), P(0x09bb0), P(0x09bb4),
+ P(0x09bb8), P(0x09bbc), P(0x09bc0), P(0x09bc4), P(0x09bc8),
+ P(0x09bcc), P(0x09bd0), P(0x09bd4), P(0x09bd8), P(0x09bdc),
+ P(0x09be0), P(0x09be4), P(0x09be8), P(0x09bec), P(0x09bf0),
+ P(0x09bf4), P(0x09bf8), P(0x09bfc), P(0x09848), P(0x0a848)
+};
+
+static const uint32_t ar9280_2_0_rx_gain_vals_5g[] = {
+ 0x00008184, 0x00008188, 0x0000818c, 0x00008190, 0x00008194,
+ 0x00008200, 0x00008204, 0x00008208, 0x0000820c, 0x00008210,
+ 0x00008214, 0x00008280, 0x00008284, 0x00008288, 0x0000828c,
+ 0x00008290, 0x00008300, 0x00008304, 0x00008308, 0x0000830c,
+ 0x00008310, 0x00008314, 0x00008380, 0x00008384, 0x00008388,
+ 0x0000838c, 0x00008390, 0x00008394, 0x0000a380, 0x0000a384,
+ 0x0000a388, 0x0000a38c, 0x0000a390, 0x0000a394, 0x0000a780,
+ 0x0000a784, 0x0000a788, 0x0000a78c, 0x0000a790, 0x0000a794,
+ 0x0000ab84, 0x0000ab88, 0x0000ab8c, 0x0000ab90, 0x0000ab94,
+ 0x0000af80, 0x0000af84, 0x0000af88, 0x0000af8c, 0x0000af90,
+ 0x0000af94, 0x0000b380, 0x0000b384, 0x0000b388, 0x0000b38c,
+ 0x0000b390, 0x0000b394, 0x0000b398, 0x0000b780, 0x0000b784,
+ 0x0000b788, 0x0000b78c, 0x0000b790, 0x0000b794, 0x0000b798,
+ 0x0000d784, 0x0000d788, 0x0000d78c, 0x0000d790, 0x0000f780,
+ 0x0000f784, 0x0000f788, 0x0000f78c, 0x0000f790, 0x0000f794,
+ 0x0000f7a4, 0x0000f7a8, 0x0000f7ac, 0x0000f7b0, 0x0000f7b4,
+ 0x0000f7a1, 0x0000f7a5, 0x0000f7a9, 0x0000f7ad, 0x0000f7b1,
+ 0x0000f7b5, 0x0000f7c5, 0x0000f7c9, 0x0000f7cd, 0x0000f7d1,
+ 0x0000f7d5, 0x0000f7c2, 0x0000f7c6, 0x0000f7ca, 0x0000f7ce,
+ 0x0000f7d2, 0x0000f7d6, 0x0000f7c3, 0x0000f7c7, 0x0000f7cb,
+ 0x0000f7d3, 0x0000f7d7, 0x0000f7db, 0x0000f7db, 0x0000f7db,
+ 0x0000f7db, 0x0000f7db, 0x0000f7db, 0x0000f7db, 0x0000f7db,
+ 0x0000f7db, 0x0000f7db, 0x0000f7db, 0x0000f7db, 0x0000f7db,
+ 0x0000f7db, 0x0000f7db, 0x0000f7db, 0x0000f7db, 0x0000f7db,
+ 0x0000f7db, 0x0000f7db, 0x0000f7db, 0x0000f7db, 0x0000f7db,
+ 0x0000f7db, 0x0000f7db, 0x0000f7db, 0x00001066, 0x00001066
+};
+
+static const uint32_t ar9280_2_0_rx_gain_vals_2g[] = {
+ 0x00008000, 0x00008000, 0x00008000, 0x00008000, 0x00008000,
+ 0x00008000, 0x00008004, 0x00008008, 0x0000800c, 0x00008080,
+ 0x00008084, 0x00008088, 0x0000808c, 0x00008100, 0x00008104,
+ 0x00008108, 0x0000810c, 0x00008110, 0x00008114, 0x00008180,
+ 0x00008184, 0x00008188, 0x0000818c, 0x00008190, 0x00008194,
+ 0x000081a0, 0x0000820c, 0x000081a8, 0x00008284, 0x00008288,
+ 0x00008224, 0x00008290, 0x00008300, 0x00008304, 0x00008308,
+ 0x0000830c, 0x00008380, 0x00008384, 0x00008700, 0x00008704,
+ 0x00008708, 0x0000870c, 0x00008780, 0x00008784, 0x00008b00,
+ 0x00008b04, 0x00008b08, 0x00008b0c, 0x00008b80, 0x00008b84,
+ 0x00008b88, 0x00008b8c, 0x00008b90, 0x00008f80, 0x00008f84,
+ 0x00008f88, 0x00008f8c, 0x00008f90, 0x0000930c, 0x00009310,
+ 0x00009384, 0x00009388, 0x00009324, 0x00009704, 0x000096a4,
+ 0x000096a8, 0x00009710, 0x00009714, 0x00009720, 0x00009724,
+ 0x00009728, 0x0000972c, 0x000097a0, 0x000097a4, 0x000097a8,
+ 0x000097b0, 0x000097b4, 0x000097b8, 0x000097a5, 0x000097a9,
+ 0x000097ad, 0x000097b1, 0x000097b5, 0x000097b9, 0x000097c5,
+ 0x000097c9, 0x000097d1, 0x000097d5, 0x000097d9, 0x000097c6,
+ 0x000097ca, 0x000097ce, 0x000097d2, 0x000097d6, 0x000097c3,
+ 0x000097c7, 0x000097cb, 0x000097cf, 0x000097d7, 0x000097db,
+ 0x000097db, 0x000097db, 0x000097db, 0x000097db, 0x000097db,
+ 0x000097db, 0x000097db, 0x000097db, 0x000097db, 0x000097db,
+ 0x000097db, 0x000097db, 0x000097db, 0x000097db, 0x000097db,
+ 0x000097db, 0x000097db, 0x000097db, 0x000097db, 0x000097db,
+ 0x000097db, 0x000097db, 0x000097db, 0x000097db, 0x000097db,
+ 0x000097db, 0x000097db, 0x000097db, 0x00001063, 0x00001063
+};
+
+static const struct athn_gain ar9280_2_0_rx_gain = {
+ __arraycount(ar9280_2_0_rx_gain_regs),
+ ar9280_2_0_rx_gain_regs,
+ ar9280_2_0_rx_gain_vals_5g,
+ ar9280_2_0_rx_gain_vals_2g
+};
+
+static const uint32_t ar9280_2_0_rx_gain_13db_backoff_vals_5g[] = {
+ 0x00008184, 0x00008188, 0x0000818c, 0x00008190, 0x00008194,
+ 0x00008200, 0x00008204, 0x00008208, 0x0000820c, 0x00008210,
+ 0x00008214, 0x00008280, 0x00008284, 0x00008288, 0x0000828c,
+ 0x00008290, 0x00008300, 0x00008304, 0x00008308, 0x0000830c,
+ 0x00008310, 0x00008314, 0x00008380, 0x00008384, 0x00008388,
+ 0x0000838c, 0x00008390, 0x00008394, 0x0000a380, 0x0000a384,
+ 0x0000a388, 0x0000a38c, 0x0000a390, 0x0000a394, 0x0000a780,
+ 0x0000a784, 0x0000a788, 0x0000a78c, 0x0000a790, 0x0000a794,
+ 0x0000ab84, 0x0000ab88, 0x0000ab8c, 0x0000ab90, 0x0000ab94,
+ 0x0000af80, 0x0000af84, 0x0000af88, 0x0000af8c, 0x0000af90,
+ 0x0000af94, 0x0000b380, 0x0000b384, 0x0000b388, 0x0000b38c,
+ 0x0000b390, 0x0000b394, 0x0000b398, 0x0000b780, 0x0000b784,
+ 0x0000b788, 0x0000b78c, 0x0000b790, 0x0000b794, 0x0000b798,
+ 0x0000d784, 0x0000d788, 0x0000d78c, 0x0000d790, 0x0000f780,
+ 0x0000f784, 0x0000f788, 0x0000f78c, 0x0000f790, 0x0000f794,
+ 0x0000f7a4, 0x0000f7a8, 0x0000f7ac, 0x0000f7b0, 0x0000f7b4,
+ 0x0000f7a1, 0x0000f7a5, 0x0000f7a9, 0x0000f7ad, 0x0000f7b1,
+ 0x0000f7b5, 0x0000f7c5, 0x0000f7c9, 0x0000f7cd, 0x0000f7d1,
+ 0x0000f7d5, 0x0000f7c2, 0x0000f7c6, 0x0000f7ca, 0x0000f7ce,
+ 0x0000f7d2, 0x0000f7d6, 0x0000f7c3, 0x0000f7c7, 0x0000f7cb,
+ 0x0000f7d3, 0x0000f7d7, 0x0000f7db, 0x0000f7db, 0x0000f7db,
+ 0x0000f7db, 0x0000f7db, 0x0000f7db, 0x0000f7db, 0x0000f7db,
+ 0x0000f7db, 0x0000f7db, 0x0000f7db, 0x0000f7db, 0x0000f7db,
+ 0x0000f7db, 0x0000f7db, 0x0000f7db, 0x0000f7db, 0x0000f7db,
+ 0x0000f7db, 0x0000f7db, 0x0000f7db, 0x0000f7db, 0x0000f7db,
+ 0x0000f7db, 0x0000f7db, 0x0000f7db, 0x00001066, 0x00001066
+};
+
+static const uint32_t ar9280_2_0_rx_gain_13db_backoff_vals_2g[] = {
+ 0x00000290, 0x00000300, 0x00000304, 0x00000308, 0x0000030c,
+ 0x00008000, 0x00008004, 0x00008008, 0x0000800c, 0x00008080,
+ 0x00008084, 0x00008088, 0x0000808c, 0x00008100, 0x00008104,
+ 0x00008108, 0x0000810c, 0x00008110, 0x00008114, 0x00008180,
+ 0x00008184, 0x00008188, 0x0000818c, 0x00008190, 0x00008194,
+ 0x000081a0, 0x0000820c, 0x000081a8, 0x00008284, 0x00008288,
+ 0x00008224, 0x00008290, 0x00008300, 0x00008304, 0x00008308,
+ 0x0000830c, 0x00008380, 0x00008384, 0x00008700, 0x00008704,
+ 0x00008708, 0x0000870c, 0x00008780, 0x00008784, 0x00008b00,
+ 0x00008b04, 0x00008b08, 0x00008b0c, 0x00008b80, 0x00008b84,
+ 0x00008b88, 0x00008b8c, 0x00008b90, 0x00008f80, 0x00008f84,
+ 0x00008f88, 0x00008f8c, 0x00008f90, 0x00009310, 0x00009314,
+ 0x00009320, 0x00009324, 0x00009328, 0x0000932c, 0x00009330,
+ 0x00009334, 0x00009321, 0x00009325, 0x00009329, 0x0000932d,
+ 0x00009331, 0x00009335, 0x00009322, 0x00009326, 0x0000932a,
+ 0x0000932e, 0x00009332, 0x00009336, 0x00009323, 0x00009327,
+ 0x0000932b, 0x0000932f, 0x00009333, 0x00009337, 0x00009343,
+ 0x00009347, 0x0000934b, 0x0000934f, 0x00009353, 0x00009357,
+ 0x0000935b, 0x0000935b, 0x0000935b, 0x0000935b, 0x0000935b,
+ 0x0000935b, 0x0000935b, 0x0000935b, 0x0000935b, 0x0000935b,
+ 0x0000935b, 0x0000935b, 0x0000935b, 0x0000935b, 0x0000935b,
+ 0x0000935b, 0x0000935b, 0x0000935b, 0x0000935b, 0x0000935b,
+ 0x0000935b, 0x0000935b, 0x0000935b, 0x0000935b, 0x0000935b,
+ 0x0000935b, 0x0000935b, 0x0000935b, 0x0000935b, 0x0000935b,
+ 0x0000935b, 0x0000935b, 0x0000935b, 0x0000935b, 0x0000935b,
+ 0x0000935b, 0x0000935b, 0x0000935b, 0x0000105a, 0x0000105a
+};
+
+static const struct athn_gain ar9280_2_0_rx_gain_13db_backoff = {
+ __arraycount(ar9280_2_0_rx_gain_regs),
+ ar9280_2_0_rx_gain_regs,
+ ar9280_2_0_rx_gain_13db_backoff_vals_5g,
+ ar9280_2_0_rx_gain_13db_backoff_vals_2g
+};
+
+static const uint32_t ar9280_2_0_rx_gain_23db_backoff_vals_5g[] = {
+ 0x00008184, 0x00008188, 0x0000818c, 0x00008190, 0x00008194,
+ 0x00008200, 0x00008204, 0x00008208, 0x0000820c, 0x00008210,
+ 0x00008214, 0x00008280, 0x00008284, 0x00008288, 0x0000828c,
+ 0x00008290, 0x00008300, 0x00008304, 0x00008308, 0x0000830c,
+ 0x00008310, 0x00008314, 0x00008380, 0x00008384, 0x00008388,
+ 0x0000838c, 0x00008390, 0x00008394, 0x0000a380, 0x0000a384,
+ 0x0000a388, 0x0000a38c, 0x0000a390, 0x0000a394, 0x0000a780,
+ 0x0000a784, 0x0000a788, 0x0000a78c, 0x0000a790, 0x0000a794,
+ 0x0000ab84, 0x0000ab88, 0x0000ab8c, 0x0000ab90, 0x0000ab94,
+ 0x0000af80, 0x0000af84, 0x0000af88, 0x0000af8c, 0x0000af90,
+ 0x0000af94, 0x0000b380, 0x0000b384, 0x0000b388, 0x0000b38c,
+ 0x0000b390, 0x0000b394, 0x0000b398, 0x0000b780, 0x0000b784,
+ 0x0000b788, 0x0000b78c, 0x0000b790, 0x0000b794, 0x0000b798,
+ 0x0000d784, 0x0000d788, 0x0000d78c, 0x0000d790, 0x0000f780,
+ 0x0000f784, 0x0000f788, 0x0000f78c, 0x0000f790, 0x0000f794,
+ 0x0000f7a4, 0x0000f7a8, 0x0000f7ac, 0x0000f7b0, 0x0000f7b4,
+ 0x0000f7a1, 0x0000f7a5, 0x0000f7a9, 0x0000f7ad, 0x0000f7b1,
+ 0x0000f7b5, 0x0000f7c5, 0x0000f7c9, 0x0000f7cd, 0x0000f7d1,
+ 0x0000f7d5, 0x0000f7c2, 0x0000f7c6, 0x0000f7ca, 0x0000f7ce,
+ 0x0000f7d2, 0x0000f7d6, 0x0000f7c3, 0x0000f7c7, 0x0000f7cb,
+ 0x0000f7d3, 0x0000f7d7, 0x0000f7db, 0x0000f7db, 0x0000f7db,
+ 0x0000f7db, 0x0000f7db, 0x0000f7db, 0x0000f7db, 0x0000f7db,
+ 0x0000f7db, 0x0000f7db, 0x0000f7db, 0x0000f7db, 0x0000f7db,
+ 0x0000f7db, 0x0000f7db, 0x0000f7db, 0x0000f7db, 0x0000f7db,
+ 0x0000f7db, 0x0000f7db, 0x0000f7db, 0x0000f7db, 0x0000f7db,
+ 0x0000f7db, 0x0000f7db, 0x0000f7db, 0x00001066, 0x00001066
+};
+
+static const uint32_t ar9280_2_0_rx_gain_23db_backoff_vals_2g[] = {
+ 0x00000290, 0x00000300, 0x00000304, 0x00000308, 0x0000030c,
+ 0x00008000, 0x00008004, 0x00008008, 0x0000800c, 0x00008080,
+ 0x00008084, 0x00008088, 0x0000808c, 0x00008100, 0x00008104,
+ 0x00008108, 0x0000810c, 0x00008110, 0x00008114, 0x00008180,
+ 0x00008184, 0x00008188, 0x0000818c, 0x00008190, 0x00008194,
+ 0x000081a0, 0x0000820c, 0x000081a8, 0x00008284, 0x00008288,
+ 0x00008224, 0x00008290, 0x00008300, 0x00008304, 0x00008308,
+ 0x0000830c, 0x00008380, 0x00008384, 0x00008700, 0x00008704,
+ 0x00008708, 0x0000870c, 0x00008780, 0x00008784, 0x00008b00,
+ 0x00008b04, 0x00008b08, 0x00008b0c, 0x00008b10, 0x00008b80,
+ 0x00008b84, 0x00008b88, 0x00008b8c, 0x00008b90, 0x00008b94,
+ 0x00008b98, 0x00008ba4, 0x00008ba8, 0x00008bac, 0x00008bb0,
+ 0x00008bb4, 0x00008ba1, 0x00008ba5, 0x00008ba9, 0x00008bad,
+ 0x00008bb1, 0x00008bb5, 0x00008ba2, 0x00008ba6, 0x00008baa,
+ 0x00008bae, 0x00008bb2, 0x00008bb6, 0x00008ba3, 0x00008ba7,
+ 0x00008bab, 0x00008baf, 0x00008bb3, 0x00008bb7, 0x00008bc3,
+ 0x00008bc7, 0x00008bcb, 0x00008bcf, 0x00008bd3, 0x00008bd7,
+ 0x00008bdb, 0x00008bdb, 0x00008bdb, 0x00008bdb, 0x00008bdb,
+ 0x00008bdb, 0x00008bdb, 0x00008bdb, 0x00008bdb, 0x00008bdb,
+ 0x00008bdb, 0x00008bdb, 0x00008bdb, 0x00008bdb, 0x00008bdb,
+ 0x00008bdb, 0x00008bdb, 0x00008bdb, 0x00008bdb, 0x00008bdb,
+ 0x00008bdb, 0x00008bdb, 0x00008bdb, 0x00008bdb, 0x00008bdb,
+ 0x00008bdb, 0x00008bdb, 0x00008bdb, 0x00008bdb, 0x00008bdb,
+ 0x00008bdb, 0x00008bdb, 0x00008bdb, 0x00008bdb, 0x00008bdb,
+ 0x00008bdb, 0x00008bdb, 0x00008bdb, 0x00008bdb, 0x00008bdb,
+ 0x00008bdb, 0x00008bdb, 0x00008bdb, 0x00001055, 0x00001055
+};
+
+static const struct athn_gain ar9280_2_0_rx_gain_23db_backoff = {
+ __arraycount(ar9280_2_0_rx_gain_regs),
+ ar9280_2_0_rx_gain_regs,
+ ar9280_2_0_rx_gain_23db_backoff_vals_5g,
+ ar9280_2_0_rx_gain_23db_backoff_vals_2g
+};
+
+/*
+ * Serializer/Deserializer programming.
+ */
+
+static const uint32_t ar9280_2_0_serdes_regs[] = {
+ AR_PCIE_SERDES,
+ AR_PCIE_SERDES,
+ AR_PCIE_SERDES,
+ AR_PCIE_SERDES,
+ AR_PCIE_SERDES,
+ AR_PCIE_SERDES,
+ AR_PCIE_SERDES,
+ AR_PCIE_SERDES,
+ AR_PCIE_SERDES,
+ AR_PCIE_SERDES2,
+};
+
+static const uint32_t ar9280_2_0_serdes_vals[] = {
+ 0x9248fd00,
+ 0x24924924,
+ 0xa8000019,
+ 0x13160820,
+ 0xe5980560,
+#ifdef ATHN_PCIE_CLKREQ
+ 0xc01dcffc,
+#else
+ 0xc01dcffd,
+#endif
+ 0x1aaabe41,
+ 0xbe105554,
+ 0x00043007,
+ 0x00000000
+};
+
+static const struct athn_serdes ar9280_2_0_serdes = {
+ __arraycount(ar9280_2_0_serdes_vals),
+ ar9280_2_0_serdes_regs,
+ ar9280_2_0_serdes_vals
+};
+
+#endif /* _ARN9280REG_H_ */
diff --git a/sys/dev/ic/arn9285.c b/sys/dev/ic/arn9285.c
new file mode 100644
index 00000000000..685c5855d99
--- /dev/null
+++ b/sys/dev/ic/arn9285.c
@@ -0,0 +1,887 @@
+/* $NetBSD: arn9285.c,v 1.1 2013/03/30 02:53:01 christos Exp $ */
+/* $OpenBSD: ar9285.c,v 1.19 2012/06/10 21:23:36 kettenis Exp $ */
+
+/*-
+ * Copyright (c) 2009-2010 Damien Bergamini <damien.bergamini@free.fr>
+ * Copyright (c) 2008-2010 Atheros Communications Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+/*
+ * Driver for Atheros 802.11a/g/n chipsets.
+ * Routines for AR9285 and AR9271 chipsets.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: arn9285.c,v 1.1 2013/03/30 02:53:01 christos Exp $");
+
+#ifndef _MODULE
+#include "athn_usb.h"
+#endif
+
+#include <sys/param.h>
+#include <sys/sockio.h>
+#include <sys/mbuf.h>
+#include <sys/kernel.h>
+#include <sys/socket.h>
+#include <sys/systm.h>
+#include <sys/malloc.h>
+#include <sys/queue.h>
+#include <sys/callout.h>
+#include <sys/conf.h>
+#include <sys/device.h>
+
+#include <sys/bus.h>
+#include <sys/endian.h>
+#include <sys/intr.h>
+
+#include <net/bpf.h>
+#include <net/if.h>
+#include <net/if_arp.h>
+#include <net/if_dl.h>
+#include <net/if_media.h>
+#include <net/if_types.h>
+
+#include <netinet/in.h>
+#include <netinet/in_systm.h>
+#include <netinet/in_var.h>
+#include <netinet/ip.h>
+
+#include <net80211/ieee80211_var.h>
+#include <net80211/ieee80211_amrr.h>
+#include <net80211/ieee80211_radiotap.h>
+
+#include <dev/ic/athnreg.h>
+#include <dev/ic/athnvar.h>
+#include <dev/ic/arn9285.h>
+
+#include <dev/ic/arn5008reg.h>
+#include <dev/ic/arn9280reg.h>
+#include <dev/ic/arn9285reg.h>
+
+#include <dev/ic/arn5008.h>
+#include <dev/ic/arn9280.h>
+#include <dev/ic/arn9285.h>
+
+#define Static static
+
+Static int ar9285_cl_cal(struct athn_softc *, struct ieee80211_channel *,
+ struct ieee80211_channel *);
+Static void ar9285_get_pdadcs(struct athn_softc *,
+ struct ieee80211_channel *, int, uint8_t, uint8_t *,
+ uint8_t *);
+Static const struct ar_spur_chan *
+ ar9285_get_spur_chans(struct athn_softc *, int);
+Static void ar9285_init_from_rom(struct athn_softc *,
+ struct ieee80211_channel *, struct ieee80211_channel *);
+Static void ar9285_set_power_calib(struct athn_softc *,
+ struct ieee80211_channel *);
+Static void ar9285_set_txpower(struct athn_softc *,
+ struct ieee80211_channel *, struct ieee80211_channel *);
+Static void ar9285_setup(struct athn_softc *);
+Static void ar9285_swap_rom(struct athn_softc *);
+
+PUBLIC int
+ar9285_attach(struct athn_softc *sc)
+{
+
+ sc->sc_eep_base = AR9285_EEP_START_LOC;
+ sc->sc_eep_size = sizeof(struct ar9285_eeprom);
+ sc->sc_def_nf = AR9285_PHY_CCA_MAX_GOOD_VALUE;
+ sc->sc_ngpiopins = (sc->sc_flags & ATHN_FLAG_USB) ? 16 : 12;
+ sc->sc_led_pin = (sc->sc_flags & ATHN_FLAG_USB) ? 15 : 1;
+ sc->sc_workaround = AR9285_WA_DEFAULT;
+ sc->sc_ops.setup = ar9285_setup;
+ sc->sc_ops.swap_rom = ar9285_swap_rom;
+ sc->sc_ops.init_from_rom = ar9285_init_from_rom;
+ sc->sc_ops.set_txpower = ar9285_set_txpower;
+ sc->sc_ops.set_synth = ar9280_set_synth;
+ sc->sc_ops.spur_mitigate = ar9280_spur_mitigate;
+ sc->sc_ops.get_spur_chans = ar9285_get_spur_chans;
+#if NATHN_USB > 0
+ if (AR_SREV_9271(sc))
+ sc->sc_ini = &ar9271_ini;
+ else
+#endif
+ sc->sc_ini = &ar9285_1_2_ini;
+ sc->sc_serdes = &ar9280_2_0_serdes;
+
+ return ar5008_attach(sc);
+}
+
+Static void
+ar9285_setup(struct athn_softc *sc)
+{
+ const struct ar9285_eeprom *eep = sc->sc_eep;
+ uint8_t type;
+
+ /* Select initialization values based on ROM. */
+ type = eep->baseEepHeader.txGainType;
+ DPRINTFN(DBG_TX, sc, "Tx gain type=0x%x\n", type);
+#if NATHN_USB > 0
+ if (AR_SREV_9271(sc)) {
+ if (type == AR_EEP_TXGAIN_HIGH_POWER)
+ sc->sc_tx_gain = &ar9271_tx_gain_high_power;
+ else
+ sc->sc_tx_gain = &ar9271_tx_gain;
+ }
+ else
+#endif /* NATHN_USB */
+ if ((AR_READ(sc, AR_AN_SYNTH9) & 0x7) == 0x1) { /* XE rev. */
+ if (type == AR_EEP_TXGAIN_HIGH_POWER)
+ sc->sc_tx_gain = &ar9285_2_0_tx_gain_high_power;
+ else
+ sc->sc_tx_gain = &ar9285_2_0_tx_gain;
+ }
+ else {
+ if (type == AR_EEP_TXGAIN_HIGH_POWER)
+ sc->sc_tx_gain = &ar9285_1_2_tx_gain_high_power;
+ else
+ sc->sc_tx_gain = &ar9285_1_2_tx_gain;
+ }
+}
+
+Static void
+ar9285_swap_rom(struct athn_softc *sc)
+{
+ struct ar9285_eeprom *eep = sc->sc_eep;
+ int i;
+
+ eep->modalHeader.antCtrlCommon =
+ bswap32(eep->modalHeader.antCtrlCommon);
+ eep->modalHeader.antCtrlChain =
+ bswap32(eep->modalHeader.antCtrlChain);
+
+ for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
+ eep->modalHeader.spurChans[i].spurChan =
+ bswap16(eep->modalHeader.spurChans[i].spurChan);
+ }
+}
+
+Static const struct ar_spur_chan *
+ar9285_get_spur_chans(struct athn_softc *sc, int is2ghz)
+{
+ const struct ar9285_eeprom *eep = sc->sc_eep;
+
+ KASSERT(is2ghz);
+ return eep->modalHeader.spurChans;
+}
+
+Static void
+ar9285_init_from_rom(struct athn_softc *sc, struct ieee80211_channel *c,
+ struct ieee80211_channel *extc)
+{
+ const struct ar9285_eeprom *eep = sc->sc_eep;
+ const struct ar9285_modal_eep_header *modal = &eep->modalHeader;
+ uint32_t reg, offset = 0x1000;
+ uint8_t ob[5], db1[5], db2[5];
+ uint8_t txRxAtten;
+
+ AR_WRITE(sc, AR_PHY_SWITCH_COM, modal->antCtrlCommon);
+ AR_WRITE(sc, AR_PHY_SWITCH_CHAIN_0, modal->antCtrlChain);
+
+ reg = AR_READ(sc, AR_PHY_TIMING_CTRL4_0);
+ reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, modal->iqCalI);
+ reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, modal->iqCalQ);
+ AR_WRITE(sc, AR_PHY_TIMING_CTRL4_0, reg);
+
+ if (sc->sc_eep_rev >= AR_EEP_MINOR_VER_3) {
+ reg = AR_READ(sc, AR_PHY_GAIN_2GHZ);
+ reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
+ modal->bswMargin);
+ reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_DB,
+ modal->bswAtten);
+ reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
+ modal->xatten2Margin);
+ reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_DB,
+ modal->xatten2Db);
+ AR_WRITE(sc, AR_PHY_GAIN_2GHZ, reg);
+
+ /* Duplicate values of chain 0 for chain 1. */
+ reg = AR_READ(sc, AR_PHY_GAIN_2GHZ + offset);
+ reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
+ modal->bswMargin);
+ reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_DB,
+ modal->bswAtten);
+ reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
+ modal->xatten2Margin);
+ reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_DB,
+ modal->xatten2Db);
+ AR_WRITE(sc, AR_PHY_GAIN_2GHZ + offset, reg);
+ }
+ if (sc->sc_eep_rev >= AR_EEP_MINOR_VER_3)
+ txRxAtten = modal->txRxAtten;
+ else /* Workaround for ROM versions < 14.3. */
+ txRxAtten = 23;
+ reg = AR_READ(sc, AR_PHY_RXGAIN);
+ reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAtten);
+ reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_MARGIN, modal->rxTxMargin);
+ AR_WRITE(sc, AR_PHY_RXGAIN, reg);
+
+ /* Duplicate values of chain 0 for chain 1. */
+ reg = AR_READ(sc, AR_PHY_RXGAIN + offset);
+ reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAtten);
+ reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_MARGIN, modal->rxTxMargin);
+ AR_WRITE(sc, AR_PHY_RXGAIN + offset, reg);
+
+ if (modal->version >= 3) {
+ /* Setup antenna diversity from ROM. */
+ reg = AR_READ(sc, AR_PHY_MULTICHAIN_GAIN_CTL);
+ reg = RW(reg, AR9285_PHY_ANT_DIV_CTL_ALL, 0);
+ reg = RW(reg, AR9285_PHY_ANT_DIV_CTL,
+ (modal->ob_234 >> 12) & 0x1);
+ reg = RW(reg, AR9285_PHY_ANT_DIV_ALT_LNACONF,
+ (modal->db1_234 >> 12) & 0x3);
+ reg = RW(reg, AR9285_PHY_ANT_DIV_MAIN_LNACONF,
+ (modal->db1_234 >> 14) & 0x3);
+ reg = RW(reg, AR9285_PHY_ANT_DIV_ALT_GAINTB,
+ (modal->ob_234 >> 13) & 0x1);
+ reg = RW(reg, AR9285_PHY_ANT_DIV_MAIN_GAINTB,
+ (modal->ob_234 >> 14) & 0x1);
+ AR_WRITE(sc, AR_PHY_MULTICHAIN_GAIN_CTL, reg);
+ reg = AR_READ(sc, AR_PHY_MULTICHAIN_GAIN_CTL); /* Flush. */
+
+ reg = AR_READ(sc, AR_PHY_CCK_DETECT);
+ if (modal->ob_234 & (1 << 15))
+ reg |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
+ else
+ reg &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
+ AR_WRITE(sc, AR_PHY_CCK_DETECT, reg);
+ reg = AR_READ(sc, AR_PHY_CCK_DETECT); /* Flush. */
+ }
+ if (modal->version >= 2) {
+ ob [0] = (modal->ob_01 >> 0) & 0xf;
+ ob [1] = (modal->ob_01 >> 4) & 0xf;
+ ob [2] = (modal->ob_234 >> 0) & 0xf;
+ ob [3] = (modal->ob_234 >> 4) & 0xf;
+ ob [4] = (modal->ob_234 >> 8) & 0xf;
+
+ db1[0] = (modal->db1_01 >> 0) & 0xf;
+ db1[1] = (modal->db1_01 >> 4) & 0xf;
+ db1[2] = (modal->db1_234 >> 0) & 0xf;
+ db1[3] = (modal->db1_234 >> 4) & 0xf;
+ db1[4] = (modal->db1_234 >> 8) & 0xf;
+
+ db2[0] = (modal->db2_01 >> 0) & 0xf;
+ db2[1] = (modal->db2_01 >> 4) & 0xf;
+ db2[2] = (modal->db2_234 >> 0) & 0xf;
+ db2[3] = (modal->db2_234 >> 4) & 0xf;
+ db2[4] = (modal->db2_234 >> 8) & 0xf;
+
+ }
+ else if (modal->version == 1) {
+ ob [0] = (modal->ob_01 >> 0) & 0xf;
+ ob [1] = (modal->ob_01 >> 4) & 0xf;
+ /* Field ob_234 does not exist, use ob_01. */
+ ob [2] = ob [3] = ob [4] = ob [1];
+
+ db1[0] = (modal->db1_01 >> 0) & 0xf;
+ db1[1] = (modal->db1_01 >> 4) & 0xf;
+ /* Field db1_234 does not exist, use db1_01. */
+ db1[2] = db1[3] = db1[4] = db1[1];
+
+ db2[0] = (modal->db2_01 >> 0) & 0xf;
+ db2[1] = (modal->db2_01 >> 4) & 0xf;
+ /* Field db2_234 does not exist, use db2_01. */
+ db2[2] = db2[3] = db2[4] = db2[1];
+
+ }
+ else {
+ ob [0] = modal->ob_01;
+ ob [1] = ob [2] = ob [3] = ob [4] = ob [0];
+
+ db1[0] = modal->db1_01;
+ db1[1] = db1[2] = db1[3] = db1[4] = db1[0];
+
+ /* Field db2_01 does not exist, use db1_01. */
+ db2[0] = modal->db1_01;
+ db2[1] = db2[2] = db2[3] = db2[4] = db2[0];
+ }
+#if NATHN_USB > 0
+ if (AR_SREV_9271(sc)) {
+ reg = AR_READ(sc, AR9285_AN_RF2G3);
+ reg = RW(reg, AR9271_AN_RF2G3_OB_CCK, ob [0]);
+ reg = RW(reg, AR9271_AN_RF2G3_OB_PSK, ob [1]);
+ reg = RW(reg, AR9271_AN_RF2G3_OB_QAM, ob [2]);
+ reg = RW(reg, AR9271_AN_RF2G3_DB1, db1[0]);
+ AR_WRITE(sc, AR9285_AN_RF2G3, reg);
+ AR_WRITE_BARRIER(sc);
+ DELAY(100);
+ reg = AR_READ(sc, AR9285_AN_RF2G4);
+ reg = RW(reg, AR9271_AN_RF2G4_DB2, db2[0]);
+ AR_WRITE(sc, AR9285_AN_RF2G4, reg);
+ AR_WRITE_BARRIER(sc);
+ DELAY(100);
+ }
+ else
+#endif /* ATHN_USB */
+ {
+ reg = AR_READ(sc, AR9285_AN_RF2G3);
+ reg = RW(reg, AR9285_AN_RF2G3_OB_0, ob [0]);
+ reg = RW(reg, AR9285_AN_RF2G3_OB_1, ob [1]);
+ reg = RW(reg, AR9285_AN_RF2G3_OB_2, ob [2]);
+ reg = RW(reg, AR9285_AN_RF2G3_OB_3, ob [3]);
+ reg = RW(reg, AR9285_AN_RF2G3_OB_4, ob [4]);
+ reg = RW(reg, AR9285_AN_RF2G3_DB1_0, db1[0]);
+ reg = RW(reg, AR9285_AN_RF2G3_DB1_1, db1[1]);
+ reg = RW(reg, AR9285_AN_RF2G3_DB1_2, db1[2]);
+ AR_WRITE(sc, AR9285_AN_RF2G3, reg);
+ AR_WRITE_BARRIER(sc);
+ DELAY(100);
+ reg = AR_READ(sc, AR9285_AN_RF2G4);
+ reg = RW(reg, AR9285_AN_RF2G4_DB1_3, db1[3]);
+ reg = RW(reg, AR9285_AN_RF2G4_DB1_4, db1[4]);
+ reg = RW(reg, AR9285_AN_RF2G4_DB2_0, db2[0]);
+ reg = RW(reg, AR9285_AN_RF2G4_DB2_1, db2[1]);
+ reg = RW(reg, AR9285_AN_RF2G4_DB2_2, db2[2]);
+ reg = RW(reg, AR9285_AN_RF2G4_DB2_3, db2[3]);
+ reg = RW(reg, AR9285_AN_RF2G4_DB2_4, db2[4]);
+ AR_WRITE(sc, AR9285_AN_RF2G4, reg);
+ AR_WRITE_BARRIER(sc);
+ DELAY(100);
+ }
+
+ reg = AR_READ(sc, AR_PHY_SETTLING);
+ reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->switchSettling);
+ AR_WRITE(sc, AR_PHY_SETTLING, reg);
+
+ reg = AR_READ(sc, AR_PHY_DESIRED_SZ);
+ reg = RW(reg, AR_PHY_DESIRED_SZ_ADC, modal->adcDesiredSize);
+ AR_WRITE(sc, AR_PHY_DESIRED_SZ, reg);
+
+ reg = SM(AR_PHY_RF_CTL4_TX_END_XPAA_OFF, modal->txEndToXpaOff);
+ reg |= SM(AR_PHY_RF_CTL4_TX_END_XPAB_OFF, modal->txEndToXpaOff);
+ reg |= SM(AR_PHY_RF_CTL4_FRAME_XPAA_ON, modal->txFrameToXpaOn);
+ reg |= SM(AR_PHY_RF_CTL4_FRAME_XPAB_ON, modal->txFrameToXpaOn);
+ AR_WRITE(sc, AR_PHY_RF_CTL4, reg);
+
+ reg = AR_READ(sc, AR_PHY_RF_CTL3);
+ reg = RW(reg, AR_PHY_TX_END_TO_A2_RX_ON, modal->txEndToRxOn);
+ AR_WRITE(sc, AR_PHY_RF_CTL3, reg);
+
+ reg = AR_READ(sc, AR_PHY_CCA(0));
+ reg = RW(reg, AR9280_PHY_CCA_THRESH62, modal->thresh62);
+ AR_WRITE(sc, AR_PHY_CCA(0), reg);
+
+ reg = AR_READ(sc, AR_PHY_EXT_CCA0);
+ reg = RW(reg, AR_PHY_EXT_CCA0_THRESH62, modal->thresh62);
+ AR_WRITE(sc, AR_PHY_EXT_CCA0, reg);
+
+ if (sc->sc_eep_rev >= AR_EEP_MINOR_VER_2) {
+ reg = AR_READ(sc, AR_PHY_RF_CTL2);
+ reg = RW(reg, AR_PHY_TX_END_PA_ON,
+ modal->txFrameToPaOn);
+ reg = RW(reg, AR_PHY_TX_END_DATA_START,
+ modal->txFrameToDataStart);
+ AR_WRITE(sc, AR_PHY_RF_CTL2, reg);
+ }
+#ifndef IEEE80211_NO_HT
+ if (sc->sc_eep_rev >= AR_EEP_MINOR_VER_3 && extc != NULL) {
+ reg = AR_READ(sc, AR_PHY_SETTLING);
+ reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->swSettleHt40);
+ AR_WRITE(sc, AR_PHY_SETTLING, reg);
+ }
+#endif
+ AR_WRITE_BARRIER(sc);
+}
+
+PUBLIC void
+ar9285_pa_calib(struct athn_softc *sc)
+{
+ /* List of registers that need to be saved/restored. */
+ static const uint16_t regs[] = {
+ AR9285_AN_TOP3,
+ AR9285_AN_RXTXBB1,
+ AR9285_AN_RF2G1,
+ AR9285_AN_RF2G2,
+ AR9285_AN_TOP2,
+ AR9285_AN_RF2G8,
+ AR9285_AN_RF2G7
+ };
+ uint32_t svg[7], reg, ccomp_svg;
+ size_t i;
+
+ /* No PA calibration needed for high power solutions. */
+ if (AR_SREV_9285(sc) &&
+ ((struct ar9285_base_eep_header *)sc->sc_eep)->txGainType ==
+ AR_EEP_TXGAIN_HIGH_POWER) /* XXX AR9287? */
+ return;
+
+ /* Save registers. */
+ for (i = 0; i < __arraycount(regs); i++)
+ svg[i] = AR_READ(sc, regs[i]);
+
+ AR_CLRBITS(sc, AR9285_AN_RF2G6, 1);
+ AR_SETBITS(sc, AR_PHY(2), 1 << 27);
+
+ AR_SETBITS(sc, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC);
+ AR_SETBITS(sc, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1);
+ AR_SETBITS(sc, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I);
+ AR_SETBITS(sc, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF);
+ AR_CLRBITS(sc, AR9285_AN_RF2G2, AR9285_AN_RF2G2_OFFCAL);
+ AR_CLRBITS(sc, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PWDDB);
+ AR_CLRBITS(sc, AR9285_AN_RF2G1, AR9285_AN_RF2G1_ENPACAL);
+ /* Power down PA drivers. */
+ AR_CLRBITS(sc, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV1);
+ AR_CLRBITS(sc, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV2);
+ AR_CLRBITS(sc, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPAOUT);
+
+ reg = AR_READ(sc, AR9285_AN_RF2G8);
+ reg = RW(reg, AR9285_AN_RF2G8_PADRVGN2TAB0, 7);
+ AR_WRITE(sc, AR9285_AN_RF2G8, reg);
+
+ reg = AR_READ(sc, AR9285_AN_RF2G7);
+ reg = RW(reg, AR9285_AN_RF2G7_PADRVGN2TAB0, 0);
+ AR_WRITE(sc, AR9285_AN_RF2G7, reg);
+
+ reg = AR_READ(sc, AR9285_AN_RF2G6);
+ /* Save compensation capacitor value. */
+ ccomp_svg = MS(reg, AR9285_AN_RF2G6_CCOMP);
+ /* Program compensation capacitor for dynamic PA. */
+ reg = RW(reg, AR9285_AN_RF2G6_CCOMP, 0xf);
+ AR_WRITE(sc, AR9285_AN_RF2G6, reg);
+
+ AR_WRITE(sc, AR9285_AN_TOP2, AR9285_AN_TOP2_DEFAULT);
+ AR_WRITE_BARRIER(sc);
+ DELAY(30);
+
+ /* Clear offsets 6-1. */
+ AR_CLRBITS(sc, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS_6_1);
+ /* Clear offset 0. */
+ AR_CLRBITS(sc, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP);
+ /* Set offsets 6-1. */
+ for (i = 6; i >= 1; i--) {
+ AR_SETBITS(sc, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS(i));
+ AR_WRITE_BARRIER(sc);
+ DELAY(1);
+ if (AR_READ(sc, AR9285_AN_RF2G9) & AR9285_AN_RXTXBB1_SPARE9) {
+ AR_SETBITS(sc, AR9285_AN_RF2G6,
+ AR9285_AN_RF2G6_OFFS(i));
+ }
+ else {
+ AR_CLRBITS(sc, AR9285_AN_RF2G6,
+ AR9285_AN_RF2G6_OFFS(i));
+ }
+ }
+ /* Set offset 0. */
+ AR_SETBITS(sc, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP);
+ AR_WRITE_BARRIER(sc);
+ DELAY(1);
+ if (AR_READ(sc, AR9285_AN_RF2G9) & AR9285_AN_RXTXBB1_SPARE9)
+ AR_SETBITS(sc, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP);
+ else
+ AR_CLRBITS(sc, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP);
+
+ AR_WRITE_BARRIER(sc);
+
+ AR_SETBITS(sc, AR9285_AN_RF2G6, 1);
+ AR_CLRBITS(sc, AR_PHY(2), 1 << 27);
+
+ /* Restore registers. */
+ for (i = 0; i < __arraycount(regs); i++)
+ AR_WRITE(sc, regs[i], svg[i]);
+
+ /* Restore compensation capacitor value. */
+ reg = AR_READ(sc, AR9285_AN_RF2G6);
+ reg = RW(reg, AR9285_AN_RF2G6_CCOMP, ccomp_svg);
+ AR_WRITE(sc, AR9285_AN_RF2G6, reg);
+ AR_WRITE_BARRIER(sc);
+}
+
+PUBLIC void
+ar9271_pa_calib(struct athn_softc *sc)
+{
+#if NATHN_USB > 0
+ /* List of registers that need to be saved/restored. */
+ static const uint16_t regs[] = {
+ AR9285_AN_TOP3,
+ AR9285_AN_RXTXBB1,
+ AR9285_AN_RF2G1,
+ AR9285_AN_RF2G2,
+ AR9285_AN_TOP2,
+ AR9285_AN_RF2G8,
+ AR9285_AN_RF2G7
+ };
+ uint32_t svg[7], reg, rf2g3_svg;
+ size_t i;
+
+ /* Save registers. */
+ for (i = 0; i < __arraycount(regs); i++)
+ svg[i] = AR_READ(sc, regs[i]);
+
+ AR_CLRBITS(sc, AR9285_AN_RF2G6, 1);
+ AR_SETBITS(sc, AR_PHY(2), 1 << 27);
+
+ AR_SETBITS(sc, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC);
+ AR_SETBITS(sc, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1);
+ AR_SETBITS(sc, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I);
+ AR_SETBITS(sc, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF);
+ AR_CLRBITS(sc, AR9285_AN_RF2G2, AR9285_AN_RF2G2_OFFCAL);
+ AR_CLRBITS(sc, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PWDDB);
+ AR_CLRBITS(sc, AR9285_AN_RF2G1, AR9285_AN_RF2G1_ENPACAL);
+ /* Power down PA drivers. */
+ AR_CLRBITS(sc, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV1);
+ AR_CLRBITS(sc, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV2);
+ AR_CLRBITS(sc, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPAOUT);
+
+ reg = AR_READ(sc, AR9285_AN_RF2G8);
+ reg = RW(reg, AR9285_AN_RF2G8_PADRVGN2TAB0, 7);
+ AR_WRITE(sc, AR9285_AN_RF2G8, reg);
+
+ reg = AR_READ(sc, AR9285_AN_RF2G7);
+ reg = RW(reg, AR9285_AN_RF2G7_PADRVGN2TAB0, 0);
+ AR_WRITE(sc, AR9285_AN_RF2G7, reg);
+
+ /* Save compensation capacitor value. */
+ reg = rf2g3_svg = AR_READ(sc, AR9285_AN_RF2G3);
+ /* Program compensation capacitor for dynamic PA. */
+ reg = RW(reg, AR9271_AN_RF2G3_CCOMP, 0xfff);
+ AR_WRITE(sc, AR9285_AN_RF2G3, reg);
+
+ AR_WRITE(sc, AR9285_AN_TOP2, AR9285_AN_TOP2_DEFAULT);
+ AR_WRITE_BARRIER(sc);
+ DELAY(30);
+
+ /* Clear offsets 6-0. */
+ AR_CLRBITS(sc, AR9285_AN_RF2G6, AR9271_AN_RF2G6_OFFS_6_0);
+ /* Set offsets 6-1. */
+ for (i = 6; i >= 1; i--) {
+ reg = AR_READ(sc, AR9285_AN_RF2G6);
+ reg |= AR9271_AN_RF2G6_OFFS(i);
+ AR_WRITE(sc, AR9285_AN_RF2G6, reg);
+ AR_WRITE_BARRIER(sc);
+ DELAY(1);
+ if (!(AR_READ(sc, AR9285_AN_RF2G9) & AR9285_AN_RXTXBB1_SPARE9))
+ reg &= ~AR9271_AN_RF2G6_OFFS(i);
+ AR_WRITE(sc, AR9285_AN_RF2G6, reg);
+ }
+ AR_WRITE_BARRIER(sc);
+
+ AR_SETBITS(sc, AR9285_AN_RF2G6, 1);
+ AR_CLRBITS(sc, AR_PHY(2), 1 << 27);
+
+ /* Restore registers. */
+ for (i = 0; i < __arraycount(regs); i++)
+ AR_WRITE(sc, regs[i], svg[i]);
+
+ /* Restore compensation capacitor value. */
+ AR_WRITE(sc, AR9285_AN_RF2G3, rf2g3_svg);
+ AR_WRITE_BARRIER(sc);
+#endif /* NATHN_USB */
+}
+
+/*
+ * Carrier Leakage Calibration.
+ */
+int
+ar9285_cl_cal(struct athn_softc *sc, struct ieee80211_channel *c,
+ struct ieee80211_channel *extc)
+{
+ int ntries;
+
+ AR_SETBITS(sc, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
+#ifndef IEEE80211_NO_HT
+ if (0 && extc == NULL) { /* XXX IS_CHAN_HT20!! */
+ AR_SETBITS(sc, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE);
+ AR_SETBITS(sc, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN);
+ AR_CLRBITS(sc, AR_PHY_AGC_CONTROL,
+ AR_PHY_AGC_CONTROL_FLTR_CAL);
+ AR_CLRBITS(sc, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE);
+ AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
+ for (ntries = 0; ntries < 10000; ntries++) {
+ if (!(AR_READ(sc, AR_PHY_AGC_CONTROL) &
+ AR_PHY_AGC_CONTROL_CAL))
+ break;
+ DELAY(10);
+ }
+ if (ntries == 10000)
+ return ETIMEDOUT;
+ AR_CLRBITS(sc, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN);
+ AR_CLRBITS(sc, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE);
+ AR_CLRBITS(sc, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
+ }
+#endif
+ AR_CLRBITS(sc, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
+ AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL);
+ AR_SETBITS(sc, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE);
+ AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
+ for (ntries = 0; ntries < 10000; ntries++) {
+ if (!(AR_READ(sc, AR_PHY_AGC_CONTROL) &
+ AR_PHY_AGC_CONTROL_CAL))
+ break;
+ DELAY(10);
+ }
+ if (ntries == 10000)
+ return ETIMEDOUT;
+ AR_SETBITS(sc, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
+ AR_CLRBITS(sc, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
+ AR_CLRBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL);
+ AR_WRITE_BARRIER(sc);
+ return 0;
+}
+
+PUBLIC void
+ar9271_load_ani(struct athn_softc *sc)
+{
+
+#if NATHN_USB > 0
+ /* Write ANI registers. */
+ AR_WRITE(sc, AR_PHY_DESIRED_SZ, 0x6d4000e2);
+ AR_WRITE(sc, AR_PHY_AGC_CTL1, 0x3139605e);
+ AR_WRITE(sc, AR_PHY_FIND_SIG, 0x7ec84d2e);
+ AR_WRITE(sc, AR_PHY_SFCORR_LOW, 0x06903881);
+ AR_WRITE(sc, AR_PHY_SFCORR, 0x5ac640d0);
+ AR_WRITE(sc, AR_PHY_CCK_DETECT, 0x803e68c8);
+ AR_WRITE(sc, AR_PHY_TIMING5, 0xd00a8007);
+ AR_WRITE(sc, AR_PHY_SFCORR_EXT, 0x05eea6d4);
+ AR_WRITE_BARRIER(sc);
+#endif /* NATHN_USB */
+}
+
+int
+ar9285_init_calib(struct athn_softc *sc, struct ieee80211_channel *c,
+ struct ieee80211_channel *extc)
+{
+ uint32_t reg, mask, clcgain, rf2g5_svg;
+ int i, maxgain, nclcs, thresh, error;
+
+ /* Do carrier leakage calibration. */
+ if ((error = ar9285_cl_cal(sc, c, extc)) != 0)
+ return error;
+
+ /* Workaround for high temperature is not applicable on AR9271. */
+ if (AR_SREV_9271(sc))
+ return 0;
+
+ mask = 0;
+ nclcs = 0;
+ reg = AR_READ(sc, AR_PHY_TX_PWRCTRL7);
+ maxgain = MS(reg, AR_PHY_TX_PWRCTRL_TX_GAIN_TAB_MAX);
+ for (i = 0; i <= maxgain; i++) {
+ reg = AR_READ(sc, AR_PHY_TX_GAIN_TBL(i));
+ clcgain = MS(reg, AR_PHY_TX_GAIN_CLC);
+ /* NB: clcgain <= 0xf. */
+ if (!(mask & (1 << clcgain))) {
+ mask |= 1 << clcgain;
+ nclcs++;
+ }
+ }
+ thresh = 0;
+ for (i = 0; i < nclcs; i++) {
+ reg = AR_READ(sc, AR_PHY_CLC_TBL(i));
+ if (MS(reg, AR_PHY_CLC_I0) == 0)
+ thresh++;
+ if (MS(reg, AR_PHY_CLC_Q0) == 0)
+ thresh++;
+ }
+ if (thresh <= AR9285_CL_CAL_REDO_THRESH)
+ return 0; /* No need to redo. */
+
+ /* Threshold reached, redo carrier leakage calibration. */
+ DPRINTFN(DBG_INIT, sc, "CLC threshold=%d\n", thresh);
+ rf2g5_svg = reg = AR_READ(sc, AR9285_AN_RF2G5);
+ if ((AR_READ(sc, AR_AN_SYNTH9) & 0x7) == 0x1) /* XE rev. */
+ reg = RW(reg, AR9285_AN_RF2G5_IC50TX, 0x5);
+ else
+ reg = RW(reg, AR9285_AN_RF2G5_IC50TX, 0x4);
+ AR_WRITE(sc, AR9285_AN_RF2G5, reg);
+ AR_WRITE_BARRIER(sc);
+ error = ar9285_cl_cal(sc, c, extc);
+ AR_WRITE(sc, AR9285_AN_RF2G5, rf2g5_svg);
+ AR_WRITE_BARRIER(sc);
+ return error;
+}
+
+Static void
+ar9285_get_pdadcs(struct athn_softc *sc, struct ieee80211_channel *c,
+ int nxpdgains, uint8_t overlap, uint8_t *boundaries, uint8_t *pdadcs)
+{
+ const struct ar9285_eeprom *eep = sc->sc_eep;
+ const struct ar9285_cal_data_per_freq *pierdata;
+ const uint8_t *pierfreq;
+ struct athn_pier lopier, hipier;
+ uint8_t fbin;
+ int i, lo, hi, npiers;
+
+ pierfreq = eep->calFreqPier2G;
+ pierdata = eep->calPierData2G;
+ npiers = AR9285_NUM_2G_CAL_PIERS;
+
+ /* Find channel in ROM pier table. */
+ fbin = athn_chan2fbin(c);
+ athn_get_pier_ival(fbin, pierfreq, npiers, &lo, &hi);
+
+ lopier.fbin = pierfreq[lo];
+ hipier.fbin = pierfreq[hi];
+ for (i = 0; i < nxpdgains; i++) {
+ lopier.pwr[i] = pierdata[lo].pwrPdg[i];
+ lopier.vpd[i] = pierdata[lo].vpdPdg[i];
+ hipier.pwr[i] = pierdata[lo].pwrPdg[i];
+ hipier.vpd[i] = pierdata[lo].vpdPdg[i];
+ }
+ ar5008_get_pdadcs(sc, fbin, &lopier, &hipier, nxpdgains,
+ AR9285_PD_GAIN_ICEPTS, overlap, boundaries, pdadcs);
+}
+
+Static void
+ar9285_set_power_calib(struct athn_softc *sc, struct ieee80211_channel *c)
+{
+ const struct ar9285_eeprom *eep = sc->sc_eep;
+ uint8_t boundaries[AR_PD_GAINS_IN_MASK];
+ uint8_t pdadcs[AR_NUM_PDADC_VALUES];
+ uint8_t xpdgains[AR9285_NUM_PD_GAINS];
+ uint8_t overlap;
+ uint32_t reg;
+ int i, nxpdgains;
+
+ if (sc->sc_eep_rev < AR_EEP_MINOR_VER_2) {
+ overlap = MS(AR_READ(sc, AR_PHY_TPCRG5),
+ AR_PHY_TPCRG5_PD_GAIN_OVERLAP);
+ }
+ else
+ overlap = eep->modalHeader.pdGainOverlap;
+
+ nxpdgains = 0;
+ memset(xpdgains, 0, sizeof(xpdgains));
+ for (i = AR9285_PD_GAINS_IN_MASK - 1; i >= 0; i--) {
+ if (nxpdgains >= AR9285_NUM_PD_GAINS)
+ break;
+ if (eep->modalHeader.xpdGain & (1 << i))
+ xpdgains[nxpdgains++] = i;
+ }
+ reg = AR_READ(sc, AR_PHY_TPCRG1);
+ reg = RW(reg, AR_PHY_TPCRG1_NUM_PD_GAIN, nxpdgains - 1);
+ reg = RW(reg, AR_PHY_TPCRG1_PD_GAIN_1, xpdgains[0]);
+ reg = RW(reg, AR_PHY_TPCRG1_PD_GAIN_2, xpdgains[1]);
+ AR_WRITE(sc, AR_PHY_TPCRG1, reg);
+
+ /* NB: No open loop power control for AR9285. */
+ ar9285_get_pdadcs(sc, c, nxpdgains, overlap, boundaries, pdadcs);
+
+ /* Write boundaries. */
+ reg = SM(AR_PHY_TPCRG5_PD_GAIN_OVERLAP, overlap);
+ reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1, boundaries[0]);
+ reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2, boundaries[1]);
+ reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3, boundaries[2]);
+ reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4, boundaries[3]);
+ AR_WRITE(sc, AR_PHY_TPCRG5, reg);
+
+ /* Write PDADC values. */
+ for (i = 0; i < AR_NUM_PDADC_VALUES; i += 4) {
+ AR_WRITE(sc, AR_PHY_PDADC_TBL_BASE + i,
+ pdadcs[i + 0] << 0 |
+ pdadcs[i + 1] << 8 |
+ pdadcs[i + 2] << 16 |
+ pdadcs[i + 3] << 24);
+ }
+ AR_WRITE_BARRIER(sc);
+}
+
+Static void
+ar9285_set_txpower(struct athn_softc *sc, struct ieee80211_channel *c,
+ struct ieee80211_channel *extc)
+{
+ const struct ar9285_eeprom *eep = sc->sc_eep;
+ const struct ar9285_modal_eep_header *modal = &eep->modalHeader;
+ uint8_t tpow_cck[4], tpow_ofdm[4];
+#ifndef IEEE80211_NO_HT
+ uint8_t tpow_cck_ext[4], tpow_ofdm_ext[4];
+ uint8_t tpow_ht20[8], tpow_ht40[8];
+ uint8_t ht40inc;
+#endif
+ int16_t max_ant_gain, power[ATHN_POWER_COUNT];
+ int i;
+
+ ar9285_set_power_calib(sc, c);
+
+ /* Compute transmit power reduction due to antenna gain. */
+ max_ant_gain = modal->antennaGain;
+ /* XXX */
+
+ /* Get CCK target powers. */
+ ar5008_get_lg_tpow(sc, c, AR_CTL_11B, eep->calTargetPowerCck,
+ AR9285_NUM_2G_CCK_TARGET_POWERS, tpow_cck);
+
+ /* Get OFDM target powers. */
+ ar5008_get_lg_tpow(sc, c, AR_CTL_11G, eep->calTargetPower2G,
+ AR9285_NUM_2G_20_TARGET_POWERS, tpow_ofdm);
+
+#ifndef IEEE80211_NO_HT
+ /* Get HT-20 target powers. */
+ ar5008_get_ht_tpow(sc, c, AR_CTL_2GHT20, eep->calTargetPower2GHT20,
+ AR9285_NUM_2G_20_TARGET_POWERS, tpow_ht20);
+
+ if (extc != NULL) {
+ /* Get HT-40 target powers. */
+ ar5008_get_ht_tpow(sc, c, AR_CTL_2GHT40,
+ eep->calTargetPower2GHT40, AR9285_NUM_2G_40_TARGET_POWERS,
+ tpow_ht40);
+
+ /* Get secondary channel CCK target powers. */
+ ar5008_get_lg_tpow(sc, extc, AR_CTL_11B,
+ eep->calTargetPowerCck, AR9285_NUM_2G_CCK_TARGET_POWERS,
+ tpow_cck_ext);
+
+ /* Get secondary channel OFDM target powers. */
+ ar5008_get_lg_tpow(sc, extc, AR_CTL_11G,
+ eep->calTargetPower2G, AR9285_NUM_2G_20_TARGET_POWERS,
+ tpow_ofdm_ext);
+ }
+#endif
+
+ memset(power, 0, sizeof(power));
+ /* Shuffle target powers accross transmit rates. */
+ power[ATHN_POWER_OFDM6 ] =
+ power[ATHN_POWER_OFDM9 ] =
+ power[ATHN_POWER_OFDM12 ] =
+ power[ATHN_POWER_OFDM18 ] =
+ power[ATHN_POWER_OFDM24 ] = tpow_ofdm[0];
+ power[ATHN_POWER_OFDM36 ] = tpow_ofdm[1];
+ power[ATHN_POWER_OFDM48 ] = tpow_ofdm[2];
+ power[ATHN_POWER_OFDM54 ] = tpow_ofdm[3];
+ power[ATHN_POWER_XR ] = tpow_ofdm[0];
+ power[ATHN_POWER_CCK1_LP ] = tpow_cck[0];
+ power[ATHN_POWER_CCK2_LP ] =
+ power[ATHN_POWER_CCK2_SP ] = tpow_cck[1];
+ power[ATHN_POWER_CCK55_LP] =
+ power[ATHN_POWER_CCK55_SP] = tpow_cck[2];
+ power[ATHN_POWER_CCK11_LP] =
+ power[ATHN_POWER_CCK11_SP] = tpow_cck[3];
+#ifndef IEEE80211_NO_HT
+ for (i = 0; i < __arraycount(tpow_ht20); i++)
+ power[ATHN_POWER_HT20(i)] = tpow_ht20[i];
+ if (extc != NULL) {
+ /* Correct PAR difference between HT40 and HT20/Legacy. */
+ if (sc->sc_eep_rev >= AR_EEP_MINOR_VER_2)
+ ht40inc = modal->ht40PowerIncForPdadc;
+ else
+ ht40inc = AR_HT40_POWER_INC_FOR_PDADC;
+ for (i = 0; i < __arraycount(tpow_ht40); i++)
+ power[ATHN_POWER_HT40(i)] = tpow_ht40[i] + ht40inc;
+ power[ATHN_POWER_OFDM_DUP] = tpow_ht40[0];
+ power[ATHN_POWER_CCK_DUP ] = tpow_ht40[0];
+ power[ATHN_POWER_OFDM_EXT] = tpow_ofdm_ext[0];
+ power[ATHN_POWER_CCK_EXT ] = tpow_cck_ext[0];
+ }
+#endif
+
+ for (i = 0; i < ATHN_POWER_COUNT; i++) {
+ power[i] -= AR_PWR_TABLE_OFFSET_DB * 2; /* In half dB. */
+ if (power[i] > AR_MAX_RATE_POWER)
+ power[i] = AR_MAX_RATE_POWER;
+ }
+
+ /* Commit transmit power values to hardware. */
+ ar5008_write_txpower(sc, power);
+}
diff --git a/sys/dev/ic/arn9285.h b/sys/dev/ic/arn9285.h
new file mode 100644
index 00000000000..4b06cce3371
--- /dev/null
+++ b/sys/dev/ic/arn9285.h
@@ -0,0 +1,38 @@
+/* $NetBSD: arn9285.h,v 1.1 2013/03/30 02:53:01 christos Exp $ */
+/*
+ * Copyright (c) 2001, 2004 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _IF_ARN9285_H_
+#define _IF_ARN9285_H_
+
+int ar9285_attach(struct athn_softc *);
+int ar9285_init_calib(struct athn_softc *, struct ieee80211_channel *,
+ struct ieee80211_channel *);
+void ar9285_pa_calib(struct athn_softc *);
+void ar9271_load_ani(struct athn_softc *);
+void ar9271_pa_calib(struct athn_softc *);
+
+#endif /* _IF_ARN9285_H_ */
diff --git a/sys/dev/ic/arn9285reg.h b/sys/dev/ic/arn9285reg.h
new file mode 100644
index 00000000000..10dc201d6cc
--- /dev/null
+++ b/sys/dev/ic/arn9285reg.h
@@ -0,0 +1,1093 @@
+/* $NetBSD: arn9285reg.h,v 1.1 2013/03/30 02:53:01 christos Exp $ */
+/* $OpenBSD: ar9285reg.h,v 1.7 2011/01/06 07:27:15 damien Exp $ */
+
+/*-
+ * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr>
+ * Copyright (c) 2008-2009 Atheros Communications Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _ARN9285REG_H_
+#define _ARN9285REG_H_
+
+#define AR9285_MAX_CHAINS 1
+
+#define AR9285_PHY_CCA_MAX_GOOD_VALUE (-118)
+
+#define AR9285_CL_CAL_REDO_THRESH 1
+
+/*
+ * Analog registers.
+ */
+#define AR9285_AN_RF2G1 0x7820
+#define AR9285_AN_RF2G2 0x7824
+#define AR9285_AN_RF2G3 0x7828
+#define AR9285_AN_RF2G4 0x782c
+#define AR9285_AN_RF2G5 0x7830
+#define AR9285_AN_RF2G6 0x7834
+#define AR9285_AN_RF2G7 0x7838
+#define AR9285_AN_RF2G8 0x783c
+#define AR9285_AN_RF2G9 0x7840
+#define AR9285_AN_RXTXBB1 0x7854
+#define AR9285_AN_TOP2 0x7868
+#define AR9285_AN_TOP3 0x786c
+#define AR9285_AN_TOP4 0x7870
+
+/* Bits for AR9285_AN_RF2G1. */
+#define AR9285_AN_RF2G1_ENPACAL 0x00000800
+#define AR9285_AN_RF2G1_PDPAOUT 0x00800000
+#define AR9285_AN_RF2G1_PDPADRV2 0x01000000
+#define AR9285_AN_RF2G1_PDPADRV1 0x02000000
+
+/* Bits for AR9285_AN_RF2G2. */
+#define AR9285_AN_RF2G2_OFFCAL 0x00001000
+
+/* Bits for AR9285_AN_RF2G3. */
+#define AR9285_AN_RF2G3_DB1_2_M 0x00000007
+#define AR9285_AN_RF2G3_DB1_2_S 0
+#define AR9285_AN_RF2G3_DB1_1_M 0x00000038
+#define AR9285_AN_RF2G3_DB1_1_S 3
+#define AR9285_AN_RF2G3_DB1_0_M 0x000001c0
+#define AR9285_AN_RF2G3_DB1_0_S 6
+#define AR9285_AN_RF2G3_OB_4_M 0x00000e00
+#define AR9285_AN_RF2G3_OB_4_S 9
+#define AR9285_AN_RF2G3_OB_3_M 0x00007000
+#define AR9285_AN_RF2G3_OB_3_S 12
+#define AR9285_AN_RF2G3_OB_2_M 0x00038000
+#define AR9285_AN_RF2G3_OB_2_S 15
+#define AR9285_AN_RF2G3_OB_1_M 0x001c0000
+#define AR9285_AN_RF2G3_OB_1_S 18
+#define AR9285_AN_RF2G3_OB_0_M 0x00e00000
+#define AR9285_AN_RF2G3_OB_0_S 21
+#define AR9285_AN_RF2G3_PDVCCOMP 0x02000000
+#define AR9271_AN_RF2G3_CCOMP_M 0x00000fff
+#define AR9271_AN_RF2G3_CCOMP_S 0
+#define AR9271_AN_RF2G3_OB_QAM_M 0x00007000
+#define AR9271_AN_RF2G3_OB_QAM_S 12
+#define AR9271_AN_RF2G3_OB_PSK_M 0x00038000
+#define AR9271_AN_RF2G3_OB_PSK_S 15
+#define AR9271_AN_RF2G3_OB_CCK_M 0x001c0000
+#define AR9271_AN_RF2G3_OB_CCK_S 18
+#define AR9271_AN_RF2G3_DB1_M 0x00e00000
+#define AR9271_AN_RF2G3_DB1_S 21
+
+/* Bits for AR9285_AN_RF2G4. */
+#define AR9285_AN_RF2G4_DB2_4_M 0x00003800
+#define AR9285_AN_RF2G4_DB2_4_S 11
+#define AR9285_AN_RF2G4_DB2_3_M 0x0001c000
+#define AR9285_AN_RF2G4_DB2_3_S 14
+#define AR9285_AN_RF2G4_DB2_2_M 0x000e0000
+#define AR9285_AN_RF2G4_DB2_2_S 17
+#define AR9285_AN_RF2G4_DB2_1_M 0x00700000
+#define AR9285_AN_RF2G4_DB2_1_S 20
+#define AR9285_AN_RF2G4_DB2_0_M 0x03800000
+#define AR9285_AN_RF2G4_DB2_0_S 23
+#define AR9285_AN_RF2G4_DB1_4_M 0x1c000000
+#define AR9285_AN_RF2G4_DB1_4_S 26
+#define AR9285_AN_RF2G4_DB1_3_M 0xe0000000
+#define AR9285_AN_RF2G4_DB1_3_S 29
+#define AR9271_AN_RF2G4_DB2_M 0xe0000000
+#define AR9271_AN_RF2G4_DB2_S 29
+
+/* Bits for AR9285_AN_RF2G5. */
+#define AR9285_AN_RF2G5_IC50TX_M 0x00000700
+#define AR9285_AN_RF2G5_IC50TX_S 8
+
+/* Bits for AR9285_AN_RF2G6. */
+#define AR9285_AN_RF2G6_CCOMP_M 0x00007800
+#define AR9285_AN_RF2G6_CCOMP_S 11
+#define AR9285_AN_RF2G6_OFFS_6_1 0x03f00000
+#define AR9285_AN_RF2G6_OFFS(i) (1 << (19 + (i)))
+#define AR9271_AN_RF2G6_OFFS_6_0 0x07f00000
+#define AR9271_AN_RF2G6_OFFS(i) (1 << (20 + (i)))
+
+/* Bits for AR9285_AN_RF2G7. */
+#define AR9285_AN_RF2G7_PWDDB 0x00000002
+#define AR9285_AN_RF2G7_PADRVGN2TAB0_M 0xe0000000
+#define AR9285_AN_RF2G7_PADRVGN2TAB0_S 29
+
+/* Bits for AR9285_AN_RF2G8. */
+#define AR9285_AN_RF2G8_PADRVGN2TAB0_M 0x0001c000
+#define AR9285_AN_RF2G8_PADRVGN2TAB0_S 14
+
+/* Bits for AR9285_AN_RXTXBB1. */
+#define AR9285_AN_RXTXBB1_SPARE9 0x00000001
+#define AR9285_AN_RXTXBB1_PDRXTXBB1 0x00000020
+#define AR9285_AN_RXTXBB1_PDV2I 0x00000080
+#define AR9285_AN_RXTXBB1_PDDACIF 0x00000100
+
+/* Bits for AR9285_AN_TOP2. */
+#define AR9285_AN_TOP2_DEFAULT 0xca0358a0 /* XXX magic */
+
+/* Bits for AR9285_AN_TOP3. */
+#define AR9285_AN_TOP3_XPABIAS_LVL_M 0x0000000c
+#define AR9285_AN_TOP3_XPABIAS_LVL_S 2
+#define AR9285_AN_TOP3_PWDDAC 0x00800000
+
+/* Bits for AR9285_AN_TOP4. */
+#define AR9285_AN_TOP4_DEFAULT 0x10142c00 /* XXX magic */
+#define AR9285_AN_TOP4_UNLOCKED 0x10142c14 /* XXX magic */
+
+/* Bits for AR_PHY_MULTICHAIN_GAIN_CTL. */
+#define AR9285_PHY_ANT_DIV_CTL_ALL_M 0x7f000000
+#define AR9285_PHY_ANT_DIV_CTL_ALL_S 24
+#define AR9285_PHY_ANT_DIV_CTL_M 0x01000000
+#define AR9285_PHY_ANT_DIV_CTL_S 24
+#define AR9285_PHY_ANT_DIV_ALT_LNACONF_M 0x06000000
+#define AR9285_PHY_ANT_DIV_ALT_LNACONF_S 25
+#define AR9285_PHY_ANT_DIV_MAIN_LNACONF_M 0x18000000
+#define AR9285_PHY_ANT_DIV_MAIN_LNACONF_S 27
+#define AR9285_PHY_ANT_DIV_ALT_GAINTB_M 0x20000000
+#define AR9285_PHY_ANT_DIV_ALT_GAINTB_S 29
+#define AR9285_PHY_ANT_DIV_MAIN_GAINTB_M 0x40000000
+#define AR9285_PHY_ANT_DIV_MAIN_GAINTB_S 30
+
+/*
+ * ROM layout used by AR9285 (single-stream, 2GHz only).
+ */
+#define AR9285_EEP_START_LOC 64
+#define AR9285_NUM_2G_CAL_PIERS 3
+#define AR9285_NUM_2G_CCK_TARGET_POWERS 3
+#define AR9285_NUM_2G_20_TARGET_POWERS 3
+#define AR9285_NUM_2G_40_TARGET_POWERS 3
+#define AR9285_NUM_CTLS 12
+#define AR9285_NUM_BAND_EDGES 4
+#define AR9285_NUM_PD_GAINS 2
+#define AR9285_PD_GAINS_IN_MASK 4
+#define AR9285_PD_GAIN_ICEPTS 5
+
+struct ar9285_base_eep_header {
+ uint16_t length;
+ uint16_t checksum;
+ uint16_t version;
+ uint8_t opCapFlags;
+ uint8_t eepMisc;
+ uint16_t regDmn[2];
+ uint8_t macAddr[6];
+ uint8_t rxMask;
+ uint8_t txMask;
+ uint16_t rfSilent;
+ uint16_t blueToothOptions;
+ uint16_t deviceCap;
+ uint32_t binBuildNumber;
+ uint8_t deviceType;
+ /* End of common header. */
+ uint8_t txGainType;
+} __packed;
+
+struct ar9285_modal_eep_header {
+ uint32_t antCtrlChain;
+ uint32_t antCtrlCommon;
+ uint8_t antennaGain;
+ uint8_t switchSettling;
+ uint8_t txRxAtten;
+ uint8_t rxTxMargin;
+ uint8_t adcDesiredSize;
+ uint8_t pgaDesiredSize;
+ uint8_t xlnaGain;
+ uint8_t txEndToXpaOff;
+ uint8_t txEndToRxOn;
+ uint8_t txFrameToXpaOn;
+ uint8_t thresh62;
+ uint8_t noiseFloorThresh;
+ uint8_t xpdGain;
+ uint8_t xpd;
+ uint8_t iqCalI;
+ uint8_t iqCalQ;
+ uint8_t pdGainOverlap;
+ uint8_t ob_01;
+ uint8_t db1_01;
+ uint8_t xpaBiasLvl;
+ uint8_t txFrameToDataStart;
+ uint8_t txFrameToPaOn;
+ uint8_t ht40PowerIncForPdadc;
+ uint8_t bswAtten;
+ uint8_t bswMargin;
+ uint8_t swSettleHt40;
+ uint8_t xatten2Db;
+ uint8_t xatten2Margin;
+ uint8_t db2_01;
+ uint8_t version;
+ uint16_t ob_234;
+ uint16_t db1_234;
+ uint16_t db2_234;
+ uint8_t futureModal[4];
+ struct ar_spur_chan spurChans[AR_EEPROM_MODAL_SPURS];
+} __packed;
+
+struct ar9285_cal_data_per_freq {
+ uint8_t pwrPdg[AR9285_NUM_PD_GAINS][AR9285_PD_GAIN_ICEPTS];
+ uint8_t vpdPdg[AR9285_NUM_PD_GAINS][AR9285_PD_GAIN_ICEPTS];
+} __packed;
+
+struct ar9285_cal_ctl_data {
+ struct ar_cal_ctl_edges ctlEdges[AR9285_NUM_BAND_EDGES];
+} __packed;
+
+struct ar9285_eeprom {
+ struct ar9285_base_eep_header baseEepHeader;
+ uint8_t custData[20];
+ struct ar9285_modal_eep_header modalHeader;
+ uint8_t calFreqPier2G[AR9285_NUM_2G_CAL_PIERS];
+ struct ar9285_cal_data_per_freq
+ calPierData2G[AR9285_NUM_2G_CAL_PIERS];
+ struct ar_cal_target_power_leg
+ calTargetPowerCck[AR9285_NUM_2G_CCK_TARGET_POWERS];
+ struct ar_cal_target_power_leg
+ calTargetPower2G[AR9285_NUM_2G_20_TARGET_POWERS];
+ struct ar_cal_target_power_ht
+ calTargetPower2GHT20[AR9285_NUM_2G_20_TARGET_POWERS];
+ struct ar_cal_target_power_ht
+ calTargetPower2GHT40[AR9285_NUM_2G_40_TARGET_POWERS];
+ uint8_t ctlIndex[AR9285_NUM_CTLS];
+ struct ar9285_cal_ctl_data ctlData[AR9285_NUM_CTLS];
+ uint8_t padding;
+} __packed;
+
+/* Macro to "pack" registers to 16-bit to save some .rodata space. */
+#define P(x) (x)
+
+/*
+ * AR9285 1.2 initialization values.
+ */
+static const uint16_t ar9285_1_2_regs[] = {
+ P(0x01030), P(0x01070), P(0x010b0), P(0x010f0), P(0x08014),
+ P(0x0801c), P(0x08318), P(0x09804), P(0x09820), P(0x09824),
+ P(0x09828), P(0x09834), P(0x09838), P(0x09840), P(0x09844),
+ P(0x09848), P(0x0a848), P(0x09850), P(0x09858), P(0x0985c),
+ P(0x09860), P(0x09864), P(0x09868), P(0x0986c), P(0x09914),
+ P(0x09918), P(0x09924), P(0x09944), P(0x09960), P(0x09964),
+ P(0x099b8), P(0x099bc), P(0x099c0), P(0x099c4), P(0x099c8),
+ P(0x099cc), P(0x099d0), P(0x099d4), P(0x099d8), P(0x09a00),
+ P(0x09a04), P(0x09a08), P(0x09a0c), P(0x09a10), P(0x09a14),
+ P(0x09a18), P(0x09a1c), P(0x09a20), P(0x09a24), P(0x09a28),
+ P(0x09a2c), P(0x09a30), P(0x09a34), P(0x09a38), P(0x09a3c),
+ P(0x09a40), P(0x09a44), P(0x09a48), P(0x09a4c), P(0x09a50),
+ P(0x09a54), P(0x09a58), P(0x09a5c), P(0x09a60), P(0x09a64),
+ P(0x09a68), P(0x09a6c), P(0x09a70), P(0x09a74), P(0x09a78),
+ P(0x09a7c), P(0x09a80), P(0x09a84), P(0x09a88), P(0x09a8c),
+ P(0x09a90), P(0x09a94), P(0x09a98), P(0x09a9c), P(0x09aa0),
+ P(0x09aa4), P(0x09aa8), P(0x09aac), P(0x09ab0), P(0x09ab4),
+ P(0x09ab8), P(0x09abc), P(0x09ac0), P(0x09ac4), P(0x09ac8),
+ P(0x09acc), P(0x09ad0), P(0x09ad4), P(0x09ad8), P(0x09adc),
+ P(0x09ae0), P(0x09ae4), P(0x09ae8), P(0x09aec), P(0x09af0),
+ P(0x09af4), P(0x09af8), P(0x09afc), P(0x09b00), P(0x09b04),
+ P(0x09b08), P(0x09b0c), P(0x09b10), P(0x09b14), P(0x09b18),
+ P(0x09b1c), P(0x09b20), P(0x09b24), P(0x09b28), P(0x09b2c),
+ P(0x09b30), P(0x09b34), P(0x09b38), P(0x09b3c), P(0x09b40),
+ P(0x09b44), P(0x09b48), P(0x09b4c), P(0x09b50), P(0x09b54),
+ P(0x09b58), P(0x09b5c), P(0x09b60), P(0x09b64), P(0x09b68),
+ P(0x09b6c), P(0x09b70), P(0x09b74), P(0x09b78), P(0x09b7c),
+ P(0x09b80), P(0x09b84), P(0x09b88), P(0x09b8c), P(0x09b90),
+ P(0x09b94), P(0x09b98), P(0x09b9c), P(0x09ba0), P(0x09ba4),
+ P(0x09ba8), P(0x09bac), P(0x09bb0), P(0x09bb4), P(0x09bb8),
+ P(0x09bbc), P(0x09bc0), P(0x09bc4), P(0x09bc8), P(0x09bcc),
+ P(0x09bd0), P(0x09bd4), P(0x09bd8), P(0x09bdc), P(0x09be0),
+ P(0x09be4), P(0x09be8), P(0x09bec), P(0x09bf0), P(0x09bf4),
+ P(0x09bf8), P(0x09bfc), P(0x0aa00), P(0x0aa04), P(0x0aa08),
+ P(0x0aa0c), P(0x0aa10), P(0x0aa14), P(0x0aa18), P(0x0aa1c),
+ P(0x0aa20), P(0x0aa24), P(0x0aa28), P(0x0aa2c), P(0x0aa30),
+ P(0x0aa34), P(0x0aa38), P(0x0aa3c), P(0x0aa40), P(0x0aa44),
+ P(0x0aa48), P(0x0aa4c), P(0x0aa50), P(0x0aa54), P(0x0aa58),
+ P(0x0aa5c), P(0x0aa60), P(0x0aa64), P(0x0aa68), P(0x0aa6c),
+ P(0x0aa70), P(0x0aa74), P(0x0aa78), P(0x0aa7c), P(0x0aa80),
+ P(0x0aa84), P(0x0aa88), P(0x0aa8c), P(0x0aa90), P(0x0aa94),
+ P(0x0aa98), P(0x0aa9c), P(0x0aaa0), P(0x0aaa4), P(0x0aaa8),
+ P(0x0aaac), P(0x0aab0), P(0x0aab4), P(0x0aab8), P(0x0aabc),
+ P(0x0aac0), P(0x0aac4), P(0x0aac8), P(0x0aacc), P(0x0aad0),
+ P(0x0aad4), P(0x0aad8), P(0x0aadc), P(0x0aae0), P(0x0aae4),
+ P(0x0aae8), P(0x0aaec), P(0x0aaf0), P(0x0aaf4), P(0x0aaf8),
+ P(0x0aafc), P(0x0ab00), P(0x0ab04), P(0x0ab08), P(0x0ab0c),
+ P(0x0ab10), P(0x0ab14), P(0x0ab18), P(0x0ab1c), P(0x0ab20),
+ P(0x0ab24), P(0x0ab28), P(0x0ab2c), P(0x0ab30), P(0x0ab34),
+ P(0x0ab38), P(0x0ab3c), P(0x0ab40), P(0x0ab44), P(0x0ab48),
+ P(0x0ab4c), P(0x0ab50), P(0x0ab54), P(0x0ab58), P(0x0ab5c),
+ P(0x0ab60), P(0x0ab64), P(0x0ab68), P(0x0ab6c), P(0x0ab70),
+ P(0x0ab74), P(0x0ab78), P(0x0ab7c), P(0x0ab80), P(0x0ab84),
+ P(0x0ab88), P(0x0ab8c), P(0x0ab90), P(0x0ab94), P(0x0ab98),
+ P(0x0ab9c), P(0x0aba0), P(0x0aba4), P(0x0aba8), P(0x0abac),
+ P(0x0abb0), P(0x0abb4), P(0x0abb8), P(0x0abbc), P(0x0abc0),
+ P(0x0abc4), P(0x0abc8), P(0x0abcc), P(0x0abd0), P(0x0abd4),
+ P(0x0abd8), P(0x0abdc), P(0x0abe0), P(0x0abe4), P(0x0abe8),
+ P(0x0abec), P(0x0abf0), P(0x0abf4), P(0x0abf8), P(0x0abfc),
+ P(0x0a204), P(0x0a20c), P(0x0b20c), P(0x0a21c), P(0x0a230),
+ P(0x0a250), P(0x0a358)
+};
+
+#ifndef IEEE80211_NO_HT
+static const uint32_t ar9285_1_2_vals_2g40[] = {
+ 0x000002c0, 0x00000318, 0x00007c70, 0x00000000, 0x10801600,
+ 0x12e00057, 0x00006880, 0x000003c4, 0x02020200, 0x01000e0e,
+ 0x0a020001, 0x00000e0e, 0x00000007, 0x206a012e, 0x03721620,
+ 0x00001053, 0x00001053, 0x6d4000e2, 0x7ec84d2e, 0x3137605e,
+ 0x00058d20, 0x0001ce00, 0x5ac640d0, 0x06903881, 0x00001130,
+ 0x00000016, 0xd00a800d, 0xffbc1020, 0x00000000, 0x00000000,
+ 0x0000421c, 0x00000c00, 0x05eea6d4, 0x06336f77, 0x6af6532f,
+ 0x08f186c8, 0x00046384, 0x00000000, 0x00000000, 0x00058084,
+ 0x00058088, 0x0005808c, 0x00058100, 0x00058104, 0x00058108,
+ 0x0005810c, 0x00058110, 0x00058114, 0x00058180, 0x00058184,
+ 0x00058188, 0x0005818c, 0x00058190, 0x00058194, 0x000581a0,
+ 0x0005820c, 0x000581a8, 0x00058284, 0x00058288, 0x00058224,
+ 0x00058290, 0x00058300, 0x00058304, 0x00058308, 0x0005830c,
+ 0x00058380, 0x00058384, 0x00068700, 0x00068704, 0x00068708,
+ 0x0006870c, 0x00068780, 0x00068784, 0x00078b00, 0x00078b04,
+ 0x00078b08, 0x00078b0c, 0x00078b80, 0x00078b84, 0x00078b88,
+ 0x00078b8c, 0x00078b90, 0x000caf80, 0x000caf84, 0x000caf88,
+ 0x000caf8c, 0x000caf90, 0x000db30c, 0x000db310, 0x000db384,
+ 0x000db388, 0x000db324, 0x000eb704, 0x000eb6a4, 0x000eb6a8,
+ 0x000eb710, 0x000eb714, 0x000eb720, 0x000eb724, 0x000eb728,
+ 0x000eb72c, 0x000eb7a0, 0x000eb7a4, 0x000eb7a8, 0x000eb7b0,
+ 0x000eb7b4, 0x000eb7b8, 0x000eb7a5, 0x000eb7a9, 0x000eb7ad,
+ 0x000eb7b1, 0x000eb7b5, 0x000eb7b9, 0x000eb7c5, 0x000eb7c9,
+ 0x000eb7d1, 0x000eb7d5, 0x000eb7d9, 0x000eb7c6, 0x000eb7ca,
+ 0x000eb7ce, 0x000eb7d2, 0x000eb7d6, 0x000eb7c3, 0x000eb7c7,
+ 0x000eb7cb, 0x000eb7cf, 0x000eb7d7, 0x000eb7db, 0x000eb7db,
+ 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db,
+ 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db,
+ 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db,
+ 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db,
+ 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db,
+ 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db,
+ 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db,
+ 0x000eb7db, 0x000eb7db, 0x00058084, 0x00058088, 0x0005808c,
+ 0x00058100, 0x00058104, 0x00058108, 0x0005810c, 0x00058110,
+ 0x00058114, 0x00058180, 0x00058184, 0x00058188, 0x0005818c,
+ 0x00058190, 0x00058194, 0x000581a0, 0x0005820c, 0x000581a8,
+ 0x00058284, 0x00058288, 0x00058224, 0x00058290, 0x00058300,
+ 0x00058304, 0x00058308, 0x0005830c, 0x00058380, 0x00058384,
+ 0x00068700, 0x00068704, 0x00068708, 0x0006870c, 0x00068780,
+ 0x00068784, 0x00078b00, 0x00078b04, 0x00078b08, 0x00078b0c,
+ 0x00078b80, 0x00078b84, 0x00078b88, 0x00078b8c, 0x00078b90,
+ 0x000caf80, 0x000caf84, 0x000caf88, 0x000caf8c, 0x000caf90,
+ 0x000db30c, 0x000db310, 0x000db384, 0x000db388, 0x000db324,
+ 0x000eb704, 0x000eb6a4, 0x000eb6a8, 0x000eb710, 0x000eb714,
+ 0x000eb720, 0x000eb724, 0x000eb728, 0x000eb72c, 0x000eb7a0,
+ 0x000eb7a4, 0x000eb7a8, 0x000eb7b0, 0x000eb7b4, 0x000eb7b8,
+ 0x000eb7a5, 0x000eb7a9, 0x000eb7ad, 0x000eb7b1, 0x000eb7b5,
+ 0x000eb7b9, 0x000eb7c5, 0x000eb7c9, 0x000eb7d1, 0x000eb7d5,
+ 0x000eb7d9, 0x000eb7c6, 0x000eb7ca, 0x000eb7ce, 0x000eb7d2,
+ 0x000eb7d6, 0x000eb7c3, 0x000eb7c7, 0x000eb7cb, 0x000eb7cf,
+ 0x000eb7d7, 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db,
+ 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db,
+ 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db,
+ 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db,
+ 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db,
+ 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db,
+ 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db,
+ 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db,
+ 0x00000004, 0x0001f000, 0x0001f000, 0x1883800a, 0x00000210,
+ 0x0004a000, 0x7999aa0e
+};
+#endif
+
+static const uint32_t ar9285_1_2_vals_2g20[] = {
+ 0x00000160, 0x0000018c, 0x00003e38, 0x00000000, 0x08400b00,
+ 0x12e0002b, 0x00003440, 0x00000300, 0x02020200, 0x01000e0e,
+ 0x0a020001, 0x00000e0e, 0x00000007, 0x206a012e, 0x03721620,
+ 0x00001053, 0x00001053, 0x6d4000e2, 0x7ec84d2e, 0x3137605e,
+ 0x00058d20, 0x0001ce00, 0x5ac640d0, 0x06903881, 0x00000898,
+ 0x0000000b, 0xd00a800d, 0xffbc1020, 0x00000000, 0x00000000,
+ 0x0000421c, 0x00000c00, 0x05eea6d4, 0x06336f77, 0x6af6532f,
+ 0x08f186c8, 0x00046384, 0x00000000, 0x00000000, 0x00058084,
+ 0x00058088, 0x0005808c, 0x00058100, 0x00058104, 0x00058108,
+ 0x0005810c, 0x00058110, 0x00058114, 0x00058180, 0x00058184,
+ 0x00058188, 0x0005818c, 0x00058190, 0x00058194, 0x000581a0,
+ 0x0005820c, 0x000581a8, 0x00058284, 0x00058288, 0x00058224,
+ 0x00058290, 0x00058300, 0x00058304, 0x00058308, 0x0005830c,
+ 0x00058380, 0x00058384, 0x00068700, 0x00068704, 0x00068708,
+ 0x0006870c, 0x00068780, 0x00068784, 0x00078b00, 0x00078b04,
+ 0x00078b08, 0x00078b0c, 0x00078b80, 0x00078b84, 0x00078b88,
+ 0x00078b8c, 0x00078b90, 0x000caf80, 0x000caf84, 0x000caf88,
+ 0x000caf8c, 0x000caf90, 0x000db30c, 0x000db310, 0x000db384,
+ 0x000db388, 0x000db324, 0x000eb704, 0x000eb6a4, 0x000eb6a8,
+ 0x000eb710, 0x000eb714, 0x000eb720, 0x000eb724, 0x000eb728,
+ 0x000eb72c, 0x000eb7a0, 0x000eb7a4, 0x000eb7a8, 0x000eb7b0,
+ 0x000eb7b4, 0x000eb7b8, 0x000eb7a5, 0x000eb7a9, 0x000eb7ad,
+ 0x000eb7b1, 0x000eb7b5, 0x000eb7b9, 0x000eb7c5, 0x000eb7c9,
+ 0x000eb7d1, 0x000eb7d5, 0x000eb7d9, 0x000eb7c6, 0x000eb7ca,
+ 0x000eb7ce, 0x000eb7d2, 0x000eb7d6, 0x000eb7c3, 0x000eb7c7,
+ 0x000eb7cb, 0x000eb7cf, 0x000eb7d7, 0x000eb7db, 0x000eb7db,
+ 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db,
+ 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db,
+ 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db,
+ 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db,
+ 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db,
+ 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db,
+ 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db,
+ 0x000eb7db, 0x000eb7db, 0x00058084, 0x00058088, 0x0005808c,
+ 0x00058100, 0x00058104, 0x00058108, 0x0005810c, 0x00058110,
+ 0x00058114, 0x00058180, 0x00058184, 0x00058188, 0x0005818c,
+ 0x00058190, 0x00058194, 0x000581a0, 0x0005820c, 0x000581a8,
+ 0x00058284, 0x00058288, 0x00058224, 0x00058290, 0x00058300,
+ 0x00058304, 0x00058308, 0x0005830c, 0x00058380, 0x00058384,
+ 0x00068700, 0x00068704, 0x00068708, 0x0006870c, 0x00068780,
+ 0x00068784, 0x00078b00, 0x00078b04, 0x00078b08, 0x00078b0c,
+ 0x00078b80, 0x00078b84, 0x00078b88, 0x00078b8c, 0x00078b90,
+ 0x000caf80, 0x000caf84, 0x000caf88, 0x000caf8c, 0x000caf90,
+ 0x000db30c, 0x000db310, 0x000db384, 0x000db388, 0x000db324,
+ 0x000eb704, 0x000eb6a4, 0x000eb6a8, 0x000eb710, 0x000eb714,
+ 0x000eb720, 0x000eb724, 0x000eb728, 0x000eb72c, 0x000eb7a0,
+ 0x000eb7a4, 0x000eb7a8, 0x000eb7b0, 0x000eb7b4, 0x000eb7b8,
+ 0x000eb7a5, 0x000eb7a9, 0x000eb7ad, 0x000eb7b1, 0x000eb7b5,
+ 0x000eb7b9, 0x000eb7c5, 0x000eb7c9, 0x000eb7d1, 0x000eb7d5,
+ 0x000eb7d9, 0x000eb7c6, 0x000eb7ca, 0x000eb7ce, 0x000eb7d2,
+ 0x000eb7d6, 0x000eb7c3, 0x000eb7c7, 0x000eb7cb, 0x000eb7cf,
+ 0x000eb7d7, 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db,
+ 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db,
+ 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db,
+ 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db,
+ 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db,
+ 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db,
+ 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db,
+ 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db,
+ 0x00000004, 0x0001f000, 0x0001f000, 0x1883800a, 0x00000108,
+ 0x0004a000, 0x7999aa0e
+};
+
+static const uint16_t ar9285_1_2_cm_regs[] = {
+ P(0x0000c), P(0x00030), P(0x00034), P(0x00040), P(0x00044),
+ P(0x00048), P(0x0004c), P(0x00050), P(0x00054), P(0x00800),
+ P(0x00804), P(0x00808), P(0x0080c), P(0x00810), P(0x00814),
+ P(0x00818), P(0x0081c), P(0x00820), P(0x00824), P(0x01040),
+ P(0x01044), P(0x01048), P(0x0104c), P(0x01050), P(0x01054),
+ P(0x01058), P(0x0105c), P(0x01060), P(0x01064), P(0x01230),
+ P(0x01270), P(0x01038), P(0x01078), P(0x010b8), P(0x010f8),
+ P(0x01138), P(0x01178), P(0x011b8), P(0x011f8), P(0x01238),
+ P(0x01278), P(0x012b8), P(0x012f8), P(0x01338), P(0x01378),
+ P(0x013b8), P(0x013f8), P(0x01438), P(0x01478), P(0x014b8),
+ P(0x014f8), P(0x01538), P(0x01578), P(0x015b8), P(0x015f8),
+ P(0x01638), P(0x01678), P(0x016b8), P(0x016f8), P(0x01738),
+ P(0x01778), P(0x017b8), P(0x017f8), P(0x0103c), P(0x0107c),
+ P(0x010bc), P(0x010fc), P(0x0113c), P(0x0117c), P(0x011bc),
+ P(0x011fc), P(0x0123c), P(0x0127c), P(0x012bc), P(0x012fc),
+ P(0x0133c), P(0x0137c), P(0x013bc), P(0x013fc), P(0x0143c),
+ P(0x0147c), P(0x04030), P(0x0403c), P(0x04024), P(0x04060),
+ P(0x04064), P(0x07010), P(0x07034), P(0x07038), P(0x08004),
+ P(0x08008), P(0x0800c), P(0x08018), P(0x08020), P(0x08038),
+ P(0x0803c), P(0x08048), P(0x08054), P(0x08058), P(0x0805c),
+ P(0x08060), P(0x08064), P(0x08070), P(0x080c0), P(0x080c4),
+ P(0x080c8), P(0x080cc), P(0x080d0), P(0x080d4), P(0x080d8),
+ P(0x080e0), P(0x080e4), P(0x080e8), P(0x080ec), P(0x080f0),
+ P(0x080f4), P(0x080f8), P(0x080fc), P(0x08100), P(0x08104),
+ P(0x08108), P(0x0810c), P(0x08110), P(0x08118), P(0x0811c),
+ P(0x08120), P(0x08124), P(0x08128), P(0x0812c), P(0x08130),
+ P(0x08134), P(0x08138), P(0x0813c), P(0x08144), P(0x08168),
+ P(0x0816c), P(0x08170), P(0x08174), P(0x08178), P(0x0817c),
+ P(0x081c0), P(0x081d0), P(0x081ec), P(0x081f0), P(0x081f4),
+ P(0x081f8), P(0x081fc), P(0x08200), P(0x08204), P(0x08208),
+ P(0x0820c), P(0x08210), P(0x08214), P(0x08218), P(0x0821c),
+ P(0x08220), P(0x08224), P(0x08228), P(0x0822c), P(0x08230),
+ P(0x08234), P(0x08238), P(0x0823c), P(0x08240), P(0x08244),
+ P(0x08248), P(0x0824c), P(0x08250), P(0x08254), P(0x08258),
+ P(0x0825c), P(0x08260), P(0x08264), P(0x08270), P(0x08274),
+ P(0x08278), P(0x0827c), P(0x08284), P(0x08288), P(0x0828c),
+ P(0x08294), P(0x08298), P(0x0829c), P(0x08300), P(0x08314),
+ P(0x08328), P(0x0832c), P(0x08330), P(0x08334), P(0x08338),
+ P(0x0833c), P(0x08340), P(0x08344), P(0x09808), P(0x0980c),
+ P(0x09810), P(0x09814), P(0x0981c), P(0x0982c), P(0x09830),
+ P(0x0983c), P(0x0984c), P(0x09854), P(0x09900), P(0x09904),
+ P(0x09908), P(0x0990c), P(0x09910), P(0x0991c), P(0x09920),
+ P(0x09928), P(0x0992c), P(0x09934), P(0x09938), P(0x0993c),
+ P(0x09940), P(0x09948), P(0x0994c), P(0x09954), P(0x09958),
+ P(0x09968), P(0x09970), P(0x09974), P(0x09978), P(0x0997c),
+ P(0x09980), P(0x09984), P(0x09988), P(0x0998c), P(0x09990),
+ P(0x09994), P(0x09998), P(0x0999c), P(0x099a0), P(0x099a4),
+ P(0x099a8), P(0x099ac), P(0x099b0), P(0x099b4), P(0x099dc),
+ P(0x099e0), P(0x099e4), P(0x099e8), P(0x099ec), P(0x099f0),
+ P(0x0a208), P(0x0a210), P(0x0a214), P(0x0a218), P(0x0a220),
+ P(0x0a224), P(0x0a228), P(0x0a22c), P(0x0a234), P(0x0a238),
+ P(0x0a244), P(0x0a248), P(0x0a24c), P(0x0a254), P(0x0a258),
+ P(0x0a25c), P(0x0a260), P(0x0a268), P(0x0a26c), P(0x0d270),
+ P(0x0d35c), P(0x0d360), P(0x0d364), P(0x0d368), P(0x0d36c),
+ P(0x0d370), P(0x0d374), P(0x0d378), P(0x0d37c), P(0x0d380),
+ P(0x0d384), P(0x0a388), P(0x0a38c), P(0x0a390), P(0x0a39c),
+ P(0x0a3a0), P(0x0a3a4), P(0x0a3a8), P(0x0a3ac), P(0x0a3b0),
+ P(0x0a3b4), P(0x0a3b8), P(0x0a3bc), P(0x0a3c0), P(0x0a3c4),
+ P(0x0a3cc), P(0x0a3d0), P(0x0a3d4), P(0x0a3e4), P(0x0a3e8),
+ P(0x0a3ec), P(0x07800), P(0x07804), P(0x07808), P(0x0780c),
+ P(0x07810), P(0x0781c), P(0x07824), P(0x0782c), P(0x07834),
+ P(0x07844), P(0x07848), P(0x0784c), P(0x07850), P(0x07854),
+ P(0x07858), P(0x0785c), P(0x07860), P(0x07864), P(0x07868),
+ P(0x07870)
+};
+
+static const uint32_t ar9285_1_2_cm_vals[] = {
+ 0x00000000, 0x00020045, 0x00000005, 0x00000000, 0x00000008,
+ 0x00000008, 0x00000010, 0x00000000, 0x0000001f, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x002ffc0f,
+ 0x002ffc0f, 0x002ffc0f, 0x002ffc0f, 0x002ffc0f, 0x002ffc0f,
+ 0x002ffc0f, 0x002ffc0f, 0x002ffc0f, 0x002ffc0f, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000002, 0x00000002, 0x0000001f, 0x00000000,
+ 0x00000000, 0x00000031, 0x00000002, 0x000004c2, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000700, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000fc78f,
+ 0x0000000f, 0x00000000, 0x00000000, 0x2a80001a, 0x05dc01e0,
+ 0x1f402710, 0x01f40000, 0x00001e00, 0x00000000, 0x00400000,
+ 0xffffffff, 0x0000ffff, 0x003f3f3f, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00020000, 0x00020000, 0x00000001,
+ 0x00000052, 0x00000000, 0x00000168, 0x000100aa, 0x00003210,
+ 0x08f04810, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0xffffffff, 0x00000000,
+ 0x00000000, 0x32143320, 0xfaa4fa50, 0x00000100, 0x00000000,
+ 0x00000000, 0x0000320a, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00100000, 0x0010f400,
+ 0x00000100, 0x0001e800, 0x00000000, 0x00000000, 0x00000000,
+ 0x400000ff, 0x00080922, 0x88a00010, 0x00000000, 0x40000000,
+ 0x003e4180, 0x00000000, 0x0000002c, 0x0000002c, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000040, 0x00000000,
+ 0x00000000, 0x00000001, 0x00000302, 0x00000e00, 0x00ff0000,
+ 0x00000000, 0x00010380, 0x00481043, 0x00000000, 0xafe68e30,
+ 0xfd14e000, 0x9c0a9f6b, 0x00000000, 0x0000a000, 0x00000000,
+ 0x00200400, 0x0040233c, 0x00000044, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x01002310, 0x10000fff, 0x04900000,
+ 0x00000001, 0x00000004, 0x1e1f2022, 0x0a0b0c0d, 0x00000000,
+ 0x14750604, 0x9280c00a, 0x00020028, 0x5f3ca3de, 0x2108ecff,
+ 0x000003ce, 0x192bb514, 0x00000000, 0x00000001, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000001,
+ 0x201fff00, 0x2def0400, 0x03051000, 0x00000820, 0x00000000,
+ 0x00000000, 0xaaaaaaaa, 0x3c466478, 0x0cc80caa, 0x00000000,
+ 0x803e68c8, 0x4080a333, 0x00206c10, 0x009c4060, 0x01834061,
+ 0x00000400, 0x000003b5, 0x00000000, 0x20202020, 0x20202020,
+ 0x00000000, 0xfffffffc, 0x00000000, 0x00000000, 0x0ccb5380,
+ 0x15151501, 0xdfa90f01, 0x00000000, 0x0ebae9e6, 0x0d820820,
+ 0x07ffffef, 0x0fffffe7, 0x17ffffe5, 0x1fffffe4, 0x37ffffe3,
+ 0x3fffffe3, 0x57ffffe3, 0x5fffffe2, 0x7fffffe2, 0x7f3c7bba,
+ 0xf3307ff0, 0x0c000000, 0x20202020, 0x20202020, 0x00000001,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x20202020, 0x20202020, 0x20202020, 0x00000000, 0x18c43433,
+ 0x00f70081, 0x00140000, 0x0e4548d8, 0x54214514, 0x02025830,
+ 0x71c0d388, 0x00000000, 0x00d86fff, 0x6e36d97b, 0x71400087,
+ 0x000c0db6, 0x6db6246f, 0x6d9b66db, 0x6d8c6dba, 0x00040000,
+ 0xdb003012, 0x04924914, 0x21084210, 0xf7d7ffde, 0xc2034080,
+ 0x10142c00
+};
+
+static const struct athn_ini ar9285_1_2_ini = {
+ .nregs = __arraycount(ar9285_1_2_regs),
+ .regs = ar9285_1_2_regs,
+ .vals_5g20 = NULL, /* 2GHz only. */
+#ifndef IEEE80211_NO_HT
+ .vals_5g40 = NULL, /* 2GHz only. */
+ .vals_2g40 = ar9285_1_2_vals_2g40,
+#endif
+ .vals_2g20 = ar9285_1_2_vals_2g20,
+ .ncmregs = __arraycount(ar9285_1_2_cm_regs),
+ .cmregs = ar9285_1_2_cm_regs,
+ .cmvals = ar9285_1_2_cm_vals,
+};
+
+#if NATHN_USB > 0
+/*
+ * AR9271 programming.
+ */
+static const uint16_t ar9271_regs[] = {
+ P(0x01030), P(0x01070), P(0x010b0), P(0x010f0), P(0x08014),
+ P(0x0801c), P(0x08318), P(0x09804), P(0x09820), P(0x09824),
+ P(0x09828), P(0x09834), P(0x09838), P(0x09840), P(0x09844),
+ P(0x09848), P(0x0a848), P(0x09850), P(0x09858), P(0x0985c),
+ P(0x09860), P(0x09864), P(0x09868), P(0x0986c), P(0x09910),
+ P(0x09914), P(0x09918), P(0x09924), P(0x09944), P(0x09960),
+ P(0x09964), P(0x099b8), P(0x099bc), P(0x099c0), P(0x099c4),
+ P(0x099c8), P(0x099cc), P(0x099d0), P(0x099d4), P(0x099d8),
+ P(0x09a00), P(0x09a04), P(0x09a08), P(0x09a0c), P(0x09a10),
+ P(0x09a14), P(0x09a18), P(0x09a1c), P(0x09a20), P(0x09a24),
+ P(0x09a28), P(0x09a2c), P(0x09a30), P(0x09a34), P(0x09a38),
+ P(0x09a3c), P(0x09a40), P(0x09a44), P(0x09a48), P(0x09a4c),
+ P(0x09a50), P(0x09a54), P(0x09a58), P(0x09a5c), P(0x09a60),
+ P(0x09a64), P(0x09a68), P(0x09a6c), P(0x09a70), P(0x09a74),
+ P(0x09a78), P(0x09a7c), P(0x09a80), P(0x09a84), P(0x09a88),
+ P(0x09a8c), P(0x09a90), P(0x09a94), P(0x09a98), P(0x09a9c),
+ P(0x09aa0), P(0x09aa4), P(0x09aa8), P(0x09aac), P(0x09ab0),
+ P(0x09ab4), P(0x09ab8), P(0x09abc), P(0x09ac0), P(0x09ac4),
+ P(0x09ac8), P(0x09acc), P(0x09ad0), P(0x09ad4), P(0x09ad8),
+ P(0x09adc), P(0x09ae0), P(0x09ae4), P(0x09ae8), P(0x09aec),
+ P(0x09af0), P(0x09af4), P(0x09af8), P(0x09afc), P(0x09b00),
+ P(0x09b04), P(0x09b08), P(0x09b0c), P(0x09b10), P(0x09b14),
+ P(0x09b18), P(0x09b1c), P(0x09b20), P(0x09b24), P(0x09b28),
+ P(0x09b2c), P(0x09b30), P(0x09b34), P(0x09b38), P(0x09b3c),
+ P(0x09b40), P(0x09b44), P(0x09b48), P(0x09b4c), P(0x09b50),
+ P(0x09b54), P(0x09b58), P(0x09b5c), P(0x09b60), P(0x09b64),
+ P(0x09b68), P(0x09b6c), P(0x09b70), P(0x09b74), P(0x09b78),
+ P(0x09b7c), P(0x09b80), P(0x09b84), P(0x09b88), P(0x09b8c),
+ P(0x09b90), P(0x09b94), P(0x09b98), P(0x09b9c), P(0x09ba0),
+ P(0x09ba4), P(0x09ba8), P(0x09bac), P(0x09bb0), P(0x09bb4),
+ P(0x09bb8), P(0x09bbc), P(0x09bc0), P(0x09bc4), P(0x09bc8),
+ P(0x09bcc), P(0x09bd0), P(0x09bd4), P(0x09bd8), P(0x09bdc),
+ P(0x09be0), P(0x09be4), P(0x09be8), P(0x09bec), P(0x09bf0),
+ P(0x09bf4), P(0x09bf8), P(0x09bfc), P(0x0aa00), P(0x0aa04),
+ P(0x0aa08), P(0x0aa0c), P(0x0aa10), P(0x0aa14), P(0x0aa18),
+ P(0x0aa1c), P(0x0aa20), P(0x0aa24), P(0x0aa28), P(0x0aa2c),
+ P(0x0aa30), P(0x0aa34), P(0x0aa38), P(0x0aa3c), P(0x0aa40),
+ P(0x0aa44), P(0x0aa48), P(0x0aa4c), P(0x0aa50), P(0x0aa54),
+ P(0x0aa58), P(0x0aa5c), P(0x0aa60), P(0x0aa64), P(0x0aa68),
+ P(0x0aa6c), P(0x0aa70), P(0x0aa74), P(0x0aa78), P(0x0aa7c),
+ P(0x0aa80), P(0x0aa84), P(0x0aa88), P(0x0aa8c), P(0x0aa90),
+ P(0x0aa94), P(0x0aa98), P(0x0aa9c), P(0x0aaa0), P(0x0aaa4),
+ P(0x0aaa8), P(0x0aaac), P(0x0aab0), P(0x0aab4), P(0x0aab8),
+ P(0x0aabc), P(0x0aac0), P(0x0aac4), P(0x0aac8), P(0x0aacc),
+ P(0x0aad0), P(0x0aad4), P(0x0aad8), P(0x0aadc), P(0x0aae0),
+ P(0x0aae4), P(0x0aae8), P(0x0aaec), P(0x0aaf0), P(0x0aaf4),
+ P(0x0aaf8), P(0x0aafc), P(0x0ab00), P(0x0ab04), P(0x0ab08),
+ P(0x0ab0c), P(0x0ab10), P(0x0ab14), P(0x0ab18), P(0x0ab1c),
+ P(0x0ab20), P(0x0ab24), P(0x0ab28), P(0x0ab2c), P(0x0ab30),
+ P(0x0ab34), P(0x0ab38), P(0x0ab3c), P(0x0ab40), P(0x0ab44),
+ P(0x0ab48), P(0x0ab4c), P(0x0ab50), P(0x0ab54), P(0x0ab58),
+ P(0x0ab5c), P(0x0ab60), P(0x0ab64), P(0x0ab68), P(0x0ab6c),
+ P(0x0ab70), P(0x0ab74), P(0x0ab78), P(0x0ab7c), P(0x0ab80),
+ P(0x0ab84), P(0x0ab88), P(0x0ab8c), P(0x0ab90), P(0x0ab94),
+ P(0x0ab98), P(0x0ab9c), P(0x0aba0), P(0x0aba4), P(0x0aba8),
+ P(0x0abac), P(0x0abb0), P(0x0abb4), P(0x0abb8), P(0x0abbc),
+ P(0x0abc0), P(0x0abc4), P(0x0abc8), P(0x0abcc), P(0x0abd0),
+ P(0x0abd4), P(0x0abd8), P(0x0abdc), P(0x0abe0), P(0x0abe4),
+ P(0x0abe8), P(0x0abec), P(0x0abf0), P(0x0abf4), P(0x0abf8),
+ P(0x0abfc), P(0x0a204), P(0x0a20c), P(0x0b20c), P(0x0a21c),
+ P(0x0a230), P(0x0a250), P(0x0a358)
+};
+
+#ifndef IEEE80211_NO_HT
+static const uint32_t ar9271_vals_2g40[] = {
+ 0x000002c0, 0x00000318, 0x00007c70, 0x00000000, 0x10801600,
+ 0x12e00057, 0x00006880, 0x000003c4, 0x02020200, 0x01000e0e,
+ 0x3a020001, 0x00000e0e, 0x00000007, 0x206a012e, 0x03721620,
+ 0x00001053, 0x00001053, 0x6d4000e2, 0x7ec84d2e, 0x3137605e,
+ 0x00058d18, 0x0001ce00, 0x5ac640d0, 0x06903881, 0x30002310,
+ 0x00001130, 0x00000016, 0xd00a800d, 0xffbc1020, 0x00000000,
+ 0x00000000, 0x0000421c, 0x00000c00, 0x05eea6d4, 0x06336f77,
+ 0x6af6532f, 0x08f186c8, 0x00046384, 0x00000000, 0x00000000,
+ 0x00058084, 0x00058088, 0x0005808c, 0x00058100, 0x00058104,
+ 0x00058108, 0x0005810c, 0x00058110, 0x00058114, 0x00058180,
+ 0x00058184, 0x00058188, 0x0005818c, 0x00058190, 0x00058194,
+ 0x000581a0, 0x0005820c, 0x000581a8, 0x00058284, 0x00058288,
+ 0x00058224, 0x00058290, 0x00058300, 0x00058304, 0x00058308,
+ 0x0005830c, 0x00058380, 0x00058384, 0x00068700, 0x00068704,
+ 0x00068708, 0x0006870c, 0x00068780, 0x00068784, 0x00078b00,
+ 0x00078b04, 0x00078b08, 0x00078b0c, 0x00078b80, 0x00078b84,
+ 0x00078b88, 0x00078b8c, 0x00078b90, 0x000caf80, 0x000caf84,
+ 0x000caf88, 0x000caf8c, 0x000caf90, 0x000db30c, 0x000db310,
+ 0x000db384, 0x000db388, 0x000db324, 0x000eb704, 0x000eb6a4,
+ 0x000eb6a8, 0x000eb710, 0x000eb714, 0x000eb720, 0x000eb724,
+ 0x000eb728, 0x000eb72c, 0x000eb7a0, 0x000eb7a4, 0x000eb7a8,
+ 0x000eb7b0, 0x000eb7b4, 0x000eb7b8, 0x000eb7a5, 0x000eb7a9,
+ 0x000eb7ad, 0x000eb7b1, 0x000eb7b5, 0x000eb7b9, 0x000eb7c5,
+ 0x000eb7c9, 0x000eb7d1, 0x000eb7d5, 0x000eb7d9, 0x000eb7c6,
+ 0x000eb7ca, 0x000eb7ce, 0x000eb7d2, 0x000eb7d6, 0x000eb7c3,
+ 0x000eb7c7, 0x000eb7cb, 0x000eb7cf, 0x000eb7d7, 0x000eb7db,
+ 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db,
+ 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db,
+ 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db,
+ 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db,
+ 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db,
+ 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db,
+ 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db,
+ 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x00058084, 0x00058088,
+ 0x0005808c, 0x00058100, 0x00058104, 0x00058108, 0x0005810c,
+ 0x00058110, 0x00058114, 0x00058180, 0x00058184, 0x00058188,
+ 0x0005818c, 0x00058190, 0x00058194, 0x000581a0, 0x0005820c,
+ 0x000581a8, 0x00058284, 0x00058288, 0x00058224, 0x00058290,
+ 0x00058300, 0x00058304, 0x00058308, 0x0005830c, 0x00058380,
+ 0x00058384, 0x00068700, 0x00068704, 0x00068708, 0x0006870c,
+ 0x00068780, 0x00068784, 0x00078b00, 0x00078b04, 0x00078b08,
+ 0x00078b0c, 0x00078b80, 0x00078b84, 0x00078b88, 0x00078b8c,
+ 0x00078b90, 0x000caf80, 0x000caf84, 0x000caf88, 0x000caf8c,
+ 0x000caf90, 0x000db30c, 0x000db310, 0x000db384, 0x000db388,
+ 0x000db324, 0x000eb704, 0x000eb6a4, 0x000eb6a8, 0x000eb710,
+ 0x000eb714, 0x000eb720, 0x000eb724, 0x000eb728, 0x000eb72c,
+ 0x000eb7a0, 0x000eb7a4, 0x000eb7a8, 0x000eb7b0, 0x000eb7b4,
+ 0x000eb7b8, 0x000eb7a5, 0x000eb7a9, 0x000eb7ad, 0x000eb7b1,
+ 0x000eb7b5, 0x000eb7b9, 0x000eb7c5, 0x000eb7c9, 0x000eb7d1,
+ 0x000eb7d5, 0x000eb7d9, 0x000eb7c6, 0x000eb7ca, 0x000eb7ce,
+ 0x000eb7d2, 0x000eb7d6, 0x000eb7c3, 0x000eb7c7, 0x000eb7cb,
+ 0x000eb7cf, 0x000eb7d7, 0x000eb7db, 0x000eb7db, 0x000eb7db,
+ 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db,
+ 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db,
+ 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db,
+ 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db,
+ 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db,
+ 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db,
+ 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db,
+ 0x000eb7db, 0x00000004, 0x0001f000, 0x0001f000, 0x1883800a,
+ 0x00000210, 0x0004a000, 0x7999aa0e
+};
+#endif
+
+static const uint32_t ar9271_vals_2g20[] = {
+ 0x00000160, 0x0000018c, 0x00003e38, 0x00000000, 0x08400b00,
+ 0x12e0002b, 0x00003440, 0x00000300, 0x02020200, 0x01000e0e,
+ 0x3a020001, 0x00000e0e, 0x00000007, 0x206a012e, 0x03721620,
+ 0x00001053, 0x00001053, 0x6d4000e2, 0x7ec84d2e, 0x3137605e,
+ 0x00058d18, 0x0001ce00, 0x5ac640d0, 0x06903881, 0x30002310,
+ 0x00000898, 0x0000000b, 0xd00a800d, 0xffbc1020, 0x00000000,
+ 0x00000000, 0x0000421c, 0x00000c00, 0x05eea6d4, 0x06336f77,
+ 0x6af6532f, 0x08f186c8, 0x00046384, 0x00000000, 0x00000000,
+ 0x00058084, 0x00058088, 0x0005808c, 0x00058100, 0x00058104,
+ 0x00058108, 0x0005810c, 0x00058110, 0x00058114, 0x00058180,
+ 0x00058184, 0x00058188, 0x0005818c, 0x00058190, 0x00058194,
+ 0x000581a0, 0x0005820c, 0x000581a8, 0x00058284, 0x00058288,
+ 0x00058224, 0x00058290, 0x00058300, 0x00058304, 0x00058308,
+ 0x0005830c, 0x00058380, 0x00058384, 0x00068700, 0x00068704,
+ 0x00068708, 0x0006870c, 0x00068780, 0x00068784, 0x00078b00,
+ 0x00078b04, 0x00078b08, 0x00078b0c, 0x00078b80, 0x00078b84,
+ 0x00078b88, 0x00078b8c, 0x00078b90, 0x000caf80, 0x000caf84,
+ 0x000caf88, 0x000caf8c, 0x000caf90, 0x000db30c, 0x000db310,
+ 0x000db384, 0x000db388, 0x000db324, 0x000eb704, 0x000eb6a4,
+ 0x000eb6a8, 0x000eb710, 0x000eb714, 0x000eb720, 0x000eb724,
+ 0x000eb728, 0x000eb72c, 0x000eb7a0, 0x000eb7a4, 0x000eb7a8,
+ 0x000eb7b0, 0x000eb7b4, 0x000eb7b8, 0x000eb7a5, 0x000eb7a9,
+ 0x000eb7ad, 0x000eb7b1, 0x000eb7b5, 0x000eb7b9, 0x000eb7c5,
+ 0x000eb7c9, 0x000eb7d1, 0x000eb7d5, 0x000eb7d9, 0x000eb7c6,
+ 0x000eb7ca, 0x000eb7ce, 0x000eb7d2, 0x000eb7d6, 0x000eb7c3,
+ 0x000eb7c7, 0x000eb7cb, 0x000eb7cf, 0x000eb7d7, 0x000eb7db,
+ 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db,
+ 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db,
+ 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db,
+ 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db,
+ 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db,
+ 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db,
+ 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db,
+ 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x00058084, 0x00058088,
+ 0x0005808c, 0x00058100, 0x00058104, 0x00058108, 0x0005810c,
+ 0x00058110, 0x00058114, 0x00058180, 0x00058184, 0x00058188,
+ 0x0005818c, 0x00058190, 0x00058194, 0x000581a0, 0x0005820c,
+ 0x000581a8, 0x00058284, 0x00058288, 0x00058224, 0x00058290,
+ 0x00058300, 0x00058304, 0x00058308, 0x0005830c, 0x00058380,
+ 0x00058384, 0x00068700, 0x00068704, 0x00068708, 0x0006870c,
+ 0x00068780, 0x00068784, 0x00078b00, 0x00078b04, 0x00078b08,
+ 0x00078b0c, 0x00078b80, 0x00078b84, 0x00078b88, 0x00078b8c,
+ 0x00078b90, 0x000caf80, 0x000caf84, 0x000caf88, 0x000caf8c,
+ 0x000caf90, 0x000db30c, 0x000db310, 0x000db384, 0x000db388,
+ 0x000db324, 0x000eb704, 0x000eb6a4, 0x000eb6a8, 0x000eb710,
+ 0x000eb714, 0x000eb720, 0x000eb724, 0x000eb728, 0x000eb72c,
+ 0x000eb7a0, 0x000eb7a4, 0x000eb7a8, 0x000eb7b0, 0x000eb7b4,
+ 0x000eb7b8, 0x000eb7a5, 0x000eb7a9, 0x000eb7ad, 0x000eb7b1,
+ 0x000eb7b5, 0x000eb7b9, 0x000eb7c5, 0x000eb7c9, 0x000eb7d1,
+ 0x000eb7d5, 0x000eb7d9, 0x000eb7c6, 0x000eb7ca, 0x000eb7ce,
+ 0x000eb7d2, 0x000eb7d6, 0x000eb7c3, 0x000eb7c7, 0x000eb7cb,
+ 0x000eb7cf, 0x000eb7d7, 0x000eb7db, 0x000eb7db, 0x000eb7db,
+ 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db,
+ 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db,
+ 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db,
+ 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db,
+ 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db,
+ 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db,
+ 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db, 0x000eb7db,
+ 0x000eb7db, 0x00000004, 0x0001f000, 0x0001f000, 0x1883800a,
+ 0x00000108, 0x0004a000, 0x7999aa0e
+};
+
+static const uint16_t ar9271_cm_regs[] = {
+ P(0x0000c), P(0x00030), P(0x00034), P(0x00040), P(0x00044),
+ P(0x00048), P(0x0004c), P(0x00050), P(0x00054), P(0x00800),
+ P(0x00804), P(0x00808), P(0x0080c), P(0x00810), P(0x00814),
+ P(0x00818), P(0x0081c), P(0x00820), P(0x00824), P(0x01040),
+ P(0x01044), P(0x01048), P(0x0104c), P(0x01050), P(0x01054),
+ P(0x01058), P(0x0105c), P(0x01060), P(0x01064), P(0x01230),
+ P(0x01270), P(0x01038), P(0x01078), P(0x010b8), P(0x010f8),
+ P(0x01138), P(0x01178), P(0x011b8), P(0x011f8), P(0x01238),
+ P(0x01278), P(0x012b8), P(0x012f8), P(0x01338), P(0x01378),
+ P(0x013b8), P(0x013f8), P(0x01438), P(0x01478), P(0x014b8),
+ P(0x014f8), P(0x01538), P(0x01578), P(0x015b8), P(0x015f8),
+ P(0x01638), P(0x01678), P(0x016b8), P(0x016f8), P(0x01738),
+ P(0x01778), P(0x017b8), P(0x017f8), P(0x0103c), P(0x0107c),
+ P(0x010bc), P(0x010fc), P(0x0113c), P(0x0117c), P(0x011bc),
+ P(0x011fc), P(0x0123c), P(0x0127c), P(0x012bc), P(0x012fc),
+ P(0x0133c), P(0x0137c), P(0x013bc), P(0x013fc), P(0x0143c),
+ P(0x0147c), P(0x04030), P(0x0403c), P(0x04024), P(0x04060),
+ P(0x04064), P(0x08004), P(0x08008), P(0x0800c), P(0x08018),
+ P(0x08020), P(0x08038), P(0x0803c), P(0x08048), P(0x08054),
+ P(0x08058), P(0x0805c), P(0x08060), P(0x08064), P(0x08070),
+ P(0x080b0), P(0x080b4), P(0x080b8), P(0x080bc), P(0x080c0),
+ P(0x080c4), P(0x080c8), P(0x080cc), P(0x080d0), P(0x080d4),
+ P(0x080d8), P(0x080e0), P(0x080e4), P(0x080e8), P(0x080ec),
+ P(0x080f0), P(0x080f4), P(0x080f8), P(0x080fc), P(0x08100),
+ P(0x08104), P(0x08108), P(0x0810c), P(0x08110), P(0x08118),
+ P(0x0811c), P(0x08120), P(0x08124), P(0x08128), P(0x0812c),
+ P(0x08130), P(0x08134), P(0x08138), P(0x0813c), P(0x08144),
+ P(0x08168), P(0x0816c), P(0x08170), P(0x08174), P(0x08178),
+ P(0x0817c), P(0x081c0), P(0x081d0), P(0x081ec), P(0x081f0),
+ P(0x081f4), P(0x081f8), P(0x081fc), P(0x08200), P(0x08204),
+ P(0x08208), P(0x0820c), P(0x08210), P(0x08214), P(0x08218),
+ P(0x0821c), P(0x08220), P(0x08224), P(0x08228), P(0x0822c),
+ P(0x08230), P(0x08234), P(0x08238), P(0x0823c), P(0x08240),
+ P(0x08244), P(0x08248), P(0x0824c), P(0x08250), P(0x08254),
+ P(0x08258), P(0x0825c), P(0x08260), P(0x08264), P(0x08270),
+ P(0x08274), P(0x08278), P(0x0827c), P(0x08284), P(0x08288),
+ P(0x0828c), P(0x08294), P(0x08298), P(0x0829c), P(0x08300),
+ P(0x08314), P(0x08328), P(0x0832c), P(0x08330), P(0x08334),
+ P(0x08338), P(0x0833c), P(0x08340), P(0x08344), P(0x07010),
+ P(0x07034), P(0x07038), P(0x07800), P(0x07804), P(0x07808),
+ P(0x0780c), P(0x07810), P(0x07814), P(0x0781c), P(0x07828),
+ P(0x0782c), P(0x07830), P(0x07834), P(0x0783c), P(0x07840),
+ P(0x07844), P(0x07848), P(0x0784c), P(0x07850), P(0x07854),
+ P(0x07858), P(0x0785c), P(0x07860), P(0x07864), P(0x07868),
+ P(0x07870), P(0x09808), P(0x0980c), P(0x09810), P(0x09814),
+ P(0x0981c), P(0x0982c), P(0x09830), P(0x0983c), P(0x0984c),
+ P(0x09854), P(0x09900), P(0x09904), P(0x09908), P(0x0990c),
+ P(0x0991c), P(0x09920), P(0x09928), P(0x0992c), P(0x09934),
+ P(0x09938), P(0x0993c), P(0x09940), P(0x09948), P(0x0994c),
+ P(0x09954), P(0x09958), P(0x09968), P(0x09970), P(0x09974),
+ P(0x09978), P(0x0997c), P(0x09980), P(0x09984), P(0x09988),
+ P(0x0998c), P(0x09990), P(0x09994), P(0x09998), P(0x0999c),
+ P(0x099a0), P(0x099a4), P(0x099a8), P(0x099ac), P(0x099b0),
+ P(0x099b4), P(0x099dc), P(0x099e0), P(0x099e4), P(0x099e8),
+ P(0x099ec), P(0x099f0), P(0x0a208), P(0x0a210), P(0x0a214),
+ P(0x0a218), P(0x0a220), P(0x0a224), P(0x0a228), P(0x0a22c),
+ P(0x0a234), P(0x0a238), P(0x0a244), P(0x0a248), P(0x0a24c),
+ P(0x0a254), P(0x0a258), P(0x0a25c), P(0x0a260), P(0x0a268),
+ P(0x0a26c), P(0x0a388), P(0x0a38c), P(0x0a390), P(0x0a39c),
+ P(0x0a3a0), P(0x0a3a4), P(0x0a3a8), P(0x0a3ac), P(0x0a3b0),
+ P(0x0a3b4), P(0x0a3b8), P(0x0a3bc), P(0x0a3c0), P(0x0a3c4),
+ P(0x0a3cc), P(0x0a3d0), P(0x0a3d4), P(0x0a3e4), P(0x0a3e8),
+ P(0x0a3ec), P(0x0a3f0), P(0x0a3f4), P(0x0d270), P(0x0d35c),
+ P(0x0d360), P(0x0d364), P(0x0d368), P(0x0d36c), P(0x0d370),
+ P(0x0d374), P(0x0d378), P(0x0d37c), P(0x0d380), P(0x0d384)
+};
+
+static const uint32_t ar9271_cm_vals[] = {
+ 0x00000000, 0x00020045, 0x00000005, 0x00000000, 0x00000008,
+ 0x00000008, 0x00000010, 0x00000000, 0x0000001f, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x002ffc0f,
+ 0x002ffc0f, 0x002ffc0f, 0x002ffc0f, 0x002ffc0f, 0x002ffc0f,
+ 0x002ffc0f, 0x002ffc0f, 0x002ffc0f, 0x002ffc0f, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000002, 0x00000002, 0x0000001f, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000700,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x000fc78f, 0x0000000f, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x2a80001a,
+ 0x05dc01e0, 0x1f402710, 0x01f40000, 0x00001e00, 0x00000000,
+ 0x00400000, 0xffffffff, 0x0000ffff, 0x003f3f3f, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00020000, 0x00020000,
+ 0x00000001, 0x00000052, 0x00000000, 0x00000168, 0x000100aa,
+ 0x00003210, 0x08f04810, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffffffff,
+ 0x00000000, 0x00000000, 0x32143320, 0xfaa4fa50, 0x00000100,
+ 0x00000000, 0x00000000, 0x0000320a, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00100000,
+ 0x0010f400, 0x00000100, 0x0001e800, 0x00000000, 0x00000000,
+ 0x00000000, 0x400000ff, 0x00080922, 0x88a00010, 0x00000000,
+ 0x40000000, 0x003e4180, 0x00000000, 0x0000002c, 0x0000002c,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000040,
+ 0x00000000, 0x00000000, 0x00000001, 0x00000302, 0x00000e00,
+ 0x00ff0000, 0x00000000, 0x00010380, 0x00581043, 0x00000030,
+ 0x00000002, 0x000004c2, 0x00140000, 0x0e4548d8, 0x54214514,
+ 0x02025820, 0x71c0d388, 0x924934a8, 0x00000000, 0x66964300,
+ 0x8db6d961, 0x8db6d96c, 0x6140008b, 0x72ee0a72, 0xbbfffffc,
+ 0x000c0db6, 0x6db6246f, 0x6d9b66db, 0x6d8c6dba, 0x00040000,
+ 0xdb003012, 0x04924914, 0x21084210, 0xf7d7ffde, 0xc2034080,
+ 0x10142c00, 0x00000000, 0xafe68e30, 0xfd14e000, 0x9c0a9f6b,
+ 0x00000000, 0x0000a000, 0x00000000, 0x00200400, 0x0040233c,
+ 0x00000044, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x10000fff, 0x04900000, 0x00000001, 0x00000004, 0x1e1f2022,
+ 0x0a0b0c0d, 0x00000000, 0x14750604, 0x9280c00a, 0x00020028,
+ 0x5f3ca3de, 0x0108ecff, 0x000003ce, 0x192bb514, 0x00000000,
+ 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000001, 0x201fff00, 0x2def0400, 0x03051000,
+ 0x00000820, 0x00000000, 0x00000000, 0xaaaaaaaa, 0x3c466478,
+ 0x0cc80caa, 0x00000000, 0x803e68c8, 0x4080a333, 0x00206c10,
+ 0x009c4060, 0x01834061, 0x00000400, 0x000003b5, 0x00000000,
+ 0x20202020, 0x20202020, 0x00000000, 0xfffffffc, 0x00000000,
+ 0x00000000, 0x0ccb5380, 0x15151501, 0xdfa90f01, 0x00000000,
+ 0x0ebae9e6, 0x0c000000, 0x20202020, 0x20202020, 0x00000001,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x20202020, 0x20202020, 0x20202020, 0x00000000, 0x18c43433,
+ 0x00f70081, 0x01036a2f, 0x00000000, 0x0d820820, 0x07ffffef,
+ 0x0fffffe7, 0x17ffffe5, 0x1fffffe4, 0x37ffffe3, 0x3fffffe3,
+ 0x57ffffe3, 0x5fffffe2, 0x7fffffe2, 0x7f3c7bba, 0xf3307ff0
+};
+
+static const struct athn_ini ar9271_ini = {
+ .nregs = __arraycount(ar9271_regs),
+ .regs = ar9271_regs,
+ .vals_5g20 = NULL, /* 2GHz only. */
+#ifndef IEEE80211_NO_HT
+ .vals_5g40 = NULL, /* 2GHz only. */
+ .vals_2g40 = ar9271_vals_2g40,
+#endif
+ .vals_2g20 = ar9271_vals_2g20,
+ .ncmregs = __arraycount(ar9271_cm_regs),
+ .cmregs = ar9271_cm_regs,
+ .cmvals = ar9271_cm_vals,
+};
+#endif /* NATHN_USB */
+
+/*
+ * AR9285 1.2 Tx gains.
+ */
+static const uint16_t ar9285_1_2_tx_gain_regs[] = {
+ P(0x0a300), P(0x0a304), P(0x0a308), P(0x0a30c), P(0x0a310),
+ P(0x0a314), P(0x0a318), P(0x0a31c), P(0x0a320), P(0x0a324),
+ P(0x0a328), P(0x0a32c), P(0x0a330), P(0x0a334), P(0x0a338),
+ P(0x0a33c), P(0x0a340), P(0x0a344), P(0x0a348), P(0x0a34c),
+ P(0x0a350), P(0x0a354), P(0x07814), P(0x07828), P(0x07830),
+ P(0x07838), P(0x0783c), P(0x07840), P(0x0786c), P(0x07820),
+ P(0x0a274), P(0x0a278), P(0x0a27c), P(0x0a394), P(0x0a398),
+ P(0x0a3dc), P(0x0a3e0)
+};
+
+static const uint32_t ar9285_1_2_tx_gain_vals_2g[] = {
+ 0x00000000, 0x00009200, 0x00010208, 0x00019608, 0x00022618,
+ 0x0002a6c9, 0x00031710, 0x00035718, 0x00038758, 0x0003c75a,
+ 0x0004075c, 0x0004475e, 0x0004679f, 0x000487df, 0x0003891e,
+ 0x0003a95e, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df,
+ 0x0003e9df, 0x0003e9df, 0x924934a8, 0x26d2491b, 0xedb6d96e,
+ 0xfac68801, 0x0001fffe, 0xffeb1a20, 0x48609eb4, 0x00000c04,
+ 0x0a21a652, 0x39ce739c, 0x050e039c, 0x39ce739c, 0x0000039c,
+ 0x39ce739c, 0x0000039c
+};
+
+static const struct athn_gain ar9285_1_2_tx_gain = {
+ __arraycount(ar9285_1_2_tx_gain_regs),
+ ar9285_1_2_tx_gain_regs,
+ NULL, /* 2GHz only. */
+ ar9285_1_2_tx_gain_vals_2g
+};
+
+static const uint32_t ar9285_1_2_tx_gain_high_power_vals_2g[] = {
+ 0x00000000, 0x00006200, 0x00008201, 0x0000b240, 0x0000d241,
+ 0x0000f600, 0x00012800, 0x00016802, 0x0001b805, 0x00021a80,
+ 0x00028b00, 0x0002ab40, 0x0002cd80, 0x00033d82, 0x0003891e,
+ 0x0003a95e, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df,
+ 0x0003e9df, 0x0003e9df, 0x924934a8, 0x26d2491b, 0xedb6d96e,
+ 0xfac68803, 0x0001fffe, 0xffeb1a20, 0x08609ebe, 0x00000c00,
+ 0x0a216652, 0x0e739ce7, 0x050380e7, 0x0e739ce7, 0x000000e7,
+ 0x0e739ce7, 0x000000e7
+};
+
+static const struct athn_gain ar9285_1_2_tx_gain_high_power = {
+ __arraycount(ar9285_1_2_tx_gain_regs),
+ ar9285_1_2_tx_gain_regs,
+ NULL, /* 2GHz only. */
+ ar9285_1_2_tx_gain_high_power_vals_2g
+};
+
+/*
+ * AR9285 XE 2.0 Tx gains.
+ */
+static const uint32_t ar9285_2_0_tx_gain_vals_2g[] = {
+ 0x00000000, 0x00009200, 0x00010208, 0x00019608, 0x00022618,
+ 0x0002a6c9, 0x00031710, 0x00035718, 0x00038758, 0x0003c75a,
+ 0x0004075c, 0x0004475e, 0x0004679f, 0x000487df, 0x0003891e,
+ 0x0003a95e, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df,
+ 0x0003e9df, 0x0003e9df, 0x92497ca8, 0x2ad2491b, 0xedb6da6e,
+ 0xdac71441, 0x2481f6fe, 0xba5f638c, 0x48609eb4, 0x00000c04,
+ 0x0a21a652, 0x39ce739c, 0x050e039c, 0x39ce739c, 0x0000039c,
+ 0x39ce739c, 0x0000039c
+};
+
+static const struct athn_gain ar9285_2_0_tx_gain = {
+ __arraycount(ar9285_1_2_tx_gain_regs),
+ ar9285_1_2_tx_gain_regs,
+ NULL, /* 2GHz only. */
+ ar9285_2_0_tx_gain_vals_2g
+};
+
+static const uint32_t ar9285_2_0_tx_gain_high_power_vals_2g[] = {
+ 0x00000000, 0x00006200, 0x00008201, 0x0000b240, 0x0000d241,
+ 0x0000f600, 0x00012800, 0x00016802, 0x0001b805, 0x00021a80,
+ 0x00028b00, 0x0002ab40, 0x0002cd80, 0x00033d82, 0x0003891e,
+ 0x0003a95e, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df,
+ 0x0003e9df, 0x0003e9df, 0x92497ca8, 0x2ad2491b, 0xedb6da6e,
+ 0xdac71443, 0x2481f6fe, 0xba5f638c, 0x08609ebe, 0x00000c00,
+ 0x0a216652, 0x0e739ce7, 0x050380e7, 0x0e739ce7, 0x000000e7,
+ 0x0e739ce7, 0x000000e7
+};
+
+static const struct athn_gain ar9285_2_0_tx_gain_high_power = {
+ __arraycount(ar9285_1_2_tx_gain_regs),
+ ar9285_1_2_tx_gain_regs,
+ NULL, /* 2GHz only. */
+ ar9285_2_0_tx_gain_high_power_vals_2g
+};
+
+#if NATHN_USB > 0
+/*
+ * AR9271 Tx gains.
+ */
+static const uint16_t ar9271_tx_gain_regs[] = {
+ P(0x0a300), P(0x0a304), P(0x0a308), P(0x0a30c), P(0x0a310),
+ P(0x0a314), P(0x0a318), P(0x0a31c), P(0x0a320), P(0x0a324),
+ P(0x0a328), P(0x0a32c), P(0x0a330), P(0x0a334), P(0x0a338),
+ P(0x0a33c), P(0x0a340), P(0x0a344), P(0x0a348), P(0x0a34c),
+ P(0x0a350), P(0x0a354), P(0x07838), P(0x07824), P(0x0786c),
+ P(0x07820), P(0x0a274), P(0x0a278), P(0x0a27c), P(0x0a394),
+ P(0x0a398), P(0x0a3dc), P(0x0a3e0)
+};
+
+static const uint32_t ar9271_tx_gain_vals_2g[] = {
+ 0x00000000, 0x00009200, 0x00010208, 0x00019608, 0x0001e610,
+ 0x0002d6d0, 0x00039758, 0x0003b759, 0x0003d75a, 0x0004175c,
+ 0x0004575e, 0x0004979f, 0x0004d7df, 0x000368de, 0x0003891e,
+ 0x0003a95e, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df,
+ 0x0003e9df, 0x0003e9df, 0x00000029, 0x00d8abff, 0x48609eb4,
+ 0x00000c04, 0x0a218652, 0x3bdef7bd, 0x050e83bd, 0x3bdef7bd,
+ 0x000003bd, 0x3bdef7bd, 0x000003bd
+};
+
+static const struct athn_gain ar9271_tx_gain = {
+ __arraycount(ar9271_tx_gain_regs),
+ ar9271_tx_gain_regs,
+ NULL, /* 2GHz only. */
+ ar9271_tx_gain_vals_2g
+};
+
+static const uint32_t ar9271_tx_gain_high_power_vals_2g[] = {
+ 0x00010000, 0x00016200, 0x00018201, 0x0001b240, 0x0001d241,
+ 0x0001f600, 0x00022800, 0x00026802, 0x0002b805, 0x0002ea41,
+ 0x00038b00, 0x0003ab40, 0x0003cd80, 0x000368de, 0x0003891e,
+ 0x0003a95e, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df,
+ 0x0003e9df, 0x0003e9df, 0x0000002b, 0x00d8a7ff, 0x08609eba,
+ 0x00000c00, 0x0a214652, 0x0e739ce7, 0x05018063, 0x06318c63,
+ 0x00000063, 0x06318c63, 0x00000063
+};
+
+static const struct athn_gain ar9271_tx_gain_high_power = {
+ __arraycount(ar9271_tx_gain_regs),
+ ar9271_tx_gain_regs,
+ NULL, /* 2GHz only. */
+ ar9271_tx_gain_high_power_vals_2g
+};
+#endif /* NATHN_USB */
+
+#endif /* _ARN9285REG_H_ */
diff --git a/sys/dev/ic/arn9287.c b/sys/dev/ic/arn9287.c
new file mode 100644
index 00000000000..01a8e6b0b2d
--- /dev/null
+++ b/sys/dev/ic/arn9287.c
@@ -0,0 +1,628 @@
+/* $NetBSD: arn9287.c,v 1.1 2013/03/30 02:53:01 christos Exp $ */
+/* $OpenBSD: ar9287.c,v 1.17 2012/06/10 21:23:36 kettenis Exp $ */
+
+/*-
+ * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr>
+ * Copyright (c) 2008-2009 Atheros Communications Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+/*
+ * Driver for Atheros 802.11a/g/n chipsets.
+ * Routines for AR9227 and AR9287 chipsets.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: arn9287.c,v 1.1 2013/03/30 02:53:01 christos Exp $");
+
+#include <sys/param.h>
+#include <sys/sockio.h>
+#include <sys/mbuf.h>
+#include <sys/kernel.h>
+#include <sys/socket.h>
+#include <sys/systm.h>
+#include <sys/malloc.h>
+#include <sys/queue.h>
+#include <sys/callout.h>
+#include <sys/conf.h>
+#include <sys/device.h>
+
+#include <sys/bus.h>
+#include <sys/endian.h>
+#include <sys/intr.h>
+
+#include <net/bpf.h>
+#include <net/if.h>
+#include <net/if_arp.h>
+#include <net/if_dl.h>
+#include <net/if_media.h>
+#include <net/if_types.h>
+
+#include <netinet/in.h>
+#include <netinet/in_systm.h>
+#include <netinet/in_var.h>
+#include <netinet/ip.h>
+
+#include <net80211/ieee80211_var.h>
+#include <net80211/ieee80211_amrr.h>
+#include <net80211/ieee80211_radiotap.h>
+
+#include <dev/ic/athnreg.h>
+#include <dev/ic/athnvar.h>
+
+#include <dev/ic/arn5008reg.h>
+#include <dev/ic/arn9280reg.h>
+#include <dev/ic/arn9287reg.h>
+
+#include <dev/ic/arn5008.h>
+#include <dev/ic/arn9280.h>
+#include <dev/ic/arn9287.h>
+
+#define Static static
+
+Static void ar9287_get_pdadcs(struct athn_softc *,
+ struct ieee80211_channel *, int, int, uint8_t, uint8_t *,
+ uint8_t *);
+Static const struct ar_spur_chan *
+ ar9287_get_spur_chans(struct athn_softc *, int);
+Static void ar9287_init_from_rom(struct athn_softc *,
+ struct ieee80211_channel *, struct ieee80211_channel *);
+Static void ar9287_olpc_get_pdgain(struct athn_softc *,
+ struct ieee80211_channel *, int, int8_t *);
+Static void ar9287_olpc_init(struct athn_softc *);
+Static void ar9287_olpc_temp_compensation(struct athn_softc *);
+Static void ar9287_set_power_calib(struct athn_softc *,
+ struct ieee80211_channel *);
+Static void ar9287_set_txpower(struct athn_softc *,
+ struct ieee80211_channel *, struct ieee80211_channel *);
+Static void ar9287_setup(struct athn_softc *);
+Static void ar9287_swap_rom(struct athn_softc *);
+
+PUBLIC int
+ar9287_attach(struct athn_softc *sc)
+{
+
+ sc->sc_eep_base = AR9287_EEP_START_LOC;
+ sc->sc_eep_size = sizeof(struct ar9287_eeprom);
+ sc->sc_def_nf = AR9287_PHY_CCA_MAX_GOOD_VALUE;
+ sc->sc_ngpiopins = (sc->sc_flags & ATHN_FLAG_USB) ? 16 : 11;
+ sc->sc_led_pin = 8;
+ sc->sc_workaround = AR9285_WA_DEFAULT;
+ sc->sc_ops.setup = ar9287_setup;
+ sc->sc_ops.swap_rom = ar9287_swap_rom;
+ sc->sc_ops.init_from_rom = ar9287_init_from_rom;
+ sc->sc_ops.set_txpower = ar9287_set_txpower;
+ sc->sc_ops.set_synth = ar9280_set_synth;
+ sc->sc_ops.spur_mitigate = ar9280_spur_mitigate;
+ sc->sc_ops.get_spur_chans = ar9287_get_spur_chans;
+ sc->sc_ops.olpc_init = ar9287_olpc_init;
+ sc->sc_ops.olpc_temp_compensation = ar9287_olpc_temp_compensation;
+ sc->sc_ini = &ar9287_1_1_ini;
+ sc->sc_serdes = &ar9280_2_0_serdes;
+
+ return ar5008_attach(sc);
+}
+
+Static void
+ar9287_setup(struct athn_softc *sc)
+{
+ const struct ar9287_eeprom *eep = sc->sc_eep;
+
+ /* Determine if open loop power control should be used. */
+ if (eep->baseEepHeader.openLoopPwrCntl)
+ sc->sc_flags |= ATHN_FLAG_OLPC;
+
+ sc->sc_rx_gain = &ar9287_1_1_rx_gain;
+ sc->sc_tx_gain = &ar9287_1_1_tx_gain;
+}
+
+Static void
+ar9287_swap_rom(struct athn_softc *sc)
+{
+ struct ar9287_eeprom *eep = sc->sc_eep;
+ int i;
+
+ eep->modalHeader.antCtrlCommon =
+ bswap32(eep->modalHeader.antCtrlCommon);
+
+ for (i = 0; i < AR9287_MAX_CHAINS; i++) {
+ eep->modalHeader.antCtrlChain[i] =
+ bswap32(eep->modalHeader.antCtrlChain[i]);
+ }
+ for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
+ eep->modalHeader.spurChans[i].spurChan =
+ bswap16(eep->modalHeader.spurChans[i].spurChan);
+ }
+}
+
+Static const struct ar_spur_chan *
+ar9287_get_spur_chans(struct athn_softc *sc, int is2ghz)
+{
+ const struct ar9287_eeprom *eep = sc->sc_eep;
+
+ KASSERT(is2ghz);
+ return eep->modalHeader.spurChans;
+}
+
+Static void
+ar9287_init_from_rom(struct athn_softc *sc, struct ieee80211_channel *c,
+ struct ieee80211_channel *extc)
+{
+ const struct ar9287_eeprom *eep = sc->sc_eep;
+ const struct ar9287_modal_eep_header *modal = &eep->modalHeader;
+ uint32_t reg, offset;
+ int i;
+
+ AR_WRITE(sc, AR_PHY_SWITCH_COM, modal->antCtrlCommon);
+
+ for (i = 0; i < AR9287_MAX_CHAINS; i++) {
+ offset = i * 0x1000;
+
+ AR_WRITE(sc, AR_PHY_SWITCH_CHAIN_0 + offset,
+ modal->antCtrlChain[i]);
+
+ reg = AR_READ(sc, AR_PHY_TIMING_CTRL4_0 + offset);
+ reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF,
+ modal->iqCalICh[i]);
+ reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF,
+ modal->iqCalQCh[i]);
+ AR_WRITE(sc, AR_PHY_TIMING_CTRL4_0 + offset, reg);
+
+ reg = AR_READ(sc, AR_PHY_GAIN_2GHZ + offset);
+ reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
+ modal->bswMargin[i]);
+ reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_DB,
+ modal->bswAtten[i]);
+ AR_WRITE(sc, AR_PHY_GAIN_2GHZ + offset, reg);
+
+ reg = AR_READ(sc, AR_PHY_RXGAIN + offset);
+ reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_MARGIN,
+ modal->rxTxMarginCh[i]);
+ reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_ATTEN,
+ modal->txRxAttenCh[i]);
+ AR_WRITE(sc, AR_PHY_RXGAIN + offset, reg);
+ }
+
+ reg = AR_READ(sc, AR_PHY_SETTLING);
+#ifndef IEEE80211_NO_HT
+ if (extc != NULL)
+ reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->swSettleHt40);
+ else
+#endif
+ reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->switchSettling);
+ AR_WRITE(sc, AR_PHY_SETTLING, reg);
+
+ reg = AR_READ(sc, AR_PHY_DESIRED_SZ);
+ reg = RW(reg, AR_PHY_DESIRED_SZ_ADC, modal->adcDesiredSize);
+ AR_WRITE(sc, AR_PHY_DESIRED_SZ, reg);
+
+ reg = SM(AR_PHY_RF_CTL4_TX_END_XPAA_OFF, modal->txEndToXpaOff);
+ reg |= SM(AR_PHY_RF_CTL4_TX_END_XPAB_OFF, modal->txEndToXpaOff);
+ reg |= SM(AR_PHY_RF_CTL4_FRAME_XPAA_ON, modal->txFrameToXpaOn);
+ reg |= SM(AR_PHY_RF_CTL4_FRAME_XPAB_ON, modal->txFrameToXpaOn);
+ AR_WRITE(sc, AR_PHY_RF_CTL4, reg);
+
+ reg = AR_READ(sc, AR_PHY_RF_CTL3);
+ reg = RW(reg, AR_PHY_TX_END_TO_A2_RX_ON, modal->txEndToRxOn);
+ AR_WRITE(sc, AR_PHY_RF_CTL3, reg);
+
+ reg = AR_READ(sc, AR_PHY_CCA(0));
+ reg = RW(reg, AR9280_PHY_CCA_THRESH62, modal->thresh62);
+ AR_WRITE(sc, AR_PHY_CCA(0), reg);
+
+ reg = AR_READ(sc, AR_PHY_EXT_CCA0);
+ reg = RW(reg, AR_PHY_EXT_CCA0_THRESH62, modal->thresh62);
+ AR_WRITE(sc, AR_PHY_EXT_CCA0, reg);
+
+ reg = AR_READ(sc, AR9287_AN_RF2G3_CH0);
+ reg = RW(reg, AR9287_AN_RF2G3_DB1, modal->db1);
+ reg = RW(reg, AR9287_AN_RF2G3_DB2, modal->db2);
+ reg = RW(reg, AR9287_AN_RF2G3_OB_CCK, modal->ob_cck);
+ reg = RW(reg, AR9287_AN_RF2G3_OB_PSK, modal->ob_psk);
+ reg = RW(reg, AR9287_AN_RF2G3_OB_QAM, modal->ob_qam);
+ reg = RW(reg, AR9287_AN_RF2G3_OB_PAL_OFF, modal->ob_pal_off);
+ AR_WRITE(sc, AR9287_AN_RF2G3_CH0, reg);
+ AR_WRITE_BARRIER(sc);
+ DELAY(100);
+
+ reg = AR_READ(sc, AR9287_AN_RF2G3_CH1);
+ reg = RW(reg, AR9287_AN_RF2G3_DB1, modal->db1);
+ reg = RW(reg, AR9287_AN_RF2G3_DB2, modal->db2);
+ reg = RW(reg, AR9287_AN_RF2G3_OB_CCK, modal->ob_cck);
+ reg = RW(reg, AR9287_AN_RF2G3_OB_PSK, modal->ob_psk);
+ reg = RW(reg, AR9287_AN_RF2G3_OB_QAM, modal->ob_qam);
+ reg = RW(reg, AR9287_AN_RF2G3_OB_PAL_OFF, modal->ob_pal_off);
+ AR_WRITE(sc, AR9287_AN_RF2G3_CH1, reg);
+ AR_WRITE_BARRIER(sc);
+ DELAY(100);
+
+ reg = AR_READ(sc, AR_PHY_RF_CTL2);
+ reg = RW(reg, AR_PHY_TX_END_DATA_START, modal->txFrameToDataStart);
+ reg = RW(reg, AR_PHY_TX_END_PA_ON, modal->txFrameToPaOn);
+ AR_WRITE(sc, AR_PHY_RF_CTL2, reg);
+
+ reg = AR_READ(sc, AR9287_AN_TOP2);
+ reg = RW(reg, AR9287_AN_TOP2_XPABIAS_LVL, modal->xpaBiasLvl);
+ AR_WRITE(sc, AR9287_AN_TOP2, reg);
+ AR_WRITE_BARRIER(sc);
+ DELAY(100);
+}
+
+Static void
+ar9287_get_pdadcs(struct athn_softc *sc, struct ieee80211_channel *c,
+ int chain, int nxpdgains, uint8_t overlap, uint8_t *boundaries,
+ uint8_t *pdadcs)
+{
+ const struct ar9287_eeprom *eep = sc->sc_eep;
+ const struct ar9287_cal_data_per_freq *pierdata;
+ const uint8_t *pierfreq;
+ struct athn_pier lopier, hipier;
+ int16_t delta;
+ uint8_t fbin;
+ int i, lo, hi, npiers;
+
+ pierfreq = eep->calFreqPier2G;
+ pierdata = (const struct ar9287_cal_data_per_freq *)
+ eep->calPierData2G[chain];
+ npiers = AR9287_NUM_2G_CAL_PIERS;
+
+ /* Find channel in ROM pier table. */
+ fbin = athn_chan2fbin(c);
+ athn_get_pier_ival(fbin, pierfreq, npiers, &lo, &hi);
+
+ lopier.fbin = pierfreq[lo];
+ hipier.fbin = pierfreq[hi];
+ for (i = 0; i < nxpdgains; i++) {
+ lopier.pwr[i] = pierdata[lo].pwrPdg[i];
+ lopier.vpd[i] = pierdata[lo].vpdPdg[i];
+ hipier.pwr[i] = pierdata[lo].pwrPdg[i];
+ hipier.vpd[i] = pierdata[lo].vpdPdg[i];
+ }
+ ar5008_get_pdadcs(sc, fbin, &lopier, &hipier, nxpdgains,
+ AR9287_PD_GAIN_ICEPTS, overlap, boundaries, pdadcs);
+
+ delta = (eep->baseEepHeader.pwrTableOffset -
+ AR_PWR_TABLE_OFFSET_DB) * 2; /* In half dB. */
+ if (delta != 0) {
+ /* Shift the PDADC table to start at the new offset. */
+ /* XXX Our padding value differs from Linux. */
+ for (i = 0; i < AR_NUM_PDADC_VALUES; i++)
+ pdadcs[i] = pdadcs[MIN(i + delta,
+ AR_NUM_PDADC_VALUES - 1)];
+ }
+}
+
+Static void
+ar9287_olpc_get_pdgain(struct athn_softc *sc, struct ieee80211_channel *c,
+ int chain, int8_t *pwr)
+{
+ const struct ar9287_eeprom *eep = sc->sc_eep;
+ const struct ar_cal_data_per_freq_olpc *pierdata;
+ const uint8_t *pierfreq;
+ uint8_t fbin;
+ int lo, hi, npiers;
+
+ pierfreq = eep->calFreqPier2G;
+ pierdata = (const struct ar_cal_data_per_freq_olpc *)
+ eep->calPierData2G[chain];
+ npiers = AR9287_NUM_2G_CAL_PIERS;
+
+ /* Find channel in ROM pier table. */
+ fbin = athn_chan2fbin(c);
+ athn_get_pier_ival(fbin, pierfreq, npiers, &lo, &hi);
+#if 0
+ *pwr = athn_interpolate(fbin,
+ pierfreq[lo], pierdata[lo].pwrPdg[0][0],
+ pierfreq[hi], pierdata[hi].pwrPdg[0][0]);
+#else
+ *pwr = (pierdata[lo].pwrPdg[0][0] + pierdata[hi].pwrPdg[0][0]) / 2;
+#endif
+}
+
+Static void
+ar9287_set_power_calib(struct athn_softc *sc, struct ieee80211_channel *c)
+{
+ const struct ar9287_eeprom *eep = sc->sc_eep;
+ uint8_t boundaries[AR_PD_GAINS_IN_MASK];
+ uint8_t pdadcs[AR_NUM_PDADC_VALUES];
+ uint8_t xpdgains[AR9287_NUM_PD_GAINS];
+ int8_t txpower;
+ uint8_t overlap;
+ uint32_t reg, offset;
+ int i, j, nxpdgains;
+
+ if (sc->sc_eep_rev < AR_EEP_MINOR_VER_2) {
+ overlap = MS(AR_READ(sc, AR_PHY_TPCRG5),
+ AR_PHY_TPCRG5_PD_GAIN_OVERLAP);
+ }
+ else
+ overlap = eep->modalHeader.pdGainOverlap;
+
+ if (sc->sc_flags & ATHN_FLAG_OLPC) {
+ /* XXX not here. */
+ sc->sc_pdadc =
+ ((const struct ar_cal_data_per_freq_olpc *)
+ eep->calPierData2G[0])->vpdPdg[0][0];
+ }
+
+ nxpdgains = 0;
+ memset(xpdgains, 0, sizeof(xpdgains));
+ for (i = AR9287_PD_GAINS_IN_MASK - 1; i >= 0; i--) {
+ if (nxpdgains >= AR9287_NUM_PD_GAINS)
+ break; /* Can't happen. */
+ if (eep->modalHeader.xpdGain & (1 << i))
+ xpdgains[nxpdgains++] = i;
+ }
+ reg = AR_READ(sc, AR_PHY_TPCRG1);
+ reg = RW(reg, AR_PHY_TPCRG1_NUM_PD_GAIN, nxpdgains - 1);
+ reg = RW(reg, AR_PHY_TPCRG1_PD_GAIN_1, xpdgains[0]);
+ reg = RW(reg, AR_PHY_TPCRG1_PD_GAIN_2, xpdgains[1]);
+ AR_WRITE(sc, AR_PHY_TPCRG1, reg);
+ AR_WRITE_BARRIER(sc);
+
+ for (i = 0; i < AR9287_MAX_CHAINS; i++) {
+ if (!(sc->sc_txchainmask & (1 << i)))
+ continue;
+
+ offset = i * 0x1000;
+
+ if (sc->sc_flags & ATHN_FLAG_OLPC) {
+ ar9287_olpc_get_pdgain(sc, c, i, &txpower);
+
+ reg = AR_READ(sc, AR_PHY_TX_PWRCTRL6_0);
+ reg = RW(reg, AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3);
+ AR_WRITE(sc, AR_PHY_TX_PWRCTRL6_0, reg);
+
+ reg = AR_READ(sc, AR_PHY_TX_PWRCTRL6_1);
+ reg = RW(reg, AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3);
+ AR_WRITE(sc, AR_PHY_TX_PWRCTRL6_1, reg);
+
+ /* NB: txpower is in half dB. */
+ reg = AR_READ(sc, AR_PHY_CH0_TX_PWRCTRL11 + offset);
+ reg = RW(reg, AR_PHY_TX_PWRCTRL_OLPC_PWR, txpower);
+ AR_WRITE(sc, AR_PHY_CH0_TX_PWRCTRL11 + offset, reg);
+
+ AR_WRITE_BARRIER(sc);
+ continue; /* That's it for open loop mode. */
+ }
+
+ /* Closed loop power control. */
+ ar9287_get_pdadcs(sc, c, i, nxpdgains, overlap,
+ boundaries, pdadcs);
+
+ /* Write boundaries. */
+ if (i == 0) {
+ reg = SM(AR_PHY_TPCRG5_PD_GAIN_OVERLAP,
+ overlap);
+ reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1,
+ boundaries[0]);
+ reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2,
+ boundaries[1]);
+ reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3,
+ boundaries[2]);
+ reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4,
+ boundaries[3]);
+ AR_WRITE(sc, AR_PHY_TPCRG5 + offset, reg);
+ }
+ /* Write PDADC values. */
+ for (j = 0; j < AR_NUM_PDADC_VALUES; j += 4) {
+ AR_WRITE(sc, AR_PHY_PDADC_TBL_BASE + offset + j,
+ pdadcs[j + 0] << 0 |
+ pdadcs[j + 1] << 8 |
+ pdadcs[j + 2] << 16 |
+ pdadcs[j + 3] << 24);
+ }
+ AR_WRITE_BARRIER(sc);
+ }
+}
+
+Static void
+ar9287_set_txpower(struct athn_softc *sc, struct ieee80211_channel *c,
+ struct ieee80211_channel *extc)
+{
+ const struct ar9287_eeprom *eep = sc->sc_eep;
+ const struct ar9287_modal_eep_header *modal = &eep->modalHeader;
+ uint8_t tpow_cck[4], tpow_ofdm[4];
+#ifndef IEEE80211_NO_HT
+ uint8_t tpow_cck_ext[4], tpow_ofdm_ext[4];
+ uint8_t tpow_ht20[8], tpow_ht40[8];
+ uint8_t ht40inc;
+#endif
+ int16_t pwr = 0, max_ant_gain, power[ATHN_POWER_COUNT];
+ int i;
+
+ ar9287_set_power_calib(sc, c);
+
+ /* Compute transmit power reduction due to antenna gain. */
+ max_ant_gain = MAX(modal->antennaGainCh[0], modal->antennaGainCh[1]);
+ /* XXX */
+
+ /*
+ * Reduce scaled power by number of active chains to get per-chain
+ * transmit power level.
+ */
+ if (sc->sc_ntxchains == 2)
+ pwr -= AR_PWR_DECREASE_FOR_2_CHAIN;
+ if (pwr < 0)
+ pwr = 0;
+
+ /* Get CCK target powers. */
+ ar5008_get_lg_tpow(sc, c, AR_CTL_11B, eep->calTargetPowerCck,
+ AR9287_NUM_2G_CCK_TARGET_POWERS, tpow_cck);
+
+ /* Get OFDM target powers. */
+ ar5008_get_lg_tpow(sc, c, AR_CTL_11G, eep->calTargetPower2G,
+ AR9287_NUM_2G_20_TARGET_POWERS, tpow_ofdm);
+
+#ifndef IEEE80211_NO_HT
+ /* Get HT-20 target powers. */
+ ar5008_get_ht_tpow(sc, c, AR_CTL_2GHT20, eep->calTargetPower2GHT20,
+ AR9287_NUM_2G_20_TARGET_POWERS, tpow_ht20);
+
+ if (extc != NULL) {
+ /* Get HT-40 target powers. */
+ ar5008_get_ht_tpow(sc, c, AR_CTL_2GHT40,
+ eep->calTargetPower2GHT40, AR9287_NUM_2G_40_TARGET_POWERS,
+ tpow_ht40);
+
+ /* Get secondary channel CCK target powers. */
+ ar5008_get_lg_tpow(sc, extc, AR_CTL_11B,
+ eep->calTargetPowerCck, AR9287_NUM_2G_CCK_TARGET_POWERS,
+ tpow_cck_ext);
+
+ /* Get secondary channel OFDM target powers. */
+ ar5008_get_lg_tpow(sc, extc, AR_CTL_11G,
+ eep->calTargetPower2G, AR9287_NUM_2G_20_TARGET_POWERS,
+ tpow_ofdm_ext);
+ }
+#endif
+
+ memset(power, 0, sizeof(power));
+ /* Shuffle target powers accross transmit rates. */
+ power[ATHN_POWER_OFDM6 ] =
+ power[ATHN_POWER_OFDM9 ] =
+ power[ATHN_POWER_OFDM12 ] =
+ power[ATHN_POWER_OFDM18 ] =
+ power[ATHN_POWER_OFDM24 ] = tpow_ofdm[0];
+ power[ATHN_POWER_OFDM36 ] = tpow_ofdm[1];
+ power[ATHN_POWER_OFDM48 ] = tpow_ofdm[2];
+ power[ATHN_POWER_OFDM54 ] = tpow_ofdm[3];
+ power[ATHN_POWER_XR ] = tpow_ofdm[0];
+ power[ATHN_POWER_CCK1_LP ] = tpow_cck[0];
+ power[ATHN_POWER_CCK2_LP ] =
+ power[ATHN_POWER_CCK2_SP ] = tpow_cck[1];
+ power[ATHN_POWER_CCK55_LP] =
+ power[ATHN_POWER_CCK55_SP] = tpow_cck[2];
+ power[ATHN_POWER_CCK11_LP] =
+ power[ATHN_POWER_CCK11_SP] = tpow_cck[3];
+#ifndef IEEE80211_NO_HT
+ for (i = 0; i < nitems(tpow_ht20); i++)
+ power[ATHN_POWER_HT20(i)] = tpow_ht20[i];
+ if (extc != NULL) {
+ /* Correct PAR difference between HT40 and HT20/Legacy. */
+ if (sc->sc_eep_rev >= AR_EEP_MINOR_VER_2)
+ ht40inc = modal->ht40PowerIncForPdadc;
+ else
+ ht40inc = AR_HT40_POWER_INC_FOR_PDADC;
+ for (i = 0; i < nitems(tpow_ht40); i++)
+ power[ATHN_POWER_HT40(i)] = tpow_ht40[i] + ht40inc;
+ power[ATHN_POWER_OFDM_DUP] = tpow_ht40[0];
+ power[ATHN_POWER_CCK_DUP ] = tpow_ht40[0];
+ power[ATHN_POWER_OFDM_EXT] = tpow_ofdm_ext[0];
+ if (IEEE80211_IS_CHAN_2GHZ(c))
+ power[ATHN_POWER_CCK_EXT] = tpow_cck_ext[0];
+ }
+#endif
+
+ for (i = 0; i < ATHN_POWER_COUNT; i++) {
+ power[i] -= AR_PWR_TABLE_OFFSET_DB * 2; /* In half dB. */
+ if (power[i] > AR_MAX_RATE_POWER)
+ power[i] = AR_MAX_RATE_POWER;
+ }
+ /* Commit transmit power values to hardware. */
+ ar5008_write_txpower(sc, power);
+}
+
+Static void
+ar9287_olpc_init(struct athn_softc *sc)
+{
+ uint32_t reg;
+
+ AR_SETBITS(sc, AR_PHY_TX_PWRCTRL9, AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL);
+
+ reg = AR_READ(sc, AR9287_AN_TXPC0);
+ reg = RW(reg, AR9287_AN_TXPC0_TXPCMODE,
+ AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE);
+ AR_WRITE(sc, AR9287_AN_TXPC0, reg);
+ AR_WRITE_BARRIER(sc);
+ DELAY(100);
+}
+
+Static void
+ar9287_olpc_temp_compensation(struct athn_softc *sc)
+{
+ const struct ar9287_eeprom *eep = sc->sc_eep;
+ int8_t pdadc, slope, tcomp;
+ uint32_t reg;
+
+ reg = AR_READ(sc, AR_PHY_TX_PWRCTRL4);
+ pdadc = MS(reg, AR_PHY_TX_PWRCTRL_PD_AVG_OUT);
+ DPRINTFN(DBG_RF, sc, "PD Avg Out=%d\n", pdadc);
+
+ if (sc->sc_pdadc == 0 || pdadc == 0)
+ return; /* No frames transmitted yet. */
+
+ /* Compute Tx gain temperature compensation. */
+ if (sc->sc_eep_rev >= AR_EEP_MINOR_VER_2)
+ slope = eep->baseEepHeader.tempSensSlope;
+ else
+ slope = 0;
+ if (slope != 0) /* Prevents division by zero. */
+ tcomp = ((pdadc - sc->sc_pdadc) * 4) / slope;
+ else
+ tcomp = 0;
+ DPRINTFN(DBG_RF, sc, "OLPC temp compensation=%d\n", tcomp);
+
+ /* Write compensation value for both Tx chains. */
+ reg = AR_READ(sc, AR_PHY_CH0_TX_PWRCTRL11);
+ reg = RW(reg, AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP, tcomp);
+ AR_WRITE(sc, AR_PHY_CH0_TX_PWRCTRL11, reg);
+
+ reg = AR_READ(sc, AR_PHY_CH1_TX_PWRCTRL11);
+ reg = RW(reg, AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP, tcomp);
+ AR_WRITE(sc, AR_PHY_CH1_TX_PWRCTRL11, reg);
+ AR_WRITE_BARRIER(sc);
+}
+
+PUBLIC void
+ar9287_1_3_enable_async_fifo(struct athn_softc *sc)
+{
+
+ /* Enable ASYNC FIFO. */
+ AR_SETBITS(sc, AR_MAC_PCU_ASYNC_FIFO_REG3,
+ AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
+ AR_SETBITS(sc, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
+ AR_CLRBITS(sc, AR_MAC_PCU_ASYNC_FIFO_REG3,
+ AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
+ AR_SETBITS(sc, AR_MAC_PCU_ASYNC_FIFO_REG3,
+ AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
+ AR_WRITE_BARRIER(sc);
+}
+
+PUBLIC void
+ar9287_1_3_setup_async_fifo(struct athn_softc *sc)
+{
+ uint32_t reg;
+
+ /*
+ * MAC runs at 117MHz (instead of 88/44MHz) when ASYNC FIFO is
+ * enabled, so the following counters have to be changed.
+ */
+ AR_WRITE(sc, AR_D_GBL_IFS_SIFS, AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
+ AR_WRITE(sc, AR_D_GBL_IFS_SLOT, AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
+ AR_WRITE(sc, AR_D_GBL_IFS_EIFS, AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);
+
+ AR_WRITE(sc, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
+ AR_WRITE(sc, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);
+
+ AR_SETBITS(sc, AR_MAC_PCU_LOGIC_ANALYZER,
+ AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
+
+ reg = AR_READ(sc, AR_AHB_MODE);
+ reg = RW(reg, AR_AHB_CUSTOM_BURST, AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
+ AR_WRITE(sc, AR_AHB_MODE, reg);
+
+ AR_SETBITS(sc, AR_PCU_MISC_MODE2, AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
+ AR_WRITE_BARRIER(sc);
+}
diff --git a/sys/dev/ic/arn9287.h b/sys/dev/ic/arn9287.h
new file mode 100644
index 00000000000..00f0bf193c3
--- /dev/null
+++ b/sys/dev/ic/arn9287.h
@@ -0,0 +1,35 @@
+/* $NetBSD: arn9287.h,v 1.1 2013/03/30 02:53:01 christos Exp $ */
+/*
+ * Copyright (c) 2001, 2004 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _IF_ARN9287_H_
+#define _IF_ARN9287_H_
+
+int ar9287_attach(struct athn_softc *);
+void ar9287_1_3_enable_async_fifo(struct athn_softc *);
+void ar9287_1_3_setup_async_fifo(struct athn_softc *);
+
+#endif /* _IF_ARN9287_H_ */
diff --git a/sys/dev/ic/arn9287reg.h b/sys/dev/ic/arn9287reg.h
new file mode 100644
index 00000000000..ae82d730258
--- /dev/null
+++ b/sys/dev/ic/arn9287reg.h
@@ -0,0 +1,539 @@
+/* $NetBSD: arn9287reg.h,v 1.1 2013/03/30 02:53:02 christos Exp $ */
+/* $OpenBSD: ar9287reg.h,v 1.3 2010/07/15 19:07:43 damien Exp $ */
+
+/*-
+ * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr>
+ * Copyright (c) 2008-2009 Atheros Communications Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _ARN9287REG_H_
+#define _ARN9287REG_H_
+
+#define AR9287_MAX_CHAINS 2
+
+#define AR9287_PHY_CCA_MAX_GOOD_VALUE (-118)
+
+/*
+ * Analog registers.
+ */
+#define AR9287_AN_RF2G3_CH0 0x7808
+#define AR9287_AN_RF2G3_CH1 0x785c
+#define AR9287_AN_TXPC0 0x7898
+#define AR9287_AN_TOP2 0x78b4
+
+/* Bits for AR9287_AN_RF2G3_CH[01]. */
+#define AR9287_AN_RF2G3_OB_PAL_OFF_M 0x0001c000
+#define AR9287_AN_RF2G3_OB_PAL_OFF_S 14
+#define AR9287_AN_RF2G3_OB_QAM_M 0x000e0000
+#define AR9287_AN_RF2G3_OB_QAM_S 17
+#define AR9287_AN_RF2G3_OB_PSK_M 0x00700000
+#define AR9287_AN_RF2G3_OB_PSK_S 20
+#define AR9287_AN_RF2G3_OB_CCK_M 0x03800000
+#define AR9287_AN_RF2G3_OB_CCK_S 23
+#define AR9287_AN_RF2G3_DB2_M 0x1c000000
+#define AR9287_AN_RF2G3_DB2_S 26
+#define AR9287_AN_RF2G3_DB1_M 0xe0000000
+#define AR9287_AN_RF2G3_DB1_S 29
+
+/* Bits for AR9287_AN_TXPC0. */
+#define AR9287_AN_TXPC0_TXPCMODE_M 0x0000c000
+#define AR9287_AN_TXPC0_TXPCMODE_S 14
+#define AR9287_AN_TXPC0_TXPCMODE_NORMAL 0
+#define AR9287_AN_TXPC0_TXPCMODE_TEST 1
+#define AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE 2
+#define AR9287_AN_TXPC0_TXPCMODE_ATBTEST 3
+
+/* Bits for AR9287_AN_TOP2. */
+#define AR9287_AN_TOP2_XPABIAS_LVL_M 0xc0000000
+#define AR9287_AN_TOP2_XPABIAS_LVL_S 30
+
+/*
+ * ROM layout used by AR9287 (2GHz only).
+ */
+#define AR9287_EEP_START_LOC 128
+#define AR9287_NUM_2G_CAL_PIERS 3
+#define AR9287_NUM_2G_CCK_TARGET_POWERS 3
+#define AR9287_NUM_2G_20_TARGET_POWERS 3
+#define AR9287_NUM_2G_40_TARGET_POWERS 3
+#define AR9287_NUM_CTLS 12
+#define AR9287_NUM_BAND_EDGES 4
+#define AR9287_NUM_PD_GAINS 4
+#define AR9287_PD_GAINS_IN_MASK 4
+#define AR9287_PD_GAIN_ICEPTS 1
+#define AR9287_MAX_RATE_POWER 63
+#define AR9287_NUM_RATES 16
+
+struct ar9287_base_eep_header {
+ uint16_t length;
+ uint16_t checksum;
+ uint16_t version;
+ uint8_t opCapFlags;
+ uint8_t eepMisc;
+#define AR9287_EEPMISC_BIG_ENDIAN 0x01
+#define AR9287_EEPMISC_WOW 0x02
+
+ uint16_t regDmn[2];
+ uint8_t macAddr[6];
+ uint8_t rxMask;
+ uint8_t txMask;
+ uint16_t rfSilent;
+ uint16_t blueToothOptions;
+ uint16_t deviceCap;
+ uint32_t binBuildNumber;
+ uint8_t deviceType;
+ /* End of common header. */
+ uint8_t openLoopPwrCntl;
+ int8_t pwrTableOffset;
+ int8_t tempSensSlope;
+ int8_t tempSensSlopePalOn;
+ uint8_t futureBase[29];
+} __packed;
+
+struct ar9287_modal_eep_header {
+ uint32_t antCtrlChain[AR9287_MAX_CHAINS];
+ uint32_t antCtrlCommon;
+ int8_t antennaGainCh[AR9287_MAX_CHAINS];
+ uint8_t switchSettling;
+ uint8_t txRxAttenCh[AR9287_MAX_CHAINS];
+ uint8_t rxTxMarginCh[AR9287_MAX_CHAINS];
+ int8_t adcDesiredSize;
+ uint8_t txEndToXpaOff;
+ uint8_t txEndToRxOn;
+ uint8_t txFrameToXpaOn;
+ uint8_t thresh62;
+ int8_t noiseFloorThreshCh[AR9287_MAX_CHAINS];
+ uint8_t xpdGain;
+ uint8_t xpd;
+ int8_t iqCalICh[AR9287_MAX_CHAINS];
+ int8_t iqCalQCh[AR9287_MAX_CHAINS];
+ uint8_t pdGainOverlap;
+ uint8_t xpaBiasLvl;
+ uint8_t txFrameToDataStart;
+ uint8_t txFrameToPaOn;
+ uint8_t ht40PowerIncForPdadc;
+ uint8_t bswAtten[AR9287_MAX_CHAINS];
+ uint8_t bswMargin[AR9287_MAX_CHAINS];
+ uint8_t swSettleHt40;
+ uint8_t version;
+ uint8_t db1;
+ uint8_t db2;
+ uint8_t ob_cck;
+ uint8_t ob_psk;
+ uint8_t ob_qam;
+ uint8_t ob_pal_off;
+ uint8_t futureModal[30];
+ struct ar_spur_chan spurChans[AR_EEPROM_MODAL_SPURS];
+} __packed;
+
+struct ar9287_cal_data_per_freq {
+ uint8_t pwrPdg[AR9287_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS];
+ uint8_t vpdPdg[AR9287_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS];
+} __packed;
+
+union ar9287_cal_data_per_freq_u {
+ struct ar_cal_data_per_freq_olpc calDataOpen;
+ struct ar9287_cal_data_per_freq calDataClose;
+} __packed;
+
+struct ar9287_cal_ctl_data {
+ struct ar_cal_ctl_edges
+ ctlEdges[AR9287_MAX_CHAINS][AR9287_NUM_BAND_EDGES];
+} __packed;
+
+struct ar9287_eeprom {
+ struct ar9287_base_eep_header baseEepHeader;
+ uint8_t custData[32];
+ struct ar9287_modal_eep_header modalHeader;
+ uint8_t calFreqPier2G[AR9287_NUM_2G_CAL_PIERS];
+ union ar9287_cal_data_per_freq_u
+ calPierData2G[AR9287_MAX_CHAINS][AR9287_NUM_2G_CAL_PIERS];
+ struct ar_cal_target_power_leg
+ calTargetPowerCck[AR9287_NUM_2G_CCK_TARGET_POWERS];
+ struct ar_cal_target_power_leg
+ calTargetPower2G[AR9287_NUM_2G_20_TARGET_POWERS];
+ struct ar_cal_target_power_ht
+ calTargetPower2GHT20[AR9287_NUM_2G_20_TARGET_POWERS];
+ struct ar_cal_target_power_ht
+ calTargetPower2GHT40[AR9287_NUM_2G_40_TARGET_POWERS];
+ uint8_t ctlIndex[AR9287_NUM_CTLS];
+ struct ar9287_cal_ctl_data ctlData[AR9287_NUM_CTLS];
+ uint8_t padding;
+} __packed;
+
+/* Macro to "pack" registers to 16-bit to save some .rodata space. */
+#define P(x) (x)
+
+/*
+ * AR9287 1.1 initialization values.
+ */
+static const uint16_t ar9287_1_1_regs[] = {
+ P(0x01030), P(0x01070), P(0x010b0), P(0x010f0), P(0x08014),
+ P(0x0801c), P(0x08120), P(0x081d0), P(0x08318), P(0x09804),
+ P(0x09820), P(0x09824), P(0x09828), P(0x09834), P(0x09838),
+ P(0x09840), P(0x09844), P(0x09850), P(0x09858), P(0x0985c),
+ P(0x09860), P(0x09864), P(0x09868), P(0x0986c), P(0x09914),
+ P(0x09918), P(0x09924), P(0x09944), P(0x09960), P(0x0a960),
+ P(0x09964), P(0x0c968), P(0x099b8), P(0x099bc), P(0x099c0),
+ P(0x0a204), P(0x0a20c), P(0x0b20c), P(0x0a21c), P(0x0a230),
+ P(0x0a250), P(0x0a358), P(0x0a3d8)
+};
+
+#ifndef IEEE80211_NO_HT
+static const uint32_t ar9287_1_1_vals_2g40[] = {
+ 0x000002c0, 0x00000318, 0x00007c70, 0x00000000, 0x10801600,
+ 0x12e00057, 0x08f04810, 0x0000320a, 0x00006880, 0x000003c4,
+ 0x02020200, 0x01000e0e, 0x3a020001, 0x00000e0e, 0x00000007,
+ 0x206a012e, 0x037216a0, 0x6d4000e2, 0x7ec84d2e, 0x3139605e,
+ 0x00058d20, 0x0001ce00, 0x5ac640d0, 0x06903881, 0x00001130,
+ 0x00000016, 0xd00a8a0d, 0xefbc1010, 0x00000010, 0x00000010,
+ 0x00000210, 0x000003ce, 0x0000001c, 0x00000c00, 0x05eea6d4,
+ 0x00000444, 0x00000000, 0x00000000, 0x1883800a, 0x00000210,
+ 0x0004a000, 0x7999aa0e, 0x00000000
+};
+#endif
+
+static const uint32_t ar9287_1_1_vals_2g20[] = {
+ 0x00000160, 0x0000018c, 0x00003e38, 0x00000000, 0x08400b00,
+ 0x12e0002b, 0x08f04810, 0x0000320a, 0x00003440, 0x00000300,
+ 0x02020200, 0x01000e0e, 0x3a020001, 0x00000e0e, 0x00000007,
+ 0x206a012e, 0x037216a0, 0x6c4000e2, 0x7ec84d2e, 0x31395d5e,
+ 0x00058d20, 0x0001ce00, 0x5ac640d0, 0x06903881, 0x00000898,
+ 0x0000000b, 0xd00a8a0d, 0xefbc1010, 0x00000010, 0x00000010,
+ 0x00000210, 0x000003ce, 0x0000001c, 0x00000c00, 0x05eea6d4,
+ 0x00000444, 0x00000000, 0x00000000, 0x1883800a, 0x00000108,
+ 0x0004a000, 0x7999aa0e, 0x00000000
+};
+
+static const uint16_t ar9287_1_1_cm_regs[] = {
+ P(0x0000c), P(0x00030), P(0x00034), P(0x00040), P(0x00044),
+ P(0x00048), P(0x0004c), P(0x00050), P(0x00054), P(0x00800),
+ P(0x00804), P(0x00808), P(0x0080c), P(0x00810), P(0x00814),
+ P(0x00818), P(0x0081c), P(0x00820), P(0x00824), P(0x01040),
+ P(0x01044), P(0x01048), P(0x0104c), P(0x01050), P(0x01054),
+ P(0x01058), P(0x0105c), P(0x01060), P(0x01064), P(0x01230),
+ P(0x01270), P(0x01038), P(0x01078), P(0x010b8), P(0x010f8),
+ P(0x01138), P(0x01178), P(0x011b8), P(0x011f8), P(0x01238),
+ P(0x01278), P(0x012b8), P(0x012f8), P(0x01338), P(0x01378),
+ P(0x013b8), P(0x013f8), P(0x01438), P(0x01478), P(0x014b8),
+ P(0x014f8), P(0x01538), P(0x01578), P(0x015b8), P(0x015f8),
+ P(0x01638), P(0x01678), P(0x016b8), P(0x016f8), P(0x01738),
+ P(0x01778), P(0x017b8), P(0x017f8), P(0x0103c), P(0x0107c),
+ P(0x010bc), P(0x010fc), P(0x0113c), P(0x0117c), P(0x011bc),
+ P(0x011fc), P(0x0123c), P(0x0127c), P(0x012bc), P(0x012fc),
+ P(0x0133c), P(0x0137c), P(0x013bc), P(0x013fc), P(0x0143c),
+ P(0x0147c), P(0x04030), P(0x0403c), P(0x04024), P(0x04060),
+ P(0x04064), P(0x07010), P(0x07020), P(0x07034), P(0x07038),
+ P(0x08004), P(0x08008), P(0x0800c), P(0x08018), P(0x08020),
+ P(0x08038), P(0x0803c), P(0x08048), P(0x08054), P(0x08058),
+ P(0x0805c), P(0x08060), P(0x08064), P(0x08070), P(0x080c0),
+ P(0x080c4), P(0x080c8), P(0x080cc), P(0x080d0), P(0x080d4),
+ P(0x080d8), P(0x080e0), P(0x080e4), P(0x080e8), P(0x080ec),
+ P(0x080f0), P(0x080f4), P(0x080f8), P(0x080fc), P(0x08100),
+ P(0x08104), P(0x08108), P(0x0810c), P(0x08110), P(0x08118),
+ P(0x0811c), P(0x08124), P(0x08128), P(0x0812c), P(0x08130),
+ P(0x08134), P(0x08138), P(0x0813c), P(0x08144), P(0x08168),
+ P(0x0816c), P(0x08170), P(0x08174), P(0x08178), P(0x0817c),
+ P(0x081c0), P(0x081c4), P(0x081d4), P(0x081ec), P(0x081f0),
+ P(0x081f4), P(0x081f8), P(0x081fc), P(0x08200), P(0x08204),
+ P(0x08208), P(0x0820c), P(0x08210), P(0x08214), P(0x08218),
+ P(0x0821c), P(0x08220), P(0x08224), P(0x08228), P(0x0822c),
+ P(0x08230), P(0x08234), P(0x08238), P(0x0823c), P(0x08240),
+ P(0x08244), P(0x08248), P(0x0824c), P(0x08250), P(0x08254),
+ P(0x08258), P(0x0825c), P(0x08260), P(0x08264), P(0x08270),
+ P(0x08274), P(0x08278), P(0x0827c), P(0x08284), P(0x08288),
+ P(0x0828c), P(0x08294), P(0x08298), P(0x0829c), P(0x08300),
+ P(0x08314), P(0x08328), P(0x0832c), P(0x08330), P(0x08334),
+ P(0x08338), P(0x0833c), P(0x08340), P(0x08344), P(0x08360),
+ P(0x08364), P(0x08368), P(0x08370), P(0x08374), P(0x08378),
+ P(0x0837c), P(0x08380), P(0x08384), P(0x08390), P(0x08394),
+ P(0x08398), P(0x0839c), P(0x083a0), P(0x09808), P(0x0980c),
+ P(0x09810), P(0x09814), P(0x0981c), P(0x0982c), P(0x09830),
+ P(0x0983c), P(0x0984c), P(0x0a84c), P(0x09854), P(0x09900),
+ P(0x09904), P(0x09908), P(0x0990c), P(0x09910), P(0x0991c),
+ P(0x09920), P(0x0a920), P(0x09928), P(0x0992c), P(0x09930),
+ P(0x0a930), P(0x09934), P(0x09938), P(0x0993c), P(0x09948),
+ P(0x0994c), P(0x09954), P(0x09958), P(0x09940), P(0x0c95c),
+ P(0x09970), P(0x09974), P(0x09978), P(0x0997c), P(0x099a0),
+ P(0x099a4), P(0x099a8), P(0x099ac), P(0x099b0), P(0x099b4),
+ P(0x099c4), P(0x099c8), P(0x099cc), P(0x099d0), P(0x099dc),
+ P(0x099e0), P(0x099e4), P(0x099e8), P(0x099ec), P(0x099f0),
+ P(0x099fc), P(0x0a208), P(0x0a210), P(0x0a214), P(0x0a218),
+ P(0x0a220), P(0x0a224), P(0x0a228), P(0x0a22c), P(0x0a234),
+ P(0x0a238), P(0x0a23c), P(0x0a240), P(0x0a244), P(0x0a248),
+ P(0x0a24c), P(0x0a254), P(0x0a258), P(0x0a25c), P(0x0a260),
+ P(0x0a264), P(0x0b264), P(0x0a268), P(0x0a26c), P(0x0b26c),
+ P(0x0d270), P(0x0a278), P(0x0a27c), P(0x0d35c), P(0x0d360),
+ P(0x0d364), P(0x0d368), P(0x0d36c), P(0x0d370), P(0x0d374),
+ P(0x0d378), P(0x0d37c), P(0x0d380), P(0x0d384), P(0x0a388),
+ P(0x0a38c), P(0x0a390), P(0x0a394), P(0x0a398), P(0x0b398),
+ P(0x0a39c), P(0x0a3c8), P(0x0a3cc), P(0x0a3d0), P(0x0a3d4),
+ P(0x0a3dc), P(0x0a3e0), P(0x0a3e4), P(0x0a3e8), P(0x0a3ec),
+ P(0x0a3f0), P(0x0a3f4), P(0x0b3f4), P(0x0a7d8), P(0x07800),
+ P(0x07804), P(0x07808), P(0x0780c), P(0x07810), P(0x07814),
+ P(0x07818), P(0x0781c), P(0x07820), P(0x07824), P(0x07828),
+ P(0x0782c), P(0x07830), P(0x07834), P(0x07838), P(0x0783c),
+ P(0x07840), P(0x07844), P(0x07848), P(0x07850), P(0x07854),
+ P(0x07858), P(0x0785c), P(0x07860), P(0x07864), P(0x07868),
+ P(0x0786c), P(0x07870), P(0x07874), P(0x07878), P(0x0787c),
+ P(0x07880), P(0x07884), P(0x07888), P(0x0788c), P(0x07890),
+ P(0x07894), P(0x07898), P(0x0789c), P(0x078a0), P(0x078a4),
+ P(0x078a8), P(0x078ac), P(0x078b0), P(0x078b4), P(0x078b8)
+};
+
+static const uint32_t ar9287_1_1_cm_vals[] = {
+ 0x00000000, 0x00020015, 0x00000005, 0x00000000, 0x00000008,
+ 0x00000008, 0x00000010, 0x00000000, 0x0000001f, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x002ffc0f,
+ 0x002ffc0f, 0x002ffc0f, 0x002ffc0f, 0x002ffc0f, 0x002ffc0f,
+ 0x002ffc0f, 0x002ffc0f, 0x002ffc0f, 0x002ffc0f, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000002, 0x00000002, 0x0000001f, 0x00000000,
+ 0x00000000, 0x00000033, 0x00000000, 0x00000002, 0x000004c2,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000700, 0x00000000,
+ 0x00000000, 0x00000000, 0x40000000, 0x00000000, 0x00000000,
+ 0x000fc78f, 0x0000000f, 0x00000000, 0x00000000, 0x2a80001a,
+ 0x05dc01e0, 0x1f402710, 0x01f40000, 0x00001e00, 0x00000000,
+ 0x00400000, 0xffffffff, 0x0000ffff, 0x003f3f3f, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00020000, 0x00020000,
+ 0x00000001, 0x00000052, 0x00000000, 0x00000168, 0x000100aa,
+ 0x00003210, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0xffffffff, 0x00000000,
+ 0x00000000, 0x18487320, 0xfaa4fa50, 0x00000100, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00100000,
+ 0x0010f400, 0x00000100, 0x0001e800, 0x00000000, 0x00000000,
+ 0x00000000, 0x400000ff, 0x00080922, 0x88a00010, 0x00000000,
+ 0x40000000, 0x003e4180, 0x00000000, 0x0000002c, 0x0000002c,
+ 0x000000ff, 0x00000000, 0x00000000, 0x00000000, 0x00000040,
+ 0x00000000, 0x00000000, 0x00000007, 0x00000302, 0x00000e00,
+ 0x00ff0000, 0x00000000, 0x000107ff, 0x01c81043, 0xffffffff,
+ 0xffffffff, 0x00000000, 0x00000000, 0x000000ff, 0x00000000,
+ 0x00000000, 0xffffffff, 0xffffffff, 0x0fffffff, 0x0fffffff,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xafe68e30,
+ 0xfd14e000, 0x9c0a9f6b, 0x00000000, 0x0000a000, 0x00000000,
+ 0x00200400, 0x0040233c, 0x0040233c, 0x00000044, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x10002310, 0x10000fff,
+ 0x04900000, 0x04900000, 0x00000001, 0x00000004, 0x00000000,
+ 0x00000000, 0x1e1f2022, 0x0a0b0c0d, 0x00000000, 0x9280c00a,
+ 0x00020028, 0x5f3ca3de, 0x0108ecff, 0x14750604, 0x004b6a8e,
+ 0x990bb514, 0x00000000, 0x00000001, 0x00000000, 0x00000000,
+ 0x00000001, 0x201fff00, 0x0c6f0000, 0x03051000, 0x00000820,
+ 0x06336f77, 0x6af6532f, 0x08f186c8, 0x00046384, 0x00000000,
+ 0x00000000, 0xaaaaaaaa, 0x3c466478, 0x0cc80caa, 0x00000000,
+ 0x00001042, 0x803e4788, 0x4080a333, 0x40206c10, 0x009c4060,
+ 0x01834061, 0x00000400, 0x000003b5, 0x233f7180, 0x20202020,
+ 0x20202020, 0x13c889af, 0x38490a20, 0x00000000, 0xfffffffc,
+ 0x00000000, 0x00000000, 0x0cdbd380, 0x0f0f0f01, 0xdfa91f01,
+ 0x00418a11, 0x00418a11, 0x00000000, 0x0e79e5c6, 0x0e79e5c6,
+ 0x00820820, 0x1ce739ce, 0x050701ce, 0x07ffffef, 0x0fffffe7,
+ 0x17ffffe5, 0x1fffffe4, 0x37ffffe3, 0x3fffffe3, 0x57ffffe3,
+ 0x5fffffe2, 0x7fffffe2, 0x7f3c7bba, 0xf3307ff0, 0x0c000000,
+ 0x20202020, 0x20202020, 0x1ce739ce, 0x000001ce, 0x000001ce,
+ 0x00000001, 0x00000246, 0x20202020, 0x20202020, 0x20202020,
+ 0x1ce739ce, 0x000001ce, 0x00000000, 0x18c43433, 0x00f70081,
+ 0x01036a1e, 0x00000000, 0x00000000, 0x000003f1, 0x00000800,
+ 0x6c35ffd2, 0x6db6c000, 0x6db6cb30, 0x6db6cb6c, 0x0501e200,
+ 0x0094128d, 0x976ee392, 0xf75ff6fc, 0x00040000, 0xdb003012,
+ 0x04924914, 0x21084210, 0x00140000, 0x0e4548d8, 0x54214514,
+ 0x02025830, 0x71c0d388, 0x934934a8, 0x00000000, 0x00000800,
+ 0x6c35ffd2, 0x6db6c000, 0x6db6cb30, 0x6db6cb6c, 0x0501e200,
+ 0x0094128d, 0x976ee392, 0xf75ff6fc, 0x00040000, 0xdb003012,
+ 0x04924914, 0x21084210, 0x001b6db0, 0x00376b63, 0x06db6db6,
+ 0x006d8000, 0x48100000, 0x00000000, 0x08000000, 0x0007ffd8,
+ 0x0007ffd8, 0x001c0020, 0x00060aeb, 0x40008080, 0x2a850160
+};
+
+static const struct athn_ini ar9287_1_1_ini = {
+ .nregs = __arraycount(ar9287_1_1_regs),
+ .regs = ar9287_1_1_regs,
+ .vals_5g20 = NULL, /* 2GHz only. */
+#ifndef IEEE80211_NO_HT
+ .vals_5g40 = NULL, /* 2GHz only. */
+ .vals_2g40 = ar9287_1_1_vals_2g40,
+#endif
+ .vals_2g20 = ar9287_1_1_vals_2g20,
+ .ncmregs = __arraycount(ar9287_1_1_cm_regs),
+ .cmregs = ar9287_1_1_cm_regs,
+ .cmvals = ar9287_1_1_cm_vals
+};
+
+/*
+ * AR9287 1.1 Tx gains.
+ */
+static const uint16_t ar9287_1_1_tx_gain_regs[] = {
+ P(0x0a300), P(0x0a304), P(0x0a308), P(0x0a30c), P(0x0a310),
+ P(0x0a314), P(0x0a318), P(0x0a31c), P(0x0a320), P(0x0a324),
+ P(0x0a328), P(0x0a32c), P(0x0a330), P(0x0a334), P(0x0a338),
+ P(0x0a33c), P(0x0a340), P(0x0a344), P(0x0a348), P(0x0a34c),
+ P(0x0a350), P(0x0a354), P(0x0a780), P(0x0a784), P(0x0a788),
+ P(0x0a78c), P(0x0a790), P(0x0a794), P(0x0a798), P(0x0a79c),
+ P(0x0a7a0), P(0x0a7a4), P(0x0a7a8), P(0x0a7ac), P(0x0a7b0),
+ P(0x0a7b4), P(0x0a7b8), P(0x0a7bc), P(0x0a7c0), P(0x0a7c4),
+ P(0x0a7c8), P(0x0a7cc), P(0x0a7d0), P(0x0a7d4), P(0x0a274)
+};
+
+static const uint32_t ar9287_1_1_tx_gain_vals_2g[] = {
+ 0x00000000, 0x00004002, 0x00008004, 0x0000c00a, 0x0001000c,
+ 0x0001420b, 0x0001824a, 0x0001c44a, 0x0002064a, 0x0002484a,
+ 0x00028a4a, 0x0002cc4a, 0x00030e4a, 0x00034e8a, 0x00038e8c,
+ 0x0003cecc, 0x00040ed4, 0x00044edc, 0x00048ede, 0x0004cf1e,
+ 0x00050f5e, 0x00054f9e, 0x00000062, 0x00004064, 0x000080a4,
+ 0x0000c0aa, 0x000100ac, 0x000140b4, 0x000180f4, 0x0001c134,
+ 0x00020174, 0x0002417c, 0x0002817e, 0x0002c1be, 0x000301fe,
+ 0x000301fe, 0x000301fe, 0x000301fe, 0x000301fe, 0x000301fe,
+ 0x000301fe, 0x000301fe, 0x000301fe, 0x000301fe, 0x0a1aa000
+};
+
+static const struct athn_gain ar9287_1_1_tx_gain = {
+ __arraycount(ar9287_1_1_tx_gain_regs),
+ ar9287_1_1_tx_gain_regs,
+ NULL, /* 2GHz only. */
+ ar9287_1_1_tx_gain_vals_2g
+};
+
+/*
+ * AR9287 1.1 Rx gains.
+ */
+static const uint16_t ar9287_1_1_rx_gain_regs[] = {
+ P(0x09a00), P(0x09a04), P(0x09a08), P(0x09a0c), P(0x09a10),
+ P(0x09a14), P(0x09a18), P(0x09a1c), P(0x09a20), P(0x09a24),
+ P(0x09a28), P(0x09a2c), P(0x09a30), P(0x09a34), P(0x09a38),
+ P(0x09a3c), P(0x09a40), P(0x09a44), P(0x09a48), P(0x09a4c),
+ P(0x09a50), P(0x09a54), P(0x09a58), P(0x09a5c), P(0x09a60),
+ P(0x09a64), P(0x09a68), P(0x09a6c), P(0x09a70), P(0x09a74),
+ P(0x09a78), P(0x09a7c), P(0x09a80), P(0x09a84), P(0x09a88),
+ P(0x09a8c), P(0x09a90), P(0x09a94), P(0x09a98), P(0x09a9c),
+ P(0x09aa0), P(0x09aa4), P(0x09aa8), P(0x09aac), P(0x09ab0),
+ P(0x09ab4), P(0x09ab8), P(0x09abc), P(0x09ac0), P(0x09ac4),
+ P(0x09ac8), P(0x09acc), P(0x09ad0), P(0x09ad4), P(0x09ad8),
+ P(0x09adc), P(0x09ae0), P(0x09ae4), P(0x09ae8), P(0x09aec),
+ P(0x09af0), P(0x09af4), P(0x09af8), P(0x09afc), P(0x09b00),
+ P(0x09b04), P(0x09b08), P(0x09b0c), P(0x09b10), P(0x09b14),
+ P(0x09b18), P(0x09b1c), P(0x09b20), P(0x09b24), P(0x09b28),
+ P(0x09b2c), P(0x09b30), P(0x09b34), P(0x09b38), P(0x09b3c),
+ P(0x09b40), P(0x09b44), P(0x09b48), P(0x09b4c), P(0x09b50),
+ P(0x09b54), P(0x09b58), P(0x09b5c), P(0x09b60), P(0x09b64),
+ P(0x09b68), P(0x09b6c), P(0x09b70), P(0x09b74), P(0x09b78),
+ P(0x09b7c), P(0x09b80), P(0x09b84), P(0x09b88), P(0x09b8c),
+ P(0x09b90), P(0x09b94), P(0x09b98), P(0x09b9c), P(0x09ba0),
+ P(0x09ba4), P(0x09ba8), P(0x09bac), P(0x09bb0), P(0x09bb4),
+ P(0x09bb8), P(0x09bbc), P(0x09bc0), P(0x09bc4), P(0x09bc8),
+ P(0x09bcc), P(0x09bd0), P(0x09bd4), P(0x09bd8), P(0x09bdc),
+ P(0x09be0), P(0x09be4), P(0x09be8), P(0x09bec), P(0x09bf0),
+ P(0x09bf4), P(0x09bf8), P(0x09bfc), P(0x0aa00), P(0x0aa04),
+ P(0x0aa08), P(0x0aa0c), P(0x0aa10), P(0x0aa14), P(0x0aa18),
+ P(0x0aa1c), P(0x0aa20), P(0x0aa24), P(0x0aa28), P(0x0aa2c),
+ P(0x0aa30), P(0x0aa34), P(0x0aa38), P(0x0aa3c), P(0x0aa40),
+ P(0x0aa44), P(0x0aa48), P(0x0aa4c), P(0x0aa50), P(0x0aa54),
+ P(0x0aa58), P(0x0aa5c), P(0x0aa60), P(0x0aa64), P(0x0aa68),
+ P(0x0aa6c), P(0x0aa70), P(0x0aa74), P(0x0aa78), P(0x0aa7c),
+ P(0x0aa80), P(0x0aa84), P(0x0aa88), P(0x0aa8c), P(0x0aa90),
+ P(0x0aa94), P(0x0aa98), P(0x0aa9c), P(0x0aaa0), P(0x0aaa4),
+ P(0x0aaa8), P(0x0aaac), P(0x0aab0), P(0x0aab4), P(0x0aab8),
+ P(0x0aabc), P(0x0aac0), P(0x0aac4), P(0x0aac8), P(0x0aacc),
+ P(0x0aad0), P(0x0aad4), P(0x0aad8), P(0x0aadc), P(0x0aae0),
+ P(0x0aae4), P(0x0aae8), P(0x0aaec), P(0x0aaf0), P(0x0aaf4),
+ P(0x0aaf8), P(0x0aafc), P(0x0ab00), P(0x0ab04), P(0x0ab08),
+ P(0x0ab0c), P(0x0ab10), P(0x0ab14), P(0x0ab18), P(0x0ab1c),
+ P(0x0ab20), P(0x0ab24), P(0x0ab28), P(0x0ab2c), P(0x0ab30),
+ P(0x0ab34), P(0x0ab38), P(0x0ab3c), P(0x0ab40), P(0x0ab44),
+ P(0x0ab48), P(0x0ab4c), P(0x0ab50), P(0x0ab54), P(0x0ab58),
+ P(0x0ab5c), P(0x0ab60), P(0x0ab64), P(0x0ab68), P(0x0ab6c),
+ P(0x0ab70), P(0x0ab74), P(0x0ab78), P(0x0ab7c), P(0x0ab80),
+ P(0x0ab84), P(0x0ab88), P(0x0ab8c), P(0x0ab90), P(0x0ab94),
+ P(0x0ab98), P(0x0ab9c), P(0x0aba0), P(0x0aba4), P(0x0aba8),
+ P(0x0abac), P(0x0abb0), P(0x0abb4), P(0x0abb8), P(0x0abbc),
+ P(0x0abc0), P(0x0abc4), P(0x0abc8), P(0x0abcc), P(0x0abd0),
+ P(0x0abd4), P(0x0abd8), P(0x0abdc), P(0x0abe0), P(0x0abe4),
+ P(0x0abe8), P(0x0abec), P(0x0abf0), P(0x0abf4), P(0x0abf8),
+ P(0x0abfc), P(0x09848), P(0x0a848)
+};
+
+static const uint32_t ar9287_1_1_rx_gain_vals_2g[] = {
+ 0x0000a120, 0x0000a124, 0x0000a128, 0x0000a12c, 0x0000a130,
+ 0x0000a194, 0x0000a198, 0x0000a20c, 0x0000a210, 0x0000a284,
+ 0x0000a288, 0x0000a28c, 0x0000a290, 0x0000a294, 0x0000a2a0,
+ 0x0000a2a4, 0x0000a2a8, 0x0000a2ac, 0x0000a2b0, 0x0000a2b4,
+ 0x0000a2b8, 0x0000a2c4, 0x0000a708, 0x0000a70c, 0x0000a710,
+ 0x0000ab04, 0x0000ab08, 0x0000ab0c, 0x0000ab10, 0x0000ab14,
+ 0x0000ab18, 0x0000ab8c, 0x0000ab90, 0x0000ab94, 0x0000ab98,
+ 0x0000aba4, 0x0000aba8, 0x0000cb04, 0x0000cb08, 0x0000cb0c,
+ 0x0000cb10, 0x0000cb14, 0x0000cb18, 0x0000cb8c, 0x0000cb90,
+ 0x0000cf18, 0x0000cf24, 0x0000cf28, 0x0000d314, 0x0000d318,
+ 0x0000d38c, 0x0000d390, 0x0000d394, 0x0000d398, 0x0000d3a4,
+ 0x0000d3a8, 0x0000d3ac, 0x0000d3b0, 0x0000f380, 0x0000f384,
+ 0x0000f388, 0x0000f710, 0x0000f714, 0x0000f718, 0x0000fb10,
+ 0x0000fb14, 0x0000fb18, 0x0000fb8c, 0x0000fb90, 0x0000fb94,
+ 0x0000ff8c, 0x0000ff90, 0x0000ff94, 0x0000ffa0, 0x0000ffa4,
+ 0x0000ffa8, 0x0000ffac, 0x0000ffb0, 0x0000ffb4, 0x0000ffa1,
+ 0x0000ffa5, 0x0000ffa9, 0x0000ffad, 0x0000ffb1, 0x0000ffb5,
+ 0x0000ffb9, 0x0000ffc5, 0x0000ffc9, 0x0000ffcd, 0x0000ffd1,
+ 0x0000ffd5, 0x0000ffc2, 0x0000ffc6, 0x0000ffca, 0x0000ffce,
+ 0x0000ffd2, 0x0000ffd6, 0x0000ffda, 0x0000ffc7, 0x0000ffcb,
+ 0x0000ffcf, 0x0000ffd3, 0x0000ffd7, 0x0000ffdb, 0x0000ffdb,
+ 0x0000ffdb, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb,
+ 0x0000ffdb, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb,
+ 0x0000ffdb, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb,
+ 0x0000ffdb, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb,
+ 0x0000ffdb, 0x0000ffdb, 0x0000ffdb, 0x0000a120, 0x0000a124,
+ 0x0000a128, 0x0000a12c, 0x0000a130, 0x0000a194, 0x0000a198,
+ 0x0000a20c, 0x0000a210, 0x0000a284, 0x0000a288, 0x0000a28c,
+ 0x0000a290, 0x0000a294, 0x0000a2a0, 0x0000a2a4, 0x0000a2a8,
+ 0x0000a2ac, 0x0000a2b0, 0x0000a2b4, 0x0000a2b8, 0x0000a2c4,
+ 0x0000a708, 0x0000a70c, 0x0000a710, 0x0000ab04, 0x0000ab08,
+ 0x0000ab0c, 0x0000ab10, 0x0000ab14, 0x0000ab18, 0x0000ab8c,
+ 0x0000ab90, 0x0000ab94, 0x0000ab98, 0x0000aba4, 0x0000aba8,
+ 0x0000cb04, 0x0000cb08, 0x0000cb0c, 0x0000cb10, 0x0000cb14,
+ 0x0000cb18, 0x0000cb8c, 0x0000cb90, 0x0000cf18, 0x0000cf24,
+ 0x0000cf28, 0x0000d314, 0x0000d318, 0x0000d38c, 0x0000d390,
+ 0x0000d394, 0x0000d398, 0x0000d3a4, 0x0000d3a8, 0x0000d3ac,
+ 0x0000d3b0, 0x0000f380, 0x0000f384, 0x0000f388, 0x0000f710,
+ 0x0000f714, 0x0000f718, 0x0000fb10, 0x0000fb14, 0x0000fb18,
+ 0x0000fb8c, 0x0000fb90, 0x0000fb94, 0x0000ff8c, 0x0000ff90,
+ 0x0000ff94, 0x0000ffa0, 0x0000ffa4, 0x0000ffa8, 0x0000ffac,
+ 0x0000ffb0, 0x0000ffb4, 0x0000ffa1, 0x0000ffa5, 0x0000ffa9,
+ 0x0000ffad, 0x0000ffb1, 0x0000ffb5, 0x0000ffb9, 0x0000ffc5,
+ 0x0000ffc9, 0x0000ffcd, 0x0000ffd1, 0x0000ffd5, 0x0000ffc2,
+ 0x0000ffc6, 0x0000ffca, 0x0000ffce, 0x0000ffd2, 0x0000ffd6,
+ 0x0000ffda, 0x0000ffc7, 0x0000ffcb, 0x0000ffcf, 0x0000ffd3,
+ 0x0000ffd7, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb,
+ 0x0000ffdb, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb,
+ 0x0000ffdb, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb,
+ 0x0000ffdb, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb,
+ 0x0000ffdb, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb,
+ 0x0000ffdb, 0x00001067, 0x00001067
+};
+
+static const struct athn_gain ar9287_1_1_rx_gain = {
+ __arraycount(ar9287_1_1_rx_gain_regs),
+ ar9287_1_1_rx_gain_regs,
+ NULL, /* 2GHz only. */
+ ar9287_1_1_rx_gain_vals_2g
+};
+
+#endif /* _ARN9287REG_H_ */
diff --git a/sys/dev/ic/arn9380.c b/sys/dev/ic/arn9380.c
new file mode 100644
index 00000000000..1c117f6afc8
--- /dev/null
+++ b/sys/dev/ic/arn9380.c
@@ -0,0 +1,917 @@
+/* $NetBSD: arn9380.c,v 1.1 2013/03/30 02:53:02 christos Exp $ */
+/* $OpenBSD: ar9380.c,v 1.17 2012/10/20 09:54:20 stsp Exp $ */
+
+/*-
+ * Copyright (c) 2011 Damien Bergamini <damien.bergamini@free.fr>
+ * Copyright (c) 2010 Atheros Communications Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+/*
+ * Driver for Atheros 802.11a/g/n chipsets.
+ * Routines for AR9380 and AR9485 chipsets.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: arn9380.c,v 1.1 2013/03/30 02:53:02 christos Exp $");
+
+#include <sys/param.h>
+#include <sys/sockio.h>
+#include <sys/mbuf.h>
+#include <sys/kernel.h>
+#include <sys/socket.h>
+#include <sys/systm.h>
+#include <sys/malloc.h>
+#include <sys/queue.h>
+#include <sys/conf.h>
+#include <sys/device.h>
+
+#include <sys/bus.h>
+#include <sys/endian.h>
+
+#include <net/bpf.h>
+#include <net/if.h>
+#include <net/if_arp.h>
+#include <net/if_dl.h>
+#include <net/if_media.h>
+#include <net/if_types.h>
+
+#include <netinet/in.h>
+#include <netinet/in_systm.h>
+#include <netinet/in_var.h>
+
+#include <net80211/ieee80211_var.h>
+#include <net80211/ieee80211_amrr.h>
+#include <net80211/ieee80211_radiotap.h>
+
+#include <dev/ic/athnreg.h>
+#include <dev/ic/athnvar.h>
+
+#include <dev/ic/arn9003reg.h>
+#include <dev/ic/arn9380reg.h>
+
+#include <dev/ic/arn9003.h>
+#include <dev/ic/arn9380.h>
+
+#define Static static
+
+Static void ar9380_get_correction(struct athn_softc *,
+ struct ieee80211_channel *, int, int *, int *);
+Static void ar9380_get_paprd_masks(struct athn_softc *,
+ struct ieee80211_channel *, uint32_t *, uint32_t *);
+Static const uint8_t *
+ ar9380_get_rom_template(struct athn_softc *, uint8_t);
+Static void ar9380_init_from_rom(struct athn_softc *,
+ struct ieee80211_channel *, struct ieee80211_channel *);
+Static void ar9380_set_correction(struct athn_softc *,
+ struct ieee80211_channel *);
+Static int ar9380_set_synth(struct athn_softc *,
+ struct ieee80211_channel *, struct ieee80211_channel *);
+Static void ar9380_set_txpower(struct athn_softc *,
+ struct ieee80211_channel *, struct ieee80211_channel *);
+Static void ar9380_setup(struct athn_softc *);
+Static void ar9380_spur_mitigate(struct athn_softc *,
+ struct ieee80211_channel *, struct ieee80211_channel *);
+Static void ar9380_spur_mitigate_cck(struct athn_softc *,
+ struct ieee80211_channel *, struct ieee80211_channel *);
+Static void ar9380_spur_mitigate_ofdm(struct athn_softc *,
+ struct ieee80211_channel *, struct ieee80211_channel *);
+Static void ar9380_swap_rom(struct athn_softc *);
+
+Static void ar9485_init_swreg(struct athn_softc *);
+#define ar9485_pmu_read AR_READ
+Static int ar9485_pmu_write(struct athn_softc *, uint32_t, uint32_t);
+
+#ifdef notused
+Static void ar9380_init_swreg(struct athn_softc *);
+#endif /* notused */
+
+PUBLIC int
+ar9380_attach(struct athn_softc *sc)
+{
+
+ sc->sc_ngpiopins = 17;
+ sc->sc_ops.setup = ar9380_setup;
+ sc->sc_ops.get_rom_template = ar9380_get_rom_template;
+ sc->sc_ops.swap_rom = ar9380_swap_rom;
+ sc->sc_ops.init_from_rom = ar9380_init_from_rom;
+ sc->sc_ops.set_txpower = ar9380_set_txpower;
+ sc->sc_ops.set_synth = ar9380_set_synth;
+ sc->sc_ops.spur_mitigate = ar9380_spur_mitigate;
+ sc->sc_ops.get_paprd_masks = ar9380_get_paprd_masks;
+ sc->sc_cca_min_2g = AR9380_PHY_CCA_MIN_GOOD_VAL_2GHZ;
+ sc->sc_cca_max_2g = AR9380_PHY_CCA_MAX_GOOD_VAL_2GHZ;
+ sc->sc_cca_min_5g = AR9380_PHY_CCA_MIN_GOOD_VAL_5GHZ;
+ sc->sc_cca_max_5g = AR9380_PHY_CCA_MAX_GOOD_VAL_5GHZ;
+ if (AR_SREV_9485(sc)) {
+ sc->sc_ini = &ar9485_1_1_ini;
+ sc->sc_serdes = &ar9485_1_1_serdes;
+ }
+ else {
+ sc->sc_ini = &ar9380_2_2_ini;
+ sc->sc_serdes = &ar9380_2_2_serdes;
+ }
+
+ return ar9003_attach(sc);
+}
+
+Static void
+ar9380_setup(struct athn_softc *sc)
+{
+ struct ieee80211com *ic = &sc->sc_ic;
+ struct ar9380_eeprom *eep = sc->sc_eep;
+ struct ar9380_base_eep_hdr *base = &eep->baseEepHeader;
+ uint8_t type;
+
+ if (base->opFlags & AR_OPFLAGS_11A)
+ sc->sc_flags |= ATHN_FLAG_11A;
+ if (base->opFlags & AR_OPFLAGS_11G)
+ sc->sc_flags |= ATHN_FLAG_11G;
+ if (base->opFlags & AR_OPFLAGS_11N)
+ sc->sc_flags |= ATHN_FLAG_11N;
+
+ IEEE80211_ADDR_COPY(ic->ic_myaddr, eep->macAddr);
+ sc->sc_led_pin = base->wlanLedGpio;
+
+ /* Check if we have a hardware radio switch. */
+ if (base->rfSilent & AR_EEP_RFSILENT_ENABLED) {
+ sc->sc_flags |= ATHN_FLAG_RFSILENT;
+ /* Get GPIO pin used by hardware radio switch. */
+ sc->sc_rfsilent_pin = MS(base->rfSilent,
+ AR_EEP_RFSILENT_GPIO_SEL);
+ /* Get polarity of hardware radio switch. */
+ if (base->rfSilent & AR_EEP_RFSILENT_POLARITY)
+ sc->sc_flags |= ATHN_FLAG_RFSILENT_REVERSED;
+ }
+
+ /* Set the number of HW key cache entries. */
+ sc->sc_kc_entries = AR_KEYTABLE_SIZE;
+
+ sc->sc_txchainmask = MS(base->txrxMask, AR_EEP_TX_MASK);
+ sc->sc_rxchainmask = MS(base->txrxMask, AR_EEP_RX_MASK);
+
+ /* Fast PLL clock is always supported. */
+ sc->sc_flags |= ATHN_FLAG_FAST_PLL_CLOCK;
+
+ /* Enable PA predistortion if supported. */
+ if (base->featureEnable & AR_EEP_PAPRD)
+ sc->sc_flags |= ATHN_FLAG_PAPRD;
+ /*
+ * Some 3-stream chips may exceed the PCIe power requirements,
+ * requiring to reduce the number of Tx chains in some cases.
+ */
+ if ((base->miscConfiguration & AR_EEP_CHAIN_MASK_REDUCE) &&
+ sc->sc_txchainmask == 0x7)
+ sc->sc_flags |= ATHN_FLAG_3TREDUCE_CHAIN;
+
+ /* Select initialization values based on ROM. */
+ type = MS(eep->baseEepHeader.txrxgain, AR_EEP_RX_GAIN);
+ if (!AR_SREV_9485(sc)) {
+ if (type == AR_EEP_RX_GAIN_WO_XLNA)
+ sc->sc_rx_gain = &ar9380_2_2_rx_gain_wo_xlna;
+ else
+ sc->sc_rx_gain = &ar9380_2_2_rx_gain;
+ }
+ else
+ sc->sc_rx_gain = &ar9485_1_1_rx_gain;
+
+ /* Select initialization values based on ROM. */
+ type = MS(eep->baseEepHeader.txrxgain, AR_EEP_TX_GAIN);
+ if (!AR_SREV_9485(sc)) {
+ if (type == AR_EEP_TX_GAIN_HIGH_OB_DB)
+ sc->sc_tx_gain = &ar9380_2_2_tx_gain_high_ob_db;
+ else if (type == AR_EEP_TX_GAIN_LOW_OB_DB)
+ sc->sc_tx_gain = &ar9380_2_2_tx_gain_low_ob_db;
+ else if (type == AR_EEP_TX_GAIN_HIGH_POWER)
+ sc->sc_tx_gain = &ar9380_2_2_tx_gain_high_power;
+ else
+ sc->sc_tx_gain = &ar9380_2_2_tx_gain;
+ }
+ else
+ sc->sc_tx_gain = &ar9485_1_1_tx_gain;
+}
+
+Static const uint8_t *
+ar9380_get_rom_template(struct athn_softc *sc, uint8_t ref)
+{
+ size_t i;
+
+ /* Retrieve template ROM image for given reference. */
+ for (i = 0; i < __arraycount(ar9380_rom_templates); i++)
+ if (ar9380_rom_templates[i][1] == ref)
+ return ar9380_rom_templates[i];
+ return NULL;
+}
+
+Static void
+ar9380_swap_rom(struct athn_softc *sc)
+{
+#if BYTE_ORDER == BIG_ENDIAN
+ struct ar9380_eeprom *eep = sc->sc_eep;
+ struct ar9380_base_eep_hdr *base = &eep->baseEepHeader;
+ struct ar9380_modal_eep_header *modal;
+ int i;
+
+ base->regDmn[0] = swap16(base->regDmn[0]);
+ base->regDmn[1] = swap16(base->regDmn[1]);
+ base->swreg = swap32(base->swreg);
+
+ modal = &eep->modalHeader2G;
+ modal->antCtrlCommon = swap32(modal->antCtrlCommon);
+ modal->antCtrlCommon2 = swap32(modal->antCtrlCommon2);
+ modal->papdRateMaskHt20 = swap32(modal->papdRateMaskHt20);
+ modal->papdRateMaskHt40 = swap32(modal->papdRateMaskHt40);
+ for (i = 0; i < AR9380_MAX_CHAINS; i++)
+ modal->antCtrlChain[i] = swap16(modal->antCtrlChain[i]);
+
+ modal = &eep->modalHeader5G;
+ modal->antCtrlCommon = swap32(modal->antCtrlCommon);
+ modal->antCtrlCommon2 = swap32(modal->antCtrlCommon2);
+ modal->papdRateMaskHt20 = swap32(modal->papdRateMaskHt20);
+ modal->papdRateMaskHt40 = swap32(modal->papdRateMaskHt40);
+ for (i = 0; i < AR9380_MAX_CHAINS; i++)
+ modal->antCtrlChain[i] = swap16(modal->antCtrlChain[i]);
+#endif
+}
+
+Static void
+ar9380_get_paprd_masks(struct athn_softc *sc, struct ieee80211_channel *c,
+ uint32_t *ht20mask, uint32_t *ht40mask)
+{
+ const struct ar9380_eeprom *eep = sc->sc_eep;
+ const struct ar9380_modal_eep_header *modal;
+
+ if (IEEE80211_IS_CHAN_2GHZ(c))
+ modal = &eep->modalHeader2G;
+ else
+ modal = &eep->modalHeader5G;
+ *ht20mask = modal->papdRateMaskHt20;
+ *ht40mask = modal->papdRateMaskHt40;
+}
+
+Static int
+ar9380_set_synth(struct athn_softc *sc, struct ieee80211_channel *c,
+ struct ieee80211_channel *extc)
+{
+ uint32_t freq = c->ic_freq;
+ uint32_t chansel, phy;
+
+ if (IEEE80211_IS_CHAN_2GHZ(c)) {
+ if (AR_SREV_9485(sc))
+ chansel = ((freq << 16) - 215) / 15;
+ else
+ chansel = (freq << 16) / 15;
+ AR_WRITE(sc, AR_PHY_SYNTH_CONTROL, AR9380_BMODE);
+ }
+ else {
+ chansel = (freq << 15) / 15;
+ chansel >>= 1;
+ AR_WRITE(sc, AR_PHY_SYNTH_CONTROL, 0);
+ }
+
+ /* Enable Long Shift Select for synthesizer. */
+ AR_SETBITS(sc, AR_PHY_65NM_CH0_SYNTH4,
+ AR_PHY_SYNTH4_LONG_SHIFT_SELECT);
+ AR_WRITE_BARRIER(sc);
+
+ /* Program synthesizer. */
+ phy = (chansel << 2) | AR9380_FRACMODE;
+ DPRINTFN(DBG_RF, sc, "AR_PHY_65NM_CH0_SYNTH7=0x%08x\n", phy);
+ AR_WRITE(sc, AR_PHY_65NM_CH0_SYNTH7, phy);
+ AR_WRITE_BARRIER(sc);
+ /* Toggle Load Synth Channel bit. */
+ AR_WRITE(sc, AR_PHY_65NM_CH0_SYNTH7, phy | AR9380_LOAD_SYNTH);
+ AR_WRITE_BARRIER(sc);
+ return 0;
+}
+
+Static void
+ar9380_init_from_rom(struct athn_softc *sc, struct ieee80211_channel *c,
+ struct ieee80211_channel *extc)
+{
+ const struct ar9380_eeprom *eep = sc->sc_eep;
+ const struct ar9380_modal_eep_header *modal;
+ uint8_t db, margin, ant_div_ctrl;
+ uint32_t reg;
+ int i, maxchains;
+
+ if (IEEE80211_IS_CHAN_2GHZ(c))
+ modal = &eep->modalHeader2G;
+ else
+ modal = &eep->modalHeader5G;
+
+ /* Apply XPA bias level. */
+ if (AR_SREV_9485(sc)) {
+ reg = AR_READ(sc, AR9485_PHY_65NM_CH0_TOP2);
+ reg = RW(reg, AR9485_PHY_65NM_CH0_TOP2_XPABIASLVL,
+ modal->xpaBiasLvl);
+ AR_WRITE(sc, AR9485_PHY_65NM_CH0_TOP2, reg);
+ }
+ else {
+ reg = AR_READ(sc, AR_PHY_65NM_CH0_TOP);
+ reg = RW(reg, AR_PHY_65NM_CH0_TOP_XPABIASLVL,
+ modal->xpaBiasLvl & 0x3);
+ AR_WRITE(sc, AR_PHY_65NM_CH0_TOP, reg);
+ reg = AR_READ(sc, AR_PHY_65NM_CH0_THERM);
+ reg = RW(reg, AR_PHY_65NM_CH0_THERM_XPABIASLVL_MSB,
+ modal->xpaBiasLvl >> 2);
+ reg |= AR_PHY_65NM_CH0_THERM_XPASHORT2GND;
+ AR_WRITE(sc, AR_PHY_65NM_CH0_THERM, reg);
+ }
+
+ /* Apply antenna control. */
+ reg = AR_READ(sc, AR_PHY_SWITCH_COM);
+ reg = RW(reg, AR_SWITCH_TABLE_COM_ALL, modal->antCtrlCommon);
+ AR_WRITE(sc, AR_PHY_SWITCH_COM, reg);
+ reg = AR_READ(sc, AR_PHY_SWITCH_COM_2);
+ reg = RW(reg, AR_SWITCH_TABLE_COM_2_ALL, modal->antCtrlCommon2);
+ AR_WRITE(sc, AR_PHY_SWITCH_COM_2, reg);
+
+ maxchains = AR_SREV_9485(sc) ? 1 : AR9380_MAX_CHAINS;
+ for (i = 0; i < maxchains; i++) {
+ reg = AR_READ(sc, AR_PHY_SWITCH_CHAIN(i));
+ reg = RW(reg, AR_SWITCH_TABLE_ALL, modal->antCtrlChain[i]);
+ AR_WRITE(sc, AR_PHY_SWITCH_CHAIN(i), reg);
+ }
+
+ if (AR_SREV_9485(sc)) {
+ ant_div_ctrl = eep->base_ext1.ant_div_control;
+ reg = AR_READ(sc, AR_PHY_MC_GAIN_CTRL);
+ reg = RW(reg, AR_PHY_MC_GAIN_CTRL_ANT_DIV_CTRL_ALL,
+ MS(ant_div_ctrl, AR_EEP_ANT_DIV_CTRL_ALL));
+ if (ant_div_ctrl & AR_EEP_ANT_DIV_CTRL_ANT_DIV)
+ reg |= AR_PHY_MC_GAIN_CTRL_ENABLE_ANT_DIV;
+ else
+ reg &= ~AR_PHY_MC_GAIN_CTRL_ENABLE_ANT_DIV;
+ AR_WRITE(sc, AR_PHY_MC_GAIN_CTRL, reg);
+ reg = AR_READ(sc, AR_PHY_CCK_DETECT);
+ if (ant_div_ctrl & AR_EEP_ANT_DIV_CTRL_FAST_DIV)
+ reg |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
+ else
+ reg &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
+ AR_WRITE(sc, AR_PHY_CCK_DETECT, reg);
+ }
+
+ if (eep->baseEepHeader.miscConfiguration & AR_EEP_DRIVE_STRENGTH) {
+ /* Apply drive strength. */
+ reg = AR_READ(sc, AR_PHY_65NM_CH0_BIAS1);
+ reg = RW(reg, AR_PHY_65NM_CH0_BIAS1_0, 5);
+ reg = RW(reg, AR_PHY_65NM_CH0_BIAS1_1, 5);
+ reg = RW(reg, AR_PHY_65NM_CH0_BIAS1_2, 5);
+ reg = RW(reg, AR_PHY_65NM_CH0_BIAS1_3, 5);
+ reg = RW(reg, AR_PHY_65NM_CH0_BIAS1_4, 5);
+ reg = RW(reg, AR_PHY_65NM_CH0_BIAS1_5, 5);
+ AR_WRITE(sc, AR_PHY_65NM_CH0_BIAS1, reg);
+
+ reg = AR_READ(sc, AR_PHY_65NM_CH0_BIAS2);
+ reg = RW(reg, AR_PHY_65NM_CH0_BIAS2_0, 5);
+ reg = RW(reg, AR_PHY_65NM_CH0_BIAS2_1, 5);
+ reg = RW(reg, AR_PHY_65NM_CH0_BIAS2_2, 5);
+ reg = RW(reg, AR_PHY_65NM_CH0_BIAS2_3, 5);
+ reg = RW(reg, AR_PHY_65NM_CH0_BIAS2_4, 5);
+ reg = RW(reg, AR_PHY_65NM_CH0_BIAS2_5, 5);
+ reg = RW(reg, AR_PHY_65NM_CH0_BIAS2_6, 5);
+ reg = RW(reg, AR_PHY_65NM_CH0_BIAS2_7, 5);
+ reg = RW(reg, AR_PHY_65NM_CH0_BIAS2_8, 5);
+ AR_WRITE(sc, AR_PHY_65NM_CH0_BIAS2, reg);
+
+ reg = AR_READ(sc, AR_PHY_65NM_CH0_BIAS4);
+ reg = RW(reg, AR_PHY_65NM_CH0_BIAS4_0, 5);
+ reg = RW(reg, AR_PHY_65NM_CH0_BIAS4_1, 5);
+ reg = RW(reg, AR_PHY_65NM_CH0_BIAS4_2, 5);
+ AR_WRITE(sc, AR_PHY_65NM_CH0_BIAS4, reg);
+ }
+
+ /* Apply attenuation settings. */
+ maxchains = AR_SREV_9485(sc) ? 1 : AR9380_MAX_CHAINS;
+ for (i = 0; i < maxchains; i++) {
+ if (IEEE80211_IS_CHAN_5GHZ(c) &&
+ eep->base_ext2.xatten1DBLow[i] != 0) {
+ if (c->ic_freq <= 5500) {
+ db = athn_interpolate(c->ic_freq,
+ 5180, eep->base_ext2.xatten1DBLow[i],
+ 5500, modal->xatten1DB[i]);
+ }
+ else {
+ db = athn_interpolate(c->ic_freq,
+ 5500, modal->xatten1DB[i],
+ 5785, eep->base_ext2.xatten1DBHigh[i]);
+ }
+ }
+ else
+ db = modal->xatten1DB[i];
+ if (IEEE80211_IS_CHAN_5GHZ(c) &&
+ eep->base_ext2.xatten1MarginLow[i] != 0) {
+ if (c->ic_freq <= 5500) {
+ margin = athn_interpolate(c->ic_freq,
+ 5180, eep->base_ext2.xatten1MarginLow[i],
+ 5500, modal->xatten1Margin[i]);
+ }
+ else {
+ margin = athn_interpolate(c->ic_freq,
+ 5500, modal->xatten1Margin[i],
+ 5785, eep->base_ext2.xatten1MarginHigh[i]);
+ }
+ }
+ else
+ margin = modal->xatten1Margin[i];
+ reg = AR_READ(sc, AR_PHY_EXT_ATTEN_CTL(i));
+ reg = RW(reg, AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB, db);
+ reg = RW(reg, AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN, margin);
+ AR_WRITE(sc, AR_PHY_EXT_ATTEN_CTL(i), reg);
+ }
+
+ /* Initialize switching regulator. */
+ if (AR_SREV_9485(sc))
+ ar9485_init_swreg(sc);
+ else
+ ar9485_init_swreg(sc);
+
+ /* Apply tuning capabilities. */
+ if (AR_SREV_9485(sc) &&
+ (eep->baseEepHeader.featureEnable & AR_EEP_TUNING_CAPS)) {
+ reg = AR_READ(sc, AR9485_PHY_CH0_XTAL);
+ reg = RW(reg, AR9485_PHY_CH0_XTAL_CAPINDAC,
+ eep->baseEepHeader.params_for_tuning_caps[0]);
+ reg = RW(reg, AR9485_PHY_CH0_XTAL_CAPOUTDAC,
+ eep->baseEepHeader.params_for_tuning_caps[0]);
+ AR_WRITE(sc, AR9485_PHY_CH0_XTAL, reg);
+ }
+ AR_WRITE_BARRIER(sc);
+}
+
+#ifdef notused
+Static void
+ar9380_init_swreg(struct athn_softc *sc)
+{
+ const struct ar9380_eeprom *eep = sc->sc_eep;
+
+ if (eep->baseEepHeader.featureEnable & AR_EEP_INTERNAL_REGULATOR) {
+ /* Internal regulator is ON. */
+ AR_CLRBITS(sc, AR_RTC_REG_CONTROL1,
+ AR_RTC_REG_CONTROL1_SWREG_PROGRAM);
+ AR_WRITE(sc, AR_RTC_REG_CONTROL0, eep->baseEepHeader.swreg);
+ AR_SETBITS(sc, AR_RTC_REG_CONTROL1,
+ AR_RTC_REG_CONTROL1_SWREG_PROGRAM);
+ }
+ else
+ AR_SETBITS(sc, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_SWREG_PRD);
+ AR_WRITE_BARRIER(sc);
+}
+#endif /* notused */
+
+Static int
+ar9485_pmu_write(struct athn_softc *sc, uint32_t addr, uint32_t val)
+{
+ int ntries;
+
+ AR_WRITE(sc, addr, val);
+ /* Wait for write to complete. */
+ for (ntries = 0; ntries < 100; ntries++) {
+ if (AR_READ(sc, addr) == val)
+ return 0;
+ AR_WRITE(sc, addr, val); /* Insist. */
+ AR_WRITE_BARRIER(sc);
+ DELAY(10);
+ }
+ return ETIMEDOUT;
+}
+
+Static void
+ar9485_init_swreg(struct athn_softc *sc)
+{
+ const struct ar9380_eeprom *eep = sc->sc_eep;
+ uint32_t reg;
+
+ ar9485_pmu_write(sc, AR_PHY_PMU2,
+ ar9485_pmu_read(sc, AR_PHY_PMU2) & ~AR_PHY_PMU2_PGM);
+
+ if (eep->baseEepHeader.featureEnable & AR_EEP_INTERNAL_REGULATOR) {
+ ar9485_pmu_write(sc, AR_PHY_PMU1, 0x131dc17a);
+
+ reg = ar9485_pmu_read(sc, AR_PHY_PMU2);
+ reg = (reg & ~0xffc00000) | 0x10000000;
+ ar9485_pmu_write(sc, AR_PHY_PMU2, reg);
+ }
+ else {
+ ar9485_pmu_write(sc, AR_PHY_PMU1,
+ ar9485_pmu_read(sc, AR_PHY_PMU1) | AR_PHY_PMU1_PWD);
+ }
+
+ ar9485_pmu_write(sc, AR_PHY_PMU2,
+ ar9485_pmu_read(sc, AR_PHY_PMU2) | AR_PHY_PMU2_PGM);
+}
+
+/*
+ * NB: It is safe to call this function for 5GHz channels.
+ */
+Static void
+ar9380_spur_mitigate_cck(struct athn_softc *sc, struct ieee80211_channel *c,
+ struct ieee80211_channel *extc)
+{
+ static const int16_t freqs[] = { 2420, 2440, 2464, 2480 };
+ size_t i;
+ int spur, freq;
+ uint32_t reg;
+
+ for (i = 0; i < __arraycount(freqs); i++) {
+ spur = freqs[i] - c->ic_freq;
+ if (abs(spur) < 10) /* +/- 10MHz range. */
+ break;
+ }
+ if (i == __arraycount(freqs)) {
+ /* Disable CCK spur mitigation. */
+ reg = AR_READ(sc, AR_PHY_AGC_CONTROL);
+ reg = RW(reg, AR_PHY_AGC_CONTROL_YCOK_MAX, 0x5);
+ AR_WRITE(sc, AR_PHY_AGC_CONTROL, reg);
+ reg = AR_READ(sc, AR_PHY_CCK_SPUR_MIT);
+ reg = RW(reg, AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, 0);
+ reg &= ~AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT;
+ AR_WRITE(sc, AR_PHY_CCK_SPUR_MIT, reg);
+ AR_WRITE_BARRIER(sc);
+ return;
+ }
+ freq = (spur * 524288) / 11;
+
+ reg = AR_READ(sc, AR_PHY_AGC_CONTROL);
+ reg = RW(reg, AR_PHY_AGC_CONTROL_YCOK_MAX, 0x7);
+ AR_WRITE(sc, AR_PHY_AGC_CONTROL, reg);
+
+ reg = AR_READ(sc, AR_PHY_CCK_SPUR_MIT);
+ reg = RW(reg, AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, freq);
+ reg = RW(reg, AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR, 0x7f);
+ reg = RW(reg, AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE, 0x2);
+ reg |= AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT;
+ AR_WRITE(sc, AR_PHY_CCK_SPUR_MIT, reg);
+ AR_WRITE_BARRIER(sc);
+}
+
+Static void
+ar9380_spur_mitigate_ofdm(struct athn_softc *sc, struct ieee80211_channel *c,
+ struct ieee80211_channel *extc)
+{
+ const struct ar9380_eeprom *eep = sc->sc_eep;
+ const uint8_t *spurchans;
+ uint32_t reg;
+ int idx, spur_delta_phase, spur_off, range, i;
+ int freq, spur, spur_freq_sd, spur_subchannel_sd;
+
+ if (IEEE80211_IS_CHAN_2GHZ(c))
+ spurchans = eep->modalHeader2G.spurChans;
+ else
+ spurchans = eep->modalHeader5G.spurChans;
+ if (spurchans[0] == 0)
+ return;
+
+ /* Disable OFDM spur mitigation. */
+ AR_CLRBITS(sc, AR_PHY_TIMING4, AR_PHY_TIMING4_ENABLE_SPUR_FILTER);
+
+ reg = AR_READ(sc, AR_PHY_TIMING11);
+ reg = RW(reg, AR_PHY_TIMING11_SPUR_FREQ_SD, 0);
+ reg = RW(reg, AR_PHY_TIMING11_SPUR_DELTA_PHASE, 0);
+ reg &= ~AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC;
+ reg &= ~AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR;
+ AR_WRITE(sc, AR_PHY_TIMING11, reg);
+
+ AR_CLRBITS(sc, AR_PHY_SFCORR_EXT,
+ AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD);
+
+ AR_CLRBITS(sc, AR_PHY_TIMING4, AR_PHY_TIMING4_ENABLE_SPUR_RSSI);
+
+ reg = AR_READ(sc, AR_PHY_SPUR_REG);
+ reg = RW(reg, AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0);
+ reg &= ~AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI;
+ reg &= ~AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT;
+ reg &= ~AR_PHY_SPUR_REG_ENABLE_MASK_PPM;
+ AR_WRITE(sc, AR_PHY_SPUR_REG, reg);
+ AR_WRITE_BARRIER(sc);
+
+ freq = c->ic_freq;
+#ifndef IEEE80211_NO_HT
+ if (extc != NULL) {
+ range = 19; /* +/- 19MHz range. */
+ if (AR_READ(sc, AR_PHY_GEN_CTRL) & AR_PHY_GC_DYN2040_PRI_CH)
+ freq += 10;
+ else
+ freq -= 10;
+ }
+ else
+#endif
+ range = 10; /* +/- 10MHz range. */
+ for (i = 0; i < AR9380_EEPROM_MODAL_SPURS; i++) {
+ spur = spurchans[i];
+ if (spur == 0)
+ return;
+ /* Convert to frequency. */
+ if (IEEE80211_IS_CHAN_2GHZ(c))
+ spur = 2300 + spur;
+ else
+ spur = 4900 + (spur * 5);
+ spur -= freq;
+ if (abs(spur) < range)
+ break;
+ }
+ if (i == AR9380_EEPROM_MODAL_SPURS)
+ return;
+
+ /* Enable OFDM spur mitigation. */
+#ifndef IEEE80211_NO_HT
+ if (extc != NULL) {
+ spur_delta_phase = (spur * 131072) / 5;
+ reg = AR_READ(sc, AR_PHY_GEN_CTRL);
+ if (spur < 0) {
+ spur_subchannel_sd =
+ (reg & AR_PHY_GC_DYN2040_PRI_CH) == 0;
+ spur_off = spur + 10;
+ }
+ else {
+ spur_subchannel_sd =
+ (reg & AR_PHY_GC_DYN2040_PRI_CH) != 0;
+ spur_off = spur - 10;
+ }
+ }
+ else
+#endif
+ {
+ spur_delta_phase = (spur * 262144) / 5;
+ spur_subchannel_sd = 0;
+ spur_off = spur;
+ }
+ spur_freq_sd = (spur_off * 512) / 11;
+
+ AR_SETBITS(sc, AR_PHY_TIMING4, AR_PHY_TIMING4_ENABLE_SPUR_FILTER);
+
+ reg = AR_READ(sc, AR_PHY_TIMING11);
+ reg = RW(reg, AR_PHY_TIMING11_SPUR_FREQ_SD, spur_freq_sd);
+ reg = RW(reg, AR_PHY_TIMING11_SPUR_DELTA_PHASE, spur_delta_phase);
+ reg |= AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC;
+ reg |= AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR;
+ AR_WRITE(sc, AR_PHY_TIMING11, reg);
+
+ reg = AR_READ(sc, AR_PHY_SFCORR_EXT);
+ if (spur_subchannel_sd)
+ reg |= AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD;
+ else
+ reg &= ~AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD;
+ AR_WRITE(sc, AR_PHY_SFCORR_EXT, reg);
+
+ AR_SETBITS(sc, AR_PHY_TIMING4, AR_PHY_TIMING4_ENABLE_SPUR_RSSI);
+
+ reg = AR_READ(sc, AR_PHY_SPUR_REG);
+ reg = RW(reg, AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0xff);
+ reg = RW(reg, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, 34);
+ reg |= AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI;
+ if (AR_READ(sc, AR_PHY_MODE) & AR_PHY_MODE_DYNAMIC)
+ reg |= AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT;
+ reg |= AR_PHY_SPUR_REG_ENABLE_MASK_PPM;
+ AR_WRITE(sc, AR_PHY_SPUR_REG, reg);
+
+ idx = (spur * 16) / 5;
+ if (idx < 0)
+ idx--;
+
+ /* Write pilot mask. */
+ AR_SETBITS(sc, AR_PHY_TIMING4,
+ AR_PHY_TIMING4_ENABLE_PILOT_MASK |
+ AR_PHY_TIMING4_ENABLE_CHAN_MASK);
+
+ reg = AR_READ(sc, AR_PHY_PILOT_SPUR_MASK);
+ reg = RW(reg, AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, idx);
+ reg = RW(reg, AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0x0c);
+ AR_WRITE(sc, AR_PHY_PILOT_SPUR_MASK, reg);
+
+ reg = AR_READ(sc, AR_PHY_SPUR_MASK_A);
+ reg = RW(reg, AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, idx);
+ reg = RW(reg, AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0);
+ AR_WRITE(sc, AR_PHY_SPUR_MASK_A, reg);
+
+ reg = AR_READ(sc, AR_PHY_CHAN_SPUR_MASK);
+ reg = RW(reg, AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, idx);
+ reg = RW(reg, AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0x0c);
+ AR_WRITE(sc, AR_PHY_CHAN_SPUR_MASK, reg);
+ AR_WRITE_BARRIER(sc);
+}
+
+Static void
+ar9380_spur_mitigate(struct athn_softc *sc, struct ieee80211_channel *c,
+ struct ieee80211_channel *extc)
+{
+
+ /* NB: We call spur_mitigate_cck for 5GHz too, just to disable it. */
+ ar9380_spur_mitigate_cck(sc, c, extc);
+ ar9380_spur_mitigate_ofdm(sc, c, extc);
+}
+
+Static void
+ar9380_set_txpower(struct athn_softc *sc, struct ieee80211_channel *c,
+ struct ieee80211_channel *extc)
+{
+ const struct ar9380_eeprom *eep = sc->sc_eep;
+ uint8_t tpow_cck[4], tpow_ofdm[4];
+ uint8_t tpow_ht20[14], tpow_ht40[14];
+ int16_t power[ATHN_POWER_COUNT];
+
+ if (IEEE80211_IS_CHAN_2GHZ(c)) {
+ /* Get CCK target powers. */
+ ar9003_get_lg_tpow(sc, c, AR_CTL_11B,
+ eep->calTargetFbinCck, eep->calTargetPowerCck,
+ AR9380_NUM_2G_CCK_TARGET_POWERS, tpow_cck);
+
+ /* Get OFDM target powers. */
+ ar9003_get_lg_tpow(sc, c, AR_CTL_11G,
+ eep->calTargetFbin2G, eep->calTargetPower2G,
+ AR9380_NUM_2G_20_TARGET_POWERS, tpow_ofdm);
+
+ /* Get HT-20 target powers. */
+ ar9003_get_ht_tpow(sc, c, AR_CTL_2GHT20,
+ eep->calTargetFbin2GHT20, eep->calTargetPower2GHT20,
+ AR9380_NUM_2G_20_TARGET_POWERS, tpow_ht20);
+
+ if (extc != NULL) {
+ /* Get HT-40 target powers. */
+ ar9003_get_ht_tpow(sc, c, AR_CTL_2GHT40,
+ eep->calTargetFbin2GHT40,
+ eep->calTargetPower2GHT40,
+ AR9380_NUM_2G_40_TARGET_POWERS, tpow_ht40);
+ }
+ }
+ else {
+ /* Get OFDM target powers. */
+ ar9003_get_lg_tpow(sc, c, AR_CTL_11A,
+ eep->calTargetFbin5G, eep->calTargetPower5G,
+ AR9380_NUM_5G_20_TARGET_POWERS, tpow_ofdm);
+
+ /* Get HT-20 target powers. */
+ ar9003_get_ht_tpow(sc, c, AR_CTL_5GHT20,
+ eep->calTargetFbin5GHT20, eep->calTargetPower5GHT20,
+ AR9380_NUM_5G_20_TARGET_POWERS, tpow_ht20);
+
+ if (extc != NULL) {
+ /* Get HT-40 target powers. */
+ ar9003_get_ht_tpow(sc, c, AR_CTL_5GHT40,
+ eep->calTargetFbin5GHT40,
+ eep->calTargetPower5GHT40,
+ AR9380_NUM_5G_40_TARGET_POWERS, tpow_ht40);
+ }
+ }
+
+ memset(power, 0, sizeof(power));
+ /* Shuffle target powers accross transmit rates. */
+ power[ATHN_POWER_OFDM6 ] =
+ power[ATHN_POWER_OFDM9 ] =
+ power[ATHN_POWER_OFDM12] =
+ power[ATHN_POWER_OFDM18] =
+ power[ATHN_POWER_OFDM24] = tpow_ofdm[0];
+ power[ATHN_POWER_OFDM36] = tpow_ofdm[1];
+ power[ATHN_POWER_OFDM48] = tpow_ofdm[2];
+ power[ATHN_POWER_OFDM54] = tpow_ofdm[3];
+ if (IEEE80211_IS_CHAN_2GHZ(c)) {
+ power[ATHN_POWER_CCK1_LP ] =
+ power[ATHN_POWER_CCK2_LP ] =
+ power[ATHN_POWER_CCK2_SP ] =
+ power[ATHN_POWER_CCK55_LP] = tpow_cck[0];
+ power[ATHN_POWER_CCK55_SP] = tpow_cck[1];
+ power[ATHN_POWER_CCK11_LP] = tpow_cck[2];
+ power[ATHN_POWER_CCK11_SP] = tpow_cck[3];
+ }
+ /* Next entry covers MCS0, MCS8 and MCS16. */
+ power[ATHN_POWER_HT20( 0)] = tpow_ht20[ 0];
+ /* Next entry covers MCS1-3, MCS9-11 and MCS17-19. */
+ power[ATHN_POWER_HT20( 1)] = tpow_ht20[ 1];
+ power[ATHN_POWER_HT20( 4)] = tpow_ht20[ 2];
+ power[ATHN_POWER_HT20( 5)] = tpow_ht20[ 3];
+ power[ATHN_POWER_HT20( 6)] = tpow_ht20[ 4];
+ power[ATHN_POWER_HT20( 7)] = tpow_ht20[ 5];
+ power[ATHN_POWER_HT20(12)] = tpow_ht20[ 6];
+ power[ATHN_POWER_HT20(13)] = tpow_ht20[ 7];
+ power[ATHN_POWER_HT20(14)] = tpow_ht20[ 8];
+ power[ATHN_POWER_HT20(15)] = tpow_ht20[ 9];
+ power[ATHN_POWER_HT20(20)] = tpow_ht20[10];
+ power[ATHN_POWER_HT20(21)] = tpow_ht20[11];
+ power[ATHN_POWER_HT20(22)] = tpow_ht20[12];
+ power[ATHN_POWER_HT20(23)] = tpow_ht20[13];
+ if (extc != NULL) {
+ /* Next entry covers MCS0, MCS8 and MCS16. */
+ power[ATHN_POWER_HT40( 0)] = tpow_ht40[ 0];
+ /* Next entry covers MCS1-3, MCS9-11 and MCS17-19. */
+ power[ATHN_POWER_HT40( 1)] = tpow_ht40[ 1];
+ power[ATHN_POWER_HT40( 4)] = tpow_ht40[ 2];
+ power[ATHN_POWER_HT40( 5)] = tpow_ht40[ 3];
+ power[ATHN_POWER_HT40( 6)] = tpow_ht40[ 4];
+ power[ATHN_POWER_HT40( 7)] = tpow_ht40[ 5];
+ power[ATHN_POWER_HT40(12)] = tpow_ht40[ 6];
+ power[ATHN_POWER_HT40(13)] = tpow_ht40[ 7];
+ power[ATHN_POWER_HT40(14)] = tpow_ht40[ 8];
+ power[ATHN_POWER_HT40(15)] = tpow_ht40[ 9];
+ power[ATHN_POWER_HT40(20)] = tpow_ht40[10];
+ power[ATHN_POWER_HT40(21)] = tpow_ht40[11];
+ power[ATHN_POWER_HT40(22)] = tpow_ht40[12];
+ power[ATHN_POWER_HT40(23)] = tpow_ht40[13];
+ }
+
+ /* Write transmit power values to hardware. */
+ ar9003_write_txpower(sc, power);
+
+ /* Apply transmit power correction. */
+ ar9380_set_correction(sc, c);
+}
+
+Static void
+ar9380_get_correction(struct athn_softc *sc, struct ieee80211_channel *c,
+ int chain, int *corr, int *temp)
+{
+ const struct ar9380_eeprom *eep = sc->sc_eep;
+ const struct ar9380_cal_data_per_freq_op_loop *pierdata;
+ const uint8_t *pierfreq;
+ uint8_t fbin;
+ int lo, hi, npiers;
+
+ if (IEEE80211_IS_CHAN_2GHZ(c)) {
+ pierfreq = eep->calFreqPier2G;
+ pierdata = eep->calPierData2G[chain];
+ npiers = AR9380_NUM_2G_CAL_PIERS;
+ }
+ else {
+ pierfreq = eep->calFreqPier5G;
+ pierdata = eep->calPierData5G[chain];
+ npiers = AR9380_NUM_5G_CAL_PIERS;
+ }
+ /* Find channel in ROM pier table. */
+ fbin = athn_chan2fbin(c);
+ athn_get_pier_ival(fbin, pierfreq, npiers, &lo, &hi);
+
+ *corr = athn_interpolate(fbin,
+ pierfreq[lo], pierdata[lo].refPower,
+ pierfreq[hi], pierdata[hi].refPower);
+ *temp = athn_interpolate(fbin,
+ pierfreq[lo], pierdata[lo].tempMeas,
+ pierfreq[hi], pierdata[hi].tempMeas);
+}
+
+Static void
+ar9380_set_correction(struct athn_softc *sc, struct ieee80211_channel *c)
+{
+ const struct ar9380_eeprom *eep = sc->sc_eep;
+ const struct ar9380_modal_eep_header *modal;
+ uint32_t reg;
+ int8_t slope;
+ int i, corr, temp, temp0;
+
+ if (IEEE80211_IS_CHAN_2GHZ(c))
+ modal = &eep->modalHeader2G;
+ else
+ modal = &eep->modalHeader5G;
+
+ temp0 = 0; /* XXX: gcc */
+ for (i = 0; i < AR9380_MAX_CHAINS; i++) {
+ ar9380_get_correction(sc, c, i, &corr, &temp);
+ if (i == 0)
+ temp0 = temp;
+
+ reg = AR_READ(sc, AR_PHY_TPC_11_B(i));
+ reg = RW(reg, AR_PHY_TPC_11_OLPC_GAIN_DELTA, corr);
+ AR_WRITE(sc, AR_PHY_TPC_11_B(i), reg);
+
+ /* Enable open loop power control. */
+ reg = AR_READ(sc, AR_PHY_TPC_6_B(i));
+ reg = RW(reg, AR_PHY_TPC_6_ERROR_EST_MODE, 3);
+ AR_WRITE(sc, AR_PHY_TPC_6_B(i), reg);
+ }
+
+ /* Enable temperature compensation. */
+ if (IEEE80211_IS_CHAN_5GHZ(c) &&
+ eep->base_ext2.tempSlopeLow != 0) {
+ if (c->ic_freq <= 5500) {
+ slope = athn_interpolate(c->ic_freq,
+ 5180, eep->base_ext2.tempSlopeLow,
+ 5500, modal->tempSlope);
+ }
+ else {
+ slope = athn_interpolate(c->ic_freq,
+ 5500, modal->tempSlope,
+ 5785, eep->base_ext2.tempSlopeHigh);
+ }
+ }
+ else
+ slope = modal->tempSlope;
+
+ reg = AR_READ(sc, AR_PHY_TPC_19);
+ reg = RW(reg, AR_PHY_TPC_19_ALPHA_THERM, slope);
+ AR_WRITE(sc, AR_PHY_TPC_19, reg);
+
+ reg = AR_READ(sc, AR_PHY_TPC_18);
+ reg = RW(reg, AR_PHY_TPC_18_THERM_CAL, temp0);
+ AR_WRITE(sc, AR_PHY_TPC_18, reg);
+ AR_WRITE_BARRIER(sc);
+}
diff --git a/sys/dev/ic/arn9380.h b/sys/dev/ic/arn9380.h
new file mode 100644
index 00000000000..d3d1e9b65d2
--- /dev/null
+++ b/sys/dev/ic/arn9380.h
@@ -0,0 +1,33 @@
+/* $NetBSD: arn9380.h,v 1.1 2013/03/30 02:53:02 christos Exp $ */
+/*
+ * Copyright (c) 2001, 2004 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _IF_ARN9380_H_
+#define _IF_ARN9380_H_
+
+int ar9380_attach(struct athn_softc *);
+
+#endif /* _IF_ARN9380_H_ */
diff --git a/sys/dev/ic/arn9380reg.h b/sys/dev/ic/arn9380reg.h
new file mode 100644
index 00000000000..4d29e1dda7c
--- /dev/null
+++ b/sys/dev/ic/arn9380reg.h
@@ -0,0 +1,1926 @@
+/* $NetBSD: arn9380reg.h,v 1.1 2013/03/30 02:53:02 christos Exp $ */
+/* $OpenBSD: ar9380reg.h,v 1.19 2012/10/20 09:54:20 stsp Exp $ */
+
+/*-
+ * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr>
+ * Copyright (c) 2010 Atheros Communications Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _ARN9380REG_H_
+#define _ARN9380REG_H_
+
+#define AR9380_MAX_CHAINS 3
+
+#define AR9380_PHY_CCA_NOM_VAL_2GHZ (-110)
+#define AR9380_PHY_CCA_NOM_VAL_5GHZ (-115)
+#define AR9380_PHY_CCA_MIN_GOOD_VAL_2GHZ (-125)
+#define AR9380_PHY_CCA_MIN_GOOD_VAL_5GHZ (-125)
+#define AR9380_PHY_CCA_MAX_GOOD_VAL_2GHZ ( -95)
+#define AR9380_PHY_CCA_MAX_GOOD_VAL_5GHZ (-100)
+
+/*
+ * ROM layout used by AR9380.
+ */
+#define AR9380_NUM_5G_CAL_PIERS 8
+#define AR9380_NUM_2G_CAL_PIERS 3
+#define AR9380_NUM_5G_20_TARGET_POWERS 8
+#define AR9380_NUM_5G_40_TARGET_POWERS 8
+#define AR9380_NUM_2G_CCK_TARGET_POWERS 2
+#define AR9380_NUM_2G_20_TARGET_POWERS 3
+#define AR9380_NUM_2G_40_TARGET_POWERS 3
+#define AR9380_NUM_CTLS_5G 9
+#define AR9380_NUM_CTLS_2G 12
+#define AR9380_NUM_BAND_EDGES_5G 8
+#define AR9380_NUM_BAND_EDGES_2G 4
+#define AR9380_NUM_PD_GAINS 4
+#define AR9380_PD_GAINS_IN_MASK 4
+#define AR9380_PD_GAIN_ICEPTS 5
+#define AR9380_EEPROM_MODAL_SPURS 5
+#define AR9380_CUSTOMER_DATA_SIZE 20
+
+struct ar9380_cal_ctl_data_2g {
+ uint8_t ctlEdges[AR9380_NUM_BAND_EDGES_2G];
+} __packed;
+
+struct ar9380_cal_ctl_data_5g {
+ uint8_t ctlEdges[AR9380_NUM_BAND_EDGES_5G];
+} __packed;
+
+struct ar9380_base_eep_hdr {
+ uint16_t regDmn[2];
+ uint8_t txrxMask;
+#define AR_EEP_TX_MASK_M 0xf0
+#define AR_EEP_TX_MASK_S 4
+#define AR_EEP_RX_MASK_M 0x0f
+#define AR_EEP_RX_MASK_S 0
+
+ uint8_t opFlags;
+#define AR_OPFLAGS_11A 0x01
+#define AR_OPFLAGS_11G 0x02
+#define AR_OPFLAGS_11N_5G40 0x04
+#define AR_OPFLAGS_11N_2G40 0x08
+#define AR_OPFLAGS_11N_5G20 0x10
+#define AR_OPFLAGS_11N_2G20 0x20
+/* Shortcut. */
+#define AR_OPFLAGS_11N 0x3c
+
+ uint8_t eepMisc;
+ uint8_t rfSilent;
+#define AR_EEP_RFSILENT_ENABLED 0x0001
+#define AR_EEP_RFSILENT_GPIO_SEL_M 0x001c
+#define AR_EEP_RFSILENT_GPIO_SEL_S 2
+#define AR_EEP_RFSILENT_POLARITY 0x0002
+
+ uint8_t blueToothOptions;
+ uint8_t deviceCap;
+ uint8_t deviceType;
+ int8_t pwrTableOffset;
+ uint8_t params_for_tuning_caps[2];
+ uint8_t featureEnable;
+#define AR_EEP_TX_TEMP_COMP_EN 0x01
+#define AR_EEP_TX_VOLT_COMP_EN 0x02
+#define AR_EEP_FAST_CLOCK_EN 0x04
+#define AR_EEP_DOUBLING_EN 0x08
+#define AR_EEP_INTERNAL_REGULATOR 0x10
+#define AR_EEP_PAPRD 0x20
+#define AR_EEP_TUNING_CAPS 0x40
+
+ uint8_t miscConfiguration;
+#define AR_EEP_DRIVE_STRENGTH 0x01
+#define AR_EEP_CHAIN_MASK_REDUCE 0x08
+
+ uint8_t eepromWriteEnableGpio;
+ uint8_t wlanDisableGpio;
+ uint8_t wlanLedGpio;
+ uint8_t rxBandSelectGpio;
+ uint8_t txrxgain;
+#define AR_EEP_TX_GAIN_M 0xf0
+#define AR_EEP_TX_GAIN_S 4
+#define AR_EEP_TX_GAIN_HIGH_OB_DB 1
+#define AR_EEP_TX_GAIN_LOW_OB_DB 2
+#define AR_EEP_TX_GAIN_HIGH_POWER 3
+#define AR_EEP_RX_GAIN_M 0x0f
+#define AR_EEP_RX_GAIN_S 0
+#define AR_EEP_RX_GAIN_WO_XLNA 1
+
+ uint32_t swreg;
+} __packed;
+
+struct ar9380_modal_eep_header {
+ uint32_t antCtrlCommon;
+ uint32_t antCtrlCommon2;
+ uint16_t antCtrlChain[AR9380_MAX_CHAINS];
+ uint8_t xatten1DB[AR9380_MAX_CHAINS];
+ uint8_t xatten1Margin[AR9380_MAX_CHAINS];
+ int8_t tempSlope;
+ int8_t voltSlope;
+ uint8_t spurChans[AR9380_EEPROM_MODAL_SPURS];
+ int8_t noiseFloorThreshCh[AR9380_MAX_CHAINS];
+ uint8_t ob[AR9380_MAX_CHAINS];
+ uint8_t db_stage2[AR9380_MAX_CHAINS];
+ uint8_t db_stage3[AR9380_MAX_CHAINS];
+ uint8_t db_stage4[AR9380_MAX_CHAINS];
+ uint8_t xpaBiasLvl;
+ uint8_t txFrameToDataStart;
+ uint8_t txFrameToPaOn;
+ uint8_t txClip;
+ int8_t antennaGain;
+ uint8_t switchSettling;
+ int8_t adcDesiredSize;
+ uint8_t txEndToXpaOff;
+ uint8_t txEndToRxOn;
+ uint8_t txFrameToXpaOn;
+ uint8_t thresh62;
+ uint32_t papdRateMaskHt20;
+ uint32_t papdRateMaskHt40;
+ uint8_t futureModal[10];
+} __packed;
+
+struct ar9380_cal_data_per_freq_op_loop {
+ int8_t refPower;
+ uint8_t voltMeas;
+ uint8_t tempMeas;
+ int8_t rxNoisefloorCal;
+ int8_t rxNoisefloorPower;
+ uint8_t rxTempMeas;
+} __packed;
+
+struct ar9380_base_extension_1 {
+ uint8_t ant_div_control;
+#define AR_EEP_ANT_DIV_CTRL_ALL_M 0x3f
+#define AR_EEP_ANT_DIV_CTRL_ALL_S 0
+#define AR_EEP_ANT_DIV_CTRL_ANT_DIV 0x40
+#define AR_EEP_ANT_DIV_CTRL_FAST_DIV 0x80
+
+ uint8_t future[13];
+} __packed;
+
+struct ar9380_base_extension_2 {
+ int8_t tempSlopeLow;
+ int8_t tempSlopeHigh;
+ uint8_t xatten1DBLow[AR9380_MAX_CHAINS];
+ uint8_t xatten1MarginLow[AR9380_MAX_CHAINS];
+ uint8_t xatten1DBHigh[AR9380_MAX_CHAINS];
+ uint8_t xatten1MarginHigh[AR9380_MAX_CHAINS];
+} __packed;
+
+struct ar9380_eeprom {
+ uint8_t eepromVersion;
+ uint8_t templateVersion;
+ uint8_t macAddr[6];
+ uint8_t custData[AR9380_CUSTOMER_DATA_SIZE];
+ struct ar9380_base_eep_hdr baseEepHeader;
+ struct ar9380_modal_eep_header modalHeader2G;
+ struct ar9380_base_extension_1 base_ext1;
+ uint8_t calFreqPier2G[AR9380_NUM_2G_CAL_PIERS];
+ struct ar9380_cal_data_per_freq_op_loop
+ calPierData2G[AR9380_MAX_CHAINS][AR9380_NUM_2G_CAL_PIERS];
+ uint8_t calTargetFbinCck[AR9380_NUM_2G_CCK_TARGET_POWERS];
+ uint8_t calTargetFbin2G[AR9380_NUM_2G_20_TARGET_POWERS];
+ uint8_t calTargetFbin2GHT20[AR9380_NUM_2G_20_TARGET_POWERS];
+ uint8_t calTargetFbin2GHT40[AR9380_NUM_2G_40_TARGET_POWERS];
+ struct ar_cal_target_power_leg
+ calTargetPowerCck[AR9380_NUM_2G_CCK_TARGET_POWERS];
+ struct ar_cal_target_power_leg
+ calTargetPower2G[AR9380_NUM_2G_20_TARGET_POWERS];
+ struct ar_cal_target_power_ht
+ calTargetPower2GHT20[AR9380_NUM_2G_20_TARGET_POWERS];
+ struct ar_cal_target_power_ht
+ calTargetPower2GHT40[AR9380_NUM_2G_40_TARGET_POWERS];
+ uint8_t ctlIndex_2G[AR9380_NUM_CTLS_2G];
+ uint8_t ctl_freqbin_2G[AR9380_NUM_CTLS_2G][AR9380_NUM_BAND_EDGES_2G];
+ struct ar9380_cal_ctl_data_2g ctlPowerData_2G[AR9380_NUM_CTLS_2G];
+ struct ar9380_modal_eep_header modalHeader5G;
+ struct ar9380_base_extension_2 base_ext2;
+ uint8_t calFreqPier5G[AR9380_NUM_5G_CAL_PIERS];
+ struct ar9380_cal_data_per_freq_op_loop
+ calPierData5G[AR9380_MAX_CHAINS][AR9380_NUM_5G_CAL_PIERS];
+ uint8_t calTargetFbin5G[AR9380_NUM_5G_20_TARGET_POWERS];
+ uint8_t calTargetFbin5GHT20[AR9380_NUM_5G_20_TARGET_POWERS];
+ uint8_t calTargetFbin5GHT40[AR9380_NUM_5G_40_TARGET_POWERS];
+ struct ar_cal_target_power_leg
+ calTargetPower5G[AR9380_NUM_5G_20_TARGET_POWERS];
+ struct ar_cal_target_power_ht
+ calTargetPower5GHT20[AR9380_NUM_5G_20_TARGET_POWERS];
+ struct ar_cal_target_power_ht
+ calTargetPower5GHT40[AR9380_NUM_5G_40_TARGET_POWERS];
+ uint8_t ctlIndex_5G[AR9380_NUM_CTLS_5G];
+ uint8_t ctl_freqbin_5G[AR9380_NUM_CTLS_5G][AR9380_NUM_BAND_EDGES_5G];
+ struct ar9380_cal_ctl_data_5g ctlPowerData_5G[AR9380_NUM_CTLS_5G];
+} __packed;
+
+/*
+ * ROM templates (little endian).
+ */
+static const uint8_t ar9380_def_rom[] = {
+ 0x02, 0x02, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x1f, 0x00, 0x77, 0x03, 0x00, 0x00, 0x00, 0x00, 0x05, 0x00,
+ 0x00, 0x00, 0x0c, 0x00, 0x03, 0x00, 0x08, 0xff, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x10, 0x01, 0x00, 0x00, 0x22, 0x22, 0x02,
+ 0x00, 0x50, 0x01, 0x50, 0x01, 0x50, 0x01, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0xff, 0x00, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0e, 0x0e, 0x03, 0x00,
+ 0x2c, 0xe2, 0x00, 0x02, 0x0e, 0x1c, 0xe0, 0xe0, 0xf0, 0x0c,
+ 0xe0, 0xe0, 0xf0, 0x6c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x89,
+ 0xac, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0xb8, 0x70, 0x89, 0xac,
+ 0x70, 0x89, 0xac, 0x70, 0x89, 0xac, 0x24, 0x24, 0x24, 0x24,
+ 0x24, 0x24, 0x24, 0x24, 0x20, 0x20, 0x1c, 0x18, 0x20, 0x20,
+ 0x1c, 0x18, 0x20, 0x20, 0x1c, 0x18, 0x20, 0x20, 0x20, 0x20,
+ 0x1c, 0x14, 0x20, 0x20, 0x1c, 0x14, 0x20, 0x20, 0x1c, 0x14,
+ 0x20, 0x20, 0x20, 0x20, 0x1c, 0x14, 0x20, 0x20, 0x1c, 0x14,
+ 0x20, 0x20, 0x1c, 0x14, 0x20, 0x20, 0x20, 0x20, 0x1c, 0x14,
+ 0x20, 0x20, 0x1c, 0x14, 0x20, 0x20, 0x1c, 0x14, 0x20, 0x20,
+ 0x20, 0x20, 0x1c, 0x14, 0x20, 0x20, 0x1c, 0x14, 0x20, 0x20,
+ 0x1c, 0x14, 0x20, 0x20, 0x20, 0x20, 0x1c, 0x14, 0x20, 0x20,
+ 0x1c, 0x14, 0x20, 0x20, 0x1c, 0x14, 0x20, 0x20, 0x20, 0x20,
+ 0x1c, 0x14, 0x20, 0x20, 0x1c, 0x14, 0x20, 0x20, 0x1c, 0x14,
+ 0x11, 0x12, 0x15, 0x17, 0x41, 0x42, 0x45, 0x47, 0x31, 0x32,
+ 0x35, 0x37, 0x70, 0x75, 0x9d, 0xa2, 0x70, 0x75, 0xa2, 0xff,
+ 0x70, 0x75, 0xa2, 0xff, 0x7a, 0x7f, 0x93, 0x98, 0x70, 0x75,
+ 0xac, 0xb8, 0x70, 0x75, 0xac, 0x00, 0x70, 0x75, 0xac, 0x00,
+ 0x7a, 0x7f, 0x93, 0xa2, 0x70, 0x75, 0xac, 0x00, 0x70, 0x75,
+ 0xac, 0x00, 0x70, 0x75, 0xac, 0x00, 0x7a, 0x7f, 0x93, 0xa2,
+ 0x3c, 0x7c, 0x3c, 0x3c, 0x3c, 0x7c, 0x3c, 0x3c, 0x7c, 0x3c,
+ 0x3c, 0x7c, 0x7c, 0x3c, 0x00, 0x00, 0x3c, 0x7c, 0x3c, 0x3c,
+ 0x3c, 0x7c, 0x3c, 0x3c, 0x3c, 0x7c, 0x7c, 0x3c, 0x3c, 0x7c,
+ 0x3c, 0x3c, 0x3c, 0x7c, 0x3c, 0x3c, 0x3c, 0x7c, 0x3c, 0x3c,
+ 0x3c, 0x7c, 0x7c, 0x7c, 0x3c, 0x7c, 0x7c, 0x7c, 0x10, 0x01,
+ 0x00, 0x00, 0x22, 0x22, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x44, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x03, 0x03,
+ 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03,
+ 0x00, 0x0e, 0x0e, 0x03, 0x00, 0x2d, 0xe2, 0x00, 0x02, 0x0e,
+ 0x1c, 0x80, 0xc0, 0x80, 0x0c, 0x80, 0xc0, 0x80, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x4c, 0x54, 0x68, 0x78, 0x8c, 0xa0, 0xb9,
+ 0xcd, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x4c, 0x54, 0x68, 0x78, 0x8c,
+ 0xa0, 0xb9, 0xcd, 0x4c, 0x58, 0x68, 0x8c, 0xb4, 0xbd, 0xb9,
+ 0xcd, 0x4c, 0x58, 0x68, 0x8c, 0xb4, 0xbd, 0xb9, 0xcd, 0x14,
+ 0x14, 0x14, 0x0a, 0x14, 0x14, 0x14, 0x0a, 0x14, 0x14, 0x14,
+ 0x0a, 0x14, 0x14, 0x14, 0x0a, 0x14, 0x14, 0x14, 0x0a, 0x14,
+ 0x14, 0x14, 0x0a, 0x14, 0x14, 0x14, 0x0a, 0x14, 0x14, 0x14,
+ 0x0a, 0x14, 0x14, 0x0a, 0x0a, 0x00, 0x00, 0x0a, 0x0a, 0x00,
+ 0x00, 0x0a, 0x0a, 0x00, 0x00, 0x14, 0x14, 0x0a, 0x0a, 0x00,
+ 0x00, 0x0a, 0x0a, 0x00, 0x00, 0x0a, 0x0a, 0x00, 0x00, 0x14,
+ 0x14, 0x0a, 0x0a, 0x00, 0x00, 0x0a, 0x0a, 0x00, 0x00, 0x0a,
+ 0x0a, 0x00, 0x00, 0x14, 0x14, 0x0a, 0x0a, 0x00, 0x00, 0x0a,
+ 0x0a, 0x00, 0x00, 0x0a, 0x0a, 0x00, 0x00, 0x14, 0x14, 0x0a,
+ 0x0a, 0x00, 0x00, 0x0a, 0x0a, 0x00, 0x00, 0x0a, 0x0a, 0x00,
+ 0x00, 0x14, 0x14, 0x0a, 0x0a, 0x00, 0x00, 0x0a, 0x0a, 0x00,
+ 0x00, 0x0a, 0x0a, 0x00, 0x00, 0x14, 0x14, 0x0a, 0x0a, 0x00,
+ 0x00, 0x0a, 0x0a, 0x00, 0x00, 0x0a, 0x0a, 0x00, 0x00, 0x14,
+ 0x14, 0x0a, 0x0a, 0x00, 0x00, 0x0a, 0x0a, 0x00, 0x00, 0x0a,
+ 0x0a, 0x00, 0x00, 0x14, 0x14, 0x0a, 0x0a, 0x00, 0x00, 0x0a,
+ 0x0a, 0x00, 0x00, 0x0a, 0x0a, 0x00, 0x00, 0x14, 0x14, 0x0a,
+ 0x0a, 0x00, 0x00, 0x0a, 0x0a, 0x00, 0x00, 0x0a, 0x0a, 0x00,
+ 0x00, 0x14, 0x14, 0x0a, 0x0a, 0x00, 0x00, 0x0a, 0x0a, 0x00,
+ 0x00, 0x0a, 0x0a, 0x00, 0x00, 0x14, 0x14, 0x0a, 0x0a, 0x00,
+ 0x00, 0x0a, 0x0a, 0x00, 0x00, 0x0a, 0x0a, 0x00, 0x00, 0x14,
+ 0x14, 0x0a, 0x0a, 0x00, 0x00, 0x0a, 0x0a, 0x00, 0x00, 0x0a,
+ 0x0a, 0x00, 0x00, 0x14, 0x14, 0x0a, 0x0a, 0x00, 0x00, 0x0a,
+ 0x0a, 0x00, 0x00, 0x0a, 0x0a, 0x00, 0x00, 0x14, 0x14, 0x0a,
+ 0x0a, 0x00, 0x00, 0x0a, 0x0a, 0x00, 0x00, 0x0a, 0x0a, 0x00,
+ 0x00, 0x14, 0x14, 0x0a, 0x0a, 0x00, 0x00, 0x0a, 0x0a, 0x00,
+ 0x00, 0x0a, 0x0a, 0x00, 0x00, 0x10, 0x16, 0x18, 0x40, 0x46,
+ 0x48, 0x30, 0x36, 0x38, 0x4c, 0x5c, 0x60, 0x8c, 0xa0, 0xb4,
+ 0xbd, 0xcd, 0x4c, 0x5c, 0x60, 0x8c, 0x90, 0xb4, 0xbd, 0xcd,
+ 0x4e, 0x56, 0x5e, 0x66, 0x8e, 0x96, 0xae, 0xbf, 0x4c, 0x50,
+ 0x5c, 0x68, 0x8c, 0xb4, 0xff, 0xff, 0x4c, 0x5c, 0x8c, 0xb4,
+ 0xff, 0xff, 0xff, 0xff, 0x4e, 0x5e, 0x66, 0x8e, 0x9e, 0xae,
+ 0xff, 0xff, 0x4c, 0x50, 0x54, 0x5c, 0x8c, 0xa0, 0xb4, 0xbd,
+ 0x4c, 0x5c, 0x68, 0x8c, 0x98, 0xb4, 0xbd, 0xcd, 0x4e, 0x56,
+ 0x5e, 0x8e, 0x96, 0xae, 0xbf, 0xc7, 0x7c, 0x7c, 0x7c, 0x7c,
+ 0x7c, 0x7c, 0x7c, 0x3c, 0x7c, 0x7c, 0x7c, 0x7c, 0x7c, 0x7c,
+ 0x7c, 0x3c, 0x3c, 0x7c, 0x3c, 0x7c, 0x7c, 0x7c, 0x7c, 0x7c,
+ 0x3c, 0x7c, 0x7c, 0x3c, 0x7c, 0x3c, 0x3c, 0x3c, 0x7c, 0x7c,
+ 0x7c, 0x3c, 0x3c, 0x3c, 0x3c, 0x3c, 0x7c, 0x7c, 0x7c, 0x7c,
+ 0x7c, 0x3c, 0x3c, 0x3c, 0x7c, 0x7c, 0x7c, 0x7c, 0x7c, 0x7c,
+ 0x7c, 0x7c, 0x7c, 0x7c, 0x3c, 0x7c, 0x7c, 0x7c, 0x7c, 0x3c,
+ 0x7c, 0x3c, 0x7c, 0x7c, 0x7c, 0x7c, 0x3c, 0x7c
+};
+
+static const uint8_t ar9380_def_rom_h112[] = {
+ 0x02, 0x03, 0x00, 0x03, 0x7f, 0x00, 0x00, 0x00, 0x68, 0x31,
+ 0x31, 0x32, 0x2d, 0x32, 0x34, 0x31, 0x2d, 0x66, 0x30, 0x30,
+ 0x30, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x1f, 0x00, 0x77, 0x03, 0x00, 0x00, 0x00, 0x00, 0x05, 0x00,
+ 0x00, 0x00, 0x0d, 0x00, 0x06, 0x00, 0x08, 0xff, 0x10, 0x00,
+ 0x00, 0x00, 0x00, 0x10, 0x01, 0x00, 0x00, 0x44, 0x44, 0x04,
+ 0x00, 0x50, 0x01, 0x50, 0x01, 0x50, 0x01, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x19, 0x00, 0xa4, 0x00, 0x00, 0x00, 0x00,
+ 0xff, 0x00, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0e, 0x0e, 0x03, 0x00,
+ 0x2c, 0xe2, 0x00, 0x02, 0x0e, 0x1c, 0x80, 0xc0, 0x80, 0x00,
+ 0x80, 0xc0, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x89,
+ 0xac, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0xb8, 0x70, 0x89, 0xac,
+ 0x70, 0x89, 0xac, 0x70, 0x89, 0xac, 0x22, 0x22, 0x22, 0x22,
+ 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x20, 0x20, 0x22, 0x22,
+ 0x20, 0x20, 0x22, 0x22, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+ 0x20, 0x1e, 0x20, 0x20, 0x1e, 0x1c, 0x1c, 0x1c, 0x1c, 0x18,
+ 0x20, 0x20, 0x20, 0x20, 0x20, 0x1e, 0x20, 0x20, 0x1e, 0x1c,
+ 0x1c, 0x1c, 0x1c, 0x18, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1e,
+ 0x20, 0x20, 0x1e, 0x1c, 0x1c, 0x1c, 0x1c, 0x18, 0x1e, 0x1e,
+ 0x1e, 0x1e, 0x1e, 0x1c, 0x1e, 0x1e, 0x1c, 0x1a, 0x1a, 0x1a,
+ 0x1a, 0x16, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1c, 0x1e, 0x1e,
+ 0x1c, 0x1a, 0x1a, 0x1a, 0x1a, 0x16, 0x1e, 0x1e, 0x1e, 0x1e,
+ 0x1e, 0x1c, 0x1e, 0x1e, 0x1c, 0x1a, 0x1a, 0x1a, 0x1a, 0x16,
+ 0x11, 0x12, 0x15, 0x17, 0x41, 0x42, 0x45, 0x47, 0x31, 0x32,
+ 0x35, 0x37, 0x70, 0x75, 0x9d, 0xa2, 0x70, 0x75, 0xa2, 0xff,
+ 0x70, 0x75, 0xa2, 0xff, 0x7a, 0x7f, 0x93, 0x98, 0x70, 0x75,
+ 0xac, 0xb8, 0x70, 0x75, 0xac, 0x00, 0x70, 0x75, 0xac, 0x00,
+ 0x7a, 0x7f, 0x93, 0xa2, 0x70, 0x75, 0xac, 0x00, 0x70, 0x75,
+ 0xac, 0x00, 0x70, 0x75, 0xac, 0x00, 0x7a, 0x7f, 0x93, 0xa2,
+ 0x3c, 0x7c, 0x3c, 0x3c, 0x3c, 0x7c, 0x3c, 0x3c, 0x7c, 0x3c,
+ 0x3c, 0x7c, 0x7c, 0x3c, 0x00, 0x00, 0x3c, 0x7c, 0x3c, 0x3c,
+ 0x3c, 0x7c, 0x3c, 0x3c, 0x3c, 0x7c, 0x7c, 0x3c, 0x3c, 0x7c,
+ 0x3c, 0x3c, 0x3c, 0x7c, 0x3c, 0x3c, 0x3c, 0x7c, 0x3c, 0x3c,
+ 0x3c, 0x7c, 0x7c, 0x7c, 0x3c, 0x7c, 0x7c, 0x7c, 0x20, 0x02,
+ 0x00, 0x00, 0x44, 0x44, 0x04, 0x00, 0x50, 0x01, 0x50, 0x01,
+ 0x50, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2d, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x03, 0x03,
+ 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03,
+ 0x00, 0x0e, 0x0e, 0x03, 0x00, 0x2d, 0xe2, 0x00, 0x02, 0x0e,
+ 0x1c, 0xe0, 0xe0, 0xf0, 0x0c, 0xe0, 0xe0, 0xf0, 0x6c, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x28,
+ 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x4c, 0x54, 0x68, 0x78, 0x8c, 0xa0, 0xb4,
+ 0xcd, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x4c, 0x58, 0x68, 0x78, 0x8c,
+ 0xa0, 0xb4, 0xcd, 0x4c, 0x58, 0x68, 0x78, 0x8c, 0xb4, 0xbd,
+ 0xcd, 0x4c, 0x58, 0x68, 0x78, 0x8c, 0xb4, 0xbd, 0xcd, 0x1e,
+ 0x1e, 0x1c, 0x18, 0x1e, 0x1e, 0x1c, 0x18, 0x1e, 0x1e, 0x1c,
+ 0x18, 0x1e, 0x1e, 0x1c, 0x18, 0x1e, 0x1e, 0x1c, 0x18, 0x1e,
+ 0x1e, 0x1c, 0x18, 0x1e, 0x1e, 0x1c, 0x18, 0x1e, 0x1e, 0x1c,
+ 0x18, 0x1e, 0x1e, 0x1e, 0x1c, 0x18, 0x14, 0x1e, 0x1c, 0x18,
+ 0x14, 0x14, 0x14, 0x14, 0x10, 0x1e, 0x1e, 0x1e, 0x1c, 0x18,
+ 0x14, 0x1e, 0x1c, 0x18, 0x14, 0x14, 0x14, 0x14, 0x10, 0x1e,
+ 0x1e, 0x1e, 0x1a, 0x16, 0x12, 0x1e, 0x1a, 0x16, 0x12, 0x12,
+ 0x12, 0x12, 0x10, 0x1e, 0x1e, 0x1e, 0x1a, 0x16, 0x12, 0x1e,
+ 0x1a, 0x16, 0x12, 0x12, 0x12, 0x12, 0x10, 0x1e, 0x1e, 0x1e,
+ 0x18, 0x14, 0x10, 0x1e, 0x18, 0x14, 0x10, 0x10, 0x10, 0x10,
+ 0x0e, 0x1e, 0x1e, 0x1e, 0x18, 0x14, 0x10, 0x1e, 0x18, 0x14,
+ 0x10, 0x10, 0x10, 0x10, 0x0e, 0x1e, 0x1e, 0x1e, 0x16, 0x12,
+ 0x0e, 0x1e, 0x16, 0x12, 0x0e, 0x0e, 0x0e, 0x0e, 0x0c, 0x1e,
+ 0x1e, 0x1e, 0x16, 0x12, 0x0e, 0x1e, 0x16, 0x12, 0x0e, 0x0e,
+ 0x0e, 0x0e, 0x0c, 0x1c, 0x1c, 0x1c, 0x1a, 0x16, 0x12, 0x1c,
+ 0x1a, 0x16, 0x12, 0x12, 0x12, 0x12, 0x0e, 0x1c, 0x1c, 0x1c,
+ 0x1a, 0x16, 0x12, 0x1c, 0x1a, 0x16, 0x12, 0x12, 0x12, 0x12,
+ 0x0e, 0x1c, 0x1c, 0x1c, 0x18, 0x14, 0x10, 0x1c, 0x18, 0x14,
+ 0x10, 0x10, 0x10, 0x10, 0x0c, 0x1c, 0x1c, 0x1c, 0x18, 0x14,
+ 0x10, 0x1c, 0x18, 0x14, 0x10, 0x10, 0x10, 0x10, 0x0c, 0x1c,
+ 0x1c, 0x1c, 0x16, 0x12, 0x0e, 0x1c, 0x16, 0x12, 0x0e, 0x0e,
+ 0x0e, 0x0e, 0x0a, 0x1c, 0x1c, 0x1c, 0x16, 0x12, 0x0e, 0x1c,
+ 0x16, 0x12, 0x0e, 0x0e, 0x0e, 0x0e, 0x0a, 0x1c, 0x1c, 0x1c,
+ 0x14, 0x10, 0x0c, 0x1c, 0x14, 0x10, 0x0c, 0x0c, 0x0c, 0x0c,
+ 0x08, 0x1c, 0x1c, 0x1c, 0x14, 0x10, 0x0c, 0x1c, 0x14, 0x10,
+ 0x0c, 0x0c, 0x0c, 0x0c, 0x08, 0x10, 0x16, 0x18, 0x40, 0x46,
+ 0x48, 0x30, 0x36, 0x38, 0x4c, 0x5c, 0x60, 0x8c, 0xa0, 0xb4,
+ 0xbd, 0xcd, 0x4c, 0x5c, 0x60, 0x8c, 0x90, 0xb4, 0xbd, 0xcd,
+ 0x4e, 0x56, 0x5e, 0x66, 0x8e, 0x96, 0xae, 0xbf, 0x4c, 0x50,
+ 0x5c, 0x68, 0x8c, 0xb4, 0xff, 0xff, 0x4c, 0x5c, 0x8c, 0xb4,
+ 0xff, 0xff, 0xff, 0xff, 0x4e, 0x5e, 0x66, 0x8e, 0x9e, 0xae,
+ 0xff, 0xff, 0x4c, 0x50, 0x54, 0x5c, 0x8c, 0xa0, 0xb4, 0xbd,
+ 0x4c, 0x5c, 0x68, 0x8c, 0x98, 0xb4, 0xbd, 0xcd, 0x4e, 0x56,
+ 0x5e, 0x8e, 0x96, 0xae, 0xbf, 0xc7, 0x7c, 0x7c, 0x7c, 0x7c,
+ 0x7c, 0x7c, 0x7c, 0x3c, 0x7c, 0x7c, 0x7c, 0x7c, 0x7c, 0x7c,
+ 0x7c, 0x3c, 0x3c, 0x7c, 0x3c, 0x7c, 0x7c, 0x7c, 0x7c, 0x7c,
+ 0x3c, 0x7c, 0x7c, 0x3c, 0x7c, 0x3c, 0x3c, 0x3c, 0x7c, 0x7c,
+ 0x7c, 0x3c, 0x3c, 0x3c, 0x3c, 0x3c, 0x7c, 0x7c, 0x7c, 0x7c,
+ 0x7c, 0x3c, 0x3c, 0x3c, 0x7c, 0x7c, 0x7c, 0x7c, 0x7c, 0x7c,
+ 0x7c, 0x7c, 0x7c, 0x7c, 0x3c, 0x7c, 0x7c, 0x7c, 0x7c, 0x3c,
+ 0x7c, 0x3c, 0x7c, 0x7c, 0x7c, 0x7c, 0x3c, 0x7c
+};
+
+static const uint8_t ar9380_def_rom_h116[] = {
+ 0x02, 0x04, 0x00, 0x03, 0x7f, 0x00, 0x00, 0x00, 0x68, 0x31,
+ 0x31, 0x36, 0x2d, 0x30, 0x34, 0x31, 0x2d, 0x66, 0x30, 0x30,
+ 0x30, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x1f, 0x00, 0x33, 0x03, 0x00, 0x00, 0x00, 0x00, 0x05, 0x00,
+ 0x00, 0x00, 0x0d, 0x00, 0x06, 0x00, 0x08, 0xff, 0x10, 0x00,
+ 0x00, 0x00, 0x00, 0x10, 0x01, 0x00, 0x00, 0x44, 0x44, 0x04,
+ 0x00, 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0x1f, 0x1f, 0x1f,
+ 0x12, 0x12, 0x12, 0x19, 0x00, 0xa4, 0x00, 0x00, 0x00, 0x00,
+ 0xff, 0x00, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0e, 0x0e, 0x03, 0x00,
+ 0x2c, 0xe2, 0x00, 0x02, 0x0e, 0x1c, 0x80, 0xc0, 0x80, 0x0c,
+ 0x80, 0xc0, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x89,
+ 0xac, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0xac, 0x70, 0x89, 0xac,
+ 0x70, 0x89, 0xac, 0x70, 0x89, 0xac, 0x22, 0x22, 0x22, 0x22,
+ 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x20, 0x20, 0x22, 0x22,
+ 0x20, 0x20, 0x22, 0x22, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+ 0x20, 0x1e, 0x20, 0x20, 0x1e, 0x1c, 0x00, 0x00, 0x00, 0x00,
+ 0x20, 0x20, 0x20, 0x20, 0x20, 0x1e, 0x20, 0x20, 0x1e, 0x1c,
+ 0x00, 0x00, 0x00, 0x00, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1e,
+ 0x20, 0x20, 0x1e, 0x1c, 0x00, 0x00, 0x00, 0x00, 0x1e, 0x1e,
+ 0x1e, 0x1e, 0x1e, 0x1c, 0x1e, 0x1e, 0x1c, 0x1a, 0x00, 0x00,
+ 0x00, 0x00, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1c, 0x1e, 0x1e,
+ 0x1c, 0x1a, 0x00, 0x00, 0x00, 0x00, 0x1e, 0x1e, 0x1e, 0x1e,
+ 0x1e, 0x1c, 0x1e, 0x1e, 0x1c, 0x1a, 0x00, 0x00, 0x00, 0x00,
+ 0x11, 0x12, 0x15, 0x17, 0x41, 0x42, 0x45, 0x47, 0x31, 0x32,
+ 0x35, 0x37, 0x70, 0x75, 0x9d, 0xa2, 0x70, 0x75, 0xa2, 0xff,
+ 0x70, 0x75, 0xa2, 0xff, 0x7a, 0x7f, 0x93, 0x98, 0x70, 0x75,
+ 0xac, 0xb8, 0x70, 0x75, 0xac, 0x00, 0x70, 0x75, 0xac, 0x00,
+ 0x7a, 0x7f, 0x93, 0xa2, 0x70, 0x75, 0xac, 0x00, 0x70, 0x75,
+ 0xac, 0x00, 0x70, 0x75, 0xac, 0x00, 0x7a, 0x7f, 0x93, 0xa2,
+ 0x3c, 0x7c, 0x3c, 0x3c, 0x3c, 0x7c, 0x3c, 0x3c, 0x7c, 0x3c,
+ 0x3c, 0x7c, 0x7c, 0x3c, 0x00, 0x00, 0x3c, 0x7c, 0x3c, 0x3c,
+ 0x3c, 0x7c, 0x3c, 0x3c, 0x3c, 0x7c, 0x7c, 0x3c, 0x3c, 0x7c,
+ 0x3c, 0x3c, 0x3c, 0x7c, 0x3c, 0x3c, 0x3c, 0x7c, 0x3c, 0x3c,
+ 0x3c, 0x7c, 0x7c, 0x7c, 0x3c, 0x7c, 0x7c, 0x7c, 0x20, 0x02,
+ 0x00, 0x00, 0x44, 0x44, 0x04, 0x00, 0x50, 0x01, 0x50, 0x01,
+ 0x50, 0x01, 0x19, 0x19, 0x19, 0x14, 0x14, 0x14, 0x46, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x03, 0x03,
+ 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03,
+ 0x00, 0x0e, 0x0e, 0x03, 0x00, 0x2d, 0xe2, 0x00, 0x02, 0x0e,
+ 0x1c, 0xe0, 0xe0, 0xf0, 0x0c, 0xe0, 0xe0, 0xf0, 0x6c, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
+ 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x4c, 0x54, 0x68, 0x78, 0x8c, 0xa0, 0xb4,
+ 0xc5, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x4c, 0x58, 0x68, 0x78, 0x8c,
+ 0xa0, 0xb4, 0xcd, 0x4c, 0x58, 0x68, 0x78, 0x8c, 0xb4, 0xbd,
+ 0xcd, 0x4c, 0x58, 0x68, 0x78, 0x8c, 0xb4, 0xbd, 0xcd, 0x1e,
+ 0x1e, 0x1c, 0x18, 0x1e, 0x1e, 0x1c, 0x18, 0x1e, 0x1e, 0x1c,
+ 0x18, 0x1e, 0x1e, 0x1c, 0x18, 0x1e, 0x1e, 0x1c, 0x18, 0x1e,
+ 0x1e, 0x1c, 0x18, 0x1e, 0x1e, 0x1c, 0x18, 0x1e, 0x1e, 0x1c,
+ 0x18, 0x1e, 0x1e, 0x1e, 0x1c, 0x18, 0x14, 0x1e, 0x1c, 0x18,
+ 0x14, 0x00, 0x00, 0x00, 0x00, 0x1e, 0x1e, 0x1e, 0x1c, 0x18,
+ 0x14, 0x1e, 0x1c, 0x18, 0x14, 0x00, 0x00, 0x00, 0x00, 0x1e,
+ 0x1e, 0x1e, 0x1a, 0x16, 0x12, 0x1e, 0x1a, 0x16, 0x12, 0x00,
+ 0x00, 0x00, 0x00, 0x1e, 0x1e, 0x1e, 0x1a, 0x16, 0x12, 0x1e,
+ 0x1a, 0x16, 0x12, 0x00, 0x00, 0x00, 0x00, 0x1e, 0x1e, 0x1e,
+ 0x18, 0x14, 0x10, 0x1e, 0x18, 0x14, 0x10, 0x00, 0x00, 0x00,
+ 0x00, 0x1e, 0x1e, 0x1e, 0x18, 0x14, 0x10, 0x1e, 0x18, 0x14,
+ 0x10, 0x00, 0x00, 0x00, 0x00, 0x1e, 0x1e, 0x1e, 0x16, 0x12,
+ 0x0e, 0x1e, 0x16, 0x12, 0x0e, 0x00, 0x00, 0x00, 0x00, 0x1e,
+ 0x1e, 0x1e, 0x16, 0x12, 0x0e, 0x1e, 0x16, 0x12, 0x0e, 0x00,
+ 0x00, 0x00, 0x00, 0x1c, 0x1c, 0x1c, 0x1a, 0x16, 0x12, 0x1c,
+ 0x1a, 0x16, 0x12, 0x00, 0x00, 0x00, 0x00, 0x1c, 0x1c, 0x1c,
+ 0x1a, 0x16, 0x12, 0x1c, 0x1a, 0x16, 0x12, 0x00, 0x00, 0x00,
+ 0x00, 0x1c, 0x1c, 0x1c, 0x18, 0x14, 0x10, 0x1c, 0x18, 0x14,
+ 0x10, 0x00, 0x00, 0x00, 0x00, 0x1c, 0x1c, 0x1c, 0x18, 0x14,
+ 0x10, 0x1c, 0x18, 0x14, 0x10, 0x00, 0x00, 0x00, 0x00, 0x1c,
+ 0x1c, 0x1c, 0x16, 0x12, 0x0e, 0x1c, 0x16, 0x12, 0x0e, 0x00,
+ 0x00, 0x00, 0x00, 0x1c, 0x1c, 0x1c, 0x16, 0x12, 0x0e, 0x1c,
+ 0x16, 0x12, 0x0e, 0x00, 0x00, 0x00, 0x00, 0x1c, 0x1c, 0x1c,
+ 0x14, 0x10, 0x0c, 0x1c, 0x14, 0x10, 0x0c, 0x00, 0x00, 0x00,
+ 0x00, 0x1c, 0x1c, 0x1c, 0x14, 0x10, 0x0c, 0x1c, 0x14, 0x10,
+ 0x0c, 0x00, 0x00, 0x00, 0x00, 0x10, 0x16, 0x18, 0x40, 0x46,
+ 0x48, 0x30, 0x36, 0x38, 0x4c, 0x5c, 0x60, 0x8c, 0xa0, 0xb4,
+ 0xbd, 0xcd, 0x4c, 0x5c, 0x60, 0x8c, 0x90, 0xb4, 0xbd, 0xcd,
+ 0x4e, 0x56, 0x5e, 0x66, 0x8e, 0x96, 0xae, 0xbf, 0x4c, 0x50,
+ 0x5c, 0x68, 0x8c, 0xb4, 0xff, 0xff, 0x4c, 0x5c, 0x8c, 0xb4,
+ 0xff, 0xff, 0xff, 0xff, 0x4e, 0x5e, 0x66, 0x8e, 0x9e, 0xae,
+ 0xff, 0xff, 0x4c, 0x50, 0x54, 0x5c, 0x8c, 0xa0, 0xb4, 0xbd,
+ 0x4c, 0x5c, 0x68, 0x8c, 0x98, 0xb4, 0xbd, 0xcd, 0x4e, 0x56,
+ 0x5e, 0x8e, 0x96, 0xae, 0xbf, 0xc7, 0x7c, 0x7c, 0x7c, 0x7c,
+ 0x7c, 0x7c, 0x7c, 0x3c, 0x7c, 0x7c, 0x7c, 0x7c, 0x7c, 0x7c,
+ 0x7c, 0x3c, 0x3c, 0x7c, 0x3c, 0x7c, 0x7c, 0x7c, 0x7c, 0x7c,
+ 0x3c, 0x7c, 0x7c, 0x3c, 0x7c, 0x3c, 0x3c, 0x3c, 0x7c, 0x7c,
+ 0x7c, 0x3c, 0x3c, 0x3c, 0x3c, 0x3c, 0x7c, 0x7c, 0x7c, 0x7c,
+ 0x7c, 0x3c, 0x3c, 0x3c, 0x7c, 0x7c, 0x7c, 0x7c, 0x7c, 0x7c,
+ 0x7c, 0x7c, 0x7c, 0x7c, 0x3c, 0x7c, 0x7c, 0x7c, 0x7c, 0x3c,
+ 0x7c, 0x3c, 0x7c, 0x7c, 0x7c, 0x7c, 0x3c, 0x7c
+};
+
+static const uint8_t ar9380_def_rom_x112[] = {
+ 0x02, 0x05, 0x00, 0x03, 0x7f, 0x00, 0x00, 0x00, 0x78, 0x31,
+ 0x31, 0x32, 0x2d, 0x30, 0x34, 0x31, 0x2d, 0x66, 0x30, 0x30,
+ 0x30, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x1f, 0x00, 0x77, 0x03, 0x00, 0x00, 0x00, 0x00, 0x05, 0x00,
+ 0x00, 0x00, 0x0d, 0x00, 0x06, 0x00, 0x08, 0xff, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x10, 0x01, 0x00, 0x00, 0x22, 0x22, 0x02,
+ 0x00, 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0x1b, 0x1b, 0x1b,
+ 0x15, 0x15, 0x15, 0x32, 0x00, 0xa4, 0x00, 0x00, 0x00, 0x00,
+ 0xff, 0x00, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0e, 0x0e, 0x03, 0x00,
+ 0x2c, 0xe2, 0x00, 0x02, 0x0e, 0x1c, 0x80, 0xc0, 0x80, 0x0c,
+ 0x80, 0xc0, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x89,
+ 0xac, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0xac, 0x70, 0x89, 0xac,
+ 0x70, 0x89, 0xac, 0x70, 0x89, 0xac, 0x26, 0x26, 0x26, 0x26,
+ 0x26, 0x26, 0x26, 0x26, 0x26, 0x26, 0x24, 0x22, 0x26, 0x26,
+ 0x24, 0x22, 0x26, 0x26, 0x22, 0x20, 0x24, 0x24, 0x24, 0x24,
+ 0x24, 0x22, 0x22, 0x20, 0x1e, 0x1c, 0x1c, 0x1c, 0x1c, 0x1a,
+ 0x24, 0x24, 0x24, 0x24, 0x24, 0x22, 0x24, 0x22, 0x20, 0x1e,
+ 0x1e, 0x1e, 0x1c, 0x1a, 0x24, 0x24, 0x24, 0x24, 0x24, 0x22,
+ 0x22, 0x20, 0x1e, 0x1c, 0x1c, 0x1c, 0x1c, 0x1a, 0x24, 0x24,
+ 0x24, 0x24, 0x22, 0x20, 0x20, 0x1e, 0x1c, 0x1a, 0x1a, 0x1a,
+ 0x1a, 0x18, 0x24, 0x24, 0x24, 0x24, 0x22, 0x20, 0x22, 0x20,
+ 0x1e, 0x1c, 0x1c, 0x1c, 0x1c, 0x18, 0x24, 0x24, 0x24, 0x24,
+ 0x22, 0x20, 0x20, 0x1e, 0x1c, 0x1a, 0x1a, 0x1a, 0x1a, 0x18,
+ 0x11, 0x12, 0x15, 0x17, 0x41, 0x42, 0x45, 0x47, 0x31, 0x32,
+ 0x35, 0x37, 0x70, 0x75, 0x9d, 0xa2, 0x70, 0x75, 0xa2, 0xff,
+ 0x70, 0x75, 0xa2, 0xff, 0x7a, 0x7f, 0x93, 0x98, 0x70, 0x75,
+ 0xac, 0xb8, 0x70, 0x75, 0xac, 0x00, 0x70, 0x75, 0xac, 0x00,
+ 0x7a, 0x7f, 0x93, 0xa2, 0x70, 0x75, 0xac, 0x00, 0x70, 0x75,
+ 0xac, 0x00, 0x70, 0x75, 0xac, 0x00, 0x7a, 0x7f, 0x93, 0xa2,
+ 0x3c, 0x7c, 0x3c, 0x3c, 0x3c, 0x7c, 0x3c, 0x3c, 0x7c, 0x3c,
+ 0x3c, 0x7c, 0x7c, 0x3c, 0x00, 0x00, 0x3c, 0x7c, 0x3c, 0x3c,
+ 0x3c, 0x7c, 0x3c, 0x3c, 0x3c, 0x7c, 0x7c, 0x3c, 0x3c, 0x7c,
+ 0x3c, 0x3c, 0x3c, 0x7c, 0x3c, 0x3c, 0x3c, 0x7c, 0x3c, 0x3c,
+ 0x3c, 0x7c, 0x7c, 0x7c, 0x3c, 0x7c, 0x7c, 0x7c, 0x10, 0x01,
+ 0x00, 0x00, 0x22, 0x22, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x13, 0x19, 0x17, 0x19, 0x19, 0x19, 0x46, 0x0f,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x03, 0x03,
+ 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03,
+ 0x00, 0x0e, 0x0e, 0x03, 0x00, 0x2d, 0xe2, 0x00, 0x02, 0x0e,
+ 0x1c, 0xe0, 0xe0, 0xf0, 0x0c, 0xe0, 0xe0, 0xf0, 0x6c, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48,
+ 0x69, 0x10, 0x14, 0x10, 0x19, 0x19, 0x19, 0x1d, 0x20, 0x24,
+ 0x10, 0x10, 0x10, 0x4c, 0x54, 0x68, 0x78, 0x8c, 0xa0, 0xb4,
+ 0xc5, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x4c, 0x54, 0x68, 0x78, 0x8c,
+ 0xa0, 0xb9, 0xcd, 0x4c, 0x54, 0x68, 0x78, 0x8c, 0xa0, 0xb9,
+ 0xcd, 0x4c, 0x54, 0x68, 0x78, 0x8c, 0xa0, 0xb9, 0xcd, 0x20,
+ 0x20, 0x1c, 0x1a, 0x20, 0x20, 0x1c, 0x1a, 0x20, 0x20, 0x1c,
+ 0x1a, 0x20, 0x20, 0x1a, 0x18, 0x20, 0x20, 0x1a, 0x18, 0x20,
+ 0x20, 0x18, 0x16, 0x1e, 0x1e, 0x18, 0x16, 0x1e, 0x1e, 0x18,
+ 0x16, 0x20, 0x20, 0x20, 0x20, 0x1c, 0x1a, 0x20, 0x1c, 0x1a,
+ 0x18, 0x18, 0x18, 0x16, 0x16, 0x20, 0x20, 0x20, 0x20, 0x1c,
+ 0x1a, 0x20, 0x1c, 0x1a, 0x18, 0x18, 0x18, 0x16, 0x16, 0x20,
+ 0x20, 0x20, 0x20, 0x1c, 0x1a, 0x20, 0x1c, 0x1a, 0x18, 0x18,
+ 0x18, 0x16, 0x16, 0x20, 0x20, 0x20, 0x20, 0x1c, 0x1a, 0x20,
+ 0x1a, 0x18, 0x16, 0x16, 0x16, 0x14, 0x14, 0x20, 0x20, 0x20,
+ 0x20, 0x1c, 0x1a, 0x20, 0x1a, 0x18, 0x16, 0x14, 0x12, 0x10,
+ 0x10, 0x20, 0x20, 0x20, 0x20, 0x1c, 0x1a, 0x20, 0x18, 0x14,
+ 0x10, 0x12, 0x10, 0x0e, 0x0e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1c,
+ 0x1a, 0x1e, 0x18, 0x14, 0x10, 0x12, 0x10, 0x0e, 0x0e, 0x1e,
+ 0x1e, 0x1e, 0x1e, 0x1c, 0x1a, 0x1e, 0x18, 0x14, 0x10, 0x12,
+ 0x10, 0x0e, 0x0e, 0x20, 0x20, 0x20, 0x1e, 0x1c, 0x1a, 0x1e,
+ 0x1c, 0x1a, 0x18, 0x18, 0x18, 0x16, 0x16, 0x20, 0x20, 0x20,
+ 0x1e, 0x1c, 0x1a, 0x1e, 0x1c, 0x1a, 0x18, 0x18, 0x18, 0x16,
+ 0x16, 0x20, 0x20, 0x20, 0x1e, 0x1c, 0x1a, 0x1e, 0x1c, 0x1a,
+ 0x18, 0x18, 0x18, 0x16, 0x16, 0x20, 0x20, 0x20, 0x1e, 0x1c,
+ 0x1a, 0x1e, 0x1a, 0x18, 0x16, 0x16, 0x16, 0x14, 0x14, 0x20,
+ 0x20, 0x20, 0x1e, 0x1c, 0x1a, 0x1e, 0x1a, 0x18, 0x16, 0x14,
+ 0x12, 0x10, 0x10, 0x20, 0x20, 0x20, 0x1e, 0x1c, 0x1a, 0x1e,
+ 0x16, 0x14, 0x10, 0x12, 0x10, 0x0e, 0x0e, 0x1e, 0x1e, 0x1e,
+ 0x1e, 0x1c, 0x1a, 0x1e, 0x16, 0x14, 0x10, 0x12, 0x10, 0x0e,
+ 0x0e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1c, 0x1a, 0x1e, 0x16, 0x14,
+ 0x10, 0x12, 0x10, 0x0e, 0x0e, 0x10, 0x16, 0x18, 0x40, 0x46,
+ 0x48, 0x30, 0x36, 0x38, 0x4c, 0x5c, 0x60, 0x8c, 0xa0, 0xb4,
+ 0xbd, 0xcd, 0x4c, 0x5c, 0x60, 0x8c, 0x90, 0xb4, 0xbd, 0xcd,
+ 0x4e, 0x56, 0x5e, 0x66, 0x8e, 0x96, 0xae, 0xbf, 0x4c, 0x50,
+ 0x5c, 0x68, 0x8c, 0xb4, 0xff, 0xff, 0x4c, 0x5c, 0x8c, 0xb4,
+ 0xff, 0xff, 0xff, 0xff, 0x4e, 0x5e, 0x66, 0x8e, 0x9e, 0xae,
+ 0xff, 0xff, 0x4c, 0x50, 0x54, 0x5c, 0x8c, 0xa0, 0xb4, 0xbd,
+ 0x4c, 0x5c, 0x68, 0x8c, 0x98, 0xb4, 0xbd, 0xcd, 0x4e, 0x56,
+ 0x5e, 0x8e, 0x96, 0xae, 0xbf, 0xc7, 0x7c, 0x7c, 0x7c, 0x7c,
+ 0x7c, 0x7c, 0x7c, 0x3c, 0x7c, 0x7c, 0x7c, 0x7c, 0x7c, 0x7c,
+ 0x7c, 0x3c, 0x3c, 0x7c, 0x3c, 0x7c, 0x7c, 0x7c, 0x7c, 0x7c,
+ 0x3c, 0x7c, 0x7c, 0x3c, 0x7c, 0x3c, 0x3c, 0x3c, 0x7c, 0x7c,
+ 0x7c, 0x3c, 0x3c, 0x3c, 0x3c, 0x3c, 0x7c, 0x7c, 0x7c, 0x7c,
+ 0x7c, 0x3c, 0x3c, 0x3c, 0x7c, 0x7c, 0x7c, 0x7c, 0x7c, 0x7c,
+ 0x7c, 0x7c, 0x7c, 0x7c, 0x3c, 0x7c, 0x7c, 0x7c, 0x7c, 0x3c,
+ 0x7c, 0x3c, 0x7c, 0x7c, 0x7c, 0x7c, 0x3c, 0x7c
+};
+
+static const uint8_t ar9380_def_rom_x113[] = {
+ 0x02, 0x06, 0x00, 0x03, 0x7f, 0x00, 0x00, 0x00, 0x78, 0x31,
+ 0x31, 0x33, 0x2d, 0x30, 0x32, 0x33, 0x2d, 0x66, 0x30, 0x30,
+ 0x30, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x1f, 0x00, 0x77, 0x03, 0x00, 0x00, 0x00, 0x00, 0x05, 0x00,
+ 0x00, 0x00, 0x0d, 0x00, 0x06, 0x00, 0x08, 0xff, 0x21, 0x00,
+ 0x00, 0x00, 0x00, 0x10, 0x01, 0x00, 0x00, 0x44, 0x44, 0x04,
+ 0x00, 0x50, 0x01, 0x50, 0x01, 0x50, 0x01, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x19, 0x00, 0xa4, 0x00, 0x00, 0x00, 0x00,
+ 0xff, 0x00, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0e, 0x0e, 0x03, 0x00,
+ 0x2c, 0xe2, 0x00, 0x02, 0x0e, 0x1c, 0x80, 0xc0, 0x80, 0x0c,
+ 0x80, 0xc0, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x89,
+ 0xac, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0xac, 0x70, 0x89, 0xac,
+ 0x70, 0x89, 0xac, 0x70, 0x89, 0xac, 0x22, 0x22, 0x22, 0x22,
+ 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x20, 0x20, 0x22, 0x22,
+ 0x20, 0x20, 0x22, 0x22, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+ 0x20, 0x1c, 0x20, 0x20, 0x1e, 0x1c, 0x00, 0x00, 0x00, 0x00,
+ 0x20, 0x20, 0x20, 0x20, 0x20, 0x1c, 0x20, 0x20, 0x1e, 0x1c,
+ 0x00, 0x00, 0x00, 0x00, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1c,
+ 0x20, 0x20, 0x1e, 0x1c, 0x00, 0x00, 0x00, 0x00, 0x1e, 0x1e,
+ 0x1e, 0x1e, 0x1e, 0x1c, 0x1e, 0x1e, 0x1c, 0x1a, 0x00, 0x00,
+ 0x00, 0x00, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1c, 0x1e, 0x1e,
+ 0x1c, 0x1a, 0x00, 0x00, 0x00, 0x00, 0x1e, 0x1e, 0x1e, 0x1e,
+ 0x1e, 0x1c, 0x1e, 0x1e, 0x1c, 0x1a, 0x00, 0x00, 0x00, 0x00,
+ 0x11, 0x12, 0x15, 0x17, 0x41, 0x42, 0x45, 0x47, 0x31, 0x32,
+ 0x35, 0x37, 0x70, 0x75, 0x9d, 0xa2, 0x70, 0x75, 0xa2, 0xff,
+ 0x70, 0x75, 0xa2, 0xff, 0x7a, 0x7f, 0x93, 0x98, 0x70, 0x75,
+ 0xac, 0xb8, 0x70, 0x75, 0xac, 0x00, 0x70, 0x75, 0xac, 0x00,
+ 0x7a, 0x7f, 0x93, 0xa2, 0x70, 0x75, 0xac, 0x00, 0x70, 0x75,
+ 0xac, 0x00, 0x70, 0x75, 0xac, 0x00, 0x7a, 0x7f, 0x93, 0xa2,
+ 0x3c, 0x7c, 0x3c, 0x3c, 0x3c, 0x7c, 0x3c, 0x3c, 0x7c, 0x3c,
+ 0x3c, 0x7c, 0x7c, 0x3c, 0x00, 0x00, 0x3c, 0x7c, 0x3c, 0x3c,
+ 0x3c, 0x7c, 0x3c, 0x3c, 0x3c, 0x7c, 0x7c, 0x3c, 0x3c, 0x7c,
+ 0x3c, 0x3c, 0x3c, 0x7c, 0x3c, 0x3c, 0x3c, 0x7c, 0x3c, 0x3c,
+ 0x3c, 0x7c, 0x7c, 0x7c, 0x3c, 0x7c, 0x7c, 0x7c, 0x20, 0x02,
+ 0x00, 0x00, 0x11, 0x11, 0x01, 0x00, 0x50, 0x01, 0x50, 0x01,
+ 0x50, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x44, 0x00,
+ 0x8c, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x03, 0x03,
+ 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03,
+ 0x00, 0x0e, 0x0e, 0x03, 0x00, 0x2d, 0xe2, 0x00, 0x02, 0x0e,
+ 0x1c, 0xe0, 0xe0, 0xf0, 0x0c, 0xe0, 0xe0, 0xf0, 0x6c, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48,
+ 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x4c, 0x58, 0x68, 0x78, 0x8c, 0xa0, 0xbd,
+ 0xc5, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x4c, 0x54, 0x68, 0x78, 0x8c,
+ 0xa0, 0xbd, 0xc5, 0x4c, 0x58, 0x68, 0x78, 0x8c, 0xb4, 0xbd,
+ 0xcd, 0x4e, 0x56, 0x68, 0x7a, 0x8e, 0xae, 0xbf, 0xcd, 0x2a,
+ 0x28, 0x28, 0x22, 0x2a, 0x28, 0x28, 0x22, 0x2a, 0x28, 0x28,
+ 0x22, 0x2a, 0x28, 0x28, 0x22, 0x2a, 0x28, 0x28, 0x22, 0x2a,
+ 0x28, 0x28, 0x22, 0x2a, 0x28, 0x28, 0x22, 0x2a, 0x28, 0x28,
+ 0x22, 0x28, 0x28, 0x28, 0x28, 0x20, 0x1c, 0x28, 0x28, 0x20,
+ 0x1c, 0x28, 0x28, 0x20, 0x14, 0x28, 0x28, 0x28, 0x28, 0x20,
+ 0x1c, 0x28, 0x28, 0x20, 0x1c, 0x28, 0x28, 0x20, 0x14, 0x28,
+ 0x28, 0x28, 0x28, 0x20, 0x1c, 0x28, 0x28, 0x20, 0x1c, 0x28,
+ 0x28, 0x20, 0x14, 0x28, 0x28, 0x28, 0x28, 0x20, 0x1c, 0x28,
+ 0x28, 0x20, 0x1c, 0x28, 0x28, 0x20, 0x14, 0x28, 0x28, 0x28,
+ 0x28, 0x20, 0x1c, 0x28, 0x28, 0x20, 0x1c, 0x28, 0x28, 0x20,
+ 0x14, 0x28, 0x28, 0x28, 0x28, 0x20, 0x1c, 0x28, 0x28, 0x20,
+ 0x1c, 0x28, 0x28, 0x20, 0x14, 0x26, 0x26, 0x26, 0x26, 0x20,
+ 0x1c, 0x26, 0x26, 0x20, 0x1c, 0x26, 0x26, 0x20, 0x1a, 0x24,
+ 0x24, 0x24, 0x24, 0x20, 0x1c, 0x24, 0x24, 0x20, 0x1c, 0x24,
+ 0x24, 0x20, 0x1a, 0x28, 0x28, 0x28, 0x26, 0x1e, 0x1a, 0x28,
+ 0x28, 0x1e, 0x1a, 0x28, 0x28, 0x1e, 0x18, 0x28, 0x28, 0x28,
+ 0x26, 0x1e, 0x1a, 0x28, 0x28, 0x1e, 0x1a, 0x28, 0x28, 0x1e,
+ 0x18, 0x28, 0x28, 0x28, 0x26, 0x1e, 0x1a, 0x28, 0x28, 0x1e,
+ 0x1a, 0x28, 0x28, 0x1e, 0x18, 0x28, 0x28, 0x28, 0x26, 0x1e,
+ 0x1a, 0x28, 0x28, 0x1e, 0x1a, 0x28, 0x28, 0x1e, 0x18, 0x28,
+ 0x28, 0x28, 0x26, 0x1e, 0x1a, 0x28, 0x28, 0x1e, 0x1a, 0x28,
+ 0x28, 0x1e, 0x18, 0x28, 0x28, 0x28, 0x26, 0x1e, 0x1a, 0x28,
+ 0x28, 0x1e, 0x1a, 0x28, 0x28, 0x1e, 0x18, 0x24, 0x24, 0x24,
+ 0x24, 0x1e, 0x1a, 0x24, 0x24, 0x1e, 0x1a, 0x24, 0x24, 0x1e,
+ 0x18, 0x22, 0x22, 0x22, 0x22, 0x1e, 0x1a, 0x22, 0x22, 0x1e,
+ 0x1a, 0x22, 0x22, 0x1e, 0x18, 0x10, 0x16, 0x18, 0x40, 0x46,
+ 0x48, 0x30, 0x36, 0x38, 0x4c, 0x5c, 0x60, 0x8c, 0xa0, 0xb4,
+ 0xbd, 0xcd, 0x4c, 0x5c, 0x60, 0x8c, 0x90, 0xb4, 0xbd, 0xcd,
+ 0x4e, 0x56, 0x5e, 0x66, 0x8e, 0x96, 0xae, 0xbf, 0x4c, 0x50,
+ 0x5c, 0x68, 0x8c, 0xb4, 0xff, 0xff, 0x4c, 0x5c, 0x8c, 0xb4,
+ 0xff, 0xff, 0xff, 0xff, 0x4e, 0x5e, 0x66, 0x8e, 0x9e, 0xae,
+ 0xff, 0xff, 0x4c, 0x50, 0x54, 0x5c, 0x8c, 0xa0, 0xb4, 0xbd,
+ 0x4c, 0x5c, 0x68, 0x8c, 0x98, 0xb4, 0xbd, 0xcd, 0x4e, 0x56,
+ 0x5e, 0x8e, 0x96, 0xae, 0xbf, 0xc7, 0x7c, 0x7c, 0x7c, 0x7c,
+ 0x7c, 0x7c, 0x7c, 0x3c, 0x7c, 0x7c, 0x7c, 0x7c, 0x7c, 0x7c,
+ 0x7c, 0x3c, 0x3c, 0x7c, 0x3c, 0x7c, 0x7c, 0x7c, 0x7c, 0x7c,
+ 0x3c, 0x7c, 0x7c, 0x3c, 0x7c, 0x3c, 0x3c, 0x3c, 0x7c, 0x7c,
+ 0x7c, 0x3c, 0x3c, 0x3c, 0x3c, 0x3c, 0x7c, 0x7c, 0x7c, 0x7c,
+ 0x7c, 0x3c, 0x3c, 0x3c, 0x7c, 0x7c, 0x7c, 0x7c, 0x7c, 0x7c,
+ 0x7c, 0x7c, 0x7c, 0x7c, 0x3c, 0x7c, 0x7c, 0x7c, 0x7c, 0x3c,
+ 0x7c, 0x3c, 0x7c, 0x7c, 0x7c, 0x7c, 0x3c, 0x7c
+};
+
+static const uint8_t *ar9380_rom_templates[] = {
+ ar9380_def_rom,
+ ar9380_def_rom_h112,
+ ar9380_def_rom_h116,
+ ar9380_def_rom_x112,
+ ar9380_def_rom_x113
+};
+
+/* Macro to "pack" registers to 16-bit to save some .rodata space. */
+#define P(x) ((x) >> 2)
+
+/*
+ * AR9380 2.2 programming.
+ */
+static const uint16_t ar9380_2_2_regs[] = {
+ P(0x07010), P(0x01030), P(0x01070), P(0x010b0), P(0x08014),
+ P(0x0801c), P(0x08120), P(0x081d0), P(0x08318), P(0x1609c),
+ P(0x160ac), P(0x160b0), P(0x1610c), P(0x16140), P(0x1650c),
+ P(0x16540), P(0x1690c), P(0x16940), P(0x09810), P(0x09820),
+ P(0x09824), P(0x09828), P(0x0982c), P(0x09830), P(0x09c00),
+ P(0x09e00), P(0x09e04), P(0x09e0c), P(0x09e10), P(0x09e14),
+ P(0x09e18), P(0x09e1c), P(0x09e20), P(0x09e2c), P(0x09e3c),
+ P(0x09e44), P(0x09e48), P(0x09fc8), P(0x0a204), P(0x0a208),
+ P(0x0a22c), P(0x0a230), P(0x0a234), P(0x0a238), P(0x0a250),
+ P(0x0a254), P(0x0a258), P(0x0a25c), P(0x0a260), P(0x0a264),
+ P(0x0a280), P(0x0a284), P(0x0a288), P(0x0a28c), P(0x0a2c4),
+ P(0x0a2d0), P(0x0a2d8), P(0x0a358), P(0x0a830), P(0x0ae04),
+ P(0x0ae18), P(0x0ae1c), P(0x0ae20), P(0x0b284), P(0x0b830),
+ P(0x0be04), P(0x0be18), P(0x0be1c), P(0x0be20), P(0x0c284)
+};
+
+static const uint32_t ar9380_2_2_vals_5g20[] = {
+ 0x00000023, 0x00000230, 0x00000168, 0x00000e60, 0x03e803e8,
+ 0x128d8027, 0x08f04800, 0x00003210, 0x00003e80, 0x0dd08f29,
+ 0xa4653c00, 0x03284f3e, 0x08000000, 0x10804008, 0x08000000,
+ 0x10804008, 0x08000000, 0x10804008, 0xd00a8005, 0x206a022e,
+ 0x5ac640d0, 0x06903081, 0x05eea6d4, 0x0000059c, 0x000000c4,
+ 0x0372111a, 0x001c2020, 0x6c4000e2, 0x7ec88d2e, 0x37b95d5e,
+ 0x00000000, 0x0001cf9c, 0x000003b5, 0x0000001c, 0xcf946220,
+ 0x02321e27, 0x5030201a, 0x0003f000, 0x000037c0, 0x00000104,
+ 0x01026a2f, 0x0000000a, 0x00000fff, 0xffb81018, 0x00000000,
+ 0x000007d0, 0x02020002, 0x01000e0e, 0x0a021501, 0x00000e0e,
+ 0x00000007, 0x00000000, 0x00000110, 0x00022222, 0x00158d18,
+ 0x00071981, 0x7999a83a, 0x00000000, 0x0000019c, 0x001c0000,
+ 0x00000000, 0x0000019c, 0x000001b5, 0x00000000, 0x0000019c,
+ 0x001c0000, 0x00000000, 0x0000019c, 0x000001b5, 0x00000000
+};
+
+#ifndef IEEE80211_NO_HT
+static const uint32_t ar9380_2_2_vals_5g40[] = {
+ 0x00000023, 0x00000460, 0x000002d0, 0x00001cc0, 0x07d007d0,
+ 0x128d804f, 0x08f04800, 0x00003210, 0x00007d00, 0x0dd08f29,
+ 0xa4653c00, 0x03284f3e, 0x00000000, 0x10804008, 0x00000000,
+ 0x10804008, 0x00000000, 0x10804008, 0xd00a8005, 0x206a022e,
+ 0x5ac640d0, 0x06903081, 0x05eea6d4, 0x0000059c, 0x000000c4,
+ 0x0372111a, 0x001c2020, 0x6d4000e2, 0x7ec88d2e, 0x37b9605e,
+ 0x00000000, 0x0001cf9c, 0x000003b5, 0x0000001c, 0xcf946220,
+ 0x02321e27, 0x5030201a, 0x0003f000, 0x000037c4, 0x00000104,
+ 0x01026a2f, 0x00000014, 0x10000fff, 0xffb81018, 0x00000000,
+ 0x00000fa0, 0x02020002, 0x01000e0e, 0x0a021501, 0x00000e0e,
+ 0x00000007, 0x00000000, 0x00000110, 0x00022222, 0x00158d18,
+ 0x00071981, 0x7999a83a, 0x00000000, 0x0000019c, 0x001c0000,
+ 0x00000000, 0x0000019c, 0x000001b5, 0x00000000, 0x0000019c,
+ 0x001c0000, 0x00000000, 0x0000019c, 0x000001b5, 0x00000000
+};
+
+static const uint32_t ar9380_2_2_vals_2g40[] = {
+ 0x00000023, 0x000002c0, 0x00000318, 0x00007c70, 0x10801600,
+ 0x12e00057, 0x08f04810, 0x0000320a, 0x00006880, 0x0b283f31,
+ 0x24652800, 0x05d08f20, 0x00000000, 0x50804008, 0x00000000,
+ 0x50804008, 0x00000000, 0x50804008, 0xd00a8011, 0x206a012e,
+ 0x5ac640d0, 0x06903881, 0x05eea6d4, 0x0000119c, 0x000000c4,
+ 0x037216a0, 0x001c2020, 0x6d4000e2, 0x7ec84d2e, 0x3379605e,
+ 0x00000000, 0x00021f9c, 0x000003ce, 0x00000021, 0xcf946222,
+ 0x02291e27, 0x50302012, 0x0001a000, 0x000037c4, 0x00000004,
+ 0x01026a2f, 0x00000016, 0x10000fff, 0xffb81018, 0x00000210,
+ 0x00001130, 0x02020002, 0x01000e0e, 0x3a021501, 0x00000e0e,
+ 0x0000000b, 0x00000150, 0x00000110, 0x00022222, 0x00158d18,
+ 0x00071981, 0x7999a83a, 0x00000000, 0x0000019c, 0x001c0000,
+ 0x00000000, 0x0000019c, 0x000001ce, 0x00000150, 0x0000019c,
+ 0x001c0000, 0x00000000, 0x0000019c, 0x000001ce, 0x00000150
+};
+#endif
+
+static const uint32_t ar9380_2_2_vals_2g20[] = {
+ 0x00000023, 0x00000160, 0x0000018c, 0x00003e38, 0x08400b00,
+ 0x12e0002b, 0x08f04810, 0x0000320a, 0x00003440, 0x0b283f31,
+ 0x24652800, 0x05d08f20, 0x00000000, 0x50804008, 0x00000000,
+ 0x50804008, 0x00000000, 0x50804008, 0xd00a8011, 0x206a012e,
+ 0x5ac640d0, 0x06903881, 0x05eea6d4, 0x0000119c, 0x000000c4,
+ 0x037216a0, 0x001c2020, 0x6c4000e2, 0x7ec84d2e, 0x33795d5e,
+ 0x00000000, 0x00021f9c, 0x000003ce, 0x00000021, 0xcf946222,
+ 0x02291e27, 0x50302012, 0x0001a000, 0x000037c0, 0x00000004,
+ 0x01026a2f, 0x0000000b, 0x00000fff, 0xffb81018, 0x00000108,
+ 0x00000898, 0x02020002, 0x01000e0e, 0x3a021501, 0x00000e0e,
+ 0x0000000b, 0x00000150, 0x00000110, 0x00022222, 0x00158d18,
+ 0x00071982, 0x7999a83a, 0x00000000, 0x0000019c, 0x001c0000,
+ 0x00000000, 0x0000019c, 0x000001ce, 0x00000150, 0x0000019c,
+ 0x001c0000, 0x00000000, 0x0000019c, 0x000001ce, 0x00000150
+};
+
+static const uint16_t ar9380_2_2_cm_regs[] = {
+ P(0x040a4), P(0x07008), P(0x07020), P(0x07034), P(0x07038),
+ P(0x07048), P(0x00008), P(0x00030), P(0x00034), P(0x00040),
+ P(0x00044), P(0x00048), P(0x0004c), P(0x00050), P(0x01040),
+ P(0x01044), P(0x01048), P(0x0104c), P(0x01050), P(0x01054),
+ P(0x01058), P(0x0105c), P(0x01060), P(0x01064), P(0x010f0),
+ P(0x01270), P(0x012b0), P(0x012f0), P(0x0143c), P(0x0147c),
+ P(0x08000), P(0x08004), P(0x08008), P(0x0800c), P(0x08018),
+ P(0x08020), P(0x08038), P(0x0803c), P(0x08040), P(0x08044),
+ P(0x08048), P(0x0804c), P(0x08054), P(0x08058), P(0x0805c),
+ P(0x08060), P(0x08064), P(0x08070), P(0x08074), P(0x08078),
+ P(0x0809c), P(0x080a0), P(0x080a4), P(0x080a8), P(0x080ac),
+ P(0x080b0), P(0x080b4), P(0x080b8), P(0x080bc), P(0x080c0),
+ P(0x080c4), P(0x080c8), P(0x080cc), P(0x080d0), P(0x080d4),
+ P(0x080d8), P(0x080dc), P(0x080e0), P(0x080e4), P(0x080e8),
+ P(0x080ec), P(0x080f0), P(0x080f4), P(0x080fc), P(0x08100),
+ P(0x08108), P(0x0810c), P(0x08110), P(0x08114), P(0x08118),
+ P(0x0811c), P(0x08124), P(0x08128), P(0x0812c), P(0x08130),
+ P(0x08134), P(0x08138), P(0x0813c), P(0x08144), P(0x08168),
+ P(0x0816c), P(0x081c0), P(0x081c4), P(0x081c8), P(0x081cc),
+ P(0x081ec), P(0x081f0), P(0x081f4), P(0x081f8), P(0x081fc),
+ P(0x08240), P(0x08244), P(0x08248), P(0x0824c), P(0x08250),
+ P(0x08254), P(0x08258), P(0x0825c), P(0x08260), P(0x08264),
+ P(0x08268), P(0x0826c), P(0x08270), P(0x08274), P(0x08278),
+ P(0x0827c), P(0x08284), P(0x08288), P(0x0828c), P(0x08294),
+ P(0x08298), P(0x0829c), P(0x08300), P(0x08314), P(0x0831c),
+ P(0x08328), P(0x0832c), P(0x08330), P(0x08334), P(0x08338),
+ P(0x0833c), P(0x08340), P(0x08344), P(0x08348), P(0x0835c),
+ P(0x08360), P(0x08364), P(0x08368), P(0x08370), P(0x08374),
+ P(0x08378), P(0x0837c), P(0x08380), P(0x08384), P(0x08390),
+ P(0x08394), P(0x08398), P(0x0839c), P(0x083a0), P(0x083a4),
+ P(0x083a8), P(0x083ac), P(0x083b0), P(0x083b4), P(0x083b8),
+ P(0x083bc), P(0x083c0), P(0x083c4), P(0x083c8), P(0x083cc),
+ P(0x083d0), P(0x09800), P(0x09804), P(0x09808), P(0x0980c),
+ P(0x09814), P(0x09818), P(0x0981c), P(0x09834), P(0x09838),
+ P(0x0983c), P(0x09880), P(0x09884), P(0x098a4), P(0x098b0),
+ P(0x098d0), P(0x098d4), P(0x098dc), P(0x098f0), P(0x098f4),
+ P(0x09c04), P(0x09c08), P(0x09c0c), P(0x09c10), P(0x09c14),
+ P(0x09c18), P(0x09c1c), P(0x09d00), P(0x09d04), P(0x09d08),
+ P(0x09d0c), P(0x09d10), P(0x09d14), P(0x09d18), P(0x09e08),
+ P(0x09e24), P(0x09e28), P(0x09e30), P(0x09e34), P(0x09e38),
+ P(0x09e40), P(0x09e4c), P(0x09e50), P(0x09e54), P(0x09fc0),
+ P(0x09fc4), P(0x09fcc), P(0x09fd0), P(0x0a20c), P(0x0a220),
+ P(0x0a224), P(0x0a228), P(0x0a23c), P(0x0a244), P(0x0a2a0),
+ P(0x0a2c0), P(0x0a2c8), P(0x0a2cc), P(0x0a2d4), P(0x0a2ec),
+ P(0x0a2f0), P(0x0a2f4), P(0x0a2f8), P(0x0a344), P(0x0a34c),
+ P(0x0a350), P(0x0a364), P(0x0a370), P(0x0a390), P(0x0a394),
+ P(0x0a398), P(0x0a39c), P(0x0a3a0), P(0x0a3a4), P(0x0a3a8),
+ P(0x0a3ac), P(0x0a3c0), P(0x0a3c4), P(0x0a3c8), P(0x0a3cc),
+ P(0x0a3d0), P(0x0a3d4), P(0x0a3d8), P(0x0a3dc), P(0x0a3e0),
+ P(0x0a3e4), P(0x0a3e8), P(0x0a3ec), P(0x0a3f0), P(0x0a3f4),
+ P(0x0a3f8), P(0x0a3fc), P(0x0a400), P(0x0a404), P(0x0a408),
+ P(0x0a40c), P(0x0a414), P(0x0a418), P(0x0a41c), P(0x0a420),
+ P(0x0a424), P(0x0a428), P(0x0a42c), P(0x0a430), P(0x0a434),
+ P(0x0a438), P(0x0a43c), P(0x0a440), P(0x0a444), P(0x0a448),
+ P(0x0a44c), P(0x0a450), P(0x0a458), P(0x0a640), P(0x0a644),
+ P(0x0a648), P(0x0a64c), P(0x0a670), P(0x0a674), P(0x0a678),
+ P(0x0a67c), P(0x0a680), P(0x0a684), P(0x0a688), P(0x0a690),
+ P(0x0a7c0), P(0x0a7c4), P(0x0a7c8), P(0x0a7cc), P(0x0a7d0),
+ P(0x0a7d4), P(0x0a7dc), P(0x0a8d0), P(0x0a8d4), P(0x0a8dc),
+ P(0x0a8f0), P(0x0a8f4), P(0x0b2d0), P(0x0b2d4), P(0x0b2ec),
+ P(0x0b2f0), P(0x0b2f4), P(0x0b2f8), P(0x0b408), P(0x0b40c),
+ P(0x0b420), P(0x0b8d0), P(0x0b8d4), P(0x0b8dc), P(0x0b8f0),
+ P(0x0b8f4), P(0x0c2d0), P(0x0c2d4), P(0x0c2ec), P(0x0c2f0),
+ P(0x0c2f4), P(0x0c2f8), P(0x0c408), P(0x0c40c), P(0x0c420),
+ P(0x16000), P(0x16004), P(0x16008), P(0x1600c), P(0x16040),
+ P(0x1604c), P(0x16050), P(0x16054), P(0x16058), P(0x1605c),
+ P(0x16060), P(0x16064), P(0x1606c), P(0x16080), P(0x16084),
+ P(0x16088), P(0x1608c), P(0x16090), P(0x16098), P(0x160a0),
+ P(0x160a4), P(0x160a8), P(0x160b4), P(0x160c0), P(0x160c4),
+ P(0x160c8), P(0x160cc), P(0x16100), P(0x16104), P(0x16108),
+ P(0x16144), P(0x16148), P(0x16280), P(0x16284), P(0x16288),
+ P(0x1628c), P(0x16290), P(0x16294), P(0x16380), P(0x16384),
+ P(0x16388), P(0x1638c), P(0x16390), P(0x16394), P(0x16398),
+ P(0x1639c), P(0x163a0), P(0x163a4), P(0x163a8), P(0x163ac),
+ P(0x163b0), P(0x163b4), P(0x163b8), P(0x163bc), P(0x163c0),
+ P(0x163c4), P(0x163c8), P(0x163cc), P(0x163d0), P(0x163d4),
+ P(0x16400), P(0x16404), P(0x16408), P(0x1640c), P(0x16440),
+ P(0x1644c), P(0x16450), P(0x16454), P(0x16458), P(0x1645c),
+ P(0x16460), P(0x16464), P(0x1646c), P(0x16500), P(0x16504),
+ P(0x16508), P(0x16544), P(0x16548), P(0x16780), P(0x16784),
+ P(0x16788), P(0x1678c), P(0x16790), P(0x16794), P(0x16798),
+ P(0x1679c), P(0x167a0), P(0x167a4), P(0x167a8), P(0x167ac),
+ P(0x167b0), P(0x167b4), P(0x167b8), P(0x167bc), P(0x167c0),
+ P(0x167c4), P(0x167c8), P(0x167cc), P(0x167d0), P(0x167d4),
+ P(0x16800), P(0x16804), P(0x16808), P(0x1680c), P(0x16840),
+ P(0x1684c), P(0x16850), P(0x16854), P(0x16858), P(0x1685c),
+ P(0x16860), P(0x16864), P(0x1686c), P(0x16900), P(0x16904),
+ P(0x16908), P(0x16944), P(0x16948), P(0x16b80), P(0x16b84),
+ P(0x16b88), P(0x16b8c), P(0x16b90), P(0x16b94), P(0x16b98),
+ P(0x16b9c), P(0x16ba0), P(0x16ba4), P(0x16ba8), P(0x16bac),
+ P(0x16bb0), P(0x16bb4), P(0x16bb8), P(0x16bbc), P(0x16bc0),
+ P(0x16bc4), P(0x16bc8), P(0x16bcc), P(0x16bd0), P(0x16bd4)
+};
+
+static const uint32_t ar9380_2_2_cm_vals[] = {
+ 0x00a0c1c9, 0x00000000, 0x00000000, 0x00000002, 0x000004c2,
+ 0x00000008, 0x00000000, 0x00020085, 0x00000005, 0x00000000,
+ 0x00000000, 0x00000008, 0x00000010, 0x00000000, 0x002ffc0f,
+ 0x002ffc0f, 0x002ffc0f, 0x002ffc0f, 0x002ffc0f, 0x002ffc0f,
+ 0x002ffc0f, 0x002ffc0f, 0x002ffc0f, 0x002ffc0f, 0x00000100,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x000fc78f,
+ 0x0000000f, 0x00000000, 0x00000310, 0x00000020, 0x00000000,
+ 0x0000000f, 0x00000000, 0x02ff0000, 0x0e070605, 0x0000000d,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x2a800000,
+ 0x06900168, 0x13881c20, 0x01f40000, 0x00252500, 0x00a00000,
+ 0x00400000, 0x00000000, 0xffffffff, 0x0000ffff, 0x3f3f3f3f,
+ 0x00000000, 0x00000000, 0x00000000, 0x00020000, 0x00000000,
+ 0x00000052, 0x00000000, 0x00000000, 0x000007ff, 0x000000aa,
+ 0x00003210, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x0000ffff, 0xffffffff, 0x00000000,
+ 0x00000000, 0x00000000, 0x33332210, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00100000, 0x0010f424, 0x00000800, 0x0001e848, 0x00000000,
+ 0x00000000, 0x00000000, 0x40000000, 0x00080922, 0x9bc00010,
+ 0xffffffff, 0x0000ffff, 0x00000000, 0x40000000, 0x003e4180,
+ 0x00000004, 0x0000002c, 0x0000002c, 0x000000ff, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000140, 0x00000000, 0x0000010d,
+ 0x00000000, 0x00000007, 0x00000302, 0x00000700, 0x00ff0000,
+ 0x02400000, 0x000107ff, 0xaa48105b, 0x008f0000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0x00000000, 0x00000000, 0x000000ff,
+ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x0000fa14,
+ 0x000f0c00, 0x33332210, 0x33332210, 0x33332210, 0x33332210,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000200,
+ 0x000301ff, 0xafe68e30, 0xfd14e000, 0x9c0a9f6b, 0x04900000,
+ 0x9280c00a, 0x00000000, 0x00020028, 0x6400a290, 0x0108ecff,
+ 0x0d000600, 0x201fff00, 0x00001042, 0x00200400, 0x32840bbe,
+ 0x004b6a8e, 0x00000820, 0x00000000, 0x00000000, 0x00000000,
+ 0xff55ff55, 0x0320ff55, 0x00000000, 0x00000000, 0x00046384,
+ 0x05b6b440, 0x00b6b440, 0xc080a333, 0x40206c10, 0x009c4060,
+ 0x9883800a, 0x01834061, 0x00c0040b, 0x00000000, 0x0038230c,
+ 0x990bb515, 0x0c6f0000, 0x06336f77, 0x6af6532f, 0x0cc80c00,
+ 0x0d261820, 0x00001004, 0x00ff03f1, 0x00000000, 0x803e4788,
+ 0x0001efb5, 0x40000014, 0x01193b93, 0x00000000, 0x00000000,
+ 0x00000000, 0x10002310, 0x00000000, 0x0c000000, 0x00000001,
+ 0x00000001, 0x00000000, 0x18c43433, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x0000a000, 0x00000000, 0x00000000, 0x00000001, 0x00000444,
+ 0x001f0e0f, 0x0075393f, 0xb79f6427, 0x00000000, 0xaaaaaaaa,
+ 0x3c466478, 0x20202020, 0x22222220, 0x20200020, 0x20202020,
+ 0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020,
+ 0x20202020, 0x20202020, 0x20202020, 0x00000000, 0x00000246,
+ 0x0cdbd380, 0x000f0f01, 0x8fa91f01, 0x00000000, 0x0e79e5c6,
+ 0x00820820, 0x1ce739ce, 0x2d001dce, 0x1ce739ce, 0x000001ce,
+ 0x1ce739ce, 0x000001ce, 0x1ce739ce, 0x1ce739ce, 0x00000000,
+ 0x00001801, 0x00100000, 0x00000000, 0x00000000, 0x06000080,
+ 0x00000001, 0x00010000, 0x00000000, 0x00000000, 0x3fad9d74,
+ 0x0048060a, 0x00003c37, 0x03020100, 0x09080504, 0x0d0c0b0a,
+ 0x13121110, 0x31301514, 0x35343332, 0x00000036, 0x00000838,
+ 0x00000000, 0xfffffffc, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000004, 0x00000001, 0x004b6a8e, 0x00000820, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000080, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x0e79e5c0, 0x00820820,
+ 0x00000000, 0x004b6a8e, 0x00000820, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x0e79e5c0, 0x00820820, 0x00000000,
+ 0x36db6db6, 0x6db6db40, 0x73f00000, 0x00000000, 0x7f80fff8,
+ 0x76d005b5, 0x556cf031, 0x13449440, 0x0c51c92c, 0x3db7fffc,
+ 0xfffffffc, 0x000f0278, 0x6db60000, 0x00000000, 0x0e48048c,
+ 0x54214514, 0x119f481e, 0x24926490, 0xd2888888, 0x0a108ffe,
+ 0x812fc370, 0x423c8000, 0x92480080, 0x00adb6d0, 0x6db6db60,
+ 0x6db6db6c, 0x01e6c000, 0x3fffbe01, 0xfff80000, 0x00080010,
+ 0x02084080, 0x00000000, 0x058a0001, 0x3d840208, 0x05a20408,
+ 0x00038c07, 0x00000004, 0x458aa14f, 0x00000000, 0x00000000,
+ 0x00800700, 0x00800700, 0x00800700, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000001, 0x00000001, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000000a0,
+ 0x000c0000, 0x14021402, 0x00001402, 0x00000000, 0x00000000,
+ 0x36db6db6, 0x6db6db40, 0x73f00000, 0x00000000, 0x7f80fff8,
+ 0x76d005b5, 0x556cf031, 0x13449440, 0x0c51c92c, 0x3db7fffc,
+ 0xfffffffc, 0x000f0278, 0x6db60000, 0x3fffbe01, 0xfff80000,
+ 0x00080010, 0x02084080, 0x00000000, 0x00000000, 0x00000000,
+ 0x00800700, 0x00800700, 0x00800700, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000001, 0x00000001, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000000a0,
+ 0x000c0000, 0x14021402, 0x00001402, 0x00000000, 0x00000000,
+ 0x36db6db6, 0x6db6db40, 0x73f00000, 0x00000000, 0x7f80fff8,
+ 0x76d005b5, 0x556cf031, 0x13449440, 0x0c51c92c, 0x3db7fffc,
+ 0xfffffffc, 0x000f0278, 0x6db60000, 0x3fffbe01, 0xfff80000,
+ 0x00080010, 0x02084080, 0x00000000, 0x00000000, 0x00000000,
+ 0x00800700, 0x00800700, 0x00800700, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000001, 0x00000001, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000000a0,
+ 0x000c0000, 0x14021402, 0x00001402, 0x00000000, 0x00000000
+};
+
+static const uint16_t ar9380_2_2_fast_clock_regs[] = {
+ P(0x01030), P(0x01070), P(0x010b0), P(0x08014), P(0x0801c),
+ P(0x08318), P(0x09e00), P(0x0a230), P(0x0a254)
+};
+
+static const uint32_t ar9380_2_2_fast_clock_vals_5g20[] = {
+ 0x00000268, 0x0000018c, 0x00000fd0, 0x044c044c, 0x148ec02b,
+ 0x000044c0, 0x0372131c, 0x0000000b, 0x00000898
+};
+
+#ifndef IEEE80211_NO_HT
+static const uint32_t ar9380_2_2_fast_clock_vals_5g40[] = {
+ 0x000004d0, 0x00000318, 0x00001fa0, 0x08980898, 0x148ec057,
+ 0x00008980, 0x0372131c, 0x00000016, 0x00001130
+};
+#endif
+
+static const struct athn_ini ar9380_2_2_ini = {
+ .nregs = __arraycount(ar9380_2_2_regs),
+ .regs = ar9380_2_2_regs,
+ .vals_5g20 = ar9380_2_2_vals_5g20,
+#ifndef IEEE80211_NO_HT
+ .vals_5g40 = ar9380_2_2_vals_5g40,
+ .vals_2g40 = ar9380_2_2_vals_2g40,
+#endif
+ .vals_2g20 = ar9380_2_2_vals_2g20,
+ .ncmregs = __arraycount(ar9380_2_2_cm_regs),
+ .cmregs = ar9380_2_2_cm_regs,
+ .cmvals = ar9380_2_2_cm_vals,
+ .nfastregs = __arraycount(ar9380_2_2_fast_clock_regs),
+ .fastregs = ar9380_2_2_fast_clock_regs,
+ .fastvals_5g20 = ar9380_2_2_fast_clock_vals_5g20,
+#ifndef IEEE80211_NO_HT
+ .fastvals_5g50 = ar9380_2_2_fast_clock_vals_5g40
+#endif
+};
+
+/*
+ * AR9485 1.1 programming.
+ */
+
+static const uint16_t ar9485_1_1_regs[] = {
+ P(0x01030), P(0x01070), P(0x010b0), P(0x08014), P(0x0801c),
+ P(0x08120), P(0x081d0), P(0x08318), P(0x09810), P(0x09820),
+ P(0x09824), P(0x09828), P(0x0982c), P(0x09830), P(0x09c00),
+ P(0x09e00), P(0x09e04), P(0x09e0c), P(0x09e10), P(0x09e14),
+ P(0x09e18), P(0x09e1c), P(0x09e20), P(0x09e2c), P(0x09e3c),
+ P(0x09e44), P(0x09e48), P(0x09fc8), P(0x0a204), P(0x0a208),
+ P(0x0a230), P(0x0a234), P(0x0a238), P(0x0a250), P(0x0a254),
+ P(0x0a258), P(0x0a25c), P(0x0a260), P(0x0a264), P(0x0a280),
+ P(0x0a284), P(0x0a288), P(0x0a28c), P(0x0a2c4), P(0x0a2d0),
+ P(0x0a2d8), P(0x0a358), P(0x0be04), P(0x0be18), P(0x1609c),
+ P(0x160ac), P(0x160b0), P(0x1610c), P(0x16140)
+};
+
+static const uint32_t ar9485_1_1_vals_2g40[] = {
+ 0x000002c0, 0x00000318, 0x00007c70, 0x10801600, 0x12e00057,
+ 0x08f04810, 0x0000320a, 0x00006880, 0xd00a8005, 0x206a002e,
+ 0x5ac640d0, 0x06903881, 0x05eea6d4, 0x0000059c, 0x00000044,
+ 0x037216a0, 0x00182020, 0x6d4000e2, 0x7ec80d2e, 0x3139605e,
+ 0x00000000, 0x00021f9c, 0x000003ce, 0x00000021, 0xcf946222,
+ 0x02282324, 0x50302010, 0x0001a000, 0x01303fc4, 0x00000004,
+ 0x00004016, 0x10000fff, 0xffb81018, 0x00000210, 0x00001130,
+ 0x02020002, 0x01000e0e, 0x3a021501, 0x00000e0e, 0x0000000b,
+ 0x000002a0, 0x00000000, 0x00000000, 0x00158d18, 0x00071982,
+ 0xf999a83a, 0x00000000, 0x00802020, 0x00000000, 0x0b283f31,
+ 0x24611800, 0x03284f3e, 0x00170000, 0x50804008
+};
+
+static const uint32_t ar9485_1_1_vals_2g20[] = {
+ 0x00000160, 0x0000018c, 0x00003e38, 0x08400b00, 0x12e0002b,
+ 0x08f04810, 0x0000320a, 0x00003440, 0xd00a8005, 0x206a002e,
+ 0x5ac640d0, 0x06903881, 0x05eea6d4, 0x0000059c, 0x00000044,
+ 0x037216a0, 0x00182020, 0x6c4000e2, 0x7ec80d2e, 0x31395d5e,
+ 0x00000000, 0x00021f9c, 0x000003ce, 0x00000021, 0xcf946222,
+ 0x02282324, 0x50302010, 0x0001a000, 0x01303fc0, 0x00000004,
+ 0x0000400b, 0x10000fff, 0xffb81018, 0x00000108, 0x00000898,
+ 0x02020002, 0x01000e0e, 0x3a021501, 0x00000e0e, 0x0000000b,
+ 0x000002a0, 0x00000000, 0x00000000, 0x00158d18, 0x00071982,
+ 0xf999a83a, 0x00000000, 0x00802020, 0x00000000, 0x0b283f31,
+ 0x24611800, 0x03284f3e, 0x00170000, 0x50804008
+};
+
+static const uint16_t ar9485_1_1_cm_regs[] = {
+ P(0x00008), P(0x00030), P(0x00034), P(0x00040), P(0x00044),
+ P(0x00048), P(0x0004c), P(0x00050), P(0x01040), P(0x01044),
+ P(0x01048), P(0x0104c), P(0x01050), P(0x01054), P(0x01058),
+ P(0x0105c), P(0x01060), P(0x01064), P(0x010f0), P(0x01270),
+ P(0x012b0), P(0x012f0), P(0x0143c), P(0x0147c), P(0x08000),
+ P(0x08004), P(0x08008), P(0x0800c), P(0x08018), P(0x08020),
+ P(0x08038), P(0x0803c), P(0x08040), P(0x08044), P(0x08048),
+ P(0x0804c), P(0x08054), P(0x08058), P(0x0805c), P(0x08060),
+ P(0x08064), P(0x08070), P(0x08074), P(0x08078), P(0x0809c),
+ P(0x080a0), P(0x080a4), P(0x080a8), P(0x080ac), P(0x080b0),
+ P(0x080b4), P(0x080b8), P(0x080bc), P(0x080c0), P(0x080c4),
+ P(0x080c8), P(0x080cc), P(0x080d0), P(0x080d4), P(0x080d8),
+ P(0x080dc), P(0x080e0), P(0x080e4), P(0x080e8), P(0x080ec),
+ P(0x080f0), P(0x080f4), P(0x080fc), P(0x08100), P(0x08108),
+ P(0x0810c), P(0x08110), P(0x08114), P(0x08118), P(0x0811c),
+ P(0x08124), P(0x08128), P(0x0812c), P(0x08130), P(0x08134),
+ P(0x08138), P(0x0813c), P(0x08144), P(0x08168), P(0x0816c),
+ P(0x08170), P(0x08174), P(0x08178), P(0x0817c), P(0x081c0),
+ P(0x081c4), P(0x081d4), P(0x081ec), P(0x081f0), P(0x081f4),
+ P(0x081f8), P(0x081fc), P(0x08240), P(0x08244), P(0x08248),
+ P(0x0824c), P(0x08250), P(0x08254), P(0x08258), P(0x0825c),
+ P(0x08260), P(0x08264), P(0x08268), P(0x0826c), P(0x08270),
+ P(0x08274), P(0x08278), P(0x0827c), P(0x08284), P(0x08288),
+ P(0x0828c), P(0x08294), P(0x08298), P(0x0829c), P(0x08300),
+ P(0x08314), P(0x0831c), P(0x08328), P(0x0832c), P(0x08330),
+ P(0x08334), P(0x08338), P(0x0833c), P(0x08340), P(0x08344),
+ P(0x08348), P(0x0835c), P(0x08360), P(0x08364), P(0x08368),
+ P(0x08370), P(0x08374), P(0x08378), P(0x0837c), P(0x08380),
+ P(0x08384), P(0x08390), P(0x08394), P(0x08398), P(0x0839c),
+ P(0x083a0), P(0x083a4), P(0x083a8), P(0x083ac), P(0x083b0),
+ P(0x083b4), P(0x083b8), P(0x083bc), P(0x083c0), P(0x083c4),
+ P(0x083c8), P(0x083cc), P(0x083d0), P(0x0a580), P(0x0a584),
+ P(0x0a588), P(0x0a58c), P(0x0a590), P(0x0a594), P(0x0a598),
+ P(0x0a59c), P(0x0a5a0), P(0x0a5a4), P(0x0a5a8), P(0x0a5ac),
+ P(0x0a5b0), P(0x0a5b4), P(0x0a5b8), P(0x0a5bc), P(0x09800),
+ P(0x09804), P(0x09808), P(0x0980c), P(0x09814), P(0x09818),
+ P(0x0981c), P(0x09834), P(0x09838), P(0x0983c), P(0x09880),
+ P(0x09884), P(0x098a4), P(0x098b0), P(0x098d0), P(0x098d4),
+ P(0x098dc), P(0x098f0), P(0x098f4), P(0x09c04), P(0x09c08),
+ P(0x09c0c), P(0x09c10), P(0x09c14), P(0x09c18), P(0x09c1c),
+ P(0x09d00), P(0x09d04), P(0x09d08), P(0x09d0c), P(0x09d10),
+ P(0x09d14), P(0x09d18), P(0x09d1c), P(0x09e08), P(0x09e24),
+ P(0x09e28), P(0x09e30), P(0x09e34), P(0x09e38), P(0x09e40),
+ P(0x09e4c), P(0x09e50), P(0x09fc0), P(0x09fc4), P(0x09fcc),
+ P(0x0a20c), P(0x0a210), P(0x0a220), P(0x0a224), P(0x0a228),
+ P(0x0a23c), P(0x0a244), P(0x0a2a0), P(0x0a2c0), P(0x0a2c8),
+ P(0x0a2cc), P(0x0a2d4), P(0x0a2dc), P(0x0a2e0), P(0x0a2e4),
+ P(0x0a2e8), P(0x0a2ec), P(0x0a2f0), P(0x0a2f4), P(0x0a2f8),
+ P(0x0a344), P(0x0a34c), P(0x0a350), P(0x0a364), P(0x0a370),
+ P(0x0a390), P(0x0a394), P(0x0a398), P(0x0a39c), P(0x0a3a0),
+ P(0x0a3a4), P(0x0a3a8), P(0x0a3ac), P(0x0a3c0), P(0x0a3c4),
+ P(0x0a3c8), P(0x0a3cc), P(0x0a3d0), P(0x0a3d4), P(0x0a3d8),
+ P(0x0a3dc), P(0x0a3e0), P(0x0a3e4), P(0x0a3e8), P(0x0a3ec),
+ P(0x0a3f0), P(0x0a3f4), P(0x0a3f8), P(0x0a3fc), P(0x0a400),
+ P(0x0a404), P(0x0a408), P(0x0a40c), P(0x0a414), P(0x0a418),
+ P(0x0a41c), P(0x0a420), P(0x0a424), P(0x0a428), P(0x0a42c),
+ P(0x0a430), P(0x0a434), P(0x0a438), P(0x0a43c), P(0x0a440),
+ P(0x0a444), P(0x0a448), P(0x0a44c), P(0x0a450), P(0x0a5c4),
+ P(0x0a5c8), P(0x0a5cc), P(0x0a760), P(0x0a764), P(0x0a768),
+ P(0x0a76c), P(0x0a770), P(0x0a774), P(0x0a778), P(0x0a780),
+ P(0x0a7c0), P(0x0a7c4), P(0x0a7c8), P(0x0a7cc), P(0x0a7d0),
+ P(0x0a7d4), P(0x0a7dc), P(0x16000), P(0x16004), P(0x16008),
+ P(0x1600c), P(0x16040), P(0x1604c), P(0x16050), P(0x16054),
+ P(0x16080), P(0x16084), P(0x16088), P(0x1608c), P(0x16090),
+ P(0x16098), P(0x160a0), P(0x160a4), P(0x160a8), P(0x160b4),
+ P(0x160c0), P(0x160c4), P(0x160c8), P(0x160cc), P(0x160d0),
+ P(0x16100), P(0x16104), P(0x16108), P(0x16144), P(0x16148),
+ P(0x16240), P(0x16244), P(0x16248), P(0x1624c), P(0x16280),
+ P(0x16284), P(0x16288), P(0x1628c), P(0x16290), P(0x16380),
+ P(0x16384), P(0x16388), P(0x1638c), P(0x16390), P(0x16394),
+ P(0x16398), P(0x1639c), P(0x163a0), P(0x163a4), P(0x163a8),
+ P(0x163ac), P(0x163b0), P(0x163b4), P(0x163b8), P(0x163bc),
+ P(0x163c0), P(0x163c4), P(0x163c8), P(0x163cc), P(0x163d0),
+ P(0x163d4), P(0x16c40), P(0x16c44), P(0x04014), P(0x04090),
+ P(0x040a4), P(0x07010), P(0x07020), P(0x07034), P(0x07038),
+ P(0x07048)
+};
+
+static const uint32_t ar9485_1_1_cm_vals[] = {
+ 0x00000000, 0x00020085, 0x00000005, 0x00000000, 0x00000000,
+ 0x00000008, 0x00000010, 0x00000000, 0x002ffc0f, 0x002ffc0f,
+ 0x002ffc0f, 0x002ffc0f, 0x002ffc0f, 0x002ffc0f, 0x002ffc0f,
+ 0x002ffc0f, 0x002ffc0f, 0x002ffc0f, 0x00000100, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0xffffffff, 0x00000000, 0x00000000, 0x000fc78f, 0x0000000f,
+ 0x00000000, 0x00000310, 0x00000020, 0x00000000, 0x0000000f,
+ 0x00000000, 0x02ff0000, 0x0e070605, 0x0000000d, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x2a800000, 0x06900168,
+ 0x13881c22, 0x01f40000, 0x00252500, 0x00a00000, 0x00400000,
+ 0x00000000, 0xffffffff, 0x0000ffff, 0x3f3f3f3f, 0x00000000,
+ 0x00000000, 0x00000000, 0x00020000, 0x00000000, 0x00000052,
+ 0x00000000, 0x00000000, 0x000007ff, 0x000000aa, 0x00003210,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x0000ffff, 0xffffffff, 0x00000000, 0x00000000,
+ 0x18486200, 0x33332210, 0x00000000, 0x00020000, 0x00000000,
+ 0x33332210, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00100000, 0x0010f400, 0x00000800,
+ 0x0001e800, 0x00000000, 0x00000000, 0x00000000, 0x40000000,
+ 0x00080922, 0x9ca00010, 0xffffffff, 0x0000ffff, 0x00000000,
+ 0x40000000, 0x003e4180, 0x00000004, 0x0000002c, 0x0000002c,
+ 0x000000ff, 0x00000000, 0x00000000, 0x00000000, 0x00000140,
+ 0x00000000, 0x0000010d, 0x00000000, 0x00000007, 0x00000302,
+ 0x00000700, 0x00ff0000, 0x02400000, 0x000107ff, 0xa248105b,
+ 0x008f0000, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000,
+ 0x00000000, 0x000000ff, 0x00000000, 0x00000000, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
+ 0x00000000, 0x0000fa14, 0x000f0c00, 0x33332210, 0x33332210,
+ 0x33332210, 0x33332210, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000200, 0x000301ff, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xafe68e30,
+ 0xfd14e000, 0x9c0a8f6b, 0x04800000, 0x9280c00a, 0x00000000,
+ 0x00020028, 0x5f3ca3de, 0x0108ecff, 0x14750600, 0x201fff00,
+ 0x00001042, 0x00200400, 0x52440bbe, 0x004b6a8e, 0x00000820,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03200000,
+ 0x00000000, 0x00000000, 0x00046384, 0x05b6b440, 0x00b6b440,
+ 0xc080a333, 0x40206c10, 0x009c4060, 0x1883800a, 0x01834061,
+ 0x00c00400, 0x00000000, 0x00000000, 0x0038233c, 0x9927b515,
+ 0x12ef0200, 0x06336f77, 0x6af6532f, 0x0cc80c00, 0x0d261820,
+ 0x00001004, 0x00ff03f1, 0x80be4788, 0x0001efb5, 0x40000014,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x10002310,
+ 0x00000000, 0x0c000000, 0x00000001, 0x00000001, 0x00000000,
+ 0x18c43433, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x0000a000, 0x00000000, 0x00000000,
+ 0x00000001, 0x00000444, 0x001f0e0f, 0x0075393f, 0xb79f6427,
+ 0x000000ff, 0x3b3b3b3b, 0x2f2f2f2f, 0x20202020, 0x22222220,
+ 0x20200020, 0x20202020, 0x20202020, 0x20202020, 0x20202020,
+ 0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020,
+ 0x00000000, 0x00000006, 0x0cdbd380, 0x000f0f01, 0x8fa91f01,
+ 0x00000000, 0x0e79e5c6, 0x00820820, 0x1ce739cf, 0x2d0019ce,
+ 0x1ce739ce, 0x000001ce, 0x1ce739ce, 0x000001ce, 0x1ce739ce,
+ 0x1ce739ce, 0x00000000, 0x00001801, 0x00000000, 0x00000000,
+ 0x00000000, 0x04000000, 0x00000001, 0x00010000, 0xbfad9d74,
+ 0x0048060a, 0x00000637, 0x03020100, 0x09080504, 0x0d0c0b0a,
+ 0x13121110, 0x31301514, 0x35343332, 0x00000036, 0x00000838,
+ 0x00000000, 0xfffffffc, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000004, 0x00000000, 0x36db6db6, 0x6db6db40, 0x73800000,
+ 0x00000000, 0x7f80fff8, 0x000f0278, 0x4db6db8c, 0x6db60000,
+ 0x00080000, 0x0e48048c, 0x14214514, 0x119f081e, 0x24926490,
+ 0xd28b3330, 0xc2108ffe, 0x812fc370, 0x423c8000, 0x92480040,
+ 0x006db6db, 0x0186db60, 0x6db6db6c, 0x6de6fbe0, 0xf7dfcf3c,
+ 0x04cb0001, 0xfff80015, 0x00080010, 0x01884080, 0x00008040,
+ 0x08400000, 0x1bf90f00, 0x00000000, 0x00000000, 0x01000015,
+ 0x00d30000, 0x00318000, 0x50000000, 0x4b96210f, 0x00000000,
+ 0x00000000, 0x00800700, 0x00800700, 0x00800700, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000001, 0x00000001, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x000000a0, 0x000c0000, 0x14021402, 0x00001402, 0x00000000,
+ 0x00000000, 0x13188278, 0x12000000, 0xba280400, 0x00aa10aa,
+ 0x00a0c9c9, 0x00000022, 0x00000000, 0x00000002, 0x000004c2,
+ 0x00000002
+};
+
+static const struct athn_ini ar9485_1_1_ini = {
+ .nregs = __arraycount(ar9485_1_1_regs),
+ .regs = ar9485_1_1_regs,
+ .vals_5g20 = NULL, /* 2GHz only. */
+#ifndef IEEE80211_NO_HT
+ .vals_5g40 = NULL, /* 2GHz only. */
+ .vals_2g40 = ar9485_1_1_vals_2g40,
+#endif
+ .vals_2g20 = ar9485_1_1_vals_2g20,
+ .ncmregs = __arraycount(ar9485_1_1_cm_regs),
+ .cmregs = ar9485_1_1_cm_regs,
+ .cmvals = ar9485_1_1_cm_vals
+};
+
+/*
+ * AR9380 2.2 Tx gains.
+ */
+static const uint16_t ar9380_2_2_tx_gain_regs[] = {
+ P(0x0a2dc), P(0x0a2e0), P(0x0a2e4), P(0x0a2e8), P(0x0a410),
+ P(0x0a500), P(0x0a504), P(0x0a508), P(0x0a50c), P(0x0a510),
+ P(0x0a514), P(0x0a518), P(0x0a51c), P(0x0a520), P(0x0a524),
+ P(0x0a528), P(0x0a52c), P(0x0a530), P(0x0a534), P(0x0a538),
+ P(0x0a53c), P(0x0a540), P(0x0a544), P(0x0a548), P(0x0a54c),
+ P(0x0a550), P(0x0a554), P(0x0a558), P(0x0a55c), P(0x0a560),
+ P(0x0a564), P(0x0a568), P(0x0a56c), P(0x0a570), P(0x0a574),
+ P(0x0a578), P(0x0a57c), P(0x0a580), P(0x0a584), P(0x0a588),
+ P(0x0a58c), P(0x0a590), P(0x0a594), P(0x0a598), P(0x0a59c),
+ P(0x0a5a0), P(0x0a5a4), P(0x0a5a8), P(0x0a5ac), P(0x0a5b0),
+ P(0x0a5b4), P(0x0a5b8), P(0x0a5bc), P(0x0a5c0), P(0x0a5c4),
+ P(0x0a5c8), P(0x0a5cc), P(0x0a5d0), P(0x0a5d4), P(0x0a5d8),
+ P(0x0a5dc), P(0x0a5e0), P(0x0a5e4), P(0x0a5e8), P(0x0a5ec),
+ P(0x0a5f0), P(0x0a5f4), P(0x0a5f8), P(0x0a5fc), P(0x0a600),
+ P(0x0a604), P(0x0a608), P(0x0a60c), P(0x0a610), P(0x0a614),
+ P(0x0a618), P(0x0a61c), P(0x0a620), P(0x0a624), P(0x0a628),
+ P(0x0a62c), P(0x0a630), P(0x0a634), P(0x0a638), P(0x0a63c),
+ P(0x0b2dc), P(0x0b2e0), P(0x0b2e4), P(0x0b2e8), P(0x0c2dc),
+ P(0x0c2e0), P(0x0c2e4), P(0x0c2e8), P(0x16044), P(0x16048),
+ P(0x16068), P(0x16444), P(0x16448), P(0x16468), P(0x16844),
+ P(0x16848), P(0x16868)
+};
+
+static const uint32_t ar9380_2_2_tx_gain_vals_5g[] = {
+ 0x00033800, 0x0003c000, 0x03fc0000, 0x00000000, 0x000050d9,
+ 0x00000000, 0x06000003, 0x0a000020, 0x10000023, 0x16000220,
+ 0x1c000223, 0x21002220, 0x27002223, 0x2b022220, 0x2f022222,
+ 0x34022225, 0x3a02222a, 0x3e02222c, 0x4202242a, 0x4702244a,
+ 0x4b02244c, 0x4e02246c, 0x52022470, 0x55022490, 0x59022492,
+ 0x5d022692, 0x61022892, 0x65024890, 0x69024892, 0x6e024c92,
+ 0x74026e92, 0x74026e92, 0x74026e92, 0x74026e92, 0x74026e92,
+ 0x74026e92, 0x74026e92, 0x00800000, 0x06800003, 0x0a800020,
+ 0x10800023, 0x16800220, 0x1c800223, 0x21802220, 0x27802223,
+ 0x2b822220, 0x2f822222, 0x34822225, 0x3a82222a, 0x3e82222c,
+ 0x4282242a, 0x4782244a, 0x4b82244c, 0x4e82246c, 0x52822470,
+ 0x55822490, 0x59822492, 0x5d822692, 0x61822892, 0x65824890,
+ 0x69824892, 0x6e824c92, 0x74826e92, 0x74826e92, 0x74826e92,
+ 0x74826e92, 0x74826e92, 0x74826e92, 0x74826e92, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x02004000,
+ 0x02004801, 0x02808a02, 0x0380ce03, 0x04411104, 0x04411104,
+ 0x04411104, 0x04411104, 0x04411104, 0x04411104, 0x04411104,
+ 0x00033800, 0x0003c000, 0x03fc0000, 0x00000000, 0x00033800,
+ 0x0003c000, 0x03fc0000, 0x00000000, 0x012492d4, 0x62480001,
+ 0x6db6db6c, 0x012492d4, 0x62480001, 0x6db6db6c, 0x012492d4,
+ 0x62480001, 0x6db6db6c
+};
+
+static const uint32_t ar9380_2_2_tx_gain_vals_2g[] = {
+ 0x00637800, 0x03838000, 0x03fc0000, 0x00000000, 0x000050d9,
+ 0x00000000, 0x04000002, 0x08000004, 0x0b000200, 0x0f000202,
+ 0x12000400, 0x16000402, 0x19000404, 0x1c000603, 0x21000a02,
+ 0x25000a04, 0x28000a20, 0x2c000e20, 0x30000e22, 0x34000e24,
+ 0x38001640, 0x3c001660, 0x3f001861, 0x43001a81, 0x47001a83,
+ 0x4a001c84, 0x4e001ce3, 0x52001ce5, 0x56001ce9, 0x5a001ceb,
+ 0x5d001eec, 0x5d001eec, 0x5d001eec, 0x5d001eec, 0x5d001eec,
+ 0x5d001eec, 0x5d001eec, 0x00800000, 0x04800002, 0x08800004,
+ 0x0b800200, 0x0f800202, 0x12800400, 0x16800402, 0x19800404,
+ 0x1c800603, 0x21800a02, 0x25800a04, 0x28800a20, 0x2c800e20,
+ 0x30800e22, 0x34800e24, 0x38801640, 0x3c801660, 0x3f801861,
+ 0x43801a81, 0x47801a83, 0x4a801c84, 0x4e801ce3, 0x52801ce5,
+ 0x56801ce9, 0x5a801ceb, 0x5d801eec, 0x5d801eec, 0x5d801eec,
+ 0x5d801eec, 0x5d801eec, 0x5d801eec, 0x5d801eec, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01404000,
+ 0x01404501, 0x02008501, 0x0280ca03, 0x03010c04, 0x04014c04,
+ 0x04015005, 0x04015005, 0x04015005, 0x04015005, 0x04015005,
+ 0x00637800, 0x03838000, 0x03fc0000, 0x00000000, 0x00637800,
+ 0x03838000, 0x03fc0000, 0x00000000, 0x012492d4, 0x62480001,
+ 0x6db6db6c, 0x012492d4, 0x62480001, 0x6db6db6c, 0x012492d4,
+ 0x62480001, 0x6db6db6c
+};
+
+static const struct athn_gain ar9380_2_2_tx_gain = {
+ __arraycount(ar9380_2_2_tx_gain_regs),
+ ar9380_2_2_tx_gain_regs,
+ ar9380_2_2_tx_gain_vals_5g,
+ ar9380_2_2_tx_gain_vals_2g
+};
+
+/*
+ * AR9380 2.2 high ob/db Tx gains.
+ */
+static const uint32_t ar9380_2_2_tx_gain_high_ob_db_vals_5g[] = {
+ 0x01feee00, 0x0000f000, 0x01ff0000, 0x00000000, 0x000050d8,
+ 0x00002220, 0x04002222, 0x09002421, 0x0d002621, 0x13004620,
+ 0x19004a20, 0x1d004e20, 0x21005420, 0x26005e20, 0x2b005e40,
+ 0x2f005e42, 0x33005e44, 0x38005e65, 0x3c005e69, 0x40005e6b,
+ 0x44005e6d, 0x49005e72, 0x4e005eb2, 0x53005f12, 0x59025eb2,
+ 0x5e025f12, 0x61027f12, 0x6702bf12, 0x6b02bf14, 0x6f02bf16,
+ 0x6f02bf16, 0x6f02bf16, 0x6f02bf16, 0x6f02bf16, 0x6f02bf16,
+ 0x6f02bf16, 0x6f02bf16, 0x00802220, 0x04802222, 0x09802421,
+ 0x0d802621, 0x13804620, 0x19804a20, 0x1d804e20, 0x21805420,
+ 0x26805e20, 0x2b805e40, 0x2f805e42, 0x33805e44, 0x38805e65,
+ 0x3c805e69, 0x40805e6b, 0x44805e6d, 0x49805e72, 0x4e805eb2,
+ 0x53805f12, 0x59825eb2, 0x5e825f12, 0x61827f12, 0x6782bf12,
+ 0x6b82bf14, 0x6f82bf16, 0x6f82bf16, 0x6f82bf16, 0x6f82bf16,
+ 0x6f82bf16, 0x6f82bf16, 0x6f82bf16, 0x6f82bf16, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00804000, 0x00804201,
+ 0x0280c802, 0x0280ca03, 0x04c15104, 0x04c15305, 0x04c15305,
+ 0x04c15305, 0x04c15305, 0x04c15305, 0x04c15305, 0x04c15305,
+ 0x01feee00, 0x0000f000, 0x01ff0000, 0x00000000, 0x01feee00,
+ 0x0000f000, 0x01ff0000, 0x00000000, 0x056db2e4, 0x8e480001,
+ 0x6db6db6c, 0x056db2e4, 0x8e480001, 0x6db6db6c, 0x056db2e4,
+ 0x8e480001, 0x6db6db6c
+};
+
+static const uint32_t ar9380_2_2_tx_gain_high_ob_db_vals_2g[] = {
+ 0x00637800, 0x03838000, 0x03fc0000, 0x00000000, 0x000050d9,
+ 0x00000000, 0x04000002, 0x08000004, 0x0b000200, 0x0f000202,
+ 0x11000400, 0x15000402, 0x19000404, 0x1b000603, 0x1f000a02,
+ 0x23000a04, 0x26000a20, 0x2a000e20, 0x2e000e22, 0x31000e24,
+ 0x34001640, 0x38001660, 0x3b001861, 0x3e001a81, 0x42001a83,
+ 0x44001c84, 0x48001ce3, 0x4c001ce5, 0x50001ce9, 0x54001ceb,
+ 0x56001eec, 0x56001eec, 0x56001eec, 0x56001eec, 0x56001eec,
+ 0x56001eec, 0x56001eec, 0x00800000, 0x04800002, 0x08800004,
+ 0x0b800200, 0x0f800202, 0x11800400, 0x15800402, 0x19800404,
+ 0x1b800603, 0x1f800a02, 0x23800a04, 0x26800a20, 0x2a800e20,
+ 0x2e800e22, 0x31800e24, 0x34801640, 0x38801660, 0x3b801861,
+ 0x3e801a81, 0x42801a83, 0x44801c84, 0x48801ce3, 0x4c801ce5,
+ 0x50801ce9, 0x54801ceb, 0x56801eec, 0x56801eec, 0x56801eec,
+ 0x56801eec, 0x56801eec, 0x56801eec, 0x56801eec, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01404000,
+ 0x01404501, 0x02008501, 0x0280ca03, 0x03010c04, 0x04014c04,
+ 0x04015005, 0x04015005, 0x04015005, 0x04015005, 0x04015005,
+ 0x00637800, 0x03838000, 0x03fc0000, 0x00000000, 0x00637800,
+ 0x03838000, 0x03fc0000, 0x00000000, 0x056db2e4, 0x8e480001,
+ 0x6db6db6c, 0x056db2e4, 0x8e480001, 0x6db6db6c, 0x056db2e4,
+ 0x8e480001, 0x6db6db6c
+};
+
+static const struct athn_gain ar9380_2_2_tx_gain_high_ob_db = {
+ __arraycount(ar9380_2_2_tx_gain_regs),
+ ar9380_2_2_tx_gain_regs,
+ ar9380_2_2_tx_gain_high_ob_db_vals_5g,
+ ar9380_2_2_tx_gain_high_ob_db_vals_2g
+};
+
+/*
+ * AR9380 2.2 low ob/db Tx gains.
+ */
+static const uint32_t ar9380_2_2_tx_gain_low_ob_db_vals_5g[] = {
+ 0x0380c7fc, 0x0000f800, 0x03ff0000, 0x00000000, 0x000050d9,
+ 0x00000000, 0x06000003, 0x0a000020, 0x10000023, 0x16000220,
+ 0x1c000223, 0x21002220, 0x27002223, 0x2b022220, 0x2f022222,
+ 0x34022225, 0x3a02222a, 0x3e02222c, 0x4202242a, 0x4702244a,
+ 0x4b02244c, 0x4e02246c, 0x5302266c, 0x5702286c, 0x5c02486b,
+ 0x61024a6c, 0x66026a6c, 0x6b026e6c, 0x7002708c, 0x7302b08a,
+ 0x7702b08c, 0x7702b08c, 0x7702b08c, 0x7702b08c, 0x7702b08c,
+ 0x7702b08c, 0x7702b08c, 0x00800000, 0x06800003, 0x0a800020,
+ 0x10800023, 0x16800220, 0x1c800223, 0x21802220, 0x27802223,
+ 0x2b822220, 0x2f822222, 0x34822225, 0x3a82222a, 0x3e82222c,
+ 0x4282242a, 0x4782244a, 0x4b82244c, 0x4e82246c, 0x5382266c,
+ 0x5782286c, 0x5c82486b, 0x61824a6c, 0x66826a6c, 0x6b826e6c,
+ 0x7082708c, 0x7382b08a, 0x7782b08c, 0x7782b08c, 0x7782b08c,
+ 0x7782b08c, 0x7782b08c, 0x7782b08c, 0x7782b08c, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01404000,
+ 0x01404501, 0x02008802, 0x0300cc03, 0x0300cc03, 0x0300cc03,
+ 0x03810c03, 0x03810e04, 0x03810e04, 0x03810e04, 0x03810e04,
+ 0x0380c7fc, 0x0000f800, 0x03ff0000, 0x00000000, 0x0380c7fc,
+ 0x0000f800, 0x03ff0000, 0x00000000, 0x012492d4, 0x66480001,
+ 0x6db6db6c, 0x012492d4, 0x66480001, 0x6db6db6c, 0x012492d4,
+ 0x66480001, 0x6db6db6c
+};
+
+static const uint32_t ar9380_2_2_tx_gain_low_ob_db_vals_2g[] = {
+ 0x00637800, 0x03838000, 0x03fc0000, 0x00000000, 0x000050d9,
+ 0x00000000, 0x04000002, 0x08000004, 0x0b000200, 0x0f000202,
+ 0x12000400, 0x16000402, 0x19000404, 0x1c000603, 0x21000a02,
+ 0x25000a04, 0x28000a20, 0x2c000e20, 0x30000e22, 0x34000e24,
+ 0x38001640, 0x3c001660, 0x3f001861, 0x43001a81, 0x47001a83,
+ 0x4a001c84, 0x4e001ce3, 0x52001ce5, 0x56001ce9, 0x5a001ceb,
+ 0x5d001eec, 0x5d001eec, 0x5d001eec, 0x5d001eec, 0x5d001eec,
+ 0x5d001eec, 0x5d001eec, 0x00800000, 0x04800002, 0x08800004,
+ 0x0b800200, 0x0f800202, 0x12800400, 0x16800402, 0x19800404,
+ 0x1c800603, 0x21800a02, 0x25800a04, 0x28800a20, 0x2c800e20,
+ 0x30800e22, 0x34800e24, 0x38801640, 0x3c801660, 0x3f801861,
+ 0x43801a81, 0x47801a83, 0x4a801c84, 0x4e801ce3, 0x52801ce5,
+ 0x56801ce9, 0x5a801ceb, 0x5d801eec, 0x5d801eec, 0x5d801eec,
+ 0x5d801eec, 0x5d801eec, 0x5d801eec, 0x5d801eec, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01404000,
+ 0x01404501, 0x02008501, 0x0280ca03, 0x03010c04, 0x04014c04,
+ 0x04015005, 0x04015005, 0x04015005, 0x04015005, 0x04015005,
+ 0x00637800, 0x03838000, 0x03fc0000, 0x00000000, 0x00637800,
+ 0x03838000, 0x03fc0000, 0x00000000, 0x012492d4, 0x66480001,
+ 0x6db6db6c, 0x012492d4, 0x66480001, 0x6db6db6c, 0x012492d4,
+ 0x66480001, 0x6db6db6c
+};
+
+static const struct athn_gain ar9380_2_2_tx_gain_low_ob_db = {
+ __arraycount(ar9380_2_2_tx_gain_regs),
+ ar9380_2_2_tx_gain_regs,
+ ar9380_2_2_tx_gain_low_ob_db_vals_5g,
+ ar9380_2_2_tx_gain_low_ob_db_vals_2g
+};
+
+/*
+ * AR9380 2.2 high power Tx gains.
+ */
+static const uint32_t ar9380_2_2_tx_gain_high_power_vals_5g[] = {
+ 0x0380c7fc, 0x0000f800, 0x03ff0000, 0x00000000, 0x000050d8,
+ 0x00002220, 0x04002222, 0x09002421, 0x0d002621, 0x13004620,
+ 0x19004a20, 0x1d004e20, 0x21005420, 0x26005e20, 0x2b005e40,
+ 0x2f005e42, 0x33005e44, 0x38005e65, 0x3c005e69, 0x40005e6b,
+ 0x44005e6d, 0x49005e72, 0x4e005eb2, 0x53005f12, 0x59025eb2,
+ 0x5e025f12, 0x61027f12, 0x6702bf12, 0x6b02bf14, 0x6f02bf16,
+ 0x6f02bf16, 0x6f02bf16, 0x6f02bf16, 0x6f02bf16, 0x6f02bf16,
+ 0x6f02bf16, 0x6f02bf16, 0x00802220, 0x04802222, 0x09802421,
+ 0x0d802621, 0x13804620, 0x19804a20, 0x1d804e20, 0x21805420,
+ 0x26805e20, 0x2b805e40, 0x2f805e42, 0x33805e44, 0x38805e65,
+ 0x3c805e69, 0x40805e6b, 0x44805e6d, 0x49805e72, 0x4e805eb2,
+ 0x53805f12, 0x59825eb2, 0x5e825f12, 0x61827f12, 0x6782bf12,
+ 0x6b82bf14, 0x6f82bf16, 0x6f82bf16, 0x6f82bf16, 0x6f82bf16,
+ 0x6f82bf16, 0x6f82bf16, 0x6f82bf16, 0x6f82bf16, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00804000, 0x00804201,
+ 0x0280c802, 0x0280ca03, 0x04c15104, 0x04c15305, 0x04c15305,
+ 0x04c15305, 0x04c15305, 0x04c15305, 0x04c15305, 0x04c15305,
+ 0x0380c7fc, 0x0000f800, 0x03ff0000, 0x00000000, 0x0380c7fc,
+ 0x0000f800, 0x03ff0000, 0x00000000, 0x056db2e6, 0xae480001,
+ 0x6eb6db6c, 0x056db2e6, 0xae480001, 0x6eb6db6c, 0x056db2e6,
+ 0xae480001, 0x6eb6db6c
+};
+
+static const uint32_t ar9380_2_2_tx_gain_high_power_vals_2g[] = {
+ 0x00637800, 0x03838000, 0x03fc0000, 0x00000000, 0x000050d9,
+ 0x00000000, 0x04000002, 0x08000004, 0x0b000200, 0x0f000202,
+ 0x11000400, 0x15000402, 0x19000404, 0x1b000603, 0x1f000a02,
+ 0x23000a04, 0x26000a20, 0x2a000e20, 0x2e000e22, 0x31000e24,
+ 0x34001640, 0x38001660, 0x3b001861, 0x3e001a81, 0x42001a83,
+ 0x44001c84, 0x48001ce3, 0x4c001ce5, 0x50001ce9, 0x54001ceb,
+ 0x56001eec, 0x56001eec, 0x56001eec, 0x56001eec, 0x56001eec,
+ 0x56001eec, 0x56001eec, 0x00800000, 0x04800002, 0x08800004,
+ 0x0b800200, 0x0f800202, 0x11800400, 0x15800402, 0x19800404,
+ 0x1b800603, 0x1f800a02, 0x23800a04, 0x26800a20, 0x2a800e20,
+ 0x2e800e22, 0x31800e24, 0x34801640, 0x38801660, 0x3b801861,
+ 0x3e801a81, 0x42801a83, 0x44801c84, 0x48801ce3, 0x4c801ce5,
+ 0x50801ce9, 0x54801ceb, 0x56801eec, 0x56801eec, 0x56801eec,
+ 0x56801eec, 0x56801eec, 0x56801eec, 0x56801eec, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01404000,
+ 0x01404501, 0x02008501, 0x0280ca03, 0x03010c04, 0x04014c04,
+ 0x04015005, 0x04015005, 0x04015005, 0x04015005, 0x04015005,
+ 0x00637800, 0x03838000, 0x03fc0000, 0x00000000, 0x00637800,
+ 0x03838000, 0x03fc0000, 0x00000000, 0x056db2e6, 0xae480001,
+ 0x6eb6db6c, 0x056db2e6, 0xae480001, 0x6eb6db6c, 0x056db2e6,
+ 0xae480001, 0x6eb6db6c
+};
+
+static const struct athn_gain ar9380_2_2_tx_gain_high_power = {
+ __arraycount(ar9380_2_2_tx_gain_regs),
+ ar9380_2_2_tx_gain_regs,
+ ar9380_2_2_tx_gain_high_power_vals_5g,
+ ar9380_2_2_tx_gain_high_power_vals_2g
+};
+
+/*
+ * AR9485 1.1 Tx gains.
+ */
+static const uint16_t ar9485_1_1_tx_gain_regs[] = {
+ P(0x098bc), P(0x0a410), P(0x0a458), P(0x0a500), P(0x0a504),
+ P(0x0a508), P(0x0a50c), P(0x0a510), P(0x0a514), P(0x0a518),
+ P(0x0a51c), P(0x0a520), P(0x0a524), P(0x0a528), P(0x0a52c),
+ P(0x0a530), P(0x0a534), P(0x0a538), P(0x0a53c), P(0x0a540),
+ P(0x0a544), P(0x0a548), P(0x0a54c), P(0x0a550), P(0x0a554),
+ P(0x0a558), P(0x0a55c), P(0x0a560), P(0x0a564), P(0x0a568),
+ P(0x0a56c), P(0x0a570), P(0x0a574), P(0x0a578), P(0x0a57c),
+ P(0x0b500), P(0x0b504), P(0x0b508), P(0x0b50c), P(0x0b510),
+ P(0x0b514), P(0x0b518), P(0x0b51c), P(0x0b520), P(0x0b524),
+ P(0x0b528), P(0x0b52c), P(0x0b530), P(0x0b534), P(0x0b538),
+ P(0x0b53c), P(0x0b540), P(0x0b544), P(0x0b548), P(0x0b54c),
+ P(0x0b550), P(0x0b554), P(0x0b558), P(0x0b55c), P(0x0b560),
+ P(0x0b564), P(0x0b568), P(0x0b56c), P(0x0b570), P(0x0b574),
+ P(0x0b578), P(0x0b57c), P(0x16044), P(0x16048),
+};
+
+static const uint32_t ar9485_1_1_tx_gain_vals_2g[] = {
+ 0x00000002, 0x000050d8, 0x00000000, 0x00000000, 0x04000002,
+ 0x08000004, 0x0d000200, 0x11000202, 0x15000400, 0x19000402,
+ 0x1d000404, 0x21000603, 0x25000605, 0x2a000a03, 0x2c000a04,
+ 0x34000e20, 0x35000e21, 0x43000e62, 0x45000e63, 0x49000e65,
+ 0x4b000e66, 0x4d001645, 0x51001865, 0x55001a86, 0x57001ce9,
+ 0x5a001ceb, 0x5e001eeb, 0x5e001eeb, 0x5e001eeb, 0x5e001eeb,
+ 0x5e001eeb, 0x5e001eeb, 0x5e001eeb, 0x5e001eeb, 0x5e001eeb,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x05d6b2db, 0x6c924260
+};
+
+static const struct athn_gain ar9485_1_1_tx_gain = {
+ __arraycount(ar9485_1_1_tx_gain_regs),
+ ar9485_1_1_tx_gain_regs,
+ NULL, /* 2GHz only. */
+ ar9485_1_1_tx_gain_vals_2g
+};
+
+/*
+ * AR9380 2.2 Rx gains.
+ */
+static const uint16_t ar9380_2_2_rx_gain_regs[] = {
+ P(0x0a000), P(0x0a004), P(0x0a008), P(0x0a00c), P(0x0a010),
+ P(0x0a014), P(0x0a018), P(0x0a01c), P(0x0a020), P(0x0a024),
+ P(0x0a028), P(0x0a02c), P(0x0a030), P(0x0a034), P(0x0a038),
+ P(0x0a03c), P(0x0a040), P(0x0a044), P(0x0a048), P(0x0a04c),
+ P(0x0a050), P(0x0a054), P(0x0a058), P(0x0a05c), P(0x0a060),
+ P(0x0a064), P(0x0a068), P(0x0a06c), P(0x0a070), P(0x0a074),
+ P(0x0a078), P(0x0a07c), P(0x0a080), P(0x0a084), P(0x0a088),
+ P(0x0a08c), P(0x0a090), P(0x0a094), P(0x0a098), P(0x0a09c),
+ P(0x0a0a0), P(0x0a0a4), P(0x0a0a8), P(0x0a0ac), P(0x0a0b0),
+ P(0x0a0b4), P(0x0a0b8), P(0x0a0bc), P(0x0a0c0), P(0x0a0c4),
+ P(0x0a0c8), P(0x0a0cc), P(0x0a0d0), P(0x0a0d4), P(0x0a0d8),
+ P(0x0a0dc), P(0x0a0e0), P(0x0a0e4), P(0x0a0e8), P(0x0a0ec),
+ P(0x0a0f0), P(0x0a0f4), P(0x0a0f8), P(0x0a0fc), P(0x0a100),
+ P(0x0a104), P(0x0a108), P(0x0a10c), P(0x0a110), P(0x0a114),
+ P(0x0a118), P(0x0a11c), P(0x0a120), P(0x0a124), P(0x0a128),
+ P(0x0a12c), P(0x0a130), P(0x0a134), P(0x0a138), P(0x0a13c),
+ P(0x0a140), P(0x0a144), P(0x0a148), P(0x0a14c), P(0x0a150),
+ P(0x0a154), P(0x0a158), P(0x0a15c), P(0x0a160), P(0x0a164),
+ P(0x0a168), P(0x0a16c), P(0x0a170), P(0x0a174), P(0x0a178),
+ P(0x0a17c), P(0x0a180), P(0x0a184), P(0x0a188), P(0x0a18c),
+ P(0x0a190), P(0x0a194), P(0x0a198), P(0x0a19c), P(0x0a1a0),
+ P(0x0a1a4), P(0x0a1a8), P(0x0a1ac), P(0x0a1b0), P(0x0a1b4),
+ P(0x0a1b8), P(0x0a1bc), P(0x0a1c0), P(0x0a1c4), P(0x0a1c8),
+ P(0x0a1cc), P(0x0a1d0), P(0x0a1d4), P(0x0a1d8), P(0x0a1dc),
+ P(0x0a1e0), P(0x0a1e4), P(0x0a1e8), P(0x0a1ec), P(0x0a1f0),
+ P(0x0a1f4), P(0x0a1f8), P(0x0a1fc), P(0x0b000), P(0x0b004),
+ P(0x0b008), P(0x0b00c), P(0x0b010), P(0x0b014), P(0x0b018),
+ P(0x0b01c), P(0x0b020), P(0x0b024), P(0x0b028), P(0x0b02c),
+ P(0x0b030), P(0x0b034), P(0x0b038), P(0x0b03c), P(0x0b040),
+ P(0x0b044), P(0x0b048), P(0x0b04c), P(0x0b050), P(0x0b054),
+ P(0x0b058), P(0x0b05c), P(0x0b060), P(0x0b064), P(0x0b068),
+ P(0x0b06c), P(0x0b070), P(0x0b074), P(0x0b078), P(0x0b07c),
+ P(0x0b080), P(0x0b084), P(0x0b088), P(0x0b08c), P(0x0b090),
+ P(0x0b094), P(0x0b098), P(0x0b09c), P(0x0b0a0), P(0x0b0a4),
+ P(0x0b0a8), P(0x0b0ac), P(0x0b0b0), P(0x0b0b4), P(0x0b0b8),
+ P(0x0b0bc), P(0x0b0c0), P(0x0b0c4), P(0x0b0c8), P(0x0b0cc),
+ P(0x0b0d0), P(0x0b0d4), P(0x0b0d8), P(0x0b0dc), P(0x0b0e0),
+ P(0x0b0e4), P(0x0b0e8), P(0x0b0ec), P(0x0b0f0), P(0x0b0f4),
+ P(0x0b0f8), P(0x0b0fc), P(0x0b100), P(0x0b104), P(0x0b108),
+ P(0x0b10c), P(0x0b110), P(0x0b114), P(0x0b118), P(0x0b11c),
+ P(0x0b120), P(0x0b124), P(0x0b128), P(0x0b12c), P(0x0b130),
+ P(0x0b134), P(0x0b138), P(0x0b13c), P(0x0b140), P(0x0b144),
+ P(0x0b148), P(0x0b14c), P(0x0b150), P(0x0b154), P(0x0b158),
+ P(0x0b15c), P(0x0b160), P(0x0b164), P(0x0b168), P(0x0b16c),
+ P(0x0b170), P(0x0b174), P(0x0b178), P(0x0b17c), P(0x0b180),
+ P(0x0b184), P(0x0b188), P(0x0b18c), P(0x0b190), P(0x0b194),
+ P(0x0b198), P(0x0b19c), P(0x0b1a0), P(0x0b1a4), P(0x0b1a8),
+ P(0x0b1ac), P(0x0b1b0), P(0x0b1b4), P(0x0b1b8), P(0x0b1bc),
+ P(0x0b1c0), P(0x0b1c4), P(0x0b1c8), P(0x0b1cc), P(0x0b1d0),
+ P(0x0b1d4), P(0x0b1d8), P(0x0b1dc), P(0x0b1e0), P(0x0b1e4),
+ P(0x0b1e8), P(0x0b1ec), P(0x0b1f0), P(0x0b1f4), P(0x0b1f8),
+ P(0x0b1fc)
+};
+
+static const uint32_t ar9380_2_2_rx_gain_vals[] = {
+ 0x00010000, 0x00030002, 0x00050004, 0x00810080, 0x00830082,
+ 0x01810180, 0x01830182, 0x01850184, 0x01890188, 0x018b018a,
+ 0x018d018c, 0x01910190, 0x01930192, 0x01950194, 0x038a0196,
+ 0x038c038b, 0x0390038d, 0x03920391, 0x03940393, 0x03960395,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x22222229, 0x1d1d1d1d, 0x1d1d1d1d,
+ 0x1d1d1d1d, 0x171d1d1d, 0x11111717, 0x00030311, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x001f0000, 0x01000101,
+ 0x011e011f, 0x011c011d, 0x02030204, 0x02010202, 0x021f0200,
+ 0x0302021e, 0x03000301, 0x031e031f, 0x0402031d, 0x04000401,
+ 0x041e041f, 0x0502041d, 0x05000501, 0x051e051f, 0x06010602,
+ 0x061f0600, 0x061d061e, 0x07020703, 0x07000701, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x001f0000, 0x01000101, 0x011e011f, 0x011c011d, 0x02030204,
+ 0x02010202, 0x021f0200, 0x0302021e, 0x03000301, 0x031e031f,
+ 0x0402031d, 0x04000401, 0x041e041f, 0x0502041d, 0x05000501,
+ 0x051e051f, 0x06010602, 0x061f0600, 0x061d061e, 0x07020703,
+ 0x07000701, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000396,
+ 0x00000396, 0x00000396, 0x00000196, 0x00010000, 0x00030002,
+ 0x00050004, 0x00810080, 0x00830082, 0x01810180, 0x01830182,
+ 0x01850184, 0x02810280, 0x02830282, 0x02850284, 0x02890288,
+ 0x028b028a, 0x0388028c, 0x038a0389, 0x038c038b, 0x0390038d,
+ 0x03920391, 0x03940393, 0x03960395, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x2a2d2f32, 0x21232328, 0x19191c1e, 0x12141417, 0x07070e0e,
+ 0x03030305, 0x00000003, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x003f0020, 0x00400041, 0x0140005f, 0x0160015f,
+ 0x017e017f, 0x02410242, 0x025f0240, 0x027f0260, 0x0341027e,
+ 0x035f0340, 0x037f0360, 0x04400441, 0x0460045f, 0x0541047f,
+ 0x055f0540, 0x057f0560, 0x06400641, 0x0660065f, 0x067e067f,
+ 0x07410742, 0x075f0740, 0x077f0760, 0x07800781, 0x07a0079f,
+ 0x07c107bf, 0x000007c0, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x003f0020, 0x00400041,
+ 0x0140005f, 0x0160015f, 0x017e017f, 0x02410242, 0x025f0240,
+ 0x027f0260, 0x0341027e, 0x035f0340, 0x037f0360, 0x04400441,
+ 0x0460045f, 0x0541047f, 0x055f0540, 0x057f0560, 0x06400641,
+ 0x0660065f, 0x067e067f, 0x07410742, 0x075f0740, 0x077f0760,
+ 0x07800781, 0x07a0079f, 0x07c107bf, 0x000007c0, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000396, 0x00000396, 0x00000396,
+ 0x00000196
+};
+
+static const struct athn_gain ar9380_2_2_rx_gain = {
+ __arraycount(ar9380_2_2_rx_gain_regs),
+ ar9380_2_2_rx_gain_regs,
+ ar9380_2_2_rx_gain_vals,
+ ar9380_2_2_rx_gain_vals
+};
+
+/*
+ * AR9380 2.2 without external low-noise amplifier Rx gains.
+ */
+static const uint32_t ar9380_2_2_rx_gain_wo_xlna_vals[] = {
+ 0x00010000, 0x00030002, 0x00050004, 0x00810080, 0x00830082,
+ 0x01810180, 0x01830182, 0x01850184, 0x01890188, 0x018b018a,
+ 0x018d018c, 0x03820190, 0x03840383, 0x03880385, 0x038a0389,
+ 0x038c038b, 0x0390038d, 0x03920391, 0x03940393, 0x03960395,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x29292929, 0x29292929, 0x29292929,
+ 0x29292929, 0x22292929, 0x1d1d2222, 0x0c111117, 0x00030303,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x001f0000, 0x01000101,
+ 0x011e011f, 0x011c011d, 0x02030204, 0x02010202, 0x021f0200,
+ 0x0302021e, 0x03000301, 0x031e031f, 0x0402031d, 0x04000401,
+ 0x041e041f, 0x0502041d, 0x05000501, 0x051e051f, 0x06010602,
+ 0x061f0600, 0x061d061e, 0x07020703, 0x07000701, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x001f0000, 0x01000101, 0x011e011f, 0x011c011d, 0x02030204,
+ 0x02010202, 0x021f0200, 0x0302021e, 0x03000301, 0x031e031f,
+ 0x0402031d, 0x04000401, 0x041e041f, 0x0502041d, 0x05000501,
+ 0x051e051f, 0x06010602, 0x061f0600, 0x061d061e, 0x07020703,
+ 0x07000701, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000396,
+ 0x00000396, 0x00000396, 0x00000196, 0x00010000, 0x00030002,
+ 0x00050004, 0x00810080, 0x00830082, 0x01810180, 0x01830182,
+ 0x01850184, 0x02810280, 0x02830282, 0x02850284, 0x02890288,
+ 0x028b028a, 0x0388028c, 0x038a0389, 0x038c038b, 0x0390038d,
+ 0x03920391, 0x03940393, 0x03960395, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x32323232, 0x2f2f3232, 0x23282a2d, 0x1c1e2123, 0x14171919,
+ 0x0e0e1214, 0x03050707, 0x00030303, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x003f0020, 0x00400041, 0x0140005f, 0x0160015f,
+ 0x017e017f, 0x02410242, 0x025f0240, 0x027f0260, 0x0341027e,
+ 0x035f0340, 0x037f0360, 0x04400441, 0x0460045f, 0x0541047f,
+ 0x055f0540, 0x057f0560, 0x06400641, 0x0660065f, 0x067e067f,
+ 0x07410742, 0x075f0740, 0x077f0760, 0x07800781, 0x07a0079f,
+ 0x07c107bf, 0x000007c0, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x003f0020, 0x00400041,
+ 0x0140005f, 0x0160015f, 0x017e017f, 0x02410242, 0x025f0240,
+ 0x027f0260, 0x0341027e, 0x035f0340, 0x037f0360, 0x04400441,
+ 0x0460045f, 0x0541047f, 0x055f0540, 0x057f0560, 0x06400641,
+ 0x0660065f, 0x067e067f, 0x07410742, 0x075f0740, 0x077f0760,
+ 0x07800781, 0x07a0079f, 0x07c107bf, 0x000007c0, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000396, 0x00000396, 0x00000396,
+ 0x00000196
+};
+
+static const struct athn_gain ar9380_2_2_rx_gain_wo_xlna = {
+ __arraycount(ar9380_2_2_rx_gain_regs),
+ ar9380_2_2_rx_gain_regs,
+ ar9380_2_2_rx_gain_wo_xlna_vals,
+ ar9380_2_2_rx_gain_wo_xlna_vals
+};
+
+/*
+ * AR9485 1.1 Rx gains.
+ */
+static const uint16_t ar9485_1_1_rx_gain_regs[] = {
+ P(0x0a000), P(0x0a004), P(0x0a008), P(0x0a00c), P(0x0a010),
+ P(0x0a014), P(0x0a018), P(0x0a01c), P(0x0a020), P(0x0a024),
+ P(0x0a028), P(0x0a02c), P(0x0a030), P(0x0a034), P(0x0a038),
+ P(0x0a03c), P(0x0a040), P(0x0a044), P(0x0a048), P(0x0a04c),
+ P(0x0a050), P(0x0a054), P(0x0a058), P(0x0a05c), P(0x0a060),
+ P(0x0a064), P(0x0a068), P(0x0a06c), P(0x0a070), P(0x0a074),
+ P(0x0a078), P(0x0a07c), P(0x0a080), P(0x0a084), P(0x0a088),
+ P(0x0a08c), P(0x0a090), P(0x0a094), P(0x0a098), P(0x0a09c),
+ P(0x0a0a0), P(0x0a0a4), P(0x0a0a8), P(0x0a0ac), P(0x0a0b0),
+ P(0x0a0b4), P(0x0a0b8), P(0x0a0bc), P(0x0a0c0), P(0x0a0c4),
+ P(0x0a0c8), P(0x0a0cc), P(0x0a0d0), P(0x0a0d4), P(0x0a0d8),
+ P(0x0a0dc), P(0x0a0e0), P(0x0a0e4), P(0x0a0e8), P(0x0a0ec),
+ P(0x0a0f0), P(0x0a0f4), P(0x0a0f8), P(0x0a0fc), P(0x0a100),
+ P(0x0a104), P(0x0a108), P(0x0a10c), P(0x0a110), P(0x0a114),
+ P(0x0a118), P(0x0a11c), P(0x0a120), P(0x0a124), P(0x0a128),
+ P(0x0a12c), P(0x0a130), P(0x0a134), P(0x0a138), P(0x0a13c),
+ P(0x0a140), P(0x0a144), P(0x0a148), P(0x0a14c), P(0x0a150),
+ P(0x0a154), P(0x0a158), P(0x0a15c), P(0x0a160), P(0x0a164),
+ P(0x0a168), P(0x0a16c), P(0x0a170), P(0x0a174), P(0x0a178),
+ P(0x0a17c), P(0x0a180), P(0x0a184), P(0x0a188), P(0x0a18c),
+ P(0x0a190), P(0x0a194), P(0x0a198), P(0x0a19c), P(0x0a1a0),
+ P(0x0a1a4), P(0x0a1a8), P(0x0a1ac), P(0x0a1b0), P(0x0a1b4),
+ P(0x0a1b8), P(0x0a1bc), P(0x0a1c0), P(0x0a1c4), P(0x0a1c8),
+ P(0x0a1cc), P(0x0a1d0), P(0x0a1d4), P(0x0a1d8), P(0x0a1dc),
+ P(0x0a1e0), P(0x0a1e4), P(0x0a1e8), P(0x0a1ec), P(0x0a1f0),
+ P(0x0a1f4), P(0x0a1f8), P(0x0a1fc)
+};
+
+static const uint32_t ar9485_1_1_rx_gain_vals[] = {
+ 0x00060005, 0x00810080, 0x00830082, 0x00850084, 0x01820181,
+ 0x01840183, 0x01880185, 0x018a0189, 0x02850284, 0x02890288,
+ 0x028b028a, 0x03850384, 0x03890388, 0x038b038a, 0x038d038c,
+ 0x03910390, 0x03930392, 0x03950394, 0x00000396, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x28282828, 0x28282828, 0x28282828,
+ 0x28282828, 0x28282828, 0x24242428, 0x171e1e1e, 0x02020b0b,
+ 0x02020202, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x22072208, 0x22052206,
+ 0x22032204, 0x22012202, 0x221f2200, 0x221d221e, 0x33023303,
+ 0x33003301, 0x331e331f, 0x4402331d, 0x44004401, 0x441e441f,
+ 0x55025503, 0x55005501, 0x551e551f, 0x6602551d, 0x66006601,
+ 0x661e661f, 0x7703661d, 0x77017702, 0x00007700, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x001f0000, 0x111f1100, 0x111d111e, 0x111b111c, 0x22032204,
+ 0x22012202, 0x221f2200, 0x221d221e, 0x33013302, 0x331f3300,
+ 0x4402331e, 0x44004401, 0x441e441f, 0x55015502, 0x551f5500,
+ 0x6602551e, 0x66006601, 0x661e661f, 0x7703661d, 0x77017702,
+ 0x00007700, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000396,
+ 0x00000396, 0x00000396, 0x00000296
+};
+
+static const struct athn_gain ar9485_1_1_rx_gain = {
+ __arraycount(ar9485_1_1_rx_gain_regs),
+ ar9485_1_1_rx_gain_regs,
+ NULL, /* 2GHz only. */
+ ar9485_1_1_rx_gain_vals
+};
+
+/*
+ * Serializer/Deserializer programming.
+ */
+
+static const uint32_t ar9380_2_2_serdes_regs[] = {
+ AR_PCIE_SERDES,
+ AR_PCIE_SERDES,
+ AR_PCIE_SERDES2
+};
+
+static const uint32_t ar9380_2_2_serdes_vals[] = {
+ 0x08212e5e,
+ 0x0008003b,
+ 0x00000000
+};
+
+static const struct athn_serdes ar9380_2_2_serdes = {
+ __arraycount(ar9380_2_2_serdes_vals),
+ ar9380_2_2_serdes_regs,
+ ar9380_2_2_serdes_vals
+};
+
+static const uint32_t ar9485_1_1_serdes_regs[] = {
+ 0x00018c00,
+ 0x00018c04,
+ 0x00018c08
+};
+
+static const uint32_t ar9485_1_1_serdes_vals[] = {
+ 0x18013e5e,
+ 0x000801d8,
+ 0x0000080c
+};
+
+static const struct athn_serdes ar9485_1_1_serdes = {
+ __arraycount(ar9485_1_1_serdes_vals),
+ ar9485_1_1_serdes_regs,
+ ar9485_1_1_serdes_vals
+};
+
+#endif /* _ARN9380REG_H_ */
diff --git a/sys/dev/ic/athn.c b/sys/dev/ic/athn.c
new file mode 100644
index 00000000000..c3cdf18ce7b
--- /dev/null
+++ b/sys/dev/ic/athn.c
@@ -0,0 +1,2969 @@
+/* $NetBSD: athn.c,v 1.1 2013/03/30 02:53:02 christos Exp $ */
+/* $OpenBSD: athn.c,v 1.75 2013/01/14 09:50:31 jsing Exp $ */
+
+/*-
+ * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr>
+ * Copyright (c) 2008-2010 Atheros Communications Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+/*
+ * Driver for Atheros 802.11a/g/n chipsets.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: athn.c,v 1.1 2013/03/30 02:53:02 christos Exp $");
+
+#ifndef _MODULE
+#include "athn_usb.h" /* for NATHN_USB */
+#endif
+
+#include <sys/param.h>
+#include <sys/sockio.h>
+#include <sys/mbuf.h>
+#include <sys/kernel.h>
+#include <sys/socket.h>
+#include <sys/systm.h>
+#include <sys/malloc.h>
+#include <sys/queue.h>
+#include <sys/callout.h>
+#include <sys/conf.h>
+#include <sys/device.h>
+
+#include <sys/bus.h>
+#include <sys/endian.h>
+#include <sys/intr.h>
+
+#include <net/bpf.h>
+#include <net/if.h>
+#include <net/if_arp.h>
+#include <net/if_dl.h>
+#include <net/if_ether.h>
+#include <net/if_media.h>
+#include <net/if_types.h>
+
+#include <netinet/in.h>
+#include <netinet/in_systm.h>
+#include <netinet/in_var.h>
+#include <netinet/ip.h>
+
+#include <net80211/ieee80211_var.h>
+#include <net80211/ieee80211_amrr.h>
+#include <net80211/ieee80211_radiotap.h>
+
+#include <dev/ic/athnreg.h>
+#include <dev/ic/athnvar.h>
+#include <dev/ic/arn5008.h>
+#include <dev/ic/arn5416.h>
+#include <dev/ic/arn9003.h>
+#include <dev/ic/arn9280.h>
+#include <dev/ic/arn9285.h>
+#include <dev/ic/arn9287.h>
+#include <dev/ic/arn9380.h>
+
+#define Static static
+
+#define IS_UP_AND_RUNNING(ifp) \
+ (((ifp)->if_flags & IFF_UP) && ((ifp)->if_flags & IFF_RUNNING))
+
+#ifdef ATHN_DEBUG
+int athn_debug = 0;
+#endif
+
+Static int athn_clock_rate(struct athn_softc *);
+Static const char *
+ athn_get_mac_name(struct athn_softc *);
+Static const char *
+ athn_get_rf_name(struct athn_softc *);
+Static int athn_init(struct ifnet *);
+Static int athn_init_calib(struct athn_softc *,
+ struct ieee80211_channel *, struct ieee80211_channel *);
+Static int athn_ioctl(struct ifnet *, u_long, void *);
+Static int athn_media_change(struct ifnet *);
+Static int athn_newstate(struct ieee80211com *, enum ieee80211_state,
+ int);
+Static struct ieee80211_node *
+ athn_node_alloc(struct ieee80211_node_table *);
+Static int athn_reset_power_on(struct athn_softc *);
+Static int athn_stop_rx_dma(struct athn_softc *);
+Static int athn_switch_chan(struct athn_softc *,
+ struct ieee80211_channel *, struct ieee80211_channel *);
+Static void athn_calib_to(void *);
+Static void athn_disable_interrupts(struct athn_softc *);
+Static void athn_enable_interrupts(struct athn_softc *);
+Static void athn_get_chanlist(struct athn_softc *);
+Static void athn_get_chipid(struct athn_softc *);
+Static void athn_init_dma(struct athn_softc *);
+Static void athn_init_qos(struct athn_softc *);
+Static void athn_init_tx_queues(struct athn_softc *);
+Static void athn_iter_func(void *, struct ieee80211_node *);
+Static void athn_newassoc(struct ieee80211_node *, int);
+Static void athn_next_scan(void *);
+Static void athn_radiotap_attach(struct athn_softc *);
+Static void athn_start(struct ifnet *);
+Static void athn_tx_reclaim(struct athn_softc *, int);
+Static void athn_watchdog(struct ifnet *);
+Static void athn_write_serdes(struct athn_softc *,
+ const struct athn_serdes *);
+
+#ifdef ATHN_BT_COEXISTENCE
+Static void athn_btcoex_enable(struct athn_softc *);
+Static void athn_btcoex_disable(struct athn_softc *);
+#endif
+
+#ifdef unused
+Static int32_t athn_ani_get_rssi(struct athn_softc *);
+Static int athn_rx_abort(struct athn_softc *);
+#endif
+
+#ifdef notyet
+Static void athn_ani_monitor(struct athn_softc *);
+Static void athn_ani_ofdm_err_trigger(struct athn_softc *);
+Static void athn_ani_cck_err_trigger(struct athn_softc *);
+Static void athn_ani_lower_immunity(struct athn_softc *);
+Static void athn_ani_restart(struct athn_softc *);
+Static void athn_set_multi(struct athn_softc *);
+#endif /* notyet */
+
+PUBLIC int
+athn_attach(struct athn_softc *sc)
+{
+ struct ieee80211com *ic = &sc->sc_ic;
+ struct ifnet *ifp = &sc->sc_if;
+ size_t max_nnodes;
+ int error;
+
+ /* Read hardware revision. */
+ athn_get_chipid(sc);
+
+ if ((error = athn_reset_power_on(sc)) != 0) {
+ aprint_error_dev(sc->sc_dev, "could not reset chip\n");
+ return error;
+ }
+
+ if ((error = athn_set_power_awake(sc)) != 0) {
+ aprint_error_dev(sc->sc_dev, "could not wakeup chip\n");
+ return error;
+ }
+
+ if (AR_SREV_5416(sc) || AR_SREV_9160(sc))
+ error = ar5416_attach(sc);
+ else if (AR_SREV_9280(sc))
+ error = ar9280_attach(sc);
+ else if (AR_SREV_9285(sc))
+ error = ar9285_attach(sc);
+#if NATHN_USB > 0
+ else if (AR_SREV_9271(sc))
+ error = ar9285_attach(sc);
+#endif
+ else if (AR_SREV_9287(sc))
+ error = ar9287_attach(sc);
+ else if (AR_SREV_9380(sc) || AR_SREV_9485(sc))
+ error = ar9380_attach(sc);
+ else
+ error = ENOTSUP;
+ if (error != 0) {
+ aprint_error_dev(sc->sc_dev, "could not attach chip\n");
+ return error;
+ }
+
+ pmf_self_suspensor_init(sc->sc_dev, &sc->sc_suspensor, &sc->sc_qual);
+
+ /* We can put the chip in sleep state now. */
+ athn_set_power_sleep(sc);
+
+ if (!(sc->sc_flags & ATHN_FLAG_USB)) {
+ error = sc->sc_ops.dma_alloc(sc);
+ if (error != 0) {
+ aprint_error_dev(sc->sc_dev,
+ "could not allocate DMA resources\n");
+ return error;
+ }
+ /* Steal one Tx buffer for beacons. */
+ sc->sc_bcnbuf = SIMPLEQ_FIRST(&sc->sc_txbufs);
+ SIMPLEQ_REMOVE_HEAD(&sc->sc_txbufs, bf_list);
+ }
+
+ if (sc->sc_flags & ATHN_FLAG_RFSILENT) {
+ DPRINTFN(DBG_INIT, sc,
+ "found RF switch connected to GPIO pin %d\n",
+ sc->sc_rfsilent_pin);
+ }
+ DPRINTFN(DBG_INIT, sc, "%zd key cache entries\n", sc->sc_kc_entries);
+
+ /*
+ * In HostAP mode, the number of STAs that we can handle is
+ * limited by the number of entries in the HW key cache.
+ * TKIP keys consume 2 entries in the cache.
+ */
+ KASSERT(sc->sc_kc_entries / 2 > IEEE80211_WEP_NKID);
+ max_nnodes = (sc->sc_kc_entries / 2) - IEEE80211_WEP_NKID;
+ if (sc->sc_max_aid != 0) /* we have an override */
+ ic->ic_max_aid = sc->sc_max_aid;
+ if (ic->ic_max_aid > max_nnodes)
+ ic->ic_max_aid = max_nnodes;
+
+ DPRINTFN(DBG_INIT, sc, "using %s loop power control\n",
+ (sc->sc_flags & ATHN_FLAG_OLPC) ? "open" : "closed");
+ DPRINTFN(DBG_INIT, sc, "txchainmask=0x%x rxchainmask=0x%x\n",
+ sc->sc_txchainmask, sc->sc_rxchainmask);
+
+ /* Count the number of bits set (in lowest 3 bits). */
+ sc->sc_ntxchains =
+ ((sc->sc_txchainmask >> 2) & 1) +
+ ((sc->sc_txchainmask >> 1) & 1) +
+ ((sc->sc_txchainmask >> 0) & 1);
+ sc->sc_nrxchains =
+ ((sc->sc_rxchainmask >> 2) & 1) +
+ ((sc->sc_rxchainmask >> 1) & 1) +
+ ((sc->sc_rxchainmask >> 0) & 1);
+
+ if (AR_SINGLE_CHIP(sc)) {
+ aprint_normal_dev(sc->sc_dev,
+ "%s rev %d (%dT%dR), ROM rev %d, address %s\n",
+ athn_get_mac_name(sc), sc->sc_mac_rev,
+ sc->sc_ntxchains, sc->sc_nrxchains, sc->sc_eep_rev,
+ ether_sprintf(ic->ic_myaddr));
+ }
+ else {
+ aprint_normal_dev(sc->sc_dev,
+ "MAC %s rev %d, RF %s (%dT%dR), ROM rev %d, address %s\n",
+ athn_get_mac_name(sc), sc->sc_mac_rev,
+ athn_get_rf_name(sc), sc->sc_ntxchains, sc->sc_nrxchains,
+ sc->sc_eep_rev, ether_sprintf(ic->ic_myaddr));
+ }
+
+ callout_init(&sc->sc_scan_to, 0);
+ callout_setfunc(&sc->sc_scan_to, athn_next_scan, sc);
+ callout_init(&sc->sc_calib_to, 0);
+ callout_setfunc(&sc->sc_calib_to, athn_calib_to, sc);
+
+ sc->sc_amrr.amrr_min_success_threshold = 1;
+ sc->sc_amrr.amrr_max_success_threshold = 15;
+
+ ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */
+ ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */
+ ic->ic_state = IEEE80211_S_INIT;
+
+ /* Set device capabilities. */
+ ic->ic_caps =
+ IEEE80211_C_WPA | /* 802.11i */
+#ifndef IEEE80211_STA_ONLY
+ IEEE80211_C_HOSTAP | /* Host AP mode supported. */
+// XXX? IEEE80211_C_APPMGT | /* Host AP power saving supported. */
+#endif
+ IEEE80211_C_MONITOR | /* Monitor mode supported. */
+ IEEE80211_C_SHSLOT | /* Short slot time supported. */
+ IEEE80211_C_SHPREAMBLE | /* Short preamble supported. */
+ IEEE80211_C_PMGT; /* Power saving supported. */
+
+#ifndef IEEE80211_NO_HT
+ if (sc->sc_flags & ATHN_FLAG_11N) {
+ int i, ntxstreams, nrxstreams;
+
+ /* Set HT capabilities. */
+ ic->ic_htcaps =
+ IEEE80211_HTCAP_SMPS_DIS |
+ IEEE80211_HTCAP_CBW20_40 |
+ IEEE80211_HTCAP_SGI40 |
+ IEEE80211_HTCAP_DSSSCCK40;
+ if (AR_SREV_9271(sc) || AR_SREV_9287_10_OR_LATER(sc))
+ ic->ic_htcaps |= IEEE80211_HTCAP_SGI20;
+ if (AR_SREV_9380_10_OR_LATER(sc))
+ ic->ic_htcaps |= IEEE80211_HTCAP_LDPC;
+ if (AR_SREV_9280_10_OR_LATER(sc)) {
+ ic->ic_htcaps |= IEEE80211_HTCAP_TXSTBC;
+ ic->ic_htcaps |= 1 << IEEE80211_HTCAP_RXSTBC_SHIFT;
+ }
+ ntxstreams = sc->sc_ntxchains;
+ nrxstreams = sc->sc_nrxchains;
+ if (!AR_SREV_9380_10_OR_LATER(sc)) {
+ ntxstreams = MIN(ntxstreams, 2);
+ nrxstreams = MIN(nrxstreams, 2);
+ }
+ /* Set supported HT rates. */
+ for (i = 0; i < nrxstreams; i++)
+ ic->ic_sup_mcs[i] = 0xff;
+ /* Set the "Tx MCS Set Defined" bit. */
+ ic->ic_sup_mcs[12] |= 0x01;
+ if (ntxstreams != nrxstreams) {
+ /* Set "Tx Rx MCS Set Not Equal" bit. */
+ ic->ic_sup_mcs[12] |= 0x02;
+ ic->ic_sup_mcs[12] |= (ntxstreams - 1) << 2;
+ }
+ }
+#endif
+
+ /* Set supported rates. */
+ if (sc->sc_flags & ATHN_FLAG_11G) {
+ ic->ic_sup_rates[IEEE80211_MODE_11B] =
+ ieee80211_std_rateset_11b;
+ ic->ic_sup_rates[IEEE80211_MODE_11G] =
+ ieee80211_std_rateset_11g;
+ }
+ if (sc->sc_flags & ATHN_FLAG_11A) {
+ ic->ic_sup_rates[IEEE80211_MODE_11A] =
+ ieee80211_std_rateset_11a;
+ }
+
+ /* Get the list of authorized/supported channels. */
+ athn_get_chanlist(sc);
+
+ ifp->if_softc = sc;
+ ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
+ ifp->if_init = athn_init;
+ ifp->if_ioctl = athn_ioctl;
+ ifp->if_start = athn_start;
+ ifp->if_watchdog = athn_watchdog;
+ IFQ_SET_READY(&ifp->if_snd);
+ memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ);
+
+ if_attach(ifp);
+ ieee80211_ifattach(ic);
+
+ ic->ic_node_alloc = athn_node_alloc;
+ ic->ic_newassoc = athn_newassoc;
+ if (ic->ic_updateslot == NULL)
+ ic->ic_updateslot = athn_updateslot;
+#ifdef notyet_edca
+ ic->ic_updateedca = athn_updateedca;
+#endif
+#ifdef notyet
+ ic->ic_set_key = athn_set_key;
+ ic->ic_delete_key = athn_delete_key;
+#endif
+
+ /* Override 802.11 state transition machine. */
+ sc->sc_newstate = ic->ic_newstate;
+ ic->ic_newstate = athn_newstate;
+
+ if (sc->sc_media_change == NULL)
+ sc->sc_media_change = athn_media_change;
+ ieee80211_media_init(ic, sc->sc_media_change, ieee80211_media_status);
+
+ athn_radiotap_attach(sc);
+ return 0;
+}
+
+PUBLIC void
+athn_detach(struct athn_softc *sc)
+{
+ struct ifnet *ifp = &sc->sc_if;
+ int qid;
+
+ callout_halt(&sc->sc_scan_to, NULL);
+ callout_halt(&sc->sc_calib_to, NULL);
+
+ if (!(sc->sc_flags & ATHN_FLAG_USB)) {
+ for (qid = 0; qid < ATHN_QID_COUNT; qid++)
+ athn_tx_reclaim(sc, qid);
+
+ /* Free Tx/Rx DMA resources. */
+ sc->sc_ops.dma_free(sc);
+ }
+ /* Free ROM copy. */
+ if (sc->sc_eep != NULL) {
+ free(sc->sc_eep, M_DEVBUF);
+ sc->sc_eep = NULL;
+ }
+
+ bpf_detach(ifp);
+ ieee80211_ifdetach(&sc->sc_ic);
+ if_detach(ifp);
+
+ callout_destroy(&sc->sc_scan_to);
+ callout_destroy(&sc->sc_calib_to);
+}
+
+/*
+ * Attach the interface to 802.11 radiotap.
+ */
+Static void
+athn_radiotap_attach(struct athn_softc *sc)
+{
+
+ bpf_attach2(&sc->sc_if, DLT_IEEE802_11_RADIO,
+ sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN,
+ &sc->sc_drvbpf);
+
+ sc->sc_rxtap_len = sizeof(sc->sc_rxtapu);
+ sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len);
+ sc->sc_rxtap.wr_ihdr.it_present = htole32(ATHN_RX_RADIOTAP_PRESENT);
+
+ sc->sc_txtap_len = sizeof(sc->sc_txtapu);
+ sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len);
+ sc->sc_txtap.wt_ihdr.it_present = htole32(ATHN_TX_RADIOTAP_PRESENT);
+}
+
+Static void
+athn_get_chanlist(struct athn_softc *sc)
+{
+ struct ieee80211com *ic = &sc->sc_ic;
+ uint8_t chan;
+ size_t i;
+
+ if (sc->sc_flags & ATHN_FLAG_11G) {
+ for (i = 1; i <= 14; i++) {
+ chan = i;
+ ic->ic_channels[chan].ic_freq =
+ ieee80211_ieee2mhz(chan, IEEE80211_CHAN_2GHZ);
+ ic->ic_channels[chan].ic_flags =
+ IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM |
+ IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ;
+ }
+ }
+ if (sc->sc_flags & ATHN_FLAG_11A) {
+ for (i = 0; i < __arraycount(athn_5ghz_chans); i++) {
+ chan = athn_5ghz_chans[i];
+ ic->ic_channels[chan].ic_freq =
+ ieee80211_ieee2mhz(chan, IEEE80211_CHAN_5GHZ);
+ ic->ic_channels[chan].ic_flags = IEEE80211_CHAN_A;
+ }
+ }
+}
+
+PUBLIC void
+athn_rx_start(struct athn_softc *sc)
+{
+ struct ieee80211com *ic = &sc->sc_ic;
+ uint32_t rfilt;
+
+ /* Setup Rx DMA descriptors. */
+ sc->sc_ops.rx_enable(sc);
+
+ /* Set Rx filter. */
+ rfilt = AR_RX_FILTER_UCAST | AR_RX_FILTER_BCAST | AR_RX_FILTER_MCAST;
+#ifndef IEEE80211_NO_HT
+ /* Want Compressed Block Ack Requests. */
+ rfilt |= AR_RX_FILTER_COMPR_BAR;
+#endif
+ rfilt |= AR_RX_FILTER_BEACON;
+ if (ic->ic_opmode != IEEE80211_M_STA) {
+ rfilt |= AR_RX_FILTER_PROBEREQ;
+ if (ic->ic_opmode == IEEE80211_M_MONITOR)
+ rfilt |= AR_RX_FILTER_PROM;
+#ifndef IEEE80211_STA_ONLY
+ if (AR_SREV_9280_10_OR_LATER(sc) &&
+ ic->ic_opmode == IEEE80211_M_HOSTAP)
+ rfilt |= AR_RX_FILTER_PSPOLL;
+#endif
+ }
+ athn_set_rxfilter(sc, rfilt);
+
+ /* Set BSSID mask. */
+ AR_WRITE(sc, AR_BSSMSKL, 0xffffffff);
+ AR_WRITE(sc, AR_BSSMSKU, 0xffff);
+
+ athn_set_opmode(sc);
+
+ /* Set multicast filter. */
+ AR_WRITE(sc, AR_MCAST_FIL0, 0xffffffff);
+ AR_WRITE(sc, AR_MCAST_FIL1, 0xffffffff);
+
+ AR_WRITE(sc, AR_FILT_OFDM, 0);
+ AR_WRITE(sc, AR_FILT_CCK, 0);
+ AR_WRITE(sc, AR_MIBC, 0);
+ AR_WRITE(sc, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
+ AR_WRITE(sc, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
+
+ /* XXX ANI. */
+ AR_WRITE(sc, AR_PHY_ERR_1, 0);
+ AR_WRITE(sc, AR_PHY_ERR_2, 0);
+
+ /* Disable HW crypto for now. */
+ AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_ENCRYPT_DIS | AR_DIAG_DECRYPT_DIS);
+
+ /* Start PCU Rx. */
+ AR_CLRBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT);
+ AR_WRITE_BARRIER(sc);
+}
+
+PUBLIC void
+athn_set_rxfilter(struct athn_softc *sc, uint32_t rfilt)
+{
+
+ AR_WRITE(sc, AR_RX_FILTER, rfilt);
+#ifdef notyet
+ reg = AR_READ(sc, AR_PHY_ERR);
+ reg &= (AR_PHY_ERR_RADAR | AR_PHY_ERR_OFDM_TIMING |
+ AR_PHY_ERR_CCK_TIMING);
+ AR_WRITE(sc, AR_PHY_ERR, reg);
+ if (reg != 0)
+ AR_SETBITS(sc, AR_RXCFG, AR_RXCFG_ZLFDMA);
+ else
+ AR_CLRBITS(sc, AR_RXCFG, AR_RXCFG_ZLFDMA);
+#else
+ AR_WRITE(sc, AR_PHY_ERR, 0);
+ AR_CLRBITS(sc, AR_RXCFG, AR_RXCFG_ZLFDMA);
+#endif
+ AR_WRITE_BARRIER(sc);
+}
+
+PUBLIC int
+athn_intr(void *xsc)
+{
+ struct athn_softc *sc = xsc;
+ struct ifnet *ifp = &sc->sc_if;
+
+ if (!IS_UP_AND_RUNNING(ifp))
+ return 0;
+
+ return sc->sc_ops.intr(sc);
+}
+
+Static void
+athn_get_chipid(struct athn_softc *sc)
+{
+ uint32_t reg;
+
+ reg = AR_READ(sc, AR_SREV);
+ if (MS(reg, AR_SREV_ID) == 0xff) {
+ sc->sc_mac_ver = MS(reg, AR_SREV_VERSION2);
+ sc->sc_mac_rev = MS(reg, AR_SREV_REVISION2);
+ if (!(reg & AR_SREV_TYPE2_HOST_MODE))
+ sc->sc_flags |= ATHN_FLAG_PCIE;
+ }
+ else {
+ sc->sc_mac_ver = MS(reg, AR_SREV_VERSION);
+ sc->sc_mac_rev = MS(reg, AR_SREV_REVISION);
+ if (sc->sc_mac_ver == AR_SREV_VERSION_5416_PCIE)
+ sc->sc_flags |= ATHN_FLAG_PCIE;
+ }
+}
+
+Static const char *
+athn_get_mac_name(struct athn_softc *sc)
+{
+
+ switch (sc->sc_mac_ver) {
+ case AR_SREV_VERSION_5416_PCI:
+ return "AR5416";
+ case AR_SREV_VERSION_5416_PCIE:
+ return "AR5418";
+ case AR_SREV_VERSION_9160:
+ return "AR9160";
+ case AR_SREV_VERSION_9280:
+ return "AR9280";
+ case AR_SREV_VERSION_9285:
+ return "AR9285";
+ case AR_SREV_VERSION_9271:
+ return "AR9271";
+ case AR_SREV_VERSION_9287:
+ return "AR9287";
+ case AR_SREV_VERSION_9380:
+ return "AR9380";
+ case AR_SREV_VERSION_9485:
+ return "AR9485";
+ default:
+ return "unknown";
+ }
+}
+
+/*
+ * Return RF chip name (not for single-chip solutions).
+ */
+Static const char *
+athn_get_rf_name(struct athn_softc *sc)
+{
+
+ KASSERT(!AR_SINGLE_CHIP(sc));
+
+ switch (sc->sc_rf_rev) {
+ case AR_RAD5133_SREV_MAJOR: /* Dual-band 3T3R. */
+ return "AR5133";
+ case AR_RAD2133_SREV_MAJOR: /* Single-band 3T3R. */
+ return "AR2133";
+ case AR_RAD5122_SREV_MAJOR: /* Dual-band 2T2R. */
+ return "AR5122";
+ case AR_RAD2122_SREV_MAJOR: /* Single-band 2T2R. */
+ return "AR2122";
+ default:
+ return "unknown";
+ }
+}
+
+PUBLIC int
+athn_reset_power_on(struct athn_softc *sc)
+{
+ int ntries;
+
+ /* Set force wake. */
+ AR_WRITE(sc, AR_RTC_FORCE_WAKE,
+ AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
+
+ if (!AR_SREV_9380_10_OR_LATER(sc)) {
+ /* Make sure no DMA is active by doing an AHB reset. */
+ AR_WRITE(sc, AR_RC, AR_RC_AHB);
+ }
+ /* RTC reset and clear. */
+ AR_WRITE(sc, AR_RTC_RESET, 0);
+ AR_WRITE_BARRIER(sc);
+ DELAY(2);
+ if (!AR_SREV_9380_10_OR_LATER(sc))
+ AR_WRITE(sc, AR_RC, 0);
+ AR_WRITE(sc, AR_RTC_RESET, 1);
+
+ /* Poll until RTC is ON. */
+ for (ntries = 0; ntries < 1000; ntries++) {
+ if ((AR_READ(sc, AR_RTC_STATUS) & AR_RTC_STATUS_M) ==
+ AR_RTC_STATUS_ON)
+ break;
+ DELAY(10);
+ }
+ if (ntries == 1000) {
+ DPRINTFN(DBG_INIT, sc, "RTC not waking up\n");
+ return ETIMEDOUT;
+ }
+ return athn_reset(sc, 0);
+}
+
+PUBLIC int
+athn_reset(struct athn_softc *sc, int cold_reset)
+{
+ int ntries;
+
+ /* Set force wake. */
+ AR_WRITE(sc, AR_RTC_FORCE_WAKE,
+ AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
+
+ if (AR_READ(sc, AR_INTR_SYNC_CAUSE) &
+ (AR_INTR_SYNC_LOCAL_TIMEOUT | AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
+ AR_WRITE(sc, AR_INTR_SYNC_ENABLE, 0);
+ AR_WRITE(sc, AR_RC, AR_RC_HOSTIF |
+ (!AR_SREV_9380_10_OR_LATER(sc) ? AR_RC_AHB : 0));
+ }
+ else if (!AR_SREV_9380_10_OR_LATER(sc))
+ AR_WRITE(sc, AR_RC, AR_RC_AHB);
+
+ AR_WRITE(sc, AR_RTC_RC, AR_RTC_RC_MAC_WARM |
+ (cold_reset ? AR_RTC_RC_MAC_COLD : 0));
+ AR_WRITE_BARRIER(sc);
+ DELAY(50);
+ AR_WRITE(sc, AR_RTC_RC, 0);
+ for (ntries = 0; ntries < 1000; ntries++) {
+ if (!(AR_READ(sc, AR_RTC_RC) &
+ (AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD)))
+ break;
+ DELAY(10);
+ }
+ if (ntries == 1000) {
+ DPRINTFN(DBG_INIT, sc, "RTC stuck in MAC reset\n");
+ return ETIMEDOUT;
+ }
+ AR_WRITE(sc, AR_RC, 0);
+ AR_WRITE_BARRIER(sc);
+ return 0;
+}
+
+PUBLIC int
+athn_set_power_awake(struct athn_softc *sc)
+{
+ int ntries, error;
+
+ /* Do a Power-On-Reset if shutdown. */
+ if ((AR_READ(sc, AR_RTC_STATUS) & AR_RTC_STATUS_M) ==
+ AR_RTC_STATUS_SHUTDOWN) {
+ if ((error = athn_reset_power_on(sc)) != 0)
+ return error;
+ if (!AR_SREV_9380_10_OR_LATER(sc))
+ athn_init_pll(sc, NULL);
+ }
+ AR_SETBITS(sc, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
+ AR_WRITE_BARRIER(sc);
+ DELAY(50); /* Give chip the chance to awake. */
+
+ /* Poll until RTC is ON. */
+ for (ntries = 0; ntries < 4000; ntries++) {
+ if ((AR_READ(sc, AR_RTC_STATUS) & AR_RTC_STATUS_M) ==
+ AR_RTC_STATUS_ON)
+ break;
+ DELAY(50);
+ AR_SETBITS(sc, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
+ }
+ if (ntries == 4000) {
+ DPRINTFN(DBG_INIT, sc, "RTC not waking up\n");
+ return ETIMEDOUT;
+ }
+
+ AR_CLRBITS(sc, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
+ AR_WRITE_BARRIER(sc);
+ return 0;
+}
+
+PUBLIC void
+athn_set_power_sleep(struct athn_softc *sc)
+{
+
+ AR_SETBITS(sc, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
+ /* Allow the MAC to go to sleep. */
+ AR_CLRBITS(sc, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
+ if (!AR_SREV_9380_10_OR_LATER(sc))
+ AR_WRITE(sc, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
+ /*
+ * NB: Clearing RTC_RESET_EN when setting the chip to sleep mode
+ * results in high power consumption on AR5416 chipsets.
+ */
+ if (!AR_SREV_5416(sc) && !AR_SREV_9271(sc))
+ AR_CLRBITS(sc, AR_RTC_RESET, AR_RTC_RESET_EN);
+ AR_WRITE_BARRIER(sc);
+}
+
+PUBLIC void
+athn_init_pll(struct athn_softc *sc, const struct ieee80211_channel *c)
+{
+ uint32_t pll;
+
+ if (AR_SREV_9380_10_OR_LATER(sc)) {
+ if (AR_SREV_9485(sc))
+ AR_WRITE(sc, AR_RTC_PLL_CONTROL2, 0x886666);
+ pll = SM(AR_RTC_9160_PLL_REFDIV, 0x5);
+ pll |= SM(AR_RTC_9160_PLL_DIV, 0x2c);
+ }
+ else if (AR_SREV_9280_10_OR_LATER(sc)) {
+ pll = SM(AR_RTC_9160_PLL_REFDIV, 0x05);
+ if (c != NULL && IEEE80211_IS_CHAN_5GHZ(c)) {
+ if (sc->sc_flags & ATHN_FLAG_FAST_PLL_CLOCK)
+ pll = 0x142c;
+ else if (AR_SREV_9280_20(sc))
+ pll = 0x2850;
+ else
+ pll |= SM(AR_RTC_9160_PLL_DIV, 0x28);
+ }
+ else
+ pll |= SM(AR_RTC_9160_PLL_DIV, 0x2c);
+ }
+ else if (AR_SREV_9160_10_OR_LATER(sc)) {
+ pll = SM(AR_RTC_9160_PLL_REFDIV, 0x05);
+ if (c != NULL && IEEE80211_IS_CHAN_5GHZ(c))
+ pll |= SM(AR_RTC_9160_PLL_DIV, 0x50);
+ else
+ pll |= SM(AR_RTC_9160_PLL_DIV, 0x58);
+ }
+ else {
+ pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
+ if (c != NULL && IEEE80211_IS_CHAN_5GHZ(c))
+ pll |= SM(AR_RTC_PLL_DIV, 0x0a);
+ else
+ pll |= SM(AR_RTC_PLL_DIV, 0x0b);
+ }
+ DPRINTFN(DBG_INIT, sc, "AR_RTC_PLL_CONTROL=0x%08x\n", pll);
+ AR_WRITE(sc, AR_RTC_PLL_CONTROL, pll);
+ if (AR_SREV_9271(sc)) {
+ /* Switch core clock to 117MHz. */
+ AR_WRITE_BARRIER(sc);
+ DELAY(500);
+ AR_WRITE(sc, 0x50050, 0x304);
+ }
+ AR_WRITE_BARRIER(sc);
+ DELAY(100);
+ AR_WRITE(sc, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
+ AR_WRITE_BARRIER(sc);
+}
+
+Static void
+athn_write_serdes(struct athn_softc *sc, const struct athn_serdes *serdes)
+{
+ int i;
+
+ /* Write sequence to Serializer/Deserializer. */
+ for (i = 0; i < serdes->nvals; i++)
+ AR_WRITE(sc, serdes->regs[i], serdes->vals[i]);
+ AR_WRITE_BARRIER(sc);
+}
+
+PUBLIC void
+athn_config_pcie(struct athn_softc *sc)
+{
+
+ /* Disable PLL when in L0s as well as receiver clock when in L1. */
+ athn_write_serdes(sc, sc->sc_serdes);
+
+ DELAY(1000);
+ /* Allow forcing of PCIe core into L1 state. */
+ AR_SETBITS(sc, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
+
+#ifndef ATHN_PCIE_WAEN
+ AR_WRITE(sc, AR_WA, sc->sc_workaround);
+#else
+ AR_WRITE(sc, AR_WA, ATHN_PCIE_WAEN);
+#endif
+ AR_WRITE_BARRIER(sc);
+}
+
+/*
+ * Serializer/Deserializer programming for non-PCIe devices.
+ */
+static const uint32_t ar_nonpcie_serdes_regs[] = {
+ AR_PCIE_SERDES,
+ AR_PCIE_SERDES,
+ AR_PCIE_SERDES,
+ AR_PCIE_SERDES,
+ AR_PCIE_SERDES,
+ AR_PCIE_SERDES,
+ AR_PCIE_SERDES,
+ AR_PCIE_SERDES,
+ AR_PCIE_SERDES,
+ AR_PCIE_SERDES2,
+};
+
+static const uint32_t ar_nonpcie_serdes_vals[] = {
+ 0x9248fc00,
+ 0x24924924,
+ 0x28000029,
+ 0x57160824,
+ 0x25980579,
+ 0x00000000,
+ 0x1aaabe40,
+ 0xbe105554,
+ 0x000e1007,
+ 0x00000000
+};
+
+static const struct athn_serdes ar_nonpcie_serdes = {
+ __arraycount(ar_nonpcie_serdes_vals),
+ ar_nonpcie_serdes_regs,
+ ar_nonpcie_serdes_vals
+};
+
+PUBLIC void
+athn_config_nonpcie(struct athn_softc *sc)
+{
+
+ athn_write_serdes(sc, &ar_nonpcie_serdes);
+}
+
+PUBLIC int
+athn_set_chan(struct athn_softc *sc, struct ieee80211_channel *curchan,
+ struct ieee80211_channel *extchan)
+{
+ struct athn_ops *ops = &sc->sc_ops;
+ int error, qid;
+
+ /* Check that Tx is stopped, otherwise RF Bus grant will not work. */
+ for (qid = 0; qid < ATHN_QID_COUNT; qid++)
+ if (athn_tx_pending(sc, qid))
+ return EBUSY;
+
+ /* Request RF Bus grant. */
+ if ((error = ops->rf_bus_request(sc)) != 0)
+ return error;
+
+ ops->set_phy(sc, curchan, extchan);
+
+ /* Change the synthesizer. */
+ if ((error = ops->set_synth(sc, curchan, extchan)) != 0)
+ return error;
+
+ sc->sc_curchan = curchan;
+ sc->sc_curchanext = extchan;
+
+ /* Set transmit power values for new channel. */
+ ops->set_txpower(sc, curchan, extchan);
+
+ /* Release the RF Bus grant. */
+ ops->rf_bus_release(sc);
+
+ /* Write delta slope coeffs for modes where OFDM may be used. */
+ if (sc->sc_ic.ic_curmode != IEEE80211_MODE_11B)
+ ops->set_delta_slope(sc, curchan, extchan);
+
+ ops->spur_mitigate(sc, curchan, extchan);
+ /* XXX Load noisefloor values and start calibration. */
+
+ return 0;
+}
+
+Static int
+athn_switch_chan(struct athn_softc *sc, struct ieee80211_channel *curchan,
+ struct ieee80211_channel *extchan)
+{
+ int error, qid;
+
+ /* Disable interrupts. */
+ athn_disable_interrupts(sc);
+
+ /* Stop all Tx queues. */
+ for (qid = 0; qid < ATHN_QID_COUNT; qid++)
+ athn_stop_tx_dma(sc, qid);
+ for (qid = 0; qid < ATHN_QID_COUNT; qid++)
+ athn_tx_reclaim(sc, qid);
+
+ /* Stop Rx. */
+ AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT);
+ AR_WRITE(sc, AR_MIBC, AR_MIBC_FMC);
+ AR_WRITE(sc, AR_MIBC, AR_MIBC_CMC);
+ AR_WRITE(sc, AR_FILT_OFDM, 0);
+ AR_WRITE(sc, AR_FILT_CCK, 0);
+ athn_set_rxfilter(sc, 0);
+ error = athn_stop_rx_dma(sc);
+ if (error != 0)
+ goto reset;
+
+#ifdef notyet
+ /* AR9280 needs a full reset. */
+ if (AR_SREV_9280(sc))
+#endif
+ goto reset;
+
+ /* If band or bandwidth changes, we need to do a full reset. */
+ if (curchan->ic_flags != sc->sc_curchan->ic_flags ||
+ ((extchan != NULL) ^ (sc->sc_curchanext != NULL))) {
+ DPRINTFN(DBG_RF, sc, "channel band switch\n");
+ goto reset;
+ }
+ error = athn_set_power_awake(sc);
+ if (error != 0)
+ goto reset;
+
+ error = athn_set_chan(sc, curchan, extchan);
+ if (error != 0) {
+ reset: /* Error found, try a full reset. */
+ DPRINTFN(DBG_RF, sc, "needs a full reset\n");
+ error = athn_hw_reset(sc, curchan, extchan, 0);
+ if (error != 0) /* Hopeless case. */
+ return error;
+ }
+ athn_rx_start(sc);
+
+ /* Re-enable interrupts. */
+ athn_enable_interrupts(sc);
+ return 0;
+}
+
+PUBLIC void
+athn_get_delta_slope(uint32_t coeff, uint32_t *exponent, uint32_t *mantissa)
+{
+#define COEFF_SCALE_SHIFT 24
+ uint32_t exp, man;
+
+ /* exponent = 14 - floor(log2(coeff)) */
+ for (exp = 31; exp > 0; exp--)
+ if (coeff & (1 << exp))
+ break;
+ exp = 14 - (exp - COEFF_SCALE_SHIFT);
+
+ /* mantissa = floor(coeff * 2^exponent + 0.5) */
+ man = coeff + (1 << (COEFF_SCALE_SHIFT - exp - 1));
+
+ *mantissa = man >> (COEFF_SCALE_SHIFT - exp);
+ *exponent = exp - 16;
+#undef COEFF_SCALE_SHIFT
+}
+
+PUBLIC void
+athn_reset_key(struct athn_softc *sc, int entry)
+{
+
+ /*
+ * NB: Key cache registers access special memory area that requires
+ * two 32-bit writes to actually update the values in the internal
+ * memory. Consequently, writes must be grouped by pair.
+ */
+ AR_WRITE(sc, AR_KEYTABLE_KEY0(entry), 0);
+ AR_WRITE(sc, AR_KEYTABLE_KEY1(entry), 0);
+
+ AR_WRITE(sc, AR_KEYTABLE_KEY2(entry), 0);
+ AR_WRITE(sc, AR_KEYTABLE_KEY3(entry), 0);
+
+ AR_WRITE(sc, AR_KEYTABLE_KEY4(entry), 0);
+ AR_WRITE(sc, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
+
+ AR_WRITE(sc, AR_KEYTABLE_MAC0(entry), 0);
+ AR_WRITE(sc, AR_KEYTABLE_MAC1(entry), 0);
+
+ AR_WRITE_BARRIER(sc);
+}
+
+#ifdef notyet
+Static int
+athn_set_key(struct ieee80211com *ic, struct ieee80211_node *ni,
+ struct ieee80211_key *k)
+{
+ struct athn_softc *sc = ic->ic_ifp->if_softc;
+ const uint8_t *txmic, *rxmic, *key, *addr;
+ uintptr_t entry, micentry;
+ uint32_t type, lo, hi;
+
+ switch (k->k_cipher) {
+ case IEEE80211_CIPHER_WEP40:
+ type = AR_KEYTABLE_TYPE_40;
+ break;
+ case IEEE80211_CIPHER_WEP104:
+ type = AR_KEYTABLE_TYPE_104;
+ break;
+ case IEEE80211_CIPHER_TKIP:
+ type = AR_KEYTABLE_TYPE_TKIP;
+ break;
+ case IEEE80211_CIPHER_CCMP:
+ type = AR_KEYTABLE_TYPE_CCM;
+ break;
+ default:
+ /* Fallback to software crypto for other ciphers. */
+ return ieee80211_set_key(ic, ni, k);
+ }
+
+ if (!(k->k_flags & IEEE80211_KEY_GROUP))
+ entry = IEEE80211_WEP_NKID + IEEE80211_AID(ni->ni_associd);
+ else
+ entry = k->k_id;
+ k->k_priv = (void *)entry;
+
+ /* NB: See note about key cache registers access above. */
+ key = k->k_key;
+ if (type == AR_KEYTABLE_TYPE_TKIP) {
+#ifndef IEEE80211_STA_ONLY
+ if (ic->ic_opmode == IEEE80211_M_HOSTAP) {
+ txmic = &key[16];
+ rxmic = &key[24];
+ }
+ else
+#endif
+ {
+ rxmic = &key[16];
+ txmic = &key[24];
+ }
+ /* Tx+Rx MIC key is at entry + 64. */
+ micentry = entry + 64;
+ AR_WRITE(sc, AR_KEYTABLE_KEY0(micentry), LE_READ_4(&rxmic[0]));
+ AR_WRITE(sc, AR_KEYTABLE_KEY1(micentry), LE_READ_2(&txmic[2]));
+
+ AR_WRITE(sc, AR_KEYTABLE_KEY2(micentry), LE_READ_4(&rxmic[4]));
+ AR_WRITE(sc, AR_KEYTABLE_KEY3(micentry), LE_READ_2(&txmic[0]));
+
+ AR_WRITE(sc, AR_KEYTABLE_KEY4(micentry), LE_READ_4(&txmic[4]));
+ AR_WRITE(sc, AR_KEYTABLE_TYPE(micentry), AR_KEYTABLE_TYPE_CLR);
+ }
+ AR_WRITE(sc, AR_KEYTABLE_KEY0(entry), LE_READ_4(&key[ 0]));
+ AR_WRITE(sc, AR_KEYTABLE_KEY1(entry), LE_READ_2(&key[ 4]));
+
+ AR_WRITE(sc, AR_KEYTABLE_KEY2(entry), LE_READ_4(&key[ 6]));
+ AR_WRITE(sc, AR_KEYTABLE_KEY3(entry), LE_READ_2(&key[10]));
+
+ AR_WRITE(sc, AR_KEYTABLE_KEY4(entry), LE_READ_4(&key[12]));
+ AR_WRITE(sc, AR_KEYTABLE_TYPE(entry), type);
+
+ if (!(k->k_flags & IEEE80211_KEY_GROUP)) {
+ addr = ni->ni_macaddr;
+ lo = LE_READ_4(&addr[0]);
+ hi = LE_READ_2(&addr[4]);
+ lo = lo >> 1 | hi << 31;
+ hi = hi >> 1;
+ }
+ else
+ lo = hi = 0;
+ AR_WRITE(sc, AR_KEYTABLE_MAC0(entry), lo);
+ AR_WRITE(sc, AR_KEYTABLE_MAC1(entry), hi | AR_KEYTABLE_VALID);
+ AR_WRITE_BARRIER(sc);
+ return 0;
+}
+
+Static void
+athn_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni,
+ struct ieee80211_key *k)
+{
+ struct athn_softc *sc = ic->ic_ifp->if_softc;
+ uintptr_t entry;
+
+ switch (k->k_cipher) {
+ case IEEE80211_CIPHER_WEP40:
+ case IEEE80211_CIPHER_WEP104:
+ case IEEE80211_CIPHER_CCMP:
+ entry = (uintptr_t)k->k_priv;
+ athn_reset_key(sc, entry);
+ break;
+ case IEEE80211_CIPHER_TKIP:
+ entry = (uintptr_t)k->k_priv;
+ athn_reset_key(sc, entry);
+ athn_reset_key(sc, entry + 64);
+ break;
+ default:
+ /* Fallback to software crypto for other ciphers. */
+ ieee80211_delete_key(ic, ni, k);
+ }
+}
+#endif /* notyet */
+
+PUBLIC void
+athn_led_init(struct athn_softc *sc)
+{
+ struct athn_ops *ops = &sc->sc_ops;
+
+ ops->gpio_config_output(sc, sc->sc_led_pin, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
+ /* LED off, active low. */
+ athn_set_led(sc, 0);
+}
+
+PUBLIC void
+athn_set_led(struct athn_softc *sc, int on)
+{
+ struct athn_ops *ops = &sc->sc_ops;
+
+ sc->sc_led_state = on;
+ ops->gpio_write(sc, sc->sc_led_pin, !sc->sc_led_state);
+}
+
+#ifdef ATHN_BT_COEXISTENCE
+Static void
+athn_btcoex_init(struct athn_softc *sc)
+{
+ struct athn_ops *ops = &sc->sc_ops;
+ uint32_t reg;
+
+ if (sc->sc_flags & ATHN_FLAG_BTCOEX2WIRE) {
+ /* Connect bt_active to baseband. */
+ AR_CLRBITS(sc, sc->sc_gpio_input_en_off,
+ AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF |
+ AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF);
+ AR_SETBITS(sc, sc->sc_gpio_input_en_off,
+ AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB);
+
+ reg = AR_READ(sc, AR_GPIO_INPUT_MUX1);
+ reg = RW(reg, AR_GPIO_INPUT_MUX1_BT_ACTIVE,
+ AR_GPIO_BTACTIVE_PIN);
+ AR_WRITE(sc, AR_GPIO_INPUT_MUX1, reg);
+ AR_WRITE_BARRIER(sc);
+
+ ops->gpio_config_input(sc, AR_GPIO_BTACTIVE_PIN);
+ }
+ else { /* 3-wire. */
+ AR_SETBITS(sc, sc->sc_gpio_input_en_off,
+ AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB |
+ AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB);
+
+ reg = AR_READ(sc, AR_GPIO_INPUT_MUX1);
+ reg = RW(reg, AR_GPIO_INPUT_MUX1_BT_ACTIVE,
+ AR_GPIO_BTACTIVE_PIN);
+ reg = RW(reg, AR_GPIO_INPUT_MUX1_BT_PRIORITY,
+ AR_GPIO_BTPRIORITY_PIN);
+ AR_WRITE(sc, AR_GPIO_INPUT_MUX1, reg);
+ AR_WRITE_BARRIER(sc);
+
+ ops->gpio_config_input(sc, AR_GPIO_BTACTIVE_PIN);
+ ops->gpio_config_input(sc, AR_GPIO_BTPRIORITY_PIN);
+ }
+}
+
+Static void
+athn_btcoex_enable(struct athn_softc *sc)
+{
+ struct athn_ops *ops = &sc->sc_ops;
+ uint32_t reg;
+
+ if (sc->sc_flags & ATHN_FLAG_BTCOEX3WIRE) {
+ AR_WRITE(sc, AR_BT_COEX_MODE,
+ SM(AR_BT_MODE, AR_BT_MODE_SLOTTED) |
+ SM(AR_BT_PRIORITY_TIME, 2) |
+ SM(AR_BT_FIRST_SLOT_TIME, 5) |
+ SM(AR_BT_QCU_THRESH, ATHN_QID_AC_BE) |
+ AR_BT_TXSTATE_EXTEND | AR_BT_TX_FRAME_EXTEND |
+ AR_BT_QUIET | AR_BT_RX_CLEAR_POLARITY);
+ AR_WRITE(sc, AR_BT_COEX_WEIGHT,
+ SM(AR_BTCOEX_BT_WGHT, AR_STOMP_LOW_BT_WGHT) |
+ SM(AR_BTCOEX_WL_WGHT, AR_STOMP_LOW_WL_WGHT));
+ AR_WRITE(sc, AR_BT_COEX_MODE2,
+ SM(AR_BT_BCN_MISS_THRESH, 50) |
+ AR_BT_HOLD_RX_CLEAR | AR_BT_DISABLE_BT_ANT);
+
+ AR_SETBITS(sc, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE);
+ AR_CLRBITS(sc, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX);
+ AR_WRITE_BARRIER(sc);
+
+ ops->gpio_config_output(sc, AR_GPIO_WLANACTIVE_PIN,
+ AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL);
+
+ }
+ else { /* 2-wire. */
+ ops->gpio_config_output(sc, AR_GPIO_WLANACTIVE_PIN,
+ AR_GPIO_OUTPUT_MUX_AS_TX_FRAME);
+ }
+ reg = AR_READ(sc, AR_GPIO_PDPU);
+ reg &= ~(0x3 << (AR_GPIO_WLANACTIVE_PIN * 2));
+ reg |= 0x2 << (AR_GPIO_WLANACTIVE_PIN * 2);
+ AR_WRITE(sc, AR_GPIO_PDPU, reg);
+ AR_WRITE_BARRIER(sc);
+
+ /* Disable PCIe Active State Power Management (ASPM). */
+ if (sc->sc_disable_aspm != NULL)
+ sc->sc_disable_aspm(sc);
+
+ /* XXX Start periodic timer. */
+}
+
+Static void
+athn_btcoex_disable(struct athn_softc *sc)
+{
+ struct athn_ops *ops = &sc->sc_ops;
+
+ ops->gpio_write(sc, AR_GPIO_WLANACTIVE_PIN, 0);
+
+ ops->gpio_config_output(sc, AR_GPIO_WLANACTIVE_PIN,
+ AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
+
+ if (sc->sc_flags & ATHN_FLAG_BTCOEX3WIRE) {
+ AR_WRITE(sc, AR_BT_COEX_MODE,
+ SM(AR_BT_MODE, AR_BT_MODE_DISABLED) | AR_BT_QUIET);
+ AR_WRITE(sc, AR_BT_COEX_WEIGHT, 0);
+ AR_WRITE(sc, AR_BT_COEX_MODE2, 0);
+ /* XXX Stop periodic timer. */
+ }
+ AR_WRITE_BARRIER(sc);
+ /* XXX Restore ASPM setting? */
+}
+#endif
+
+Static void
+athn_iter_func(void *arg, struct ieee80211_node *ni)
+{
+ struct athn_softc *sc = arg;
+ struct athn_node *an = (struct athn_node *)ni;
+
+ ieee80211_amrr_choose(&sc->sc_amrr, ni, &an->amn);
+}
+
+Static void
+athn_calib_to(void *arg)
+{
+ extern int ticks;
+ struct athn_softc *sc = arg;
+ struct athn_ops *ops = &sc->sc_ops;
+ struct ieee80211com *ic = &sc->sc_ic;
+ int s;
+
+ s = splnet();
+
+ /* Do periodic (every 4 minutes) PA calibration. */
+ if (AR_SREV_9285_11_OR_LATER(sc) &&
+ !AR_SREV_9380_10_OR_LATER(sc) &&
+ ticks >= sc->sc_pa_calib_ticks + 240 * hz) {
+ sc->sc_pa_calib_ticks = ticks;
+ if (AR_SREV_9271(sc))
+ ar9271_pa_calib(sc);
+ else
+ ar9285_pa_calib(sc);
+ }
+
+ /* Do periodic (every 30 seconds) temperature compensation. */
+ if ((sc->sc_flags & ATHN_FLAG_OLPC) &&
+ ticks >= sc->sc_olpc_ticks + 30 * hz) {
+ sc->sc_olpc_ticks = ticks;
+ ops->olpc_temp_compensation(sc);
+ }
+
+#ifdef notyet
+ /* XXX ANI. */
+ athn_ani_monitor(sc);
+
+ ops->next_calib(sc);
+#endif
+ if (ic->ic_fixed_rate == -1) {
+ if (ic->ic_opmode == IEEE80211_M_STA)
+ athn_iter_func(sc, ic->ic_bss);
+ else
+ ieee80211_iterate_nodes(&ic->ic_sta, athn_iter_func, sc);
+ }
+ callout_schedule(&sc->sc_calib_to, hz / 2);
+ splx(s);
+}
+
+Static int
+athn_init_calib(struct athn_softc *sc, struct ieee80211_channel *curchan,
+ struct ieee80211_channel *extchan)
+{
+ struct athn_ops *ops = &sc->sc_ops;
+ int error;
+
+ if (AR_SREV_9380_10_OR_LATER(sc))
+ error = ar9003_init_calib(sc);
+ else if (AR_SREV_9285_10_OR_LATER(sc))
+ error = ar9285_init_calib(sc, curchan, extchan);
+ else
+ error = ar5416_init_calib(sc, curchan, extchan);
+ if (error != 0)
+ return error;
+
+ if (!AR_SREV_9380_10_OR_LATER(sc)) {
+ /* Do PA calibration. */
+ if (AR_SREV_9285_11_OR_LATER(sc)) {
+ extern int ticks;
+ sc->sc_pa_calib_ticks = ticks;
+ if (AR_SREV_9271(sc))
+ ar9271_pa_calib(sc);
+ else
+ ar9285_pa_calib(sc);
+ }
+ /* Do noisefloor calibration. */
+ ops->noisefloor_calib(sc);
+ }
+ if (AR_SREV_9160_10_OR_LATER(sc)) {
+ /* Support IQ calibration. */
+ sc->sc_sup_calib_mask = ATHN_CAL_IQ;
+ if (AR_SREV_9380_10_OR_LATER(sc)) {
+ /* Support temperature compensation calibration. */
+ sc->sc_sup_calib_mask |= ATHN_CAL_TEMP;
+ }
+ else if (IEEE80211_IS_CHAN_5GHZ(curchan) || extchan != NULL) {
+ /*
+ * ADC gain calibration causes uplink throughput
+ * drops in HT40 mode on AR9287.
+ */
+ if (!AR_SREV_9287(sc)) {
+ /* Support ADC gain calibration. */
+ sc->sc_sup_calib_mask |= ATHN_CAL_ADC_GAIN;
+ }
+ /* Support ADC DC offset calibration. */
+ sc->sc_sup_calib_mask |= ATHN_CAL_ADC_DC;
+ }
+ }
+ return 0;
+}
+
+/*
+ * Adaptive noise immunity.
+ */
+#ifdef notyet
+Static int32_t
+athn_ani_get_rssi(struct athn_softc *sc)
+{
+
+ return 0; /* XXX */
+}
+#endif /* notyet */
+
+#ifdef notyet
+Static void
+athn_ani_ofdm_err_trigger(struct athn_softc *sc)
+{
+ struct athn_ani *ani = &sc->sc_ani;
+ struct athn_ops *ops = &sc->sc_ops;
+ int32_t rssi;
+
+ /* First, raise noise immunity level, up to max. */
+ if (ani->noise_immunity_level < 4) {
+ ani->noise_immunity_level++;
+ ops->set_noise_immunity_level(sc, ani->noise_immunity_level);
+ return;
+ }
+
+ /* Then, raise our spur immunity level, up to max. */
+ if (ani->spur_immunity_level < 7) {
+ ani->spur_immunity_level++;
+ ops->set_spur_immunity_level(sc, ani->spur_immunity_level);
+ return;
+ }
+
+#ifndef IEEE80211_STA_ONLY
+ if (sc->sc_ic.ic_opmode == IEEE80211_M_HOSTAP) {
+ if (ani->firstep_level < 2) {
+ ani->firstep_level++;
+ ops->set_firstep_level(sc, ani->firstep_level);
+ }
+ return;
+ }
+#endif
+ rssi = athn_ani_get_rssi(sc);
+ if (rssi > ATHN_ANI_RSSI_THR_HIGH) {
+ /*
+ * Beacon RSSI is high, turn off OFDM weak signal detection
+ * or raise first step level as last resort.
+ */
+ if (ani->ofdm_weak_signal) {
+ ani->ofdm_weak_signal = 0;
+ ops->disable_ofdm_weak_signal(sc);
+ ani->spur_immunity_level = 0;
+ ops->set_spur_immunity_level(sc, 0);
+ }
+ else if (ani->firstep_level < 2) {
+ ani->firstep_level++;
+ ops->set_firstep_level(sc, ani->firstep_level);
+ }
+ }
+ else if (rssi > ATHN_ANI_RSSI_THR_LOW) {
+ /*
+ * Beacon RSSI is in mid range, we need OFDM weak signal
+ * detection but we can raise first step level.
+ */
+ if (!ani->ofdm_weak_signal) {
+ ani->ofdm_weak_signal = 1;
+ ops->enable_ofdm_weak_signal(sc);
+ }
+ if (ani->firstep_level < 2) {
+ ani->firstep_level++;
+ ops->set_firstep_level(sc, ani->firstep_level);
+ }
+ }
+ else if (sc->sc_ic.ic_curmode != IEEE80211_MODE_11A) {
+ /*
+ * Beacon RSSI is low, if in b/g mode, turn off OFDM weak
+ * signal detection and zero first step level to maximize
+ * CCK sensitivity.
+ */
+ if (ani->ofdm_weak_signal) {
+ ani->ofdm_weak_signal = 0;
+ ops->disable_ofdm_weak_signal(sc);
+ }
+ if (ani->firstep_level > 0) {
+ ani->firstep_level = 0;
+ ops->set_firstep_level(sc, 0);
+ }
+ }
+}
+#endif /* notyet */
+
+#ifdef notyet
+Static void
+athn_ani_cck_err_trigger(struct athn_softc *sc)
+{
+ struct athn_ani *ani = &sc->sc_ani;
+ struct athn_ops *ops = &sc->sc_ops;
+ int32_t rssi;
+
+ /* Raise noise immunity level, up to max. */
+ if (ani->noise_immunity_level < 4) {
+ ani->noise_immunity_level++;
+ ops->set_noise_immunity_level(sc, ani->noise_immunity_level);
+ return;
+ }
+
+#ifndef IEEE80211_STA_ONLY
+ if (sc->sc_ic.ic_opmode == IEEE80211_M_HOSTAP) {
+ if (ani->firstep_level < 2) {
+ ani->firstep_level++;
+ ops->set_firstep_level(sc, ani->firstep_level);
+ }
+ return;
+ }
+#endif
+ rssi = athn_ani_get_rssi(sc);
+ if (rssi > ATHN_ANI_RSSI_THR_LOW) {
+ /*
+ * Beacon RSSI is in mid or high range, raise first step
+ * level.
+ */
+ if (ani->firstep_level < 2) {
+ ani->firstep_level++;
+ ops->set_firstep_level(sc, ani->firstep_level);
+ }
+ }
+ else if (sc->sc_ic.ic_curmode != IEEE80211_MODE_11A) {
+ /*
+ * Beacon RSSI is low, zero first step level to maximize
+ * CCK sensitivity.
+ */
+ if (ani->firstep_level > 0) {
+ ani->firstep_level = 0;
+ ops->set_firstep_level(sc, 0);
+ }
+ }
+}
+#endif /* notyet */
+
+#ifdef notyet
+Static void
+athn_ani_lower_immunity(struct athn_softc *sc)
+{
+ struct athn_ani *ani = &sc->sc_ani;
+ struct athn_ops *ops = &sc->sc_ops;
+ int32_t rssi;
+
+#ifndef IEEE80211_STA_ONLY
+ if (sc->sc_ic.ic_opmode == IEEE80211_M_HOSTAP) {
+ if (ani->firstep_level > 0) {
+ ani->firstep_level--;
+ ops->set_firstep_level(sc, ani->firstep_level);
+ }
+ return;
+ }
+#endif
+ rssi = athn_ani_get_rssi(sc);
+ if (rssi > ATHN_ANI_RSSI_THR_HIGH) {
+ /*
+ * Beacon RSSI is high, leave OFDM weak signal detection
+ * off or it may oscillate.
+ */
+ }
+ else if (rssi > ATHN_ANI_RSSI_THR_LOW) {
+ /*
+ * Beacon RSSI is in mid range, turn on OFDM weak signal
+ * detection or lower first step level.
+ */
+ if (!ani->ofdm_weak_signal) {
+ ani->ofdm_weak_signal = 1;
+ ops->enable_ofdm_weak_signal(sc);
+ return;
+ }
+ if (ani->firstep_level > 0) {
+ ani->firstep_level--;
+ ops->set_firstep_level(sc, ani->firstep_level);
+ return;
+ }
+ }
+ else {
+ /* Beacon RSSI is low, lower first step level. */
+ if (ani->firstep_level > 0) {
+ ani->firstep_level--;
+ ops->set_firstep_level(sc, ani->firstep_level);
+ return;
+ }
+ }
+ /*
+ * Lower spur immunity level down to zero, or if all else fails,
+ * lower noise immunity level down to zero.
+ */
+ if (ani->spur_immunity_level > 0) {
+ ani->spur_immunity_level--;
+ ops->set_spur_immunity_level(sc, ani->spur_immunity_level);
+ }
+ else if (ani->noise_immunity_level > 0) {
+ ani->noise_immunity_level--;
+ ops->set_noise_immunity_level(sc, ani->noise_immunity_level);
+ }
+}
+#endif /* notyet */
+
+#ifdef notyet
+Static void
+athn_ani_restart(struct athn_softc *sc)
+{
+ struct athn_ani *ani = &sc->sc_ani;
+
+ AR_WRITE(sc, AR_PHY_ERR_1, 0);
+ AR_WRITE(sc, AR_PHY_ERR_2, 0);
+ AR_WRITE(sc, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
+ AR_WRITE(sc, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
+ AR_WRITE_BARRIER(sc);
+
+ ani->listen_time = 0;
+ ani->ofdm_phy_err_count = 0;
+ ani->cck_phy_err_count = 0;
+}
+#endif /* notyet */
+
+#ifdef notyet
+Static void
+athn_ani_monitor(struct athn_softc *sc)
+{
+ struct athn_ani *ani = &sc->sc_ani;
+ uint32_t cyccnt, txfcnt, rxfcnt, phy1, phy2;
+ int32_t cycdelta, txfdelta, rxfdelta;
+ int32_t listen_time;
+
+ txfcnt = AR_READ(sc, AR_TFCNT); /* Tx frame count. */
+ rxfcnt = AR_READ(sc, AR_RFCNT); /* Rx frame count. */
+ cyccnt = AR_READ(sc, AR_CCCNT); /* Cycle count. */
+
+ if (ani->cyccnt != 0 && ani->cyccnt <= cyccnt) {
+ cycdelta = cyccnt - ani->cyccnt;
+ txfdelta = txfcnt - ani->txfcnt;
+ rxfdelta = rxfcnt - ani->rxfcnt;
+
+ listen_time = (cycdelta - txfdelta - rxfdelta) /
+ (athn_clock_rate(sc) * 1000);
+ }
+ else
+ listen_time = 0;
+
+ ani->cyccnt = cyccnt;
+ ani->txfcnt = txfcnt;
+ ani->rxfcnt = rxfcnt;
+
+ if (listen_time < 0) {
+ athn_ani_restart(sc);
+ return;
+ }
+ ani->listen_time += listen_time;
+
+ phy1 = AR_READ(sc, AR_PHY_ERR_1);
+ phy2 = AR_READ(sc, AR_PHY_ERR_2);
+
+ if (phy1 < ani->ofdm_phy_err_base) {
+ AR_WRITE(sc, AR_PHY_ERR_1, ani->ofdm_phy_err_base);
+ AR_WRITE(sc, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
+ }
+ if (phy2 < ani->cck_phy_err_base) {
+ AR_WRITE(sc, AR_PHY_ERR_2, ani->cck_phy_err_base);
+ AR_WRITE(sc, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
+ }
+ if (phy1 < ani->ofdm_phy_err_base || phy2 < ani->cck_phy_err_base) {
+ AR_WRITE_BARRIER(sc);
+ return;
+ }
+ ani->ofdm_phy_err_count = phy1 - ani->ofdm_phy_err_base;
+ ani->cck_phy_err_count = phy2 - ani->cck_phy_err_base;
+
+ if (ani->listen_time > 5 * ATHN_ANI_PERIOD) {
+ /* Check to see if we need to lower immunity. */
+ if (ani->ofdm_phy_err_count <=
+ ani->listen_time * ani->ofdm_trig_low / 1000 &&
+ ani->cck_phy_err_count <=
+ ani->listen_time * ani->cck_trig_low / 1000)
+ athn_ani_lower_immunity(sc);
+ athn_ani_restart(sc);
+
+ }
+ else if (ani->listen_time > ATHN_ANI_PERIOD) {
+ /* Check to see if we need to raise immunity. */
+ if (ani->ofdm_phy_err_count >
+ ani->listen_time * ani->ofdm_trig_high / 1000) {
+ athn_ani_ofdm_err_trigger(sc);
+ athn_ani_restart(sc);
+ }
+ else if (ani->cck_phy_err_count >
+ ani->listen_time * ani->cck_trig_high / 1000) {
+ athn_ani_cck_err_trigger(sc);
+ athn_ani_restart(sc);
+ }
+ }
+}
+#endif /* notyet */
+
+PUBLIC uint8_t
+athn_chan2fbin(struct ieee80211_channel *c)
+{
+
+ if (IEEE80211_IS_CHAN_2GHZ(c))
+ return c->ic_freq - 2300;
+ else
+ return (c->ic_freq - 4800) / 5;
+}
+
+PUBLIC int
+athn_interpolate(int x, int x1, int y1, int x2, int y2)
+{
+
+ if (x1 == x2) /* Prevents division by zero. */
+ return y1;
+ /* Linear interpolation. */
+ return y1 + ((x - x1) * (y2 - y1)) / (x2 - x1);
+}
+
+PUBLIC void
+athn_get_pier_ival(uint8_t fbin, const uint8_t *pierfreq, int npiers,
+ int *lo, int *hi)
+{
+ int i;
+
+ for (i = 0; i < npiers; i++)
+ if (pierfreq[i] == AR_BCHAN_UNUSED ||
+ pierfreq[i] > fbin)
+ break;
+ *hi = i;
+ *lo = *hi - 1;
+ if (*lo == -1)
+ *lo = *hi;
+ else if (*hi == npiers || pierfreq[*hi] == AR_BCHAN_UNUSED)
+ *hi = *lo;
+}
+
+Static void
+athn_init_dma(struct athn_softc *sc)
+{
+ uint32_t reg;
+
+ if (!AR_SREV_9380_10_OR_LATER(sc)) {
+ /* Set AHB not to do cacheline prefetches. */
+ AR_SETBITS(sc, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN);
+ }
+ reg = AR_READ(sc, AR_TXCFG);
+ /* Let MAC DMA reads be in 128-byte chunks. */
+ reg = RW(reg, AR_TXCFG_DMASZ, AR_DMASZ_128B);
+
+ /* Set initial Tx trigger level. */
+ if (AR_SREV_9285(sc) || AR_SREV_9271(sc))
+ reg = RW(reg, AR_TXCFG_FTRIG, AR_TXCFG_FTRIG_256B);
+ else if (!AR_SREV_9380_10_OR_LATER(sc))
+ reg = RW(reg, AR_TXCFG_FTRIG, AR_TXCFG_FTRIG_512B);
+ AR_WRITE(sc, AR_TXCFG, reg);
+
+ /* Let MAC DMA writes be in 128-byte chunks. */
+ reg = AR_READ(sc, AR_RXCFG);
+ reg = RW(reg, AR_RXCFG_DMASZ, AR_DMASZ_128B);
+ AR_WRITE(sc, AR_RXCFG, reg);
+
+ /* Setup Rx FIFO threshold to hold off Tx activities. */
+ AR_WRITE(sc, AR_RXFIFO_CFG, 512);
+
+ /* Reduce the number of entries in PCU TXBUF to avoid wrap around. */
+ if (AR_SREV_9285(sc)) {
+ AR_WRITE(sc, AR_PCU_TXBUF_CTRL,
+ AR9285_PCU_TXBUF_CTRL_USABLE_SIZE);
+ }
+ else if (!AR_SREV_9271(sc)) {
+ AR_WRITE(sc, AR_PCU_TXBUF_CTRL,
+ AR_PCU_TXBUF_CTRL_USABLE_SIZE);
+ }
+ AR_WRITE_BARRIER(sc);
+
+ /* Reset Tx status ring. */
+ if (AR_SREV_9380_10_OR_LATER(sc))
+ ar9003_reset_txsring(sc);
+}
+
+PUBLIC void
+athn_inc_tx_trigger_level(struct athn_softc *sc)
+{
+ uint32_t reg, ftrig;
+
+ reg = AR_READ(sc, AR_TXCFG);
+ ftrig = MS(reg, AR_TXCFG_FTRIG);
+ /*
+ * NB: The AR9285 and all single-stream parts have an issue that
+ * limits the size of the PCU Tx FIFO to 2KB instead of 4KB.
+ */
+ if (ftrig == ((AR_SREV_9285(sc) || AR_SREV_9271(sc)) ? 0x1f : 0x3f))
+ return; /* Already at max. */
+ reg = RW(reg, AR_TXCFG_FTRIG, ftrig + 1);
+ AR_WRITE(sc, AR_TXCFG, reg);
+ AR_WRITE_BARRIER(sc);
+}
+
+PUBLIC int
+athn_stop_rx_dma(struct athn_softc *sc)
+{
+ int ntries;
+
+ AR_WRITE(sc, AR_CR, AR_CR_RXD);
+ /* Wait for Rx enable bit to go low. */
+ for (ntries = 0; ntries < 100; ntries++) {
+ if (!(AR_READ(sc, AR_CR) & AR_CR_RXE))
+ return 0;
+ DELAY(100);
+ }
+ DPRINTFN(DBG_RX, sc, "Rx DMA failed to stop\n");
+ return ETIMEDOUT;
+}
+
+#ifdef unused
+Static int
+athn_rx_abort(struct athn_softc *sc)
+{
+ int ntries;
+
+ AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT);
+ for (ntries = 0; ntries < 1000; ntries++) {
+ if (MS(AR_READ(sc, AR_OBS_BUS_1), AR_OBS_BUS_1_RX_STATE) == 0)
+ return 0;
+ DELAY(10);
+ }
+ DPRINTFN(DBG_RX, sc, "Rx failed to go idle in 10ms\n");
+ AR_CLRBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT);
+ AR_WRITE_BARRIER(sc);
+ return ETIMEDOUT;
+}
+#endif /* unused */
+
+Static void
+athn_tx_reclaim(struct athn_softc *sc, int qid)
+{
+ struct athn_txq *txq = &sc->sc_txq[qid];
+ struct athn_tx_buf *bf;
+
+ /* Reclaim all buffers queued in the specified Tx queue. */
+ /* NB: Tx DMA must be stopped. */
+ while ((bf = SIMPLEQ_FIRST(&txq->head)) != NULL) {
+ SIMPLEQ_REMOVE_HEAD(&txq->head, bf_list);
+
+ bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0,
+ bf->bf_map->dm_mapsize, BUS_DMASYNC_POSTWRITE);
+ bus_dmamap_unload(sc->sc_dmat, bf->bf_map);
+ m_freem(bf->bf_m);
+ bf->bf_m = NULL;
+ bf->bf_ni = NULL; /* Nodes already freed! */
+
+ /* Link Tx buffer back to global free list. */
+ SIMPLEQ_INSERT_TAIL(&sc->sc_txbufs, bf, bf_list);
+ }
+}
+
+PUBLIC int
+athn_tx_pending(struct athn_softc *sc, int qid)
+{
+
+ return MS(AR_READ(sc, AR_QSTS(qid)), AR_Q_STS_PEND_FR_CNT) != 0 ||
+ (AR_READ(sc, AR_Q_TXE) & (1 << qid)) != 0;
+}
+
+PUBLIC void
+athn_stop_tx_dma(struct athn_softc *sc, int qid)
+{
+ uint32_t tsflo;
+ int ntries, i;
+
+ AR_WRITE(sc, AR_Q_TXD, 1 << qid);
+ for (ntries = 0; ntries < 40; ntries++) {
+ if (!athn_tx_pending(sc, qid))
+ break;
+ DELAY(100);
+ }
+ if (ntries == 40) {
+ for (i = 0; i < 2; i++) {
+ tsflo = AR_READ(sc, AR_TSF_L32) / 1024;
+ AR_WRITE(sc, AR_QUIET2,
+ SM(AR_QUIET2_QUIET_DUR, 10));
+ AR_WRITE(sc, AR_QUIET_PERIOD, 100);
+ AR_WRITE(sc, AR_NEXT_QUIET_TIMER, tsflo);
+ AR_SETBITS(sc, AR_TIMER_MODE, AR_QUIET_TIMER_EN);
+ if (AR_READ(sc, AR_TSF_L32) / 1024 == tsflo)
+ break;
+ }
+ AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
+ AR_WRITE_BARRIER(sc);
+ DELAY(200);
+ AR_CLRBITS(sc, AR_TIMER_MODE, AR_QUIET_TIMER_EN);
+ AR_WRITE_BARRIER(sc);
+
+ for (ntries = 0; ntries < 40; ntries++) {
+ if (!athn_tx_pending(sc, qid))
+ break;
+ DELAY(100);
+ }
+
+ AR_CLRBITS(sc, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
+ }
+ AR_WRITE(sc, AR_Q_TXD, 0);
+ AR_WRITE_BARRIER(sc);
+}
+
+PUBLIC int
+athn_txtime(struct athn_softc *sc, int len, int ridx, u_int flags)
+{
+#define divround(a, b) (((a) + (b) - 1) / (b))
+ int txtime;
+
+ /* XXX HT. */
+ if (athn_rates[ridx].phy == IEEE80211_T_OFDM) {
+ txtime = divround(8 + 4 * len + 3, athn_rates[ridx].rate);
+ /* SIFS is 10us for 11g but Signal Extension adds 6us. */
+ txtime = 16 + 4 + 4 * txtime + 16;
+ }
+ else {
+ txtime = divround(16 * len, athn_rates[ridx].rate);
+ if (ridx != ATHN_RIDX_CCK1 && (flags & IEEE80211_F_SHPREAMBLE))
+ txtime += 72 + 24;
+ else
+ txtime += 144 + 48;
+ txtime += 10; /* 10us SIFS. */
+ }
+ return txtime;
+#undef divround
+}
+
+PUBLIC void
+athn_init_tx_queues(struct athn_softc *sc)
+{
+ int qid;
+
+ for (qid = 0; qid < ATHN_QID_COUNT; qid++) {
+ SIMPLEQ_INIT(&sc->sc_txq[qid].head);
+ sc->sc_txq[qid].lastds = NULL;
+ sc->sc_txq[qid].wait = NULL;
+ sc->sc_txq[qid].queued = 0;
+
+ AR_WRITE(sc, AR_DRETRY_LIMIT(qid),
+ SM(AR_D_RETRY_LIMIT_STA_SH, 32) |
+ SM(AR_D_RETRY_LIMIT_STA_LG, 32) |
+ SM(AR_D_RETRY_LIMIT_FR_SH, 10));
+ AR_WRITE(sc, AR_QMISC(qid),
+ AR_Q_MISC_DCU_EARLY_TERM_REQ);
+ AR_WRITE(sc, AR_DMISC(qid),
+ SM(AR_D_MISC_BKOFF_THRESH, 2) |
+ AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN);
+ }
+
+ /* Init beacon queue. */
+ AR_SETBITS(sc, AR_QMISC(ATHN_QID_BEACON),
+ AR_Q_MISC_FSP_DBA_GATED | AR_Q_MISC_BEACON_USE |
+ AR_Q_MISC_CBR_INCR_DIS1);
+ AR_SETBITS(sc, AR_DMISC(ATHN_QID_BEACON),
+ SM(AR_D_MISC_ARB_LOCKOUT_CNTRL,
+ AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL) |
+ AR_D_MISC_BEACON_USE |
+ AR_D_MISC_POST_FR_BKOFF_DIS);
+ AR_WRITE(sc, AR_DLCL_IFS(ATHN_QID_BEACON),
+ SM(AR_D_LCL_IFS_CWMIN, 0) |
+ SM(AR_D_LCL_IFS_CWMAX, 0) |
+ SM(AR_D_LCL_IFS_AIFS, 1));
+
+ /* Init CAB (Content After Beacon) queue. */
+ AR_SETBITS(sc, AR_QMISC(ATHN_QID_CAB),
+ AR_Q_MISC_FSP_DBA_GATED | AR_Q_MISC_CBR_INCR_DIS1 |
+ AR_Q_MISC_CBR_INCR_DIS0);
+ AR_SETBITS(sc, AR_DMISC(ATHN_QID_CAB),
+ SM(AR_D_MISC_ARB_LOCKOUT_CNTRL,
+ AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL));
+
+ /* Init PS-Poll queue. */
+ AR_SETBITS(sc, AR_QMISC(ATHN_QID_PSPOLL),
+ AR_Q_MISC_CBR_INCR_DIS1);
+
+ /* Init UAPSD queue. */
+ AR_SETBITS(sc, AR_DMISC(ATHN_QID_UAPSD),
+ AR_D_MISC_POST_FR_BKOFF_DIS);
+
+ if (AR_SREV_9380_10_OR_LATER(sc)) {
+ /* Enable MAC descriptor CRC check. */
+ AR_WRITE(sc, AR_Q_DESC_CRCCHK, AR_Q_DESC_CRCCHK_EN);
+ }
+ /* Enable DESC interrupts for all Tx queues. */
+ AR_WRITE(sc, AR_IMR_S0, 0x00ff0000);
+ /* Enable EOL interrupts for all Tx queues except UAPSD. */
+ AR_WRITE(sc, AR_IMR_S1, 0x00df0000);
+ AR_WRITE_BARRIER(sc);
+}
+
+PUBLIC void
+athn_set_sta_timers(struct athn_softc *sc)
+{
+ struct ieee80211com *ic = &sc->sc_ic;
+ uint32_t tsfhi, tsflo, tsftu, reg;
+ uint32_t intval, next_tbtt, next_dtim;
+ int dtim_period, dtim_count, rem_dtim_count;
+
+ tsfhi = AR_READ(sc, AR_TSF_U32);
+ tsflo = AR_READ(sc, AR_TSF_L32);
+ tsftu = AR_TSF_TO_TU(tsfhi, tsflo) + AR_FUDGE;
+
+ /* Beacon interval in TU. */
+ intval = ic->ic_bss->ni_intval;
+
+ next_tbtt = roundup(tsftu, intval);
+#ifdef notyet
+ dtim_period = ic->ic_dtim_period;
+ if (dtim_period <= 0)
+#endif
+ dtim_period = 1; /* Assume all TIMs are DTIMs. */
+
+#ifdef notyet
+ dtim_count = ic->ic_dtim_count;
+ if (dtim_count >= dtim_period) /* Should not happen. */
+#endif
+ dtim_count = 0; /* Assume last TIM was a DTIM. */
+
+ /* Compute number of remaining TIMs until next DTIM. */
+ rem_dtim_count = 0; /* XXX */
+ next_dtim = next_tbtt + rem_dtim_count * intval;
+
+ AR_WRITE(sc, AR_NEXT_TBTT_TIMER, next_tbtt * IEEE80211_DUR_TU);
+ AR_WRITE(sc, AR_BEACON_PERIOD, intval * IEEE80211_DUR_TU);
+ AR_WRITE(sc, AR_DMA_BEACON_PERIOD, intval * IEEE80211_DUR_TU);
+
+ /*
+ * Set the number of consecutive beacons to miss before raising
+ * a BMISS interrupt to 10.
+ */
+ reg = AR_READ(sc, AR_RSSI_THR);
+ reg = RW(reg, AR_RSSI_THR_BM_THR, 10);
+ AR_WRITE(sc, AR_RSSI_THR, reg);
+
+ AR_WRITE(sc, AR_NEXT_DTIM,
+ (next_dtim - AR_SLEEP_SLOP) * IEEE80211_DUR_TU);
+ AR_WRITE(sc, AR_NEXT_TIM,
+ (next_tbtt - AR_SLEEP_SLOP) * IEEE80211_DUR_TU);
+
+ /* CAB timeout is in 1/8 TU. */
+ AR_WRITE(sc, AR_SLEEP1,
+ SM(AR_SLEEP1_CAB_TIMEOUT, AR_CAB_TIMEOUT_VAL * 8) |
+ AR_SLEEP1_ASSUME_DTIM);
+ AR_WRITE(sc, AR_SLEEP2,
+ SM(AR_SLEEP2_BEACON_TIMEOUT, AR_MIN_BEACON_TIMEOUT_VAL));
+
+ AR_WRITE(sc, AR_TIM_PERIOD, intval * IEEE80211_DUR_TU);
+ AR_WRITE(sc, AR_DTIM_PERIOD, dtim_period * intval * IEEE80211_DUR_TU);
+
+ AR_SETBITS(sc, AR_TIMER_MODE,
+ AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN | AR_DTIM_TIMER_EN);
+
+ /* Set TSF out-of-range threshold (fixed at 16k us). */
+ AR_WRITE(sc, AR_TSFOOR_THRESHOLD, 0x4240);
+
+ AR_WRITE_BARRIER(sc);
+}
+
+#ifndef IEEE80211_STA_ONLY
+PUBLIC void
+athn_set_hostap_timers(struct athn_softc *sc)
+{
+ struct ieee80211com *ic = &sc->sc_ic;
+ uint32_t intval, next_tbtt;
+
+ /* Beacon interval in TU. */
+ intval = ic->ic_bss->ni_intval;
+ next_tbtt = intval;
+
+ AR_WRITE(sc, AR_NEXT_TBTT_TIMER, next_tbtt * IEEE80211_DUR_TU);
+ AR_WRITE(sc, AR_NEXT_DMA_BEACON_ALERT,
+ (next_tbtt - AR_BEACON_DMA_DELAY) * IEEE80211_DUR_TU);
+ AR_WRITE(sc, AR_NEXT_CFP,
+ (next_tbtt - AR_SWBA_DELAY) * IEEE80211_DUR_TU);
+
+ AR_WRITE(sc, AR_BEACON_PERIOD, intval * IEEE80211_DUR_TU);
+ AR_WRITE(sc, AR_DMA_BEACON_PERIOD, intval * IEEE80211_DUR_TU);
+ AR_WRITE(sc, AR_SWBA_PERIOD, intval * IEEE80211_DUR_TU);
+ AR_WRITE(sc, AR_NDP_PERIOD, intval * IEEE80211_DUR_TU);
+
+ AR_WRITE(sc, AR_TIMER_MODE,
+ AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN);
+
+ AR_WRITE_BARRIER(sc);
+}
+#endif
+
+PUBLIC void
+athn_set_opmode(struct athn_softc *sc)
+{
+ uint32_t reg;
+
+ switch (sc->sc_ic.ic_opmode) {
+#ifndef IEEE80211_STA_ONLY
+ case IEEE80211_M_HOSTAP:
+ reg = AR_READ(sc, AR_STA_ID1);
+ reg &= ~AR_STA_ID1_ADHOC;
+ reg |= AR_STA_ID1_STA_AP | AR_STA_ID1_KSRCH_MODE;
+ AR_WRITE(sc, AR_STA_ID1, reg);
+
+ AR_CLRBITS(sc, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
+ break;
+ case IEEE80211_M_IBSS:
+ case IEEE80211_M_AHDEMO:
+ reg = AR_READ(sc, AR_STA_ID1);
+ reg &= ~AR_STA_ID1_STA_AP;
+ reg |= AR_STA_ID1_ADHOC | AR_STA_ID1_KSRCH_MODE;
+ AR_WRITE(sc, AR_STA_ID1, reg);
+
+ AR_SETBITS(sc, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
+ break;
+#endif
+ default:
+ reg = AR_READ(sc, AR_STA_ID1);
+ reg &= ~(AR_STA_ID1_ADHOC | AR_STA_ID1_STA_AP);
+ reg |= AR_STA_ID1_KSRCH_MODE;
+ AR_WRITE(sc, AR_STA_ID1, reg);
+ break;
+ }
+ AR_WRITE_BARRIER(sc);
+}
+
+PUBLIC void
+athn_set_bss(struct athn_softc *sc, struct ieee80211_node *ni)
+{
+ const uint8_t *bssid = ni->ni_bssid;
+
+ AR_WRITE(sc, AR_BSS_ID0, LE_READ_4(&bssid[0]));
+ AR_WRITE(sc, AR_BSS_ID1, LE_READ_2(&bssid[4]) |
+ SM(AR_BSS_ID1_AID, IEEE80211_AID(ni->ni_associd)));
+ AR_WRITE_BARRIER(sc);
+}
+
+Static void
+athn_enable_interrupts(struct athn_softc *sc)
+{
+ uint32_t mask2;
+
+ athn_disable_interrupts(sc); /* XXX */
+
+ AR_WRITE(sc, AR_IMR, sc->sc_imask);
+
+ mask2 = AR_READ(sc, AR_IMR_S2);
+ mask2 &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC |
+ AR_IMR_S2_CABEND | AR_IMR_S2_CABTO | AR_IMR_S2_TSFOOR);
+ mask2 |= AR_IMR_S2_GTT | AR_IMR_S2_CST;
+ AR_WRITE(sc, AR_IMR_S2, mask2);
+
+ AR_CLRBITS(sc, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
+
+ AR_WRITE(sc, AR_IER, AR_IER_ENABLE);
+
+ AR_WRITE(sc, AR_INTR_ASYNC_ENABLE, AR_INTR_MAC_IRQ);
+ AR_WRITE(sc, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
+
+ AR_WRITE(sc, AR_INTR_SYNC_ENABLE, sc->sc_isync);
+ AR_WRITE(sc, AR_INTR_SYNC_MASK, sc->sc_isync);
+ AR_WRITE_BARRIER(sc);
+}
+
+Static void
+athn_disable_interrupts(struct athn_softc *sc)
+{
+
+ AR_WRITE(sc, AR_IER, 0);
+ (void)AR_READ(sc, AR_IER);
+
+ AR_WRITE(sc, AR_INTR_ASYNC_ENABLE, 0);
+ (void)AR_READ(sc, AR_INTR_ASYNC_ENABLE);
+
+ AR_WRITE(sc, AR_INTR_SYNC_ENABLE, 0);
+ (void)AR_READ(sc, AR_INTR_SYNC_ENABLE);
+
+ AR_WRITE(sc, AR_IMR, 0);
+
+ AR_CLRBITS(sc, AR_IMR_S2, AR_IMR_S2_TIM | AR_IMR_S2_DTIM |
+ AR_IMR_S2_DTIMSYNC | AR_IMR_S2_CABEND | AR_IMR_S2_CABTO |
+ AR_IMR_S2_TSFOOR | AR_IMR_S2_GTT | AR_IMR_S2_CST);
+
+ AR_CLRBITS(sc, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
+ AR_WRITE_BARRIER(sc);
+}
+
+Static void
+athn_init_qos(struct athn_softc *sc)
+{
+
+ /* Initialize QoS settings. */
+ AR_WRITE(sc, AR_MIC_QOS_CONTROL, 0x100aa);
+ AR_WRITE(sc, AR_MIC_QOS_SELECT, 0x3210);
+ AR_WRITE(sc, AR_QOS_NO_ACK,
+ SM(AR_QOS_NO_ACK_TWO_BIT, 2) |
+ SM(AR_QOS_NO_ACK_BIT_OFF, 5) |
+ SM(AR_QOS_NO_ACK_BYTE_OFF, 0));
+ AR_WRITE(sc, AR_TXOP_X, AR_TXOP_X_VAL);
+ /* Initialize TXOP for all TIDs. */
+ AR_WRITE(sc, AR_TXOP_0_3, 0xffffffff);
+ AR_WRITE(sc, AR_TXOP_4_7, 0xffffffff);
+ AR_WRITE(sc, AR_TXOP_8_11, 0xffffffff);
+ AR_WRITE(sc, AR_TXOP_12_15, 0xffffffff);
+ AR_WRITE_BARRIER(sc);
+}
+
+PUBLIC int
+athn_hw_reset(struct athn_softc *sc, struct ieee80211_channel *curchan,
+ struct ieee80211_channel *extchan, int init)
+{
+ struct ieee80211com *ic = &sc->sc_ic;
+ struct athn_ops *ops = &sc->sc_ops;
+ uint32_t reg, def_ant, sta_id1, cfg_led, tsflo, tsfhi;
+ int i, error;
+
+ /* XXX not if already awake */
+ if ((error = athn_set_power_awake(sc)) != 0) {
+ aprint_error_dev(sc->sc_dev, "could not wakeup chip\n");
+ return error;
+ }
+
+ /* Preserve the antenna on a channel switch. */
+ if ((def_ant = AR_READ(sc, AR_DEF_ANTENNA)) == 0)
+ def_ant = 1;
+ /* Preserve other registers. */
+ sta_id1 = AR_READ(sc, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
+ cfg_led = AR_READ(sc, AR_CFG_LED) & (AR_CFG_LED_ASSOC_CTL_M |
+ AR_CFG_LED_MODE_SEL_M | AR_CFG_LED_BLINK_THRESH_SEL_M |
+ AR_CFG_LED_BLINK_SLOW);
+
+ /* Mark PHY as inactive. */
+ ops->disable_phy(sc);
+
+ if (init && AR_SREV_9271(sc)) {
+ AR_WRITE(sc, AR9271_RESET_POWER_DOWN_CONTROL,
+ AR9271_RADIO_RF_RST);
+ DELAY(50);
+ }
+ if (AR_SREV_9280(sc) && (sc->sc_flags & ATHN_FLAG_OLPC)) {
+ /* Save TSF before it gets cleared. */
+ tsfhi = AR_READ(sc, AR_TSF_U32);
+ tsflo = AR_READ(sc, AR_TSF_L32);
+
+ /* NB: RTC reset clears TSF. */
+ error = athn_reset_power_on(sc);
+ }
+ else {
+ tsfhi = tsflo = 0; /* XXX: gcc */
+ error = athn_reset(sc, 0);
+ }
+ if (error != 0) {
+ aprint_error_dev(sc->sc_dev,
+ "could not reset chip (error=%d)\n", error);
+ return error;
+ }
+
+ /* XXX not if already awake */
+ if ((error = athn_set_power_awake(sc)) != 0) {
+ aprint_error_dev(sc->sc_dev, "could not wakeup chip\n");
+ return error;
+ }
+
+ athn_init_pll(sc, curchan);
+ ops->set_rf_mode(sc, curchan);
+
+ if (sc->sc_flags & ATHN_FLAG_RFSILENT) {
+ /* Check that the radio is not disabled by hardware switch. */
+ reg = ops->gpio_read(sc, sc->sc_rfsilent_pin);
+ if (sc->sc_flags & ATHN_FLAG_RFSILENT_REVERSED)
+ reg = !reg;
+ if (!reg) {
+ aprint_error_dev(sc->sc_dev,
+ "radio is disabled by hardware switch\n");
+ return EPERM;
+ }
+ }
+ if (init && AR_SREV_9271(sc)) {
+ AR_WRITE(sc, AR9271_RESET_POWER_DOWN_CONTROL,
+ AR9271_GATE_MAC_CTL);
+ DELAY(50);
+ }
+ if (AR_SREV_9280(sc) && (sc->sc_flags & ATHN_FLAG_OLPC)) {
+ /* Restore TSF if it got cleared. */
+ AR_WRITE(sc, AR_TSF_L32, tsflo);
+ AR_WRITE(sc, AR_TSF_U32, tsfhi);
+ }
+
+ if (AR_SREV_9280_10_OR_LATER(sc))
+ AR_SETBITS(sc, sc->sc_gpio_input_en_off, AR_GPIO_JTAG_DISABLE);
+
+ if (AR_SREV_9287_13_OR_LATER(sc) && !AR_SREV_9380_10_OR_LATER(sc))
+ ar9287_1_3_enable_async_fifo(sc);
+
+ /* Write init values to hardware. */
+ ops->hw_init(sc, curchan, extchan);
+
+ /*
+ * Only >=AR9280 2.0 parts are capable of encrypting unicast
+ * management frames using CCMP.
+ */
+ if (AR_SREV_9280_20_OR_LATER(sc)) {
+ reg = AR_READ(sc, AR_AES_MUTE_MASK1);
+ /* Do not mask the subtype field in management frames. */
+ reg = RW(reg, AR_AES_MUTE_MASK1_FC0_MGMT, 0xff);
+ reg = RW(reg, AR_AES_MUTE_MASK1_FC1_MGMT,
+ ~(IEEE80211_FC1_RETRY | IEEE80211_FC1_PWR_MGT |
+ IEEE80211_FC1_MORE_DATA));
+ AR_WRITE(sc, AR_AES_MUTE_MASK1, reg);
+ }
+ else if (AR_SREV_9160_10_OR_LATER(sc)) {
+ /* Disable hardware crypto for management frames. */
+ AR_CLRBITS(sc, AR_PCU_MISC_MODE2,
+ AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
+ AR_SETBITS(sc, AR_PCU_MISC_MODE2,
+ AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
+ }
+
+ if (ic->ic_curmode != IEEE80211_MODE_11B)
+ ops->set_delta_slope(sc, curchan, extchan);
+
+ ops->spur_mitigate(sc, curchan, extchan);
+ ops->init_from_rom(sc, curchan, extchan);
+
+ /* XXX */
+ AR_WRITE(sc, AR_STA_ID0, LE_READ_4(&ic->ic_myaddr[0]));
+ AR_WRITE(sc, AR_STA_ID1, LE_READ_2(&ic->ic_myaddr[4]) |
+ sta_id1 | AR_STA_ID1_RTS_USE_DEF | AR_STA_ID1_CRPT_MIC_ENABLE);
+
+ athn_set_opmode(sc);
+
+ AR_WRITE(sc, AR_BSSMSKL, 0xffffffff);
+ AR_WRITE(sc, AR_BSSMSKU, 0xffff);
+
+ /* Restore previous antenna. */
+ AR_WRITE(sc, AR_DEF_ANTENNA, def_ant);
+
+ AR_WRITE(sc, AR_BSS_ID0, 0);
+ AR_WRITE(sc, AR_BSS_ID1, 0);
+
+ AR_WRITE(sc, AR_ISR, 0xffffffff);
+
+ AR_WRITE(sc, AR_RSSI_THR, SM(AR_RSSI_THR_BM_THR, 7));
+
+ if ((error = ops->set_synth(sc, curchan, extchan)) != 0) {
+ aprint_error_dev(sc->sc_dev, "could not set channel\n");
+ return error;
+ }
+ sc->sc_curchan = curchan;
+ sc->sc_curchanext = extchan;
+
+ for (i = 0; i < AR_NUM_DCU; i++)
+ AR_WRITE(sc, AR_DQCUMASK(i), 1 << i);
+
+ athn_init_tx_queues(sc);
+
+ /* Initialize interrupt mask. */
+ sc->sc_imask =
+ AR_IMR_TXDESC | AR_IMR_TXEOL |
+ AR_IMR_RXERR | AR_IMR_RXEOL | AR_IMR_RXORN |
+ AR_IMR_RXMINTR | AR_IMR_RXINTM |
+ AR_IMR_GENTMR | AR_IMR_BCNMISC;
+ if (AR_SREV_9380_10_OR_LATER(sc))
+ sc->sc_imask |= AR_IMR_RXERR | AR_IMR_HP_RXOK;
+#ifndef IEEE80211_STA_ONLY
+ if (0 && ic->ic_opmode == IEEE80211_M_HOSTAP)
+ sc->sc_imask |= AR_IMR_MIB;
+#endif
+ AR_WRITE(sc, AR_IMR, sc->sc_imask);
+ AR_SETBITS(sc, AR_IMR_S2, AR_IMR_S2_GTT);
+ AR_WRITE(sc, AR_INTR_SYNC_CAUSE, 0xffffffff);
+ sc->sc_isync = AR_INTR_SYNC_DEFAULT;
+ if (sc->sc_flags & ATHN_FLAG_RFSILENT)
+ sc->sc_isync |= AR_INTR_SYNC_GPIO_PIN(sc->sc_rfsilent_pin);
+ AR_WRITE(sc, AR_INTR_SYNC_ENABLE, sc->sc_isync);
+ AR_WRITE(sc, AR_INTR_SYNC_MASK, 0);
+ if (AR_SREV_9380_10_OR_LATER(sc)) {
+ AR_WRITE(sc, AR_INTR_PRIO_ASYNC_ENABLE, 0);
+ AR_WRITE(sc, AR_INTR_PRIO_ASYNC_MASK, 0);
+ AR_WRITE(sc, AR_INTR_PRIO_SYNC_ENABLE, 0);
+ AR_WRITE(sc, AR_INTR_PRIO_SYNC_MASK, 0);
+ }
+
+ athn_init_qos(sc);
+
+ AR_SETBITS(sc, AR_PCU_MISC, AR_PCU_MIC_NEW_LOC_ENA);
+
+ if (AR_SREV_9287_13_OR_LATER(sc) && !AR_SREV_9380_10_OR_LATER(sc))
+ ar9287_1_3_setup_async_fifo(sc);
+
+ /* Disable sequence number generation in hardware. */
+ AR_SETBITS(sc, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
+
+ athn_init_dma(sc);
+
+ /* Program observation bus to see MAC interrupts. */
+ AR_WRITE(sc, sc->sc_obs_off, 8);
+
+ /* Setup Rx interrupt mitigation. */
+ AR_WRITE(sc, AR_RIMT, SM(AR_RIMT_FIRST, 2000) | SM(AR_RIMT_LAST, 500));
+
+ ops->init_baseband(sc);
+
+ if ((error = athn_init_calib(sc, curchan, extchan)) != 0) {
+ aprint_error_dev(sc->sc_dev,
+ "could not initialize calibration\n");
+ return error;
+ }
+
+ ops->set_rxchains(sc);
+
+ AR_WRITE(sc, AR_CFG_LED, cfg_led | AR_CFG_SCLK_32KHZ);
+
+ if (sc->sc_flags & ATHN_FLAG_USB) {
+ if (AR_SREV_9271(sc))
+ AR_WRITE(sc, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
+ else
+ AR_WRITE(sc, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
+ }
+#if BYTE_ORDER == BIG_ENDIAN
+ else {
+ /* Default is LE, turn on swapping for BE. */
+ AR_WRITE(sc, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
+ }
+#endif
+ AR_WRITE_BARRIER(sc);
+
+ return 0;
+}
+
+Static struct ieee80211_node *
+athn_node_alloc(struct ieee80211_node_table *ntp)
+{
+
+ return malloc(sizeof(struct athn_node), M_DEVBUF,
+ M_NOWAIT | M_ZERO);
+}
+
+Static void
+athn_newassoc(struct ieee80211_node *ni, int isnew)
+{
+ struct ieee80211com *ic = ni->ni_ic;
+ struct athn_softc *sc = ic->ic_ifp->if_softc;
+ struct athn_node *an = (void *)ni;
+ struct ieee80211_rateset *rs = &ni->ni_rates;
+ uint8_t rate;
+ int ridx, i, j;
+
+ ieee80211_amrr_node_init(&sc->sc_amrr, &an->amn);
+ /* Start at lowest available bit-rate, AMRR will raise. */
+ ni->ni_txrate = 0;
+
+ for (i = 0; i < rs->rs_nrates; i++) {
+ rate = rs->rs_rates[i] & IEEE80211_RATE_VAL;
+
+ /* Map 802.11 rate to HW rate index. */
+ for (ridx = 0; ridx <= ATHN_RIDX_MAX; ridx++)
+ if (athn_rates[ridx].rate == rate)
+ break;
+ an->ridx[i] = ridx;
+ DPRINTFN(DBG_STM, sc, "rate %d index %d\n", rate, ridx);
+
+ /* Compute fallback rate for retries. */
+ an->fallback[i] = i;
+ for (j = i - 1; j >= 0; j--) {
+ if (athn_rates[an->ridx[j]].phy ==
+ athn_rates[an->ridx[i]].phy) {
+ an->fallback[i] = j;
+ break;
+ }
+ }
+ DPRINTFN(DBG_STM, sc, "%d fallbacks to %d\n",
+ i, an->fallback[i]);
+ }
+}
+
+Static int
+athn_media_change(struct ifnet *ifp)
+{
+ struct athn_softc *sc = ifp->if_softc;
+ struct ieee80211com *ic = &sc->sc_ic;
+ uint8_t rate, ridx;
+ int error;
+
+ error = ieee80211_media_change(ifp);
+ if (error != ENETRESET)
+ return error;
+
+ if (ic->ic_fixed_rate != -1) {
+ rate = ic->ic_sup_rates[ic->ic_curmode].
+ rs_rates[ic->ic_fixed_rate] & IEEE80211_RATE_VAL;
+ /* Map 802.11 rate to HW rate index. */
+ for (ridx = 0; ridx <= ATHN_RIDX_MAX; ridx++)
+ if (athn_rates[ridx].rate == rate)
+ break;
+ sc->sc_fixed_ridx = ridx;
+ }
+ if (IS_UP_AND_RUNNING(ifp)) {
+ athn_stop(ifp, 0);
+ error = athn_init(ifp);
+ }
+ return error;
+}
+
+Static void
+athn_next_scan(void *arg)
+{
+ struct athn_softc *sc = arg;
+ struct ieee80211com *ic = &sc->sc_ic;
+ int s;
+
+ s = splnet();
+ if (ic->ic_state == IEEE80211_S_SCAN)
+ ieee80211_next_scan(ic);
+ splx(s);
+}
+
+Static int
+athn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg)
+{
+ struct ifnet *ifp = ic->ic_ifp;
+ struct athn_softc *sc = ifp->if_softc;
+ uint32_t reg;
+ int error;
+
+ callout_stop(&sc->sc_calib_to);
+
+ switch (nstate) {
+ case IEEE80211_S_INIT:
+ athn_set_led(sc, 0);
+ break;
+ case IEEE80211_S_SCAN:
+ /* Make the LED blink while scanning. */
+ athn_set_led(sc, !sc->sc_led_state);
+ error = athn_switch_chan(sc, ic->ic_curchan, NULL);
+ if (error != 0)
+ return error;
+ callout_schedule(&sc->sc_scan_to, hz / 5);
+ break;
+ case IEEE80211_S_AUTH:
+ athn_set_led(sc, 0);
+ error = athn_switch_chan(sc, ic->ic_curchan, NULL);
+ if (error != 0)
+ return error;
+ break;
+ case IEEE80211_S_ASSOC:
+ break;
+ case IEEE80211_S_RUN:
+ athn_set_led(sc, 1);
+
+ if (ic->ic_opmode == IEEE80211_M_MONITOR)
+ break;
+
+ /* Fake a join to initialize the Tx rate. */
+ athn_newassoc(ic->ic_bss, 1);
+
+ athn_set_bss(sc, ic->ic_bss);
+ athn_disable_interrupts(sc);
+#ifndef IEEE80211_STA_ONLY
+ if (ic->ic_opmode == IEEE80211_M_HOSTAP) {
+ athn_set_hostap_timers(sc);
+ /* Enable software beacon alert interrupts. */
+ sc->sc_imask |= AR_IMR_SWBA;
+ }
+ else
+#endif
+ {
+ athn_set_sta_timers(sc);
+ /* Enable beacon miss interrupts. */
+ sc->sc_imask |= AR_IMR_BMISS;
+
+ /* Stop receiving beacons from other BSS. */
+ reg = AR_READ(sc, AR_RX_FILTER);
+ reg = (reg & ~AR_RX_FILTER_BEACON) |
+ AR_RX_FILTER_MYBEACON;
+ AR_WRITE(sc, AR_RX_FILTER, reg);
+ AR_WRITE_BARRIER(sc);
+ }
+ athn_enable_interrupts(sc);
+
+ if (sc->sc_sup_calib_mask != 0) {
+ memset(&sc->sc_calib, 0, sizeof(sc->sc_calib));
+ sc->sc_cur_calib_mask = sc->sc_sup_calib_mask;
+ /* ops->do_calib(sc); */
+ }
+ /* XXX Start ANI. */
+
+ callout_schedule(&sc->sc_calib_to, hz / 2);
+ break;
+ }
+
+ return sc->sc_newstate(ic, nstate, arg);
+}
+
+#ifdef notyet_edca
+PUBLIC void
+athn_updateedca(struct ieee80211com *ic)
+{
+#define ATHN_EXP2(x) ((1 << (x)) - 1) /* CWmin = 2^ECWmin - 1 */
+ struct athn_softc *sc = ic->ic_ifp->if_softc;
+ const struct ieee80211_edca_ac_params *ac;
+ int aci, qid;
+
+ for (aci = 0; aci < EDCA_NUM_AC; aci++) {
+ ac = &ic->ic_edca_ac[aci];
+ qid = athn_ac2qid[aci];
+
+ AR_WRITE(sc, AR_DLCL_IFS(qid),
+ SM(AR_D_LCL_IFS_CWMIN, ATHN_EXP2(ac->ac_ecwmin)) |
+ SM(AR_D_LCL_IFS_CWMAX, ATHN_EXP2(ac->ac_ecwmax)) |
+ SM(AR_D_LCL_IFS_AIFS, ac->ac_aifsn));
+ if (ac->ac_txoplimit != 0) {
+ AR_WRITE(sc, AR_DCHNTIME(qid),
+ SM(AR_D_CHNTIME_DUR,
+ IEEE80211_TXOP_TO_US(ac->ac_txoplimit)) |
+ AR_D_CHNTIME_EN);
+ }
+ else
+ AR_WRITE(sc, AR_DCHNTIME(qid), 0);
+ }
+ AR_WRITE_BARRIER(sc);
+#undef ATHN_EXP2
+}
+#endif /* notyet_edca */
+
+Static int
+athn_clock_rate(struct athn_softc *sc)
+{
+ struct ieee80211com *ic = &sc->sc_ic;
+ int clockrate; /* MHz. */
+
+ if (ic->ic_curmode == IEEE80211_MODE_11A) {
+ if (sc->sc_flags & ATHN_FLAG_FAST_PLL_CLOCK)
+ clockrate = AR_CLOCK_RATE_FAST_5GHZ_OFDM;
+ else
+ clockrate = AR_CLOCK_RATE_5GHZ_OFDM;
+ }
+ else if (ic->ic_curmode == IEEE80211_MODE_11B) {
+ clockrate = AR_CLOCK_RATE_CCK;
+ }
+ else
+ clockrate = AR_CLOCK_RATE_2GHZ_OFDM;
+#ifndef IEEE80211_NO_HT
+ if (sc->sc_curchanext != NULL)
+ clockrate *= 2;
+#endif
+ return clockrate;
+}
+
+PUBLIC void
+athn_updateslot(struct ifnet *ifp)
+{
+ struct athn_softc *sc = ifp->if_softc;
+ struct ieee80211com *ic = &sc->sc_ic;
+ int slot;
+
+ slot = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20;
+ AR_WRITE(sc, AR_D_GBL_IFS_SLOT, slot * athn_clock_rate(sc));
+ AR_WRITE_BARRIER(sc);
+}
+
+Static void
+athn_start(struct ifnet *ifp)
+{
+ struct athn_softc *sc = ifp->if_softc;
+ struct ieee80211com *ic = &sc->sc_ic;
+ struct ether_header *eh;
+ struct ieee80211_node *ni;
+ struct mbuf *m;
+
+ if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
+ return;
+
+ for (;;) {
+ if (SIMPLEQ_EMPTY(&sc->sc_txbufs)) {
+ ifp->if_flags |= IFF_OACTIVE;
+ break;
+ }
+ /* Send pending management frames first. */
+ IF_DEQUEUE(&ic->ic_mgtq, m);
+ if (m != NULL) {
+ ni = (void *)m->m_pkthdr.rcvif;
+ goto sendit;
+ }
+ if (ic->ic_state != IEEE80211_S_RUN)
+ break;
+
+ /* Encapsulate and send data frames. */
+ IFQ_DEQUEUE(&ifp->if_snd, m);
+ if (m == NULL)
+ break;
+
+ if (m->m_len < (int)sizeof(*eh) &&
+ (m = m_pullup(m, sizeof(*eh))) == NULL) {
+ ifp->if_oerrors++;
+ continue;
+ }
+ eh = mtod(m, struct ether_header *);
+ ni = ieee80211_find_txnode(ic, eh->ether_dhost);
+ if (ni == NULL) {
+ m_freem(m);
+ ifp->if_oerrors++;
+ continue;
+ }
+
+ bpf_mtap(ifp, m);
+
+ if ((m = ieee80211_encap(ic, m, ni)) == NULL)
+ continue;
+ sendit:
+ bpf_mtap3(ic->ic_rawbpf, m);
+
+ if (sc->sc_ops.tx(sc, m, ni, 0) != 0) {
+ ieee80211_free_node(ni);
+ ifp->if_oerrors++;
+ continue;
+ }
+
+ sc->sc_tx_timer = 5;
+ ifp->if_timer = 1;
+ }
+}
+
+Static void
+athn_watchdog(struct ifnet *ifp)
+{
+ struct athn_softc *sc = ifp->if_softc;
+
+ ifp->if_timer = 0;
+
+ if (sc->sc_tx_timer > 0) {
+ if (--sc->sc_tx_timer == 0) {
+ aprint_error_dev(sc->sc_dev, "device timeout\n");
+ athn_stop(ifp, 1);
+ (void)athn_init(ifp);
+ ifp->if_oerrors++;
+ return;
+ }
+ ifp->if_timer = 1;
+ }
+ ieee80211_watchdog(&sc->sc_ic);
+}
+
+#ifdef notyet
+Static void
+athn_set_multi(struct athn_softc *sc)
+{
+ struct arpcom *ac = &sc->sc_ic.ic_ac;
+ struct ifnet *ifp = &ac->ac_if;
+ struct ether_multi *enm;
+ struct ether_multistep step;
+ const uint8_t *addr;
+ uint32_t val, lo, hi;
+ uint8_t bit;
+
+ if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) {
+ lo = hi = 0xffffffff;
+ goto done;
+ }
+ lo = hi = 0;
+ ETHER_FIRST_MULTI(step, ac, enm);
+ while (enm != NULL) {
+ if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6) != 0) {
+ ifp->if_flags |= IFF_ALLMULTI;
+ lo = hi = 0xffffffff;
+ goto done;
+ }
+ addr = enm->enm_addrlo;
+ /* Calculate the XOR value of all eight 6-bit words. */
+ val = addr[0] | addr[1] << 8 | addr[2] << 16;
+ bit = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
+ val = addr[3] | addr[4] << 8 | addr[5] << 16;
+ bit ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
+ bit &= 0x3f;
+ if (bit < 32)
+ lo |= 1 << bit;
+ else
+ hi |= 1 << (bit - 32);
+ ETHER_NEXT_MULTI(step, enm);
+ }
+ done:
+ AR_WRITE(sc, AR_MCAST_FIL0, lo);
+ AR_WRITE(sc, AR_MCAST_FIL1, hi);
+ AR_WRITE_BARRIER(sc);
+}
+#endif /* notyet */
+
+Static int
+athn_ioctl(struct ifnet *ifp, u_long cmd, void *data)
+{
+ struct athn_softc *sc = ifp->if_softc;
+ struct ieee80211com *ic = &sc->sc_ic;
+ int s, error = 0;
+
+ s = splnet();
+
+ switch (cmd) {
+ case SIOCSIFFLAGS:
+ if ((error = ifioctl_common(ifp, cmd, data)) != 0)
+ break;
+
+ switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) {
+ case IFF_UP | IFF_RUNNING:
+#ifdef notyet
+ if (((ifp->if_flags ^ sc->sc_if_flags) &
+ (IFF_ALLMULTI | IFF_PROMISC)) != 0)
+ /* XXX: setup multi */
+#endif
+ break;
+ case IFF_UP:
+ athn_init(ifp);
+ break;
+
+ case IFF_RUNNING:
+ athn_stop(ifp, 1);
+ break;
+ case 0:
+ default:
+ break;
+ }
+ sc->sc_if_flags = ifp->if_flags;
+ break;
+
+ case SIOCADDMULTI:
+ case SIOCDELMULTI:
+ if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) {
+ /* setup multicast filter, etc */
+#ifdef notyet
+ athn_set_multi(sc);
+#endif
+ error = 0;
+ }
+ break;
+
+ case SIOCS80211CHANNEL:
+ error = ieee80211_ioctl(ic, cmd, data);
+ if (error == ENETRESET &&
+ ic->ic_opmode == IEEE80211_M_MONITOR) {
+ if (IS_UP_AND_RUNNING(ifp))
+ athn_switch_chan(sc, ic->ic_curchan, NULL);
+ error = 0;
+ }
+ break;
+
+ default:
+ error = ieee80211_ioctl(ic, cmd, data);
+ }
+
+ if (error == ENETRESET) {
+ error = 0;
+ if (IS_UP_AND_RUNNING(ifp) &&
+ ic->ic_roaming != IEEE80211_ROAMING_MANUAL) {
+ athn_stop(ifp, 0);
+ error = athn_init(ifp);
+ }
+ }
+
+ splx(s);
+ return error;
+}
+
+Static int
+athn_init(struct ifnet *ifp)
+{
+ struct athn_softc *sc = ifp->if_softc;
+ struct athn_ops *ops = &sc->sc_ops;
+ struct ieee80211com *ic = &sc->sc_ic;
+ struct ieee80211_channel *curchan, *extchan;
+ size_t i;
+ int error;
+
+ if (device_is_active(sc->sc_dev))
+ athn_stop(ifp, 0); /* XXX: necessary? */
+ else if (!pmf_device_subtree_resume(sc->sc_dev, &sc->sc_qual) ||
+ !device_is_active(sc->sc_dev))
+ return 0;
+
+ curchan = ic->ic_curchan;
+ extchan = NULL;
+
+ /* In case a new MAC address has been configured. */
+ IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl));
+
+#ifdef openbsd_power_management
+ /* For CardBus, power on the socket. */
+ if (sc->sc_enable != NULL) {
+ if ((error = sc->sc_enable(sc)) != 0) {
+ aprint_error_dev(sc->sc_dev,
+ "could not enable device\n");
+ goto fail;
+ }
+ if ((error = athn_reset_power_on(sc)) != 0) {
+ aprint_error_dev(sc->sc_dev,
+ "could not power on device\n");
+ goto fail;
+ }
+ }
+#endif
+ if (!(sc->sc_flags & ATHN_FLAG_PCIE))
+ athn_config_nonpcie(sc);
+ else
+ athn_config_pcie(sc);
+
+ /* Reset HW key cache entries. */
+ for (i = 0; i < sc->sc_kc_entries; i++)
+ athn_reset_key(sc, i);
+
+ ops->enable_antenna_diversity(sc);
+
+#ifdef ATHN_BT_COEXISTENCE
+ /* Configure bluetooth coexistence for combo chips. */
+ if (sc->sc_flags & ATHN_FLAG_BTCOEX)
+ athn_btcoex_init(sc);
+#endif
+
+ /* Configure LED. */
+ athn_led_init(sc);
+
+ /* Configure hardware radio switch. */
+ if (sc->sc_flags & ATHN_FLAG_RFSILENT)
+ ops->rfsilent_init(sc);
+
+ if ((error = athn_hw_reset(sc, curchan, extchan, 1)) != 0) {
+ aprint_error_dev(sc->sc_dev,
+ "unable to reset hardware; reset status %d\n", error);
+ goto fail;
+ }
+
+ /* Enable Rx. */
+ athn_rx_start(sc);
+
+ /* Enable interrupts. */
+ athn_enable_interrupts(sc);
+
+#ifdef ATHN_BT_COEXISTENCE
+ /* Enable bluetooth coexistence for combo chips. */
+ if (sc->sc_flags & ATHN_FLAG_BTCOEX)
+ athn_btcoex_enable(sc);
+#endif
+
+ ifp->if_flags &= ~IFF_OACTIVE;
+ ifp->if_flags |= IFF_RUNNING;
+
+#ifdef notyet
+ if (ic->ic_flags & IEEE80211_F_WEPON) {
+ /* Configure WEP keys. */
+ for (i = 0; i < IEEE80211_WEP_NKID; i++)
+ athn_set_key(ic, NULL, &ic->ic_nw_keys[i]);
+ }
+#endif
+ if (ic->ic_opmode == IEEE80211_M_MONITOR)
+ ieee80211_new_state(ic, IEEE80211_S_RUN, -1);
+ else
+ ieee80211_new_state(ic, IEEE80211_S_SCAN, -1);
+
+ return 0;
+ fail:
+ athn_stop(ifp, 1);
+ return error;
+}
+
+PUBLIC void
+athn_stop(struct ifnet *ifp, int disable)
+{
+ struct athn_softc *sc = ifp->if_softc;
+ struct ieee80211com *ic = &sc->sc_ic;
+ int qid;
+
+ ifp->if_timer = sc->sc_tx_timer = 0;
+ ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
+
+ callout_stop(&sc->sc_scan_to);
+ /* In case we were scanning, release the scan "lock". */
+// ic->ic_scan_lock = IEEE80211_SCAN_UNLOCKED; /* XXX:??? */
+
+ ieee80211_new_state(ic, IEEE80211_S_INIT, -1);
+
+#ifdef ATHN_BT_COEXISTENCE
+ /* Disable bluetooth coexistence for combo chips. */
+ if (sc->sc_flags & ATHN_FLAG_BTCOEX)
+ athn_btcoex_disable(sc);
+#endif
+
+ /* Disable interrupts. */
+ athn_disable_interrupts(sc);
+ /* Acknowledge interrupts (avoids interrupt storms). */
+ AR_WRITE(sc, AR_INTR_SYNC_CAUSE, 0xffffffff);
+ AR_WRITE(sc, AR_INTR_SYNC_MASK, 0);
+
+ for (qid = 0; qid < ATHN_QID_COUNT; qid++)
+ athn_stop_tx_dma(sc, qid);
+ /* XXX call athn_hw_reset if Tx still pending? */
+ for (qid = 0; qid < ATHN_QID_COUNT; qid++)
+ athn_tx_reclaim(sc, qid);
+
+ /* Stop Rx. */
+ AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT);
+ AR_WRITE(sc, AR_MIBC, AR_MIBC_FMC);
+ AR_WRITE(sc, AR_MIBC, AR_MIBC_CMC);
+ AR_WRITE(sc, AR_FILT_OFDM, 0);
+ AR_WRITE(sc, AR_FILT_CCK, 0);
+ AR_WRITE_BARRIER(sc);
+ athn_set_rxfilter(sc, 0);
+ athn_stop_rx_dma(sc);
+
+ athn_reset(sc, 0);
+ athn_init_pll(sc, NULL);
+ athn_set_power_awake(sc);
+ athn_reset(sc, 1);
+ athn_init_pll(sc, NULL);
+
+ athn_set_power_sleep(sc);
+
+#if 0 /* XXX: shouldn't the pmf stuff take care of this? */
+ /* For CardBus, power down the socket. */
+ if (disable && sc->sc_disable != NULL)
+ sc->sc_disable(sc);
+#endif
+ if (disable)
+ pmf_device_recursive_suspend(sc->sc_dev, &sc->sc_qual);
+}
+
+PUBLIC void
+athn_suspend(struct athn_softc *sc)
+{
+ struct ifnet *ifp = &sc->sc_if;
+
+ if (ifp->if_flags & IFF_RUNNING)
+ athn_stop(ifp, 1);
+}
+
+PUBLIC int
+athn_resume(struct athn_softc *sc)
+{
+ struct ifnet *ifp = &sc->sc_if;
+
+ if (ifp->if_flags & IFF_UP)
+ return athn_init(ifp);
+ return 0;
+}
diff --git a/sys/dev/ic/athnreg.h b/sys/dev/ic/athnreg.h
new file mode 100644
index 00000000000..0070de4aa5b
--- /dev/null
+++ b/sys/dev/ic/athnreg.h
@@ -0,0 +1,1489 @@
+/* $NetBSD: athnreg.h,v 1.1 2013/03/30 02:53:02 christos Exp $ */
+/* $OpenBSD: athnreg.h,v 1.18 2012/06/10 21:23:36 kettenis Exp $ */
+
+/*-
+ * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr>
+ * Copyright (c) 2008-2009 Atheros Communications Inc.
+ *
+ * Permission to use, copy, modify, and distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _ATHNREG_H_
+#define _ATHNREG_H_
+
+/*
+ * MAC registers.
+ */
+#define AR_CR 0x0008
+#define AR_RXDP 0x000c
+#define AR_CFG 0x0014
+#define AR_RXBP_THRESH 0x0018
+#define AR_MIRT 0x0020
+#define AR_IER 0x0024
+#define AR_TIMT 0x0028
+#define AR_RIMT 0x002c
+#define AR_TXCFG 0x0030
+#define AR_RXCFG 0x0034
+#define AR_MIBC 0x0040
+#define AR_TOPS 0x0044
+#define AR_RXNPTO 0x0048
+#define AR_TXNPTO 0x004c
+#define AR_RPGTO 0x0050
+#define AR_RPCNT 0x0054
+#define AR_MACMISC 0x0058
+#define AR_DATABUF_SIZE 0x0060
+#define AR_GTXTO 0x0064
+#define AR_GTTM 0x0068
+#define AR_CST 0x006c
+#define AR_HP_RXDP 0x0074
+#define AR_LP_RXDP 0x0078
+#define AR_ISR 0x0080
+#define AR_ISR_S0 0x0084
+#define AR_ISR_S1 0x0088
+#define AR_ISR_S2 0x008c
+#define AR_ISR_S3 0x0090
+#define AR_ISR_S4 0x0094
+#define AR_ISR_S5 0x0098
+#define AR_IMR 0x00a0
+#define AR_IMR_S0 0x00a4
+#define AR_IMR_S1 0x00a8
+#define AR_IMR_S2 0x00ac
+#define AR_IMR_S3 0x00b0
+#define AR_IMR_S4 0x00b4
+#define AR_IMR_S5 0x00b8
+#define AR_ISR_RAC 0x00c0
+#define AR_ISR_S0_S 0x00c4
+#define AR_ISR_S1_S 0x00c8
+#define AR_DMADBG(i) (0x00e0 + (i) * 4)
+#define AR_QTXDP(i) (0x0800 + (i) * 4)
+#define AR_Q_STATUS_RING_START 0x0830
+#define AR_Q_STATUS_RING_END 0x0834
+#define AR_Q_TXE 0x0840
+#define AR_Q_TXD 0x0880
+#define AR_QCBRCFG(i) (0x08c0 + (i) * 4)
+#define AR_QRDYTIMECFG(i) (0x0900 + (i) * 4)
+#define AR_Q_ONESHOTARM_SC 0x0940
+#define AR_Q_ONESHOTARM_CC 0x0980
+#define AR_QMISC(i) (0x09c0 + (i) * 4)
+#define AR_QSTS(i) (0x0a00 + (i) * 4)
+#define AR_Q_RDYTIMESHDN 0x0a40
+#define AR_Q_DESC_CRCCHK 0x0a44
+#define AR_DQCUMASK(i) (0x1000 + (i) * 4)
+#define AR_D_GBL_IFS_SIFS 0x1030
+#define AR_D_TXBLK_CMD 0x1038
+#define AR_DLCL_IFS(i) (0x1040 + (i) * 4)
+#define AR_D_GBL_IFS_SLOT 0x1070
+#define AR_DRETRY_LIMIT(i) (0x1080 + (i) * 4)
+#define AR_D_GBL_IFS_EIFS 0x10b0
+#define AR_DCHNTIME(i) (0x10c0 + (i) * 4)
+#define AR_D_GBL_IFS_MISC 0x10f0
+#define AR_DMISC(i) (0x1100 + (i) * 4)
+#define AR_D_SEQNUM 0x1140
+#define AR_D_FPCTL 0x1230
+#define AR_D_TXPSE 0x1270
+#define AR_D_TXSLOTMASK 0x12f0
+#define AR_MAC_SLEEP 0x1f00
+#define AR_CFG_LED 0x1f04
+#define AR_EEPROM_OFFSET(i) (0x2000 + (i) * 4)
+#define AR_RC 0x4000
+#define AR_WA 0x4004
+#define AR_PM_STATE 0x4008
+#define AR_PCIE_PM_CTRL 0x4014
+#define AR_HOST_TIMEOUT 0x4018
+#define AR_EEPROM 0x401c
+#define AR_SREV 0x4020
+#define AR_AHB_MODE 0x4024
+#define AR_INTR_SYNC_CAUSE 0x4028
+#define AR_INTR_SYNC_ENABLE 0x402c
+#define AR_INTR_ASYNC_MASK 0x4030
+#define AR_INTR_SYNC_MASK 0x4034
+#define AR_INTR_ASYNC_CAUSE 0x4038
+#define AR_INTR_ASYNC_ENABLE 0x403c
+#define AR_PCIE_SERDES 0x4040
+#define AR_PCIE_SERDES2 0x4044
+#define AR_INTR_PRIO_SYNC_ENABLE 0x40c4
+#define AR_INTR_PRIO_ASYNC_MASK 0x40c8
+#define AR_INTR_PRIO_SYNC_MASK 0x40cc
+#define AR_INTR_PRIO_ASYNC_ENABLE 0x40d4
+#define AR_RTC_RC 0x7000
+#define AR_RTC_XTAL_CONTROL 0x7004
+#define AR_RTC_REG_CONTROL0 0x7008
+#define AR_RTC_REG_CONTROL1 0x700c
+#define AR_RTC_PLL_CONTROL 0x7014
+#define AR_RTC_PLL_CONTROL2 0x703c
+#define AR_RTC_RESET 0x7040
+#define AR_RTC_STATUS 0x7044
+#define AR_RTC_SLEEP_CLK 0x7048
+#define AR_RTC_FORCE_WAKE 0x704c
+#define AR_RTC_INTR_CAUSE 0x7050
+#define AR_RTC_INTR_ENABLE 0x7054
+#define AR_RTC_INTR_MASK 0x7058
+#define AR_STA_ID0 0x8000
+#define AR_STA_ID1 0x8004
+#define AR_BSS_ID0 0x8008
+#define AR_BSS_ID1 0x800c
+#define AR_BCN_RSSI_AVE 0x8010
+#define AR_TIME_OUT 0x8014
+#define AR_RSSI_THR 0x8018
+#define AR_USEC 0x801c
+#define AR_RESET_TSF 0x8020
+#define AR_MAX_CFP_DUR 0x8038
+#define AR_RX_FILTER 0x803c
+#define AR_MCAST_FIL0 0x8040
+#define AR_MCAST_FIL1 0x8044
+#define AR_DIAG_SW 0x8048
+#define AR_TSF_L32 0x804c
+#define AR_TSF_U32 0x8050
+#define AR_TST_ADDAC 0x8054
+#define AR_DEF_ANTENNA 0x8058
+#define AR_AES_MUTE_MASK0 0x805c
+#define AR_AES_MUTE_MASK1 0x8060
+#define AR_GATED_CLKS 0x8064
+#define AR_OBS_BUS_CTRL 0x8068
+#define AR_OBS_BUS_1 0x806c
+#define AR_LAST_TSTP 0x8080
+#define AR_NAV 0x8084
+#define AR_RTS_OK 0x8088
+#define AR_RTS_FAIL 0x808c
+#define AR_ACK_FAIL 0x8090
+#define AR_FCS_FAIL 0x8094
+#define AR_BEACON_CNT 0x8098
+#define AR_SLEEP1 0x80d4
+#define AR_SLEEP2 0x80d8
+#define AR_BSSMSKL 0x80e0
+#define AR_BSSMSKU 0x80e4
+#define AR_TPC 0x80e8
+#define AR_TFCNT 0x80ec
+#define AR_RFCNT 0x80f0
+#define AR_RCCNT 0x80f4
+#define AR_CCCNT 0x80f8
+#define AR_QUIET1 0x80fc
+#define AR_QUIET2 0x8100
+#define AR_TSF_PARM 0x8104
+#define AR_QOS_NO_ACK 0x8108
+#define AR_PHY_ERR 0x810c
+#define AR_RXFIFO_CFG 0x8114
+#define AR_MIC_QOS_CONTROL 0x8118
+#define AR_MIC_QOS_SELECT 0x811c
+#define AR_PCU_MISC 0x8120
+#define AR_FILT_OFDM 0x8124
+#define AR_FILT_CCK 0x8128
+#define AR_PHY_ERR_1 0x812c
+#define AR_PHY_ERR_MASK_1 0x8130
+#define AR_PHY_ERR_2 0x8134
+#define AR_PHY_ERR_MASK_2 0x8138
+#define AR_TSFOOR_THRESHOLD 0x813c
+#define AR_PHY_ERR_EIFS_MASK 0x8144
+#define AR_PHY_ERR_3 0x8168
+#define AR_PHY_ERR_MASK_3 0x816c
+#define AR_BT_COEX_MODE 0x8170
+#define AR_BT_COEX_WEIGHT 0x8174
+#define AR_BT_COEX_MODE2 0x817c
+#define AR_NEXT_NDP2_TIMER(i) (0x8180 + (i) * 4)
+#define AR_NDP2_PERIOD(i) (0x81a0 + (i) * 4)
+#define AR_NDP2_TIMER_MODE 0x81c0
+#define AR_TXSIFS 0x81d0
+#define AR_TXOP_X 0x81ec
+#define AR_TXOP_0_3 0x81f0
+#define AR_TXOP_4_7 0x81f4
+#define AR_TXOP_8_11 0x81f8
+#define AR_TXOP_12_15 0x81fc
+#define AR_GEN_TIMER(i) (0x8200 + (i) * 4)
+#define AR_NEXT_TBTT_TIMER AR_GEN_TIMER(0)
+#define AR_NEXT_DMA_BEACON_ALERT AR_GEN_TIMER(1)
+#define AR_NEXT_CFP AR_GEN_TIMER(2)
+#define AR_NEXT_HCF AR_GEN_TIMER(3)
+#define AR_NEXT_TIM AR_GEN_TIMER(4)
+#define AR_NEXT_DTIM AR_GEN_TIMER(5)
+#define AR_NEXT_QUIET_TIMER AR_GEN_TIMER(6)
+#define AR_NEXT_NDP_TIMER AR_GEN_TIMER(7)
+#define AR_BEACON_PERIOD AR_GEN_TIMER(8)
+#define AR_DMA_BEACON_PERIOD AR_GEN_TIMER(9)
+#define AR_SWBA_PERIOD AR_GEN_TIMER(10)
+#define AR_HCF_PERIOD AR_GEN_TIMER(11)
+#define AR_TIM_PERIOD AR_GEN_TIMER(12)
+#define AR_DTIM_PERIOD AR_GEN_TIMER(13)
+#define AR_QUIET_PERIOD AR_GEN_TIMER(14)
+#define AR_NDP_PERIOD AR_GEN_TIMER(15)
+#define AR_TIMER_MODE 0x8240
+#define AR_SLP32_MODE 0x8244
+#define AR_SLP32_WAKE 0x8248
+#define AR_SLP32_INC 0x824c
+#define AR_SLP_CNT 0x8250
+#define AR_SLP_CYCLE_CNT 0x8254
+#define AR_SLP_MIB_CTRL 0x8258
+#define AR_WOW_PATTERN_REG 0x825c
+#define AR_WOW_COUNT_REG 0x8260
+#define AR_MAC_PCU_LOGIC_ANALYZER 0x8264
+#define AR_WOW_BCN_EN_REG 0x8270
+#define AR_WOW_BCN_TIMO_REG 0x8274
+#define AR_WOW_KEEP_ALIVE_TIMO_REG 0x8278
+#define AR_WOW_KEEP_ALIVE_REG 0x827c
+#define AR_WOW_US_SCALAR_REG 0x8284
+#define AR_WOW_KEEP_ALIVE_DELAY_REG 0x8288
+#define AR_WOW_PATTERN_MATCH_REG 0x828c
+#define AR_WOW_PATTERN_OFF1_REG 0x8290
+#define AR_WOW_PATTERN_OFF2_REG 0x8294
+#define AR_WOW_EXACT_REG 0x829c
+#define AR_2040_MODE 0x8318
+#define AR_EXTRCCNT 0x8328
+#define AR_SELFGEN_MASK 0x832c
+#define AR_PCU_TXBUF_CTRL 0x8340
+#define AR_PCU_MISC_MODE2 0x8344
+#define AR_MAC_PCU_ASYNC_FIFO_REG3 0x8358
+#define AR_WOW_LENGTH1_REG 0x8360
+#define AR_WOW_LENGTH2_REG 0x8364
+#define AR_WOW_PATTERN_MATCH_LT_256B 0x8368
+#define AR_RATE_DURATION(i) (0x8700 + (i) * 4)
+#define AR_KEYTABLE(i) (0x8800 + (i) * 32)
+#define AR_KEYTABLE_KEY0(i) (AR_KEYTABLE(i) + 0)
+#define AR_KEYTABLE_KEY1(i) (AR_KEYTABLE(i) + 4)
+#define AR_KEYTABLE_KEY2(i) (AR_KEYTABLE(i) + 8)
+#define AR_KEYTABLE_KEY3(i) (AR_KEYTABLE(i) + 12)
+#define AR_KEYTABLE_KEY4(i) (AR_KEYTABLE(i) + 16)
+#define AR_KEYTABLE_TYPE(i) (AR_KEYTABLE(i) + 20)
+#define AR_KEYTABLE_MAC0(i) (AR_KEYTABLE(i) + 24)
+#define AR_KEYTABLE_MAC1(i) (AR_KEYTABLE(i) + 28)
+
+
+/* Bits for AR_CR. */
+#define AR_CR_RXE 0x00000004
+#define AR_CR_RXD 0x00000020
+#define AR_CR_SWI 0x00000040
+
+/* Bits for AR_CFG. */
+#define AR_CFG_SWTD 0x00000001
+#define AR_CFG_SWTB 0x00000002
+#define AR_CFG_SWRD 0x00000004
+#define AR_CFG_SWRB 0x00000008
+#define AR_CFG_SWRG 0x00000010
+#define AR_CFG_AP_ADHOC_INDICATION 0x00000020
+#define AR_CFG_PHOK 0x00000100
+#define AR_CFG_EEBS 0x00000200
+#define AR_CFG_CLK_GATE_DIS 0x00000400
+#define AR_CFG_PCI_MASTER_REQ_Q_THRESH_M 0x00060000
+#define AR_CFG_PCI_MASTER_REQ_Q_THRESH_S 17
+
+/* Bits for AR_RXBP_THRESH. */
+#define AR_RXBP_THRESH_HP_M 0x0000000f
+#define AR_RXBP_THRESH_HP_S 0
+#define AR_RXBP_THRESH_LP_M 0x00003f00
+#define AR_RXBP_THRESH_LP_S 8
+
+/* Bits for AR_IER. */
+#define AR_IER_ENABLE 0x00000001
+
+/* Bits for AR_TIMT. */
+#define AR_TIMT_LAST_M 0x0000ffff
+#define AR_TIMT_LAST_S 0
+#define AR_TIMT_FIRST_M 0xffff0000
+#define AR_TIMT_FIRST_S 16
+
+/* Bits for AR_RIMT. */
+#define AR_RIMT_LAST_M 0x0000ffff
+#define AR_RIMT_LAST_S 0
+#define AR_RIMT_FIRST_M 0xffff0000
+#define AR_RIMT_FIRST_S 16
+
+/* Bits for AR_[TR]XCFG_DMASZ fields. */
+#define AR_DMASZ_4B 0
+#define AR_DMASZ_8B 1
+#define AR_DMASZ_16B 2
+#define AR_DMASZ_32B 3
+#define AR_DMASZ_64B 4
+#define AR_DMASZ_128B 5
+#define AR_DMASZ_256B 6
+#define AR_DMASZ_512B 7
+
+/* Bits for AR_TXCFG. */
+#define AR_TXCFG_DMASZ_M 0x00000007
+#define AR_TXCFG_DMASZ_S 0
+#define AR_TXCFG_FTRIG_M 0x000003f0
+#define AR_TXCFG_FTRIG_S 4
+#define AR_TXCFG_FTRIG_IMMED ( 0 / 64)
+#define AR_TXCFG_FTRIG_64B ( 64 / 64)
+#define AR_TXCFG_FTRIG_128B (128 / 64)
+#define AR_TXCFG_FTRIG_192B (192 / 64)
+#define AR_TXCFG_FTRIG_256B (256 / 64)
+#define AR_TXCFG_FTRIG_512B (512 / 64)
+#define AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY 0x00000800
+
+/* Bits for AR_RXCFG. */
+#define AR_RXCFG_DMASZ_M 0x00000007
+#define AR_RXCFG_DMASZ_S 0
+#define AR_RXCFG_CHIRP 0x00000008
+#define AR_RXCFG_ZLFDMA 0x00000010
+
+/* Bits for AR_MIBC. */
+#define AR_MIBC_COW 0x00000001
+#define AR_MIBC_FMC 0x00000002
+#define AR_MIBC_CMC 0x00000004
+#define AR_MIBC_MCS 0x00000008
+
+/* Bits for AR_TOPS. */
+#define AR_TOPS_MASK 0x0000ffff
+
+/* Bits for AR_RXNPTO. */
+#define AR_RXNPTO_MASK 0x000003ff
+
+/* Bits for AR_TXNPTO. */
+#define AR_TXNPTO_MASK 0x000003ff
+#define AR_TXNPTO_QCU_MASK 0x000ffc00
+
+/* Bits for AR_RPGTO. */
+#define AR_RPGTO_MASK 0x000003ff
+
+/* Bits for AR_RPCNT. */
+#define AR_RPCNT_MASK 0x0000001f
+
+/* Bits for AR_MACMISC. */
+#define AR_MACMISC_PCI_EXT_FORCE 0x00000010
+#define AR_MACMISC_DMA_OBS_M 0x000001e0
+#define AR_MACMISC_DMA_OBS_S 5
+#define AR_MACMISC_MISC_OBS_M 0x00000e00
+#define AR_MACMISC_MISC_OBS_S 9
+#define AR_MACMISC_MISC_OBS_BUS_LSB_M 0x00007000
+#define AR_MACMISC_MISC_OBS_BUS_LSB_S 12
+#define AR_MACMISC_MISC_OBS_BUS_MSB_M 0x00038000
+#define AR_MACMISC_MISC_OBS_BUS_MSB_S 15
+
+/* Bits for AR_GTXTO. */
+#define AR_GTXTO_TIMEOUT_COUNTER_M 0x0000ffff
+#define AR_GTXTO_TIMEOUT_COUNTER_S 0
+#define AR_GTXTO_TIMEOUT_LIMIT_M 0xffff0000
+#define AR_GTXTO_TIMEOUT_LIMIT_S 16
+
+/* Bits for AR_GTTM. */
+#define AR_GTTM_USEC 0x00000001
+#define AR_GTTM_IGNORE_IDLE 0x00000002
+#define AR_GTTM_RESET_IDLE 0x00000004
+#define AR_GTTM_CST_USEC 0x00000008
+
+/* Bits for AR_CST. */
+#define AR_CST_TIMEOUT_COUNTER_M 0x0000ffff
+#define AR_CST_TIMEOUT_COUNTER_S 0
+#define AR_CST_TIMEOUT_LIMIT_M 0xffff0000
+#define AR_CST_TIMEOUT_LIMIT_S 16
+
+/* Bits for AR_ISR. */
+#define AR_ISR_RXOK 0x00000001
+#define AR_ISR_HP_RXOK 0x00000001
+#define AR_ISR_RXDESC 0x00000002
+#define AR_ISR_LP_RXOK 0x00000002
+#define AR_ISR_RXERR 0x00000004
+#define AR_ISR_RXNOPKT 0x00000008
+#define AR_ISR_RXEOL 0x00000010
+#define AR_ISR_RXORN 0x00000020
+#define AR_ISR_TXOK 0x00000040
+#define AR_ISR_TXDESC 0x00000080
+#define AR_ISR_TXERR 0x00000100
+#define AR_ISR_TXNOPKT 0x00000200
+#define AR_ISR_TXEOL 0x00000400
+#define AR_ISR_TXURN 0x00000800
+#define AR_ISR_MIB 0x00001000
+#define AR_ISR_SWI 0x00002000
+#define AR_ISR_RXPHY 0x00004000
+#define AR_ISR_RXKCM 0x00008000
+#define AR_ISR_SWBA 0x00010000
+#define AR_ISR_BRSSI 0x00020000
+#define AR_ISR_BMISS 0x00040000
+#define AR_ISR_TXMINTR 0x00080000
+#define AR_ISR_BNR 0x00100000
+#define AR_ISR_RXCHIRP 0x00200000
+#define AR_ISR_BCNMISC 0x00800000
+#define AR_ISR_TIM 0x00800000
+#define AR_ISR_RXMINTR 0x01000000
+#define AR_ISR_QCBROVF 0x02000000
+#define AR_ISR_QCBRURN 0x04000000
+#define AR_ISR_QTRIG 0x08000000
+#define AR_ISR_GENTMR 0x10000000
+#define AR_ISR_TXINTM 0x40000000
+#define AR_ISR_RXINTM 0x80000000
+
+/* Bits for AR_ISR_S0. */
+#define AR_ISR_S0_QCU_TXOK_M 0x000003ff
+#define AR_ISR_S0_QCU_TXOK_S 0
+#define AR_ISR_S0_QCU_TXDESC_M 0x03ff0000
+#define AR_ISR_S0_QCU_TXDESC_S 16
+
+/* Bits for AR_ISR_S1. */
+#define AR_ISR_S1_QCU_TXERR_M 0x000003ff
+#define AR_ISR_S1_QCU_TXERR_S 0
+#define AR_ISR_S1_QCU_TXEOL_M 0x03ff0000
+#define AR_ISR_S1_QCU_TXEOL_S 16
+
+/* Bits for AR_ISR_S2. */
+#define AR_ISR_S2_QCU_TXURN_M 0x000003ff
+#define AR_ISR_S2_QCU_TXURN_S 0
+#define AR_ISR_S2_BB_WATCHDOG 0x00010000
+#define AR_ISR_S2_CST 0x00400000
+#define AR_ISR_S2_GTT 0x00800000
+#define AR_ISR_S2_TIM 0x01000000
+#define AR_ISR_S2_CABEND 0x02000000
+#define AR_ISR_S2_DTIMSYNC 0x04000000
+#define AR_ISR_S2_BCNTO 0x08000000
+#define AR_ISR_S2_CABTO 0x10000000
+#define AR_ISR_S2_DTIM 0x20000000
+#define AR_ISR_S2_TSFOOR 0x40000000
+#define AR_ISR_S2_TBTT_TIME 0x80000000
+
+/* Bits for AR_ISR_S3. */
+#define AR_ISR_S3_QCU_QCBROVF_M 0x000003ff
+#define AR_ISR_S3_QCU_QCBROVF_S 0
+#define AR_ISR_S3_QCU_QCBRURN_M 0x03ff0000
+#define AR_ISR_S3_QCU_QCBRURN_S 0
+
+/* Bits for AR_ISR_S4. */
+#define AR_ISR_S4_QCU_QTRIG_M 0x000003ff
+#define AR_ISR_S4_QCU_QTRIG_S 0
+
+/* Bits for AR_ISR_S5. */
+#define AR_ISR_S5_TIMER_TRIG_M 0x000000ff
+#define AR_ISR_S5_TIMER_TRIG_S 0
+#define AR_ISR_S5_TIMER_THRESH_M 0x0007fe00
+#define AR_ISR_S5_TIMER_THRESH_S 9
+#define AR_ISR_S5_TIM_TIMER 0x00000010
+#define AR_ISR_S5_DTIM_TIMER 0x00000020
+#define AR_ISR_S5_GENTIMER_TRIG_M 0x0000ff80
+#define AR_ISR_S5_GENTIMER_TRIG_S 0
+#define AR_ISR_S5_GENTIMER_THRESH_M 0xff800000
+#define AR_ISR_S5_GENTIMER_THRESH_S 16
+
+/* Bits for AR_IMR. */
+#define AR_IMR_RXOK 0x00000001
+#define AR_IMR_HP_RXOK 0x00000001
+#define AR_IMR_RXDESC 0x00000002
+#define AR_IMR_LP_RXOK 0x00000002
+#define AR_IMR_RXERR 0x00000004
+#define AR_IMR_RXNOPKT 0x00000008
+#define AR_IMR_RXEOL 0x00000010
+#define AR_IMR_RXORN 0x00000020
+#define AR_IMR_TXOK 0x00000040
+#define AR_IMR_TXDESC 0x00000080
+#define AR_IMR_TXERR 0x00000100
+#define AR_IMR_TXNOPKT 0x00000200
+#define AR_IMR_TXEOL 0x00000400
+#define AR_IMR_TXURN 0x00000800
+#define AR_IMR_MIB 0x00001000
+#define AR_IMR_SWI 0x00002000
+#define AR_IMR_RXPHY 0x00004000
+#define AR_IMR_RXKCM 0x00008000
+#define AR_IMR_SWBA 0x00010000
+#define AR_IMR_BRSSI 0x00020000
+#define AR_IMR_BMISS 0x00040000
+#define AR_IMR_TXMINTR 0x00080000
+#define AR_IMR_BNR 0x00100000
+#define AR_IMR_RXCHIRP 0x00200000
+#define AR_IMR_BCNMISC 0x00800000
+#define AR_IMR_TIM 0x00800000
+#define AR_IMR_RXMINTR 0x01000000
+#define AR_IMR_QCBROVF 0x02000000
+#define AR_IMR_QCBRURN 0x04000000
+#define AR_IMR_QTRIG 0x08000000
+#define AR_IMR_GENTMR 0x10000000
+#define AR_IMR_TXINTM 0x40000000
+#define AR_IMR_RXINTM 0x80000000
+
+#define AR_IMR_DEFAULT \
+ (AR_IMR_TXERR | AR_IMR_TXURN | AR_IMR_RXERR | \
+ AR_IMR_RXORN | AR_IMR_BCNMISC | AR_IMR_RXINTM | \
+ AR_IMR_RXMINTR | AR_IMR_TXOK)
+#define AR_IMR_HOSTAP (AR_IMR_DEFAULT | AR_IMR_MIB)
+
+/* Bits for AR_IMR_S0. */
+#define AR_IMR_S0_QCU_TXOK(qid) (1 << (qid))
+#define AR_IMR_S0_QCU_TXDESC(qid) (1 << (16 + (qid)))
+
+/* Bits for AR_IMR_S1. */
+#define AR_IMR_S1_QCU_TXERR(qid) (1 << (qid))
+#define AR_IMR_S1_QCU_TXEOL(qid) (1 << (16 + (qid)))
+
+/* Bits for AR_IMR_S2. */
+#define AR_IMR_S2_QCU_TXURN(qid) (1 << (qid))
+#define AR_IMR_S2_CST 0x00400000
+#define AR_IMR_S2_GTT 0x00800000
+#define AR_IMR_S2_TIM 0x01000000
+#define AR_IMR_S2_CABEND 0x02000000
+#define AR_IMR_S2_DTIMSYNC 0x04000000
+#define AR_IMR_S2_BCNTO 0x08000000
+#define AR_IMR_S2_CABTO 0x10000000
+#define AR_IMR_S2_DTIM 0x20000000
+#define AR_IMR_S2_TSFOOR 0x40000000
+
+/* Bits for AR_IMR_S3. */
+#define AR_IMR_S3_QCU_QCBROVF(qid) (1 << (qid))
+#define AR_IMR_S3_QCU_QCBRURN(qid) (1 << (16 + (qid)))
+
+/* Bits for AR_IMR_S4. */
+#define AR_IMR_S4_QCU_QTRIG(qid) (1 << (qid))
+
+/* Bits for AR_IMR_S5. */
+#define AR_IMR_S5_TIM_TIMER 0x00000010
+#define AR_IMR_S5_DTIM_TIMER 0x00000020
+#define AR_IMR_S5_TIMER_TRIG_M 0x000000ff
+#define AR_IMR_S5_TIMER_TRIG_S 0
+#define AR_IMR_S5_TIMER_THRESH_M 0x0000ff00
+#define AR_IMR_S5_TIMER_THRESH_S 0
+
+#define AR_NUM_QCU 10
+#define AR_QCU(x) (1 << (x))
+
+/* Bits for AR_Q_TXE. */
+#define AR_Q_TXE_M 0x000003ff
+#define AR_Q_TXE_S 0
+
+/* Bits for AR_Q_TXD. */
+#define AR_Q_TXD_M 0x000003ff
+#define AR_Q_TXD_S 0
+
+/* Bits for AR_QCBRCFG_*. */
+#define AR_Q_CBRCFG_INTERVAL_M 0x00ffffff
+#define AR_Q_CBRCFG_INTERVAL_S 0
+#define AR_Q_CBRCFG_OVF_THRESH_M 0xff000000
+#define AR_Q_CBRCFG_OVF_THRESH_S 24
+
+/* Bits for AR_QRDYTIMECFG_*. */
+#define AR_Q_RDYTIMECFG_DURATION_M 0x00ffffff
+#define AR_Q_RDYTIMECFG_DURATION_S 0
+#define AR_Q_RDYTIMECFG_EN 0x01000000
+
+/* Bits for AR_QMISC_*. */
+#define AR_Q_MISC_FSP_M 0x0000000f
+#define AR_Q_MISC_FSP_S 0
+#define AR_Q_MISC_FSP_ASAP 0
+#define AR_Q_MISC_FSP_CBR 1
+#define AR_Q_MISC_FSP_DBA_GATED 2
+#define AR_Q_MISC_FSP_TIM_GATED 3
+#define AR_Q_MISC_FSP_BEACON_SENT_GATED 4
+#define AR_Q_MISC_FSP_BEACON_RCVD_GATED 5
+#define AR_Q_MISC_ONE_SHOT_EN 0x00000010
+#define AR_Q_MISC_CBR_INCR_DIS1 0x00000020
+#define AR_Q_MISC_CBR_INCR_DIS0 0x00000040
+#define AR_Q_MISC_BEACON_USE 0x00000080
+#define AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN 0x00000100
+#define AR_Q_MISC_RDYTIME_EXP_POLICY 0x00000200
+#define AR_Q_MISC_RESET_CBR_EXP_CTR 0x00000400
+#define AR_Q_MISC_DCU_EARLY_TERM_REQ 0x00000800
+
+/* Bits for AR_QSTS_*. */
+#define AR_Q_STS_PEND_FR_CNT_M 0x00000003
+#define AR_Q_STS_PEND_FR_CNT_S 0
+#define AR_Q_STS_CBR_EXP_CNT_M 0x0000ff00
+#define AR_Q_STS_CBR_EXP_CNT_S 8
+
+/* Bits for AR_Q_DESC_CRCCHK. */
+#define AR_Q_DESC_CRCCHK_EN 0x00000001
+
+#define AR_NUM_DCU 10
+#define AR_DCU(x) (1 << (x))
+
+/* Bits for AR_D_QCUMASK_*. */
+#define AR_D_QCUMASK_M 0x000003ff
+#define AR_D_QCUMASK_S 0
+
+/* Bits for AR_D_GBL_IFS_SIFS. */
+#define AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR 0x000003ab
+
+/* Bits for AR_D_TXBLK_CMD. */
+#define AR_D_TXBLK_WRITE_BITMASK_M 0x0000ffff
+#define AR_D_TXBLK_WRITE_BITMASK_S 0
+#define AR_D_TXBLK_WRITE_SLICE_M 0x000f0000
+#define AR_D_TXBLK_WRITE_SLICE_S 16
+#define AR_D_TXBLK_WRITE_DCU_M 0x00f00000
+#define AR_D_TXBLK_WRITE_DCU_S 20
+#define AR_D_TXBLK_WRITE_COMMAND_M 0x0f000000
+#define AR_D_TXBLK_WRITE_COMMAND_S 24
+
+/* Bits for AR_DLCL_IFS. */
+#define AR_D_LCL_IFS_CWMIN_M 0x000003ff
+#define AR_D_LCL_IFS_CWMIN_S 0
+#define AR_D_LCL_IFS_CWMAX_M 0x000ffc00
+#define AR_D_LCL_IFS_CWMAX_S 10
+#define AR_D_LCL_IFS_AIFS_M 0x0ff00000
+#define AR_D_LCL_IFS_AIFS_S 20
+
+/* Bits for AR_D_GBL_IFS_SLOT. */
+#define AR_D_GBL_IFS_SLOT_M 0x0000ffff
+#define AR_D_GBL_IFS_SLOT_S 0
+#define AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR 0x00000420
+
+/* Bits for AR_DRETRY_LIMIT_*. */
+#define AR_D_RETRY_LIMIT_FR_SH_M 0x0000000f
+#define AR_D_RETRY_LIMIT_FR_SH_S 0
+#define AR_D_RETRY_LIMIT_STA_SH_M 0x00003f00
+#define AR_D_RETRY_LIMIT_STA_SH_S 8
+#define AR_D_RETRY_LIMIT_STA_LG_M 0x000fc000
+#define AR_D_RETRY_LIMIT_STA_LG_S 14
+
+/* Bits for AR_D_GBL_IFS_EIFS. */
+#define AR_D_GBL_IFS_EIFS_M 0x0000ffff
+#define AR_D_GBL_IFS_EIFS_S 0
+#define AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR 0x0000a5eb
+
+/* Bits for AR_DCHNTIME_*. */
+#define AR_D_CHNTIME_DUR_M 0x000fffff
+#define AR_D_CHNTIME_DUR_S 0
+#define AR_D_CHNTIME_EN 0x00100000
+
+/* Bits for AR_D_GBL_IFS_MISC. */
+#define AR_D_GBL_IFS_MISC_LFSR_SLICE_SEL 0x00000007
+#define AR_D_GBL_IFS_MISC_TURBO_MODE 0x00000008
+#define AR_D_GBL_IFS_MISC_USEC_DURATION 0x000ffc00
+#define AR_D_GBL_IFS_MISC_DCU_ARBITER_DLY 0x00300000
+#define AR_D_GBL_IFS_MISC_RANDOM_LFSR_SLICE_DIS 0x01000000
+#define AR_D_GBL_IFS_MISC_SLOT_XMIT_WIND_LEN 0x06000000
+#define AR_D_GBL_IFS_MISC_FORCE_XMIT_SLOT_BOUND 0x08000000
+#define AR_D_GBL_IFS_MISC_IGNORE_BACKOFF 0x10000000
+
+/* Bits for AR_DMISC_*. */
+#define AR_D_MISC_BKOFF_THRESH_M 0x0000003f
+#define AR_D_MISC_BKOFF_THRESH_S 0
+#define AR_D_MISC_RETRY_CNT_RESET_EN 0x00000040
+#define AR_D_MISC_CW_RESET_EN 0x00000080
+#define AR_D_MISC_FRAG_WAIT_EN 0x00000100
+#define AR_D_MISC_FRAG_BKOFF_EN 0x00000200
+#define AR_D_MISC_CW_BKOFF_EN 0x00001000
+#define AR_D_MISC_VIR_COL_HANDLING_M 0x0000c000
+#define AR_D_MISC_VIR_COL_HANDLING_S 14
+#define AR_D_MISC_VIR_COL_HANDLING_DEFAULT 0
+#define AR_D_MISC_VIR_COL_HANDLING_IGNORE 1
+#define AR_D_MISC_BEACON_USE 0x00010000
+#define AR_D_MISC_ARB_LOCKOUT_CNTRL_M 0x00060000
+#define AR_D_MISC_ARB_LOCKOUT_CNTRL_S 17
+#define AR_D_MISC_ARB_LOCKOUT_CNTRL_NONE 0
+#define AR_D_MISC_ARB_LOCKOUT_CNTRL_INTRA_FR 1
+#define AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL 2
+#define AR_D_MISC_ARB_LOCKOUT_IGNORE 0x00080000
+#define AR_D_MISC_SEQ_NUM_INCR_DIS 0x00100000
+#define AR_D_MISC_POST_FR_BKOFF_DIS 0x00200000
+#define AR_D_MISC_VIT_COL_CW_BKOFF_EN 0x00400000
+#define AR_D_MISC_BLOWN_IFS_RETRY_EN 0x00800000
+
+/* Bits for AR_D_FPCTL. */
+#define AR_D_FPCTL_DCU_M 0x0000000f
+#define AR_D_FPCTL_DCU_S 0
+#define AR_D_FPCTL_PREFETCH_EN 0x00000010
+#define AR_D_FPCTL_BURST_PREFETCH_M 0x00007fe0
+#define AR_D_FPCTL_BURST_PREFETCH_S 5
+
+/* Bits for AR_D_TXPSE. */
+#define AR_D_TXPSE_CTRL_M 0x000003ff
+#define AR_D_TXPSE_CTRL_S 0
+#define AR_D_TXPSE_STATUS 0x00010000
+
+/* Bits for AR_D_TXSLOTMASK. */
+#define AR_D_TXSLOTMASK_NUM 0x0000000f
+
+/* Bits for AR_MAC_SLEEP. */
+#define AR_MAC_SLEEP_MAC_ASLEEP 0x00000001
+
+/* Bits for AR_CFG_LED. */
+#define AR_CFG_SCLK_RATE_IND_M 0x00000003
+#define AR_CFG_SCLK_RATE_IND_S 0
+#define AR_CFG_SCLK_32MHZ 0
+#define AR_CFG_SCLK_4MHZ 1
+#define AR_CFG_SCLK_1MHZ 2
+#define AR_CFG_SCLK_32KHZ 3
+#define AR_CFG_LED_BLINK_SLOW 0x00000008
+#define AR_CFG_LED_BLINK_THRESH_SEL_M 0x00000070
+#define AR_CFG_LED_BLINK_THRESH_SEL_S 4
+#define AR_CFG_LED_MODE_SEL_M 0x00000380
+#define AR_CFG_LED_MODE_SEL_S 7
+#define AR_CFG_LED_POWER_M 0x00000280
+#define AR_CFG_LED_POWER_S 7
+#define AR_CFG_LED_NETWORK_M 0x00000300
+#define AR_CFG_LED_NETWORK_S 7
+#define AR_CFG_LED_MODE_PROP 0
+#define AR_CFG_LED_MODE_RPROP 1
+#define AR_CFG_LED_MODE_SPLIT 2
+#define AR_CFG_LED_MODE_RAND 3
+#define AR_CFG_LED_MODE_POWER_OFF 4
+#define AR_CFG_LED_MODE_POWER_ON 5
+#define AR_CFG_LED_MODE_NETWORK_OFF 4
+#define AR_CFG_LED_MODE_NETWORK_ON 6
+#define AR_CFG_LED_ASSOC_CTL_M 0x00000c00
+#define AR_CFG_LED_ASSOC_CTL_S 10
+#define AR_CFG_LED_ASSOC_NONE 0
+#define AR_CFG_LED_ASSOC_ACTIVE 1
+#define AR_CFG_LED_ASSOC_PENDING 2
+
+/* Bit for AR_RC. */
+#define AR_RC_AHB 0x00000001
+#define AR_RC_APB 0x00000002
+#define AR_RC_HOSTIF 0x00000100
+
+/* Bits for AR_WA. */
+#define AR5416_WA_DEFAULT 0x0000073f
+#define AR9280_WA_DEFAULT 0x0040073b
+#define AR9285_WA_DEFAULT 0x004a050b
+#define AR_WA_UNTIE_RESET_EN 0x00008000
+#define AR_WA_RESET_EN 0x00040000
+#define AR_WA_ANALOG_SHIFT 0x00100000
+#define AR_WA_POR_SHORT 0x00200000
+
+/* Bits for AR_PM_STATE. */
+#define AR_PM_STATE_PME_D3COLD_VAUX 0x00100000
+
+/* Bits for AR_PCIE_PM_CTRL. */
+#define AR_PCIE_PM_CTRL_ENA 0x00080000
+
+/* Bits for AR_HOST_TIMEOUT. */
+#define AR_HOST_TIMEOUT_APB_CNTR_M 0x0000ffff
+#define AR_HOST_TIMEOUT_APB_CNTR_S 0
+#define AR_HOST_TIMEOUT_LCL_CNTR_M 0xffff0000
+#define AR_HOST_TIMEOUT_LCL_CNTR_S 16
+
+/* Bits for AR_EEPROM. */
+#define AR_EEPROM_ABSENT 0x00000100
+#define AR_EEPROM_CORRUPT 0x00000200
+#define AR_EEPROM_PROT_MASK_M 0x03fffc00
+#define AR_EEPROM_PROT_MASK_S 10
+
+/* Bits for AR_SREV. */
+#define AR_SREV_ID_M 0x000000ff
+#define AR_SREV_ID_S 0
+#define AR_SREV_REVISION_M 0x00000007
+#define AR_SREV_REVISION_S 0
+#define AR_SREV_VERSION_M 0x000000f0
+#define AR_SREV_VERSION_S 4
+#define AR_SREV_VERSION2_M 0xfffc0000
+#define AR_SREV_VERSION2_S 12 /* XXX Hack. */
+#define AR_SREV_TYPE2_M 0x0003f000
+#define AR_SREV_TYPE2_S 12
+#define AR_SREV_TYPE2_CHAIN 0x00001000
+#define AR_SREV_TYPE2_HOST_MODE 0x00002000
+#define AR_SREV_REVISION2_M 0x00000f00
+#define AR_SREV_REVISION2_S 8
+#define AR_SREV_VERSION_5416_PCI 0x00d
+#define AR_SREV_VERSION_5416_PCIE 0x00c
+#define AR_SREV_REVISION_5416_10 0
+#define AR_SREV_REVISION_5416_20 1
+#define AR_SREV_REVISION_5416_22 2
+#define AR_SREV_VERSION_9100 0x014
+#define AR_SREV_VERSION_9160 0x040
+#define AR_SREV_REVISION_9160_10 0
+#define AR_SREV_REVISION_9160_11 1
+#define AR_SREV_VERSION_9280 0x080
+#define AR_SREV_REVISION_9280_10 0
+#define AR_SREV_REVISION_9280_20 1
+#define AR_SREV_REVISION_9280_21 2
+#define AR_SREV_VERSION_9285 0x0c0
+#define AR_SREV_REVISION_9285_10 0
+#define AR_SREV_REVISION_9285_11 1
+#define AR_SREV_REVISION_9285_12 2
+#define AR_SREV_VERSION_9271 0x140
+#define AR_SREV_REVISION_9271_10 0
+#define AR_SREV_REVISION_9271_11 1
+#define AR_SREV_VERSION_9287 0x180
+#define AR_SREV_REVISION_9287_10 0
+#define AR_SREV_REVISION_9287_11 1
+#define AR_SREV_REVISION_9287_12 2
+#define AR_SREV_REVISION_9287_13 3
+#define AR_SREV_VERSION_9380 0x1c0
+#define AR_SREV_REVISION_9380_10 0
+#define AR_SREV_REVISION_9380_20 2
+#define AR_SREV_VERSION_9485 0x240
+#define AR_SREV_REVISION_9485_10 0
+
+/* Bits for AR_AHB_MODE. */
+#define AR_AHB_EXACT_WR_EN 0x00000000
+#define AR_AHB_BUF_WR_EN 0x00000001
+#define AR_AHB_EXACT_RD_EN 0x00000000
+#define AR_AHB_CACHELINE_RD_EN 0x00000002
+#define AR_AHB_PREFETCH_RD_EN 0x00000004
+#define AR_AHB_PAGE_SIZE_1K 0x00000000
+#define AR_AHB_PAGE_SIZE_2K 0x00000008
+#define AR_AHB_PAGE_SIZE_4K 0x00000010
+#define AR_AHB_CUSTOM_BURST_M 0x000000c0
+#define AR_AHB_CUSTOM_BURST_S 6
+#define AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL 3
+
+/* Bits for AR_INTR_SYNC_CAUSE. */
+#define AR_INTR_SYNC_RTC_IRQ 0x00000001
+#define AR_INTR_SYNC_MAC_IRQ 0x00000002
+#define AR_INTR_SYNC_EEPROM_ILLEGAL_ACCESS 0x00000004
+#define AR_INTR_SYNC_APB_TIMEOUT 0x00000008
+#define AR_INTR_SYNC_PCI_MODE_CONFLICT 0x00000010
+#define AR_INTR_SYNC_HOST1_FATAL 0x00000020
+#define AR_INTR_SYNC_HOST1_PERR 0x00000040
+#define AR_INTR_SYNC_TRCV_FIFO_PERR 0x00000080
+#define AR_INTR_SYNC_RADM_CPL_EP 0x00000100
+#define AR_INTR_SYNC_RADM_CPL_DLLP_ABORT 0x00000200
+#define AR_INTR_SYNC_RADM_CPL_TLP_ABORT 0x00000400
+#define AR_INTR_SYNC_RADM_CPL_ECRC_ERR 0x00000800
+#define AR_INTR_SYNC_RADM_CPL_TIMEOUT 0x00001000
+#define AR_INTR_SYNC_LOCAL_TIMEOUT 0x00002000
+#define AR_INTR_SYNC_PM_ACCESS 0x00004000
+#define AR_INTR_SYNC_MAC_AWAKE 0x00008000
+#define AR_INTR_SYNC_MAC_ASLEEP 0x00010000
+#define AR_INTR_SYNC_MAC_SLEEP_ACCESS 0x00020000
+#define AR_INTR_SYNC_ALL 0x0003ffff
+#define AR_INTR_SYNC_GPIO_PIN(i) (1 << (18 + (i)))
+
+#define AR_INTR_SYNC_DEFAULT \
+ (AR_INTR_SYNC_HOST1_FATAL | \
+ AR_INTR_SYNC_HOST1_PERR | \
+ AR_INTR_SYNC_RADM_CPL_EP | \
+ AR_INTR_SYNC_RADM_CPL_DLLP_ABORT | \
+ AR_INTR_SYNC_RADM_CPL_TLP_ABORT | \
+ AR_INTR_SYNC_RADM_CPL_ECRC_ERR | \
+ AR_INTR_SYNC_RADM_CPL_TIMEOUT | \
+ AR_INTR_SYNC_LOCAL_TIMEOUT | \
+ AR_INTR_SYNC_MAC_SLEEP_ACCESS)
+
+/* Bits for AR_INTR_ASYNC_CAUSE. */
+#define AR_INTR_RTC_IRQ 0x00000001
+#define AR_INTR_MAC_IRQ 0x00000002
+#define AR_INTR_EEP_PROT_ACCESS 0x00000004
+#define AR_INTR_MAC_AWAKE 0x00020000
+#define AR_INTR_MAC_ASLEEP 0x00040000
+#define AR_INTR_GPIO_PIN(i) (1 << (18 + (i)))
+#define AR_INTR_SPURIOUS 0xffffffff
+
+/* Bits for AR_GPIO_OE_OUT. */
+#define AR_GPIO_OE_OUT_DRV_M 0x00000003
+#define AR_GPIO_OE_OUT_DRV_S 0
+#define AR_GPIO_OE_OUT_DRV_NO 0
+#define AR_GPIO_OE_OUT_DRV_LOW 1
+#define AR_GPIO_OE_OUT_DRV_HI 2
+#define AR_GPIO_OE_OUT_DRV_ALL 3
+
+/* Bits for AR_GPIO_INTR_POL. */
+#define AR_GPIO_INTR_POL_PIN(i) (1 << (i))
+
+/* Bits for AR_GPIO_INPUT_EN_VAL. */
+#define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF 0x00000004
+#define AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF 0x00000008
+#define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_DEF 0x00000010
+#define AR_GPIO_INPUT_EN_VAL_RFSILENT_DEF 0x00000080
+#define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB 0x00000400
+#define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB 0x00001000
+#define AR_GPIO_INPUT_EN_VAL_RFSILENT_BB 0x00008000
+#define AR_GPIO_RTC_RESET_OVERRIDE_ENABLE 0x00010000
+#define AR_GPIO_JTAG_DISABLE 0x00020000
+
+/* Bits for AR_GPIO_INPUT_MUX1. */
+#define AR_GPIO_INPUT_MUX1_BT_PRIORITY_M 0x00000f00
+#define AR_GPIO_INPUT_MUX1_BT_PRIORITY_S 8
+#define AR_GPIO_INPUT_MUX1_BT_ACTIVE_M 0x000f0000
+#define AR_GPIO_INPUT_MUX1_BT_ACTIVE_S 16
+
+/* Bits for AR_GPIO_INPUT_MUX2. */
+#define AR_GPIO_INPUT_MUX2_CLK25_M 0x0000000f
+#define AR_GPIO_INPUT_MUX2_CLK25_S 0
+#define AR_GPIO_INPUT_MUX2_RFSILENT_M 0x000000f0
+#define AR_GPIO_INPUT_MUX2_RFSILENT_S 4
+#define AR_GPIO_INPUT_MUX2_RTC_RESET_M 0x00000f00
+#define AR_GPIO_INPUT_MUX2_RTC_RESET_S 8
+
+/* Bits for AR_GPIO_OUTPUT_MUX[1-3]. */
+#define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0
+#define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
+#define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2
+#define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3
+#define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4
+#define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5
+#define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6
+
+/* Bits for AR_EEPROM_STATUS_DATA. */
+#define AR_EEPROM_STATUS_DATA_VAL_M 0x0000ffff
+#define AR_EEPROM_STATUS_DATA_VAL_S 0
+#define AR_EEPROM_STATUS_DATA_BUSY 0x00010000
+#define AR_EEPROM_STATUS_DATA_BUSY_ACCESS 0x00020000
+#define AR_EEPROM_STATUS_DATA_PROT_ACCESS 0x00040000
+#define AR_EEPROM_STATUS_DATA_ABSENT_ACCESS 0x00080000
+
+/* Bits for AR_PCIE_MSI. */
+#define AR_PCIE_MSI_ENABLE 0x00000001
+
+/* Bits for AR_RTC_RC. */
+#define AR_RTC_RC_MAC_WARM 0x00000001
+#define AR_RTC_RC_MAC_COLD 0x00000002
+#define AR_RTC_RC_COLD_RESET 0x00000004
+#define AR_RTC_RC_WARM_RESET 0x00000008
+
+/* Bits for AR_RTC_REG_CONTROL1. */
+#define AR_RTC_REG_CONTROL1_SWREG_PROGRAM 0x00000001
+
+/* Bits for AR_RTC_PLL_CONTROL. */
+#define AR_RTC_PLL_DIV_M 0x0000001f
+#define AR_RTC_PLL_DIV_S 0
+#define AR_RTC_PLL_DIV2 0x00000020
+#define AR_RTC_PLL_REFDIV_5 0x000000c0
+#define AR_RTC_PLL_CLKSEL_M 0x00000300
+#define AR_RTC_PLL_CLKSEL_S 8
+#define AR_RTC_9160_PLL_DIV_M 0x000003ff
+#define AR_RTC_9160_PLL_DIV_S 0
+#define AR_RTC_9160_PLL_REFDIV_M 0x00003c00
+#define AR_RTC_9160_PLL_REFDIV_S 10
+#define AR_RTC_9160_PLL_CLKSEL_M 0x0000c000
+#define AR_RTC_9160_PLL_CLKSEL_S 14
+
+/* Bits for AR_RTC_RESET. */
+#define AR_RTC_RESET_EN 0x00000001
+
+/* Bits for AR_RTC_STATUS. */
+#define AR_RTC_STATUS_M 0x0000000f
+#define AR_RTC_STATUS_S 0
+#define AR_RTC_STATUS_SHUTDOWN 0x00000001
+#define AR_RTC_STATUS_ON 0x00000002
+#define AR_RTC_STATUS_SLEEP 0x00000004
+#define AR_RTC_STATUS_WAKEUP 0x00000008
+
+/* Bits for AR_RTC_SLEEP_CLK. */
+#define AR_RTC_FORCE_DERIVED_CLK 0x00000002
+#define AR_RTC_FORCE_SWREG_PRD 0x00000004
+
+/* Bits for AR_RTC_FORCE_WAKE. */
+#define AR_RTC_FORCE_WAKE_EN 0x00000001
+#define AR_RTC_FORCE_WAKE_ON_INT 0x00000002
+
+/* Bits for AR_STA_ID1. */
+#define AR_STA_ID1_SADH_M 0x0000ffff
+#define AR_STA_ID1_SADH_S 0
+#define AR_STA_ID1_STA_AP 0x00010000
+#define AR_STA_ID1_ADHOC 0x00020000
+#define AR_STA_ID1_PWR_SAV 0x00040000
+#define AR_STA_ID1_KSRCHDIS 0x00080000
+#define AR_STA_ID1_PCF 0x00100000
+#define AR_STA_ID1_USE_DEFANT 0x00200000
+#define AR_STA_ID1_DEFANT_UPDATE 0x00400000
+#define AR_STA_ID1_RTS_USE_DEF 0x00800000
+#define AR_STA_ID1_ACKCTS_6MB 0x01000000
+#define AR_STA_ID1_BASE_RATE_11B 0x02000000
+#define AR_STA_ID1_SECTOR_SELF_GEN 0x04000000
+#define AR_STA_ID1_CRPT_MIC_ENABLE 0x08000000
+#define AR_STA_ID1_KSRCH_MODE 0x10000000
+#define AR_STA_ID1_PRESERVE_SEQNUM 0x20000000
+#define AR_STA_ID1_CBCIV_ENDIAN 0x40000000
+#define AR_STA_ID1_MCAST_KSRCH 0x80000000
+
+/* Bits for AR_BSS_ID1. */
+#define AR_BSS_ID1_U16_M 0x0000ffff
+#define AR_BSS_ID1_U16_S 0
+#define AR_BSS_ID1_AID_M 0x07ff0000
+#define AR_BSS_ID1_AID_S 16
+
+/* Bits for AR_TIME_OUT. */
+#define AR_TIME_OUT_ACK_M 0x00003fff
+#define AR_TIME_OUT_ACK_S 0
+#define AR_TIME_OUT_CTS_M 0x3fff0000
+#define AR_TIME_OUT_CTS_S 16
+#define AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR 0x16001d56
+
+/* Bits for AR_RSSI_THR. */
+#define AR_RSSI_THR_M 0x000000ff
+#define AR_RSSI_THR_S 0
+#define AR_RSSI_THR_BM_THR_M 0x0000ff00
+#define AR_RSSI_THR_BM_THR_S 8
+#define AR_RSSI_BCN_WEIGHT_M 0x1f000000
+#define AR_RSSI_BCN_WEIGHT_S 24
+#define AR_RSSI_BCN_RSSI_RST 0x20000000
+
+/* Bits for AR_USEC. */
+#define AR_USEC_USEC_M 0x0000007f
+#define AR_USEC_USEC_S 0
+#define AR_USEC_TX_LAT_M 0x007fc000
+#define AR_USEC_TX_LAT_S 14
+#define AR_USEC_RX_LAT_M 0x1f800000
+#define AR_USEC_RX_LAT_S 23
+#define AR_USEC_ASYNC_FIFO_DUR 0x12e00074
+
+/* Bits for AR_RESET_TSF. */
+#define AR_RESET_TSF_ONCE 0x01000000
+
+/* Bits for AR_RX_FILTER. */
+#define AR_RX_FILTER_UCAST 0x00000001
+#define AR_RX_FILTER_MCAST 0x00000002
+#define AR_RX_FILTER_BCAST 0x00000004
+#define AR_RX_FILTER_CONTROL 0x00000008
+#define AR_RX_FILTER_BEACON 0x00000010
+#define AR_RX_FILTER_PROM 0x00000020
+#define AR_RX_FILTER_PROBEREQ 0x00000080
+#define AR_RX_FILTER_MYBEACON 0x00000200
+#define AR_RX_FILTER_COMPR_BAR 0x00000400
+#define AR_RX_FILTER_PSPOLL 0x00004000
+
+/* Bits for AR_DIAG_SW. */
+#define AR_DIAG_CACHE_ACK 0x00000001
+#define AR_DIAG_ACK_DIS 0x00000002
+#define AR_DIAG_CTS_DIS 0x00000004
+#define AR_DIAG_ENCRYPT_DIS 0x00000008
+#define AR_DIAG_DECRYPT_DIS 0x00000010
+#define AR_DIAG_RX_DIS 0x00000020
+#define AR_DIAG_LOOP_BACK 0x00000040
+#define AR_DIAG_CORR_FCS 0x00000080
+#define AR_DIAG_CHAN_INFO 0x00000100
+#define AR_DIAG_SCRAM_SEED_M 0x0001fe00
+#define AR_DIAG_SCRAM_SEED_S 8 /* XXX should be 9? */
+#define AR_DIAG_FRAME_NV0 0x00020000
+#define AR_DIAG_OBS_PT_SEL1_M 0x000c0000
+#define AR_DIAG_OBS_PT_SEL1_S 18
+#define AR_DIAG_FORCE_RX_CLEAR 0x00100000
+#define AR_DIAG_IGNORE_VIRT_CS 0x00200000
+#define AR_DIAG_FORCE_CH_IDLE_HIGH 0x00400000
+#define AR_DIAG_EIFS_CTRL_ENA 0x00800000
+#define AR_DIAG_DUAL_CHAIN_INFO 0x01000000
+#define AR_DIAG_RX_ABORT 0x02000000
+#define AR_DIAG_SATURATE_CYCLE_CNT 0x04000000
+#define AR_DIAG_OBS_PT_SEL2 0x08000000
+#define AR_DIAG_RX_CLEAR_CTL_LOW 0x10000000
+#define AR_DIAG_RX_CLEAR_EXT_LOW 0x20000000
+
+/* Bits for AR_AES_MUTE_MASK0. */
+#define AR_AES_MUTE_MASK0_FC_M 0x0000ffff
+#define AR_AES_MUTE_MASK0_FC_S 0
+#define AR_AES_MUTE_MASK0_QOS_M 0xffff0000
+#define AR_AES_MUTE_MASK0_QOS_S 16
+
+/* Bits for AR_AES_MUTE_MASK1. */
+#define AR_AES_MUTE_MASK1_SEQ_M 0x0000ffff
+#define AR_AES_MUTE_MASK1_SEQ_S 0
+#define AR_AES_MUTE_MASK1_FC_MGMT_M 0xffff0000
+#define AR_AES_MUTE_MASK1_FC_MGMT_S 16
+#define AR_AES_MUTE_MASK1_FC0_MGMT_M 0x00ff0000
+#define AR_AES_MUTE_MASK1_FC0_MGMT_S 16
+#define AR_AES_MUTE_MASK1_FC1_MGMT_M 0xff000000
+#define AR_AES_MUTE_MASK1_FC1_MGMT_S 24
+
+/* Bits for AR_GATED_CLKS. */
+#define AR_GATED_CLKS_TX 0x00000002
+#define AR_GATED_CLKS_RX 0x00000004
+#define AR_GATED_CLKS_REG 0x00000008
+
+/* Bits for AR_OBS_BUS_CTRL. */
+#define AR_OBS_BUS_SEL_1 0x00040000
+#define AR_OBS_BUS_SEL_2 0x00080000
+#define AR_OBS_BUS_SEL_3 0x000c0000
+#define AR_OBS_BUS_SEL_4 0x08040000
+#define AR_OBS_BUS_SEL_5 0x08080000
+
+/* Bits for AR_OBS_BUS_1. */
+#define AR_OBS_BUS_1_PCU 0x00000001
+#define AR_OBS_BUS_1_RX_END 0x00000002
+#define AR_OBS_BUS_1_RX_WEP 0x00000004
+#define AR_OBS_BUS_1_RX_BEACON 0x00000008
+#define AR_OBS_BUS_1_RX_FILTER 0x00000010
+#define AR_OBS_BUS_1_TX_HCF 0x00000020
+#define AR_OBS_BUS_1_QUIET_TIME 0x00000040
+#define AR_OBS_BUS_1_CHAN_IDLE 0x00000080
+#define AR_OBS_BUS_1_TX_HOLD 0x00000100
+#define AR_OBS_BUS_1_TX_FRAME 0x00000200
+#define AR_OBS_BUS_1_RX_FRAME 0x00000400
+#define AR_OBS_BUS_1_RX_CLEAR 0x00000800
+#define AR_OBS_BUS_1_WEP_STATE_M 0x0003f000
+#define AR_OBS_BUS_1_WEP_STATE_S 12
+#define AR_OBS_BUS_1_RX_STATE_M 0x01f00000
+#define AR_OBS_BUS_1_RX_STATE_S 20
+#define AR_OBS_BUS_1_TX_STATE_M 0x7e000000
+#define AR_OBS_BUS_1_TX_STATE_S 25
+
+/* Bits for AR_SLEEP1. */
+#define AR_SLEEP1_ASSUME_DTIM 0x00080000
+#define AR_SLEEP1_CAB_TIMEOUT_M 0xffe00000
+#define AR_SLEEP1_CAB_TIMEOUT_S 21
+/* Default value. */
+#define AR_CAB_TIMEOUT_VAL 10
+
+/* Bits for AR_SLEEP2. */
+#define AR_SLEEP2_BEACON_TIMEOUT_M 0xffe00000
+#define AR_SLEEP2_BEACON_TIMEOUT_S 21
+
+/* Bits for AR_TPC. */
+#define AR_TPC_ACK_M 0x0000003f
+#define AR_TPC_ACK_S 0
+#define AR_TPC_CTS_M 0x00003f00
+#define AR_TPC_CTS_S 8
+#define AR_TPC_CHIRP_M 0x003f0000
+#define AR_TPC_CHIRP_S 16
+
+/* Bits for AR_QUIET1. */
+#define AR_QUIET1_NEXT_QUIET_M 0x0000ffff
+#define AR_QUIET1_NEXT_QUIET_S 0
+#define AR_QUIET1_QUIET_ENABLE 0x00010000
+#define AR_QUIET1_QUIET_ACK_CTS_ENABLE 0x00020000
+
+/* Bits for AR_QUIET2. */
+#define AR_QUIET2_QUIET_PERIOD_M 0x0000ffff
+#define AR_QUIET2_QUIET_PERIOD_S 0
+#define AR_QUIET2_QUIET_DUR_M 0xffff0000
+#define AR_QUIET2_QUIET_DUR_S 16
+
+/* Bits for AR_TSF_PARM. */
+#define AR_TSF_INCREMENT_M 0x000000ff
+#define AR_TSF_INCREMENT_S 0
+
+/* Bits for AR_QOS_NO_ACK. */
+#define AR_QOS_NO_ACK_TWO_BIT_M 0x0000000f
+#define AR_QOS_NO_ACK_TWO_BIT_S 0
+#define AR_QOS_NO_ACK_BIT_OFF_M 0x0000007f
+#define AR_QOS_NO_ACK_BIT_OFF_S 4
+#define AR_QOS_NO_ACK_BYTE_OFF_M 0x00000180
+#define AR_QOS_NO_ACK_BYTE_OFF_S 7
+
+/* Bits for AR_PHY_ERR. */
+#define AR_PHY_ERR_DCHIRP 0x00000008
+#define AR_PHY_ERR_RADAR 0x00000020
+#define AR_PHY_ERR_OFDM_TIMING 0x00020000
+#define AR_PHY_ERR_CCK_TIMING 0x02000000
+
+/* Bits for AR_PCU_MISC. */
+#define AR_PCU_FORCE_BSSID_MATCH 0x00000001
+#define AR_PCU_MIC_NEW_LOC_ENA 0x00000004
+#define AR_PCU_TX_ADD_TSF 0x00000008
+#define AR_PCU_CCK_SIFS_MODE 0x00000010
+#define AR_PCU_RX_ANT_UPDT 0x00000800
+#define AR_PCU_TXOP_TBTT_LIMIT_ENA 0x00001000
+#define AR_PCU_MISS_BCN_IN_SLEEP 0x00004000
+#define AR_PCU_BUG_12306_FIX_ENA 0x00020000
+#define AR_PCU_FORCE_QUIET_COLL 0x00040000
+#define AR_PCU_BT_ANT_PREVENT_RX 0x00100000
+#define AR_PCU_TBTT_PROTECT 0x00200000
+#define AR_PCU_CLEAR_VMF 0x01000000
+#define AR_PCU_CLEAR_BA_VALID 0x04000000
+
+/* Bits for AR_BT_COEX_MODE. */
+#define AR_BT_TIME_EXTEND_M 0x000000ff
+#define AR_BT_TIME_EXTEND_S 0
+#define AR_BT_TXSTATE_EXTEND 0x00000100
+#define AR_BT_TX_FRAME_EXTEND 0x00000200
+#define AR_BT_MODE_M 0x00000c00
+#define AR_BT_MODE_S 10
+#define AR_BT_MODE_LEGACY 0
+#define AR_BT_MODE_UNSLOTTED 1
+#define AR_BT_MODE_SLOTTED 2
+#define AR_BT_MODE_DISABLED 3
+#define AR_BT_QUIET 0x00001000
+#define AR_BT_QCU_THRESH_M 0x0001e000
+#define AR_BT_QCU_THRESH_S 13
+#define AR_BT_RX_CLEAR_POLARITY 0x00020000
+#define AR_BT_PRIORITY_TIME_M 0x00fc0000
+#define AR_BT_PRIORITY_TIME_S 18
+#define AR_BT_FIRST_SLOT_TIME_M 0xff000000
+#define AR_BT_FIRST_SLOT_TIME_S 24
+
+/* Bits for AR_BT_COEX_WEIGHT. */
+#define AR_BTCOEX_BT_WGHT_M 0x0000ffff
+#define AR_BTCOEX_BT_WGHT_S 0
+#define AR_STOMP_LOW_BT_WGHT 0xff55
+#define AR_BTCOEX_WL_WGHT_M 0xffff0000
+#define AR_BTCOEX_WL_WGHT_S 16
+#define AR_STOMP_LOW_WL_WGHT 0xaaa8
+
+/* Bits for AR_BT_COEX_MODE2. */
+#define AR_BT_BCN_MISS_THRESH_M 0x000000ff
+#define AR_BT_BCN_MISS_THRESH_S 0
+#define AR_BT_BCN_MISS_CNT_M 0x0000ff00
+#define AR_BT_BCN_MISS_CNT_S 8
+#define AR_BT_HOLD_RX_CLEAR 0x00010000
+#define AR_BT_DISABLE_BT_ANT 0x00100000
+
+/* Bits for AR_PCU_TXBUF_CTRL. */
+#define AR_PCU_TXBUF_CTRL_SIZE_M 0x000007ff
+#define AR_PCU_TXBUF_CTRL_SIZE_S 0
+#define AR_PCU_TXBUF_CTRL_USABLE_SIZE 1792
+#define AR9285_PCU_TXBUF_CTRL_USABLE_SIZE (1792 / 2)
+
+/* Bits for AR_PCU_MISC_MODE2. */
+#define AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE 0x00000002
+#define AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT 0x00000004
+#define AR_PCU_MISC_MODE2_AGG_WEP_ENABLE_FIX 0x00000008
+#define AR_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE 0x00000040
+#define AR_PCU_MISC_MODE2_CFP_IGNORE 0x00000080
+#define AR_PCU_MISC_MODE2_MGMT_QOS_M 0x0000ff00
+#define AR_PCU_MISC_MODE2_MGMT_QOS_S 8
+#define AR_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DUR 0x00010000
+#define AR_PCU_MISC_MODE2_ENABLE_AGGWEP 0x00020000
+#define AR_PCU_MISC_MODE2_HWWAR1 0x00100000
+#define AR_PCU_MISC_MODE2_HWWAR2 0x02000000
+
+/* Bits for AR_MAC_PCU_LOGIC_ANALYZER. */
+#define AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768 0x20000000
+
+/* Bits for AR_MAC_PCU_ASYNC_FIFO_REG3. */
+#define AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL 0x00000400
+#define AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET 0x80000000
+
+/* Bits for AR_PHY_ERR_[123]. */
+#define AR_PHY_ERR_COUNT_M 0x00ffffff
+#define AR_PHY_ERR_COUNT_S 0
+
+/* Bits for AR_TSFOOR_THRESHOLD. */
+#define AR_TSFOOR_THRESHOLD_VAL_M 0x0000ffff
+#define AR_TSFOOR_THRESHOLD_VAL_S 0
+
+/* Bit for AR_TXSIFS. */
+#define AR_TXSIFS_TIME_M 0x000000ff
+#define AR_TXSIFS_TIME_S 0
+#define AR_TXSIFS_TX_LATENCY_M 0x00000f00
+#define AR_TXSIFS_TX_LATENCY_S 8
+#define AR_TXSIFS_ACK_SHIFT_M 0x00007000
+#define AR_TXSIFS_ACK_SHIFT_S 12
+
+/* Bits for AR_TXOP_X. */
+#define AR_TXOP_X_VAL 0x000000ff
+
+/* Bits for AR_TIMER_MODE. */
+#define AR_TBTT_TIMER_EN 0x00000001
+#define AR_DBA_TIMER_EN 0x00000002
+#define AR_SWBA_TIMER_EN 0x00000004
+#define AR_HCF_TIMER_EN 0x00000008
+#define AR_TIM_TIMER_EN 0x00000010
+#define AR_DTIM_TIMER_EN 0x00000020
+#define AR_QUIET_TIMER_EN 0x00000040
+#define AR_NDP_TIMER_EN 0x00000080
+#define AR_TIMER_OVERFLOW_INDEX_M 0x00000700
+#define AR_TIMER_OVERFLOW_INDEX_S 8
+#define AR_TIMER_THRESH_M 0xfffff000
+#define AR_TIMER_THRESH_S 12
+
+/* Bits for AR_SLP32_MODE. */
+#define AR_SLP32_HALF_CLK_LATENCY_M 0x000fffff
+#define AR_SLP32_HALF_CLK_LATENCY_S 0
+#define AR_SLP32_ENA 0x00100000
+#define AR_SLP32_TSF_WRITE_STATUS 0x00200000
+
+/* Bits for AR_SLP32_WAKE. */
+#define AR_SLP32_WAKE_XTL_TIME_M 0x0000ffff
+#define AR_SLP32_WAKE_XTL_TIME_S 0
+
+/* Bits for AR_SLP_MIB_CTRL. */
+#define AR_SLP_MIB_CLEAR 0x00000001
+#define AR_SLP_MIB_PENDING 0x00000002
+
+/* Bits for AR_2040_MODE. */
+#define AR_2040_JOINED_RX_CLEAR 0x00000001
+
+/* Bits for AR_KEYTABLE_TYPE. */
+#define AR_KEYTABLE_TYPE_M 0x00000007
+#define AR_KEYTABLE_TYPE_S 0
+#define AR_KEYTABLE_TYPE_40 0
+#define AR_KEYTABLE_TYPE_104 1
+#define AR_KEYTABLE_TYPE_128 3
+#define AR_KEYTABLE_TYPE_TKIP 4
+#define AR_KEYTABLE_TYPE_AES 5
+#define AR_KEYTABLE_TYPE_CCM 6
+#define AR_KEYTABLE_TYPE_CLR 7
+#define AR_KEYTABLE_ANT 0x00000008
+#define AR_KEYTABLE_VALID 0x00008000
+
+/*
+ * AR9271 specific registers.
+ */
+#define AR9271_RESET_POWER_DOWN_CONTROL 0x050044
+#define AR9271_FIRMWARE 0x501000
+#define AR9271_FIRMWARE_TEXT 0x903000
+#define AR7010_FIRMWARE_TEXT 0x906000
+
+/* Bits for AR9271_RESET_POWER_DOWN_CONTROL. */
+#define AR9271_RADIO_RF_RST 0x00000020
+#define AR9271_GATE_MAC_CTL 0x00004000
+
+
+#define AR_BASE_PHY_ACTIVE_DELAY 100
+
+#define AR_CLOCK_RATE_CCK 22
+#define AR_CLOCK_RATE_5GHZ_OFDM 40
+#define AR_CLOCK_RATE_FAST_5GHZ_OFDM 44
+#define AR_CLOCK_RATE_2GHZ_OFDM 44
+
+#define AR_PWR_DECREASE_FOR_2_CHAIN 6 /* 10 * log10(2) * 2 */
+#define AR_PWR_DECREASE_FOR_3_CHAIN 9 /* 10 * log10(3) * 2 */
+
+#define AR_SLEEP_SLOP 3 /* TUs */
+
+#define AR_MIN_BEACON_TIMEOUT_VAL 1
+#define AR_FUDGE 2
+#define AR_BEACON_DMA_DELAY 2
+#define AR_SWBA_DELAY 10
+/* Divides by 1024 (usecs to TU) without doing 64-bit arithmetic. */
+#define AR_TSF_TO_TU(hi, lo) ((hi) << 22 | (lo) >> 10)
+
+#define AR_KEY_CACHE_SIZE 128
+#define AR_RSVD_KEYTABLE_ENTRIES 4
+
+#define AR_CAL_SAMPLES 64 /* XXX AR9280? */
+#define AR_MAX_LOG_CAL 2 /* XXX AR9280? */
+
+/* Maximum number of chains supported by any chipset. */
+#define AR_MAX_CHAINS 3
+
+/* Default number of key cache entries. */
+#define AR_KEYTABLE_SIZE 128
+
+/* GPIO pins. */
+#define AR_GPIO_WLANACTIVE_PIN 5
+#define AR_GPIO_BTACTIVE_PIN 6
+#define AR_GPIO_BTPRIORITY_PIN 7
+
+#define AR_SREV_5416(sc) \
+ ((sc)->sc_mac_ver == AR_SREV_VERSION_5416_PCI || \
+ (sc)->sc_mac_ver == AR_SREV_VERSION_5416_PCIE)
+#define AR_SREV_5416_20_OR_LATER(sc) \
+ ((AR_SREV_5416(sc) && \
+ (sc)->sc_mac_rev >= AR_SREV_REVISION_5416_20) || \
+ (sc)->sc_mac_ver >= AR_SREV_VERSION_9100)
+#define AR_SREV_5416_22_OR_LATER(sc) \
+ ((AR_SREV_5416(sc) && \
+ (sc)->sc_mac_rev >= AR_SREV_REVISION_5416_22) || \
+ (sc)->sc_mac_ver >= AR_SREV_VERSION_9100)
+
+#define AR_SREV_9160(sc) \
+ ((sc)->sc_mac_ver == AR_SREV_VERSION_9160)
+#define AR_SREV_9160_10_OR_LATER(sc) \
+ ((sc)->sc_mac_ver >= AR_SREV_VERSION_9160)
+#define AR_SREV_9160_11(sc) \
+ (AR_SREV_9160(sc) && \
+ (sc)->sc_mac_rev == AR_SREV_REVISION_9160_11)
+
+#define AR_SREV_9280(sc) \
+ ((sc)->sc_mac_ver == AR_SREV_VERSION_9280)
+#define AR_SREV_9280_10_OR_LATER(sc) \
+ ((sc)->sc_mac_ver >= AR_SREV_VERSION_9280)
+#define AR_SREV_9280_10(sc) \
+ (AR_SREV_9280(sc) && \
+ (sc)->sc_mac_rev == AR_SREV_REVISION_9280_10)
+#define AR_SREV_9280_20(sc) \
+ (AR_SREV_9280(sc) && \
+ (sc)->sc_mac_rev >= AR_SREV_REVISION_9280_20)
+#define AR_SREV_9280_20_OR_LATER(sc) \
+ ((sc)->sc_mac_ver > AR_SREV_VERSION_9280 || \
+ (AR_SREV_9280(sc) && (sc)->sc_mac_rev >= AR_SREV_REVISION_9280_20))
+
+#define AR_SREV_9285(sc) \
+ ((sc)->sc_mac_ver == AR_SREV_VERSION_9285)
+#define AR_SREV_9285_10_OR_LATER(sc) \
+ ((sc)->sc_mac_ver >= AR_SREV_VERSION_9285)
+#define AR_SREV_9285_11(sc) \
+ (AR_SREV_9285(sc) && \
+ (sc)->sc_mac_rev == AR_SREV_REVISION_9285_11)
+#define AR_SREV_9285_11_OR_LATER(sc) \
+ ((sc)->sc_mac_ver > AR_SREV_VERSION_9285 || \
+ (AR_SREV_9285(sc) && (sc)->sc_mac_rev >= AR_SREV_REVISION_9285_11))
+#define AR_SREV_9285_12(sc) \
+ (AR_SREV_9285(sc) && \
+ ((sc)->sc_mac_rev == AR_SREV_REVISION_9285_12))
+#define AR_SREV_9285_12_OR_LATER(sc) \
+ ((sc)->sc_mac_ver > AR_SREV_VERSION_9285 || \
+ (AR_SREV_9285(sc) && (sc)->sc_mac_rev >= AR_SREV_REVISION_9285_12))
+
+#define AR_SREV_9271(sc) \
+ ((sc)->sc_mac_ver == AR_SREV_VERSION_9271)
+#define AR_SREV_9271_10(sc) \
+ (AR_SREV_9271(sc) && \
+ (sc)->sc_mac_rev == AR_SREV_REVISION_9271_10)
+
+#define AR_SREV_9287(sc) \
+ ((sc)->sc_mac_ver == AR_SREV_VERSION_9287)
+#define AR_SREV_9287_10_OR_LATER(sc) \
+ ((sc)->sc_mac_ver >= AR_SREV_VERSION_9287)
+#define AR_SREV_9287_10(sc) \
+ ((sc)->sc_mac_ver == AR_SREV_VERSION_9287 && \
+ (sc)->sc_mac_rev == AR_SREV_REVISION_9287_10)
+#define AR_SREV_9287_11(sc) \
+ ((sc)->sc_mac_ver == AR_SREV_VERSION_9287 && \
+ (sc)->sc_mac_rev == AR_SREV_REVISION_9287_11)
+#define AR_SREV_9287_11_OR_LATER(sc) \
+ ((sc)->sc_mac_ver > AR_SREV_VERSION_9287 || \
+ (AR_SREV_9287(sc) && (sc)->sc_mac_rev >= AR_SREV_REVISION_9287_11))
+#define AR_SREV_9287_12(sc) \
+ ((sc)->sc_mac_ver == AR_SREV_VERSION_9287 && \
+ (sc)->sc_mac_rev == AR_SREV_REVISION_9287_12)
+#define AR_SREV_9287_12_OR_LATER(sc) \
+ ((sc)->sc_mac_ver > AR_SREV_VERSION_9287 || \
+ (AR_SREV_9287(sc) && (sc)->sc_mac_rev >= AR_SREV_REVISION_9287_12))
+#define AR_SREV_9287_13_OR_LATER(sc) \
+ ((sc)->sc_mac_ver > AR_SREV_VERSION_9287 || \
+ (AR_SREV_9287(sc) && (sc)->sc_mac_rev >= AR_SREV_REVISION_9287_13))
+
+#define AR_SREV_9380(sc) \
+ ((sc)->sc_mac_ver == AR_SREV_VERSION_9380)
+#define AR_SREV_9380_10_OR_LATER(sc) \
+ ((sc)->sc_mac_ver >= AR_SREV_VERSION_9380)
+#define AR_SREV_9380_20(sc) \
+ (AR_SREV_9380(sc) && \
+ (sc)->sc_mac_rev == AR_SREV_REVISION_9380_20)
+#define AR_SREV_9380_20_OR_LATER(sc) \
+ ((sc)->sc_mac_ver > AR_SREV_VERSION_9380 || \
+ (AR_SREV_9380(sc) && (sc)->sc_mac_rev >= AR_SREV_REVISION_9380_20))
+
+#define AR_SREV_9485(sc) \
+ ((sc)->sc_mac_ver == AR_SREV_VERSION_9485)
+
+#define AR_SINGLE_CHIP(sc) AR_SREV_9280_10_OR_LATER(sc)
+
+#define AR_RADIO_SREV_MAJOR 0xf0
+#define AR_RAD5133_SREV_MAJOR 0xc0
+#define AR_RAD2133_SREV_MAJOR 0xd0
+#define AR_RAD5122_SREV_MAJOR 0xe0
+#define AR_RAD2122_SREV_MAJOR 0xf0
+
+#define AR_BCHAN_UNUSED 0xff
+#define AR_PD_GAINS_IN_MASK 4 /* NB: Max for all chips. */
+#define AR_MAX_RATE_POWER 63
+
+#define AR_HT40_POWER_INC_FOR_PDADC 2
+#define AR_PWR_TABLE_OFFSET_DB (-5)
+#define AR9280_TX_GAIN_TABLE_SIZE 22
+#define AR9003_TX_GAIN_TABLE_SIZE 32
+#define AR9003_PAPRD_MEM_TAB_SIZE 24
+
+#define AR_BASE_FREQ_2GHZ 2300
+#define AR_BASE_FREQ_5GHZ 4900
+
+#define AR_SD_NO_CTL 0xe0
+#define AR_NO_CTL 0xff
+#define AR_CTL_MODE_M 0x07
+#define AR_CTL_MODE_S 0
+#define AR_CTL_11A 0
+#define AR_CTL_11B 1
+#define AR_CTL_11G 2
+#define AR_CTL_2GHT20 5
+#define AR_CTL_5GHT20 6
+#define AR_CTL_2GHT40 7
+#define AR_CTL_5GHT40 8
+
+/*
+ * Macros to access registers.
+ */
+#define AR_READ(sc, reg) \
+ (sc)->sc_ops.read((sc), (reg))
+
+#define AR_WRITE(sc, reg, val) \
+ (sc)->sc_ops.write((sc), (reg), (val))
+
+#define AR_WRITE_BARRIER(sc) \
+ (sc)->sc_ops.write_barrier((sc))
+
+#define AR_SETBITS(sc, reg, mask) \
+ AR_WRITE(sc, reg, AR_READ(sc, reg) | (mask))
+
+#define AR_CLRBITS(sc, reg, mask) \
+ AR_WRITE(sc, reg, AR_READ(sc, reg) & ~(mask))
+
+/*
+ * Macros to access subfields in registers.
+ */
+/* Mask and Shift (getter). */
+#define MS(val, field) \
+ (((val) & field##_M) >> field##_S)
+
+/* Shift and Mask (setter). */
+#define SM(field, val) \
+ (((val) << field##_S) & field##_M)
+
+/* Rewrite. */
+#define RW(var, field, val) \
+ (((var) & ~field##_M) | SM(field, val))
+
+#endif /* _ATHNREG_H_ */
diff --git a/sys/dev/ic/athnvar.h b/sys/dev/ic/athnvar.h
new file mode 100644
index 00000000000..14ce334e8a6
--- /dev/null
+++ b/sys/dev/ic/athnvar.h
@@ -0,0 +1,674 @@
+/* $NetBSD: athnvar.h,v 1.1 2013/03/30 02:53:02 christos Exp $ */
+/* $OpenBSD: athnvar.h,v 1.33 2012/10/20 09:54:20 stsp Exp $ */
+
+/*-
+ * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr>
+ *
+ * Permission to use, copy, modify, and distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _ATHNVAR_H_
+#define _ATHNVAR_H_
+
+#ifdef _KERNEL_OPT
+#include "opt_athn.h"
+#endif
+
+#define PUBLIC
+
+#define IEEE80211_NO_HT /* XXX: porting artifact */
+
+#ifdef notyet
+#define ATHN_BT_COEXISTENCE 1
+#endif
+
+#define ATHN_SOFTC(sc) ((struct athn_softc *)(sc))
+#define ATHN_NODE(ni) ((struct athn_node *)(ni))
+
+#ifdef ATHN_DEBUG
+#define DBG_INIT __BIT(0)
+#define DBG_FN __BIT(1)
+#define DBG_TX __BIT(2)
+#define DBG_RX __BIT(3)
+#define DBG_STM __BIT(4)
+#define DBG_RF __BIT(5)
+#define DBG_NODES __BIT(6)
+#define DBG_INTR __BIT(7)
+#define DBG_ALL 0xffffffffU
+#define DPRINTFN(n, s, ...) do { \
+ if (athn_debug & (n)) { \
+ printf("%s: %s: ", \
+ device_xname(ATHN_SOFTC(s)->sc_dev), __func__); \
+ printf(__VA_ARGS__); \
+ } \
+} while (0)
+extern int athn_debug;
+#else /* ATHN_DEBUG */
+#define DPRINTFN(n, s, ...)
+#endif /* ATHN_DEBUG */
+
+#define LE_READ_4(p) ((p)[0] | (p)[1] << 8 | (p)[2] << 16 | (p)[3] << 24)
+#define LE_READ_2(p) ((p)[0] | (p)[1] << 8)
+
+#define ATHN_RXBUFSZ 3872
+#define ATHN_TXBUFSZ 4096
+
+#define ATHN_NRXBUFS 64
+#define ATHN_NTXBUFS 64 /* Shared between all Tx queues. */
+
+struct athn_rx_radiotap_header {
+ struct ieee80211_radiotap_header wr_ihdr;
+ uint64_t wr_tsft;
+ uint8_t wr_flags;
+ uint8_t wr_rate;
+ uint16_t wr_chan_freq;
+ uint16_t wr_chan_flags;
+ int8_t wr_dbm_antsignal;
+ uint8_t wr_antenna;
+} __packed;
+
+#define ATHN_RX_RADIOTAP_PRESENT \
+ (1 << IEEE80211_RADIOTAP_TSFT | \
+ 1 << IEEE80211_RADIOTAP_FLAGS | \
+ 1 << IEEE80211_RADIOTAP_RATE | \
+ 1 << IEEE80211_RADIOTAP_CHANNEL | \
+ 1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL | \
+ 1 << IEEE80211_RADIOTAP_ANTENNA)
+
+struct athn_tx_radiotap_header {
+ struct ieee80211_radiotap_header wt_ihdr;
+ uint8_t wt_flags;
+ uint8_t wt_rate;
+ uint16_t wt_chan_freq;
+ uint16_t wt_chan_flags;
+} __packed;
+
+#define ATHN_TX_RADIOTAP_PRESENT \
+ (1 << IEEE80211_RADIOTAP_FLAGS | \
+ 1 << IEEE80211_RADIOTAP_RATE | \
+ 1 << IEEE80211_RADIOTAP_CHANNEL)
+
+struct athn_tx_buf {
+ SIMPLEQ_ENTRY(athn_tx_buf) bf_list;
+
+ void *bf_descs;
+ bus_dmamap_t bf_map;
+ bus_addr_t bf_daddr;
+
+ struct mbuf *bf_m;
+ struct ieee80211_node *bf_ni;
+ int bf_txflags;
+#define ATHN_TXFLAG_PAPRD (1 << 0)
+#define ATHN_TXFLAG_CAB (1 << 1)
+};
+
+struct athn_txq {
+ SIMPLEQ_HEAD(, athn_tx_buf) head;
+ void *lastds;
+ struct athn_tx_buf *wait;
+ int queued;
+};
+
+struct athn_rx_buf {
+ SIMPLEQ_ENTRY(athn_rx_buf) bf_list;
+
+ void *bf_desc;
+ bus_dmamap_t bf_map;
+
+ struct mbuf *bf_m;
+ bus_addr_t bf_daddr;
+};
+
+struct athn_rxq {
+ struct athn_rx_buf *bf;
+
+ void *descs;
+ void *lastds;
+ bus_dmamap_t map;
+ bus_dma_segment_t seg;
+ int count;
+
+ SIMPLEQ_HEAD(, athn_rx_buf) head;
+};
+
+/* Software rate indexes. */
+#define ATHN_RIDX_CCK1 0
+#define ATHN_RIDX_CCK2 1
+#define ATHN_RIDX_OFDM6 4
+#define ATHN_RIDX_MCS0 12
+#define ATHN_RIDX_MCS15 27
+#define ATHN_RIDX_MAX 27
+#define ATHN_IS_HT_RIDX(ridx) ((ridx) >= ATHN_RIDX_MCS0)
+
+static const struct athn_rate {
+ uint8_t rate; /* Rate in 500Kbps unit or MCS if 0x80. */
+ uint8_t hwrate; /* HW representation. */
+ uint8_t rspridx; /* Control Response Frame rate index. */
+ enum ieee80211_phytype phy;
+} athn_rates[] = {
+ { 2, 0x1b, 0, IEEE80211_T_DS },
+ { 4, 0x1a, 1, IEEE80211_T_DS },
+ { 11, 0x19, 1, IEEE80211_T_DS },
+ { 22, 0x18, 1, IEEE80211_T_DS },
+ { 12, 0x0b, 4, IEEE80211_T_OFDM },
+ { 18, 0x0f, 4, IEEE80211_T_OFDM },
+ { 24, 0x0a, 6, IEEE80211_T_OFDM },
+ { 36, 0x0e, 6, IEEE80211_T_OFDM },
+ { 48, 0x09, 8, IEEE80211_T_OFDM },
+ { 72, 0x0d, 8, IEEE80211_T_OFDM },
+ { 96, 0x08, 8, IEEE80211_T_OFDM },
+ { 108, 0x0c, 8, IEEE80211_T_OFDM },
+ { 0x80, 0x80, 8, IEEE80211_T_OFDM },
+ { 0x81, 0x81, 8, IEEE80211_T_OFDM },
+ { 0x82, 0x82, 8, IEEE80211_T_OFDM },
+ { 0x83, 0x83, 8, IEEE80211_T_OFDM },
+ { 0x84, 0x84, 8, IEEE80211_T_OFDM },
+ { 0x85, 0x85, 8, IEEE80211_T_OFDM },
+ { 0x86, 0x86, 8, IEEE80211_T_OFDM },
+ { 0x87, 0x87, 8, IEEE80211_T_OFDM },
+ { 0x88, 0x88, 8, IEEE80211_T_OFDM },
+ { 0x89, 0x89, 8, IEEE80211_T_OFDM },
+ { 0x8a, 0x8a, 8, IEEE80211_T_OFDM },
+ { 0x8b, 0x8b, 8, IEEE80211_T_OFDM },
+ { 0x8c, 0x8c, 8, IEEE80211_T_OFDM },
+ { 0x8d, 0x8d, 8, IEEE80211_T_OFDM },
+ { 0x8e, 0x8e, 8, IEEE80211_T_OFDM },
+ { 0x8f, 0x8f, 8, IEEE80211_T_OFDM }
+};
+
+struct athn_series {
+ uint16_t dur;
+ uint8_t hwrate;
+};
+
+struct athn_pier {
+ uint8_t fbin;
+ const uint8_t *pwr[AR_PD_GAINS_IN_MASK];
+ const uint8_t *vpd[AR_PD_GAINS_IN_MASK];
+};
+
+/*
+ * Structures used to store initialization values.
+ */
+struct athn_ini {
+ int nregs;
+ const uint16_t *regs;
+ const uint32_t *vals_5g20;
+#ifndef IEEE80211_NO_HT
+ const uint32_t *vals_5g40;
+ const uint32_t *vals_2g40;
+#endif
+ const uint32_t *vals_2g20;
+ int ncmregs;
+ const uint16_t *cmregs;
+ const uint32_t *cmvals;
+ int nfastregs;
+ const uint16_t *fastregs;
+ const uint32_t *fastvals_5g20;
+#ifndef IEEE80211_NO_HT
+ const uint32_t *fastvals_5g40;
+#endif
+};
+
+struct athn_gain {
+ int nregs;
+ const uint16_t *regs;
+ const uint32_t *vals_5g;
+ const uint32_t *vals_2g;
+};
+
+struct athn_addac {
+ int nvals;
+ const uint32_t *vals;
+};
+
+struct athn_serdes {
+ int nvals;
+ const uint32_t *regs;
+ const uint32_t *vals;
+};
+
+/* Rx queue software indexes. */
+#define ATHN_QID_LP 0
+#define ATHN_QID_HP 0
+
+/* Tx queue software indexes. */
+#define ATHN_QID_AC_BE 0
+#define ATHN_QID_PSPOLL 1
+#define ATHN_QID_AC_BK 2
+#define ATHN_QID_AC_VI 3
+#define ATHN_QID_AC_VO 4
+#define ATHN_QID_UAPSD 5
+#define ATHN_QID_CAB 6
+#define ATHN_QID_BEACON 7
+#define ATHN_QID_COUNT 8
+
+/* Map Access Category to Tx queue Id. */
+static const uint8_t athn_ac2qid[EDCA_NUM_AC] = {
+ ATHN_QID_AC_BE, /* EDCA_AC_BE */
+ ATHN_QID_AC_BK, /* EDCA_AC_BK */
+ ATHN_QID_AC_VI, /* EDCA_AC_VI */
+ ATHN_QID_AC_VO /* EDCA_AC_VO */
+};
+
+static const uint8_t athn_5ghz_chans[] = {
+ /* UNII 1. */
+ 36, 40, 44, 48,
+ /* UNII 2. */
+ 52, 56, 60, 64,
+ /* Middle band. */
+ 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140,
+ /* UNII 3. */
+ 149, 153, 157, 161, 165
+};
+
+/* Number of data bits per OFDM symbol for MCS[0-15]. */
+/* See tables 20-29, 20-30, 20-33, 20-34. */
+static const uint16_t ar_mcs_ndbps[][2] = {
+ /* 20MHz 40MHz */
+ { 26, 54 }, /* MCS0 */
+ { 52, 108 }, /* MCS1 */
+ { 78, 162 }, /* MCS2 */
+ { 104, 216 }, /* MCS3 */
+ { 156, 324 }, /* MCS4 */
+ { 208, 432 }, /* MCS5 */
+ { 234, 486 }, /* MCS6 */
+ { 260, 540 }, /* MCS7 */
+ { 26, 108 }, /* MCS8 */
+ { 52, 216 }, /* MCS9 */
+ { 78, 324 }, /* MCS10 */
+ { 104, 432 }, /* MCS11 */
+ { 156, 648 }, /* MCS12 */
+ { 208, 864 }, /* MCS13 */
+ { 234, 972 }, /* MCS14 */
+ { 260, 1080 } /* MCS15 */
+};
+
+#define ATHN_POWER_OFDM6 0
+#define ATHN_POWER_OFDM9 1
+#define ATHN_POWER_OFDM12 2
+#define ATHN_POWER_OFDM18 3
+#define ATHN_POWER_OFDM24 4
+#define ATHN_POWER_OFDM36 5
+#define ATHN_POWER_OFDM48 6
+#define ATHN_POWER_OFDM54 7
+#define ATHN_POWER_CCK1_LP 8
+#define ATHN_POWER_CCK2_LP 9
+#define ATHN_POWER_CCK2_SP 10
+#define ATHN_POWER_CCK55_LP 11
+#define ATHN_POWER_CCK55_SP 12
+#define ATHN_POWER_CCK11_LP 13
+#define ATHN_POWER_CCK11_SP 14
+#define ATHN_POWER_XR 15
+#define ATHN_POWER_HT20(mcs) (16 + (mcs))
+#define ATHN_POWER_HT40(mcs) (40 + (mcs))
+#define ATHN_POWER_CCK_DUP 64
+#define ATHN_POWER_OFDM_DUP 65
+#define ATHN_POWER_CCK_EXT 66
+#define ATHN_POWER_OFDM_EXT 67
+#define ATHN_POWER_COUNT 68
+
+struct athn_node {
+ struct ieee80211_node ni;
+ struct ieee80211_amrr_node amn;
+ uint8_t ridx[IEEE80211_RATE_MAXSIZE];
+ uint8_t fallback[IEEE80211_RATE_MAXSIZE];
+ uint8_t sta_index;
+};
+
+/*
+ * Adaptive noise immunity state.
+ */
+#define ATHN_ANI_PERIOD 100
+#define ATHN_ANI_RSSI_THR_HIGH 40
+#define ATHN_ANI_RSSI_THR_LOW 7
+struct athn_ani {
+ uint8_t noise_immunity_level;
+ uint8_t spur_immunity_level;
+ uint8_t firstep_level;
+ uint8_t ofdm_weak_signal;
+ uint8_t cck_weak_signal;
+
+ uint32_t listen_time;
+
+ uint32_t ofdm_trig_high;
+ uint32_t ofdm_trig_low;
+
+ int32_t cck_trig_high;
+ int32_t cck_trig_low;
+
+ uint32_t ofdm_phy_err_base;
+ uint32_t cck_phy_err_base;
+ uint32_t ofdm_phy_err_count;
+ uint32_t cck_phy_err_count;
+
+ uint32_t cyccnt;
+ uint32_t txfcnt;
+ uint32_t rxfcnt;
+};
+
+struct athn_iq_cal {
+ uint32_t pwr_meas_i;
+ uint32_t pwr_meas_q;
+ int32_t iq_corr_meas;
+};
+
+struct athn_adc_cal {
+ uint32_t pwr_meas_odd_i;
+ uint32_t pwr_meas_even_i;
+ uint32_t pwr_meas_odd_q;
+ uint32_t pwr_meas_even_q;
+};
+
+struct athn_calib {
+ int nsamples;
+ struct athn_iq_cal iq[AR_MAX_CHAINS];
+ struct athn_adc_cal adc_gain[AR_MAX_CHAINS];
+ struct athn_adc_cal adc_dc_offset[AR_MAX_CHAINS];
+};
+
+#define ATHN_NF_CAL_HIST_MAX 5
+
+struct athn_softc;
+
+struct athn_ops {
+ /* Bus callbacks. */
+ uint32_t (*read)(struct athn_softc *, uint32_t);
+ void (*write)(struct athn_softc *, uint32_t, uint32_t);
+ void (*write_barrier)(struct athn_softc *);
+
+ void (*setup)(struct athn_softc *);
+ void (*set_txpower)(struct athn_softc *, struct ieee80211_channel *,
+ struct ieee80211_channel *);
+ void (*spur_mitigate)(struct athn_softc *,
+ struct ieee80211_channel *, struct ieee80211_channel *);
+ const struct ar_spur_chan *
+ (*get_spur_chans)(struct athn_softc *, int);
+ void (*init_from_rom)(struct athn_softc *,
+ struct ieee80211_channel *, struct ieee80211_channel *);
+ int (*set_synth)(struct athn_softc *, struct ieee80211_channel *,
+ struct ieee80211_channel *);
+ int (*read_rom_data)(struct athn_softc *, uint32_t, void *, int);
+ const uint8_t *
+ (*get_rom_template)(struct athn_softc *, uint8_t);
+ void (*swap_rom)(struct athn_softc *);
+ void (*olpc_init)(struct athn_softc *);
+ void (*olpc_temp_compensation)(struct athn_softc *);
+
+ /* GPIO callbacks. */
+ int (*gpio_read)(struct athn_softc *, int);
+ void (*gpio_write)(struct athn_softc *, int, int);
+ void (*gpio_config_input)(struct athn_softc *, int);
+ void (*gpio_config_output)(struct athn_softc *, int, int);
+ void (*rfsilent_init)(struct athn_softc *);
+
+ /* DMA callbacks. */
+ int (*dma_alloc)(struct athn_softc *);
+ void (*dma_free)(struct athn_softc *);
+ void (*rx_enable)(struct athn_softc *);
+ int (*intr)(struct athn_softc *);
+ int (*tx)(struct athn_softc *, struct mbuf *,
+ struct ieee80211_node *, int);
+
+ /* PHY callbacks. */
+ void (*set_rf_mode)(struct athn_softc *,
+ struct ieee80211_channel *);
+ int (*rf_bus_request)(struct athn_softc *);
+ void (*rf_bus_release)(struct athn_softc *);
+ void (*set_phy)(struct athn_softc *, struct ieee80211_channel *,
+ struct ieee80211_channel *);
+ void (*set_delta_slope)(struct athn_softc *,
+ struct ieee80211_channel *, struct ieee80211_channel *);
+ void (*enable_antenna_diversity)(struct athn_softc *);
+ void (*init_baseband)(struct athn_softc *);
+ void (*disable_phy)(struct athn_softc *);
+ void (*set_rxchains)(struct athn_softc *);
+ void (*noisefloor_calib)(struct athn_softc *);
+ void (*do_calib)(struct athn_softc *);
+ void (*next_calib)(struct athn_softc *);
+ void (*hw_init)(struct athn_softc *, struct ieee80211_channel *,
+ struct ieee80211_channel *);
+ void (*get_paprd_masks)(struct athn_softc *sc,
+ struct ieee80211_channel *, uint32_t *, uint32_t *);
+
+ /* ANI callbacks. */
+ void (*set_noise_immunity_level)(struct athn_softc *, int);
+ void (*enable_ofdm_weak_signal)(struct athn_softc *);
+ void (*disable_ofdm_weak_signal)(struct athn_softc *);
+ void (*set_cck_weak_signal)(struct athn_softc *, int);
+ void (*set_firstep_level)(struct athn_softc *, int);
+ void (*set_spur_immunity_level)(struct athn_softc *, int);
+};
+
+struct athn_softc {
+ device_t sc_dev;
+ device_suspensor_t sc_suspensor;
+ pmf_qual_t sc_qual;
+ struct ieee80211com sc_ic;
+ struct ifnet sc_if;
+
+#if 0
+ int (*sc_enable)(struct athn_softc *);
+ void (*sc_disable)(struct athn_softc *);
+ void (*sc_power)(struct athn_softc *, int);
+#endif
+ void (*sc_disable_aspm)(struct athn_softc *);
+ void (*sc_enable_extsynch)(
+ struct athn_softc *);
+
+ int (*sc_newstate)(struct ieee80211com *,
+ enum ieee80211_state, int);
+
+ bus_dma_tag_t sc_dmat;
+
+ callout_t sc_scan_to;
+ callout_t sc_calib_to;
+ struct ieee80211_amrr sc_amrr;
+
+ u_int sc_flags;
+#define ATHN_FLAG_PCIE (1 << 0)
+#define ATHN_FLAG_USB (1 << 1)
+#define ATHN_FLAG_OLPC (1 << 2)
+#define ATHN_FLAG_PAPRD (1 << 3)
+#define ATHN_FLAG_FAST_PLL_CLOCK (1 << 4)
+#define ATHN_FLAG_RFSILENT (1 << 5)
+#define ATHN_FLAG_RFSILENT_REVERSED (1 << 6)
+#define ATHN_FLAG_BTCOEX2WIRE (1 << 7)
+#define ATHN_FLAG_BTCOEX3WIRE (1 << 8)
+/* Shortcut. */
+#define ATHN_FLAG_BTCOEX (ATHN_FLAG_BTCOEX2WIRE | ATHN_FLAG_BTCOEX3WIRE)
+#define ATHN_FLAG_11A (1 << 9)
+#define ATHN_FLAG_11G (1 << 10)
+#define ATHN_FLAG_11N (1 << 11)
+#define ATHN_FLAG_AN_TOP2_FIXUP (1 << 12)
+#define ATHN_FLAG_NON_ENTERPRISE (1 << 13)
+#define ATHN_FLAG_3TREDUCE_CHAIN (1 << 14)
+
+ uint8_t sc_ngpiopins;
+ int sc_led_pin;
+ int sc_rfsilent_pin;
+ int sc_led_state;
+ uint32_t sc_isync;
+ uint32_t sc_imask;
+
+ uint16_t sc_mac_ver;
+ uint8_t sc_mac_rev;
+ uint8_t sc_rf_rev;
+ uint16_t sc_eep_rev;
+
+ uint8_t sc_txchainmask;
+ uint8_t sc_rxchainmask;
+ uint8_t sc_ntxchains;
+ uint8_t sc_nrxchains;
+
+ uint8_t sc_sup_calib_mask;
+ uint8_t sc_cur_calib_mask;
+#define ATHN_CAL_IQ (1 << 0)
+#define ATHN_CAL_ADC_GAIN (1 << 1)
+#define ATHN_CAL_ADC_DC (1 << 2)
+#define ATHN_CAL_TEMP (1 << 3)
+
+ struct ieee80211_channel *sc_curchan;
+ struct ieee80211_channel *sc_curchanext;
+
+ /* Open Loop Power Control. */
+ int8_t sc_tx_gain_tbl[AR9280_TX_GAIN_TABLE_SIZE];
+ int8_t sc_pdadc;
+ int8_t sc_tcomp;
+ int sc_olpc_ticks;
+
+ /* PA predistortion. */
+ uint16_t sc_gain1[AR_MAX_CHAINS];
+ uint32_t sc_txgain[AR9003_TX_GAIN_TABLE_SIZE];
+ int16_t sc_pa_in[AR_MAX_CHAINS]
+ [AR9003_PAPRD_MEM_TAB_SIZE];
+ int16_t sc_angle[AR_MAX_CHAINS]
+ [AR9003_PAPRD_MEM_TAB_SIZE];
+ int32_t sc_trainpow;
+ uint8_t sc_paprd_curchain;
+
+ uint32_t sc_rwbuf[64];
+
+ size_t sc_kc_entries;
+
+ void *sc_eep;
+ const void *sc_eep_def;
+ uint32_t sc_eep_base;
+ uint32_t sc_eep_size;
+
+ struct athn_rxq sc_rxq[2];
+ struct athn_txq sc_txq[31];
+
+ void *sc_descs;
+ bus_dmamap_t sc_map;
+ bus_dma_segment_t sc_seg;
+ SIMPLEQ_HEAD(, athn_tx_buf) sc_txbufs;
+ struct athn_tx_buf *sc_bcnbuf;
+ struct athn_tx_buf sc_txpool[ATHN_NTXBUFS];
+
+ bus_dmamap_t sc_txsmap;
+ bus_dma_segment_t sc_txsseg;
+ void *sc_txsring;
+ int sc_txscur;
+
+ int sc_if_flags;
+ int sc_tx_timer;
+
+ const struct athn_ini *sc_ini;
+ const struct athn_gain *sc_rx_gain;
+ const struct athn_gain *sc_tx_gain;
+ const struct athn_addac *sc_addac;
+ const struct athn_serdes *sc_serdes;
+ uint32_t sc_workaround;
+ uint32_t sc_obs_off;
+ uint32_t sc_gpio_input_en_off;
+
+ struct athn_ops sc_ops;
+
+ int sc_fixed_ridx;
+
+ int16_t sc_cca_min_2g;
+ int16_t sc_cca_max_2g;
+ int16_t sc_cca_min_5g;
+ int16_t sc_cca_max_5g;
+ int16_t sc_def_nf;
+ struct {
+ int16_t nf[AR_MAX_CHAINS];
+ int16_t nf_ext[AR_MAX_CHAINS];
+ } sc_nf_hist[ATHN_NF_CAL_HIST_MAX];
+ int sc_nf_hist_cur;
+ int16_t sc_nf_priv[AR_MAX_CHAINS];
+ int16_t sc_nf_ext_priv[AR_MAX_CHAINS];
+ int sc_pa_calib_ticks;
+
+ struct athn_calib sc_calib;
+ struct athn_ani sc_ani;
+
+ struct bpf_if * sc_drvbpf;
+
+ union {
+ struct athn_rx_radiotap_header th;
+ uint8_t pad[IEEE80211_RADIOTAP_HDRLEN];
+ } sc_rxtapu;
+#define sc_rxtap sc_rxtapu.th
+ int sc_rxtap_len;
+
+ union {
+ struct athn_tx_radiotap_header th;
+ uint8_t pad[IEEE80211_RADIOTAP_HDRLEN];
+ } sc_txtapu;
+#define sc_txtap sc_txtapu.th
+ int sc_txtap_len;
+
+ /*
+ * Attach overrides. Set before calling athn_attach().
+ */
+ int sc_max_aid;
+ int (*sc_media_change)(struct ifnet *);
+};
+
+int athn_attach(struct athn_softc *);
+void athn_detach(struct athn_softc *);
+void athn_suspend(struct athn_softc *);
+int athn_resume(struct athn_softc *);
+int athn_intr(void *);
+
+/* used by if_athn_usb.c */
+void athn_btcoex_init(struct athn_softc *);
+int athn_hw_reset(struct athn_softc *, struct ieee80211_channel *,
+ struct ieee80211_channel *, int);
+void athn_init_pll(struct athn_softc *, const struct ieee80211_channel *);
+void athn_led_init(struct athn_softc *);
+int athn_reset(struct athn_softc *, int);
+void athn_reset_key(struct athn_softc *, int);
+void athn_rx_start(struct athn_softc *);
+void athn_set_bss(struct athn_softc *, struct ieee80211_node *);
+int athn_set_chan(struct athn_softc *, struct ieee80211_channel *,
+ struct ieee80211_channel *);
+void athn_set_hostap_timers(struct athn_softc *);
+void athn_set_led(struct athn_softc *, int);
+void athn_set_opmode(struct athn_softc *);
+int athn_set_power_awake(struct athn_softc *);
+void athn_set_power_sleep(struct athn_softc *);
+void athn_set_rxfilter(struct athn_softc *, uint32_t);
+void athn_set_sta_timers(struct athn_softc *);
+void athn_updateslot(struct ifnet *);
+
+#ifdef notyet_edca
+void athn_updateedca(struct ieee80211com *);
+#endif
+#ifdef notyet
+void athn_delete_key(struct ieee80211com *, struct ieee80211_node *,
+ struct ieee80211_key *);
+int athn_set_key(struct ieee80211com *, struct ieee80211_node *,
+ struct ieee80211_key *);
+#endif /* notyet */
+
+/* used by ar9285.c */
+uint8_t athn_chan2fbin(struct ieee80211_channel *);
+void athn_get_pier_ival(uint8_t, const uint8_t *, int, int *, int *);
+
+/* used by arn5008.c and arn9003.c */
+void athn_config_nonpcie(struct athn_softc *);
+void athn_config_pcie(struct athn_softc *);
+void athn_get_delta_slope(uint32_t, uint32_t *, uint32_t *);
+void athn_inc_tx_trigger_level(struct athn_softc *);
+void athn_stop(struct ifnet *, int);
+void athn_stop_tx_dma(struct athn_softc *, int);
+int athn_tx_pending(struct athn_softc *, int);
+int athn_txtime(struct athn_softc *, int, int, u_int);
+
+/* used by arn5008.c, arn9003.c, arn9287.c, and arn9380.c */
+int athn_interpolate(int, int, int, int, int);
+
+#endif /* _ATHNVAR_H_ */
diff --git a/sys/dev/pci/if_athn_pci.c b/sys/dev/pci/if_athn_pci.c
new file mode 100644
index 00000000000..6d2fb345e57
--- /dev/null
+++ b/sys/dev/pci/if_athn_pci.c
@@ -0,0 +1,339 @@
+/* $NetBSD: if_athn_pci.c,v 1.1 2013/03/30 02:53:02 christos Exp $ */
+/* $OpenBSD: if_athn_pci.c,v 1.11 2011/01/08 10:02:32 damien Exp $ */
+
+/*-
+ * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr>
+ *
+ * Permission to use, copy, modify, and distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+/*
+ * PCI front-end for Atheros 802.11a/g/n chipsets.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: if_athn_pci.c,v 1.1 2013/03/30 02:53:02 christos Exp $");
+
+#include "opt_inet.h"
+
+#include <sys/param.h>
+#include <sys/sockio.h>
+#include <sys/mbuf.h>
+#include <sys/kernel.h>
+#include <sys/socket.h>
+#include <sys/systm.h>
+#include <sys/malloc.h>
+#include <sys/callout.h>
+#include <sys/device.h>
+
+#include <sys/bus.h>
+#include <sys/intr.h>
+
+#include <net/if.h>
+#include <net/if_media.h>
+
+#include <net80211/ieee80211_var.h>
+#include <net80211/ieee80211_amrr.h>
+#include <net80211/ieee80211_radiotap.h>
+
+#include <dev/ic/athnreg.h>
+#include <dev/ic/athnvar.h>
+
+#include <dev/pci/pcireg.h>
+#include <dev/pci/pcivar.h>
+#include <dev/pci/pcidevs.h>
+
+#define PCI_SUBSYSID_ATHEROS_COEX2WIRE 0x309b
+#define PCI_SUBSYSID_ATHEROS_COEX3WIRE_SA 0x30aa
+#define PCI_SUBSYSID_ATHEROS_COEX3WIRE_DA 0x30ab
+
+#define ATHN_PCI_MMBA PCI_BAR(0) /* memory mapped base */
+
+struct athn_pci_softc {
+ struct athn_softc psc_sc;
+
+ /* PCI specific goo. */
+ pci_chipset_tag_t psc_pc;
+ pcitag_t psc_tag;
+ pci_intr_handle_t psc_pih;
+ void *psc_ih;
+ bus_space_tag_t psc_iot;
+ bus_space_handle_t psc_ioh;
+ bus_size_t psc_mapsz;
+ int psc_cap_off;
+};
+
+#define Static static
+
+Static int athn_pci_match(device_t, cfdata_t, void *);
+Static void athn_pci_attach(device_t, device_t, void *);
+Static int athn_pci_detach(device_t, int);
+Static int athn_pci_activate(device_t, enum devact);
+
+CFATTACH_DECL_NEW(athn_pci, sizeof(struct athn_pci_softc), athn_pci_match,
+ athn_pci_attach, athn_pci_detach, athn_pci_activate);
+
+Static bool athn_pci_resume(device_t, const pmf_qual_t *);
+Static bool athn_pci_suspend(device_t, const pmf_qual_t *);
+Static uint32_t athn_pci_read(struct athn_softc *, uint32_t);
+Static void athn_pci_write(struct athn_softc *, uint32_t, uint32_t);
+Static void athn_pci_write_barrier(struct athn_softc *);
+Static void athn_pci_disable_aspm(struct athn_softc *);
+
+Static int
+athn_pci_match(device_t parent, cfdata_t match, void *aux)
+{
+ static const struct {
+ pci_vendor_id_t apd_vendor;
+ pci_product_id_t apd_product;
+ } athn_pci_devices[] = {
+ { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5416 },
+ { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5418 },
+ { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR9160 },
+ { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR9280 },
+ { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR9281 },
+ { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR9285 },
+ { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR2427 },
+ { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR9227 },
+ { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR9287 },
+ { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR9300 }
+ };
+ struct pci_attach_args *pa = aux;
+ size_t i;
+
+ for (i = 0; i < __arraycount(athn_pci_devices); i++) {
+ if (PCI_VENDOR(pa->pa_id) == athn_pci_devices[i].apd_vendor &&
+ PCI_VENDOR(pa->pa_id) == athn_pci_devices[i].apd_product)
+ return 1;
+ }
+ return 0;
+}
+
+Static void
+athn_pci_attach(device_t parent, device_t self, void *aux)
+{
+ struct athn_pci_softc *psc = device_private(self);
+ struct athn_softc *sc = &psc->psc_sc;
+ struct ieee80211com *ic = &sc->sc_ic;
+ struct pci_attach_args *pa = aux;
+ const char *intrstr;
+ pcireg_t memtype, reg;
+ pci_product_id_t subsysid;
+ int error;
+
+ sc->sc_dmat = pa->pa_dmat;
+ psc->psc_pc = pa->pa_pc;
+ psc->psc_tag = pa->pa_tag;
+
+ sc->sc_ops.read = athn_pci_read;
+ sc->sc_ops.write = athn_pci_write;
+ sc->sc_ops.write_barrier = athn_pci_write_barrier;
+
+ /*
+ * Get the offset of the PCI Express Capability Structure in PCI
+ * Configuration Space (Linux hardcodes it as 0x60.)
+ */
+ error = pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIEXPRESS,
+ &psc->psc_cap_off, NULL);
+ if (error != 0) { /* Found. */
+ sc->sc_disable_aspm = athn_pci_disable_aspm;
+ sc->sc_flags |= ATHN_FLAG_PCIE;
+ }
+ /*
+ * Noone knows why this shit is necessary but there are claims that
+ * not doing this may cause very frequent PCI FATAL interrupts from
+ * the card: http://bugzilla.kernel.org/show_bug.cgi?id=13483
+ */
+ reg = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x40);
+ if (reg & 0xff00)
+ pci_conf_write(pa->pa_pc, pa->pa_tag, 0x40, reg & ~0xff00);
+
+ /* Change latency timer; default value yields poor results. */
+ reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG);
+ reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT);
+ reg |= 168 << PCI_LATTIMER_SHIFT;
+ pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, reg);
+
+ /* Determine if bluetooth is also supported (combo chip.) */
+ reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG);
+ subsysid = PCI_PRODUCT(reg);
+ if (subsysid == PCI_SUBSYSID_ATHEROS_COEX3WIRE_SA ||
+ subsysid == PCI_SUBSYSID_ATHEROS_COEX3WIRE_DA)
+ sc->sc_flags |= ATHN_FLAG_BTCOEX3WIRE;
+ else if (subsysid == PCI_SUBSYSID_ATHEROS_COEX2WIRE)
+ sc->sc_flags |= ATHN_FLAG_BTCOEX2WIRE;
+
+ /*
+ * Setup memory-mapping of PCI registers.
+ */
+ memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, ATHN_PCI_MMBA);
+ if (memtype != PCI_MAPREG_TYPE_MEM &&
+ memtype != PCI_MAPREG_MEM_TYPE_64BIT) {
+ aprint_error_dev(self, "bad pci register type %d\n",
+ (int)memtype);
+ goto fail;
+ }
+ error = pci_mapreg_map(pa, PCI_MAPREG_START, memtype, 0, &psc->psc_iot,
+ &psc->psc_ioh, NULL, &psc->psc_mapsz);
+ if (error != 0) {
+ aprint_error_dev(self, "cannot map register space\n");
+ goto fail;
+ }
+
+ /*
+ * Arrange interrupt line.
+ */
+ if (pci_intr_map(pa, &psc->psc_pih) != 0) {
+ aprint_error_dev(self, "couldn't map interrupt\n");
+ goto fail1;
+ }
+
+ intrstr = pci_intr_string(psc->psc_pc, psc->psc_pih);
+ psc->psc_ih = pci_intr_establish(psc->psc_pc, psc->psc_pih, IPL_NET,
+ athn_intr, sc);
+ if (psc->psc_ih == NULL) {
+ aprint_error_dev(self, "couldn't map interrupt\n");
+ goto fail1;
+ }
+ aprint_verbose_dev(self, "interrupting at %s\n", intrstr);
+
+ if (athn_attach(sc) != 0)
+ goto fail2;
+
+ if (pmf_device_register(self, athn_pci_suspend, athn_pci_resume)) {
+ pmf_class_network_register(self, &sc->sc_if);
+ pmf_device_suspend(self, &sc->sc_qual);
+ }
+ else
+ aprint_error_dev(self, "couldn't establish power handler\n");
+
+ ieee80211_announce(ic);
+ return;
+
+ fail2:
+ pci_intr_disestablish(psc->psc_pc, psc->psc_ih);
+ psc->psc_ih = NULL;
+ fail1:
+ bus_space_unmap(psc->psc_iot, psc->psc_ioh, psc->psc_mapsz);
+ psc->psc_mapsz = 0;
+ fail:
+ return;
+}
+
+Static int
+athn_pci_detach(device_t self, int flags)
+{
+ struct athn_pci_softc *psc = device_private(self);
+ struct athn_softc *sc = &psc->psc_sc;
+
+ if (psc->psc_ih != NULL) {
+ athn_detach(sc);
+ pci_intr_disestablish(psc->psc_pc, psc->psc_ih);
+ psc->psc_ih = NULL;
+ }
+ if (psc->psc_mapsz > 0) {
+ bus_space_unmap(psc->psc_iot, psc->psc_ioh, psc->psc_mapsz);
+ psc->psc_mapsz = 0;
+ }
+ return 0;
+}
+
+Static int
+athn_pci_activate(device_t self, enum devact act)
+{
+ struct athn_pci_softc *psc = device_private(self);
+ struct athn_softc *sc = &psc->psc_sc;
+
+ switch (act) {
+ case DVACT_DEACTIVATE:
+ if_deactivate(sc->sc_ic.ic_ifp);
+ break;
+ }
+ return 0;
+}
+
+Static bool
+athn_pci_suspend(device_t self, const pmf_qual_t *qual)
+{
+ struct athn_pci_softc *psc = device_private(self);
+ struct athn_softc *sc = &psc->psc_sc;
+
+ athn_suspend(sc);
+ if (psc->psc_ih != NULL) {
+ pci_intr_disestablish(psc->psc_pc, psc->psc_ih);
+ psc->psc_ih = NULL;
+ }
+ return true;
+}
+
+Static bool
+athn_pci_resume(device_t self, const pmf_qual_t *qual)
+{
+ struct athn_pci_softc *psc = device_private(self);
+ struct athn_softc *sc = &psc->psc_sc;
+ pcireg_t reg;
+
+ /*
+ * XXX: see comment in athn_attach().
+ */
+ reg = pci_conf_read(psc->psc_pc, psc->psc_tag, 0x40);
+ if (reg & 0xff00)
+ pci_conf_write(psc->psc_pc, psc->psc_tag, 0x40, reg & ~0xff00);
+
+ psc->psc_ih = pci_intr_establish(psc->psc_pc, psc->psc_pih, IPL_NET,
+ athn_intr, sc);
+ if (psc->psc_ih == NULL) {
+ aprint_error_dev(self, "couldn't map interrupt\n");
+ return false;
+ }
+ return athn_resume(sc);
+}
+
+Static uint32_t
+athn_pci_read(struct athn_softc *sc, uint32_t addr)
+{
+ struct athn_pci_softc *psc = (struct athn_pci_softc *)sc;
+
+ return bus_space_read_4(psc->psc_iot, psc->psc_ioh, addr);
+}
+
+Static void
+athn_pci_write(struct athn_softc *sc, uint32_t addr, uint32_t val)
+{
+ struct athn_pci_softc *psc = (struct athn_pci_softc *)sc;
+
+ bus_space_write_4(psc->psc_iot, psc->psc_ioh, addr, val);
+}
+
+Static void
+athn_pci_write_barrier(struct athn_softc *sc)
+{
+ struct athn_pci_softc *psc = (struct athn_pci_softc *)sc;
+
+ bus_space_barrier(psc->psc_iot, psc->psc_ioh, 0, psc->psc_mapsz,
+ BUS_SPACE_BARRIER_WRITE);
+}
+
+Static void
+athn_pci_disable_aspm(struct athn_softc *sc)
+{
+ struct athn_pci_softc *psc = (struct athn_pci_softc *)sc;
+ pcireg_t reg;
+
+ /* Disable PCIe Active State Power Management (ASPM). */
+ reg = pci_conf_read(psc->psc_pc, psc->psc_tag,
+ psc->psc_cap_off + PCI_PCIE_LCSR);
+ reg &= ~(PCI_PCIE_LCSR_ASPM_L0S | PCI_PCIE_LCSR_ASPM_L1);
+ pci_conf_write(psc->psc_pc, psc->psc_tag,
+ psc->psc_cap_off + PCI_PCIE_LCSR, reg);
+}
diff --git a/sys/dev/usb/if_athn_usb.c b/sys/dev/usb/if_athn_usb.c
new file mode 100644
index 00000000000..a499d6062b3
--- /dev/null
+++ b/sys/dev/usb/if_athn_usb.c
@@ -0,0 +1,2815 @@
+/* $NetBSD: if_athn_usb.c,v 1.1 2013/03/30 02:53:02 christos Exp $ */
+/* $OpenBSD: if_athn_usb.c,v 1.12 2013/01/14 09:50:31 jsing Exp $ */
+
+/*-
+ * Copyright (c) 2011 Damien Bergamini <damien.bergamini@free.fr>
+ *
+ * Permission to use, copy, modify, and distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+/*
+ * USB front-end for Atheros AR9271 and AR7010 chipsets.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: if_athn_usb.c,v 1.1 2013/03/30 02:53:02 christos Exp $");
+
+#ifdef _KERNEL_OPT
+#include "opt_inet.h"
+#endif
+
+#include <sys/param.h>
+#include <sys/callout.h>
+#include <sys/conf.h>
+#include <sys/device.h>
+#include <sys/kernel.h>
+#include <sys/mbuf.h>
+#include <sys/module.h>
+#include <sys/proc.h>
+#include <sys/socket.h>
+#include <sys/sockio.h>
+#include <sys/systm.h>
+
+#include <sys/bus.h>
+#include <sys/endian.h>
+#include <sys/intr.h>
+
+#include <net/bpf.h>
+#include <net/if.h>
+#include <net/if_arp.h>
+#include <net/if_dl.h>
+#include <net/if_ether.h>
+#include <net/if_media.h>
+#include <net/if_types.h>
+
+#include <netinet/if_inarp.h>
+#include <netinet/in.h>
+#include <netinet/in_systm.h>
+#include <netinet/in_var.h>
+#include <netinet/ip.h>
+
+#include <net80211/ieee80211_var.h>
+#include <net80211/ieee80211_amrr.h>
+#include <net80211/ieee80211_radiotap.h>
+
+#include <dev/firmload.h>
+
+#include <dev/usb/usb.h>
+#include <dev/usb/usbdevs.h>
+#include <dev/usb/usbdi.h>
+#include <dev/usb/usbdi_util.h>
+
+#include <dev/ic/athnreg.h>
+#include <dev/ic/athnvar.h>
+#include <dev/ic/arn9285.h>
+#include <dev/usb/if_athn_usb.h>
+
+#define ATHN_USB_SOFTC(sc) ((struct athn_usb_softc *)(sc))
+#define ATHN_USB_NODE(ni) ((struct athn_usb_node *)(ni))
+
+#define IS_UP_AND_RUNNING(ifp) \
+ (((ifp)->if_flags & IFF_UP) && ((ifp)->if_flags & IFF_RUNNING))
+
+#define athn_usb_wmi_cmd(sc, cmd_id) \
+ athn_usb_wmi_xcmd(sc, cmd_id, NULL, 0, NULL)
+
+Static int athn_usb_activate(device_t, enum devact);
+Static int athn_usb_detach(device_t, int);
+Static int athn_usb_match(device_t, cfdata_t, void *);
+Static void athn_usb_attach(device_t, device_t, void *);
+
+CFATTACH_DECL_NEW(athn_usb, sizeof(struct athn_usb_softc), athn_usb_match,
+ athn_usb_attach, athn_usb_detach, athn_usb_activate);
+
+Static int athn_usb_alloc_rx_list(struct athn_usb_softc *);
+Static int athn_usb_alloc_tx_cmd(struct athn_usb_softc *);
+Static int athn_usb_alloc_tx_list(struct athn_usb_softc *);
+Static void athn_usb_attachhook(device_t);
+Static void athn_usb_bcneof(usbd_xfer_handle, usbd_private_handle,
+ usbd_status);
+Static void athn_usb_close_pipes(struct athn_usb_softc *);
+Static int athn_usb_create_hw_node(struct athn_usb_softc *,
+ struct ar_htc_target_sta *);
+Static int athn_usb_create_node(struct athn_usb_softc *,
+ struct ieee80211_node *);
+Static void athn_usb_do_async(struct athn_usb_softc *,
+ void (*)(struct athn_usb_softc *, void *), void *, int);
+Static void athn_usb_free_rx_list(struct athn_usb_softc *);
+Static void athn_usb_free_tx_cmd(struct athn_usb_softc *);
+Static void athn_usb_free_tx_list(struct athn_usb_softc *);
+Static int athn_usb_htc_connect_svc(struct athn_usb_softc *, uint16_t,
+ uint8_t, uint8_t, uint8_t *);
+Static int athn_usb_htc_msg(struct athn_usb_softc *, uint16_t, void *,
+ int);
+Static int athn_usb_htc_setup(struct athn_usb_softc *);
+Static int athn_usb_init(struct ifnet *);
+Static void athn_usb_intr(usbd_xfer_handle, usbd_private_handle,
+ usbd_status);
+Static int athn_usb_ioctl(struct ifnet *, u_long, void *);
+Static int athn_usb_load_firmware(struct athn_usb_softc *);
+Static const struct athn_usb_type *
+ athn_usb_lookup(int, int);
+Static int athn_usb_media_change(struct ifnet *);
+Static void athn_usb_newassoc(struct ieee80211_node *, int);
+Static void athn_usb_newassoc_cb(struct athn_usb_softc *, void *);
+Static int athn_usb_newstate(struct ieee80211com *, enum ieee80211_state,
+ int);
+Static void athn_usb_newstate_cb(struct athn_usb_softc *, void *);
+Static void athn_usb_node_cleanup(struct ieee80211_node *);
+Static void athn_usb_node_cleanup_cb(struct athn_usb_softc *, void *);
+Static int athn_usb_open_pipes(struct athn_usb_softc *);
+Static uint32_t athn_usb_read(struct athn_softc *, uint32_t);
+Static int athn_usb_remove_hw_node(struct athn_usb_softc *, uint8_t *);
+Static void athn_usb_rx_enable(struct athn_softc *);
+Static void athn_usb_rx_frame(struct athn_usb_softc *, struct mbuf *);
+Static void athn_usb_rx_radiotap(struct athn_softc *, struct mbuf *,
+ struct ar_rx_status *);
+Static void athn_usb_rx_wmi_ctrl(struct athn_usb_softc *, uint8_t *, int);
+Static void athn_usb_rxeof(usbd_xfer_handle, usbd_private_handle,
+ usbd_status);
+Static void athn_usb_start(struct ifnet *);
+Static void athn_usb_stop(struct ifnet *);
+Static void athn_usb_swba(struct athn_usb_softc *);
+Static int athn_usb_switch_chan(struct athn_softc *,
+ struct ieee80211_channel *, struct ieee80211_channel *);
+Static void athn_usb_task(void *);
+Static int athn_usb_tx(struct athn_softc *, struct mbuf *,
+ struct ieee80211_node *, struct athn_usb_tx_data *);
+Static void athn_usb_txeof(usbd_xfer_handle, usbd_private_handle,
+ usbd_status);
+Static void athn_usb_updateslot(struct ifnet *);
+Static void athn_usb_updateslot_cb(struct athn_usb_softc *, void *);
+Static void athn_usb_wait_async(struct athn_usb_softc *);
+Static void athn_usb_wait_cmd(struct athn_usb_softc *);
+Static void athn_usb_wait_msg(struct athn_usb_softc *);
+Static void athn_usb_wait_wmi(struct athn_usb_softc *);
+Static void athn_usb_watchdog(struct ifnet *);
+Static int athn_usb_wmi_xcmd(struct athn_usb_softc *, uint16_t, void *,
+ int, void *);
+Static void athn_usb_wmieof(usbd_xfer_handle, usbd_private_handle,
+ usbd_status);
+Static void athn_usb_write(struct athn_softc *, uint32_t, uint32_t);
+Static void athn_usb_write_barrier(struct athn_softc *);
+
+/************************************************************************
+ * unused/notyet declarations
+ */
+#ifdef unused
+Static int athn_usb_read_rom(struct athn_softc *);
+#endif /* unused */
+
+#ifdef notyet_edca
+Static void athn_usb_updateedca(struct ieee80211com *);
+Static void athn_usb_updateedca_cb(struct athn_usb_softc *, void *);
+#endif /* notyet_edca */
+
+#ifdef notyet
+Static int athn_usb_ampdu_tx_start(struct ieee80211com *,
+ struct ieee80211_node *, uint8_t);
+Static void athn_usb_ampdu_tx_start_cb(struct athn_usb_softc *, void *);
+Static void athn_usb_ampdu_tx_stop(struct ieee80211com *,
+ struct ieee80211_node *, uint8_t);
+Static void athn_usb_ampdu_tx_stop_cb(struct athn_usb_softc *, void *);
+Static void athn_usb_delete_key(struct ieee80211com *,
+ struct ieee80211_node *, struct ieee80211_key *);
+Static void athn_usb_delete_key_cb(struct athn_usb_softc *, void *);
+Static int athn_usb_set_key(struct ieee80211com *,
+ struct ieee80211_node *, struct ieee80211_key *);
+Static void athn_usb_set_key_cb(struct athn_usb_softc *, void *);
+#endif /* notyet */
+/************************************************************************/
+
+struct athn_usb_type {
+ struct usb_devno devno;
+ u_int flags;
+};
+
+Static const struct athn_usb_type *
+athn_usb_lookup(int vendor, int product)
+{
+ static const struct athn_usb_type athn_usb_devs[] = {
+#define _D(v,p,f) \
+ {{ USB_VENDOR_##v, USB_PRODUCT_##p }, ATHN_USB_FLAG_##f }
+
+ _D( ACCTON, ACCTON_AR9280, AR7010 ),
+ _D( ACTIONTEC, ACTIONTEC_AR9287, AR7010 ),
+ _D( ATHEROS2, ATHEROS2_AR9271_1, NONE ),
+ _D( ATHEROS2, ATHEROS2_AR9271_2, NONE ),
+ _D( ATHEROS2, ATHEROS2_AR9271_3, NONE ),
+ _D( ATHEROS2, ATHEROS2_AR9280, AR7010 ),
+ _D( ATHEROS2, ATHEROS2_AR9287, AR7010 ),
+ _D( AZUREWAVE, AZUREWAVE_AR9271_1, NONE ),
+ _D( AZUREWAVE, AZUREWAVE_AR9271_2, NONE ),
+ _D( AZUREWAVE, AZUREWAVE_AR9271_3, NONE ),
+ _D( AZUREWAVE, AZUREWAVE_AR9271_4, NONE ),
+ _D( AZUREWAVE, AZUREWAVE_AR9271_5, NONE ),
+ _D( AZUREWAVE, AZUREWAVE_AR9271_6, NONE ),
+ _D( DLINK2, DLINK2_AR9271, NONE ),
+ _D( LITEON, LITEON_AR9271, NONE ),
+ _D( NETGEAR, NETGEAR_WNA1100, NONE ),
+ _D( NETGEAR, NETGEAR_WNDA3200, AR7010 ),
+ _D( VIA, VIA_AR9271, NONE )
+#undef _D
+ };
+
+ return (const void *)usb_lookup(athn_usb_devs, vendor, product);
+}
+
+Static int
+athn_usb_match(device_t parent, cfdata_t match, void *aux)
+{
+ struct usb_attach_arg *uaa = aux;
+
+ return athn_usb_lookup(uaa->vendor, uaa->product) != NULL ?
+ UMATCH_VENDOR_PRODUCT : UMATCH_NONE;
+}
+
+Static void
+athn_usb_attach(device_t parent, device_t self, void *aux)
+{
+ struct athn_usb_softc *usc;
+ struct athn_softc *sc;
+ struct usb_attach_arg *uaa;
+ int error;
+
+ usc = device_private(self);
+ sc = &usc->usc_sc;
+ uaa = aux;
+ sc->sc_dev = self;
+ usc->usc_udev = uaa->device;
+
+ aprint_naive("\n");
+ aprint_normal("\n");
+
+ DPRINTFN(DBG_FN, sc, "\n");
+
+ usc->usc_athn_attached = 0;
+ usc->usc_flags = athn_usb_lookup(uaa->vendor, uaa->product)->flags;
+ sc->sc_flags |= ATHN_FLAG_USB;
+#ifdef notyet
+ /* Check if it is a combo WiFi+Bluetooth (WB193) device. */
+ if (strncmp(product, "wb193", 5) == 0)
+ sc->sc_flags |= ATHN_FLAG_BTCOEX3WIRE;
+#endif
+
+ sc->sc_ops.read = athn_usb_read;
+ sc->sc_ops.write = athn_usb_write;
+ sc->sc_ops.write_barrier = athn_usb_write_barrier;
+
+ mutex_init(&usc->usc_task_mtx, MUTEX_DEFAULT, IPL_NET);
+ mutex_init(&usc->usc_tx_mtx, MUTEX_DEFAULT, IPL_NONE);
+
+ usb_init_task(&usc->usc_task, athn_usb_task, usc, 0);
+
+ if (usbd_set_config_no(usc->usc_udev, 1, 0) != 0) {
+ aprint_error_dev(sc->sc_dev,
+ "could not set configuration no\n");
+ goto fail;
+ }
+
+ /* Get the first interface handle. */
+ error = usbd_device2interface_handle(usc->usc_udev, 0, &usc->usc_iface);
+ if (error != 0) {
+ aprint_error_dev(sc->sc_dev,
+ "could not get interface handle\n");
+ goto fail;
+ }
+
+ if (athn_usb_open_pipes(usc) != 0)
+ goto fail;
+
+ /* Allocate xfer for firmware commands. */
+ if (athn_usb_alloc_tx_cmd(usc) != 0)
+ goto fail;
+
+ config_mountroot(self, athn_usb_attachhook);
+
+ usbd_add_drv_event(USB_EVENT_DRIVER_ATTACH, usc->usc_udev, sc->sc_dev);
+ return;
+
+ fail:
+ athn_usb_free_tx_cmd(usc);
+ athn_usb_close_pipes(usc);
+ usb_rem_task(usc->usc_udev, &usc->usc_task);
+ mutex_destroy(&usc->usc_tx_mtx);
+ mutex_destroy(&usc->usc_task_mtx);
+}
+
+Static void
+athn_usb_node_cleanup_cb(struct athn_usb_softc *usc, void *arg)
+{
+ uint8_t sta_index = *(uint8_t *)arg;
+
+ DPRINTFN(DBG_FN, usc, "\n");
+ DPRINTFN(DBG_NODES, usc, "removing node %u\n", sta_index);
+ athn_usb_remove_hw_node(usc, &sta_index);
+}
+
+Static void
+athn_usb_node_cleanup(struct ieee80211_node *ni)
+{
+ struct athn_usb_softc *usc;
+ struct ieee80211com *ic;
+ uint8_t sta_index;
+
+ usc = ATHN_USB_SOFTC(ni->ni_ic->ic_ifp->if_softc);
+ ic = &ATHN_SOFTC(usc)->sc_ic;
+
+ DPRINTFN(DBG_FN, usc, "\n");
+
+ if (ic->ic_opmode == IEEE80211_M_HOSTAP) {
+ sta_index = ATHN_NODE(ni)->sta_index;
+ if (sta_index != 0)
+ athn_usb_do_async(usc, athn_usb_node_cleanup_cb,
+ &sta_index, sizeof(sta_index));
+ }
+ usc->usc_node_cleanup(ni);
+}
+
+Static void
+athn_usb_attachhook(device_t arg)
+{
+ struct athn_usb_softc *usc = device_private(arg);
+ struct athn_softc *sc = &usc->usc_sc;
+ struct athn_ops *ops = &sc->sc_ops;
+ struct ieee80211com *ic = &sc->sc_ic;
+ struct ifnet *ifp = &sc->sc_if;
+ size_t i;
+ int s, error;
+
+ if (usc->usc_dying)
+ return;
+
+ DPRINTFN(DBG_FN, usc, "\n");
+
+ /* Load firmware. */
+ error = athn_usb_load_firmware(usc);
+ if (error != 0) {
+ aprint_error_dev(sc->sc_dev,
+ "could not load firmware (%d)\n", error);
+ return;
+ }
+
+ /* Setup the host transport communication interface. */
+ error = athn_usb_htc_setup(usc);
+ if (error != 0)
+ return;
+
+ /* We're now ready to attach the bus agnostic driver. */
+ s = splnet();
+ ic->ic_ifp = ifp;
+ ic->ic_updateslot = athn_usb_updateslot;
+ sc->sc_max_aid = AR_USB_MAX_STA; /* Firmware is limited to 8 STA */
+ sc->sc_media_change = athn_usb_media_change;
+ error = athn_attach(sc);
+ if (error != 0) {
+ splx(s);
+ return;
+ }
+ usc->usc_athn_attached = 1;
+
+ /* Override some operations for USB. */
+ ifp->if_init = athn_usb_init;
+ ifp->if_ioctl = athn_usb_ioctl;
+ ifp->if_start = athn_usb_start;
+ ifp->if_watchdog = athn_usb_watchdog;
+
+ /* hooks for HostAP association and disassociation */
+ ic->ic_newassoc = athn_usb_newassoc;
+ usc->usc_node_cleanup = ic->ic_node_cleanup;
+ ic->ic_node_cleanup = athn_usb_node_cleanup;
+
+#ifdef notyet_edca
+ ic->ic_updateedca = athn_usb_updateedca;
+#endif
+#ifdef notyet
+ ic->ic_set_key = athn_usb_set_key;
+ ic->ic_delete_key = athn_usb_delete_key;
+ ic->ic_ampdu_tx_start = athn_usb_ampdu_tx_start;
+ ic->ic_ampdu_tx_stop = athn_usb_ampdu_tx_stop;
+#endif
+ ic->ic_newstate = athn_usb_newstate;
+
+ ops->rx_enable = athn_usb_rx_enable;
+ splx(s);
+
+ /* Reset HW key cache entries. */
+ for (i = 0; i < sc->sc_kc_entries; i++)
+ athn_reset_key(sc, i);
+
+ ops->enable_antenna_diversity(sc);
+
+#ifdef ATHN_BT_COEXISTENCE
+ /* Configure bluetooth coexistence for combo chips. */
+ if (sc->sc_flags & ATHN_FLAG_BTCOEX)
+ athn_btcoex_init(sc);
+#endif
+ /* Configure LED. */
+ athn_led_init(sc);
+
+ ieee80211_announce(ic);
+}
+
+Static int
+athn_usb_detach(device_t self, int flags)
+{
+ struct athn_usb_softc *usc = device_private(self);
+ struct athn_softc *sc = &usc->usc_sc;
+ int s;
+
+ DPRINTFN(DBG_FN, usc, "\n");
+
+ s = splusb();
+ usc->usc_dying = 1;
+
+ athn_usb_wait_wmi(usc);
+ athn_usb_wait_cmd(usc);
+ athn_usb_wait_msg(usc);
+ athn_usb_wait_async(usc);
+
+ usb_rem_task(usc->usc_udev, &usc->usc_task);
+
+ if (usc->usc_athn_attached) {
+ usc->usc_athn_attached = 0;
+ athn_detach(sc);
+ }
+ /* Abort and close Tx/Rx pipes. */
+ athn_usb_close_pipes(usc);
+ splx(s);
+
+ /* Free Tx/Rx buffers. */
+ athn_usb_free_rx_list(usc);
+ athn_usb_free_tx_list(usc);
+ athn_usb_free_tx_cmd(usc);
+
+ mutex_destroy(&usc->usc_tx_mtx);
+ mutex_destroy(&usc->usc_task_mtx);
+
+ usbd_add_drv_event(USB_EVENT_DRIVER_DETACH, usc->usc_udev, sc->sc_dev);
+ return 0;
+}
+
+Static int
+athn_usb_activate(device_t self, enum devact act)
+{
+ struct athn_usb_softc *usc = device_private(self);
+ struct athn_softc *sc = &usc->usc_sc;
+
+ DPRINTFN(DBG_FN, usc, "\n");
+
+ switch (act) {
+ case DVACT_DEACTIVATE:
+ if_deactivate(sc->sc_ic.ic_ifp);
+ usc->usc_dying = 1;
+ return 0;
+ default:
+ return EOPNOTSUPP;
+ }
+}
+
+Static int
+athn_usb_open_pipes(struct athn_usb_softc *usc)
+{
+ usb_endpoint_descriptor_t *ed;
+ int isize, error;
+
+ DPRINTFN(DBG_FN, usc, "\n");
+
+ error = usbd_open_pipe(usc->usc_iface, AR_PIPE_TX_DATA, 0,
+ &usc->usc_tx_data_pipe);
+ if (error != 0) {
+ aprint_error_dev(usc->usc_dev,
+ "could not open Tx bulk pipe\n");
+ goto fail;
+ }
+
+ error = usbd_open_pipe(usc->usc_iface, AR_PIPE_RX_DATA, 0,
+ &usc->usc_rx_data_pipe);
+ if (error != 0) {
+ aprint_error_dev(usc->usc_dev,
+ "could not open Rx bulk pipe\n");
+ goto fail;
+ }
+
+ ed = usbd_get_endpoint_descriptor(usc->usc_iface, AR_PIPE_RX_INTR);
+ if (ed == NULL) {
+ aprint_error_dev(usc->usc_dev,
+ "could not retrieve Rx intr pipe descriptor\n");
+ goto fail;
+ }
+ isize = UGETW(ed->wMaxPacketSize);
+ if (isize == 0) {
+ aprint_error_dev(usc->usc_dev,
+ "invalid Rx intr pipe descriptor\n");
+ goto fail;
+ }
+ usc->usc_ibuf = malloc(isize, M_USBDEV, M_NOWAIT);
+ if (usc->usc_ibuf == NULL) {
+ aprint_error_dev(usc->usc_dev,
+ "could not allocate Rx intr buffer\n");
+ goto fail;
+ }
+ error = usbd_open_pipe_intr(usc->usc_iface, AR_PIPE_RX_INTR,
+ USBD_SHORT_XFER_OK, &usc->usc_rx_intr_pipe, usc, usc->usc_ibuf, isize,
+ athn_usb_intr, USBD_DEFAULT_INTERVAL);
+ if (error != 0) {
+ aprint_error_dev(usc->usc_dev,
+ "could not open Rx intr pipe\n");
+ goto fail;
+ }
+ error = usbd_open_pipe(usc->usc_iface, AR_PIPE_TX_INTR, 0,
+ &usc->usc_tx_intr_pipe);
+ if (error != 0) {
+ aprint_error_dev(usc->usc_dev,
+ "could not open Tx intr pipe\n");
+ goto fail;
+ }
+ return 0;
+ fail:
+ athn_usb_close_pipes(usc);
+ return error;
+}
+
+static inline void
+athn_usb_kill_pipe(usbd_pipe_handle *pipeptr)
+{
+ usbd_pipe_handle pipe;
+
+ CTASSERT(sizeof(pipe) == sizeof(void *));
+ pipe = atomic_swap_ptr(pipeptr, NULL);
+ if (pipe != NULL) {
+ usbd_abort_pipe(pipe);
+ usbd_close_pipe(pipe);
+ }
+}
+
+Static void
+athn_usb_close_pipes(struct athn_usb_softc *usc)
+{
+ uint8_t *ibuf;
+
+ DPRINTFN(DBG_FN, usc, "\n");
+
+ athn_usb_kill_pipe(&usc->usc_tx_data_pipe);
+ athn_usb_kill_pipe(&usc->usc_rx_data_pipe);
+ athn_usb_kill_pipe(&usc->usc_tx_intr_pipe);
+ athn_usb_kill_pipe(&usc->usc_rx_intr_pipe);
+ ibuf = atomic_swap_ptr(&usc->usc_ibuf, NULL);
+ if (ibuf != NULL)
+ free(ibuf, M_USBDEV);
+}
+
+Static int
+athn_usb_alloc_rx_list(struct athn_usb_softc *usc)
+{
+ struct athn_usb_rx_data *data;
+ size_t i;
+ int error = 0;
+
+ DPRINTFN(DBG_FN, usc, "\n");
+
+ for (i = 0; i < ATHN_USB_RX_LIST_COUNT; i++) {
+ data = &usc->usc_rx_data[i];
+
+ data->sc = usc; /* Backpointer for callbacks. */
+
+ data->xfer = usbd_alloc_xfer(usc->usc_udev);
+ if (data->xfer == NULL) {
+ aprint_error_dev(usc->usc_dev,
+ "could not allocate xfer\n");
+ error = ENOMEM;
+ break;
+ }
+ data->buf = usbd_alloc_buffer(data->xfer, ATHN_USB_RXBUFSZ);
+ if (data->buf == NULL) {
+ aprint_error_dev(usc->usc_dev,
+ "could not allocate xfer buffer\n");
+ error = ENOMEM;
+ break;
+ }
+ }
+ if (error != 0)
+ athn_usb_free_rx_list(usc);
+ return error;
+}
+
+Static void
+athn_usb_free_rx_list(struct athn_usb_softc *usc)
+{
+ usbd_xfer_handle xfer;
+ size_t i;
+
+ DPRINTFN(DBG_FN, usc, "\n");
+
+ /* NB: Caller must abort pipe first. */
+ for (i = 0; i < ATHN_USB_RX_LIST_COUNT; i++) {
+ CTASSERT(sizeof(xfer) == sizeof(void *));
+ xfer = atomic_swap_ptr(&usc->usc_rx_data[i].xfer, NULL);
+ if (xfer != NULL)
+ usbd_free_xfer(xfer);
+ }
+}
+
+Static int
+athn_usb_alloc_tx_list(struct athn_usb_softc *usc)
+{
+ struct athn_usb_tx_data *data;
+ size_t i;
+ int error = 0;
+
+ DPRINTFN(DBG_FN, usc, "\n");
+
+ mutex_enter(&usc->usc_tx_mtx);
+ TAILQ_INIT(&usc->usc_tx_free_list);
+ for (i = 0; i < ATHN_USB_TX_LIST_COUNT; i++) {
+ data = &usc->usc_tx_data[i];
+
+ data->sc = usc; /* Backpointer for callbacks. */
+
+ data->xfer = usbd_alloc_xfer(usc->usc_udev);
+ if (data->xfer == NULL) {
+ aprint_error_dev(usc->usc_dev,
+ "could not allocate xfer\n");
+ error = ENOMEM;
+ break;
+ }
+ data->buf = usbd_alloc_buffer(data->xfer, ATHN_USB_TXBUFSZ);
+ if (data->buf == NULL) {
+ aprint_error_dev(usc->usc_dev,
+ "could not allocate xfer buffer\n");
+ error = ENOMEM;
+ break;
+ }
+ /* Append this Tx buffer to our free list. */
+ TAILQ_INSERT_TAIL(&usc->usc_tx_free_list, data, next);
+ }
+ if (error != 0)
+ athn_usb_free_tx_list(usc);
+ mutex_exit(&usc->usc_tx_mtx);
+ return error;
+}
+
+Static void
+athn_usb_free_tx_list(struct athn_usb_softc *usc)
+{
+ usbd_xfer_handle xfer;
+ size_t i;
+
+ DPRINTFN(DBG_FN, usc, "\n");
+
+ /* NB: Caller must abort pipe first. */
+ for (i = 0; i < ATHN_USB_TX_LIST_COUNT; i++) {
+ CTASSERT(sizeof(xfer) == sizeof(void *));
+ xfer = atomic_swap_ptr(&usc->usc_tx_data[i].xfer, NULL);
+ if (xfer != NULL)
+ usbd_free_xfer(xfer);
+ }
+}
+
+Static int
+athn_usb_alloc_tx_cmd(struct athn_usb_softc *usc)
+{
+ struct athn_usb_tx_data *data = &usc->usc_tx_cmd;
+
+ DPRINTFN(DBG_FN, usc, "\n");
+
+ data->sc = usc; /* Backpointer for callbacks. */
+
+ data->xfer = usbd_alloc_xfer(usc->usc_udev);
+ if (data->xfer == NULL) {
+ aprint_error_dev(usc->usc_dev, "could not allocate xfer\n");
+ return ENOMEM;
+ }
+ data->buf = usbd_alloc_buffer(data->xfer, ATHN_USB_TXCMDSZ);
+ if (data->buf == NULL) {
+ aprint_error_dev(usc->usc_dev,
+ "could not allocate xfer buffer\n");
+ return ENOMEM;
+ }
+ return 0;
+}
+
+Static void
+athn_usb_free_tx_cmd(struct athn_usb_softc *usc)
+{
+ usbd_xfer_handle xfer;
+
+ DPRINTFN(DBG_FN, usc, "\n");
+
+ CTASSERT(sizeof(xfer) == sizeof(void *));
+ xfer = atomic_swap_ptr(&usc->usc_tx_cmd.xfer, NULL);
+ if (xfer != NULL)
+ usbd_free_xfer(xfer);
+}
+
+Static void
+athn_usb_task(void *arg)
+{
+ struct athn_usb_softc *usc = arg;
+ struct athn_usb_host_cmd_ring *ring = &usc->usc_cmdq;
+ struct athn_usb_host_cmd *cmd;
+ int s;
+
+ DPRINTFN(DBG_FN, usc, "\n");
+
+ /* Process host commands. */
+ s = splusb();
+ mutex_spin_enter(&usc->usc_task_mtx);
+ while (ring->next != ring->cur) {
+ cmd = &ring->cmd[ring->next];
+ mutex_spin_exit(&usc->usc_task_mtx);
+ splx(s);
+
+ /* Invoke callback. */
+ if (!usc->usc_dying)
+ cmd->cb(usc, cmd->data);
+
+ s = splusb();
+ mutex_spin_enter(&usc->usc_task_mtx);
+ ring->queued--;
+ ring->next = (ring->next + 1) % ATHN_USB_HOST_CMD_RING_COUNT;
+ }
+ mutex_spin_exit(&usc->usc_task_mtx);
+ wakeup(ring);
+ splx(s);
+}
+
+Static void
+athn_usb_do_async(struct athn_usb_softc *usc,
+ void (*cb)(struct athn_usb_softc *, void *), void *arg, int len)
+{
+ struct athn_usb_host_cmd_ring *ring = &usc->usc_cmdq;
+ struct athn_usb_host_cmd *cmd;
+ int s;
+
+ if (usc->usc_dying)
+ return;
+
+ DPRINTFN(DBG_FN, usc, "\n");
+
+ s = splusb();
+ mutex_spin_enter(&usc->usc_task_mtx);
+ cmd = &ring->cmd[ring->cur];
+ cmd->cb = cb;
+ KASSERT(len <= sizeof(cmd->data));
+ memcpy(cmd->data, arg, len);
+ ring->cur = (ring->cur + 1) % ATHN_USB_HOST_CMD_RING_COUNT;
+
+ /* If there is no pending command already, schedule a task. */
+ if (++ring->queued == 1) {
+ mutex_spin_exit(&usc->usc_task_mtx);
+ usb_add_task(usc->usc_udev, &usc->usc_task, USB_TASKQ_DRIVER);
+ }
+ else
+ mutex_spin_exit(&usc->usc_task_mtx);
+ splx(s);
+}
+
+Static void
+athn_usb_wait_async(struct athn_usb_softc *usc)
+{
+
+ DPRINTFN(DBG_FN, usc, "\n");
+
+ /* Wait for all queued asynchronous commands to complete. */
+ while (usc->usc_cmdq.queued > 0)
+ tsleep(&usc->usc_cmdq, 0, "cmdq", 0);
+}
+
+Static int
+athn_usb_load_firmware(struct athn_usb_softc *usc)
+{
+ struct athn_softc *sc = &usc->usc_sc;
+ firmware_handle_t fwh;
+ usb_device_descriptor_t *dd;
+ usb_device_request_t req;
+ const char *name;
+ u_char *fw, *ptr;
+ size_t size;
+ uint32_t addr;
+ int s, mlen, error;
+
+ DPRINTFN(DBG_FN, sc, "\n");
+
+ /* Determine which firmware image to load. */
+ if (usc->usc_flags & ATHN_USB_FLAG_AR7010) {
+ dd = usbd_get_device_descriptor(usc->usc_udev);
+ if (UGETW(dd->bcdDevice) == 0x0202)
+ name = "athn-ar7010-11";
+ else
+ name = "athn-ar7010";
+ }
+ else
+ name = "athn-ar9271";
+
+ /* Read firmware image from the filesystem. */
+ if ((error = firmware_open("if_athn_usb", name, &fwh)) != 0) {
+ aprint_error_dev(sc->sc_dev,
+ "failed to open firmware file %s (%d)\n", name, error);
+ return error;
+ }
+ size = firmware_get_size(fwh);
+ fw = firmware_malloc(size);
+ if (fw == NULL) {
+ aprint_error_dev(usc->usc_dev,
+ "failed to allocate firmware memory\n");
+ firmware_close(fwh);
+ return ENOMEM;
+ }
+ error = firmware_read(fwh, 0, fw, size);
+ firmware_close(fwh);
+ if (error != 0) {
+ aprint_error_dev(usc->usc_dev,
+ "failed to read firmware (error %d)\n", error);
+ firmware_free(fw, 0);
+ return error;
+ }
+
+ /* Load firmware image. */
+ ptr = fw;
+ addr = AR9271_FIRMWARE >> 8;
+ req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
+ req.bRequest = AR_FW_DOWNLOAD;
+ USETW(req.wIndex, 0);
+ while (size > 0) {
+ mlen = MIN(size, 4096);
+
+ USETW(req.wValue, addr);
+ USETW(req.wLength, mlen);
+ error = usbd_do_request(usc->usc_udev, &req, ptr);
+ if (error != 0) {
+ free(fw, M_DEVBUF);
+ return error;
+ }
+ addr += mlen >> 8;
+ ptr += mlen;
+ size -= mlen;
+ }
+ free(fw, M_DEVBUF);
+
+ /* Start firmware. */
+ if (usc->usc_flags & ATHN_USB_FLAG_AR7010)
+ addr = AR7010_FIRMWARE_TEXT >> 8;
+ else
+ addr = AR9271_FIRMWARE_TEXT >> 8;
+ req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
+ req.bRequest = AR_FW_DOWNLOAD_COMP;
+ USETW(req.wIndex, 0);
+ USETW(req.wValue, addr);
+ USETW(req.wLength, 0);
+
+ s = splusb();
+ usc->usc_wait_msg_id = AR_HTC_MSG_READY;
+ error = usbd_do_request(usc->usc_udev, &req, NULL);
+ /* Wait at most 1 second for firmware to boot. */
+ if (error == 0 && usc->usc_wait_msg_id != 0)
+ error = tsleep(&usc->usc_wait_msg_id, 0, "athnfw", hz);
+ usc->usc_wait_msg_id = 0;
+ splx(s);
+ return error;
+}
+
+Static int
+athn_usb_htc_msg(struct athn_usb_softc *usc, uint16_t msg_id, void *buf,
+ int len)
+{
+ struct athn_usb_tx_data *data = &usc->usc_tx_cmd;
+ struct ar_htc_frame_hdr *htc;
+ struct ar_htc_msg_hdr *msg;
+
+ if (usc->usc_dying)
+ return USBD_CANCELLED;
+
+ DPRINTFN(DBG_FN, usc, "\n");
+
+ htc = (struct ar_htc_frame_hdr *)data->buf;
+ memset(htc, 0, sizeof(*htc));
+ htc->endpoint_id = 0;
+ htc->payload_len = htobe16(sizeof(*msg) + len);
+
+ msg = (struct ar_htc_msg_hdr *)&htc[1];
+ msg->msg_id = htobe16(msg_id);
+
+ memcpy(&msg[1], buf, len);
+
+ usbd_setup_xfer(data->xfer, usc->usc_tx_intr_pipe, NULL, data->buf,
+ sizeof(*htc) + sizeof(*msg) + len,
+ USBD_SHORT_XFER_OK | USBD_NO_COPY, ATHN_USB_CMD_TIMEOUT, NULL);
+ return usbd_sync_transfer(data->xfer);
+}
+
+Static int
+athn_usb_htc_setup(struct athn_usb_softc *usc)
+{
+ struct ar_htc_msg_config_pipe cfg;
+ int s, error;
+
+ /*
+ * Connect WMI services to USB pipes.
+ */
+ error = athn_usb_htc_connect_svc(usc, AR_SVC_WMI_CONTROL,
+ AR_PIPE_TX_INTR, AR_PIPE_RX_INTR, &usc->usc_ep_ctrl);
+ if (error != 0)
+ return error;
+ error = athn_usb_htc_connect_svc(usc, AR_SVC_WMI_BEACON,
+ AR_PIPE_TX_DATA, AR_PIPE_RX_DATA, &usc->usc_ep_bcn);
+ if (error != 0)
+ return error;
+ error = athn_usb_htc_connect_svc(usc, AR_SVC_WMI_CAB,
+ AR_PIPE_TX_DATA, AR_PIPE_RX_DATA, &usc->usc_ep_cab);
+ if (error != 0)
+ return error;
+ error = athn_usb_htc_connect_svc(usc, AR_SVC_WMI_UAPSD,
+ AR_PIPE_TX_DATA, AR_PIPE_RX_DATA, &usc->usc_ep_uapsd);
+ if (error != 0)
+ return error;
+ error = athn_usb_htc_connect_svc(usc, AR_SVC_WMI_MGMT,
+ AR_PIPE_TX_DATA, AR_PIPE_RX_DATA, &usc->usc_ep_mgmt);
+ if (error != 0)
+ return error;
+ error = athn_usb_htc_connect_svc(usc, AR_SVC_WMI_DATA_BE,
+ AR_PIPE_TX_DATA, AR_PIPE_RX_DATA, &usc->usc_ep_data[EDCA_AC_BE]);
+ if (error != 0)
+ return error;
+ error = athn_usb_htc_connect_svc(usc, AR_SVC_WMI_DATA_BK,
+ AR_PIPE_TX_DATA, AR_PIPE_RX_DATA, &usc->usc_ep_data[EDCA_AC_BK]);
+ if (error != 0)
+ return error;
+ error = athn_usb_htc_connect_svc(usc, AR_SVC_WMI_DATA_VI,
+ AR_PIPE_TX_DATA, AR_PIPE_RX_DATA, &usc->usc_ep_data[EDCA_AC_VI]);
+ if (error != 0)
+ return error;
+ error = athn_usb_htc_connect_svc(usc, AR_SVC_WMI_DATA_VO,
+ AR_PIPE_TX_DATA, AR_PIPE_RX_DATA, &usc->usc_ep_data[EDCA_AC_VO]);
+ if (error != 0)
+ return error;
+
+ /* Set credits for WLAN Tx pipe. */
+ memset(&cfg, 0, sizeof(cfg));
+ cfg.pipe_id = UE_GET_ADDR(AR_PIPE_TX_DATA);
+ cfg.credits = (usc->usc_flags & ATHN_USB_FLAG_AR7010) ? 45 : 33;
+
+ s = splusb();
+
+ usc->usc_wait_msg_id = AR_HTC_MSG_CONF_PIPE_RSP;
+ error = athn_usb_htc_msg(usc, AR_HTC_MSG_CONF_PIPE, &cfg, sizeof(cfg));
+ if (error == 0 && usc->usc_wait_msg_id != 0)
+ error = tsleep(&usc->usc_wait_msg_id, 0, "athnhtc", hz);
+ usc->usc_wait_msg_id = 0;
+
+ splx(s);
+
+ if (error != 0) {
+ aprint_error_dev(usc->usc_dev, "could not configure pipe\n");
+ return error;
+ }
+
+ error = athn_usb_htc_msg(usc, AR_HTC_MSG_SETUP_COMPLETE, NULL, 0);
+ if (error != 0) {
+ aprint_error_dev(usc->usc_dev, "could not complete setup\n");
+ return error;
+ }
+ return 0;
+}
+
+Static int
+athn_usb_htc_connect_svc(struct athn_usb_softc *usc, uint16_t svc_id,
+ uint8_t ul_pipe, uint8_t dl_pipe, uint8_t *endpoint_id)
+{
+ struct ar_htc_msg_conn_svc msg;
+ struct ar_htc_msg_conn_svc_rsp rsp;
+ int s, error;
+
+ DPRINTFN(DBG_FN, usc, "\n");
+
+ memset(&msg, 0, sizeof(msg));
+ msg.svc_id = htobe16(svc_id);
+ msg.dl_pipeid = UE_GET_ADDR(dl_pipe);
+ msg.ul_pipeid = UE_GET_ADDR(ul_pipe);
+ s = splusb();
+
+ usc->usc_msg_conn_svc_rsp = &rsp;
+
+ usc->usc_wait_msg_id = AR_HTC_MSG_CONN_SVC_RSP;
+ error = athn_usb_htc_msg(usc, AR_HTC_MSG_CONN_SVC, &msg, sizeof(msg));
+ if (error == 0 && usc->usc_wait_msg_id != 0)
+ error = tsleep(&usc->usc_wait_msg_id, 0, "athnhtc", hz);
+ usc->usc_wait_msg_id = 0;
+
+ splx(s);
+ if (error != 0) {
+ aprint_error_dev(usc->usc_dev,
+ "error waiting for service %d connection\n", svc_id);
+ return error;
+ }
+ if (rsp.status != AR_HTC_SVC_SUCCESS) {
+ aprint_error_dev(usc->usc_dev,
+ "service %d connection failed, error %d\n",
+ svc_id, rsp.status);
+ return EIO;
+ }
+ DPRINTFN(DBG_INIT, usc,
+ "service %d successfully connected to endpoint %d\n",
+ svc_id, rsp.endpoint_id);
+
+ /* Return endpoint id. */
+ *endpoint_id = rsp.endpoint_id;
+ return 0;
+}
+
+Static void
+athn_usb_wait_msg(struct athn_usb_softc *usc)
+{
+
+ DPRINTFN(DBG_FN, usc, "\n");
+
+ while (__predict_false(usc->usc_wait_msg_id))
+ tsleep(&usc->usc_wait_msg_id, 0, "athnmsg", hz);
+}
+
+Static void
+athn_usb_wait_cmd(struct athn_usb_softc *usc)
+{
+
+ DPRINTFN(DBG_FN, usc, "\n");
+
+ while (__predict_false(usc->usc_wait_cmd_id))
+ tsleep(&usc->usc_wait_cmd_id, 0, "athncmd", hz);
+}
+
+Static void
+athn_usb_wmieof(usbd_xfer_handle xfer, usbd_private_handle priv,
+ usbd_status status)
+{
+ struct athn_usb_softc *usc = priv;
+
+ DPRINTFN(DBG_FN, usc, "\n");
+
+ if (__predict_false(status == USBD_STALLED))
+ usbd_clear_endpoint_stall_async(usc->usc_tx_intr_pipe);
+
+ usc->usc_wmi_done = 1;
+ wakeup(&usc->usc_wmi_done);
+}
+
+Static int
+athn_usb_wmi_xcmd(struct athn_usb_softc *usc, uint16_t cmd_id, void *ibuf,
+ int ilen, void *obuf)
+{
+ struct athn_usb_tx_data *data = &usc->usc_tx_cmd;
+ struct ar_htc_frame_hdr *htc;
+ struct ar_wmi_cmd_hdr *wmi;
+ int s, error;
+
+ if (usc->usc_dying)
+ return EIO;
+
+ DPRINTFN(DBG_FN, usc, "\n");
+
+ htc = (struct ar_htc_frame_hdr *)data->buf;
+ memset(htc, 0, sizeof(*htc));
+ htc->endpoint_id = usc->usc_ep_ctrl;
+ htc->payload_len = htobe16(sizeof(*wmi) + ilen);
+
+ wmi = (struct ar_wmi_cmd_hdr *)&htc[1];
+ wmi->cmd_id = htobe16(cmd_id);
+ usc->usc_wmi_seq_no++;
+ wmi->seq_no = htobe16(usc->usc_wmi_seq_no);
+
+ memcpy(&wmi[1], ibuf, ilen);
+
+ usbd_setup_xfer(data->xfer, usc->usc_tx_intr_pipe, usc, data->buf,
+ sizeof(*htc) + sizeof(*wmi) + ilen,
+ USBD_SHORT_XFER_OK | USBD_NO_COPY, ATHN_USB_CMD_TIMEOUT,
+ athn_usb_wmieof);
+
+ s = splusb();
+ usc->usc_wmi_done = 0;
+ usc->usc_wait_cmd_id = cmd_id;
+ error = usbd_transfer(data->xfer);
+ if (__predict_true(error == 0 || error == USBD_IN_PROGRESS)) {
+ usc->usc_obuf = obuf;
+
+ /* Wait for WMI command to complete. */
+ error = tsleep(&usc->usc_wait_cmd_id, 0, "athnwmi", hz);
+ usc->usc_wait_cmd_id = 0;
+ athn_usb_wait_wmi(usc);
+ }
+ splx(s);
+ return error;
+}
+
+Static void
+athn_usb_wait_wmi(struct athn_usb_softc *usc)
+{
+
+ DPRINTFN(DBG_FN, usc, "\n");
+
+ while (__predict_false(!usc->usc_wmi_done))
+ tsleep(&usc->usc_wmi_done, 0, "athnwmi", 0);
+}
+
+#ifdef unused
+Static int
+athn_usb_read_rom(struct athn_softc *sc)
+{
+ struct athn_usb_softc *usc = ATHN_USB_SOFTC(sc);
+ uint32_t addrs[8], vals[8], addr;
+ uint16_t *eep;
+ size_t i, j;
+ int error = 0;
+
+ DPRINTFN(DBG_FN, sc, "\n");
+
+ /* Read EEPROM by blocks of 16 bytes. */
+ eep = sc->sc_eep;
+ addr = AR_EEPROM_OFFSET(sc->sc_eep_base);
+ for (i = 0; i < sc->sc_eep_size / 16; i++) {
+ for (j = 0; j < 8; j++, addr += 4)
+ addrs[j] = htobe32(addr);
+ error = athn_usb_wmi_xcmd(usc, AR_WMI_CMD_REG_READ,
+ addrs, sizeof(addrs), vals);
+ if (error != 0)
+ break;
+ for (j = 0; j < 8; j++)
+ *eep++ = be32toh(vals[j]);
+ }
+ return error;
+}
+#endif /* unused */
+
+Static uint32_t
+athn_usb_read(struct athn_softc *sc, uint32_t addr)
+{
+ struct athn_usb_softc *usc = ATHN_USB_SOFTC(sc);
+ uint32_t val;
+ int error;
+
+ if (usc->usc_dying)
+ return 0;
+
+ DPRINTFN(DBG_FN, sc, "\n");
+
+ /* Flush pending writes for strict consistency. */
+ athn_usb_write_barrier(sc);
+
+ addr = htobe32(addr);
+ error = athn_usb_wmi_xcmd(usc, AR_WMI_CMD_REG_READ,
+ &addr, sizeof(addr), &val);
+ if (error != 0)
+ return 0xdeadbeef;
+ return be32toh(val);
+}
+
+Static void
+athn_usb_write(struct athn_softc *sc, uint32_t addr, uint32_t val)
+{
+ struct athn_usb_softc *usc = ATHN_USB_SOFTC(sc);
+
+ if (usc->usc_dying)
+ return;
+
+ DPRINTFN(DBG_FN, sc, "\n");
+
+ usc->usc_wbuf[usc->usc_wcount].addr = htobe32(addr);
+ usc->usc_wbuf[usc->usc_wcount].val = htobe32(val);
+ if (++usc->usc_wcount == AR_MAX_WRITE_COUNT)
+ athn_usb_write_barrier(sc);
+}
+
+Static void
+athn_usb_write_barrier(struct athn_softc *sc)
+{
+ struct athn_usb_softc *usc = ATHN_USB_SOFTC(sc);
+
+ if (usc->usc_dying)
+ goto done;
+
+ DPRINTFN(DBG_FN, sc, "\n");
+
+ if (usc->usc_wcount == 0)
+ return;
+
+ (void)athn_usb_wmi_xcmd(usc, AR_WMI_CMD_REG_WRITE,
+ usc->usc_wbuf, usc->usc_wcount * sizeof(usc->usc_wbuf[0]), NULL);
+ done:
+ usc->usc_wcount = 0; /* Always flush buffer. */
+}
+
+Static int
+athn_usb_media_change(struct ifnet *ifp)
+{
+ struct athn_softc *sc = ifp->if_softc;
+ struct athn_usb_softc *usc = ATHN_USB_SOFTC(sc);
+ int error;
+
+ if (usc->usc_dying)
+ return EIO;
+
+ DPRINTFN(DBG_FN, sc, "\n");
+
+ error = ieee80211_media_change(ifp);
+ if (error == ENETRESET && IS_UP_AND_RUNNING(ifp)) {
+ athn_usb_stop(ifp);
+ error = athn_usb_init(ifp);
+ }
+ return error;
+}
+
+Static int
+athn_usb_newstate(struct ieee80211com *ic, enum ieee80211_state nstate,
+ int arg)
+{
+ struct athn_softc *sc = ic->ic_ifp->if_softc;
+ struct athn_usb_softc *usc = ATHN_USB_SOFTC(sc);
+ struct athn_usb_cmd_newstate cmd;
+
+ DPRINTFN(DBG_FN, sc, "\n");
+
+ /* Do it in a process context. */
+ cmd.state = nstate;
+ cmd.arg = arg;
+ athn_usb_do_async(usc, athn_usb_newstate_cb, &cmd, sizeof(cmd));
+ return 0;
+}
+
+Static void
+athn_usb_newstate_cb(struct athn_usb_softc *usc, void *arg)
+{
+ struct athn_usb_cmd_newstate *cmd = arg;
+ struct athn_softc *sc = &usc->usc_sc;
+ struct ieee80211com *ic = &sc->sc_ic;
+ enum ieee80211_state ostate, nstate;
+ uint32_t reg, imask;
+ int s;
+
+ DPRINTFN(DBG_FN, sc, "\n");
+
+ callout_stop(&sc->sc_calib_to);
+
+ s = splnet();
+
+ ostate = ic->ic_state;
+ nstate = cmd->state;
+ DPRINTFN(DBG_STM, usc, "newstate %s(%d) -> %s(%d)\n",
+ ieee80211_state_name[ostate], ostate,
+ ieee80211_state_name[nstate], nstate);
+
+ if (ostate == IEEE80211_S_RUN) {
+ uint8_t sta_index;
+
+ sta_index = ATHN_NODE(ic->ic_bss)->sta_index;
+ DPRINTFN(DBG_NODES, usc, "removing node %u\n", sta_index);
+ athn_usb_remove_hw_node(usc, &sta_index);
+ }
+
+ switch (nstate) {
+ case IEEE80211_S_INIT:
+ athn_set_led(sc, 0);
+ break;
+ case IEEE80211_S_SCAN:
+ /* Make the LED blink while scanning. */
+ athn_set_led(sc, !sc->sc_led_state);
+ (void)athn_usb_switch_chan(sc, ic->ic_curchan, NULL);
+ if (!usc->usc_dying)
+ callout_schedule(&sc->sc_scan_to, hz / 5);
+ break;
+ case IEEE80211_S_AUTH:
+ athn_set_led(sc, 0);
+ athn_usb_switch_chan(sc, ic->ic_curchan, NULL);
+ break;
+ case IEEE80211_S_ASSOC:
+ break;
+ case IEEE80211_S_RUN:
+ athn_set_led(sc, 1);
+
+ if (ic->ic_opmode == IEEE80211_M_MONITOR)
+ break;
+
+ /* Create node entry for our BSS. */
+ DPRINTFN(DBG_NODES, sc, "create node for AID=0x%x\n",
+ ic->ic_bss->ni_associd);
+ athn_usb_create_node(usc, ic->ic_bss); /* XXX: handle error? */
+
+ athn_set_bss(sc, ic->ic_bss);
+ athn_usb_wmi_cmd(usc, AR_WMI_CMD_DISABLE_INTR);
+#ifndef IEEE80211_STA_ONLY
+ if (ic->ic_opmode == IEEE80211_M_HOSTAP) {
+ athn_set_hostap_timers(sc);
+ /* Enable software beacon alert interrupts. */
+ imask = htobe32(AR_IMR_SWBA);
+ }
+ else
+#endif
+ {
+ athn_set_sta_timers(sc);
+ /* Enable beacon miss interrupts. */
+ imask = htobe32(AR_IMR_BMISS);
+
+ /* Stop receiving beacons from other BSS. */
+ reg = AR_READ(sc, AR_RX_FILTER);
+ reg = (reg & ~AR_RX_FILTER_BEACON) |
+ AR_RX_FILTER_MYBEACON;
+ AR_WRITE(sc, AR_RX_FILTER, reg);
+ AR_WRITE_BARRIER(sc);
+ }
+ athn_usb_wmi_xcmd(usc, AR_WMI_CMD_ENABLE_INTR,
+ &imask, sizeof(imask), NULL);
+ break;
+ }
+ if (!usc->usc_dying)
+ (void)sc->sc_newstate(ic, nstate, cmd->arg);
+ splx(s);
+}
+
+Static void
+athn_usb_newassoc(struct ieee80211_node *ni, int isnew)
+{
+ struct ieee80211com *ic = ni->ni_ic;
+ struct athn_softc *sc = ic->ic_ifp->if_softc;
+ struct athn_usb_softc *usc = ATHN_USB_SOFTC(sc);
+
+ DPRINTFN(DBG_FN, sc, "\n");
+
+ if (ic->ic_opmode != IEEE80211_M_HOSTAP || !isnew)
+ return;
+
+ /* Do it in a process context. */
+ ieee80211_ref_node(ni);
+ athn_usb_do_async(usc, athn_usb_newassoc_cb, &ni, sizeof(ni));
+}
+
+Static void
+athn_usb_newassoc_cb(struct athn_usb_softc *usc, void *arg)
+{
+ struct ieee80211_node *ni = *(void **)arg;
+ int s;
+
+ DPRINTFN(DBG_FN, usc, "\n");
+
+ s = splnet();
+ /* NB: Node may have left before we got scheduled. */
+ if (ni->ni_associd != 0) {
+ DPRINTFN(DBG_NODES, usc, "creating node for AID=0x%x\n",
+ ni->ni_associd);
+ (void)athn_usb_create_node(usc, ni); /* XXX: handle error? */
+ }
+ ieee80211_free_node(ni);
+ splx(s);
+}
+
+#ifdef notyet
+Static int
+athn_usb_ampdu_tx_start(struct ieee80211com *ic, struct ieee80211_node *ni,
+ uint8_t tid)
+{
+ struct athn_softc *sc = ic->ic_ifp->if_softc;
+ struct athn_usb_softc *usc = ATHN_USB_SOFTC(sc);
+ struct athn_node *an = ATHN_NODE(ni);
+ struct athn_usb_aggr_cmd cmd;
+
+ DPRINTFN(DBG_FN, sc, "\n");
+
+ /* Do it in a process context. */
+ cmd.sta_index = an->sta_index;
+ cmd.tid = tid;
+ athn_usb_do_async(usc, athn_usb_ampdu_tx_start_cb, &cmd, sizeof(cmd));
+ return 0;
+}
+
+Static void
+athn_usb_ampdu_tx_start_cb(struct athn_usb_softc *usc, void *arg)
+{
+ struct athn_usb_aggr_cmd *cmd = arg;
+ struct ar_htc_target_aggr aggr;
+
+ DPRINTFN(DBG_FN, usc, "\n");
+
+ memset(&aggr, 0, sizeof(aggr));
+ aggr.sta_index = cmd->sta_index;
+ aggr.tidno = cmd->tid;
+ aggr.aggr_enable = 1;
+ (void)athn_usb_wmi_xcmd(usc, AR_WMI_CMD_TX_AGGR_ENABLE,
+ &aggr, sizeof(aggr), NULL);
+}
+
+Static void
+athn_usb_ampdu_tx_stop(struct ieee80211com *ic, struct ieee80211_node *ni,
+ uint8_t tid)
+{
+ struct athn_softc *sc = ic->ic_ifp->if_softc;
+ struct athn_usb_softc *usc = ATHN_USB_SOFTC(sc);
+ struct athn_node *an = ATHN_NODE(ni);
+ struct athn_usb_aggr_cmd cmd;
+
+ DPRINTFN(DBG_FN, sc, "\n");
+
+ /* Do it in a process context. */
+ cmd.sta_index = an->sta_index;
+ cmd.tid = tid;
+ athn_usb_do_async(usc, athn_usb_ampdu_tx_stop_cb, &cmd, sizeof(cmd));
+}
+
+Static void
+athn_usb_ampdu_tx_stop_cb(struct athn_usb_softc *usc, void *arg)
+{
+ struct athn_usb_aggr_cmd *cmd = arg;
+ struct ar_htc_target_aggr aggr;
+
+ DPRINTFN(DBG_FN, usc, "\n");
+
+ memset(&aggr, 0, sizeof(aggr));
+ aggr.sta_index = cmd->sta_index;
+ aggr.tidno = cmd->tid;
+ aggr.aggr_enable = 0;
+ (void)athn_usb_wmi_xcmd(usc, AR_WMI_CMD_TX_AGGR_ENABLE,
+ &aggr, sizeof(aggr), NULL);
+}
+#endif /* notyet */
+
+Static int
+athn_usb_remove_hw_node(struct athn_usb_softc *usc, uint8_t *sta_idx)
+{
+ int error;
+
+ DPRINTFN(DBG_FN, usc, "\n");
+
+ error = athn_usb_wmi_xcmd(usc, AR_WMI_CMD_NODE_REMOVE,
+ sta_idx, sizeof(*sta_idx), NULL);
+
+ DPRINTFN(DBG_NODES, usc, "node=%u error=%d\n",
+ *sta_idx, error);
+ return error;
+}
+
+Static int
+athn_usb_create_hw_node(struct athn_usb_softc *usc,
+ struct ar_htc_target_sta *sta)
+{
+ int error;
+
+ DPRINTFN(DBG_FN, usc, "\n");
+
+ error = athn_usb_wmi_xcmd(usc, AR_WMI_CMD_NODE_CREATE,
+ sta, sizeof(*sta), NULL);
+
+ DPRINTFN(DBG_NODES, usc, "node=%u error=%d\n",
+ sta->sta_index, error);
+
+ return error;
+}
+
+Static int
+athn_usb_create_node(struct athn_usb_softc *usc, struct ieee80211_node *ni)
+{
+ struct athn_node *an = ATHN_NODE(ni);
+ struct ar_htc_target_sta sta;
+ struct ar_htc_target_rate rate;
+ int error;
+
+ DPRINTFN(DBG_FN | DBG_NODES, usc, "AID=0x%x\n", ni->ni_associd);
+
+ /*
+ * NB: this is called by ic_newstate and (in HOSTAP mode by)
+ * ic_newassoc.
+ *
+ * The firmware has a limit of 8 nodes. In HOSTAP mode, we
+ * limit the AID to < 8 and use that value to index the
+ * firmware node table. Node zero is used for the BSS.
+ *
+ * In STA mode, we simply use node 1 for the BSS.
+ */
+ if (ATHN_SOFTC(usc)->sc_ic.ic_opmode == IEEE80211_M_HOSTAP)
+ an->sta_index = IEEE80211_NODE_AID(ni);
+ else
+ an->sta_index = 1;
+
+ /* Create node entry on target. */
+ memset(&sta, 0, sizeof(sta));
+ IEEE80211_ADDR_COPY(sta.macaddr, ni->ni_macaddr);
+ IEEE80211_ADDR_COPY(sta.bssid, ni->ni_bssid);
+
+ sta.associd = htobe16(ni->ni_associd);
+ sta.valid = 1;
+ sta.sta_index = an->sta_index;
+
+ sta.maxampdu = 0xffff;
+#ifndef IEEE80211_NO_HT
+ if (ni->ni_flags & IEEE80211_NODE_HT)
+ sta.flags |= htobe16(AR_HTC_STA_HT);
+#endif
+ error = athn_usb_create_hw_node(usc, &sta);
+ if (error)
+ return error;
+
+ /* Setup supported rates. */
+ memset(&rate, 0, sizeof(rate));
+ rate.sta_index = sta.sta_index;
+ rate.isnew = 1;
+ rate.lg_rates.rs_nrates = ni->ni_rates.rs_nrates;
+ memcpy(rate.lg_rates.rs_rates, ni->ni_rates.rs_rates,
+ ni->ni_rates.rs_nrates);
+
+#ifndef IEEE80211_NO_HT
+ if (ni->ni_flags & IEEE80211_NODE_HT) {
+ rate.capflags |= htobe32(AR_RC_HT_FLAG);
+#ifdef notyet
+ /* XXX setup HT rates */
+ if (ni->ni_htcaps & IEEE80211_HTCAP_CBW20_40)
+ rate.capflags |= htobe32(AR_RC_40_FLAG);
+ if (ni->ni_htcaps & IEEE80211_HTCAP_SGI40)
+ rate.capflags |= htobe32(AR_RC_SGI_FLAG);
+ if (ni->ni_htcaps & IEEE80211_HTCAP_SGI20)
+ rate.capflags |= htobe32(AR_RC_SGI_FLAG);
+#endif
+ }
+#endif
+ error = athn_usb_wmi_xcmd(usc, AR_WMI_CMD_RC_RATE_UPDATE,
+ &rate, sizeof(rate), NULL);
+ return error;
+}
+
+Static void
+athn_usb_rx_enable(struct athn_softc *sc)
+{
+
+ DPRINTFN(DBG_FN, sc, "\n");
+
+ AR_WRITE(sc, AR_CR, AR_CR_RXE);
+ AR_WRITE_BARRIER(sc);
+}
+
+Static int
+athn_usb_switch_chan(struct athn_softc *sc, struct ieee80211_channel *curchan,
+ struct ieee80211_channel *extchan)
+{
+ struct athn_usb_softc *usc = ATHN_USB_SOFTC(sc);
+ uint16_t mode;
+ int error;
+
+ DPRINTFN(DBG_FN, sc, "\n");
+
+ /* Disable interrupts. */
+ error = athn_usb_wmi_cmd(usc, AR_WMI_CMD_DISABLE_INTR);
+ if (error != 0)
+ goto reset;
+ /* Stop all Tx queues. */
+ error = athn_usb_wmi_cmd(usc, AR_WMI_CMD_DRAIN_TXQ_ALL);
+ if (error != 0)
+ goto reset;
+ /* Stop Rx. */
+ error = athn_usb_wmi_cmd(usc, AR_WMI_CMD_STOP_RECV);
+ if (error != 0)
+ goto reset;
+
+ /* If band or bandwidth changes, we need to do a full reset. */
+ if (curchan->ic_flags != sc->sc_curchan->ic_flags ||
+ ((extchan != NULL) ^ (sc->sc_curchanext != NULL))) {
+ DPRINTFN(DBG_RF, sc, "channel band switch\n");
+ goto reset;
+ }
+
+ error = athn_set_chan(sc, curchan, extchan);
+ if (AR_SREV_9271(sc) && error == 0)
+ ar9271_load_ani(sc);
+ if (error != 0) {
+ reset: /* Error found, try a full reset. */
+ DPRINTFN(DBG_RF, sc, "needs a full reset\n");
+ error = athn_hw_reset(sc, curchan, extchan, 0);
+ if (error != 0) /* Hopeless case. */
+ return error;
+ }
+
+ error = athn_usb_wmi_cmd(usc, AR_WMI_CMD_START_RECV);
+ if (error != 0)
+ return error;
+ athn_rx_start(sc);
+
+ mode = htobe16(IEEE80211_IS_CHAN_2GHZ(curchan) ?
+ AR_HTC_MODE_11NG : AR_HTC_MODE_11NA);
+ error = athn_usb_wmi_xcmd(usc, AR_WMI_CMD_SET_MODE,
+ &mode, sizeof(mode), NULL);
+ if (error != 0)
+ return error;
+
+ /* Re-enable interrupts. */
+ error = athn_usb_wmi_cmd(usc, AR_WMI_CMD_ENABLE_INTR);
+ return error;
+}
+
+#ifdef notyet_edca
+Static void
+athn_usb_updateedca(struct ieee80211com *ic)
+{
+ struct athn_softc *sc = ic->ic_ifp->if_softc;
+ struct athn_usb_softc *usc = ATHN_USB_SOFTC(sc);
+
+ DPRINTFN(DBG_FN, sc, "\n");
+
+ /* Do it in a process context. */
+ athn_usb_do_async(usc, athn_usb_updateedca_cb, NULL, 0);
+}
+
+Static void
+athn_usb_updateedca_cb(struct athn_usb_softc *usc, void *arg)
+{
+ int s;
+
+ DPRINTFN(DBG_FN, usc, "\n");
+
+ s = splnet();
+ athn_updateedca(&usc->usc_sc.sc_ic);
+ splx(s);
+}
+#endif /* notyet_edca */
+
+Static void
+athn_usb_updateslot(struct ifnet *ifp)
+{
+ struct athn_softc *sc = ifp->if_softc;
+ struct athn_usb_softc *usc = ATHN_USB_SOFTC(sc);
+
+ DPRINTFN(DBG_FN, sc, "\n");
+
+ /*
+ * NB: athn_updateslog() needs to be done in a process context
+ * to avoid being called by ieee80211_reset_erp() inside a
+ * spinlock held by ieee80211_free_allnodes().
+ *
+ * XXX: calling this during the athn_attach() causes
+ * usb_insert_transfer() to produce a bunch of "not busy"
+ * messages. Why?
+ */
+ if (usc->usc_athn_attached)
+ athn_usb_do_async(usc, athn_usb_updateslot_cb, NULL, 0);
+}
+
+Static void
+athn_usb_updateslot_cb(struct athn_usb_softc *usc, void *arg)
+{
+ int s;
+
+ DPRINTFN(DBG_FN, usc, "\n");
+
+ s = splnet();
+ athn_updateslot(&usc->usc_sc.sc_if);
+ splx(s);
+}
+
+#ifdef notyet
+Static int
+athn_usb_set_key(struct ieee80211com *ic, struct ieee80211_node *ni,
+ struct ieee80211_key *k)
+{
+ struct athn_softc *sc = ic->ic_ifp->if_softc;
+ struct athn_usb_softc *usc = ATHN_USB_SOFTC(sc);
+ struct ifnet *ifp = &usc->usc_sc.sc_if;
+ struct athn_usb_cmd_key cmd;
+
+ DPRINTFN(DBG_FN, sc, "\n");
+
+ /* Defer setting of WEP keys until interface is brought up. */
+ if (!IS_UP_AND_RUNNING(ifp))
+ return 0;
+
+ /* Do it in a process context. */
+ cmd.ni = (ni != NULL) ? ieee80211_ref_node(ni) : NULL;
+ cmd.key = k;
+ athn_usb_do_async(usc, athn_usb_set_key_cb, &cmd, sizeof(cmd));
+ return 0;
+}
+
+Static void
+athn_usb_set_key_cb(struct athn_usb_softc *usc, void *arg)
+{
+ struct ieee80211com *ic = &usc->usc_sc.sc_ic;
+ struct athn_usb_cmd_key *cmd = arg;
+ int s;
+
+ DPRINTFN(DBG_FN, usc, "\n");
+
+ s = splnet();
+ athn_set_key(ic, cmd->ni, cmd->key);
+ if (cmd->ni != NULL)
+ ieee80211_free_node(cmd->ni);
+ splx(s);
+}
+
+Static void
+athn_usb_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni,
+ struct ieee80211_key *k)
+{
+ struct athn_softc *sc = ic->ic_ifp->if_softc;
+ struct athn_usb_softc *usc = ATHN_USB_SOFTC(sc);
+ struct ifnet *ifp = &usc->usc_sc.sc_if;
+ struct athn_usb_cmd_key cmd;
+
+ DPRINTFN(DBG_FN, sc, "\n");
+
+ if (!(ifp->if_flags & IFF_RUNNING) ||
+ ic->ic_state != IEEE80211_S_RUN)
+ return; /* Nothing to do. */
+
+ /* Do it in a process context. */
+ cmd.ni = (ni != NULL) ? ieee80211_ref_node(ni) : NULL;
+ cmd.key = k;
+ athn_usb_do_async(usc, athn_usb_delete_key_cb, &cmd, sizeof(cmd));
+}
+
+Static void
+athn_usb_delete_key_cb(struct athn_usb_softc *usc, void *arg)
+{
+ struct ieee80211com *ic = &usc->usc_sc.sc_ic;
+ struct athn_usb_cmd_key *cmd = arg;
+ int s;
+
+ DPRINTFN(DBG_FN, usc, "\n");
+
+ s = splnet();
+ athn_delete_key(ic, cmd->ni, cmd->key);
+ if (cmd->ni != NULL)
+ ieee80211_free_node(cmd->ni);
+ splx(s);
+}
+#endif /* notyet */
+
+#ifndef IEEE80211_STA_ONLY
+Static void
+athn_usb_bcneof(usbd_xfer_handle xfer, usbd_private_handle priv,
+ usbd_status status)
+{
+ struct athn_usb_tx_data *data = priv;
+ struct athn_usb_softc *usc = data->sc;
+
+ DPRINTFN(DBG_FN, usc, "\n");
+
+ if (__predict_false(status == USBD_STALLED))
+ usbd_clear_endpoint_stall_async(usc->usc_tx_data_pipe);
+ usc->usc_tx_bcn = data;
+}
+
+/*
+ * Process Software Beacon Alert interrupts.
+ */
+Static void
+athn_usb_swba(struct athn_usb_softc *usc)
+{
+ struct athn_softc *sc = &usc->usc_sc;
+ struct ieee80211com *ic = &sc->sc_ic;
+ struct athn_usb_tx_data *data;
+ struct ieee80211_frame *wh;
+ struct ieee80211_beacon_offsets bo;
+ struct ar_stream_hdr *hdr;
+ struct ar_htc_frame_hdr *htc;
+ struct ar_tx_bcn *bcn;
+ struct mbuf *m;
+ int error;
+
+ if (usc->usc_dying)
+ return;
+
+ DPRINTFN(DBG_FN, sc, "\n");
+
+ if (ic->ic_dtim_count == 0)
+ ic->ic_dtim_count = ic->ic_dtim_period - 1;
+ else
+ ic->ic_dtim_count--;
+
+ /* Make sure previous beacon has been sent. */
+ if (usc->usc_tx_bcn == NULL)
+ return;
+ data = usc->usc_tx_bcn;
+
+ /* Get new beacon. */
+#ifdef ATHN_DEBUG
+ memset(&bo, 0, sizeof(bo));
+#endif
+ m = ieee80211_beacon_alloc(ic, ic->ic_bss, &bo);
+ if (__predict_false(m == NULL))
+ return;
+ /* Assign sequence number. */
+ /* XXX: use non-QoS tid? */
+ wh = mtod(m, struct ieee80211_frame *);
+ *(uint16_t *)&wh->i_seq[0] =
+ htole16(ic->ic_bss->ni_txseqs[0] << IEEE80211_SEQ_SEQ_SHIFT);
+ ic->ic_bss->ni_txseqs[0]++;
+
+ hdr = (struct ar_stream_hdr *)data->buf;
+ hdr->tag = htole16(AR_USB_TX_STREAM_TAG);
+ hdr->len = htole16(sizeof(*htc) + sizeof(*bcn) + m->m_pkthdr.len);
+
+ htc = (struct ar_htc_frame_hdr *)&hdr[1];
+ memset(htc, 0, sizeof(*htc));
+ htc->endpoint_id = usc->usc_ep_bcn;
+ htc->payload_len = htobe16(sizeof(*bcn) + m->m_pkthdr.len);
+
+ bcn = (struct ar_tx_bcn *)&htc[1];
+ memset(bcn, 0, sizeof(*bcn));
+ bcn->vif_idx = 0;
+
+ m_copydata(m, 0, m->m_pkthdr.len, (void *)&bcn[1]);
+
+ usbd_setup_xfer(data->xfer, usc->usc_tx_data_pipe, data, data->buf,
+ sizeof(*hdr) + sizeof(*htc) + sizeof(*bcn) + m->m_pkthdr.len,
+ USBD_SHORT_XFER_OK | USBD_NO_COPY, ATHN_USB_TX_TIMEOUT,
+ athn_usb_bcneof);
+
+ m_freem(m);
+ usc->usc_tx_bcn = NULL;
+ error = usbd_transfer(data->xfer);
+ if (__predict_false(error != USBD_IN_PROGRESS && error != 0))
+ usc->usc_tx_bcn = data;
+}
+#endif
+
+Static void
+athn_usb_rx_wmi_ctrl(struct athn_usb_softc *usc, uint8_t *buf, int len)
+{
+#ifdef ATHN_DEBUG
+ struct ar_wmi_evt_txrate *txrate;
+#endif
+ struct ar_wmi_cmd_hdr *wmi;
+ uint16_t cmd_id;
+
+ if (usc->usc_dying)
+ return;
+
+ DPRINTFN(DBG_FN, usc, "\n");
+
+ if (__predict_false(len < (int)sizeof(*wmi)))
+ return;
+ wmi = (struct ar_wmi_cmd_hdr *)buf;
+ cmd_id = be16toh(wmi->cmd_id);
+
+ if (!(cmd_id & AR_WMI_EVT_FLAG)) {
+ if (usc->usc_wait_cmd_id != cmd_id)
+ return; /* Unexpected reply. */
+ if (usc->usc_obuf != NULL) {
+ /* Copy answer into caller supplied buffer. */
+ memcpy(usc->usc_obuf, &wmi[1], len - sizeof(*wmi));
+ }
+ /* Notify caller of completion. */
+ usc->usc_wait_cmd_id = 0;
+ wakeup(&usc->usc_wait_cmd_id);
+ return;
+ }
+ /*
+ * XXX: the Linux 2.6 and 3.7.4 kernels differ on the event numbers!
+ * See the alternate defines in if_athn_usb.h.
+ */
+ switch (cmd_id & 0xfff) {
+#ifndef IEEE80211_STA_ONLY
+ case AR_WMI_EVT_SWBA:
+ athn_usb_swba(usc);
+ break;
+#endif
+ case AR_WMI_EVT_FATAL:
+ aprint_error_dev(usc->usc_dev, "fatal firmware error\n");
+ break;
+ case AR_WMI_EVT_TXRATE:
+#ifdef ATHN_DEBUG
+ txrate = (struct ar_wmi_evt_txrate *)&wmi[1];
+ DPRINTFN(DBG_TX, usc, "txrate=%d\n", be32toh(txrate->txrate));
+#endif
+ break;
+ default:
+ DPRINTFN(DBG_TX, usc, "WMI event 0x%x (%d) ignored\n", cmd_id, cmd_id);
+ break;
+ }
+}
+
+Static void
+athn_usb_intr(usbd_xfer_handle xfer, usbd_private_handle priv,
+ usbd_status status)
+{
+ struct athn_usb_softc *usc = priv;
+ struct ar_htc_frame_hdr *htc;
+ struct ar_htc_msg_hdr *msg;
+ uint8_t *buf = usc->usc_ibuf;
+ uint16_t msg_id;
+ int len;
+
+ if (usc->usc_dying)
+ return;
+
+ DPRINTFN(DBG_FN, usc, "\n");
+
+ if (__predict_false(status != USBD_NORMAL_COMPLETION)) {
+ DPRINTFN(DBG_INTR, usc, "intr status=%d\n", status);
+ if (status == USBD_STALLED)
+ usbd_clear_endpoint_stall_async(usc->usc_rx_intr_pipe);
+ return;
+ }
+ usbd_get_xfer_status(xfer, NULL, NULL, &len, NULL);
+
+ /* Skip watchdog pattern if present. */
+ if (len >= 4 && *(uint32_t *)buf == htobe32(0x00c60000)) {
+ buf += 4;
+ len -= 4;
+ }
+ if (__predict_false(len < (int)sizeof(*htc)))
+ return;
+ htc = (struct ar_htc_frame_hdr *)buf;
+ /* Skip HTC header. */
+ buf += sizeof(*htc);
+ len -= sizeof(*htc);
+
+ if (htc->endpoint_id != 0) {
+ if (__predict_false(htc->endpoint_id != usc->usc_ep_ctrl))
+ return;
+ /* Remove trailer if present. */
+ if (htc->flags & AR_HTC_FLAG_TRAILER) {
+ if (__predict_false(len < htc->control[0]))
+ return;
+ len -= htc->control[0];
+ }
+ athn_usb_rx_wmi_ctrl(usc, buf, len);
+ return;
+ }
+
+ /*
+ * Endpoint 0 carries HTC messages.
+ */
+ if (__predict_false(len < (int)sizeof(*msg)))
+ return;
+ msg = (struct ar_htc_msg_hdr *)buf;
+ msg_id = be16toh(msg->msg_id);
+ DPRINTFN(DBG_RX, usc, "Rx HTC message %d\n", msg_id);
+ switch (msg_id) {
+ case AR_HTC_MSG_READY:
+ case AR_HTC_MSG_CONF_PIPE_RSP:
+ if (usc->usc_wait_msg_id != msg_id)
+ break;
+ usc->usc_wait_msg_id = 0;
+ wakeup(&usc->usc_wait_msg_id);
+ break;
+ case AR_HTC_MSG_CONN_SVC_RSP:
+ if (usc->usc_wait_msg_id != msg_id)
+ break;
+ if (usc->usc_msg_conn_svc_rsp != NULL) {
+ memcpy(usc->usc_msg_conn_svc_rsp, &msg[1],
+ sizeof(*usc->usc_msg_conn_svc_rsp));
+ }
+ usc->usc_wait_msg_id = 0;
+ wakeup(&usc->usc_wait_msg_id);
+ break;
+ default:
+ DPRINTFN(DBG_RX, usc, "HTC message %d ignored\n", msg_id);
+ break;
+ }
+}
+
+Static void
+athn_usb_rx_radiotap(struct athn_softc *sc, struct mbuf *m,
+ struct ar_rx_status *rs)
+{
+ struct athn_rx_radiotap_header *tap = &sc->sc_rxtap;
+ struct ieee80211com *ic = &sc->sc_ic;
+ uint8_t rate;
+
+ DPRINTFN(DBG_FN, sc, "\n");
+
+ tap->wr_flags = IEEE80211_RADIOTAP_F_FCS;
+ tap->wr_tsft = htole64(be64toh(rs->rs_tstamp));
+ tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq);
+ tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags);
+ tap->wr_dbm_antsignal = rs->rs_rssi;
+ /* XXX noise. */
+ tap->wr_antenna = rs->rs_antenna;
+ rate = rs->rs_rate;
+ if (rate & 0x80) { /* HT. */
+ /* Bit 7 set means HT MCS instead of rate. */
+ tap->wr_rate = rate;
+ if (!(rs->rs_flags & AR_RXS_FLAG_GI))
+ tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTGI;
+ }
+ else if (rate & 0x10) { /* CCK. */
+ if (rate & 0x04)
+ tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
+ switch (rate & ~0x14) {
+ case 0xb: tap->wr_rate = 2; break;
+ case 0xa: tap->wr_rate = 4; break;
+ case 0x9: tap->wr_rate = 11; break;
+ case 0x8: tap->wr_rate = 22; break;
+ default: tap->wr_rate = 0; break;
+ }
+ }
+ else { /* OFDM. */
+ switch (rate) {
+ case 0xb: tap->wr_rate = 12; break;
+ case 0xf: tap->wr_rate = 18; break;
+ case 0xa: tap->wr_rate = 24; break;
+ case 0xe: tap->wr_rate = 36; break;
+ case 0x9: tap->wr_rate = 48; break;
+ case 0xd: tap->wr_rate = 72; break;
+ case 0x8: tap->wr_rate = 96; break;
+ case 0xc: tap->wr_rate = 108; break;
+ default: tap->wr_rate = 0; break;
+ }
+ }
+ bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m);
+}
+
+Static void
+athn_usb_rx_frame(struct athn_usb_softc *usc, struct mbuf *m)
+{
+ struct athn_softc *sc = &usc->usc_sc;
+ struct ieee80211com *ic = &sc->sc_ic;
+ struct ifnet *ifp = &sc->sc_if;
+ struct ieee80211_frame *wh;
+ struct ieee80211_node *ni;
+ struct ar_htc_frame_hdr *htc;
+ struct ar_rx_status *rs;
+ uint16_t datalen;
+ int s;
+
+ DPRINTFN(DBG_FN, sc, "\n");
+
+ if (__predict_false(m->m_len < (int)sizeof(*htc)))
+ goto skip;
+ htc = mtod(m, struct ar_htc_frame_hdr *);
+ if (__predict_false(htc->endpoint_id == 0)) {
+ DPRINTFN(DBG_RX, sc, "bad endpoint %d\n", htc->endpoint_id);
+ goto skip;
+ }
+ if (htc->flags & AR_HTC_FLAG_TRAILER) {
+ if (m->m_len < htc->control[0])
+ goto skip;
+ m_adj(m, -(int)htc->control[0]);
+ }
+ m_adj(m, sizeof(*htc)); /* Strip HTC header. */
+
+ if (__predict_false(m->m_len < (int)sizeof(*rs)))
+ goto skip;
+ rs = mtod(m, struct ar_rx_status *);
+
+ /* Make sure that payload fits. */
+ datalen = be16toh(rs->rs_datalen);
+ if (__predict_false(m->m_len < (int)sizeof(*rs) + datalen))
+ goto skip;
+
+ /* Ignore runt frames. Let ACKs be seen by bpf */
+ if (__predict_false(datalen <
+ sizeof(struct ieee80211_frame_ack) + IEEE80211_CRC_LEN))
+ goto skip;
+
+ m_adj(m, sizeof(*rs)); /* Strip Rx status. */
+ m->m_pkthdr.rcvif = ifp;
+
+ s = splnet();
+
+ /* Grab a reference to the source node. */
+ wh = mtod(m, struct ieee80211_frame *);
+ ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh);
+
+ /* Remove any HW padding after the 802.11 header. */
+ if (!(wh->i_fc[0] & IEEE80211_FC0_TYPE_CTL)) {
+ u_int hdrlen = ieee80211_anyhdrsize(wh);
+ if (hdrlen & 3) {
+ ovbcopy(wh, (uint8_t *)wh + 2, hdrlen);
+ m_adj(m, 2);
+ }
+ }
+ if (__predict_false(sc->sc_drvbpf != NULL))
+ athn_usb_rx_radiotap(sc, m, rs);
+
+ /* Trim 802.11 FCS after radiotap. */
+ m_adj(m, -IEEE80211_CRC_LEN);
+
+ /* Send the frame to the 802.11 layer. */
+ ieee80211_input(ic, m, ni, rs->rs_rssi + AR_USB_DEFAULT_NF, 0);
+
+ /* Node is no longer needed. */
+ ieee80211_free_node(ni);
+ splx(s);
+ return;
+ skip:
+ m_freem(m);
+}
+
+Static void
+athn_usb_rxeof(usbd_xfer_handle xfer, usbd_private_handle priv,
+ usbd_status status)
+{
+ struct athn_usb_rx_data *data = priv;
+ struct athn_usb_softc *usc = data->sc;
+ struct athn_usb_rx_stream *stream = &usc->usc_rx_stream;
+ uint8_t *buf = data->buf;
+ struct ar_stream_hdr *hdr;
+ struct mbuf *m;
+ uint16_t pktlen;
+ int off, len;
+
+ if (usc->usc_dying)
+ return;
+
+ DPRINTFN(DBG_FN, usc, "\n");
+
+ if (__predict_false(status != USBD_NORMAL_COMPLETION)) {
+ DPRINTFN(DBG_RX, usc, "RX status=%d\n", status);
+ if (status == USBD_STALLED)
+ usbd_clear_endpoint_stall_async(usc->usc_rx_data_pipe);
+ if (status != USBD_CANCELLED)
+ goto resubmit;
+ return;
+ }
+ usbd_get_xfer_status(xfer, NULL, NULL, &len, NULL);
+
+ if (stream->left > 0) {
+ if (len >= stream->left) {
+ /* We have all our pktlen bytes now. */
+ if (__predict_true(stream->m != NULL)) {
+ memcpy(mtod(stream->m, uint8_t *) +
+ stream->moff, buf, stream->left);
+ athn_usb_rx_frame(usc, stream->m);
+ stream->m = NULL;
+ }
+ /* Next header is 32-bit aligned. */
+ off = (stream->left + 3) & ~3;
+ buf += off;
+ len -= off;
+ stream->left = 0;
+ }
+ else {
+ /* Still need more bytes, save what we have. */
+ if (__predict_true(stream->m != NULL)) {
+ memcpy(mtod(stream->m, uint8_t *) +
+ stream->moff, buf, len);
+ stream->moff += len;
+ }
+ stream->left -= len;
+ goto resubmit;
+ }
+ }
+ KASSERT(stream->left == 0);
+ while (len >= (int)sizeof(*hdr)) {
+ hdr = (struct ar_stream_hdr *)buf;
+ if (hdr->tag != htole16(AR_USB_RX_STREAM_TAG)) {
+ DPRINTFN(DBG_RX, usc, "invalid tag 0x%x\n", hdr->tag);
+ break;
+ }
+ pktlen = le16toh(hdr->len);
+ buf += sizeof(*hdr);
+ len -= sizeof(*hdr);
+
+ if (__predict_true(pktlen <= MCLBYTES)) {
+ /* Allocate an mbuf to store the next pktlen bytes. */
+ MGETHDR(m, M_DONTWAIT, MT_DATA);
+ if (__predict_true(m != NULL)) {
+ m->m_pkthdr.len = m->m_len = pktlen;
+ if (pktlen > MHLEN) {
+ MCLGET(m, M_DONTWAIT);
+ if (!(m->m_flags & M_EXT)) {
+ m_free(m);
+ m = NULL;
+ }
+ }
+ }
+ }
+ else /* Drop frames larger than MCLBYTES. */
+ m = NULL;
+ /*
+ * NB: m can be NULL, in which case the next pktlen bytes
+ * will be discarded from the Rx stream.
+ */
+ if (pktlen > len) {
+ /* Need more bytes, save what we have. */
+ stream->m = m; /* NB: m can be NULL. */
+ if (__predict_true(stream->m != NULL)) {
+ memcpy(mtod(stream->m, uint8_t *), buf, len);
+ stream->moff = len;
+ }
+ stream->left = pktlen - len;
+ goto resubmit;
+ }
+ if (__predict_true(m != NULL)) {
+ /* We have all the pktlen bytes in this xfer. */
+ memcpy(mtod(m, uint8_t *), buf, pktlen);
+ athn_usb_rx_frame(usc, m);
+ }
+
+ /* Next header is 32-bit aligned. */
+ off = (pktlen + 3) & ~3;
+ buf += off;
+ len -= off;
+ }
+
+ resubmit:
+ /* Setup a new transfer. */
+ usbd_setup_xfer(xfer, usc->usc_rx_data_pipe, data, data->buf,
+ ATHN_USB_RXBUFSZ, USBD_SHORT_XFER_OK | USBD_NO_COPY,
+ USBD_NO_TIMEOUT, athn_usb_rxeof);
+ (void)usbd_transfer(xfer);
+}
+
+Static void
+athn_usb_txeof(usbd_xfer_handle xfer, usbd_private_handle priv,
+ usbd_status status)
+{
+ struct athn_usb_tx_data *data = priv;
+ struct athn_usb_softc *usc = data->sc;
+ struct athn_softc *sc = &usc->usc_sc;
+ struct ifnet *ifp = &sc->sc_if;
+ int s;
+
+ if (usc->usc_dying)
+ return;
+
+ DPRINTFN(DBG_FN, usc, "\n");
+
+ s = splnet();
+ /* Put this Tx buffer back to our free list. */
+ mutex_enter(&usc->usc_tx_mtx);
+ TAILQ_INSERT_TAIL(&usc->usc_tx_free_list, data, next);
+ mutex_exit(&usc->usc_tx_mtx);
+
+ if (__predict_false(status != USBD_NORMAL_COMPLETION)) {
+ DPRINTFN(DBG_TX, sc, "TX status=%d\n", status);
+ if (status == USBD_STALLED)
+ usbd_clear_endpoint_stall_async(usc->usc_tx_data_pipe);
+ ifp->if_oerrors++;
+ splx(s);
+ /* XXX Why return? */
+ return;
+ }
+ sc->sc_tx_timer = 0;
+ ifp->if_opackets++;
+
+ /* We just released a Tx buffer, notify Tx. */
+ if (ifp->if_flags & IFF_OACTIVE) {
+ ifp->if_flags &= ~IFF_OACTIVE;
+ ifp->if_start(ifp);
+ }
+ splx(s);
+}
+
+Static int
+athn_usb_tx(struct athn_softc *sc, struct mbuf *m, struct ieee80211_node *ni,
+ struct athn_usb_tx_data *data)
+{
+ struct athn_usb_softc *usc = ATHN_USB_SOFTC(sc);
+ struct athn_node *an = ATHN_NODE(ni);
+ struct ieee80211com *ic = &sc->sc_ic;
+ struct ieee80211_frame *wh;
+ struct ieee80211_key *k = NULL;
+ struct ar_stream_hdr *hdr;
+ struct ar_htc_frame_hdr *htc;
+ struct ar_tx_frame *txf;
+ struct ar_tx_mgmt *txm;
+ uint8_t *frm;
+ uint8_t sta_index, qid, tid;
+ int error, s, xferlen;
+
+ DPRINTFN(DBG_FN, sc, "\n");
+
+ wh = mtod(m, struct ieee80211_frame *);
+ if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) {
+ k = ieee80211_crypto_encap(ic, ni, m);
+ if (k == NULL)
+ return ENOBUFS;
+
+ /* packet header may have moved, reset our local pointer */
+ wh = mtod(m, struct ieee80211_frame *);
+ }
+#ifdef notyet_edca
+ if (ieee80211_has_qos(wh)) {
+ uint16_t qos;
+
+ qos = ieee80211_get_qos(wh);
+ tid = qos & IEEE80211_QOS_TID;
+ qid = ieee80211_up_to_ac(ic, tid);
+ }
+ else
+#endif /* notyet_edca */
+ {
+ tid = 0;
+ qid = EDCA_AC_BE;
+ }
+
+ /* XXX Change radiotap Tx header for USB (no txrate). */
+ if (__predict_false(sc->sc_drvbpf != NULL)) {
+ struct athn_tx_radiotap_header *tap = &sc->sc_txtap;
+
+ tap->wt_flags = 0;
+ tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq);
+ tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags);
+ if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED)
+ tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP;
+
+ bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m);
+ }
+ sta_index = an->sta_index;
+
+ /* NB: We don't take advantage of USB Tx stream mode for now. */
+ hdr = (struct ar_stream_hdr *)data->buf;
+ hdr->tag = htole16(AR_USB_TX_STREAM_TAG);
+
+ htc = (struct ar_htc_frame_hdr *)&hdr[1];
+ memset(htc, 0, sizeof(*htc));
+ if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) ==
+ IEEE80211_FC0_TYPE_DATA) {
+ htc->endpoint_id = usc->usc_ep_data[qid];
+
+ txf = (struct ar_tx_frame *)&htc[1];
+ memset(txf, 0, sizeof(*txf));
+ txf->data_type = AR_HTC_NORMAL;
+ txf->node_idx = sta_index;
+ txf->vif_idx = 0;
+ txf->tid = tid;
+ if (m->m_pkthdr.len + IEEE80211_CRC_LEN > ic->ic_rtsthreshold)
+ txf->flags |= htobe32(AR_HTC_TX_RTSCTS);
+ else if (ic->ic_flags & IEEE80211_F_USEPROT) {
+ if (ic->ic_protmode == IEEE80211_PROT_CTSONLY)
+ txf->flags |= htobe32(AR_HTC_TX_CTSONLY);
+ else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS)
+ txf->flags |= htobe32(AR_HTC_TX_RTSCTS);
+ }
+ txf->key_idx = 0xff;
+ frm = (uint8_t *)&txf[1];
+ }
+ else {
+ htc->endpoint_id = usc->usc_ep_mgmt;
+
+ txm = (struct ar_tx_mgmt *)&htc[1];
+ memset(txm, 0, sizeof(*txm));
+ txm->node_idx = sta_index;
+ txm->vif_idx = 0;
+ txm->key_idx = 0xff;
+ frm = (uint8_t *)&txm[1];
+ }
+ /* Copy payload. */
+ m_copydata(m, 0, m->m_pkthdr.len, (void *)frm);
+ frm += m->m_pkthdr.len;
+
+ /* Finalize headers. */
+ htc->payload_len = htobe16(frm - (uint8_t *)&htc[1]);
+ hdr->len = htole16(frm - (uint8_t *)&hdr[1]);
+ xferlen = frm - data->buf;
+
+ s = splnet();
+ usbd_setup_xfer(data->xfer, usc->usc_tx_data_pipe, data, data->buf,
+ xferlen, USBD_FORCE_SHORT_XFER | USBD_NO_COPY, ATHN_USB_TX_TIMEOUT,
+ athn_usb_txeof);
+ error = usbd_transfer(data->xfer);
+ if (__predict_false(error != USBD_IN_PROGRESS && error != 0)) {
+ splx(s);
+ return error;
+ }
+ splx(s);
+ return 0;
+}
+
+Static void
+athn_usb_start(struct ifnet *ifp)
+{
+ struct athn_softc *sc = ifp->if_softc;
+ struct athn_usb_softc *usc = ATHN_USB_SOFTC(sc);
+ struct ieee80211com *ic = &sc->sc_ic;
+ struct athn_usb_tx_data *data;
+ struct ether_header *eh;
+ struct ieee80211_node *ni;
+ struct mbuf *m;
+
+ if (usc->usc_dying)
+ return;
+
+ DPRINTFN(DBG_FN, sc, "\n");
+
+ if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
+ return;
+
+ data = NULL;
+ for (;;) {
+ mutex_enter(&usc->usc_tx_mtx);
+ if (data == NULL && !TAILQ_EMPTY(&usc->usc_tx_free_list)) {
+ data = TAILQ_FIRST(&usc->usc_tx_free_list);
+ TAILQ_REMOVE(&usc->usc_tx_free_list, data, next);
+ }
+ mutex_exit(&usc->usc_tx_mtx);
+
+ if (data == NULL) {
+ ifp->if_flags |= IFF_OACTIVE;
+ return;
+ }
+
+ /* Send pending management frames first. */
+ IF_DEQUEUE(&ic->ic_mgtq, m);
+ if (m != NULL) {
+ ni = (void *)m->m_pkthdr.rcvif;
+ m->m_pkthdr.rcvif = NULL;
+ goto sendit;
+ }
+ if (ic->ic_state != IEEE80211_S_RUN)
+ break;
+
+ /* Encapsulate and send data frames. */
+ IFQ_DEQUEUE(&ifp->if_snd, m);
+ if (m == NULL)
+ break;
+
+ if (m->m_len < (int)sizeof(*eh) &&
+ (m = m_pullup(m, sizeof(*eh))) == NULL) {
+ ifp->if_oerrors++;
+ continue;
+ }
+ eh = mtod(m, struct ether_header *);
+ ni = ieee80211_find_txnode(ic, eh->ether_dhost);
+ if (ni == NULL) {
+ m_freem(m);
+ ifp->if_oerrors++;
+ continue;
+ }
+
+ bpf_mtap(ifp, m);
+
+ if ((m = ieee80211_encap(ic, m, ni)) == NULL) {
+ ieee80211_free_node(ni);
+ ifp->if_oerrors++;
+ continue;
+ }
+ sendit:
+ bpf_mtap3(ic->ic_rawbpf, m);
+
+ if (athn_usb_tx(sc, m, ni, data) != 0) {
+ m_free(m);
+ ieee80211_free_node(ni);
+ ifp->if_oerrors++;
+ continue;
+ }
+ data = NULL;
+ m_free(m);
+ ieee80211_free_node(ni);
+ sc->sc_tx_timer = 5;
+ ifp->if_timer = 1;
+ }
+
+ /* Return the Tx buffer to the free list */
+ mutex_enter(&usc->usc_tx_mtx);
+ TAILQ_INSERT_TAIL(&usc->usc_tx_free_list, data, next);
+ mutex_exit(&usc->usc_tx_mtx);
+}
+
+Static void
+athn_usb_watchdog(struct ifnet *ifp)
+{
+ struct athn_softc *sc = ifp->if_softc;
+
+ DPRINTFN(DBG_FN, sc, "\n");
+
+ ifp->if_timer = 0;
+
+ if (sc->sc_tx_timer > 0) {
+ if (--sc->sc_tx_timer == 0) {
+ aprint_error_dev(sc->sc_dev, "device timeout\n");
+ /* athn_usb_init(ifp); XXX needs a process context! */
+ ifp->if_oerrors++;
+ return;
+ }
+ ifp->if_timer = 1;
+ }
+ ieee80211_watchdog(&sc->sc_ic);
+}
+
+Static int
+athn_usb_ioctl(struct ifnet *ifp, u_long cmd, void *data)
+{
+ struct athn_softc *sc = ifp->if_softc;
+ struct athn_usb_softc *usc = ATHN_USB_SOFTC(sc);
+ struct ieee80211com *ic = &sc->sc_ic;
+ int s, error = 0;
+
+ if (usc->usc_dying)
+ return EIO;
+
+ DPRINTFN(DBG_FN, sc, "cmd=0x%08lx\n", cmd);
+
+ s = splnet();
+
+ switch (cmd) {
+ case SIOCSIFFLAGS:
+ if ((error = ifioctl_common(ifp, cmd, data)) != 0)
+ break;
+
+ switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) {
+ case IFF_UP | IFF_RUNNING:
+ break;
+ case IFF_UP:
+ error = athn_usb_init(ifp);
+ break;
+ case IFF_RUNNING:
+ athn_usb_stop(ifp);
+ break;
+ case 0:
+ default:
+ break;
+ }
+ break;
+
+ case SIOCADDMULTI:
+ case SIOCDELMULTI:
+ if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) {
+ /* setup multicast filter, etc */
+ error = 0;
+ }
+ break;
+
+ case SIOCS80211CHANNEL:
+ error = ieee80211_ioctl(ic, cmd, data);
+ if (error == ENETRESET &&
+ ic->ic_opmode == IEEE80211_M_MONITOR) {
+ if (IS_UP_AND_RUNNING(ifp))
+ athn_usb_switch_chan(sc, ic->ic_curchan, NULL);
+ error = 0;
+ }
+ break;
+
+ default:
+ error = ieee80211_ioctl(ic, cmd, data);
+ break;
+ }
+ if (error == ENETRESET) {
+ error = 0;
+ if (IS_UP_AND_RUNNING(ifp) &&
+ ic->ic_roaming != IEEE80211_ROAMING_MANUAL) {
+ athn_usb_stop(ifp);
+ error = athn_usb_init(ifp);
+ }
+ }
+ splx(s);
+ return error;
+}
+
+Static int
+athn_usb_init(struct ifnet *ifp)
+{
+ struct athn_softc *sc = ifp->if_softc;
+ struct athn_usb_softc *usc = ATHN_USB_SOFTC(sc);
+ struct athn_ops *ops = &sc->sc_ops;
+ struct ieee80211com *ic = &sc->sc_ic;
+ struct ieee80211_channel *curchan, *extchan;
+ struct athn_usb_rx_data *data;
+ struct ar_htc_target_vif hvif;
+ struct ar_htc_target_sta sta;
+ struct ar_htc_cap_target hic;
+ uint16_t mode;
+ size_t i;
+ int error;
+
+ if (usc->usc_dying)
+ return USBD_CANCELLED;
+
+ DPRINTFN(DBG_FN, sc, "\n");
+
+ /* Init host async commands ring. */
+ mutex_spin_enter(&usc->usc_task_mtx);
+ usc->usc_cmdq.cur = usc->usc_cmdq.next = usc->usc_cmdq.queued = 0;
+ mutex_spin_exit(&usc->usc_task_mtx);
+
+ /* Allocate Tx/Rx buffers. */
+ error = athn_usb_alloc_rx_list(usc);
+ if (error != 0)
+ goto fail;
+ error = athn_usb_alloc_tx_list(usc);
+ if (error != 0)
+ goto fail;
+ /* Steal one buffer for beacons. */
+ mutex_enter(&usc->usc_tx_mtx);
+ usc->usc_tx_bcn = TAILQ_FIRST(&usc->usc_tx_free_list);
+ TAILQ_REMOVE(&usc->usc_tx_free_list, usc->usc_tx_bcn, next);
+ mutex_exit(&usc->usc_tx_mtx);
+
+ curchan = ic->ic_curchan;
+ extchan = NULL;
+
+ /* In case a new MAC address has been configured. */
+ IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl));
+
+ error = athn_set_power_awake(sc);
+ if (error != 0)
+ goto fail;
+
+ error = athn_usb_wmi_cmd(usc, AR_WMI_CMD_FLUSH_RECV);
+ if (error != 0)
+ goto fail;
+
+ error = athn_hw_reset(sc, curchan, extchan, 1);
+ if (error != 0)
+ goto fail;
+
+ ops->set_txpower(sc, curchan, extchan);
+
+ mode = htobe16(IEEE80211_IS_CHAN_2GHZ(curchan) ?
+ AR_HTC_MODE_11NG : AR_HTC_MODE_11NA);
+ error = athn_usb_wmi_xcmd(usc, AR_WMI_CMD_SET_MODE,
+ &mode, sizeof(mode), NULL);
+ if (error != 0)
+ goto fail;
+
+ error = athn_usb_wmi_cmd(usc, AR_WMI_CMD_ATH_INIT);
+ if (error != 0)
+ goto fail;
+
+ error = athn_usb_wmi_cmd(usc, AR_WMI_CMD_START_RECV);
+ if (error != 0)
+ goto fail;
+
+ athn_rx_start(sc);
+
+ /* Create main interface on target. */
+ memset(&hvif, 0, sizeof(hvif));
+ hvif.index = 0;
+ IEEE80211_ADDR_COPY(hvif.myaddr, ic->ic_myaddr);
+ switch (ic->ic_opmode) {
+ case IEEE80211_M_STA:
+ hvif.opmode = htobe32(AR_HTC_M_STA);
+ break;
+ case IEEE80211_M_MONITOR:
+ hvif.opmode = htobe32(AR_HTC_M_MONITOR);
+ break;
+#ifndef IEEE80211_STA_ONLY
+ case IEEE80211_M_IBSS:
+ hvif.opmode = htobe32(AR_HTC_M_IBSS);
+ break;
+ case IEEE80211_M_AHDEMO:
+ hvif.opmode = htobe32(AR_HTC_M_AHDEMO);
+ break;
+ case IEEE80211_M_HOSTAP:
+ hvif.opmode = htobe32(AR_HTC_M_HOSTAP);
+ break;
+#endif
+ }
+ hvif.rtsthreshold = htobe16(ic->ic_rtsthreshold);
+ DPRINTFN(DBG_INIT, sc, "creating VAP\n");
+ error = athn_usb_wmi_xcmd(usc, AR_WMI_CMD_VAP_CREATE,
+ &hvif, sizeof(hvif), NULL);
+ if (error != 0)
+ goto fail;
+
+ /* Create a fake node to send management frames before assoc. */
+ memset(&sta, 0, sizeof(sta));
+ IEEE80211_ADDR_COPY(sta.macaddr, ic->ic_myaddr);
+ sta.sta_index = 0;
+ sta.is_vif_sta = 1;
+ sta.vif_index = hvif.index;
+ sta.maxampdu = 0xffff;
+
+ DPRINTFN(DBG_INIT | DBG_NODES, sc, "creating default node %u\n",
+ sta.sta_index);
+ error = athn_usb_create_hw_node(usc, &sta);
+ if (error != 0)
+ goto fail;
+
+ /* Update target capabilities. */
+ memset(&hic, 0, sizeof(hic));
+ hic.flags = htobe32(0x400c2400);
+ hic.flags_ext = htobe32(0x00106080);
+ hic.ampdu_limit = htobe32(0x0000ffff);
+ hic.ampdu_subframes = 20;
+ hic.protmode = 1; /* XXX */
+ hic.lg_txchainmask = sc->sc_txchainmask;
+ hic.ht_txchainmask = sc->sc_txchainmask;
+ DPRINTFN(DBG_INIT, sc, "updating target configuration\n");
+ error = athn_usb_wmi_xcmd(usc, AR_WMI_CMD_TARGET_IC_UPDATE,
+ &hic, sizeof(hic), NULL);
+ if (error != 0)
+ goto fail;
+
+ /* Queue Rx xfers. */
+ for (i = 0; i < ATHN_USB_RX_LIST_COUNT; i++) {
+ data = &usc->usc_rx_data[i];
+
+ usbd_setup_xfer(data->xfer, usc->usc_rx_data_pipe, data, data->buf,
+ ATHN_USB_RXBUFSZ, USBD_SHORT_XFER_OK | USBD_NO_COPY,
+ USBD_NO_TIMEOUT, athn_usb_rxeof);
+ error = usbd_transfer(data->xfer);
+ if (error != 0 && error != USBD_IN_PROGRESS)
+ goto fail;
+ }
+ /* We're ready to go. */
+ ifp->if_flags &= ~IFF_OACTIVE;
+ ifp->if_flags |= IFF_RUNNING;
+
+#ifdef notyet
+ if (ic->ic_flags & IEEE80211_F_WEPON) {
+ /* Install WEP keys. */
+ for (i = 0; i < IEEE80211_WEP_NKID; i++)
+ athn_usb_set_key(ic, NULL, &ic->ic_nw_keys[i]);
+ }
+#endif
+ if (ic->ic_opmode == IEEE80211_M_HOSTAP)
+ ic->ic_max_aid = AR_USB_MAX_STA; /* Firmware is limited to 8 STA */
+ else
+ ic->ic_max_aid = sc->sc_max_aid;
+
+ if (ic->ic_opmode == IEEE80211_M_MONITOR)
+ ieee80211_new_state(ic, IEEE80211_S_RUN, -1);
+ else
+ ieee80211_new_state(ic, IEEE80211_S_SCAN, -1);
+ athn_usb_wait_async(usc);
+ return 0;
+ fail:
+ athn_usb_stop(ifp);
+ return error;
+}
+
+Static void
+athn_usb_stop(struct ifnet *ifp)
+{
+ struct athn_softc *sc = ifp->if_softc;
+ struct athn_usb_softc *usc = ATHN_USB_SOFTC(sc);
+ struct ieee80211com *ic = &sc->sc_ic;
+ struct ar_htc_target_vif hvif;
+ struct mbuf *m;
+ uint8_t sta_index;
+ int s, error;
+
+ DPRINTFN(DBG_FN, sc, "\n");
+
+ s = splusb();
+ ieee80211_new_state(ic, IEEE80211_S_INIT, -1);
+ athn_usb_wait_async(usc);
+ splx(s);
+
+ sc->sc_tx_timer = 0;
+ ifp->if_timer = 0;
+ ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
+
+ callout_stop(&sc->sc_scan_to);
+ callout_stop(&sc->sc_calib_to);
+
+ /* Abort Tx/Rx. */
+ usbd_abort_pipe(usc->usc_tx_data_pipe);
+ usbd_abort_pipe(usc->usc_rx_data_pipe);
+
+ /* Free Tx/Rx buffers. */
+ athn_usb_free_tx_list(usc);
+ athn_usb_free_rx_list(usc);
+
+ /* Flush Rx stream. */
+ CTASSERT(sizeof(m) == sizeof(void *));
+ m = atomic_swap_ptr(&usc->usc_rx_stream.m, NULL);
+ m_freem(m);
+ usc->usc_rx_stream.left = 0;
+
+ /* Remove main interface. */
+ memset(&hvif, 0, sizeof(hvif));
+ hvif.index = 0;
+ IEEE80211_ADDR_COPY(hvif.myaddr, ic->ic_myaddr);
+ (void)athn_usb_wmi_xcmd(usc, AR_WMI_CMD_VAP_REMOVE,
+ &hvif, sizeof(hvif), NULL);
+
+ /* Remove default node. */
+ sta_index = 0;
+ DPRINTFN(DBG_NODES, usc, "removing node %u\n", sta_index);
+ error = athn_usb_remove_hw_node(usc, &sta_index);
+
+ (void)athn_usb_wmi_cmd(usc, AR_WMI_CMD_DISABLE_INTR);
+ (void)athn_usb_wmi_cmd(usc, AR_WMI_CMD_DRAIN_TXQ_ALL);
+ (void)athn_usb_wmi_cmd(usc, AR_WMI_CMD_STOP_RECV);
+
+ athn_reset(sc, 0);
+ athn_init_pll(sc, NULL);
+ athn_set_power_awake(sc);
+ athn_reset(sc, 1);
+ athn_init_pll(sc, NULL);
+ athn_set_power_sleep(sc);
+}
+
+MODULE(MODULE_CLASS_DRIVER, if_athn_usb, "bpf");
+
+#ifdef _MODULE
+#include "ioconf.c"
+#endif
+
+static int
+if_athn_usb_modcmd(modcmd_t cmd, void *aux)
+{
+ int error = 0;
+
+ switch (cmd) {
+ case MODULE_CMD_INIT:
+#ifdef _MODULE
+ error = config_init_component(cfdriver_ioconf_if_athn_usb,
+ cfattach_ioconf_if_athn_usb, cfdata_ioconf_if_athn_usb);
+#endif
+ return error;
+ case MODULE_CMD_FINI:
+#ifdef _MODULE
+ error = config_fini_component(cfdriver_ioconf_if_athn_usb,
+ cfattach_ioconf_if_athn_usb, cfdata_ioconf_if_athn_usb);
+#endif
+ return error;
+ default:
+ return ENOTTY;
+ }
+}
diff --git a/sys/dev/usb/if_athn_usb.h b/sys/dev/usb/if_athn_usb.h
new file mode 100644
index 00000000000..c8a1034f590
--- /dev/null
+++ b/sys/dev/usb/if_athn_usb.h
@@ -0,0 +1,493 @@
+/* $NetBSD: if_athn_usb.h,v 1.1 2013/03/30 02:53:02 christos Exp $ */
+/* $OpenBSD: if_athn_usb.h,v 1.3 2012/11/10 14:35:06 mikeb Exp $ */
+
+/*-
+ * Copyright (c) 2011 Damien Bergamini <damien.bergamini@free.fr>
+ *
+ * Permission to use, copy, modify, and distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _IF_ATHN_USB_H_
+#define _IF_ATHN_USB_H_
+
+/* Maximum number of STAs firmware can handle. */
+#define AR_USB_MAX_STA 8
+
+#define AR_USB_DEFAULT_NF (-95)
+
+/* USB requests. */
+#define AR_FW_DOWNLOAD 0x30
+#define AR_FW_DOWNLOAD_COMP 0x31
+
+/* USB endpoints addresses. */
+#define AR_PIPE_TX_DATA (UE_DIR_OUT | 1)
+#define AR_PIPE_RX_DATA (UE_DIR_IN | 2)
+#define AR_PIPE_RX_INTR (UE_DIR_IN | 3)
+#define AR_PIPE_TX_INTR (UE_DIR_OUT | 4)
+
+/* Wireless module interface commands. */
+#define AR_WMI_CMD_ECHO 0x001
+#define AR_WMI_CMD_ACCESS_MEMORY 0x002
+#define AR_WMI_CMD_DISABLE_INTR 0x003
+#define AR_WMI_CMD_ENABLE_INTR 0x004
+#define AR_WMI_CMD_RX_LINK 0x005
+#define AR_WMI_CMD_ATH_INIT 0x006
+#define AR_WMI_CMD_ABORT_TXQ 0x007
+#define AR_WMI_CMD_STOP_TX_DMA 0x008
+#define AR_WMI_CMD_STOP_DMA_RECV 0x009
+#define AR_WMI_CMD_ABORT_TX_DMA 0x00a
+#define AR_WMI_CMD_DRAIN_TXQ 0x00b
+#define AR_WMI_CMD_DRAIN_TXQ_ALL 0x00c
+#define AR_WMI_CMD_START_RECV 0x00d
+#define AR_WMI_CMD_STOP_RECV 0x00e
+#define AR_WMI_CMD_FLUSH_RECV 0x00f
+#define AR_WMI_CMD_SET_MODE 0x010
+#define AR_WMI_CMD_RESET 0x011
+#define AR_WMI_CMD_NODE_CREATE 0x012
+#define AR_WMI_CMD_NODE_REMOVE 0x013
+#define AR_WMI_CMD_VAP_REMOVE 0x014
+#define AR_WMI_CMD_VAP_CREATE 0x015
+#define AR_WMI_CMD_BEACON_UPDATE 0x016
+#define AR_WMI_CMD_REG_READ 0x017
+#define AR_WMI_CMD_REG_WRITE 0x018
+#define AR_WMI_CMD_RC_STATE_CHANGE 0x019
+#define AR_WMI_CMD_RC_RATE_UPDATE 0x01a
+#define AR_WMI_CMD_DEBUG_INFO 0x01b
+#define AR_WMI_CMD_HOST_ATTACH 0x01c
+#define AR_WMI_CMD_TARGET_IC_UPDATE 0x01d
+#define AR_WMI_CMD_TGT_STATS 0x01e
+#define AR_WMI_CMD_TX_AGGR_ENABLE 0x01f
+#define AR_WMI_CMD_TGT_DETACH 0x020
+#define AR_WMI_CMD_TGT_TXQ_ENABLE 0x021
+#define AR_WMI_CMD_AGGR_LIMIT 0x026
+/* Wireless module interface events. */
+/*
+ * XXX: the 3.7.4 Linux kernel differs with this. This matches the
+ * 2.6.36 kernel.
+ */
+#if 1 /* Linux 2.6.26 */
+#define AR_WMI_EVT_TGT_RDY 0x001
+#define AR_WMI_EVT_SWBA 0x002
+#define AR_WMI_EVT_FATAL 0x003
+#define AR_WMI_EVT_TXTO 0x004
+#define AR_WMI_EVT_BMISS 0x005
+#define AR_WMI_EVT_WLAN_TXCOMP 0x006
+#define AR_WMI_EVT_DELBA 0x007
+#define AR_WMI_EVT_TXRATE 0x008
+#else /* Linux 3.7.4 */
+#define AR_WMI_EVT_TGT_RDY 0x001
+#define AR_WMI_EVT_SWBA 0x002
+#define AR_WMI_EVT_FATAL 0x003
+#define AR_WMI_EVT_TXTO 0x004
+#define AR_WMI_EVT_BMISS 0x005
+#define AR_WMI_EVT_DELBA 0x006
+#define AR_WMI_EVT_TXSTATUS 0x007
+#endif
+
+/* Structure for service AR_SVC_WMI_CONTROL. */
+struct ar_wmi_cmd_hdr {
+ uint16_t cmd_id;
+#define AR_WMI_EVT_FLAG 0x1000
+
+ uint16_t seq_no;
+} __packed;
+
+/* Values for AR_WMI_CMD_SET_MODE. */
+#define AR_HTC_MODE_AUTO 0
+#define AR_HTC_MODE_11A 1
+#define AR_HTC_MODE_11B 2
+#define AR_HTC_MODE_11G 3
+#define AR_HTC_MODE_FH 4
+#define AR_HTC_MODE_TURBO_A 5
+#define AR_HTC_MODE_TURBO_G 6
+#define AR_HTC_MODE_11NA 7
+#define AR_HTC_MODE_11NG 8
+
+#define AR_MAX_WRITE_COUNT 32
+/* Structure for command AR_WMI_CMD_REG_WRITE. */
+struct ar_wmi_cmd_reg_write {
+ uint32_t addr;
+ uint32_t val;
+} __packed;
+
+/* Structure for command AR_WMI_CMD_NODE_{CREATE,REMOVE}. */
+struct ar_htc_target_sta {
+ uint16_t associd;
+ uint16_t txpower;
+ uint32_t pariwisekey;
+ uint8_t macaddr[IEEE80211_ADDR_LEN];
+ uint8_t bssid[IEEE80211_ADDR_LEN];
+ uint8_t sta_index;
+ uint8_t vif_index;
+ uint8_t vif_sta;
+ uint16_t flags;
+#define AR_HTC_STA_AUTH 0x0001
+#define AR_HTC_STA_QOS 0x0002
+#define AR_HTC_STA_ERP 0x0004
+#define AR_HTC_STA_HT 0x0008
+
+ uint16_t htcap;
+ uint8_t valid;
+ uint16_t capinfo;
+ uint32_t reserved[2];
+ uint16_t txseqmgmt;
+ uint8_t is_vif_sta;
+ uint16_t maxampdu;
+ uint16_t iv16;
+ uint32_t iv32;
+} __packed;
+
+/* Structures for command AR_WMI_CMD_RC_RATE_UPDATE. */
+#define AR_HTC_RATE_MAX 30
+struct ar_htc_rateset {
+ uint8_t rs_nrates;
+ uint8_t rs_rates[AR_HTC_RATE_MAX];
+} __packed;
+
+struct ar_htc_target_rate {
+ uint8_t sta_index;
+ uint8_t isnew;
+ uint32_t capflags;
+#define AR_RC_DS_FLAG 0x00000001
+#define AR_RC_TS_FLAG 0x00000002
+#define AR_RC_40_FLAG 0x00000004
+#define AR_RC_SGI_FLAG 0x00000008
+#define AR_RC_HT_FLAG 0x00000010
+
+ struct ar_htc_rateset lg_rates;
+ struct ar_htc_rateset ht_rates;
+} __packed;
+
+/* Structure for command AR_WMI_CMD_TX_AGGR_ENABLE. */
+struct ar_htc_target_aggr {
+ uint8_t sta_index;
+ uint8_t tidno;
+ uint8_t aggr_enable;
+ uint8_t padding;
+} __packed;
+
+/* Structure for command AR_WMI_CMD_VAP_CREATE. */
+struct ar_htc_target_vif {
+ uint8_t index;
+ uint8_t des_bssid[IEEE80211_ADDR_LEN];
+ uint32_t opmode;
+#define AR_HTC_M_IBSS 0
+#define AR_HTC_M_STA 1
+#define AR_HTC_M_WDS 2
+#define AR_HTC_M_AHDEMO 3
+#define AR_HTC_M_HOSTAP 6
+#define AR_HTC_M_MONITOR 8
+
+ uint8_t myaddr[IEEE80211_ADDR_LEN];
+ uint8_t bssid[IEEE80211_ADDR_LEN];
+ uint32_t flags;
+ uint32_t flags_ext;
+ uint16_t ps_sta;
+ uint16_t rtsthreshold;
+ uint8_t ath_cap;
+ int8_t mcast_rate;
+} __packed;
+
+/* Structure for command AM_WMI_CMD_TARGET_IC_UPDATE. */
+struct ar_htc_cap_target {
+ uint32_t flags;
+ uint32_t flags_ext;
+ uint32_t ampdu_limit;
+ uint8_t ampdu_subframes;
+ uint8_t ht_txchainmask;
+ uint8_t lg_txchainmask;
+ uint8_t rtscts_ratecode;
+ uint8_t protmode;
+} __packed;
+
+/* Structure for event AR_WMI_EVT_TXRATE. */
+struct ar_wmi_evt_txrate {
+ uint32_t txrate;
+ uint8_t rssi_thresh;
+ uint8_t per;
+} __packed;
+
+/* HTC header. */
+struct ar_htc_frame_hdr {
+ uint8_t endpoint_id;
+ uint8_t flags;
+#define AR_HTC_FLAG_TRAILER 0x02
+
+ uint16_t payload_len;
+ uint8_t control[4];
+} __packed;
+
+/* Structure for HTC enpoint id 0. */
+struct ar_htc_msg_hdr {
+ uint16_t msg_id;
+#define AR_HTC_MSG_READY 0x0001
+#define AR_HTC_MSG_CONN_SVC 0x0002
+#define AR_HTC_MSG_CONN_SVC_RSP 0x0003
+#define AR_HTC_MSG_SETUP_COMPLETE 0x0004
+#define AR_HTC_MSG_CONF_PIPE 0x0005
+#define AR_HTC_MSG_CONF_PIPE_RSP 0x0006
+} __packed;
+
+/* Structure for services AR_SVC_WMI_DATA_{VO,VI,BE,BK}. */
+struct ar_tx_frame {
+ uint8_t data_type;
+#define AR_HTC_AMPDU 1
+#define AR_HTC_NORMAL 2
+
+ uint8_t node_idx;
+ uint8_t vif_idx;
+ uint8_t tid;
+ uint32_t flags;
+#define AR_HTC_TX_CTSONLY 0x00000001
+#define AR_HTC_TX_RTSCTS 0x00000002
+#define AR_HTC_TX_USE_MIN_RATE 0x00000100
+
+ uint8_t key_type;
+ uint8_t key_idx;
+ uint8_t reserved[26];
+} __packed;
+
+/* Structure for service AR_SVC_WMI_MGMT. */
+struct ar_tx_mgmt {
+ uint8_t node_idx;
+ uint8_t vif_idx;
+ uint8_t tid;
+ uint8_t flags;
+ uint8_t key_type;
+ uint8_t key_idx;
+ uint16_t reserved;
+} __packed;
+
+/* Structure for service AR_SVC_WMI_BEACON. */
+struct ar_tx_bcn {
+ uint8_t len_changed;
+ uint8_t vif_idx;
+ uint16_t rev;
+} __packed;
+
+/* Structure for message AR_HTC_MSG_READY. */
+struct ar_htc_msg_ready {
+ uint16_t credits;
+ uint16_t credits_size;
+ uint8_t max_endpoints;
+ uint8_t reserved;
+} __packed;
+
+/* Structure for message AR_HTC_MSG_CONF_PIPE. */
+struct ar_htc_msg_config_pipe {
+ uint8_t pipe_id;
+ uint8_t credits;
+} __packed;
+
+/* Structure for message AR_HTC_MSG_CONN_SVC. */
+struct ar_htc_msg_conn_svc {
+ uint16_t svc_id;
+ uint16_t conn_flags;
+ uint8_t dl_pipeid;
+ uint8_t ul_pipeid;
+ uint8_t svc_meta_len;
+ uint8_t reserved;
+} __packed;
+
+/* Structure for message AR_HTC_MSG_CONN_SVC_RSP. */
+struct ar_htc_msg_conn_svc_rsp {
+ uint16_t svc_id;
+ uint8_t status;
+#define AR_HTC_SVC_SUCCESS 0
+#define AR_HTC_SVC_NOT_FOUND 1
+#define AR_HTC_SVC_FAILED 2
+#define AR_HTC_SVC_NO_RESOURCES 3
+#define AR_HTC_SVC_NO_MORE_EP 4
+
+ uint8_t endpoint_id;
+ uint16_t max_msg_len;
+ uint8_t svc_meta_len;
+ uint8_t reserved;
+} __packed;
+
+#define AR_SVC(grp, idx) ((grp) << 8 | (idx))
+#define AR_SVC_IDX(svc) ((svc) & 0xff)
+/* Service groups. */
+#define AR_SVC_GRP_RSVD 0
+#define AR_SVC_GRP_WMI 1
+/* Service identifiers for WMI group. */
+#define AR_SVC_WMI_CONTROL AR_SVC(AR_SVC_GRP_WMI, 0)
+#define AR_SVC_WMI_BEACON AR_SVC(AR_SVC_GRP_WMI, 1)
+#define AR_SVC_WMI_CAB AR_SVC(AR_SVC_GRP_WMI, 2)
+#define AR_SVC_WMI_UAPSD AR_SVC(AR_SVC_GRP_WMI, 3)
+#define AR_SVC_WMI_MGMT AR_SVC(AR_SVC_GRP_WMI, 4)
+#define AR_SVC_WMI_DATA_VO AR_SVC(AR_SVC_GRP_WMI, 5)
+#define AR_SVC_WMI_DATA_VI AR_SVC(AR_SVC_GRP_WMI, 6)
+#define AR_SVC_WMI_DATA_BE AR_SVC(AR_SVC_GRP_WMI, 7)
+#define AR_SVC_WMI_DATA_BK AR_SVC(AR_SVC_GRP_WMI, 8)
+
+struct ar_stream_hdr {
+ uint16_t len;
+ uint16_t tag;
+#define AR_USB_RX_STREAM_TAG 0x4e00
+#define AR_USB_TX_STREAM_TAG 0x697e
+} __packed __attribute__((aligned(4)));
+
+#define AR_MAX_CHAINS 3
+
+/* Rx descriptor. */
+struct ar_rx_status {
+ uint64_t rs_tstamp;
+ uint16_t rs_datalen;
+ uint8_t rs_status;
+ uint8_t rs_phyerr;
+ int8_t rs_rssi;
+ int8_t rs_rssi_ctl[AR_MAX_CHAINS];
+ int8_t rs_rssi_ext[AR_MAX_CHAINS];
+ uint8_t rs_keyix;
+ uint8_t rs_rate;
+ uint8_t rs_antenna;
+ uint8_t rs_more;
+ uint8_t rs_isaggr;
+ uint8_t rs_moreaggr;
+ uint8_t rs_num_delims;
+ uint8_t rs_flags;
+#define AR_RXS_FLAG_GI 0x04
+#define AR_RXS_FLAG_2040 0x08
+
+ uint8_t rs_dummy;
+ uint32_t rs_evm[AR_MAX_CHAINS];
+} __packed __attribute__((aligned(4)));
+
+
+/*
+ * Driver definitions.
+ */
+#define ATHN_USB_RX_LIST_COUNT 1
+#define ATHN_USB_TX_LIST_COUNT (8 + 1) /* NB: +1 for beacons. */
+
+#define ATHN_USB_HOST_CMD_RING_COUNT 32
+
+#define ATHN_USB_RXBUFSZ (8 * 1024) /* XXX Linux 16K */
+#define ATHN_USB_TXBUFSZ \
+ ((sizeof(struct ar_stream_hdr) + \
+ sizeof(struct ar_htc_frame_hdr) + \
+ sizeof(struct ar_tx_frame) + \
+ IEEE80211_MAX_LEN + 3) & ~3)
+#define ATHN_USB_TXCMDSZ 512
+
+#define ATHN_USB_TX_TIMEOUT 5000 /* ms */
+#define ATHN_USB_CMD_TIMEOUT 1000 /* ms */
+
+struct athn_usb_softc;
+
+struct athn_usb_rx_stream {
+ struct mbuf *m;
+ int moff;
+ int left;
+};
+
+struct athn_usb_rx_data {
+ struct athn_usb_softc *sc;
+ usbd_xfer_handle xfer;
+ uint8_t *buf;
+};
+
+struct athn_usb_tx_data {
+ struct athn_usb_softc *sc;
+ usbd_xfer_handle xfer;
+ uint8_t *buf;
+ TAILQ_ENTRY(athn_usb_tx_data) next;
+};
+
+struct athn_usb_host_cmd {
+ void (*cb)(struct athn_usb_softc *, void *);
+ uint8_t data[256];
+};
+
+struct athn_usb_cmd_newstate {
+ enum ieee80211_state state;
+ int arg;
+};
+
+struct athn_usb_cmd_key {
+ struct ieee80211_node *ni;
+ struct ieee80211_key *key;
+};
+
+struct athn_usb_aggr_cmd {
+ uint8_t sta_index;
+ uint8_t tid;
+};
+
+struct athn_usb_host_cmd_ring {
+ struct athn_usb_host_cmd cmd[ATHN_USB_HOST_CMD_RING_COUNT];
+ int cur;
+ int next;
+ int queued;
+};
+
+struct athn_usb_node {
+ struct athn_node aun_an;
+ /* our stuff */
+};
+
+struct athn_usb_softc {
+ struct athn_softc usc_sc;
+#define usc_dev usc_sc.sc_dev
+
+ int usc_athn_attached;
+
+ kmutex_t usc_task_mtx;
+ kmutex_t usc_tx_mtx;
+
+ /* USB specific goo. */
+ usbd_device_handle usc_udev;
+ usbd_interface_handle usc_iface;
+ struct usb_task usc_task;
+ int usc_dying;
+
+ u_int usc_flags;
+#define ATHN_USB_FLAG_NONE 0x00
+#define ATHN_USB_FLAG_AR7010 0x01
+
+ struct athn_usb_rx_stream usc_rx_stream;
+
+ usbd_pipe_handle usc_tx_data_pipe;
+ usbd_pipe_handle usc_rx_data_pipe;
+ usbd_pipe_handle usc_rx_intr_pipe;
+ usbd_pipe_handle usc_tx_intr_pipe;
+ uint8_t *usc_ibuf;
+
+ struct ar_wmi_cmd_reg_write usc_wbuf[AR_MAX_WRITE_COUNT];
+ int usc_wcount;
+
+ int usc_wmi_done;
+ uint16_t usc_wmi_seq_no;
+ uint16_t usc_wait_cmd_id;
+ uint16_t usc_wait_msg_id;
+ void *usc_obuf;
+ struct ar_htc_msg_conn_svc_rsp *usc_msg_conn_svc_rsp;
+
+ struct athn_usb_host_cmd_ring usc_cmdq;
+ struct athn_usb_rx_data usc_rx_data[ATHN_USB_RX_LIST_COUNT];
+ struct athn_usb_tx_data usc_tx_data[ATHN_USB_TX_LIST_COUNT];
+ TAILQ_HEAD(, athn_usb_tx_data) usc_tx_free_list;
+ struct athn_usb_tx_data usc_tx_cmd;
+ struct athn_usb_tx_data *usc_tx_bcn;
+
+ uint8_t usc_ep_ctrl;
+ uint8_t usc_ep_bcn;
+ uint8_t usc_ep_cab;
+ uint8_t usc_ep_uapsd;
+ uint8_t usc_ep_mgmt;
+ uint8_t usc_ep_data[EDCA_NUM_AC];
+ void (*usc_node_cleanup)(struct ieee80211_node *);
+};
+
+#endif /* _IF_ATHN_USB_H_ */