| Age | Commit message (Collapse) | Author |
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to set the cacheline size in the BHLC register. This should be the
size of the largest D-cache line on a system.
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first bus number to use, rather than always assuming that we should
start at bus #0.
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IDE channels on the P-5064 and P-6032, since PMON doesn't do it
for us (thus causing the `pciide' driver to ignore them).
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but is meant for back-up purposes.
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function now just takes an "irq", which is an index into the irqmap
table for that platform.
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I/O space on PBC revs < B2.
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V3 PBC, and use them in the bus mem tag and the bus dma tag on the
P-4032. This allows us to get much further when PMON has configured
the PBC using the old-style PCI address map.
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- Compute the number of CPU pipeline cycles per second using the
mc146818.
- Use the COMPARE interrupt for the hardclock interrupt.
- Collapse all interrupt priorities into a single priority, and use
the CPU interrupt inputs to determine the interrupt source (local
device, PCI device, ISA device, etc.)
This allows us to have interrupt sharing.
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untested, since I have no P-4032 board, but it's no worse than
the current situation, which is "totally non-working P-4032
support in the ARC port, of all places".
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support the P-5064, which has a QED RM5xxx CPU soldered on.
There is some skeletal support for the P-4032 (an older board, which
had an R4xxx CPU). There are some placeholders for the P-6032, which
is their newest board, but no real code yet (the P-6032 has a different
PCI controller, the Algorithmics BONITO).
There are still some (apprently softintr-related) problems with the
algor kernel, but it works well-enough to self-host.
Kudos to Allegro Networks for loaning me a P-5064 board on which to do
the port.
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