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2002-01-02Fix a typo.thorpej
2001-11-28Add a "cacheline_size" argument to pci_configure_bus(). It is usedthorpej
to set the cacheline size in the BHLC register. This should be the size of the largest D-cache line on a system.
2001-11-09Add a "firstbus" argument to pci_configure_bus(), indicating thethorpej
first bus number to use, rather than always assuming that we should start at bus #0.
2001-10-20Fix a tyop in a comment.simonb
2001-08-22If PCI_NETBSD_ENABLE_IDE is set, enable the PIIX{3,4} southbridgethorpej
IDE channels on the P-5064 and P-6032, since PMON doesn't do it for us (thus causing the `pciide' driver to ignore them).
2001-06-25Print more BONITO rev. info.thorpej
2001-06-22Check in work-in-progress of P-6032 support. This is not tested,thorpej
but is meant for back-up purposes.
2001-06-22A P-6032 will never have a V3 PBC -- don't include its option header.thorpej
2001-06-15Yet more interrupt cleanup -- the platform mater interrupt establishthorpej
function now just takes an "irq", which is an index into the irqmap table for that platform.
2001-06-14When the old PCI address map is in use, disable I/O space. Also disablethorpej
I/O space on PBC revs < B2.
2001-06-14Read the PCI memory space base and the PCI DMA window base from thethorpej
V3 PBC, and use them in the bus mem tag and the bus dma tag on the P-4032. This allows us to get much further when PMON has configured the PBC using the old-style PCI address map.
2001-06-10Correct for a data structure change.thorpej
2001-06-10Rewrite the interrupt handling code:thorpej
- Compute the number of CPU pipeline cycles per second using the mc146818. - Use the COMPARE interrupt for the hardclock interrupt. - Collapse all interrupt priorities into a single priority, and use the CPU interrupt inputs to determine the interrupt source (local device, PCI device, ISA device, etc.) This allows us to have interrupt sharing.
2001-06-01Add support for the Algorithmics P-4032 board. This is totallythorpej
untested, since I have no P-4032 board, but it's no worse than the current situation, which is "totally non-working P-4032 support in the ARC port, of all places".
2001-05-28A port to the Algorithmics MIPS evaluation boards. We currentlythorpej
support the P-5064, which has a QED RM5xxx CPU soldered on. There is some skeletal support for the P-4032 (an older board, which had an R4xxx CPU). There are some placeholders for the P-6032, which is their newest board, but no real code yet (the P-6032 has a different PCI controller, the Algorithmics BONITO). There are still some (apprently softintr-related) problems with the algor kernel, but it works well-enough to self-host. Kudos to Allegro Networks for loaning me a P-5064 board on which to do the port.