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path: root/sys/arch/x86/include/cpu.h
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2022-09-07NetBSD/x86: Raise the number of interrupt sources per CPU from 32 to 56.knakahara
There has been no objection for three years. https://mail-index.netbsd.org/port-amd64/2019/09/22/msg003012.html Implemented by nonaka@n.o, updated by me.
2021-10-07Move some common functions into x86/identcpu_subr.c. No functional change.msaitoh
2021-08-14Improved the performance of kernel profiling on MULTIPROCESSOR, and possible ↵ryo
to get profiling data for each CPU. In the current implementation, locks are acquired at the entrance of the mcount internal function, so the higher the number of cores, the more lock conflict occurs, making profiling performance in a MULTIPROCESSOR environment unusable and slow. Profiling buffers has been changed to be reserved for each CPU, improving profiling performance in MP by several to several dozen times. - Eliminated cpu_simple_lock in mcount internal function, using per-CPU buffers. - Add ci_gmon member to struct cpu_info of each MP arch. - Add kern.profiling.percpu node in sysctl tree. - Add new -c <cpuid> option to kgmon(8) to specify the cpuid, like openbsd. For compatibility, if the -c option is not specified, the entire system can be operated as before, and the -p option will get the total profiling data for all CPUs.
2021-02-19Identify VirtualBox as a separate guest type.christos
2020-08-08PR/55547: Dan Plassche: Fix BSD/OS binary emulation.christos
Centralize lcall sniffer and recognize the BSD/OS flavor.
2020-07-19don't include opt_user_ldt.h when it is not neededmaxv
2020-07-14Introduce per-cpu IDTsyamaguchi
This is realized by following modifications: - Add IDT pages and its allocation maps for each cpu in "struct cpu_info" - Load per-cpu IDTs at cpu_init_idt(struct cpu_info*) - Copy the IDT entries for cpu0 to other CPUs at attach - These are, for example, exceptions, db, system calls, etc. And, added a kernel option named PCPU_IDT to enable the feature.
2020-06-19localifymaxv
2020-05-02Introduce Xen PVH support in GENERIC.bouyer
This is compiled in with options XENPVHVM x86 changes: - add Xen section and xen pvh entry points to locore.S. Set vm_guest to VM_GUEST_XENPVH in this entry point. Most of the boot procedure (especially page table setup and switch to paged mode) is shared with native. - change some x86_delay() to delay_func(), which points to x86_delay() for native/HVM, and xen_delay() for PVH Xen changes: - remove Xen bits from init_x86_64_ksyms() and init386_ksyms() and move to xen_init_ksyms(), used for both PV and PVH - set ISA no-legacy-devices property for PVH - factor out code from Xen's cpu_bootconf() to xen_bootconf() in xen_machdep.c - set up a specific pvh_consinit() which starts with printk() (which uses a simple hypercall that is available early) and switch to xencons when we can use pmap_kenter_pa().
2020-04-30Don't #include xen/intrdefs.h is !XEN.bouyer
Should fix third-party module builds (e.g. virtualbox)
2020-04-27Move ci_vcpu under the #ifdef XEN section at the end of the struct cpu_info.bouyer
Hopefully will fix the nvmm module.
2020-04-25Merge the bouyer-xenpvh branch, bringing in Xen PV drivers support under HVMbouyer
guests in GENERIC. Xen support can be disabled at runtime with boot -c disable hypervisor
2020-04-21Get TSC frequency from CPUID 0x15 and/or x16 for newer Intel processors.msaitoh
- If the max CPUID leaf is >= 0x15, take TSC value from CPUID. Some processors can take TSC/core crystal clock ratio but core crystal clock frequency can't be taken. Intel SDM give us the values for some processors. - It also required to change lapic_per_second to make LAPIC timer correctly. - Add new file x86/x86/identcpu_subr.c to share common subroutines between kernel and userland. Some code in x86/x86/identcpu.c and cpuctl/arch/i386.c will be moved to this file in future. - Add comment to clarify.
2020-04-13By default, events are bound to CPU 0 (exept for IPIs and VTIMERs whichbouyer
are bound to a different CPU at creation time). Recent MI changes caused the scheduler to choose a different CPU when probing and attaching xennet devices (I guess it's the xenbus thread which runs on a different CPU). This cause the callback to be called on a different CPU than the one expected by the kernel, and the event is ignored. It is handled when the clock causes the callback to be called on the right CPU, which is why xennet still run, but slowly. Change event_set_handler() to do a EVTCHNOP_bind_vcpu if requested to, and make sure we don't do it for IPIs and VIRQs (for theses, the op fails).
2020-04-10Revert, wrong branchbouyer
2020-04-10Skip cx8_spllower patch if we're running on any form of Xen PV,bouyer
we can't handle PV interrupts with a single atomic op here. Enable x86_patch() for Xen too.
2020-01-15Push the INVLPG limit for shootdowns up to 16 (for UBC).ad
2019-12-30Fix a problem with intr_unmask() that can cause a forever-loop:thorpej
- When handling the source-is-masked case in the interrupt vector, set the interrupt bit in a new ci_imasked field and ensure the bit is cleared from ci_ipending. - In intr_unmask(), transfer the bit from ci_imasked to ci_ipending for non-level-sensitive interrupts (the PIC does the work for us in the level-sensitive case), and only force pending interrupts to be processed in this case. (In all cases, make sure the now-unmasked bit is cleared from ci_imasked.) Before, the bit was left in ci_ipending so as not to use edge-triggered interrupts while the source is masked, but Xspllower() relies on the pending bits getting cleared. Tested by forcing all wm(4) interrupts on my test system though an intr_mask() / softint / intr_unmask() cycle and exercising the network heavily.
2019-12-01Fix false sharing problems with cpu_info. Identified with tprof(8).ad
This was a very nice win in my tests on a 48 CPU box. - Reorganise cpu_data slightly according to usage. - Put cpu_onproc into struct cpu_info alongside ci_curlwp (now is ci_onproc). - On x86, put some items in their own cache lines according to usage, like the IPI bitmask and ci_want_resched.
2019-11-27Add a small API for in-kernel FPU operations.maxv
fpu_kern_enter(); /* do FPU stuff */ fpu_kern_leave();
2019-11-23cpu_need_resched():ad
- Remove all code that should be MI, leaving the bare minimum under arch/. - Make the required actions very explicit. - Pass in LWP pointer for convenience. - When a trap is required on another CPU, have the IPI set it locally. - Expunge cpu_did_resched().
2019-11-21x86 TLB shootdown IPI changes:ad
- Shave some time off processing. - Reduce cacheline/bus traffic on systems with many CPUs. - Reduce time spent at IPL_VM.
2019-11-21mi_userret(): take care of calling preempt(), set spc_curpriority directly,ad
and remove MD code that does the same.
2019-10-12Rewrite the FPU code on x86. This greatly simplifies the logic and removesmaxv
the dependency on IPL_HIGH. NVMM is updated accordingly. Posted on port-amd64 a week ago. Bump the kernel version to 9.99.16.
2019-10-03Remove the LazyFPU code, as posted 5 months ago on port-amd64@.maxv
2019-08-07Add support for USER_LDT in SVS. This allows us to have both enabled atmaxv
the same time. We allocate an LDT for each CPU in the GDT and map an area for it, in addition to the default LDT already present. In context switches between different processes, we choose between the default or the per-cpu LDT selector: if the user set specific LDT entries, we memcpy them to the per-cpu LDT and load the per-cpu selector. Tested by Naveen Narayanan (with Wine on amd64).
2019-06-26Fetch XSAVE area component offsets and sizes when initializing x86 CPUmgorny
Introduce two new arrays, x86_xsave_offsets and x86_xsave_sizes, and initialize them with XSAVE area component offsets and sizes queried via CPUID. This will be needed to implement getters and setters for additional register types. While at it, add XSAVE_* constants corresponding to specific XSAVE components.
2019-05-27Remove 'ci_svs_kpdirpa', unused. While here fix a few comments here andmaxv
there, reduces a future diff.
2019-02-15Added Microsoft Hyper-V support. It ported from OpenBSD and FreeBSD.nonaka
graphical console is not work on Gen.2 VM yet. To use the serial console, enter "consdev com,0x3f8,115200" on efiboot.
2019-02-14Welcome XENPVHVM mode.cherry
It is UP only, has xbd(4) and xennet(4) as PV drivers. The console is com0 at isa and the native portion is very rudimentary AT architecture, so is probably suboptimal to run without PV support.
2019-02-11We reorganise definitions for XEN source support as follows:cherry
XEN - common sources required for baseline XEN support. XENPV - sources required for support of XEN in PV mode. XENPVHVM - sources required for support for XEN in HVM mode. XENPVH - sources required for support for XEN in PVH mode.
2019-02-02Switch NetBSD/xen to use XEN api tag RELEASE-4.11.1cherry
The headers for this api are in sys/external/mit/xen-include-public/dist/
2018-12-25Excise XEN specific code out of x86/x86/intr.c into xen/x86/xen_intr.ccherry
While at it, separate the source function tracking so that the interrupt paths are truly independant. Use weak symbol exporting to provision for future PVHVM co-existence of both files, but with independant paths. Introduce assembler code such that in a unified scenario, native interrupts get first priority in spllower(), followed by XEN event callbacks. IPL management and semantics are unchanged - native handlers and xen callbacks are expected to maintain their ipl related semantics. In summary, after this commit, native and XEN now have completely unrelated interrupt handling mechanisms, including intr_establish_xname() and assembler stubs and intr handler management. Happy Christmas!
2018-11-18On Xen, copy just the bits we need from the trapframe for hardclock(9)cherry
and statclock(9). Current, the macros that use the trapframe are: CLKF_USERMODE() CLKF_PC() CLKF_INTR() Of these, CLKF_INTR() already ignores the frame and uses the ci_idepth variable to do its job. Convert the two remaining ones to do this, but only for XEN.
2018-11-18Save the interrupt trap/clockframe to a per-cpu copy.cherry
We can use this copy to pass on the trapframe to hardclock(9) from within the xen timer handler. This delinks the current dependency between MD code and the handler, which is specially prototyped to take the clockframe unlike any other handler. This change has performance implications, as each interrupt entry will copy the entire trapframe over to the per-cpu cached copy. This can be mitigated by selectively copying just the parts of the clockframe that are used by hardclock() et. al. Tested on amd64 XEN domU
2018-10-05export x86_fpu_mxcsr_mask, fpu_area_save and fpu_area_restoremaxv
2018-08-22- Cleanup for dynamic sysctl:msaitoh
- Remove unused *_NAMES macros for sysctl. - Remove unused *_MAXID for sysctls. - Move CTL_MACHDEP sysctl definitions for m68k into m68k/include/cpu.h and use them on all m68k machines.
2018-07-16More rearrangement of struct cpu_info to keep all the un-conditionalpgoyette
members at fixed locations. Should address my PR kern/52919 OK maxv@ XXX kernel version bump coming momentarily.
2018-07-15Hum. Move the __HAVE_DIRECT_MAP block a little below, otherwise dynamicallymaxv
loaded kernel modules use a wrong offset for some ci_* fields. Found when modloading tprof_amd on an AMD 10h, the read of ci_signature was at a wrong address, and the cpu family was not detected correctly.
2018-06-30Just use struct cpu_info members for the Xen clock state.riastradh
Silly to use percpu(9) for some things and struct cpu_info for others.
2018-06-29Rewrite Xen timecounter and hardclock timer.riastradh
With this change, the Xen timecounter should now be globally monotonic, as every timecounter is supposed to be. Should also fix a litany of races in the timecounter logic. Proposed last year; see mailing list for further details: https://mail-index.netbsd.org/port-xen/2017/10/31/msg009112.html ok cherry
2018-06-14Add some code to support eager fpu switch, INTEL-SA-00145. We restore themaxv
FPU state of the lwp right away during context switches. This guarantees that when the CPU executes in userland, the FPU doesn't contain secrets. Maybe we also need to clear the FPU in setregs(), not sure about this one. Can be enabled/disabled via: machdep.fpu_eager = {0/1} Not yet turned on automatically on affected CPUs (Intel Family 6). More generally it would be good to turn it on automatically when XSAVEOPT is supported, because in this case there is probably a non-negligible performance gain; but we need to fix PR/52966.
2018-04-04Enable the SpectreV2 mitigation by default at boot time.maxv
2018-03-30Retrieve cpuid.7:%edx.maxv
2018-01-18Unmap the kernel heap from the user page tables (SVS).maxv
This implementation is optimized and organized in such a way that we don't need to copy the kernel stack to a safe place during user<->kernel transitions. We create two VAs that point to the same physical page; one will be mapped in userland and is offset in order to contain only the trapframe, the other is mapped in the kernel and maps the entire stack. Sent on tech-kern@ a week ago.
2018-01-07Add a new option, SVS (for Separate Virtual Space), that unmaps kernelmaxv
pages when running in userland. For now, only the PTE area is unmapped. Sent on tech-kern@.
2018-01-05Add a __HAVE_PCPU_AREA option, enabled by default on native amd64 but notmaxv
Xen. With this option, the CPU structures that must always be present in the CPU's page tables are moved on L4 slot 384, which means address 0xffffc00000000000. A new pcpu_area structure is defined. It contains shared structures (IDT, LDT), and then an array of pcpu_entry structures, indexed by cpu_index(ci). Theoretically the LDT should be in the array, but this will be done later. During the boot procedure, cpu0 calls pmap_init_pcpu, which creates a page tree that is able to map the pcpu_area structure entirely. cpu0 then immediately maps the shared structures. Later, every CPU goes through cpu_pcpuarea_init, which allocates physical pages and kenters the relevant pcpu_entry to them. Finally, each pointer is replaced to point to pcpuarea. The point of this change is to make sure that the structures that must always be present in the page tables have their own L4 slot. Until now their L4 slot was that of pmap_kernel, and making a distinction between what must be mapped and what does not need to be was complicated. Even in the non-speculative-bug case this change makes some sense: there are several x86 instructions that leak the addresses of the CPU structures, and putting these structures inside pmap_kernel actually offered a way to compute the address of the kernel heap - which would have made ASLR on it plainly useless, had we implemented that. Note that, for now, pcpuarea does not contain rsp0. Unfortunately this change adds many #ifdefs, and makes the code harder to understand. There is also some duplication, but that will be solved later.
2018-01-04Allocate the TSS area dynamically. This way cpu_info and cpu_tss can bemaxv
put in separate pages.
2018-01-04Group the different TSSes into a cpu_tss structure. And pack thismaxv
structure to make sure there is no padding between 'tss' and 'iomap'.
2017-12-28typosmaxv