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2021-04-12be sure to only access vcpu if it was initialised.mrg
2021-03-26Implement nvmm_vcpu::stop, a race-free exit from nvmm_vcpu_run() withoutreinoud
signals. This introduces a new kernel and userland NVMM version indicating this support. Patch by Kamil Rytarowski <kamil@netbsd.org> and committed on his request.
2020-10-24Issue 64-bit versions of *XSAVE* for 64-bit amd64 programsmgorny
When calling FXSAVE, XSAVE, FXRSTOR, ... for 64-bit programs on amd64 use the 64-suffixed variant in order to include the complete FIP/FDP registers in the x87 area. The difference between the two variants is that the FXSAVE64 (new) variant represents FIP/FDP as 64-bit fields (union fp_addr.fa_64), while the legacy FXSAVE variant uses split fields: 32-bit offset, 16-bit segment and 16-bit reserved field (union fp_addr.fa_32). The latter implies that the actual addresses are truncated to 32 bits which is insufficient in modern programs. The change is applied only to 64-bit programs on amd64. Plain i386 and compat32 continue using plain FXSAVE. Similarly, NVMM is not changed as I am not familiar with that code. This is a potentially breaking change. However, I don't think it likely to actually break anything because the data provided by the old variant were not meaningful (because of the truncated pointer).
2020-09-08nvmm-x86: avoid hogging behavior observed recentlymaxv
When the FPU code got rewritten in NetBSD, the dependency on IPL_HIGH was eliminated, and I took _vcpu_guest_fpu_enter() out of the VCPU loop since there was no need to be in the splhigh window. Later, the code was switched to use the kernel FPU API, API that works at IPL_VM, not at IPL_NONE. These two changes mean that the whole VCPU loop is now executing at IPL_VM, which is not desired, because it introduces a delay in interrupt processing on the host in certain cases. Fix this by putting _vcpu_guest_fpu_enter() back inside the VCPU loop.
2020-09-08nvmm-x86-vmx: improve the handling of CR0maxv
- CR0_ET is hard-wired to 1 in the cpu, so force CR0_ET to 1 in the shadow. - Clarify.
2020-09-08nvmm: cosmetic changesmaxv
- Style. - Explicitly include ioccom.h.
2020-09-06Fix fallout from previous uvm.h cleanup.riastradh
- pmap(9) needs uvm/uvm_extern.h. - x86/pmap.h is not usable on its own; it is only usable if included via uvm/uvm_extern.h (-> uvm/uvm_pmap.h -> machine/pmap.h). - Make nvmm.h and nvmm_internal.h standalone.
2020-09-05Round of uvm.h cleanup.riastradh
The poorly named uvm.h is generally supposed to be for uvm-internal users only. - Narrow it to files that actually need it -- mostly files that need to query whether curlwp is the pagedaemon, which should maybe be exposed by an external header. - Use uvm_extern.h where feasible and uvm_*.h for things not exposed by it. We should split up uvm_extern.h but this will serve for now to reduce the uvm.h dependencies. - Use uvm_stat.h and #ifdef UVMHIST uvm.h for files that use UVMHIST(ubchist), since ubchist is declared in uvm.h but the reference evaporates if UVMHIST is not defined, so we reduce header file dependencies. - Make uvm_device.h and uvm_swap.h independently includable while here. ok chs@
2020-09-05x86: fix several CPUID flagsmaxv
- Rename: CPUID_PN -> CPUID_PSN CPUID_CFLUSH -> CPUID_CLFSH CPUID_SBF -> CPUID_PBE CPUID_LZCNT -> CPUID_ABM CPUID_P1GB -> CPUID_PAGE1GB CPUID2_PCLMUL -> CPUID2_PCLMULQDQ CPUID2_CID -> CPUID2_CNXTID CPUID2_xTPR -> CPUID2_XTPR CPUID2_AES -> CPUID2_AESNI To match the x86 specification and the other OSes. - Remove: CPUID_B10, CPUID_B20, CPUID_IA64. They do not exist.
2020-09-05x86: rename PGEX_X -> PGEX_Imaxv
To match the x86 specification and the other OSes.
2020-09-05nvmm: update copyright headersmaxv
2020-09-04nvmm-x86: improve the CPUID emulationmaxv
- Mask DTES64, DS_CPL, CID, SDBG, xTPR, PN. - B10, B20 and IA64 do not exist, so just remove them.
2020-09-04nvmm: more __read_mostlymaxv
2020-09-04nvmm-x86-vmx: improve the handling of CR0maxv
- Flush the guest TLB when certain CR0 bits change. - If the guest updates a static bit in CR0, then reflect the change in VMCS_CR0_SHADOW, for the guest to get the illusion that the change was applied. The "real" CR0 static bits remain unchanged. - In vmx_vcpu_{g,s}et_state(), take VMCS_CR0_SHADOW into account. - Slightly modify the CR4 handling code, just for more symmetry with CR0.
2020-09-04nvmm-x86-svm: check the SVM revisionmaxv
Only revision 1 exists, but check it, for future-proofness.
2020-08-29nvmm: explicitly include atomic.hmaxv
2020-08-26nvmm-x86-svm: improve the handling of MSR_EFERmaxv
Intercept reads of it as well, just to mask EFER_SVME, which the guest doesn't need to see.
2020-08-26nvmm-x86: improve the handling of RFLAGS.RFmaxv
- When injecting certain exceptions, set RF. For us to have an up-to-date view of RFLAGS, we commit the state before the event. - When advancing RIP, clear RF.
2020-08-26nvmm-x86-vmx: improve the handling of CR4maxv
- Filter out certain features we don't want the guest to enable. This is for general correctness, and future-proofness. - Flush the guest TLB when certain flags change.
2020-08-26nvmm: slightly clarifymaxv
2020-08-26nvmm-x86-svm: don't forget to intercept INVDmaxv
INVD executed in the guest can be dangerous for the host, due to CPU caches being flushed without write-back.
2020-08-26nvmm: misc improvementsmaxv
- use mach->ncpus to get the number of vcpus, now that we have it - don't forget to decrement mach->ncpus when a machine gets killed - add more __predict_false()
2020-08-22nvmm-x86-vmx: fix detection of the BIOS lockmaxv
If it's locked, ensure it's locked with VMX enabled. If it's not locked, then lock it ourselves with VMX enabled. Should fix NetBSD PR/55596.
2020-08-22nvmm-x86: hide more CPUID flags, mostly related to perf monitorsmaxv
2020-08-22nvmm-x86-svm: dedup codemaxv
2020-08-20nvmm-x86: improve the CPUID emulationmaxv
- x86-svm: explicitly handle 0x80000007 and 0x80000008. The latter contains extended features we must filter out. Apply the same in x86-vmx for symmetry. - x86-svm: explicitly handle extended leaves until 0x8000001F, and truncate to it.
2020-08-20nvmm-x86: advertise the SERIALIZE instruction, available on future CPUsmaxv
2020-08-18nvmm-x86-svm: improve the CPUID emulationmaxv
Limit the hypervisor range, and properly handle each basic leaf until 0xD.
2020-08-18nvmm: use relaxed atomics to read nmachinesmaxv
2020-08-18nvmm: localify a variable that doesn't need to be globalmaxv
2020-08-18nvmm-x86: also flush the guest TLB when CR4.{PCIDE,SMEP} changesmaxv
2020-08-11Micro-optimize: use pushq instead of pushw. To avoid LCP stalls andmaxv
unaligned stack accesses.
2020-08-11Improve the CPUID emulation on nvmm-intel:maxv
- Limit the highest extended leaf. - Limit 0x00000007 to ECX=0, for future-proofness.
2020-08-11Improve emulation of MSR_IA32_ARCH_CAPABILITIES: publish only the *_NOmaxv
bits. Initially they were the only ones there, but Intel then added other bits we aren't interested in, and they must be filtered out.
2020-08-11Hide OSPKE. NFC since the host never uses PKU, but still.maxv
2020-08-05Add CTASSERT.maxv
2020-08-05Improve the CPUID emulation:maxv
- Hide SGX*, PKU, WAITPKG, and SKINIT, because they are not supported. - Hide HLE and RTM, part of TSX. Because TSX is just too buggy and we cannot guarantee that it remains enabled in the guest (if for example the host disables TSX while the guest is running). Nobody wants this crap anyway, so bye-bye. - Advertise FSREP_MOV, because no reason to hide it.
2020-08-05Add new field definitions, and intercept everything, for future-proofness.maxv
2020-08-05Add new field definitions.maxv
2020-08-05Make it easier to understand what's going on, no functional change.maxv
2020-08-05Use ULL, to make it clear we are unsigned.maxv
2020-08-05Simplify, remove unnecessary #ifdef DIAGNOSTIC around KASSERTs.maxv
2020-08-01Put the few x86-specific structures under #ifdef __x86_64__, for clarity.maxv
2020-07-19Switch to fpu_kern_enter/leave, to prevent clobbering, now that the kernelmaxv
itself uses the fpu.
2020-07-19The TLB flush IPIs do not respect the IPL, so enforcing IPL_HIGH has nomaxv
effect. Disable interrupts earlier instead. This prevents a possible race against such IPIs.
2020-07-18Now that the IDT is per-CPU, it must be saved/restored on each CPUmaxv
independently.
2020-07-14Introduce per-cpu IDTsyamaguchi
This is realized by following modifications: - Add IDT pages and its allocation maps for each cpu in "struct cpu_info" - Load per-cpu IDTs at cpu_init_idt(struct cpu_info*) - Copy the IDT entries for cpu0 to other CPUs at attach - These are, for example, exceptions, db, system calls, etc. And, added a kernel option named PCPU_IDT to enable the feature.
2020-07-03Print the backend name when attaching.maxv
2020-06-25Register NVMM as an actual pseudo-device. Without PMF handler, tomaxv
explicitly disallow ACPI suspend if NVMM is running. Should fix PR/55406.
2020-06-18stylemaxv