| Age | Commit message (Collapse) | Author |
|
|
|
|
|
|
|
|
|
ixgbe.c rev. 1.298 added total values kept in evcnt(9) instead of
incremental values read from registers. Fix it.
|
|
4.15.2.1 is device-initiated resume, but we are doing host-initiated.
No functional change.
|
|
|
|
Use sc->sc_lock over individual I/O transactions, not open/close of
the whole device. This way there is a bounded time before the tpm is
unbusied even if userland is getting at it, so userland can't hold up
suspend indefinitely. Of course, the tpm might be suspended and
resumed in the middle of the user's session this way -- tough.
This limits the response buffer to 1024 bytes -- which is already a
bit hefty to have on the stack (but it's probably not very deep on
the stack from userland so maybe not a big deal). If it turns out we
need more, we can use kmem to allocate a buffer on the heap, with the
caveat that it might fail. This is necessary so that suspend doesn't
block indefinitely on uiomove in tpmread.
|
|
cv_broadcast already has a fast path for the no-waiter case.
|
|
|
|
SDHC_FLAG_HOSTCAPS means that the driver has to supply both caps and caps2
values.
|
|
RK356x has a DesignWare eMMC controller that is somewhat SDHCI compliant,
with one major problem -- the clock divisor doesn't actually work. To
change the clock card on Rockchip SoCs, the clock frequency needs to be
adjusted in the Clock & Reset Unit (CRU) directly.
The RK356x UEFI implementation introduces a DSM that allows drivers to
request firmware assistance in setting the card clock rate, for instances
like this where the divisor is broken.
From the UEFI README:
Function 1: Set Card Clock
The _DSM control method parameters for the Set Card Clock function are
as follows:
Arguments
* Arg0: UUID = 434addb0-8ff3-49d5-a724-95844b79ad1f
* Arg1: Revision = 0
* Arg2: Function Index = 1
* Arg3: Target card clock rate in Hz.
Return
The actual card clock rate in Hz. Will be less than or equal to the
target clock rate. Returns 0 if the target clock rate could not be set.
|
|
|
|
|
|
|
|
|
|
|
|
Access to the softc and hidms state is currently kernel-locked.
|
|
Need this to serialize access to sc_state, sc_refcnt.
XXX Should harmonize this with uhidev(4) and tighten assertions.
|
|
|
|
Limited to 64k and only happens on attach anyway. Let's not leave a
rake to trip on here.
|
|
- Can't run iic_exec in softint because it does cv_wait, at least on
some i2c controllers -- defer to workqueue instead.
- Fix violations of locking rules:
. Do not take a lock at higher IPL than it is defined at!
. Do not sleep under a lock!
. Definitely do not sleep under a spin lock!
In this case, sc_intr_lock was defined at IPL_VM but used at IPL_TTY,
and i2c transactions -- possibly causing sleep for cv_wait -- were
issued under it.
But in this case, the interrupt handler needs only a single bit to
mark whether the work is pending, so just use atomic_swap for that.
- Use an adaptive lock (IPL_NONE) for i2c transactions.
- Detach children, and do so before freeing anything.
|
|
Mark the sections that are conventionally separate files for hardware
interface (*reg.h) versus software state (*var.h).
|
|
|
|
|
|
|
|
|
|
|
|
For the benefit of GEDs backed by level interrupts, mask the interrupt
source before dispatching the handler to a worker thread and unmask it
after it has been handled.
|
|
|
|
Don't try to be clever and count -- just use bInterfaceNumber.
The previous logic to count interface descriptors failed to consider
interfaces with alternate settings, which led it to pass an invalid
interface number to usbd_device2interface_handle.
It is simpler to just use the recorded bInterfaceNumber, which is
guaranteed by the USB spec to be zero-indexed and below
bNumInterfaces as we need.
|
|
|
|
|
|
|
|
drain a couple of registers that want either a read or a write-1-to-
clear bit, and keep track of how many happen via evcnt.
i had this trigger one time, but not since adding instrumentation to
see exactly it was saying (the GMAC_MTL_INTERRUPT_STATUS_Q0IS bit was
set, and it requires some handling now implemented.)
ok jmcneill
|
|
there's basic interrupt evcnt, which is the parent for the rx and
tx interrupts, and 3 status interrupts, one of which has 7 more
subtypes (watchdog timeout, carrier missing/lost, etc.) as these
cases are evcnt counted now, make some debugging default off.
avoid removing bits from dma_status when rx/tx is handled, so that
later check of dma_status for non-zero does not trip. the two bits
in dma_status removed are never checked again besides the test that
may have failed (but probably doesn't as at least one other bit in
two other variables will be set.)
ok jmcneill
|
|
|
|
Without this change the LEDs would get stuck on until the first
keypress. (This also seemed to trigger a crash in heavy load on
bringing aue(4) up and down over and over again while unplugging, but
I'm not sure why and I hope it's not actually related...)
|
|
|
|
of hdaudioverbose module.
|
|
|
|
- Fix previous again. The missing comma is intended to split the long line.
- Add missing right parenthesis.
|
|
|
|
|
|
IEEE 802.3 clause 22's PHY device has a link status bit in the BMCR
register, but it's required to read twice to get the correct value.
Almost all PHY devices have the vendor specific register which has
the link status bit that it's not required to read twice. makphy(4)
use the bit in the PSSR register to reduce the access cost.
QEMU's e1000 provides the PHY specific status register at 0x11 but the
link indication bit (PSSR_LINK.) is always 1 because
e1000x_update_regs_on_link_{down,up}() modify MII_SR_LINK_STATUS
(BMSR_LINK in NetBSD) but don't modify PSSR_LINK. It causes
"virsh domif-setlink xxx yyy down" doesn't work.
To avoid this problem, read the BMSR and check the BMSR_LINK bit. Add
MAKPHY_QUIRK_PSSR_LINK bit for this quirk. Set it if MII_EXTSR doesn't
exist because it's one of the case of QEMU.
Found and tested by ozaki-r.
|
|
|
|
|
|
|
|
Externally, wsdisplay only needs wsemul_vt100_ops. Internally (as
vt100 emulation is split into several files) wsemul_vt100_subr.c needs
wsemul_vt100_reset().
|
|
|