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2022-01-17s/0xffffffff/UINT32_MAX/ in bus_dmatag_subregion callskrll
2022-01-17Add UQ_HID_IGNORE for the Microchip PICkit2 and 3 programmers.bouyer
2022-01-17Regen: Add the Microchip PICkit3 programmerbouyer
2022-01-17Add the Microchip PICkit3 programmerbouyer
2022-01-17Fix ierror counting again.msaitoh
ixgbe.c rev. 1.298 added total values kept in evcnt(9) instead of incremental values read from registers. Fix it.
2022-01-16xhci(4): Fix citation in comment.riastradh
4.15.2.1 is device-initiated resume, but we are doing host-initiated. No functional change.
2022-01-16xhci(4): Fix copypasto in resume error message.riastradh
2022-01-16tpm(4): Fix suspend and rework I/O transaction lock.riastradh
Use sc->sc_lock over individual I/O transactions, not open/close of the whole device. This way there is a bounded time before the tpm is unbusied even if userland is getting at it, so userland can't hold up suspend indefinitely. Of course, the tpm might be suspended and resumed in the middle of the user's session this way -- tough. This limits the response buffer to 1024 bytes -- which is already a bit hefty to have on the stack (but it's probably not very deep on the stack from userland so maybe not a big deal). If it turns out we need more, we can use kmem to allocate a buffer on the heap, with the caveat that it might fail. This is necessary so that suspend doesn't block indefinitely on uiomove in tpmread.
2022-01-15dk(4): Omit redundant microoptimization around cv_broadcast.riastradh
cv_broadcast already has a fast path for the no-waiter case.
2022-01-1532-bit build fixjmcneill
2022-01-15acpi: sdhc: Read caps2 even if sdhci-caps{,-mask} doesn't touch the bitsjmcneill
SDHC_FLAG_HOSTCAPS means that the driver has to supply both caps and caps2 values.
2022-01-15acpi: sdhc: Add support for RK356x eMMC controller.jmcneill
RK356x has a DesignWare eMMC controller that is somewhat SDHCI compliant, with one major problem -- the clock divisor doesn't actually work. To change the clock card on Rockchip SoCs, the clock frequency needs to be adjusted in the Clock & Reset Unit (CRU) directly. The RK356x UEFI implementation introduces a DSM that allows drivers to request firmware assistance in setting the card clock rate, for instances like this where the divisor is broken. From the UEFI README: Function 1: Set Card Clock The _DSM control method parameters for the Set Card Clock function are as follows: Arguments * Arg0: UUID = 434addb0-8ff3-49d5-a724-95844b79ad1f * Arg1: Revision = 0 * Arg2: Function Index = 1 * Arg3: Target card clock rate in Hz. Return The actual card clock rate in Hz. Will be less than or equal to the target clock rate. Returns 0 if the target clock rate could not be set.
2022-01-15acpi: Add helper for querying DSM function 0.jmcneill
2022-01-15sdhc: High speed support capability flag applies to eMMC too.jmcneill
2022-01-15Trailing whitespaceskrll
2022-01-14ihidev(4): Prohibit closing an unopened ihidev.riastradh
2022-01-14ihidev(4): Avoid reference count overflow.riastradh
2022-01-14ims(4): Sprinkle KERNEL_LOCKED_P assertions.riastradh
Access to the softc and hidms state is currently kernel-locked.
2022-01-14ihidev(4): Take the lock for ihidev_open, ihidev_close.riastradh
Need this to serialize access to sc_state, sc_refcnt. XXX Should harmonize this with uhidev(4) and tighten assertions.
2022-01-14ihidev(4): Check kmem_alloc(..., KM_NOSLEEP) for failure.riastradh
2022-01-14ihidev(4): Allocate report buffer with KM_SLEEP.riastradh
Limited to 64k and only happens on attach anyway. Let's not leave a rake to trip on here.
2022-01-14ihidev(4): Fix locking and interrupt handler.riastradh
- Can't run iic_exec in softint because it does cv_wait, at least on some i2c controllers -- defer to workqueue instead. - Fix violations of locking rules: . Do not take a lock at higher IPL than it is defined at! . Do not sleep under a lock! . Definitely do not sleep under a spin lock! In this case, sc_intr_lock was defined at IPL_VM but used at IPL_TTY, and i2c transactions -- possibly causing sleep for cv_wait -- were issued under it. But in this case, the interrupt handler needs only a single bit to mark whether the work is pending, so just use atomic_swap for that. - Use an adaptive lock (IPL_NONE) for i2c transactions. - Detach children, and do so before freeing anything.
2022-01-14ihidev(4): Add missing includes and header guard.riastradh
Mark the sections that are conventionally separate files for hardware interface (*reg.h) versus software state (*var.h).
2022-01-14Formatting. NFCI.skrll
2022-01-12Ignore new APC UPS devices when matching uhid devices.martin
2022-01-12regen (new APC UPS device id)martin
2022-01-12Add a new APC UPS device id.martin
2022-01-11acpi: sdhc: Support sdhci-caps and sdhci-caps-mask properties.jmcneill
2022-01-11acpi: ged: Mask interrupts before dispatching handlerjmcneill
For the benefit of GEDs backed by level interrupts, mask the interrupt source before dispatching the handler to a worker thread and unmask it after it has been handled.
2022-01-10Typo in a commentkhorben
2022-01-09uvideo(4): Fix USB interface numbering.riastradh
Don't try to be clever and count -- just use bInterfaceNumber. The previous logic to count interface descriptors failed to consider interfaces with alternate settings, which led it to pass an invalid interface number to usbd_device2interface_handle. It is simpler to just use the recorded bInterfaceNumber, which is guaranteed by the USB spec to be zero-indexed and below bNumInterfaces as we need.
2022-01-09dwcmmc: Add ACPI attach supportjmcneill
2022-01-09dwcmmc: Add support for card detect using SDMMC_CDETECT registerjmcneill
2022-01-09acpi: Add acpi_dsd_bool helperjmcneill
2022-01-09eqos: handle the GMAC_MTL_INTERRUPT_STATUS register having somethingmrg
drain a couple of registers that want either a read or a write-1-to- clear bit, and keep track of how many happen via evcnt. i had this trigger one time, but not since adding instrumentation to see exactly it was saying (the GMAC_MTL_INTERRUPT_STATUS_Q0IS bit was set, and it requires some handling now implemented.) ok jmcneill
2022-01-08eqos: interrupt evcnt and minor fixmrg
there's basic interrupt evcnt, which is the parent for the rx and tx interrupts, and 3 status interrupts, one of which has 7 more subtypes (watchdog timeout, carrier missing/lost, etc.) as these cases are evcnt counted now, make some debugging default off. avoid removing bits from dma_status when rx/tx is handled, so that later check of dma_status for non-zero does not trip. the two bits in dma_status removed are never checked again besides the test that may have failed (but probably doesn't as at least one other bit in two other variables will be set.) ok jmcneill
2022-01-08urlphy(4): Fix missing mii locking in urlphy_attach.riastradh
2022-01-08ukbd(4): Fix previous change to initial LED flashing.riastradh
Without this change the LEDs would get stuck on until the first keypress. (This also seemed to trigger a crash in heavy load on bringing aue(4) up and down over and over again while unplugging, but I'm not sure why and I hope it's not actually related...)
2022-01-08place additional parens around multiline string constant to appease clangtnn
2022-01-07Safe vendor/product for reporting. Avoids repeated loading/unloadingmlelstv
of hdaudioverbose module.
2022-01-07Calculate the minimum address, don't assume the first entry is the start.mlelstv
2022-01-07Two fixes:msaitoh
- Fix previous again. The missing comma is intended to split the long line. - Add missing right parenthesis.
2022-01-07Add missing comma. Found by tnn@.msaitoh
2022-01-07acpibat(4): Fix race in detach with AcpiOsExecute deferred call.riastradh
2022-01-06QEMU e1000's PHY code doesn't reflect the PSSR_LINK bit. Do workaround.msaitoh
IEEE 802.3 clause 22's PHY device has a link status bit in the BMCR register, but it's required to read twice to get the correct value. Almost all PHY devices have the vendor specific register which has the link status bit that it's not required to read twice. makphy(4) use the bit in the PSSR register to reduce the access cost. QEMU's e1000 provides the PHY specific status register at 0x11 but the link indication bit (PSSR_LINK.) is always 1 because e1000x_update_regs_on_link_{down,up}() modify MII_SR_LINK_STATUS (BMSR_LINK in NetBSD) but don't modify PSSR_LINK. It causes "virsh domif-setlink xxx yyy down" doesn't work. To avoid this problem, read the BMSR and check the BMSR_LINK bit. Add MAKPHY_QUIRK_PSSR_LINK bit for this quirk. Set it if MII_EXTSR doesn't exist because it's one of the case of QEMU. Found and tested by ozaki-r.
2022-01-05fix typos, mainly s/comand/command/andvar
2022-01-03Add driver for DesignWare Ethernet Quality-of-Service controller.jmcneill
2022-01-03Add driver for Motorcomm YT8511 GbE PHYjmcneill
2022-01-02wsemul_vt100.c - make static everything that can be staticuwe
Externally, wsdisplay only needs wsemul_vt100_ops. Internally (as vt100 emulation is split into several files) wsemul_vt100_subr.c needs wsemul_vt100_reset().
2022-01-01fix typos in word "diagnostic".andvar