From a2c8fc94fe22fb5e35ed95e1dfdae5693f577e48 Mon Sep 17 00:00:00 2001 From: thorpej Date: Thu, 29 Nov 2001 17:14:02 +0000 Subject: Provide a way for platforms to move away from the old RiscPC-centric interrupt code. Garbage-collect some unused stuff. --- sys/arch/arm/arm32/cpuswitch.S | 34 +++++++--------------------------- 1 file changed, 7 insertions(+), 27 deletions(-) (limited to 'sys') diff --git a/sys/arch/arm/arm32/cpuswitch.S b/sys/arch/arm/arm32/cpuswitch.S index 3e2213442fa..e91dca7a5b9 100644 --- a/sys/arch/arm/arm32/cpuswitch.S +++ b/sys/arch/arm/arm32/cpuswitch.S @@ -1,4 +1,4 @@ -/* $NetBSD: cpuswitch.S,v 1.4 2001/11/19 20:38:58 chris Exp $ */ +/* $NetBSD: cpuswitch.S,v 1.5 2001/11/29 17:14:02 thorpej Exp $ */ /* * Copyright (c) 1994-1998 Mark Brinicombe. @@ -290,12 +290,17 @@ ENTRY(cpu_switch) /* Lower the spl level to spl0 and get the current spl level. */ mov r7, r1 +#ifdef __NEWINTR + mov r0, #(IPL_NONE) + bl _C_LABEL(_spllower) +#else /* ! __NEWINTR */ #ifdef spl0 mov r0, #(_SPL_0) bl _C_LABEL(splx) #else bl _C_LABEL(spl0) -#endif +#endif /* spl0 */ +#endif /* __NEWINTR */ /* Push the old spl level onto the stack */ str r0, [sp, #-0x0004]! @@ -322,28 +327,6 @@ sw1: /* rem: r3 = whichqs */ /* rem: interrupts are disabled */ - /* - * Paranoid debug time .... - * Is this overkill ? If we are not in SVC mode then things are - * very sick and will probably have already died. - */ -#if 0 - mrs r4, cpsr_all - and r4, r4, #(PSR_MODE) - teq r4, #(PSR_SVC32_MODE) - beq switchmodeok - - add r0, pc, #switchpanic - . - 8 - mrs r1, cpsr_all - bl _C_LABEL(panic) - -switchpanic: - .asciz "Yikes! In cpu_switch() but not in SVC mode (%08x)\n" - .align 0 - -switchmodeok: -#endif - /* * We have found an active queue. Currently we do not know which queue * is active just that one of them is. @@ -653,9 +636,6 @@ Lse_context_switched: ldr r1, Lproc0 b switch_search -Lcurrent_spl_level: - .word _C_LABEL(current_spl_level) - ENTRY(savectx) /* * r0 = pcb -- cgit