./attr_print: send attr number = 4711 ./attr_print: send attr string = whoopee ./attr_print: send attr name foo-name value foo-value ./attr_print: send attr name bar-name value bar-value ./attr_print: send attr number = 4711 ./attr_print: send attr string = whoopee ./attr_scan: unknown_stream: wanted attribute: number ./attr_scan: input attribute name: number ./attr_scan: input attribute value: 4711 ./attr_scan: unknown_stream: wanted attribute: string ./attr_scan: input attribute name: string ./attr_scan: input attribute value: whoopee ./attr_scan: unknown_stream: wanted attribute: (any attribute name or list terminator) ./attr_scan: input attribute name: foo-name ./attr_scan: input attribute value: foo-value ./attr_scan: unknown_stream: wanted attribute: (any attribute name or list terminator) ./attr_scan: input attribute name: bar-name ./attr_scan: input attribute value: bar-value ./attr_scan: unknown_stream: wanted attribute: (any attribute name or list terminator) ./attr_scan: input attribute name: (end) ./attr_scan: unknown_stream: wanted attribute: number ./attr_scan: input attribute name: number ./attr_scan: input attribute value: 4711 ./attr_scan: unknown_stream: wanted attribute: string ./attr_scan: input attribute name: string ./attr_scan: input attribute value: whoopee ./attr_scan: unknown_stream: wanted attribute: (list terminator) ./attr_scan: input attribute name: (end) number 4711 string whoopee (hash) foo-name foo-value (hash) bar-name bar-value number 4711 string whoopee (hash) foo-name foo-value (hash) bar-name bar-value a48a309936c70c6ae3cda17034d0ecbef46'>commitdiff
path: root/sys/arch/x86/include/cacheinfo.h
AgeCommit message (Expand)Author
2013-10-28Support prefetch size.msaitoh
2013-09-14Add Shared L2 TLB and some cache and tlb entries from the latest document.msaitoh
2013-07-17 Add some new TLB and cache entries from document (Table 3-22 Encoding of CPUIDmsaitoh
2013-07-17 Fix 0x0d's DCACHE entry and 0xeb's L3CACHE entry from the documentmsaitoh
2011-12-04add info on L2 TLBs and 1GB pages.chs
2009-05-13Fix toyp in previous. Pointed out by snj@pgoyette
2009-05-131. Extend CPU probe of Intel processors to handle extended-models. Thispgoyette
2009-04-15Constify a userland-only member.lukem
2008-05-30don't undef __CI_TBL before we use it :-)christos
2008-05-30- fix an amd cache entry.christos
2008-05-30PR/38722: Paul Goyette: Share cacheinfo informationchristos
2008-05-11print L3 and TLB cache information for AMD Barcelona/Phenomcegger
2008-05-11Simplify x86 identcpu code, and share between i386/amd64.ad
2005-04-16make multi inclusion protection macros consistent.yamt
2004-08-17Get correct cache information for earlier VIA C3 models.briggs
2004-08-08VIA C3 cache info.briggs
2003-04-25Share some common cache info cpuid code between i386 and x86_64.fvdl