diff options
| author | toddpw <toddpw@NetBSD.org> | 2000-07-25 09:57:59 +0000 |
|---|---|---|
| committer | toddpw <toddpw@NetBSD.org> | 2000-07-25 09:57:59 +0000 |
| commit | 6c80daae8d14127c4e87acbee23c796fce8970b3 (patch) | |
| tree | f75f741ca00977d7cb33cb56805afa6479de3f51 | |
| parent | b38bba4202f81746155ad970275f0317c4bb3055 (diff) | |
Ignore all undefined bits in the Tadpole microcontroller status register.
Only the low nibble is defined, and on at least one 3gx (mine) there is an
undefined bit which reads as a one -- bit 6 (0x40). This screwed tctrl_intr()
which would loop forever, thinking it always had new events to process.
| -rw-r--r-- | sys/arch/sparc/dev/tctrl.c | 4 | ||||
| -rw-r--r-- | sys/arch/sparc/dev/ts102reg.h | 3 |
2 files changed, 4 insertions, 3 deletions
diff --git a/sys/arch/sparc/dev/tctrl.c b/sys/arch/sparc/dev/tctrl.c index 570493f0477..754cd6574cb 100644 --- a/sys/arch/sparc/dev/tctrl.c +++ b/sys/arch/sparc/dev/tctrl.c @@ -1,4 +1,4 @@ -/* $NetBSD: tctrl.c,v 1.11 2000/07/09 20:57:47 pk Exp $ */ +/* $NetBSD: tctrl.c,v 1.12 2000/07/25 09:57:59 toddpw Exp $ */ /*- * Copyright (c) 1998 The NetBSD Foundation, Inc. @@ -269,7 +269,7 @@ tctrl_intr(arg) again: /* find out the cause(s) of the interrupt */ - v = tctrl_read(sc, TS102_REG_UCTRL_STS); + v = tctrl_read(sc, TS102_REG_UCTRL_STS) & TS102_UCTRL_STS_MASK; /* clear the cause(s) of the interrupt */ tctrl_write(sc, TS102_REG_UCTRL_STS, v); diff --git a/sys/arch/sparc/dev/ts102reg.h b/sys/arch/sparc/dev/ts102reg.h index 2a0154b90d6..91e491eec76 100644 --- a/sys/arch/sparc/dev/ts102reg.h +++ b/sys/arch/sparc/dev/ts102reg.h @@ -1,4 +1,4 @@ -/* $NetBSD: ts102reg.h,v 1.5 2000/03/09 07:04:10 garbled Exp $ */ +/* $NetBSD: ts102reg.h,v 1.6 2000/07/25 09:57:59 toddpw Exp $ */ /*- * Copyright (c) 1998 The NetBSD Foundation, Inc. @@ -164,6 +164,7 @@ #define TS102_UCTRL_STS_TXNF_STA 0x02 /* transmit FIFO not full */ #define TS102_UCTRL_STS_RXNE_STA 0x04 /* receive FIFO not empty */ #define TS102_UCTRL_STS_RXO_STA 0x08 /* receive FIFO overflow */ +#define TS102_UCTRL_STS_MASK 0x0F /* Only 4 bits significant */ enum ts102_opcode { /* Argument Returned */ TS102_OP_RD_SERIAL_NUM=0x01, /* none ack + 4 bytes */ |
