diff options
| author | nisimura <nisimura@NetBSD.org> | 2000-05-10 01:34:13 +0000 |
|---|---|---|
| committer | nisimura <nisimura@NetBSD.org> | 2000-05-10 01:34:13 +0000 |
| commit | de13b44eddbc2c30bcbd1fba4e6752e3ae09b181 (patch) | |
| tree | aec588f2f766af059b5663dacd82dbab1f7ab70c | |
| parent | b3c4ed6cf71b43b02093be5fa2ba10b22dee72e8 (diff) | |
Have mips_locoresw[] of 3 entry pointer array for different
implementation of locore routines between MIPS1 and MIPS3. It's
independent from mips_locore_jumpvec_t which is for cache/TLB
manipulating routines peculiar to processor designs. mips_locore_jumpvec_t
will be replaced with "processor closures" encapsulating implementation
parameters (cpuinfo) and pointers to conventaion routines (cpuops),
eventually.
| -rw-r--r-- | sys/arch/mips/include/locore.h | 33 | ||||
| -rw-r--r-- | sys/arch/mips/mips/genassym.cf | 6 | ||||
| -rw-r--r-- | sys/arch/mips/mips/locore.S | 8 | ||||
| -rw-r--r-- | sys/arch/mips/mips/locore_mips1.S | 9 | ||||
| -rw-r--r-- | sys/arch/mips/mips/locore_mips3.S | 8 | ||||
| -rw-r--r-- | sys/arch/mips/mips/mips_machdep.c | 18 |
6 files changed, 49 insertions, 33 deletions
diff --git a/sys/arch/mips/include/locore.h b/sys/arch/mips/include/locore.h index 5a7a92c8e69..f8df1a79cfc 100644 --- a/sys/arch/mips/include/locore.h +++ b/sys/arch/mips/include/locore.h @@ -1,4 +1,4 @@ -/* $NetBSD: locore.h,v 1.30 2000/04/12 01:05:34 nisimura Exp $ */ +/* $NetBSD: locore.h,v 1.31 2000/05/10 01:34:13 nisimura Exp $ */ /* * Copyright 1996 The Board of Trustees of The Leland Stanford @@ -24,10 +24,6 @@ * MachFlushDCache * MachFlushICache * MachForceCacheUpdate - * MachSetPID - * MachTLBFlush - * MachTLBFlushAddr - * MachTLBUpdate * wbflush * proc_trampoline() * cpu_switch_resume() @@ -52,7 +48,6 @@ u_int32_t mips_read_causereg __P((void)); u_int32_t mips_read_statusreg __P((void)); -void mips_idle __P((void)); void mips1_ConfigCache __P((void)); void mips1_FlushCache __P((void)); @@ -64,6 +59,7 @@ void mips1_SetPID __P((int pid)); void mips1_TBIA __P((int)); void mips1_TBIAP __P((int)); void mips1_TBIS __P((vaddr_t)); +void mips1_TBRPL __P((vaddr_t, vaddr_t, paddr_t)); int mips1_TLBUpdate __P((u_int, /*pt_entry_t*/ u_int)); void mips1_wbflush __P((void)); @@ -81,6 +77,7 @@ void mips3_SetPID __P((int pid)); void mips3_TBIA __P((int)); void mips3_TBIAP __P((int)); void mips3_TBIS __P((vaddr_t)); +void mips3_TBRPL __P((vaddr_t, vaddr_t, paddr_t)); int mips3_TLBUpdate __P((u_int, /*pt_entry_t*/ u_int)); struct tlb; void mips3_TLBRead __P((int, struct tlb *)); @@ -119,13 +116,11 @@ typedef struct { void (*flushICache) __P((vaddr_t addr, vsize_t len)); void (*forceCacheUpdate) __P((void)); void (*setTLBpid) __P((int pid)); - void (*tlbFlush) __P((int numtlb)); - void (*tlbFlushAddr) __P((vaddr_t)); /* XXX Really pte highpart ? */ - int (*tlbUpdate) __P((u_int highreg, u_int lowreg)); + void (*TBIAP) __P((int)); + void (*TBIS) __P((vaddr_t)); + void (*TBRPL) __P((vaddr_t, vaddr_t, paddr_t)); + int (*tlbUpdate) __P((u_int highreg, u_int lowreg)); void (*wbflush) __P((void)); - void (*proc_trampoline) __P((void)); - void (*cpu_switch_resume) __P((void)); - void (*cpu_idle) __P((void)); } mips_locore_jumpvec_t; /* Override writebuffer-drain method. */ @@ -144,6 +139,7 @@ void logstacktrace __P((void)); extern mips_locore_jumpvec_t mips_locore_jumpvec; extern mips_locore_jumpvec_t r2000_locore_vec; extern mips_locore_jumpvec_t r4000_locore_vec; +extern long *mips_locoresw[]; #if defined(MIPS3) && !defined (MIPS1) #if defined(MIPS3_L2CACHE_ABSENT) && defined(MIPS3_5200) @@ -167,6 +163,7 @@ extern mips_locore_jumpvec_t r4000_locore_vec; #define MachSetPID mips3_SetPID #define MIPS_TBIAP() mips3_TBIAP(mips_num_tlb_entries) #define MIPS_TBIS mips3_TBIS +#define MIPS_TBRPL mips3_TBRPL #define MachTLBUpdate mips3_TLBUpdate #define wbflush() mips3_wbflush() #define proc_trampoline mips3_proc_trampoline @@ -180,6 +177,7 @@ extern mips_locore_jumpvec_t r4000_locore_vec; #define MachSetPID mips1_SetPID #define MIPS_TBIAP() mips1_TBIAP(mips_num_tlb_entries) #define MIPS_TBIS mips1_TBIS +#define MIPS_TBRPL mips1_TBRPL #define MachTLBUpdate mips1_TLBUpdate #define wbflush() mips1_wbflush() #define proc_trampoline mips1_proc_trampoline @@ -193,14 +191,17 @@ extern mips_locore_jumpvec_t r4000_locore_vec; #define MachFlushICache (*(mips_locore_jumpvec.flushICache)) #define MachForceCacheUpdate (*(mips_locore_jumpvec.forceCacheUpdate)) #define MachSetPID (*(mips_locore_jumpvec.setTLBpid)) -#define MIPS_TBIAP() (*(mips_locore_jumpvec.tlbFlush))(mips_num_tlb_entries) -#define MIPS_TBIS (*(mips_locore_jumpvec.tlbFlushAddr)) +#define MIPS_TBIAP() (*(mips_locore_jumpvec.TBIAP))(mips_num_tlb_entries) +#define MIPS_TBIS (*(mips_locore_jumpvec.TBIS)) +#define MIPS_TBRPL (*(mips_locore_jumpvec.TBRPL)) #define MachTLBUpdate (*(mips_locore_jumpvec.tlbUpdate)) -#define wbflush() (*(mips_locore_jumpvec.wbflush))() -#define proc_trampoline (mips_locore_jumpvec.proc_trampoline) #define MachHitFlushDCache mips3_HitFlushDCache +#define wbflush() (*(mips_locore_jumpvec.wbflush))() +#define proc_trampoline (mips_locoresw[1]) #endif +#define CPU_IDLE (mips_locoresw[2]) + /* cpu_switch_resume is called inside locore.S */ /* diff --git a/sys/arch/mips/mips/genassym.cf b/sys/arch/mips/mips/genassym.cf index 3a180567194..8a7cad3be56 100644 --- a/sys/arch/mips/mips/genassym.cf +++ b/sys/arch/mips/mips/genassym.cf @@ -1,4 +1,4 @@ -# $NetBSD: genassym.cf,v 1.16 2000/04/30 22:56:12 simonb Exp $ +# $NetBSD: genassym.cf,v 1.17 2000/05/10 01:34:14 nisimura Exp $ # # Copyright (c) 1997 # Jonathan Stone. All rights reserved. @@ -81,8 +81,8 @@ define SIGILL SIGILL define SIGSEGV SIGSEGV define MIPSX_FLUSHICACHE offsetof(mips_locore_jumpvec_t, flushICache) -define MIPSX_CPU_SWITCH_RESUME offsetof(mips_locore_jumpvec_t, cpu_switch_resume) -define MIPSX_CPU_IDLE offsetof(mips_locore_jumpvec_t, cpu_idle) +define MIPSX_CPU_SWITCH_RESUME sizeof(long *) * 0 +define MIPSX_CPU_IDLE sizeof(long *) * 2 define MIPS1_PG_G MIPS1_PG_G define MIPS1_PG_V MIPS1_PG_V diff --git a/sys/arch/mips/mips/locore.S b/sys/arch/mips/mips/locore.S index a8300f1fef5..b37f58df8b3 100644 --- a/sys/arch/mips/mips/locore.S +++ b/sys/arch/mips/mips/locore.S @@ -1,4 +1,4 @@ -/* $NetBSD: locore.S,v 1.96 2000/04/30 23:01:24 simonb Exp $ */ +/* $NetBSD: locore.S,v 1.97 2000/05/10 01:34:14 nisimura Exp $ */ /* * Copyright (c) 1992, 1993 @@ -311,7 +311,7 @@ NESTED(cpu_switch, CALLFRAME_SIZ, ra) addu t0, t0, 1 sw t0, uvmexp+UVMEXP_SWTCH bne t1, zero, 1f - lw t2, _C_LABEL(mips_locore_jumpvec) + MIPSX_CPU_IDLE + lw t2, _C_LABEL(mips_locoresw) + MIPSX_CPU_IDLE nop # for r2000/r3000 jal ra, t2 nop @@ -330,7 +330,7 @@ cpu_switch_queuescan: lw t0, _C_LABEL(whichqs) # look for non-empty queue li t2, -1 # t2 = lowest bit set bne t0, zero, 1f - lw t3, _C_LABEL(mips_locore_jumpvec) + MIPSX_CPU_IDLE + lw t3, _C_LABEL(mips_locoresw) + MIPSX_CPU_IDLE nop # for r2000/r3000 jal ra, t3 nop @@ -365,7 +365,7 @@ cpu_switch_queuescan: /* * Switch to new context. */ - lw t2, _C_LABEL(mips_locore_jumpvec) + MIPSX_CPU_SWITCH_RESUME + lw t2, _C_LABEL(mips_locoresw) + MIPSX_CPU_SWITCH_RESUME sw a0, _C_LABEL(curproc) jal ra, t2 move s7, a0 # -BDSLOT- diff --git a/sys/arch/mips/mips/locore_mips1.S b/sys/arch/mips/mips/locore_mips1.S index 3908212991c..10cf1e59643 100644 --- a/sys/arch/mips/mips/locore_mips1.S +++ b/sys/arch/mips/mips/locore_mips1.S @@ -1,4 +1,4 @@ -/* $NetBSD: locore_mips1.S,v 1.30 2000/04/16 09:00:26 nisimura Exp $ */ +/* $NetBSD: locore_mips1.S,v 1.31 2000/05/10 01:34:14 nisimura Exp $ */ /* * Copyright (c) 1992, 1993 @@ -1687,6 +1687,13 @@ LEAF(mips1_TBRPL) END(mips1_TBRPL) .data + + .globl _C_LABEL(mips1_locoresw) +_C_LABEL(mips1_locoresw): + .word _C_LABEL(mips1_cpu_switch_resume) + .word _C_LABEL(mips1_proc_trampoline) + .word _C_LABEL(mips_idle) + mips1_excausesw: #### #### The kernel exception handlers. diff --git a/sys/arch/mips/mips/locore_mips3.S b/sys/arch/mips/mips/locore_mips3.S index 04983d750a8..a786514d25b 100644 --- a/sys/arch/mips/mips/locore_mips3.S +++ b/sys/arch/mips/mips/locore_mips3.S @@ -1,4 +1,4 @@ -/* $NetBSD: locore_mips3.S,v 1.26 2000/05/09 09:50:17 nisimura Exp $ */ +/* $NetBSD: locore_mips3.S,v 1.27 2000/05/10 01:34:15 nisimura Exp $ */ /* * Copyright (c) 1997 Jonathan Stone (hereinafter referred to as the author) @@ -2606,6 +2606,12 @@ _C_LABEL(mips3_cacheflush_bug): .word 0 .data + .globl _C_LABEL(mips3_locoresw) +_C_LABEL(mips3_locoresw): + .word _C_LABEL(mips3_cpu_switch_resume) + .word _C_LABEL(mips3_proc_trampoline) + .word _C_LABEL(mips_idle) + _C_LABEL(mips3_excpt_sw): #### #### The kernel exception handlers. diff --git a/sys/arch/mips/mips/mips_machdep.c b/sys/arch/mips/mips/mips_machdep.c index 16dc06fe422..5579a941bf2 100644 --- a/sys/arch/mips/mips/mips_machdep.c +++ b/sys/arch/mips/mips/mips_machdep.c @@ -1,4 +1,4 @@ -/* $NetBSD: mips_machdep.c,v 1.76 2000/04/12 01:05:35 nisimura Exp $ */ +/* $NetBSD: mips_machdep.c,v 1.77 2000/05/10 01:34:15 nisimura Exp $ */ /*- * Copyright (c) 1998 The NetBSD Foundation, Inc. @@ -52,7 +52,7 @@ #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ -__KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.76 2000/04/12 01:05:35 nisimura Exp $"); +__KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.77 2000/05/10 01:34:15 nisimura Exp $"); #include "opt_compat_netbsd.h" #include "opt_compat_ultrix.h" @@ -101,6 +101,10 @@ static void mips3_vector_init __P((void)); mips_locore_jumpvec_t mips_locore_jumpvec; +long *mips_locoresw[3]; +extern long *mips1_locoresw[]; /* locore_mips1.S */ +extern long *mips3_locoresw[]; /* locore_mips3.S */ + int cpu_mhz; int mips_num_tlb_entries; @@ -136,11 +140,9 @@ mips_locore_jumpvec_t mips1_locore_vec = mips1_SetPID, mips1_TBIAP, mips1_TBIS, + mips1_TBRPL, mips1_TLBUpdate, mips1_wbflush, - mips1_proc_trampoline, - mips1_cpu_switch_resume, - mips_idle }; static void @@ -194,11 +196,9 @@ mips_locore_jumpvec_t mips3_locore_vec = mips3_SetPID, mips3_TBIAP, mips3_TBIS, + mips3_TBRPL, mips3_TLBUpdate, mips3_wbflush, - mips3_proc_trampoline, - mips3_cpu_switch_resume, - mips_idle }; /*---------------------------------------------------------------------------- @@ -441,6 +441,7 @@ mips_vector_init() case 1: mips1_TBIA(mips_num_tlb_entries); mips1_vector_init(); + memcpy(mips_locoresw, mips1_locoresw, sizeof(mips_locoresw)); break; #endif #if (MIPS3 + MIPS4) > 0 @@ -450,6 +451,7 @@ mips_vector_init() mips3_TBIA(mips_num_tlb_entries); mips3_SetWIRED(MIPS3_TLB_WIRED_ENTRIES); mips3_vector_init(); + memcpy(mips_locoresw, mips3_locoresw, sizeof(mips_locoresw)); break; #endif default: |
