summaryrefslogtreecommitdiff
path: root/crypto/external/bsd/openssl/lib/libcrypto/man/openssl_ca.1
diff options
context:
space:
mode:
authorrillig <rillig@NetBSD.org>2023-07-09 10:42:07 +0000
committerrillig <rillig@NetBSD.org>2023-07-09 10:42:07 +0000
commit61a832267cc5bff1a90f086bd56309a3a0671255 (patch)
tree6f663ed82c04970fa2f72561dc8eb6681e5f29fe /crypto/external/bsd/openssl/lib/libcrypto/man/openssl_ca.1
parentb2782b14a8e5066f0436d79a391ce49f9e782b76 (diff)
lint: remove redundant '#' after 'argument' in diagnosticsHEADtrunk
Diffstat (limited to 'crypto/external/bsd/openssl/lib/libcrypto/man/openssl_ca.1')
0 files changed, 0 insertions, 0 deletions
tsutsui on R5000/Rm52xx machines: - Add a new global variable mips_cache_virtual_alias in mips/cache.c, which indicates that VIPT cache on the CPU could cause virtual alias and software support is required to handle it. (i.e. no VCED/VCEI) - Add several cache flush/invalidate ops around KSEG0 access which might cause virtual alias if mips_cache_virtual_alias is true. (note checking mips_sdcache_line_size isn't valid for R5000/Rm52xx because only R4000/R4400 with L2 cache have VCED/VCEI) - Remove a global variable mips_sdcache_forceinv, which is now superseded by new mips_cache_virtual_alias. While here, also change some R4000/R4400 cache ops: - Don't override mips_cache_alias_mask and mips_cache_prefer_mask with values based on MIPS3_MAX_PCACHE_SIZE for R4000/R4400 with L2 cache because it's still worth to reduce VCED/VCEI. - Flush dcache in pmap_zero_page(9) unconditionally on all MIPS_HAS_R4K_MMU CPUs and remove cache flush code from cpu_lwp_fork() in vm_machdep.c. Thanks to Markus W Kilbinger for testing patches on port-cobalt/port-mips. XXX This fix is just a workaround because it doesn't handle all possible XXX virtual aliases. As discussed on port-mips, maybe the real fix XXX for virtual alias is to change MI UVM to adapt it to VIPT cache. XXX (all VA mappings against the same PA must have the same VAC index etc.) 2005-03-01Add a hint variable (mips_sdcache_forceinv, explicitly initialized to zero)sekiya that tells pmap_zero_page() and pmap_copy_page() to unconditionally invalidate pages for r5k-class CPUs with secondary cache. This behavior must be explicitly enabled by setting mips_sdcache_forceinv to 1. This is the last bit of a patch that has been kicked around since 2000 between rafal@, tsutsui@, and myself. 2003-02-17No need to protect headers with #ifdef _KERNEL if they're never installedsimonb in /usr/include. 2002-12-17Add support for caches where the data cache is fully coherent, andsimonb either requires flushing either only when the I cache ops are used or not at all. Currently only used by MIPS32/MIPS64 cache code. 2002-11-09Make cache size/mask variables unsigned.thorpej 2001-11-19Add mips_dcache_align and mips_dcache_align_mask variables thatthorpej contain information suitable for allowing other parts of the kernel to determine if a memory region is aligned to the largest data cache line size present in the system. Add a mips_dcache_compute_align() function which must be called whenever one of the data cache line size variables is changed, in order to compute mips_dcache_align and mips_dcache_align_mask. 2001-11-14Merge the thorpej-mips-cache branch onto the trunk. This is anthorpej overhaul of how caches are handled for NetBSD's MIPS ports.