diff options
| author | christos <christos@NetBSD.org> | 2020-04-03 17:51:02 +0000 |
|---|---|---|
| committer | christos <christos@NetBSD.org> | 2020-04-03 17:51:02 +0000 |
| commit | 06324dcf390b361c0bf38c77a23ce0f8d5656dfd (patch) | |
| tree | 72da054b6a3c0936977cf536bdddee9be945012a /external/gpl3/binutils.old/dist/include/opcode | |
| parent | b643afa1c71a08a0f15e787974455a14dc9dbc3c (diff) | |
Resolve conflicts
Diffstat (limited to 'external/gpl3/binutils.old/dist/include/opcode')
70 files changed, 2762 insertions, 3723 deletions
diff --git a/external/gpl3/binutils.old/dist/include/opcode/aarch64.h b/external/gpl3/binutils.old/dist/include/opcode/aarch64.h index b35a818a657..7141927fad1 100644 --- a/external/gpl3/binutils.old/dist/include/opcode/aarch64.h +++ b/external/gpl3/binutils.old/dist/include/opcode/aarch64.h @@ -1,6 +1,6 @@ /* AArch64 assembler/disassembler support. - Copyright (C) 2009-2016 Free Software Foundation, Inc. + Copyright (C) 2009-2018 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GNU Binutils. @@ -37,8 +37,14 @@ extern "C" { typedef uint32_t aarch64_insn; /* The following bitmasks control CPU features. */ +#define AARCH64_FEATURE_SHA2 0x200000000ULL /* SHA2 instructions. */ +#define AARCH64_FEATURE_AES 0x800000000ULL /* AES instructions. */ +#define AARCH64_FEATURE_V8_4 0x000000800ULL /* ARMv8.4 processors. */ +#define AARCH64_FEATURE_SM4 0x100000000ULL /* SM3 & SM4 instructions. */ +#define AARCH64_FEATURE_SHA3 0x400000000ULL /* SHA3 instructions. */ #define AARCH64_FEATURE_V8 0x00000001 /* All processors. */ #define AARCH64_FEATURE_V8_2 0x00000020 /* ARMv8.2 processors. */ +#define AARCH64_FEATURE_V8_3 0x00000040 /* ARMv8.3 processors. */ #define AARCH64_FEATURE_CRYPTO 0x00010000 /* Crypto instructions. */ #define AARCH64_FEATURE_FP 0x00020000 /* FP instructions. */ #define AARCH64_FEATURE_SIMD 0x00040000 /* SIMD instructions. */ @@ -51,42 +57,50 @@ typedef uint32_t aarch64_insn; #define AARCH64_FEATURE_F16 0x02000000 /* v8.2 FP16 instructions. */ #define AARCH64_FEATURE_RAS 0x04000000 /* RAS Extensions. */ #define AARCH64_FEATURE_PROFILE 0x08000000 /* Statistical Profiling. */ +#define AARCH64_FEATURE_SVE 0x10000000 /* SVE instructions. */ +#define AARCH64_FEATURE_RCPC 0x20000000 /* RCPC instructions. */ +#define AARCH64_FEATURE_COMPNUM 0x40000000 /* Complex # instructions. */ +#define AARCH64_FEATURE_DOTPROD 0x080000000 /* Dot Product instructions. */ +#define AARCH64_FEATURE_F16_FML 0x1000000000ULL /* v8.2 FP16FML ins. */ /* Architectures are the sum of the base and extensions. */ #define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \ AARCH64_FEATURE_FP \ | AARCH64_FEATURE_SIMD) -#define AARCH64_ARCH_V8_1 AARCH64_FEATURE (AARCH64_FEATURE_V8, \ - AARCH64_FEATURE_FP \ - | AARCH64_FEATURE_SIMD \ - | AARCH64_FEATURE_CRC \ +#define AARCH64_ARCH_V8_1 AARCH64_FEATURE (AARCH64_ARCH_V8, \ + AARCH64_FEATURE_CRC \ | AARCH64_FEATURE_V8_1 \ | AARCH64_FEATURE_LSE \ | AARCH64_FEATURE_PAN \ | AARCH64_FEATURE_LOR \ | AARCH64_FEATURE_RDMA) -#define AARCH64_ARCH_V8_2 AARCH64_FEATURE (AARCH64_FEATURE_V8, \ +#define AARCH64_ARCH_V8_2 AARCH64_FEATURE (AARCH64_ARCH_V8_1, \ AARCH64_FEATURE_V8_2 \ - | AARCH64_FEATURE_F16 \ - | AARCH64_FEATURE_RAS \ - | AARCH64_FEATURE_FP \ - | AARCH64_FEATURE_SIMD \ - | AARCH64_FEATURE_CRC \ - | AARCH64_FEATURE_V8_1 \ - | AARCH64_FEATURE_LSE \ - | AARCH64_FEATURE_PAN \ - | AARCH64_FEATURE_LOR \ - | AARCH64_FEATURE_RDMA) + | AARCH64_FEATURE_RAS) +#define AARCH64_ARCH_V8_3 AARCH64_FEATURE (AARCH64_ARCH_V8_2, \ + AARCH64_FEATURE_V8_3 \ + | AARCH64_FEATURE_RCPC \ + | AARCH64_FEATURE_COMPNUM) +#define AARCH64_ARCH_V8_4 AARCH64_FEATURE (AARCH64_ARCH_V8_3, \ + AARCH64_FEATURE_V8_4 \ + | AARCH64_FEATURE_DOTPROD \ + | AARCH64_FEATURE_F16_FML) #define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0) #define AARCH64_ANY AARCH64_FEATURE (-1, 0) /* Any basic core. */ /* CPU-specific features. */ -typedef unsigned long aarch64_feature_set; +typedef unsigned long long aarch64_feature_set; -#define AARCH64_CPU_HAS_FEATURE(CPU,FEAT) \ +#define AARCH64_CPU_HAS_ALL_FEATURES(CPU,FEAT) \ + ((~(CPU) & (FEAT)) == 0) + +#define AARCH64_CPU_HAS_ANY_FEATURES(CPU,FEAT) \ (((CPU) & (FEAT)) != 0) +#define AARCH64_CPU_HAS_FEATURE(CPU,FEAT) \ + AARCH64_CPU_HAS_ALL_FEATURES (CPU,FEAT) + #define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2) \ do \ { \ @@ -103,9 +117,6 @@ typedef unsigned long aarch64_feature_set; #define AARCH64_FEATURE(core,coproc) ((core) | (coproc)) -#define AARCH64_OPCODE_HAS_FEATURE(OPC,FEAT) \ - (((OPC) & (FEAT)) != 0) - enum aarch64_operand_class { AARCH64_OPND_CLASS_NIL, @@ -116,7 +127,8 @@ enum aarch64_operand_class AARCH64_OPND_CLASS_SIMD_ELEMENT, AARCH64_OPND_CLASS_SISD_REG, AARCH64_OPND_CLASS_SIMD_REGLIST, - AARCH64_OPND_CLASS_CP_REG, + AARCH64_OPND_CLASS_SVE_REG, + AARCH64_OPND_CLASS_PRED_REG, AARCH64_OPND_CLASS_ADDRESS, AARCH64_OPND_CLASS_IMMEDIATE, AARCH64_OPND_CLASS_SYSTEM, @@ -141,6 +153,7 @@ enum aarch64_opnd AARCH64_OPND_Rd_SP, /* Integer Rd or SP. */ AARCH64_OPND_Rn_SP, /* Integer Rn or SP. */ + AARCH64_OPND_Rm_SP, /* Integer Rm or SP. */ AARCH64_OPND_PAIRREG, /* Paired register operand. */ AARCH64_OPND_Rm_EXT, /* Integer Rm extended. */ AARCH64_OPND_Rm_SFT, /* Integer Rm shifted. */ @@ -156,6 +169,7 @@ enum aarch64_opnd AARCH64_OPND_Sn, /* AdvSIMD Scalar Sn. */ AARCH64_OPND_Sm, /* AdvSIMD Scalar Sm. */ + AARCH64_OPND_Va, /* AdvSIMD Vector Va. */ AARCH64_OPND_Vd, /* AdvSIMD Vector Vd. */ AARCH64_OPND_Vn, /* AdvSIMD Vector Vn. */ AARCH64_OPND_Vm, /* AdvSIMD Vector Vm. */ @@ -164,16 +178,19 @@ enum aarch64_opnd AARCH64_OPND_Ed, /* AdvSIMD Vector Element Vd. */ AARCH64_OPND_En, /* AdvSIMD Vector Element Vn. */ AARCH64_OPND_Em, /* AdvSIMD Vector Element Vm. */ + AARCH64_OPND_Em16, /* AdvSIMD Vector Element Vm restricted to V0 - V15 when + qualifier is S_H. */ AARCH64_OPND_LVn, /* AdvSIMD Vector register list used in e.g. TBL. */ AARCH64_OPND_LVt, /* AdvSIMD Vector register list used in ld/st. */ AARCH64_OPND_LVt_AL, /* AdvSIMD Vector register list for loading single structure to all lanes. */ AARCH64_OPND_LEt, /* AdvSIMD Vector Element list. */ - AARCH64_OPND_Cn, /* Co-processor register in CRn field. */ - AARCH64_OPND_Cm, /* Co-processor register in CRm field. */ + AARCH64_OPND_CRn, /* Co-processor register in CRn field. */ + AARCH64_OPND_CRm, /* Co-processor register in CRm field. */ AARCH64_OPND_IDX, /* AdvSIMD EXT index operand. */ + AARCH64_OPND_MASK, /* AdvSIMD EXT index operand. */ AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left. */ AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right. */ AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift. */ @@ -188,6 +205,7 @@ enum aarch64_opnd AARCH64_OPND_IMMS, /* Immediate #<imms> in e.g. BFM. */ AARCH64_OPND_WIDTH, /* Immediate #<width> in e.g. BFI. */ AARCH64_OPND_IMM, /* Immediate. */ + AARCH64_OPND_IMM_2, /* Immediate. */ AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field. */ AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field. */ AARCH64_OPND_UIMM4, /* Unsigned 4-bit immediate in the CRm field. */ @@ -195,6 +213,7 @@ enum aarch64_opnd AARCH64_OPND_BIT_NUM, /* Immediate. */ AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions. */ AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions. */ + AARCH64_OPND_SIMM5, /* 5-bit signed immediate in the imm5 field. */ AARCH64_OPND_NZCV, /* Flag bit specifier giving an alternative value for each condition flag. */ @@ -203,6 +222,9 @@ enum aarch64_opnd AARCH64_OPND_HALF, /* #<imm16>{, LSL #<shift>} operand in move wide. */ AARCH64_OPND_FBITS, /* FP #<fbits> operand in e.g. SCVTF */ AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias. */ + AARCH64_OPND_IMM_ROT1, /* Immediate rotate operand for FCMLA. */ + AARCH64_OPND_IMM_ROT2, /* Immediate rotate operand for indexed FCMLA. */ + AARCH64_OPND_IMM_ROT3, /* Immediate rotate operand for FCADD. */ AARCH64_OPND_COND, /* Standard condition as the last operand. */ AARCH64_OPND_COND1, /* Same as the above, but excluding AL and NV. */ @@ -224,8 +246,10 @@ enum aarch64_opnd friendly feature of using LDR/STR as the the mnemonic name for LDUR/STUR instructions wherever there is no ambiguity. */ + AARCH64_OPND_ADDR_SIMM10, /* Address of signed 10-bit immediate. */ AARCH64_OPND_ADDR_UIMM12, /* Address of unsigned 12-bit immediate. */ AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures. */ + AARCH64_OPND_ADDR_OFFSET, /* Address with an optional 9-bit immediate. */ AARCH64_OPND_SIMD_ADDR_POST, /* Address of ld/st multiple post-indexed. */ AARCH64_OPND_SYSREG, /* System register operand. */ @@ -238,6 +262,108 @@ enum aarch64_opnd AARCH64_OPND_BARRIER_ISB, /* Barrier operand for ISB. */ AARCH64_OPND_PRFOP, /* Prefetch operation. */ AARCH64_OPND_BARRIER_PSB, /* Barrier operand for PSB. */ + + AARCH64_OPND_SVE_ADDR_RI_S4x16, /* SVE [<Xn|SP>, #<simm4>*16]. */ + AARCH64_OPND_SVE_ADDR_RI_S4xVL, /* SVE [<Xn|SP>, #<simm4>, MUL VL]. */ + AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, /* SVE [<Xn|SP>, #<simm4>*2, MUL VL]. */ + AARCH64_OPND_SVE_ADDR_RI_S4x3xVL, /* SVE [<Xn|SP>, #<simm4>*3, MUL VL]. */ + AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, /* SVE [<Xn|SP>, #<simm4>*4, MUL VL]. */ + AARCH64_OPND_SVE_ADDR_RI_S6xVL, /* SVE [<Xn|SP>, #<simm6>, MUL VL]. */ + AARCH64_OPND_SVE_ADDR_RI_S9xVL, /* SVE [<Xn|SP>, #<simm9>, MUL VL]. */ + AARCH64_OPND_SVE_ADDR_RI_U6, /* SVE [<Xn|SP>, #<uimm6>]. */ + AARCH64_OPND_SVE_ADDR_RI_U6x2, /* SVE [<Xn|SP>, #<uimm6>*2]. */ + AARCH64_OPND_SVE_ADDR_RI_U6x4, /* SVE [<Xn|SP>, #<uimm6>*4]. */ + AARCH64_OPND_SVE_ADDR_RI_U6x8, /* SVE [<Xn|SP>, #<uimm6>*8]. */ + AARCH64_OPND_SVE_ADDR_R, /* SVE [<Xn|SP>]. */ + AARCH64_OPND_SVE_ADDR_RR, /* SVE [<Xn|SP>, <Xm|XZR>]. */ + AARCH64_OPND_SVE_ADDR_RR_LSL1, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #1]. */ + AARCH64_OPND_SVE_ADDR_RR_LSL2, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #2]. */ + AARCH64_OPND_SVE_ADDR_RR_LSL3, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #3]. */ + AARCH64_OPND_SVE_ADDR_RX, /* SVE [<Xn|SP>, <Xm>]. */ + AARCH64_OPND_SVE_ADDR_RX_LSL1, /* SVE [<Xn|SP>, <Xm>, LSL #1]. */ + AARCH64_OPND_SVE_ADDR_RX_LSL2, /* SVE [<Xn|SP>, <Xm>, LSL #2]. */ + AARCH64_OPND_SVE_ADDR_RX_LSL3, /* SVE [<Xn|SP>, <Xm>, LSL #3]. */ + AARCH64_OPND_SVE_ADDR_RZ, /* SVE [<Xn|SP>, Zm.D]. */ + AARCH64_OPND_SVE_ADDR_RZ_LSL1, /* SVE [<Xn|SP>, Zm.D, LSL #1]. */ + AARCH64_OPND_SVE_ADDR_RZ_LSL2, /* SVE [<Xn|SP>, Zm.D, LSL #2]. */ + AARCH64_OPND_SVE_ADDR_RZ_LSL3, /* SVE [<Xn|SP>, Zm.D, LSL #3]. */ + AARCH64_OPND_SVE_ADDR_RZ_XTW_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW]. + Bit 14 controls S/U choice. */ + AARCH64_OPND_SVE_ADDR_RZ_XTW_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW]. + Bit 22 controls S/U choice. */ + AARCH64_OPND_SVE_ADDR_RZ_XTW1_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1]. + Bit 14 controls S/U choice. */ + AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1]. + Bit 22 controls S/U choice. */ + AARCH64_OPND_SVE_ADDR_RZ_XTW2_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2]. + Bit 14 controls S/U choice. */ + AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2]. + Bit 22 controls S/U choice. */ + AARCH64_OPND_SVE_ADDR_RZ_XTW3_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3]. + Bit 14 controls S/U choice. */ + AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3]. + Bit 22 controls S/U choice. */ + AARCH64_OPND_SVE_ADDR_ZI_U5, /* SVE [Zn.<T>, #<uimm5>]. */ + AARCH64_OPND_SVE_ADDR_ZI_U5x2, /* SVE [Zn.<T>, #<uimm5>*2]. */ + AARCH64_OPND_SVE_ADDR_ZI_U5x4, /* SVE [Zn.<T>, #<uimm5>*4]. */ + AARCH64_OPND_SVE_ADDR_ZI_U5x8, /* SVE [Zn.<T>, #<uimm5>*8]. */ + AARCH64_OPND_SVE_ADDR_ZZ_LSL, /* SVE [Zn.<T>, Zm,<T>, LSL #<msz>]. */ + AARCH64_OPND_SVE_ADDR_ZZ_SXTW, /* SVE [Zn.<T>, Zm,<T>, SXTW #<msz>]. */ + AARCH64_OPND_SVE_ADDR_ZZ_UXTW, /* SVE [Zn.<T>, Zm,<T>, UXTW #<msz>]. */ + AARCH64_OPND_SVE_AIMM, /* SVE unsigned arithmetic immediate. */ + AARCH64_OPND_SVE_ASIMM, /* SVE signed arithmetic immediate. */ + AARCH64_OPND_SVE_FPIMM8, /* SVE 8-bit floating-point immediate. */ + AARCH64_OPND_SVE_I1_HALF_ONE, /* SVE choice between 0.5 and 1.0. */ + AARCH64_OPND_SVE_I1_HALF_TWO, /* SVE choice between 0.5 and 2.0. */ + AARCH64_OPND_SVE_I1_ZERO_ONE, /* SVE choice between 0.0 and 1.0. */ + AARCH64_OPND_SVE_IMM_ROT1, /* SVE 1-bit rotate operand (90 or 270). */ + AARCH64_OPND_SVE_IMM_ROT2, /* SVE 2-bit rotate operand (N*90). */ + AARCH64_OPND_SVE_INV_LIMM, /* SVE inverted logical immediate. */ + AARCH64_OPND_SVE_LIMM, /* SVE logical immediate. */ + AARCH64_OPND_SVE_LIMM_MOV, /* SVE logical immediate for MOV. */ + AARCH64_OPND_SVE_PATTERN, /* SVE vector pattern enumeration. */ + AARCH64_OPND_SVE_PATTERN_SCALED, /* Likewise, with additional MUL factor. */ + AARCH64_OPND_SVE_PRFOP, /* SVE prefetch operation. */ + AARCH64_OPND_SVE_Pd, /* SVE p0-p15 in Pd. */ + AARCH64_OPND_SVE_Pg3, /* SVE p0-p7 in Pg. */ + AARCH64_OPND_SVE_Pg4_5, /* SVE p0-p15 in Pg, bits [8,5]. */ + AARCH64_OPND_SVE_Pg4_10, /* SVE p0-p15 in Pg, bits [13,10]. */ + AARCH64_OPND_SVE_Pg4_16, /* SVE p0-p15 in Pg, bits [19,16]. */ + AARCH64_OPND_SVE_Pm, /* SVE p0-p15 in Pm. */ + AARCH64_OPND_SVE_Pn, /* SVE p0-p15 in Pn. */ + AARCH64_OPND_SVE_Pt, /* SVE p0-p15 in Pt. */ + AARCH64_OPND_SVE_Rm, /* Integer Rm or ZR, alt. SVE position. */ + AARCH64_OPND_SVE_Rn_SP, /* Integer Rn or SP, alt. SVE position. */ + AARCH64_OPND_SVE_SHLIMM_PRED, /* SVE shift left amount (predicated). */ + AARCH64_OPND_SVE_SHLIMM_UNPRED, /* SVE shift left amount (unpredicated). */ + AARCH64_OPND_SVE_SHRIMM_PRED, /* SVE shift right amount (predicated). */ + AARCH64_OPND_SVE_SHRIMM_UNPRED, /* SVE shift right amount (unpredicated). */ + AARCH64_OPND_SVE_SIMM5, /* SVE signed 5-bit immediate. */ + AARCH64_OPND_SVE_SIMM5B, /* SVE secondary signed 5-bit immediate. */ + AARCH64_OPND_SVE_SIMM6, /* SVE signed 6-bit immediate. */ + AARCH64_OPND_SVE_SIMM8, /* SVE signed 8-bit immediate. */ + AARCH64_OPND_SVE_UIMM3, /* SVE unsigned 3-bit immediate. */ + AARCH64_OPND_SVE_UIMM7, /* SVE unsigned 7-bit immediate. */ + AARCH64_OPND_SVE_UIMM8, /* SVE unsigned 8-bit immediate. */ + AARCH64_OPND_SVE_UIMM8_53, /* SVE split unsigned 8-bit immediate. */ + AARCH64_OPND_SVE_VZn, /* Scalar SIMD&FP register in Zn field. */ + AARCH64_OPND_SVE_Vd, /* Scalar SIMD&FP register in Vd. */ + AARCH64_OPND_SVE_Vm, /* Scalar SIMD&FP register in Vm. */ + AARCH64_OPND_SVE_Vn, /* Scalar SIMD&FP register in Vn. */ + AARCH64_OPND_SVE_Za_5, /* SVE vector register in Za, bits [9,5]. */ + AARCH64_OPND_SVE_Za_16, /* SVE vector register in Za, bits [20,16]. */ + AARCH64_OPND_SVE_Zd, /* SVE vector register in Zd. */ + AARCH64_OPND_SVE_Zm_5, /* SVE vector register in Zm, bits [9,5]. */ + AARCH64_OPND_SVE_Zm_16, /* SVE vector register in Zm, bits [20,16]. */ + AARCH64_OPND_SVE_Zm3_INDEX, /* z0-z7[0-3] in Zm, bits [20,16]. */ + AARCH64_OPND_SVE_Zm3_22_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 22. */ + AARCH64_OPND_SVE_Zm4_INDEX, /* z0-z15[0-1] in Zm, bits [20,16]. */ + AARCH64_OPND_SVE_Zn, /* SVE vector register in Zn. */ + AARCH64_OPND_SVE_Zn_INDEX, /* Indexed SVE vector register, for DUP. */ + AARCH64_OPND_SVE_ZnxN, /* SVE vector register list in Zn. */ + AARCH64_OPND_SVE_Zt, /* SVE vector register in Zt. */ + AARCH64_OPND_SVE_ZtxN, /* SVE vector register list in Zt. */ + AARCH64_OPND_SM3_IMM2, /* SM3 encodes lane in bits [13, 14]. */ }; /* Qualifier constrains an operand. It either specifies a variant of an @@ -273,6 +399,11 @@ enum aarch64_opnd_qualifier AARCH64_OPND_QLF_S_S, AARCH64_OPND_QLF_S_D, AARCH64_OPND_QLF_S_Q, + /* This type qualifier has a special meaning in that it means that 4 x 1 byte + are selected by the instruction. Other than that it has no difference + with AARCH64_OPND_QLF_S_B in encoding. It is here purely for syntactical + reasons and is an exception from normal AArch64 disassembly scheme. */ + AARCH64_OPND_QLF_S_4B, /* Qualifying an operand which is a SIMD vector register or a SIMD vector register list; indicating register shape. @@ -280,6 +411,7 @@ enum aarch64_opnd_qualifier a use is only for the ease of operand encoding/decoding and qualifier sequence matching; such a use should not be applied widely; use the value constraint qualifiers for immediate operands wherever possible. */ + AARCH64_OPND_QLF_V_4B, AARCH64_OPND_QLF_V_8B, AARCH64_OPND_QLF_V_16B, AARCH64_OPND_QLF_V_2H, @@ -291,7 +423,11 @@ enum aarch64_opnd_qualifier AARCH64_OPND_QLF_V_2D, AARCH64_OPND_QLF_V_1Q, + AARCH64_OPND_QLF_P_Z, + AARCH64_OPND_QLF_P_M, + /* Constraint on value. */ + AARCH64_OPND_QLF_CR, /* CRn, CRm. */ AARCH64_OPND_QLF_imm_0_7, AARCH64_OPND_QLF_imm_0_15, AARCH64_OPND_QLF_imm_0_31, @@ -367,6 +503,7 @@ enum aarch64_insn_class ldst_immpost, ldst_immpre, ldst_imm9, /* immpost or immpre */ + ldst_imm10, /* LDRAA/LDRAB */ ldst_pos, ldst_regoff, ldst_unpriv, @@ -382,7 +519,22 @@ enum aarch64_insn_class movewide, pcreladdr, ic_system, + sve_cpy, + sve_index, + sve_limm, + sve_misc, + sve_movprfx, + sve_pred_zm, + sve_shift_pred, + sve_shift_unpred, + sve_size_bhs, + sve_size_bhsd, + sve_size_hsd, + sve_size_sd, testbranch, + cryptosm3, + cryptosm4, + dotproduct, }; /* Opcode enumerators. */ @@ -472,6 +624,20 @@ enum aarch64_op OP_UXTL, OP_UXTL2, + OP_MOV_P_P, + OP_MOV_Z_P_Z, + OP_MOV_Z_V, + OP_MOV_Z_Z, + OP_MOV_Z_Zi, + OP_MOVM_P_P_P, + OP_MOVS_P_P, + OP_MOVZS_P_P_P, + OP_MOVZ_P_P_P, + OP_NOTS_P_P_P_Z, + OP_NOT_P_P_P_Z, + + OP_FCMLA_ELEM, /* ARMv8.3, indexed element version. */ + OP_TOTAL_NUM, /* Pseudo. */ }; @@ -536,6 +702,10 @@ struct aarch64_opcode /* Flags providing information about this instruction */ uint32_t flags; + /* If nonzero, this operand and operand 0 are both registers and + are required to have the same register number. */ + unsigned char tied_operand; + /* If non-NULL, a function to verify that a given instruction is valid. */ bfd_boolean (* verifier) (const struct aarch64_opcode *, const aarch64_insn); }; @@ -595,7 +765,13 @@ extern aarch64_opcode aarch64_opcode_table[]; #define F_OD(X) (((X) & 0x7) << 24) /* Instruction has the field of 'sz'. */ #define F_LSE_SZ (1 << 27) -/* Next bit is 28. */ +/* Require an exact qualifier match, even for NIL qualifiers. */ +#define F_STRICT (1ULL << 28) +/* This system instruction is used to read system registers. */ +#define F_SYS_READ (1ULL << 29) +/* This system instruction is used to write system registers. */ +#define F_SYS_WRITE (1ULL << 30) +/* Next bit is 31. */ static inline bfd_boolean alias_opcode_p (const aarch64_opcode *opcode) @@ -710,6 +886,8 @@ enum aarch64_modifier_kind AARCH64_MOD_SXTH, AARCH64_MOD_SXTW, AARCH64_MOD_SXTX, + AARCH64_MOD_MUL, + AARCH64_MOD_MUL_VL, }; bfd_boolean @@ -723,7 +901,7 @@ typedef struct { /* A list of names with the first one as the disassembly preference; terminated by NULL if fewer than 3. */ - const char *names[3]; + const char *names[4]; aarch64_insn value; } aarch64_cond; @@ -785,9 +963,17 @@ struct aarch64_opnd_info unsigned preind : 1; /* Pre-indexed. */ unsigned postind : 1; /* Post-indexed. */ } addr; + + struct + { + /* The encoding of the system register. */ + aarch64_insn value; + + /* The system register flags. */ + uint32_t flags; + } sysreg; + const aarch64_cond *cond; - /* The encoding of the system register. */ - aarch64_insn sysreg; /* The encoding of the PSTATE field. */ aarch64_insn pstatefield; const aarch64_sys_ins_reg *sysins_op; @@ -801,10 +987,10 @@ struct aarch64_opnd_info struct { enum aarch64_modifier_kind kind; - int amount; unsigned operator_present: 1; /* Only valid during encoding. */ /* Value of the 'S' field in ld/st reg offset; used only in decoding. */ unsigned amount_present: 1; + int64_t amount; } shifter; unsigned skip:1; /* Operand is not completed if there is a fixup needed @@ -867,6 +1053,10 @@ typedef struct aarch64_inst aarch64_inst; No syntax error, but the operands are not a valid combination, e.g. FMOV D0,S0 + AARCH64_OPDE_UNTIED_OPERAND + The asm failed to use the same register for a destination operand + and a tied source operand. + AARCH64_OPDE_OUT_OF_RANGE Error about some immediate value out of a valid range. @@ -903,6 +1093,7 @@ enum aarch64_operand_error_kind AARCH64_OPDE_SYNTAX_ERROR, AARCH64_OPDE_FATAL_SYNTAX_ERROR, AARCH64_OPDE_INVALID_VARIANT, + AARCH64_OPDE_UNTIED_OPERAND, AARCH64_OPDE_OUT_OF_RANGE, AARCH64_OPDE_UNALIGNED, AARCH64_OPDE_REG_LIST, @@ -916,6 +1107,7 @@ struct aarch64_operand_error int index; const char *error; int data[3]; /* Some data for extra information. */ + bfd_boolean non_fatal; }; typedef struct aarch64_operand_error aarch64_operand_error; @@ -940,7 +1132,8 @@ aarch64_get_opcode (enum aarch64_op); /* Generate the string representation of an operand. */ extern void aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *, - const aarch64_opnd_info *, int, int *, bfd_vma *); + const aarch64_opnd_info *, int, int *, bfd_vma *, + char **); /* Miscellaneous interface. */ @@ -961,7 +1154,8 @@ extern int aarch64_zero_register_p (const aarch64_opnd_info *); extern int -aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean); +aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean, + aarch64_operand_error *errors); /* Given an operand qualifier, return the expected data element size of a qualified operand. */ @@ -977,6 +1171,9 @@ aarch64_get_operand_name (enum aarch64_opnd); extern const char * aarch64_get_operand_desc (enum aarch64_opnd); +extern bfd_boolean +aarch64_sve_dupm_mov_immediate_p (uint64_t, int); + #ifdef DEBUG_AARCH64 extern int debug_dump; @@ -999,6 +1196,9 @@ aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2))); #define DEBUG_TRACE_IF(C, M, ...) ; #endif /* DEBUG_AARCH64 */ +extern const char *const aarch64_sve_pattern_array[32]; +extern const char *const aarch64_sve_prfop_array[16]; + #ifdef __cplusplus } #endif diff --git a/external/gpl3/binutils.old/dist/include/opcode/alpha.h b/external/gpl3/binutils.old/dist/include/opcode/alpha.h index 747660ed99d..6bded7bad0f 100644 --- a/external/gpl3/binutils.old/dist/include/opcode/alpha.h +++ b/external/gpl3/binutils.old/dist/include/opcode/alpha.h @@ -1,5 +1,5 @@ /* alpha.h -- Header file for Alpha opcode table - Copyright (C) 1996-2016 Free Software Foundation, Inc. + Copyright (C) 1996-2018 Free Software Foundation, Inc. Contributed by Richard Henderson <rth@tamu.edu>, patterned after the PPC opcode table written by Ian Lance Taylor. diff --git a/external/gpl3/binutils.old/dist/include/opcode/arc-func.h b/external/gpl3/binutils.old/dist/include/opcode/arc-func.h index cafb92fd7e2..640e490f3e8 100644 --- a/external/gpl3/binutils.old/dist/include/opcode/arc-func.h +++ b/external/gpl3/binutils.old/dist/include/opcode/arc-func.h @@ -1,5 +1,5 @@ /* Replace functions for the ARC relocs. - Copyright (C) 2015-2016 Free Software Foundation, Inc. + Copyright (C) 2015-2018 Free Software Foundation, Inc. This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and the GNU Binutils. @@ -264,3 +264,31 @@ replace_disp9s1 (unsigned insn, int value ATTRIBUTE_UNUSED) } #endif /* REPLACE_disp9s1 */ + +/* mask = 00000000000000000000111111222222. */ +#ifndef REPLACE_disp12s +#define REPLACE_disp12s +ATTRIBUTE_UNUSED static unsigned +replace_disp12s (unsigned insn, int value ATTRIBUTE_UNUSED) +{ + insn = insn & ~0xfff; + insn |= ((value >> 0) & 0x003f) << 6; + insn |= ((value >> 6) & 0x003f) << 0; + return insn; +} + +#endif /* REPLACE_disp12s */ + +/* mask = 0000001111111111. */ +#ifndef REPLACE_jli +#define REPLACE_jli +ATTRIBUTE_UNUSED static unsigned +replace_jli (unsigned insn, int value) +{ + insn = insn & ~0x3ff; + insn |= ((value >> 0) & 0x03ff) << 0; + + return insn; +} + +#endif /* REPLACE_jli */ diff --git a/external/gpl3/binutils.old/dist/include/opcode/arc.h b/external/gpl3/binutils.old/dist/include/opcode/arc.h index f0fefbbc933..6a979fce034 100644 --- a/external/gpl3/binutils.old/dist/include/opcode/arc.h +++ b/external/gpl3/binutils.old/dist/include/opcode/arc.h @@ -1,5 +1,5 @@ /* Opcode table for the ARC. - Copyright (C) 1994-2016 Free Software Foundation, Inc. + Copyright (C) 1994-2018 Free Software Foundation, Inc. Contributed by Claudiu Zissulescu (claziss@synopsys.com) @@ -33,92 +33,131 @@ extern "C" { #endif #ifndef MAX_INSN_FLGS -#define MAX_INSN_FLGS 3 +#define MAX_INSN_FLGS 4 #endif /* Instruction Class. */ typedef enum - { - ACL, - ARITH, - AUXREG, - BITOP, - BRANCH, - CONTROL, - DPI, - DSP, - FLOAT, - INVALID, - JUMP, - KERNEL, - LOGICAL, - MEMORY, - NET, - } insn_class_t; +{ + ACL, + ARITH, + AUXREG, + BBIT0, + BBIT1, + BI, + BIH, + BITOP, + BITSTREAM, + BMU, + BRANCH, + BRCC, + CONTROL, + DIVREM, + DMA, + DPI, + DSP, + EI, + ENTER, + FLOAT, + INVALID, + JLI, + JUMP, + KERNEL, + LEAVE, + LOAD, + LOGICAL, + LOOP, + MEMORY, + MISC, + MOVE, + MPY, + NET, + PROTOCOL_DECODE, + PMU, + POP, + PUSH, + SJLI, + STORE, + SUB, + ULTRAIP, + XY +} insn_class_t; /* Instruction Subclass. */ typedef enum - { - NONE, - CVT, - BTSCN, - CD1, - CD2, - COND, - DIV, - DP, - DPA, - DPX, - MPY1E, - MPY6E, - MPY7E, - MPY8E, - MPY9E, - NPS400, - QUARKSE, - SHFT1, - SHFT2, - SWAP, - SP, - SPX - } insn_subclass_t; +{ + NONE = 0, + CVT = (1U << 1), + BTSCN = (1U << 2), + CD = (1U << 3), + CD1 = CD, + CD2 = CD, + COND = (1U << 4), + DIV = (1U << 5), + DP = (1U << 6), + DPA = (1U << 7), + DPX = (1U << 8), + LL64 = (1U << 9), + MPY1E = (1U << 10), + MPY6E = (1U << 11), + MPY7E = (1U << 12), + MPY8E = (1U << 13), + MPY9E = (1U << 14), + NPS400 = (1U << 15), + QUARKSE1 = (1U << 16), + QUARKSE2 = (1U << 17), + SHFT1 = (1U << 18), + SHFT2 = (1U << 19), + SWAP = (1U << 20), + SP = (1U << 21), + SPX = (1U << 22) +} insn_subclass_t; /* Flags class. */ typedef enum - { - F_CLASS_NONE = 0, +{ + F_CLASS_NONE = 0, + + /* At most one flag from the set of flags can appear in the + instruction. */ + F_CLASS_OPTIONAL = (1 << 0), + + /* Exactly one from from the set of flags must appear in the + instruction. */ + F_CLASS_REQUIRED = (1 << 1), + + /* The conditional code can be extended over the standard variants + via .extCondCode pseudo-op. */ + F_CLASS_EXTEND = (1 << 2), - /* At most one flag from the set of flags can appear in the - instruction. */ - F_CLASS_OPTIONAL = (1 << 0), + /* Condition code flag. */ + F_CLASS_COND = (1 << 3), - /* Exactly one from from the set of flags must appear in the - instruction. */ - F_CLASS_REQUIRED = (1 << 1), + /* Write back mode. */ + F_CLASS_WB = (1 << 4), - /* The conditional code can be extended over the standard variants - via .extCondCode pseudo-op. */ - F_CLASS_EXTEND = (1 << 2), + /* Data size. */ + F_CLASS_ZZ = (1 << 5), - /* Condition code flag. */ - F_CLASS_COND = (1 << 3) - } flag_class_t; + /* Implicit flag. */ + F_CLASS_IMPLICIT = (1 << 6) +} flag_class_t; /* The opcode table is an array of struct arc_opcode. */ struct arc_opcode { /* The opcode name. */ - const char *name; + const char * name; /* The opcode itself. Those bits which will be filled in with operands are zeroes. */ - unsigned opcode; + unsigned long long opcode; /* The opcode mask. This is used by the disassembler. This is a mask containing ones indicating those bits which must match the opcode field, and zeroes indicating those bits which need not match (and are presumably filled in by operands). */ - unsigned mask; + unsigned long long mask; /* One bit flags for the opcode. These are primarily used to indicate specific processors and environments support the @@ -142,35 +181,14 @@ struct arc_opcode unsigned char flags[MAX_INSN_FLGS + 1]; }; -/* Structure used to describe 48 and 64 bit instructions. */ -struct arc_long_opcode -{ - /* The base instruction is either 16 or 32 bits, and is described like a - normal instruction. */ - struct arc_opcode base_opcode; - - /* The template value for the 32-bit LIMM extension. Used by the - assembler and disassembler in the same way as the 'opcode' field of - 'struct arc_opcode'. */ - unsigned limm_template; - - /* The mask value for the 32-bit LIMM extension. Used by the - disassembler just like the 'mask' field in 'struct arc_opcode'. */ - unsigned limm_mask; - - /* Array of operand codes similar to the 'operands' array in 'struct - arc_opcode'. These operands are used to fill in the LIMM value. */ - unsigned char operands[MAX_INSN_ARGS + 1]; -}; - -extern const struct arc_long_opcode arc_long_opcodes[]; -extern const unsigned arc_num_long_opcodes; - /* The table itself is sorted by major opcode number, and is otherwise in the order in which the disassembler should consider instructions. */ extern const struct arc_opcode arc_opcodes[]; +/* Return length of an instruction represented by OPCODE, in bytes. */ +extern int arc_opcode_len (const struct arc_opcode *opcode); + /* CPU Availability. */ #define ARC_OPCODE_NONE 0x0000 #define ARC_OPCODE_ARC600 0x0001 /* ARC 600 specific insns. */ @@ -182,50 +200,8 @@ extern const struct arc_opcode arc_opcodes[]; #define ARC_OPCODE_ARCALL (ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 \ | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS) #define ARC_OPCODE_ARCFPX (ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM) - -/* CPU extensions. */ -#define ARC_EA 0x0001 -#define ARC_CD 0x0001 /* Mutual exclusive with EA. */ -#define ARC_LLOCK 0x0002 -#define ARC_ATOMIC 0x0002 /* Mutual exclusive with LLOCK. */ -#define ARC_MPY 0x0004 -#define ARC_MULT 0x0004 -#define ARC_NPS400 0x0008 - -/* Floating point support. */ -#define ARC_DPFP 0x0010 -#define ARC_SPFP 0x0020 -#define ARC_FPU 0x0030 -#define ARC_FPUDA 0x0040 - -/* NORM & SWAP. */ -#define ARC_SWAP 0x0100 -#define ARC_NORM 0x0200 -#define ARC_BSCAN 0x0200 - -/* A7 specific. */ -#define ARC_UIX 0x1000 -#define ARC_TSTAMP 0x1000 - -/* A6 specific. */ -#define ARC_VBFDW 0x1000 -#define ARC_BARREL 0x1000 -#define ARC_DSPA 0x1000 - -/* EM specific. */ -#define ARC_SHIFT 0x1000 - -/* V2 specific. */ -#define ARC_INTR 0x1000 -#define ARC_DIV 0x1000 - -/* V1 specific. */ -#define ARC_XMAC 0x1000 -#define ARC_CRC 0x1000 - -/* A macro to check for short instructions. */ -#define ARC_SHORT(mask) \ - (((mask) & 0xFFFF0000) ? 0 : 1) +#define ARC_OPCODE_ARCV2 (ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS) +#define ARC_OPCODE_ARCMPY6E (ARC_OPCODE_ARC700 | ARC_OPCODE_ARCV2) /* The operands table is an array of struct arc_operand. */ struct arc_operand @@ -258,7 +234,9 @@ struct arc_operand string (the operand will be inserted in any case). If the operand value is legal, *ERRMSG will be unchanged (most operands can accept any value). */ - unsigned (*insert) (unsigned instruction, int op, const char **errmsg); + unsigned long long (*insert) (unsigned long long instruction, + long long int op, + const char **errmsg); /* Extraction function. This is used by the disassembler. To extract this operand type from an instruction, check this field. @@ -277,7 +255,8 @@ struct arc_operand TRUE if this operand type can not actually be extracted from this operand (i.e., the instruction does not match). If the operand is valid, *INVALID will not be changed. */ - int (*extract) (unsigned instruction, bfd_boolean *invalid); + long long int (*extract) (unsigned long long instruction, + bfd_boolean *invalid); }; /* Elements in the table are retrieved by indexing with values from @@ -336,17 +315,30 @@ extern const unsigned arc_NToperand; /* Mark the braket possition. */ #define ARC_OPERAND_BRAKET 0x1000 +/* Address type operand for NPS400. */ +#define ARC_OPERAND_ADDRTYPE 0x2000 + +/* Mark the colon position. */ +#define ARC_OPERAND_COLON 0x4000 + /* Mask for selecting the type for typecheck purposes. */ -#define ARC_OPERAND_TYPECHECK_MASK \ - (ARC_OPERAND_IR | \ - ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED | \ - ARC_OPERAND_UNSIGNED | ARC_OPERAND_BRAKET) +#define ARC_OPERAND_TYPECHECK_MASK \ + (ARC_OPERAND_IR \ + | ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED \ + | ARC_OPERAND_UNSIGNED | ARC_OPERAND_BRAKET \ + | ARC_OPERAND_ADDRTYPE | ARC_OPERAND_COLON) + +/* Macro to determine if an operand is a fake operand. */ +#define ARC_OPERAND_IS_FAKE(op) \ + ((operand->flags & ARC_OPERAND_FAKE) \ + && !((operand->flags & ARC_OPERAND_BRAKET) \ + || (operand->flags & ARC_OPERAND_COLON))) /* The flags structure. */ struct arc_flag_operand { /* The flag name. */ - const char *name; + const char * name; /* The flag code. */ unsigned code; @@ -428,13 +420,13 @@ struct arc_operand_operation struct arc_pseudo_insn { /* Mnemonic for pseudo/alias insn. */ - const char *mnemonic_p; + const char * mnemonic_p; /* Mnemonic for real instruction. */ - const char *mnemonic_r; + const char * mnemonic_r; /* Flag that will have to be added (if any). */ - const char *flag_r; + const char * flag_r; /* Amount of operands. */ unsigned operand_cnt; @@ -461,7 +453,7 @@ struct arc_aux_reg insn_subclass_t subclass; /* Register name. */ - const char *name; + const char * name; /* Size of the string. */ size_t length; @@ -512,26 +504,28 @@ extern const unsigned arc_num_relax_opcodes; #define INSN3OP_C0LU(MOP,SOP) \ (INSN3OP (MOP,SOP) | (0x03 << 22) | (0x01 << 5) | FIELDB (62)) -#define MINSN3OP_ABC (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63))) -#define MINSN3OP_ALC (~(FIELDF | FIELDA (63) | FIELDC (63))) -#define MINSN3OP_ABL (~(FIELDF | FIELDA (63) | FIELDB (63))) -#define MINSN3OP_ALL (~(FIELDF | FIELDA (63))) -#define MINSN3OP_0BC (~(FIELDF | FIELDB (63) | FIELDC (63))) -#define MINSN3OP_0LC (~(FIELDF | FIELDC (63))) -#define MINSN3OP_0BL (~(FIELDF | FIELDB (63))) -#define MINSN3OP_0LL (~(FIELDF)) -#define MINSN3OP_ABU (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63))) -#define MINSN3OP_ALU (~(FIELDF | FIELDA (63) | FIELDC (63))) -#define MINSN3OP_0BU (~(FIELDF | FIELDB (63) | FIELDC (63))) -#define MINSN3OP_0LU (~(FIELDF | FIELDC (63))) -#define MINSN3OP_BBS (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63))) -#define MINSN3OP_0LS (~(FIELDF | FIELDA (63) | FIELDC (63))) -#define MINSN3OP_CBBC (~(FIELDF | FIELDQ | FIELDB (63) | FIELDC (63))) -#define MINSN3OP_CBBL (~(FIELDF | FIELDQ | FIELDB (63))) -#define MINSN3OP_C0LC (~(FIELDF | FIELDQ | FIELDC (63))) -#define MINSN3OP_C0LL (~(FIELDF | FIELDQ)) -#define MINSN3OP_CBBU (~(FIELDF | FIELDQ | FIELDB (63) | FIELDC (63))) -#define MINSN3OP_C0LU (~(FIELDF | FIELDQ | FIELDC (63))) +#define MASK_32BIT(VAL) (0xffffffff & (VAL)) + +#define MINSN3OP_ABC (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63)))) +#define MINSN3OP_ALC (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDC (63)))) +#define MINSN3OP_ABL (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDB (63)))) +#define MINSN3OP_ALL (MASK_32BIT (~(FIELDF | FIELDA (63)))) +#define MINSN3OP_0BC (MASK_32BIT (~(FIELDF | FIELDB (63) | FIELDC (63)))) +#define MINSN3OP_0LC (MASK_32BIT (~(FIELDF | FIELDC (63)))) +#define MINSN3OP_0BL (MASK_32BIT (~(FIELDF | FIELDB (63)))) +#define MINSN3OP_0LL (MASK_32BIT (~(FIELDF))) +#define MINSN3OP_ABU (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63)))) +#define MINSN3OP_ALU (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDC (63)))) +#define MINSN3OP_0BU (MASK_32BIT (~(FIELDF | FIELDB (63) | FIELDC (63)))) +#define MINSN3OP_0LU (MASK_32BIT (~(FIELDF | FIELDC (63)))) +#define MINSN3OP_BBS (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63)))) +#define MINSN3OP_0LS (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDC (63)))) +#define MINSN3OP_CBBC (MASK_32BIT (~(FIELDF | FIELDQ | FIELDB (63) | FIELDC (63)))) +#define MINSN3OP_CBBL (MASK_32BIT (~(FIELDF | FIELDQ | FIELDB (63)))) +#define MINSN3OP_C0LC (MASK_32BIT (~(FIELDF | FIELDQ | FIELDC (63)))) +#define MINSN3OP_C0LL (MASK_32BIT (~(FIELDF | FIELDQ))) +#define MINSN3OP_CBBU (MASK_32BIT (~(FIELDF | FIELDQ | FIELDB (63) | FIELDC (63)))) +#define MINSN3OP_C0LU (MASK_32BIT (~(FIELDF | FIELDQ | FIELDC (63)))) #define INSN2OP_BC(MOP,SOP) (INSN2OP (MOP,SOP)) #define INSN2OP_BL(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDC (62)) @@ -540,12 +534,12 @@ extern const unsigned arc_num_relax_opcodes; #define INSN2OP_BU(MOP,SOP) (INSN2OP (MOP,SOP) | (0x01 << 22)) #define INSN2OP_0U(MOP,SOP) (INSN2OP (MOP,SOP) | (0x01 << 22) | FIELDB (62)) -#define MINSN2OP_BC (~(FIELDF | FIELDB (63) | FIELDC (63))) -#define MINSN2OP_BL (~(FIELDF | FIELDB (63))) -#define MINSN2OP_0C (~(FIELDF | FIELDC (63))) -#define MINSN2OP_0L (~(FIELDF)) -#define MINSN2OP_BU (~(FIELDF | FIELDB (63) | FIELDC (63))) -#define MINSN2OP_0U (~(FIELDF | FIELDC (63))) +#define MINSN2OP_BC (MASK_32BIT ((~(FIELDF | FIELDB (63) | FIELDC (63))))) +#define MINSN2OP_BL (MASK_32BIT ((~(FIELDF | FIELDB (63))))) +#define MINSN2OP_0C (MASK_32BIT ((~(FIELDF | FIELDC (63))))) +#define MINSN2OP_0L (MASK_32BIT ((~(FIELDF)))) +#define MINSN2OP_BU (MASK_32BIT ((~(FIELDF | FIELDB (63) | FIELDC (63))))) +#define MINSN2OP_0U (MASK_32BIT ((~(FIELDF | FIELDC (63))))) /* Various constants used when defining an extension instruction. */ #define ARC_SYNTAX_3OP (1 << 0) @@ -608,6 +602,67 @@ extern const unsigned char arg_32bit_rc[MAX_INSN_ARGS + 1]; extern const unsigned char arg_32bit_u6[MAX_INSN_ARGS + 1]; extern const unsigned char arg_32bit_limm[MAX_INSN_ARGS + 1]; +/* Address types used in the NPS-400. See page 367 of the NPS-400 CTOP + Instruction Set Reference Manual v2.4 for a description of address types. */ + +typedef enum +{ + /* Addresses in memory. */ + + /* Buffer descriptor. */ + ARC_NPS400_ADDRTYPE_BD, + + /* Job identifier. */ + ARC_NPS400_ADDRTYPE_JID, + + /* Linked Buffer Descriptor. */ + ARC_NPS400_ADDRTYPE_LBD, + + /* Multicast Buffer Descriptor. */ + ARC_NPS400_ADDRTYPE_MBD, + + /* Summarized Address. */ + ARC_NPS400_ADDRTYPE_SD, + + /* SMEM Security Context Local Memory. */ + ARC_NPS400_ADDRTYPE_SM, + + /* Extended Address. */ + ARC_NPS400_ADDRTYPE_XA, + + /* Extended Summarized Address. */ + ARC_NPS400_ADDRTYPE_XD, + + /* CMEM offset addresses. */ + + /* On-demand Counter Descriptor. */ + ARC_NPS400_ADDRTYPE_CD, + + /* CMEM Buffer Descriptor. */ + ARC_NPS400_ADDRTYPE_CBD, + + /* CMEM Job Identifier. */ + ARC_NPS400_ADDRTYPE_CJID, + + /* CMEM Linked Buffer Descriptor. */ + ARC_NPS400_ADDRTYPE_CLBD, + + /* CMEM Offset. */ + ARC_NPS400_ADDRTYPE_CM, + + /* CMEM Summarized Address. */ + ARC_NPS400_ADDRTYPE_CSD, + + /* CMEM Extended Address. */ + ARC_NPS400_ADDRTYPE_CXA, + + /* CMEM Extended Summarized Address. */ + ARC_NPS400_ADDRTYPE_CXD + +} arc_nps_address_type; + +#define ARC_NUM_ADDRTYPES 16 + #ifdef __cplusplus } #endif diff --git a/external/gpl3/binutils.old/dist/include/opcode/arm.h b/external/gpl3/binutils.old/dist/include/opcode/arm.h index 60715cf8828..83b3f22c68f 100644 --- a/external/gpl3/binutils.old/dist/include/opcode/arm.h +++ b/external/gpl3/binutils.old/dist/include/opcode/arm.h @@ -1,5 +1,5 @@ /* ARM assembler/disassembler support. - Copyright (C) 2004-2016 Free Software Foundation, Inc. + Copyright (C) 2004-2018 Free Software Foundation, Inc. This file is part of GDB and GAS. @@ -64,12 +64,16 @@ #define ARM_EXT2_FP16_INST 0x00000020 /* ARM V8.2A FP16 instructions. */ #define ARM_EXT2_V8M_MAIN 0x00000040 /* ARMv8-M Mainline. */ #define ARM_EXT2_RAS 0x00000080 /* RAS extension. */ +#define ARM_EXT2_V8_3A 0x00000100 /* ARM V8.3A. */ +#define ARM_EXT2_V8A 0x00000200 /* ARMv8-A. */ +#define ARM_EXT2_V8_4A 0x00000400 /* ARM V8.4A. */ +#define ARM_EXT2_FP16_FML 0x00000800 /* ARM V8.2A FP16-FML instructions. */ /* Co-processor space extensions. */ #define ARM_CEXT_XSCALE 0x00000001 /* Allow MIA etc. */ #define ARM_CEXT_MAVERICK 0x00000002 /* Use Cirrus/DSP coprocessor. */ -#define ARM_CEXT_IWMMXT 0x00000004 /* Intel Wireless MMX technology coprocessor. */ -#define ARM_CEXT_IWMMXT2 0x00000008 /* Intel Wireless MMX technology coprocessor version 2. */ +#define ARM_CEXT_IWMMXT 0x00000004 /* Intel Wireless MMX technology coprocessor. */ +#define ARM_CEXT_IWMMXT2 0x00000008 /* Intel Wireless MMX technology coprocessor version 2. */ #define FPU_ENDIAN_PURE 0x80000000 /* Pure-endian doubles. */ #define FPU_ENDIAN_BIG 0 /* Double words-big-endian. */ @@ -91,7 +95,8 @@ #define FPU_CRYPTO_EXT_ARMV8 0x00008000 /* Crypto for ARMv8. */ #define CRC_EXT_ARMV8 0x00004000 /* CRC32 for ARMv8. */ #define FPU_VFP_EXT_ARMV8xD 0x00002000 /* Single-precision FP for ARMv8. */ -#define FPU_NEON_EXT_RDMA 0x00001000 /* v8.1 Adv.SIMD extensions. */ +#define FPU_NEON_EXT_RDMA 0x00001000 /* v8.1 Adv.SIMD extensions. */ +#define FPU_NEON_EXT_DOTPROD 0x00000800 /* Dot Product extension. */ /* Architectures are the sum of the base and extensions. The ARM ARM (rev E) defines the following: ARMv3, ARMv3M, ARMv4xM, ARMv4, ARMv4TxM, ARMv4T, @@ -105,12 +110,14 @@ #define ARM_AEXT_V3M (ARM_AEXT_V3 | ARM_EXT_V3M) #define ARM_AEXT_V4xM (ARM_AEXT_V3 | ARM_EXT_V4) #define ARM_AEXT_V4 (ARM_AEXT_V3M | ARM_EXT_V4) -#define ARM_AEXT_V4TxM (ARM_AEXT_V4xM | ARM_EXT_V4T) -#define ARM_AEXT_V4T (ARM_AEXT_V4 | ARM_EXT_V4T) +#define ARM_AEXT_V4TxM (ARM_AEXT_V4xM | ARM_EXT_V4T | ARM_EXT_OS) +#define ARM_AEXT_V4T (ARM_AEXT_V4 | ARM_EXT_V4T | ARM_EXT_OS) #define ARM_AEXT_V5xM (ARM_AEXT_V4xM | ARM_EXT_V5) #define ARM_AEXT_V5 (ARM_AEXT_V4 | ARM_EXT_V5) -#define ARM_AEXT_V5TxM (ARM_AEXT_V5xM | ARM_EXT_V4T | ARM_EXT_V5T) -#define ARM_AEXT_V5T (ARM_AEXT_V5 | ARM_EXT_V4T | ARM_EXT_V5T) +#define ARM_AEXT_V5TxM (ARM_AEXT_V5xM | ARM_EXT_V4T | ARM_EXT_V5T \ + | ARM_EXT_OS) +#define ARM_AEXT_V5T (ARM_AEXT_V5 | ARM_EXT_V4T | ARM_EXT_V5T \ + | ARM_EXT_OS) #define ARM_AEXT_V5TExP (ARM_AEXT_V5T | ARM_EXT_V5ExP) #define ARM_AEXT_V5TE (ARM_AEXT_V5TExP | ARM_EXT_V5E) #define ARM_AEXT_V5TEJ (ARM_AEXT_V5TE | ARM_EXT_V5J) @@ -135,7 +142,7 @@ #define ARM_AEXT_V6M_ONLY \ ((ARM_EXT_BARRIER | ARM_EXT_V6M | ARM_EXT_THUMB_MSR) & ~(ARM_AEXT_NOTM)) #define ARM_AEXT_V6M \ - ((ARM_AEXT_V6K | ARM_AEXT_V6M_ONLY) & ~(ARM_AEXT_NOTM)) + ((ARM_AEXT_V6K | ARM_AEXT_V6M_ONLY) & ~(ARM_AEXT_NOTM | ARM_EXT_OS)) #define ARM_AEXT_V6SM (ARM_AEXT_V6M | ARM_EXT_OS) #define ARM_AEXT_V7M \ ((ARM_AEXT_V7_ARM | ARM_EXT_V6M | ARM_EXT_V7M | ARM_EXT_DIV) \ @@ -146,13 +153,20 @@ #define ARM_AEXT_V8A \ (ARM_AEXT_V7A | ARM_EXT_MP | ARM_EXT_SEC | ARM_EXT_DIV | ARM_EXT_ADIV \ | ARM_EXT_VIRT | ARM_EXT_V8) -#define ARM_AEXT2_V8A (ARM_EXT2_V6T2_V8M | ARM_EXT2_ATOMICS) +#define ARM_AEXT2_V8AR (ARM_EXT2_V6T2_V8M | ARM_EXT2_ATOMICS) +#define ARM_AEXT2_V8A (ARM_AEXT2_V8AR | ARM_EXT2_V8A) #define ARM_AEXT2_V8_1A (ARM_AEXT2_V8A | ARM_EXT2_PAN) #define ARM_AEXT2_V8_2A (ARM_AEXT2_V8_1A | ARM_EXT2_V8_2A | ARM_EXT2_RAS) +#define ARM_AEXT2_V8_3A (ARM_AEXT2_V8_2A | ARM_EXT2_V8_3A) +#define ARM_AEXT2_V8_4A (ARM_AEXT2_V8_3A | ARM_EXT2_FP16_FML | ARM_EXT2_V8_4A) #define ARM_AEXT_V8M_BASE (ARM_AEXT_V6SM | ARM_EXT_DIV) #define ARM_AEXT_V8M_MAIN ARM_AEXT_V7M +#define ARM_AEXT_V8M_MAIN_DSP ARM_AEXT_V7EM #define ARM_AEXT2_V8M (ARM_EXT2_V8M | ARM_EXT2_ATOMICS | ARM_EXT2_V6T2_V8M) #define ARM_AEXT2_V8M_MAIN (ARM_AEXT2_V8M | ARM_EXT2_V8M_MAIN) +#define ARM_AEXT2_V8M_MAIN_DSP ARM_AEXT2_V8M_MAIN +#define ARM_AEXT_V8R ARM_AEXT_V8A +#define ARM_AEXT2_V8R ARM_AEXT2_V8AR /* Processors with specific extensions in the co-processor space. */ #define ARM_ARCH_XSCALE ARM_FEATURE_LOW (ARM_AEXT_V5TE, ARM_CEXT_XSCALE) @@ -216,6 +230,9 @@ | FPU_VFP_ARMV8) #define FPU_ARCH_CRYPTO_NEON_VFP_ARMV8 \ ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8 | FPU_NEON_ARMV8 | FPU_VFP_ARMV8) +#define FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD \ + ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8 | FPU_NEON_ARMV8 | FPU_VFP_ARMV8 \ + | FPU_NEON_EXT_DOTPROD) #define ARCH_CRC_ARMV8 ARM_FEATURE_COPROC (CRC_EXT_ARMV8) #define FPU_ARCH_NEON_VFP_ARMV8_1 \ ARM_FEATURE_COPROC (FPU_NEON_ARMV8 \ @@ -224,6 +241,8 @@ #define FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1 \ ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8 | FPU_NEON_ARMV8 | FPU_VFP_ARMV8 \ | FPU_NEON_EXT_RDMA) +#define FPU_ARCH_DOTPROD_NEON_VFP_ARMV8 \ + ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD | FPU_NEON_ARMV8 | FPU_VFP_ARMV8) #define FPU_ARCH_ENDIAN_PURE ARM_FEATURE_COPROC (FPU_ENDIAN_PURE) @@ -263,18 +282,29 @@ #define ARM_ARCH_V7M ARM_FEATURE_CORE (ARM_AEXT_V7M, ARM_EXT2_V6T2_V8M) #define ARM_ARCH_V7EM ARM_FEATURE_CORE (ARM_AEXT_V7EM, ARM_EXT2_V6T2_V8M) #define ARM_ARCH_V8A ARM_FEATURE_CORE (ARM_AEXT_V8A, ARM_AEXT2_V8A) +#define ARM_ARCH_V8A_CRC ARM_FEATURE (ARM_AEXT_V8A, ARM_AEXT2_V8A, \ + CRC_EXT_ARMV8) #define ARM_ARCH_V8_1A ARM_FEATURE (ARM_AEXT_V8A, ARM_AEXT2_V8_1A, \ CRC_EXT_ARMV8 | FPU_NEON_EXT_RDMA) #define ARM_ARCH_V8_2A ARM_FEATURE (ARM_AEXT_V8A, ARM_AEXT2_V8_2A, \ CRC_EXT_ARMV8 | FPU_NEON_EXT_RDMA) +#define ARM_ARCH_V8_3A ARM_FEATURE (ARM_AEXT_V8A, ARM_AEXT2_V8_3A, \ + CRC_EXT_ARMV8 | FPU_NEON_EXT_RDMA) +#define ARM_ARCH_V8_4A ARM_FEATURE (ARM_AEXT_V8A, ARM_AEXT2_V8_4A, \ + CRC_EXT_ARMV8 | FPU_NEON_EXT_RDMA \ + | FPU_NEON_EXT_DOTPROD) #define ARM_ARCH_V8M_BASE ARM_FEATURE_CORE (ARM_AEXT_V8M_BASE, ARM_AEXT2_V8M) #define ARM_ARCH_V8M_MAIN ARM_FEATURE_CORE (ARM_AEXT_V8M_MAIN, \ ARM_AEXT2_V8M_MAIN) +#define ARM_ARCH_V8M_MAIN_DSP ARM_FEATURE_CORE (ARM_AEXT_V8M_MAIN_DSP, \ + ARM_AEXT2_V8M_MAIN_DSP) +#define ARM_ARCH_V8R ARM_FEATURE_CORE (ARM_AEXT_V8R, ARM_AEXT2_V8R) /* Some useful combinations: */ #define ARM_ARCH_NONE ARM_FEATURE_LOW (0, 0) #define FPU_NONE ARM_FEATURE_LOW (0, 0) #define ARM_ANY ARM_FEATURE (-1, -1, 0) /* Any basic core. */ +#define FPU_ANY ARM_FEATURE_COPROC (-1) /* Any FPU. */ #define ARM_FEATURE_ALL ARM_FEATURE (-1, -1, -1)/* All CPU and FPU features. */ #define FPU_ANY_HARD ARM_FEATURE_COPROC (FPU_FPA | FPU_VFP_HARD | FPU_MAVERICK) /* Extensions containing some Thumb-2 instructions. If any is present, Thumb @@ -341,31 +371,28 @@ typedef struct ((CPU).core[0] == ((arm_feature_set)ARM_ANY).core[0] \ && (CPU).core[1] == ((arm_feature_set)ARM_ANY).core[1]) -#define ARM_MERGE_FEATURE_SETS(TARG,F1,F2) \ - do { \ - (TARG).core[0] = (F1).core[0] | (F2).core[0];\ - (TARG).core[1] = (F1).core[1] | (F2).core[1];\ - (TARG).coproc = (F1).coproc | (F2).coproc; \ - } while (0) - -#define ARM_CLEAR_FEATURE(TARG,F1,F2) \ - do { \ - (TARG).core[0] = (F1).core[0] &~ (F2).core[0];\ - (TARG).core[1] = (F1).core[1] &~ (F2).core[1];\ - (TARG).coproc = (F1).coproc &~ (F2).coproc; \ - } while (0) - -#define ARM_FEATURE_COPY(F1, F2) \ - do { \ - (F1).core[0] = (F2).core[0]; \ - (F1).core[1] = (F2).core[1]; \ - (F1).coproc = (F2).coproc; \ - } while (0) +#define ARM_MERGE_FEATURE_SETS(TARG,F1,F2) \ + do \ + { \ + (TARG).core[0] = (F1).core[0] | (F2).core[0]; \ + (TARG).core[1] = (F1).core[1] | (F2).core[1]; \ + (TARG).coproc = (F1).coproc | (F2).coproc; \ + } \ + while (0) + +#define ARM_CLEAR_FEATURE(TARG,F1,F2) \ + do \ + { \ + (TARG).core[0] = (F1).core[0] &~ (F2).core[0]; \ + (TARG).core[1] = (F1).core[1] &~ (F2).core[1]; \ + (TARG).coproc = (F1).coproc &~ (F2).coproc; \ + } \ + while (0) #define ARM_FEATURE_EQUAL(T1,T2) \ - ((T1).core[0] == (T2).core[0] \ + ( (T1).core[0] == (T2).core[0] \ && (T1).core[1] == (T2).core[1] \ - && (T1).coproc == (T2).coproc) + && (T1).coproc == (T2).coproc) #define ARM_FEATURE_ZERO(T) \ ((T).core[0] == 0 && (T).core[1] == 0 && (T).coproc == 0) diff --git a/external/gpl3/binutils.old/dist/include/opcode/avr.h b/external/gpl3/binutils.old/dist/include/opcode/avr.h index feb4f88d785..d694c23501c 100644 --- a/external/gpl3/binutils.old/dist/include/opcode/avr.h +++ b/external/gpl3/binutils.old/dist/include/opcode/avr.h @@ -1,6 +1,6 @@ /* Opcode table for the Atmel AVR micro controllers. - Copyright (C) 2000-2016 Free Software Foundation, Inc. + Copyright (C) 2000-2018 Free Software Foundation, Inc. Contributed by Denis Chertykov <denisc@overta.ru> This program is free software; you can redistribute it and/or modify @@ -110,6 +110,7 @@ z - Z pointer register (for [e]lpm Rd,Z[+]) M - immediate value from 0 to 255 n - immediate value from 0 to 255 ( n = ~M ). Relocation impossible + N - immediate value from 0 to 255. Relocation impossible s - immediate value from 0 to 7 P - Port address value from 0 to 63. (in, out) p - Port address value from 0 to 31. (cbi, sbi, sbic, sbis) @@ -306,3 +307,7 @@ AVR_INSN (eijmp, "", "1001010000011001", 1, AVR_ISA_EIND, 0x9419) /* DES instruction for encryption and decryption. */ AVR_INSN (des, "E", "10010100EEEE1011", 1, AVR_ISA_DES, 0x940B) +/* Operands are evaluated by hand and won't pop new fux-ups. + The pseudo-insn is hidden behind NOP so that avr-dis.c don't see it. */ +AVR_INSN (__gcc_isr, "", "0000000000000000", 1, AVR_ISA_1200, 0x0) + diff --git a/external/gpl3/binutils.old/dist/include/opcode/bfin.h b/external/gpl3/binutils.old/dist/include/opcode/bfin.h index 22e9a7d49c2..cdfd2870805 100644 --- a/external/gpl3/binutils.old/dist/include/opcode/bfin.h +++ b/external/gpl3/binutils.old/dist/include/opcode/bfin.h @@ -1,5 +1,5 @@ /* bfin.h -- Header file for ADI Blackfin opcode table - Copyright (C) 2005-2016 Free Software Foundation, Inc. + Copyright (C) 2005-2018 Free Software Foundation, Inc. This file is part of GDB, GAS, and the GNU binutils. diff --git a/external/gpl3/binutils.old/dist/include/opcode/cgen.h b/external/gpl3/binutils.old/dist/include/opcode/cgen.h index 706d830d1fe..d8823762a26 100644 --- a/external/gpl3/binutils.old/dist/include/opcode/cgen.h +++ b/external/gpl3/binutils.old/dist/include/opcode/cgen.h @@ -1,6 +1,6 @@ /* Header file for targets using CGEN: Cpu tools GENerator. - Copyright (C) 1996-2016 Free Software Foundation, Inc. + Copyright (C) 1996-2018 Free Software Foundation, Inc. This file is part of GDB, the GNU debugger, and the GNU Binutils. diff --git a/external/gpl3/binutils.old/dist/include/opcode/convex.h b/external/gpl3/binutils.old/dist/include/opcode/convex.h index c09aa80c0cf..4d97edc04d7 100644 --- a/external/gpl3/binutils.old/dist/include/opcode/convex.h +++ b/external/gpl3/binutils.old/dist/include/opcode/convex.h @@ -1,5 +1,5 @@ /* Information for instruction disassembly on the Convex. - Copyright (C) 1989-2016 Free Software Foundation, Inc. + Copyright (C) 1989-2018 Free Software Foundation, Inc. This file is part of GDB. diff --git a/external/gpl3/binutils.old/dist/include/opcode/cr16.h b/external/gpl3/binutils.old/dist/include/opcode/cr16.h index 169834400c4..a5870b372e1 100644 --- a/external/gpl3/binutils.old/dist/include/opcode/cr16.h +++ b/external/gpl3/binutils.old/dist/include/opcode/cr16.h @@ -1,5 +1,5 @@ /* cr16.h -- Header file for CR16 opcode and register tables. - Copyright (C) 2007-2016 Free Software Foundation, Inc. + Copyright (C) 2007-2018 Free Software Foundation, Inc. Contributed by M R Swami Reddy This file is part of GAS, GDB and the GNU binutils. @@ -404,9 +404,6 @@ extern const unsigned int cr16_num_cc; /* Table of instructions with no operands. */ extern const char * cr16_no_op_insn[]; -/* Current instruction we're assembling. */ -extern const inst *instruction; - /* A macro for representing the instruction "constant" opcode, that is, the FIXED part of the instruction. The "constant" opcode is represented as a 32-bit unsigned long, where OPC is expanded (by a left SHIFT) @@ -439,11 +436,6 @@ typedef unsigned long long ULONGLONG; typedef unsigned long dwordU; typedef unsigned short wordU; -/* Globals to store opcode data and build the instruction. */ -extern wordU cr16_words[3]; -extern ULONGLONG cr16_allWords; -extern ins cr16_currInsn; - /* Prototypes for function in cr16-dis.c. */ extern void cr16_make_instruction (void); extern int cr16_match_opcode (void); diff --git a/external/gpl3/binutils.old/dist/include/opcode/cris.h b/external/gpl3/binutils.old/dist/include/opcode/cris.h index 8628ed21d39..a93c7a772c8 100644 --- a/external/gpl3/binutils.old/dist/include/opcode/cris.h +++ b/external/gpl3/binutils.old/dist/include/opcode/cris.h @@ -1,5 +1,5 @@ /* cris.h -- Header file for CRIS opcode and register tables. - Copyright (C) 2000-2016 Free Software Foundation, Inc. + Copyright (C) 2000-2018 Free Software Foundation, Inc. Contributed by Axis Communications AB, Lund, Sweden. Originally written for GAS 1.38.1 by Mikael Asker. Updated, BFDized and GNUified by Hans-Peter Nilsson. diff --git a/external/gpl3/binutils.old/dist/include/opcode/crx.h b/external/gpl3/binutils.old/dist/include/opcode/crx.h index c2d2325561d..7e4bac568f7 100644 --- a/external/gpl3/binutils.old/dist/include/opcode/crx.h +++ b/external/gpl3/binutils.old/dist/include/opcode/crx.h @@ -1,5 +1,5 @@ /* crx.h -- Header file for CRX opcode and register tables. - Copyright (C) 2004-2016 Free Software Foundation, Inc. + Copyright (C) 2004-2018 Free Software Foundation, Inc. Contributed by Tomer Levi, NSC, Israel. Originally written for GAS 2.12 by Tomer Levi, NSC, Israel. Updates, BFDizing, GNUifying and ELF support by Tomer Levi. @@ -384,14 +384,11 @@ extern const int crx_num_traps; #define NUMTRAPS crx_num_traps /* cst4 operand mapping. */ -extern const int cst4_map[]; -extern const int cst4_maps; +extern const int crx_cst4_map[]; +extern const int crx_cst4_maps; /* Table of instructions with no operands. */ -extern const char* no_op_insn[]; - -/* Current instruction we're assembling. */ -extern const inst *instruction; +extern const char* crx_no_op_insn[]; /* A macro for representing the instruction "constant" opcode, that is, the FIXED part of the instruction. The "constant" opcode is represented diff --git a/external/gpl3/binutils.old/dist/include/opcode/d10v.h b/external/gpl3/binutils.old/dist/include/opcode/d10v.h index a468e589133..7630faa7038 100644 --- a/external/gpl3/binutils.old/dist/include/opcode/d10v.h +++ b/external/gpl3/binutils.old/dist/include/opcode/d10v.h @@ -1,5 +1,5 @@ /* d10v.h -- Header file for D10V opcode table - Copyright (C) 1996-2016 Free Software Foundation, Inc. + Copyright (C) 1996-2018 Free Software Foundation, Inc. Written by Martin Hunt (hunt@cygnus.com), Cygnus Support This file is part of GDB, GAS, and the GNU binutils. diff --git a/external/gpl3/binutils.old/dist/include/opcode/d30v.h b/external/gpl3/binutils.old/dist/include/opcode/d30v.h index 910d1550c11..9fcea8a7715 100644 --- a/external/gpl3/binutils.old/dist/include/opcode/d30v.h +++ b/external/gpl3/binutils.old/dist/include/opcode/d30v.h @@ -1,5 +1,5 @@ /* d30v.h -- Header file for D30V opcode table - Copyright (C) 1997-2016 Free Software Foundation, Inc. + Copyright (C) 1997-2018 Free Software Foundation, Inc. Written by Martin Hunt (hunt@cygnus.com), Cygnus Solutions This file is part of GDB, GAS, and the GNU binutils. diff --git a/external/gpl3/binutils.old/dist/include/opcode/dlx.h b/external/gpl3/binutils.old/dist/include/opcode/dlx.h index 1d53c52a57d..94ce805192c 100644 --- a/external/gpl3/binutils.old/dist/include/opcode/dlx.h +++ b/external/gpl3/binutils.old/dist/include/opcode/dlx.h @@ -1,5 +1,5 @@ /* Table of opcodes for the DLX microprocess. - Copyright (C) 2002-2016 Free Software Foundation, Inc. + Copyright (C) 2002-2018 Free Software Foundation, Inc. This file is part of GDB and GAS. diff --git a/external/gpl3/binutils.old/dist/include/opcode/ft32.h b/external/gpl3/binutils.old/dist/include/opcode/ft32.h index 193ada6c48c..2381926ef49 100644 --- a/external/gpl3/binutils.old/dist/include/opcode/ft32.h +++ b/external/gpl3/binutils.old/dist/include/opcode/ft32.h @@ -1,5 +1,5 @@ /* Definitions for decoding the ft32 opcode table. - Copyright (C) 2013-2016 Free Software Foundation, Inc. + Copyright (C) 2013-2018 Free Software Foundation, Inc. Contributed by FTDI (support@ftdichip.com) This program is free software; you can redistribute it and/or modify @@ -89,9 +89,9 @@ typedef struct ft32_opc_info_t #define FT32_FLD_K16 (1 << 14) #define FT32_FLD_K16_BIT 0 #define FT32_FLD_K16_SIZ 16 -#define FT32_FLD_K8 (1 << 15) -#define FT32_FLD_K8_BIT 0 -#define FT32_FLD_K8_SIZ 8 +#define FT32_FLD_K15 (1 << 15) +#define FT32_FLD_K15_BIT 0 +#define FT32_FLD_K15_SIZ 15 #define FT32_FLD_AL (1 << 16) #define FT32_FLD_AL_BIT 0 #define FT32_FLD_AL_SIZ 4 @@ -104,3 +104,386 @@ typedef struct ft32_opc_info_t #define FT32_FLD_R_D_POST (1 << 17) #define FT32_FLD_R_1_POST (1 << 18) + +static const unsigned int sc_form_0[] = { +0x44000000, 0x44000002, 0x44000004, 0x44000005, 0x4400000b, +0x44000010, 0x44000012, 0x44000014, 0x44000015, 0x44000018, +0x4400001b, 0x44000020, 0x44000022, 0x44000024, 0x44000025, +0x4400002b, 0x44000030, 0x44000032, 0x44000034, 0x44000035, +0x4400003b, 0x44000040, 0x44000042, 0x44000044, 0x44000045, +0x4400004b, 0x44000050, 0x44000060, 0x44000062, 0x44000065, +0x44000070, 0x44000072, 0x44000075, 0x44000080, 0x44000082, +0x44000090, 0x44000092, 0x440000a0, 0x440000a2, 0x440000b0, +0x440000d0, 0x440000d2, 0x440000d5, 0x440000e0, 0x440000e2, +0x440000f0, 0x440000f2, 0x440000f5, 0x44000100, 0x44000102, +0x44000110, 0x44000120, 0x44000122, 0x44000130, 0x44000140, +0x44000170, 0x44000180, 0x44000190, 0x440001a0, 0x440001b0, +0x440001e0, 0x440001f0, 0x44004000, 0x44004003, 0x4400400c, +0x4400400d, 0x44004010, 0x44004011, 0x44004013, 0x44004014, +0x44004016, 0x44004019, 0x4400401a, 0x44004020, 0x44004021, +0x44004028, 0x4400402a, 0x44004034, 0x44004038, 0x44004039, +0x44004040, 0x44004048, 0x44004058, 0x44004064, 0x44004074, +0x44004080, 0x44004081, 0x44004088, 0x44004089, 0x44004098, +0x440040c0, 0x440040ca, 0x440040f4, 0x44004100, 0x44004108, +0x44004109, 0x4400410a, 0x4400410b, 0x44004180, 0x44004182, +0x440041c0, 0x440041c2, 0x440041f4, 0x44004200, 0x44004202, +0x4400420b, 0x4400421b, 0x4400422b, 0x44004240, 0x44004242, +0x4400424b, 0x4400425b, 0x4400426b, 0x4400427b, 0x44004280, +0x44004282, 0x440042ab, 0x440042bb, 0x440042c0, 0x440042c2, +0x44004300, 0x44004340, 0x440043c3, 0x4400440b, 0x44004543, +0x44004553, 0x440047f4, 0x44004800, 0x44004980, 0x44004a0b, +0x44004a80, 0x44004dc0, 0x44004ff4, 0x44005003, 0x44005353, +0x4400537b, 0x440053e3, 0x44005700, 0x4400594b, 0x4400620b, +0x4400621b, 0x4400622b, 0x4400623b, 0x4400624b, 0x4400625b, +0x4400626b, 0x4400627b, 0x4400628b, 0x4400629b, 0x440062bb, +0x440062fb, 0x4400633b, 0x4400637b, 0x44006383, 0x44007f00, +0x44007f80, 0x44007fc0, 0x44007fe0, 0x44007ff0, 0x44007ff3, 0x44007ff6 +}; +static const unsigned int sc_form_1[] = { +0x44000002, 0x44008002, 0x44010002, 0x44010008, 0x44018002, +0x44020002, 0x44030002, 0x44038002 +}; +static const unsigned int sc_form_2[] = { +0x59e04002, 0x59e04012, 0x59e04022, 0x59e04032, 0x59e04042, +0x59e04052, 0x59e04072, 0x59e04082, 0x59e07ff2, 0x5de00002, +0x5de00012, 0x5de00022, 0x5de00032, 0x5de00042, 0x5de00052, +0x5de00062, 0x5de00072, 0x5de00082, 0x5de000a2, 0x5de000d2, +0x5de000e2, 0x5de000f2, 0x5de00102, 0x5de00112, 0x5de00122, +0x5de00132, 0x5de00172, 0x5de04002, 0x5de04012, 0x5de04022, +0x5de04032, 0x5de04042, 0x5de04052, 0x5de04062, 0x5de04072, +0x5de04082, 0x5de04092, 0x5de040f2, 0x5de04102, 0x5de04112, +0x5de04142, 0x5de04162, 0x5de041b2, 0x5de041f2, 0x5de04202, +0x5de0420c, 0x5de0421c, 0x5de0422c, 0x5de0423c, 0x5de04242, +0x5de0424c, 0x5de0425c, 0x5de0426c, 0x5de0427c, 0x5de0428c, +0x5de0429c, 0x5de042ac, 0x5de042cc, 0x5de042dc, 0x5de042ec, +0x5de042fc, 0x5de0430c, 0x5de0431c, 0x5de0433c, 0x5de0436c, +0x5de0437c, 0x5de04382, 0x5de043ac, 0x5de043bc, 0x5de043cc, +0x5de043dc, 0x5de04ff2, 0x5de07ff2, 0x84000000 +}; +static const unsigned int sc_form_3[] = { +0x44000010, 0x44000024, 0x44000025, 0x44000030, 0x44000034, +0x44004000, 0x4400400c, 0x4400400d, 0x44004010, 0x44004014, +0x44004028, 0x44004038, 0x44004040, 0x440040ca, 0x44004109, +0x44004880, 0x44004ac0, 0x44004e00, 0x44004e80, 0x44004ff4, +0x4400500c, 0x44005200, 0x44005680, 0x44005700, 0x4400620b, +0x44007f80, 0x44008020, 0x44008024, 0x4400c000, 0x4400c00c, +0x4400c00d, 0x4400c010, 0x4400c028, 0x4400c038, 0x4400c1f9, +0x4400cff4, 0x4400d00c, 0x4400d173, 0x4400ff80, 0x4400fff0, +0x44010030, 0x44014000, 0x4401400c, 0x4401400d, 0x44014010, +0x44014028, 0x44014074, 0x44014080, 0x440143f3, 0x44014ff4, +0x4401500c, 0x44015743, 0x44017ff0, 0x44018030, 0x4401c000, +0x4401c00c, 0x4401c010, 0x4401cff4, 0x4401d00c, 0x44020100, +0x44024000, 0x44024014, 0x44027f80, 0x4402c000, 0x44030085, +0x44034000, 0x44034109, 0x4403c000, 0x44044000, 0x44044109, +0x4404410b, 0x4404c000, 0x440680e0, 0x4406c000, 0x4406c040, +0x4406c080, 0x4406c0c0, 0x4406c300, 0x4406c3c0, 0x4406c900, +0x4406cac0, 0x4406cb40, 0x4406cbc0, 0x4406ce80, 0x4406d5c0, +0x4406d680, 0x4406d700, 0x4406d740, 0x4406d780, 0x4406dfc0, +0x44074000, 0x44074010, 0x44074e80, 0x4407c000, 0x4407c00d, +0x4407c074, 0x44084000, 0x4408c000, 0x44094000, 0x4409c000, +0x440a4000, 0x440ac000, 0x440b4000, 0x440bc000, 0x440c4000, +0x440c4040, 0x440cc000, 0x440d4000, 0x440dc000, 0x440ef340, +0x440ef400, 0x440ef440, 0x440ef4c0, 0x440ef540, 0x440ef5c0, +0x440ef6b0, 0x440ef700, 0x440ef780, 0x440ef8c0, 0x440f420d, +0x440f421d, 0x440f426d, 0x440fc180, 0x440fc1a0, 0x440fc1b0, +0x440fc1c0, 0x440fc200, 0x440fc240, 0x440fc280, 0x440fc380, +0x440fc840, 0x440fc8c0, 0x440fc900, 0x440fc980, 0x440fcd80, +0x64000000, 0x64000001, 0x64000002, 0x64000003, 0x64000004, +0x64000005, 0x64000006, 0x64000007, 0x64000008, 0x64000009, +0x6400000a, 0x6400000b, 0x6400000c, 0x6400000d, 0x6400000e, +0x6400000f, 0x64000010, 0x64000011, 0x64000012, 0x64000013, +0x64000014, 0x64000015, 0x64000017, 0x64000018, 0x64000019, +0x6400001a, 0x6400001d, 0x64000020, 0x64000023, 0x64000024, +0x64000027, 0x6400002b, 0x6400002c, 0x6400002d, 0x64000030, +0x64000035, 0x6400003c, 0x64000040, 0x64000048, 0x64000064, +0x6400006c, 0x64000080, 0x640000ff, 0x64000100, 0x640001b0, +0x640001b8, 0x64000200, 0x64000218, 0x64000240, 0x6400024c, +0x64000250, 0x640003e8, 0x64000400, 0x64000409, 0x64000554, +0x64000600, 0x64000690, 0x64000730, 0x640007ff, 0x64000800, +0x64000900, 0x64000fff, 0x64001000, 0x6400182c, 0x64001b70, +0x64001c1c, 0x64001c24, 0x64001fff, 0x64002000, 0x64003598, +0x640036ec, 0x64003fff, 0x640052c0, 0x640054e4, 0x64005a3c, +0x64005fa4, 0x64006468, 0x64006718, 0x64008000, 0x6400c000, +0x6400ffff, 0x64010000, 0x64010008, 0x640102a0, 0x64014515, +0x64040000, 0x64050000, 0x6407c000, 0x640ff800, 0x640ffc00, +0x640ffc01, 0x640ffc02, 0x640fffff, 0x8c000000, 0x94000000, +0x94000018, 0x9400001c, 0x94000020, 0x98000000, 0xa0000000, +0xa8000000, 0xa8000001, 0xa8000002, 0xa8000003, 0xa8008000, +0xa8008002, 0xa8010000, 0xa8018000, 0xa8020000, 0xa8068000, +0xa8068005, 0xa8068006, 0xa8068007, 0xa806800f, 0xa8068040, +0xa8068043, 0xa8068054, 0xa8070000, 0xa8078000, 0xa8080000, +0xa8090000, 0xa80b0000, 0xa80f801b, 0xaa000000, 0xaa008000, +0xaa008002, 0xaa00800c, 0xaa010000, 0xaa068000, 0xaa068002, +0xaa068004, 0xaa068006, 0xaa068008, 0xaa06800a, 0xaa06800c, +0xaa068024, 0xaa070000, 0xaa070002, 0xaa07000c, 0xaa078000, +0xaa078002, 0xac000000, 0xac000004, 0xac000008, 0xac00000c, +0xac000010, 0xac000014, 0xac000018, 0xac00001c, 0xac000020, +0xac000024, 0xac000028, 0xac00002c, 0xac000030, 0xac000038, +0xac00003c, 0xac000040, 0xac000044, 0xac000058, 0xac00006c, +0xac008000, 0xac008004, 0xac008008, 0xac00800c, 0xac008010, +0xac008018, 0xac008020, 0xac008024, 0xac008028, 0xac008030, +0xac008034, 0xac008038, 0xac00803c, 0xac008044, 0xac008070, +0xac008078, 0xac010000, 0xac010004, 0xac010008, 0xac01000c, +0xac010010, 0xac01002c, 0xac018000, 0xac018004, 0xac018008, +0xac020000, 0xac020004, 0xac020008, 0xac028000, 0xac030000, +0xac038000, 0xac048000, 0xac050000, 0xac068000, 0xac068004, +0xac068008, 0xac06800c, 0xac068010, 0xac068014, 0xac068018, +0xac06801c, 0xac068020, 0xac068024, 0xac068028, 0xac06802c, +0xac068030, 0xac068034, 0xac068038, 0xac06803c, 0xac068040, +0xac068044, 0xac068048, 0xac06804c, 0xac068050, 0xac068058, +0xac070000, 0xac070004, 0xac070008, 0xac07000c, 0xac070010, +0xac070014, 0xac070018, 0xac07001c, 0xac070024, 0xac070028, +0xac07002c, 0xac070038, 0xac07003c, 0xac070040, 0xac070044, +0xac070048, 0xac07004c, 0xac070054, 0xac078000, 0xac078004, +0xac078008, 0xac07800c, 0xac078024, 0xac07803c, 0xac080000, +0xac080004, 0xac080008, 0xac08003c, 0xac088000, 0xac088004, +0xac088008, 0xac08800c, 0xac090000, 0xac098000, 0xac0a0000, +0xac0a0004, 0xac0a8000, 0xac0b0000, 0xac0c0000, 0xac0d8004, +0xac0d8008, 0xac0e8090, 0xac0e8094, 0xac0e80fc, 0xac0f8018, +0xac0f801c, 0xac0f8020, 0xac0f8024, 0xac0f8028, 0xac0f802c, +0xac0f8030, 0xac0f8034, 0xac0f8038, 0xac0f803c, 0xac0f8040, +0xac0f8044, 0xac0f8048, 0xac0f804c, 0xac0f8050, 0xac0f8054, +0xac0f8058, 0xb0000000, 0xb0000006, 0xb0000009, 0xb0000018, +0xb0000019, 0xb000001b, 0xb0008000, 0xb0010000, 0xb0018000, +0xb0018087, 0xb0020000, 0xb0030000, 0xb0070000, 0xb0078000, +0xb0080000, 0xb2000000, 0xb2000006, 0xb200000c, 0xb2008000, +0xb200800c, 0xb2010000, 0xb2018000, 0xb2020000, 0xb2078000, +0xb4000000, 0xb4000004, 0xb4000008, 0xb400000c, 0xb4000010, +0xb4000014, 0xb4000018, 0xb400001c, 0xb4000020, 0xb4000024, +0xb4000028, 0xb400002c, 0xb4000030, 0xb4000034, 0xb4000038, +0xb400003c, 0xb4000040, 0xb4000044, 0xb4000048, 0xb4000050, +0xb4000054, 0xb400006c, 0xb4008000, 0xb4008004, 0xb4008008, +0xb400800c, 0xb4008010, 0xb4008014, 0xb4008018, 0xb400801c, +0xb4008020, 0xb4008024, 0xb4008028, 0xb400802c, 0xb4008034, +0xb4008038, 0xb4008040, 0xb4008044, 0xb400806c, 0xb4008070, +0xb4010000, 0xb4010004, 0xb4010008, 0xb401000c, 0xb4010010, +0xb4010018, 0xb401001c, 0xb4010020, 0xb4010024, 0xb4010028, +0xb401002c, 0xb4018000, 0xb4018004, 0xb4018008, 0xb4018018, +0xb401801c, 0xb4020000, 0xb4020004, 0xb4020008, 0xb402000c, +0xb4020018, 0xb4028000, 0xb4028018, 0xb4030000, 0xb4030008, +0xb4030018, 0xb4038000, 0xb4068000, 0xb4068004, 0xb4068008, +0xb406800c, 0xb4068018, 0xb406801c, 0xb4068020, 0xb4068024, +0xb4068028, 0xb4070000, 0xb4070004, 0xb4070008, 0xb4070010, +0xb4070018, 0xb4070024, 0xb4070028, 0xb4078000, 0xb4078024, +0xb4080000, 0xb4080004, 0xb4090000, 0xb4098000, 0xb40c8000 +}; + +#define N_SC_FORM0 (sizeof (sc_form_0) / sizeof (unsigned int)) +#define N_SC_FORM1 (sizeof (sc_form_1) / sizeof (unsigned int)) +#define N_SC_FORM2 (sizeof (sc_form_2) / sizeof (unsigned int)) +#define N_SC_FORM3 (sizeof (sc_form_3) / sizeof (unsigned int)) + +static int +sc_compar (const void *va, const void *vb) +{ + const unsigned int *a = (unsigned int *) va; + const unsigned int *b = (unsigned int *) vb; + return (*a - *b); +} + +static int ATTRIBUTE_UNUSED +ft32_shortcode (unsigned int op32, unsigned int *sc) +{ + unsigned int Rd_mask = 31 << 20; + unsigned int R1_mask = 31 << 15; + unsigned int R2_mask = 2047 << 4; + unsigned int Rd = (op32 >> 20) & 31; + unsigned int R1 = (op32 >> 15) & 31; + unsigned int R2 = (op32 >> 4) & 2047; + unsigned int lookup; + unsigned int *find = NULL; + unsigned int code = 0, r = 0; + + /* Form 0 */ + if (Rd == R1) + { + lookup = op32 & ~Rd_mask & ~R1_mask; + find = (unsigned int *) bsearch (&lookup, sc_form_0, N_SC_FORM0, + sizeof (unsigned int), sc_compar); + code = find - sc_form_0; + r = Rd; + } + + /* Form 1 */ + if ((find == NULL) && (Rd == R2)) + { + lookup = op32 & ~Rd_mask & ~R2_mask; + find = (unsigned int *) bsearch (&lookup, sc_form_1, N_SC_FORM1, + sizeof (unsigned int), sc_compar); + code = find - sc_form_1 + N_SC_FORM0; + r = Rd; + } + + /* Form 2 */ + if (find == NULL) + { + lookup = op32 & ~R1_mask; + find = (unsigned int *) bsearch (&lookup, sc_form_2, N_SC_FORM2, + sizeof (unsigned int), sc_compar); + code = find - sc_form_2 + (N_SC_FORM0 + N_SC_FORM1); + r = R1; + } + + /* Form 3 */ + if (find == NULL) + { + lookup = op32 & ~Rd_mask; + find = (unsigned int *) bsearch (&lookup, sc_form_3, N_SC_FORM3, + sizeof (unsigned int), sc_compar); + code = find - sc_form_3 + (N_SC_FORM0 + N_SC_FORM1 + N_SC_FORM2); + r = Rd; + } + + *sc = (code << 5) | r; + + return (find != NULL); +} + +static int ATTRIBUTE_UNUSED +ft32_split_shortcode (unsigned int op32, unsigned int code15[2]) +{ + int code3; + unsigned int code30; + + switch (op32 >> 27) + { + case 2: + code3 = 0; + break; + case 3: + code3 = 1; + break; + case 4: + code3 = 2; + break; + case 5: + code3 = 3; + break; + case 6: + code3 = 4; + break; + case 9: + code3 = 5; + break; + case 10: + code3 = 6; + break; + case 14: + code3 = 7; + break; + default: + code3 = -1; + break; + } + + if (code3 == -1) + { + code15[0] = 0; + code15[1] = 0; + return 0; + } + else + { + code30 = ((op32 & 0x07ffffff) << 3) | code3; + code15[0] = code30 & 0x7fff; + code15[1] = (code30 >> 15) & 0x7fff; + return 1; + } +} + +static unsigned int ATTRIBUTE_UNUSED +ft32_merge_shortcode (unsigned int code15[2]) +{ + static const unsigned char pat3[] = { 2, 3, 4, 5, 6, 9, 10, 14 }; + + unsigned int code30 = (code15[1] << 15) | code15[0]; + unsigned int code27 = code30 >> 3; + unsigned int code3 = code30 & 7; + unsigned int pattern = pat3[code3]; + return (pattern << 27) | code27; +} + +static int ATTRIBUTE_UNUSED +ft32_decode_shortcode (unsigned int pc, unsigned int op32, unsigned int *sc) +{ + int code3; + unsigned int code30; + unsigned int code15[2]; + size_t i; + + switch (op32 >> 27) + { + case 2: + code3 = 0; + break; + case 3: + code3 = 1; + break; + case 4: + code3 = 2; + break; + case 5: + code3 = 3; + break; + case 6: + code3 = 4; + break; + case 9: + code3 = 5; + break; + case 10: + code3 = 6; + break; + case 14: + code3 = 7; + break; + default: + code3 = -1; + break; + } + + if (code3 == -1) + return 0; + else + { + code30 = ((op32 & 0x07ffffff) << 3) | code3; + code15[0] = code30 & 0x7fff; + code15[1] = (code30 >> 15) & 0x7fff; + for (i = 0; i < 2; i++) + { + unsigned int code = code15[i] >> 5; + unsigned int r = code15[i] & 0x1f; + + if (code < 768) + { + if (code < N_SC_FORM0) + sc[i] = sc_form_0[code] | (r << 20) | (r << 15); + else if (code < (N_SC_FORM0 + N_SC_FORM1)) + sc[i] = sc_form_1[code - N_SC_FORM0] | (r << 20) | (r << 4); + else if (code < (N_SC_FORM0 + N_SC_FORM1 + N_SC_FORM2)) + sc[i] = sc_form_2[code - (N_SC_FORM0 + N_SC_FORM1)] + | (r << 15); + else + sc[i] = sc_form_3[code - + (N_SC_FORM0 + N_SC_FORM1 + N_SC_FORM2)] + | (r << 20); + } + else + { + int jtype = (code15[i] >> 9) & 15; + int offset = code15[i] & 511; + if (offset & 256) + offset -= 512; + if (jtype < 14) + sc[i] = + 0x00200000 | ((jtype >> 1) << 22) | ((jtype & 1) << 19); + else if (jtype == 14) + sc[i] = 0x00300000; + else + sc[i] = 0x00340000; + sc[i] |= ((pc >> 2) + offset); + } + } + return 1; + } +} diff --git a/external/gpl3/binutils.old/dist/include/opcode/h8300.h b/external/gpl3/binutils.old/dist/include/opcode/h8300.h index c33c8958eab..bdda96ccad9 100644 --- a/external/gpl3/binutils.old/dist/include/opcode/h8300.h +++ b/external/gpl3/binutils.old/dist/include/opcode/h8300.h @@ -1,5 +1,5 @@ /* Opcode table for the H8/300 - Copyright (C) 1991-2016 Free Software Foundation, Inc. + Copyright (C) 1991-2018 Free Software Foundation, Inc. Written by Steve Chamberlain <sac@cygnus.com>. This file is part of GDB, the GNU Debugger and GAS, the GNU Assembler. diff --git a/external/gpl3/binutils.old/dist/include/opcode/hppa.h b/external/gpl3/binutils.old/dist/include/opcode/hppa.h index 2dcc8bc4a33..0700686b8a5 100644 --- a/external/gpl3/binutils.old/dist/include/opcode/hppa.h +++ b/external/gpl3/binutils.old/dist/include/opcode/hppa.h @@ -1,10 +1,10 @@ /* Table of opcodes for the PA-RISC. - Copyright (C) 1990-2016 Free Software Foundation, Inc. + Copyright (C) 1990-2018 Free Software Foundation, Inc. Contributed by the Center for Software Science at the University of Utah (pa-gdb-bugs@cs.utah.edu). - This file is part of GAS, the GNU Assembler, and GDB, the GNU disassembler. + This file is part of the GNU opcodes library. GAS/GDB is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by @@ -594,7 +594,7 @@ static const struct pa_opcode pa_opcodes[] = { "addibf", 0xac000000, 0xfc000000, "?dn5,b,w", pa10, 0}, { "bb", 0xc0006000, 0xffe06000, "?Bnx,!,w", pa20, FLAG_STRICT}, { "bb", 0xc0004000, 0xffe06000, "?bnx,!,w", pa10, FLAG_STRICT}, -{ "bb", 0xc4004000, 0xfc004000, "?Bnx,B,w", pa20, FLAG_STRICT}, +{ "bb", 0xc4006000, 0xfc006000, "?Bnx,B,w", pa20, FLAG_STRICT}, { "bb", 0xc4004000, 0xfc006000, "?bnx,Q,w", pa10, FLAG_STRICT}, { "bb", 0xc4004000, 0xfc006000, "?bnx,Q,w", pa10, 0}, { "bvb", 0xc0004000, 0xffe04000, "?bnx,w", pa10, 0}, diff --git a/external/gpl3/binutils.old/dist/include/opcode/i370.h b/external/gpl3/binutils.old/dist/include/opcode/i370.h deleted file mode 100644 index 848d653cbab..00000000000 --- a/external/gpl3/binutils.old/dist/include/opcode/i370.h +++ /dev/null @@ -1,266 +0,0 @@ -/* i370.h -- Header file for S/390 opcode table - Copyright (C) 1994-2016 Free Software Foundation, Inc. - PowerPC version written by Ian Lance Taylor, Cygnus Support - Rewritten for i370 ESA/390 support, Linas Vepstas <linas@linas.org> - - This file is part of GDB, GAS, and the GNU binutils. - - GDB, GAS, and the GNU binutils are free software; you can redistribute - them and/or modify them under the terms of the GNU General Public - License as published by the Free Software Foundation; either version 3, - or (at your option) any later version. - - GDB, GAS, and the GNU binutils are distributed in the hope that they - will be useful, but WITHOUT ANY WARRANTY; without even the implied - warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See - the GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this file; see the file COPYING3. If not, write to the Free - Software Foundation, 51 Franklin Street - Fifth Floor, Boston, - MA 02110-1301, USA. */ - -#ifndef I370_H -#define I370_H - -/* The opcode table is an array of struct i370_opcode. */ -typedef union -{ - unsigned int i[2]; - unsigned short s[4]; - unsigned char b[8]; -} i370_insn_t; - -struct i370_opcode -{ - /* The opcode name. */ - const char *name; - - /* the length of the instruction */ - char len; - - /* The opcode itself. Those bits which will be filled in with - operands are zeroes. */ - i370_insn_t opcode; - - /* The opcode mask. This is used by the disassembler. This is a - mask containing ones indicating those bits which must match the - opcode field, and zeroes indicating those bits which need not - match (and are presumably filled in by operands). */ - i370_insn_t mask; - - /* One bit flags for the opcode. These are used to indicate which - specific processors support the instructions. The defined values - are listed below. */ - unsigned long flags; - - /* An array of operand codes. Each code is an index into the - operand table. They appear in the order which the operands must - appear in assembly code, and are terminated by a zero. */ - unsigned char operands[8]; -}; - -/* The table itself is sorted by major opcode number, and is otherwise - in the order in which the disassembler should consider - instructions. */ -extern const struct i370_opcode i370_opcodes[]; -extern const int i370_num_opcodes; - -/* Values defined for the flags field of a struct i370_opcode. */ - -/* Opcode is defined for the original 360 architecture. */ -#define I370_OPCODE_360 (0x01) - -/* Opcode is defined for the 370 architecture. */ -#define I370_OPCODE_370 (0x02) - -/* Opcode is defined for the 370-XA architecture. */ -#define I370_OPCODE_370_XA (0x04) - -/* Opcode is defined for the ESA/370 architecture. */ -#define I370_OPCODE_ESA370 (0x08) - -/* Opcode is defined for the ESA/390 architecture. */ -#define I370_OPCODE_ESA390 (0x10) - -/* Opcode is defined for the ESA/390 w/ BFP facility. */ -#define I370_OPCODE_ESA390_BF (0x20) - -/* Opcode is defined for the ESA/390 w/ branch & set authority facility. */ -#define I370_OPCODE_ESA390_BS (0x40) - -/* Opcode is defined for the ESA/390 w/ checksum facility. */ -#define I370_OPCODE_ESA390_CK (0x80) - -/* Opcode is defined for the ESA/390 w/ compare & move extended facility. */ -#define I370_OPCODE_ESA390_CM (0x100) - -/* Opcode is defined for the ESA/390 w/ flt.pt. support extensions facility. */ -#define I370_OPCODE_ESA390_FX (0x200) - -/* Opcode is defined for the ESA/390 w/ HFP facility. */ -#define I370_OPCODE_ESA390_HX (0x400) - -/* Opcode is defined for the ESA/390 w/ immediate & relative facility. */ -#define I370_OPCODE_ESA390_IR (0x800) - -/* Opcode is defined for the ESA/390 w/ move-inverse facility. */ -#define I370_OPCODE_ESA390_MI (0x1000) - -/* Opcode is defined for the ESA/390 w/ program-call-fast facility. */ -#define I370_OPCODE_ESA390_PC (0x2000) - -/* Opcode is defined for the ESA/390 w/ perform-locked-op facility. */ -#define I370_OPCODE_ESA390_PL (0x4000) - -/* Opcode is defined for the ESA/390 w/ square-root facility. */ -#define I370_OPCODE_ESA390_QR (0x8000) - -/* Opcode is defined for the ESA/390 w/ resume-program facility. */ -#define I370_OPCODE_ESA390_RP (0x10000) - -/* Opcode is defined for the ESA/390 w/ set-address-space-fast facility. */ -#define I370_OPCODE_ESA390_SA (0x20000) - -/* Opcode is defined for the ESA/390 w/ subspace group facility. */ -#define I370_OPCODE_ESA390_SG (0x40000) - -/* Opcode is defined for the ESA/390 w/ string facility. */ -#define I370_OPCODE_ESA390_SR (0x80000) - -/* Opcode is defined for the ESA/390 w/ trap facility. */ -#define I370_OPCODE_ESA390_TR (0x100000) - -#define I370_OPCODE_ESA390_SUPERSET (0x1fffff) - - -/* The operands table is an array of struct i370_operand. */ - -struct i370_operand -{ - /* The number of bits in the operand. */ - int bits; - - /* How far the operand is left shifted in the instruction. */ - int shift; - - /* Insertion function. This is used by the assembler. To insert an - operand value into an instruction, check this field. - - If it is NULL, execute - i |= (op & ((1 << o->bits) - 1)) << o->shift; - (i is the instruction which we are filling in, o is a pointer to - this structure, and op is the opcode value; this assumes twos - complement arithmetic). - - If this field is not NULL, then simply call it with the - instruction and the operand value. It will return the new value - of the instruction. If the ERRMSG argument is not NULL, then if - the operand value is illegal, *ERRMSG will be set to a warning - string (the operand will be inserted in any case). If the - operand value is legal, *ERRMSG will be unchanged (most operands - can accept any value). */ - i370_insn_t (*insert) - (i370_insn_t instruction, long op, const char **errmsg); - - /* Extraction function. This is used by the disassembler. To - extract this operand type from an instruction, check this field. - - If it is NULL, compute - op = ((i) >> o->shift) & ((1 << o->bits) - 1); - if ((o->flags & I370_OPERAND_SIGNED) != 0 - && (op & (1 << (o->bits - 1))) != 0) - op -= 1 << o->bits; - (i is the instruction, o is a pointer to this structure, and op - is the result; this assumes twos complement arithmetic). - - If this field is not NULL, then simply call it with the - instruction value. It will return the value of the operand. If - the INVALID argument is not NULL, *INVALID will be set to - non-zero if this operand type can not actually be extracted from - this operand (i.e., the instruction does not match). If the - operand is valid, *INVALID will not be changed. */ - long (*extract) (i370_insn_t instruction, int *invalid); - - /* One bit syntax flags. */ - unsigned long flags; - - /* name -- handy for debugging, otherwise pointless */ - char * name; -}; - -/* Elements in the table are retrieved by indexing with values from - the operands field of the i370_opcodes table. */ - -extern const struct i370_operand i370_operands[]; - -/* Values defined for the flags field of a struct i370_operand. */ - -/* This operand should be wrapped in parentheses rather than - separated from the previous by a comma. This is used for S, RS and - SS form instructions which want their operands to look like - reg,displacement(basereg) */ -#define I370_OPERAND_SBASE (0x01) - -/* This operand is a base register. It may or may not appear next - to an index register, i.e. either of the two forms - reg,displacement(basereg) - reg,displacement(index,basereg) */ -#define I370_OPERAND_BASE (0x02) - -/* This pair of operands should be wrapped in parentheses rather than - separated from the last by a comma. This is used for the RX form - instructions which want their operands to look like - reg,displacement(index,basereg) */ -#define I370_OPERAND_INDEX (0x04) - -/* This operand names a register. The disassembler uses this to print - register names with a leading 'r'. */ -#define I370_OPERAND_GPR (0x08) - -/* This operand names a floating point register. The disassembler - prints these with a leading 'f'. */ -#define I370_OPERAND_FPR (0x10) - -/* This operand is a displacement. */ -#define I370_OPERAND_RELATIVE (0x20) - -/* This operand is a length, such as that in SS form instructions. */ -#define I370_OPERAND_LENGTH (0x40) - -/* This operand is optional, and is zero if omitted. This is used for - the optional B2 field in the shift-left, shift-right instructions. The - assembler must count the number of operands remaining on the line, - and the number of operands remaining for the opcode, and decide - whether this operand is present or not. The disassembler should - print this operand out only if it is not zero. */ -#define I370_OPERAND_OPTIONAL (0x80) - - -/* Define some misc macros. We keep them with the operands table - for simplicity. The macro table is an array of struct i370_macro. */ - -struct i370_macro -{ - /* The macro name. */ - const char *name; - - /* The number of operands the macro takes. */ - unsigned int operands; - - /* One bit flags for the opcode. These are used to indicate which - specific processors support the instructions. The values are the - same as those for the struct i370_opcode flags field. */ - unsigned long flags; - - /* A format string to turn the macro into a normal instruction. - Each %N in the string is replaced with operand number N (zero - based). */ - const char *format; -}; - -extern const struct i370_macro i370_macros[]; -extern const int i370_num_macros; - - -#endif /* I370_H */ diff --git a/external/gpl3/binutils.old/dist/include/opcode/i386.h b/external/gpl3/binutils.old/dist/include/opcode/i386.h index 783024513aa..40972750048 100644 --- a/external/gpl3/binutils.old/dist/include/opcode/i386.h +++ b/external/gpl3/binutils.old/dist/include/opcode/i386.h @@ -1,5 +1,5 @@ /* opcode/i386.h -- Intel 80386 opcode macros - Copyright (C) 1989-2016 Free Software Foundation, Inc. + Copyright (C) 1989-2018 Free Software Foundation, Inc. This file is part of GAS, the GNU Assembler, and GDB, the GNU Debugger. @@ -43,12 +43,6 @@ compatible instructions. */ #define SYSV386_COMPAT 1 #endif -#ifndef OLDGCC_COMPAT -/* Set non-zero to cater for old (<= 2.8.1) versions of gcc that could - generate nonsense fsubp, fsubrp, fdivp and fdivrp with operands - reversed. */ -#define OLDGCC_COMPAT SYSV386_COMPAT -#endif #define MOV_AX_DISP32 0xa0 #define POP_SEG_SHORT 0x07 @@ -77,6 +71,7 @@ #define XACQUIRE_PREFIX_OPCODE 0xf2 #define XRELEASE_PREFIX_OPCODE 0xf3 #define BND_PREFIX_OPCODE 0xf2 +#define NOTRACK_PREFIX_OPCODE 0x3e #define TWO_BYTE_OPCODE_ESCAPE 0x0f #define NOP_OPCODE (char) 0x90 diff --git a/external/gpl3/binutils.old/dist/include/opcode/i860.h b/external/gpl3/binutils.old/dist/include/opcode/i860.h deleted file mode 100644 index bc1a4ee3d3d..00000000000 --- a/external/gpl3/binutils.old/dist/include/opcode/i860.h +++ /dev/null @@ -1,506 +0,0 @@ -/* Table of opcodes for the i860. - Copyright (C) 1989-2016 Free Software Foundation, Inc. - - This file is part of GAS, the GNU Assembler, and GDB, the GNU disassembler. - - GAS/GDB is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3, or (at your option) - any later version. - - GAS/GDB is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with GAS or GDB; see the file COPYING3. If not, write to - the Free Software Foundation, 51 Franklin Street - Fifth Floor, - Boston, MA 02110-1301, USA. */ - -/* Structure of an opcode table entry. */ -struct i860_opcode -{ - /* The opcode name. */ - const char *name; - - /* Bits that must be set. */ - unsigned long match; - - /* Bits that must not be set. */ - unsigned long lose; - - const char *args; - - /* Nonzero if this is a possible expand-instruction. */ - char expand; -}; - - -enum expand_type -{ - E_MOV = 1, E_ADDR, E_U32, E_AND, E_S32, E_DELAY, XP_ONLY -}; - - -/* All i860 opcodes are 32 bits, except for the pseudo-instructions - and the operations utilizing a 32-bit address expression, an - unsigned 32-bit constant, or a signed 32-bit constant. - These opcodes are expanded into a two-instruction sequence for - any situation where the immediate operand does not fit in 32 bits. - In the case of the add and subtract operations the expansion is - to a three-instruction sequence (ex: orh, or, adds). In cases - where the address is to be relocated, the instruction is - expanded to handle the worse case, this could be optimized at - the final link if the actual address were known. - - The pseudoinstructions are: mov, fmov, pmov, nop, and fnop. - These instructions are implemented as a one or two instruction - sequence of other operations. - - The match component is a mask saying which bits must match a - particular opcode in order for an instruction to be an instance - of that opcode. - - The args component is a string containing one character - for each operand of the instruction. - -Kinds of operands: - # Number used by optimizer. It is ignored. - 1 src1 integer register. - 2 src2 integer register. - d dest register. - c ctrlreg control register. - i 16 bit immediate. - I 16 bit immediate, aligned 2^0. (ld.b) - J 16 bit immediate, aligned 2^1. (ld.s) - K 16 bit immediate, aligned 2^2. (ld.l, {p}fld.l, fst.l) - L 16 bit immediate, aligned 2^3. ({p}fld.d, fst.d) - M 16 bit immediate, aligned 2^4. ({p}fld.q, fst.q) - 5 5 bit immediate. - l lbroff 26 bit PC relative immediate. - r sbroff 16 bit PC relative immediate. - s split 16 bit immediate. - S split 16 bit immediate, aligned 2^0. (st.b) - T split 16 bit immediate, aligned 2^1. (st.s) - U split 16 bit immediate, aligned 2^2. (st.l) - e src1 floating point register. - f src2 floating point register. - g dest floating point register. */ - - -/* The order of the opcodes in this table is significant. The assembler - requires that all instances of the same mnemonic must be consecutive. - If they aren't, the assembler will not function properly. - - The order of opcodes does not affect the disassembler. */ - -static const struct i860_opcode i860_opcodes[] = -{ -/* REG-Format Instructions. */ -{ "ld.c", 0x30000000, 0xcc000000, "c,d", 0 }, /* ld.c csrc2,idest */ -{ "ld.b", 0x00000000, 0xfc000000, "1(2),d", 0 }, /* ld.b isrc1(isrc2),idest */ -{ "ld.b", 0x04000000, 0xf8000000, "I(2),d", E_ADDR }, /* ld.b #const(isrc2),idest */ -{ "ld.s", 0x10000000, 0xec000001, "1(2),d", 0 }, /* ld.s isrc1(isrc2),idest */ -{ "ld.s", 0x14000000, 0xe8000001, "J(2),d", E_ADDR }, /* ld.s #const(isrc2),idest */ -{ "ld.l", 0x10000001, 0xec000000, "1(2),d", 0 }, /* ld.l isrc1(isrc2),idest */ -{ "ld.l", 0x14000001, 0xe8000000, "K(2),d", E_ADDR }, /* ld.l #const(isrc2),idest */ - -{ "st.c", 0x38000000, 0xc4000000, "1,c", 0 }, /* st.c isrc1ni,csrc2 */ -{ "st.b", 0x0c000000, 0xf0000000, "1,S(2)", E_ADDR }, /* st.b isrc1ni,#const(isrc2) */ -{ "st.s", 0x1c000000, 0xe0000001, "1,T(2)", E_ADDR }, /* st.s isrc1ni,#const(isrc2) */ -{ "st.l", 0x1c000001, 0xe0000000, "1,U(2)", E_ADDR }, /* st.l isrc1ni,#const(isrc2) */ - -{ "ixfr", 0x08000000, 0xf4000000, "1,g", 0 }, /* ixfr isrc1ni,fdest */ - -{ "fld.l", 0x20000002, 0xdc000001, "1(2),g", 0 }, /* fld.l isrc1(isrc2),fdest */ -{ "fld.l", 0x24000002, 0xd8000001, "K(2),g", E_ADDR }, /* fld.l #const(isrc2),fdest */ -{ "fld.l", 0x20000003, 0xdc000000, "1(2)++,g", 0 }, /* fld.l isrc1(isrc2)++,fdest */ -{ "fld.l", 0x24000003, 0xd8000000, "K(2)++,g", E_ADDR }, /* fld.l #const(isrc2)++,fdest */ -{ "fld.d", 0x20000000, 0xdc000007, "1(2),g", 0 }, /* fld.d isrc1(isrc2),fdest */ -{ "fld.d", 0x24000000, 0xd8000007, "L(2),g", E_ADDR }, /* fld.d #const(isrc2),fdest */ -{ "fld.d", 0x20000001, 0xdc000006, "1(2)++,g", 0 }, /* fld.d isrc1(isrc2)++,fdest */ -{ "fld.d", 0x24000001, 0xd8000006, "L(2)++,g", E_ADDR }, /* fld.d #const(isrc2)++,fdest */ -{ "fld.q", 0x20000004, 0xdc000003, "1(2),g", 0 }, /* fld.q isrc1(isrc2),fdest */ -{ "fld.q", 0x24000004, 0xd8000003, "M(2),g", E_ADDR }, /* fld.q #const(isrc2),fdest */ -{ "fld.q", 0x20000005, 0xdc000002, "1(2)++,g", 0 }, /* fld.q isrc1(isrc2)++,fdest */ -{ "fld.q", 0x24000005, 0xd8000002, "M(2)++,g", E_ADDR }, /* fld.q #const(isrc2)++,fdest */ - -{ "pfld.l", 0x60000002, 0x9c000001, "1(2),g", 0 }, /* pfld.l isrc1(isrc2),fdest */ -{ "pfld.l", 0x64000002, 0x98000001, "K(2),g", E_ADDR }, /* pfld.l #const(isrc2),fdest */ -{ "pfld.l", 0x60000003, 0x9c000000, "1(2)++,g", 0 }, /* pfld.l isrc1(isrc2)++,fdest */ -{ "pfld.l", 0x64000003, 0x98000000, "K(2)++,g", E_ADDR }, /* pfld.l #const(isrc2)++,fdest */ -{ "pfld.d", 0x60000000, 0x9c000007, "1(2),g", 0 }, /* pfld.d isrc1(isrc2),fdest */ -{ "pfld.d", 0x64000000, 0x98000007, "L(2),g", E_ADDR }, /* pfld.d #const(isrc2),fdest */ -{ "pfld.d", 0x60000001, 0x9c000006, "1(2)++,g", 0 }, /* pfld.d isrc1(isrc2)++,fdest */ -{ "pfld.d", 0x64000001, 0x98000006, "L(2)++,g", E_ADDR }, /* pfld.d #const(isrc2)++,fdest */ -{ "pfld.q", 0x60000004, 0x9c000003, "1(2),g", XP_ONLY }, /* pfld.q isrc1(isrc2),fdest */ -{ "pfld.q", 0x64000004, 0x98000003, "L(2),g", XP_ONLY }, /* pfld.q #const(isrc2),fdest */ -{ "pfld.q", 0x60000005, 0x9c000002, "1(2)++,g", XP_ONLY }, /* pfld.q isrc1(isrc2)++,fdest */ -{ "pfld.q", 0x64000005, 0x98000002, "L(2)++,g", XP_ONLY }, /* pfld.q #const(isrc2)++,fdest */ - -{ "fst.l", 0x28000002, 0xd4000001, "g,1(2)", 0 }, /* fst.l fdest,isrc1(isrc2) */ -{ "fst.l", 0x2c000002, 0xd0000001, "g,K(2)", E_ADDR }, /* fst.l fdest,#const(isrc2) */ -{ "fst.l", 0x28000003, 0xd4000000, "g,1(2)++", 0 }, /* fst.l fdest,isrc1(isrc2)++ */ -{ "fst.l", 0x2c000003, 0xd0000000, "g,K(2)++", E_ADDR }, /* fst.l fdest,#const(isrc2)++ */ -{ "fst.d", 0x28000000, 0xd4000007, "g,1(2)", 0 }, /* fst.d fdest,isrc1(isrc2) */ -{ "fst.d", 0x2c000000, 0xd0000007, "g,L(2)", E_ADDR }, /* fst.d fdest,#const(isrc2) */ -{ "fst.d", 0x28000001, 0xd4000006, "g,1(2)++", 0 }, /* fst.d fdest,isrc1(isrc2)++ */ -{ "fst.d", 0x2c000001, 0xd0000006, "g,L(2)++", E_ADDR }, /* fst.d fdest,#const(isrc2)++ */ -{ "fst.q", 0x28000004, 0xd4000003, "g,1(2)", 0 }, /* fst.d fdest,isrc1(isrc2) */ -{ "fst.q", 0x2c000004, 0xd0000003, "g,M(2)", E_ADDR }, /* fst.d fdest,#const(isrc2) */ -{ "fst.q", 0x28000005, 0xd4000002, "g,1(2)++", 0 }, /* fst.d fdest,isrc1(isrc2)++ */ -{ "fst.q", 0x2c000005, 0xd0000002, "g,M(2)++", E_ADDR }, /* fst.d fdest,#const(isrc2)++ */ - -{ "pst.d", 0x3c000000, 0xc0000007, "g,L(2)", E_ADDR }, /* pst.d fdest,#const(isrc2) */ -{ "pst.d", 0x3c000001, 0xc0000006, "g,L(2)++", E_ADDR }, /* pst.d fdest,#const(isrc2)++ */ - -{ "addu", 0x80000000, 0x7c000000, "1,2,d", 0 }, /* addu isrc1,isrc2,idest */ -{ "addu", 0x84000000, 0x78000000, "i,2,d", E_S32 }, /* addu #const,isrc2,idest */ -{ "adds", 0x90000000, 0x6c000000, "1,2,d", 0 }, /* adds isrc1,isrc2,idest */ -{ "adds", 0x94000000, 0x68000000, "i,2,d", E_S32 }, /* adds #const,isrc2,idest */ -{ "subu", 0x88000000, 0x74000000, "1,2,d", 0 }, /* subu isrc1,isrc2,idest */ -{ "subu", 0x8c000000, 0x70000000, "i,2,d", E_S32 }, /* subu #const,isrc2,idest */ -{ "subs", 0x98000000, 0x64000000, "1,2,d", 0 }, /* subs isrc1,isrc2,idest */ -{ "subs", 0x9c000000, 0x60000000, "i,2,d", E_S32 }, /* subs #const,isrc2,idest */ - -{ "shl", 0xa0000000, 0x5c000000, "1,2,d", 0 }, /* shl isrc1,isrc2,idest */ -{ "shl", 0xa4000000, 0x58000000, "i,2,d", 0 }, /* shl #const,isrc2,idest */ -{ "shr", 0xa8000000, 0x54000000, "1,2,d", 0 }, /* shr isrc1,isrc2,idest */ -{ "shr", 0xac000000, 0x50000000, "i,2,d", 0 }, /* shr #const,isrc2,idest */ -{ "shrd", 0xb0000000, 0x4c000000, "1,2,d", 0 }, /* shrd isrc1,isrc2,idest */ -{ "shra", 0xb8000000, 0x44000000, "1,2,d", 0 }, /* shra isrc1,isrc2,idest */ -{ "shra", 0xbc000000, 0x40000000, "i,2,d", 0 }, /* shra #const,isrc2,idest */ - -{ "mov", 0xa0000000, 0x5c00f800, "2,d", 0 }, /* shl r0,isrc2,idest */ -{ "mov", 0x94000000, 0x69e00000, "i,d", E_MOV }, /* adds #const,r0,idest */ -{ "nop", 0xa0000000, 0x5ffff800, "", 0 }, /* shl r0,r0,r0 */ -{ "fnop", 0xb0000000, 0x4ffff800, "", 0 }, /* shrd r0,r0,r0 */ - -{ "trap", 0x44000000, 0xb8000000, "1,2,d", 0 }, /* trap isrc1ni,isrc2,idest */ - -{ "flush", 0x34000004, 0xc81f0003, "L(2)", E_ADDR }, /* flush #const(isrc2) */ -{ "flush", 0x34000005, 0xc81f0002, "L(2)++", E_ADDR }, /* flush #const(isrc2)++ */ - -{ "and", 0xc0000000, 0x3c000000, "1,2,d", 0 }, /* and isrc1,isrc2,idest */ -{ "and", 0xc4000000, 0x38000000, "i,2,d", E_AND }, /* and #const,isrc2,idest */ -{ "andh", 0xcc000000, 0x30000000, "i,2,d", 0 }, /* andh #const,isrc2,idest */ -{ "andnot", 0xd0000000, 0x2c000000, "1,2,d", 0 }, /* andnot isrc1,isrc2,idest */ -{ "andnot", 0xd4000000, 0x28000000, "i,2,d", E_U32 }, /* andnot #const,isrc2,idest */ -{ "andnoth", 0xdc000000, 0x20000000, "i,2,d", 0 }, /* andnoth #const,isrc2,idest */ -{ "or", 0xe0000000, 0x1c000000, "1,2,d", 0 }, /* or isrc1,isrc2,idest */ -{ "or", 0xe4000000, 0x18000000, "i,2,d", E_U32 }, /* or #const,isrc2,idest */ -{ "orh", 0xec000000, 0x10000000, "i,2,d", 0 }, /* orh #const,isrc2,idest */ -{ "xor", 0xf0000000, 0x0c000000, "1,2,d", 0 }, /* xor isrc1,isrc2,idest */ -{ "xor", 0xf4000000, 0x08000000, "i,2,d", E_U32 }, /* xor #const,isrc2,idest */ -{ "xorh", 0xfc000000, 0x00000000, "i,2,d", 0 }, /* xorh #const,isrc2,idest */ - -{ "bte", 0x58000000, 0xa4000000, "1,2,r", 0 }, /* bte isrc1s,isrc2,sbroff */ -{ "bte", 0x5c000000, 0xa0000000, "5,2,r", 0 }, /* bte #const5,isrc2,sbroff */ -{ "btne", 0x50000000, 0xac000000, "1,2,r", 0 }, /* btne isrc1s,isrc2,sbroff */ -{ "btne", 0x54000000, 0xa8000000, "5,2,r", 0 }, /* btne #const5,isrc2,sbroff */ -{ "bla", 0xb4000000, 0x48000000, "1,2,r", E_DELAY }, /* bla isrc1s,isrc2,sbroff */ -{ "bri", 0x40000000, 0xbc000000, "1", E_DELAY }, /* bri isrc1ni */ - -/* Core Escape Instruction Format */ -{ "lock", 0x4c000001, 0xb000001e, "", 0 }, /* lock set BL in dirbase */ -{ "calli", 0x4c000002, 0xb000001d, "1", E_DELAY }, /* calli isrc1ni */ -{ "intovr", 0x4c000004, 0xb000001b, "", 0 }, /* intovr trap on integer overflow */ -{ "unlock", 0x4c000007, 0xb0000018, "", 0 }, /* unlock clear BL in dirbase */ -{ "ldio.l", 0x4c000408, 0xb00003f7, "2,d", XP_ONLY }, /* ldio.l isrc2,idest */ -{ "ldio.s", 0x4c000208, 0xb00005f7, "2,d", XP_ONLY }, /* ldio.s isrc2,idest */ -{ "ldio.b", 0x4c000008, 0xb00007f7, "2,d", XP_ONLY }, /* ldio.b isrc2,idest */ -{ "stio.l", 0x4c000409, 0xb00003f6, "1,2", XP_ONLY }, /* stio.l isrc1ni,isrc2 */ -{ "stio.s", 0x4c000209, 0xb00005f6, "1,2", XP_ONLY }, /* stio.s isrc1ni,isrc2 */ -{ "stio.b", 0x4c000009, 0xb00007f6, "1,2", XP_ONLY }, /* stio.b isrc1ni,isrc2 */ -{ "ldint.l", 0x4c00040a, 0xb00003f5, "2,d", XP_ONLY }, /* ldint.l isrc2,idest */ -{ "ldint.s", 0x4c00020a, 0xb00005f5, "2,d", XP_ONLY }, /* ldint.s isrc2,idest */ -{ "ldint.b", 0x4c00000a, 0xb00007f5, "2,d", XP_ONLY }, /* ldint.b isrc2,idest */ -{ "scyc.b", 0x4c00000b, 0xb00007f4, "2", XP_ONLY }, /* scyc.b isrc2 */ - -/* CTRL-Format Instructions */ -{ "br", 0x68000000, 0x94000000, "l", E_DELAY }, /* br lbroff */ -{ "call", 0x6c000000, 0x90000000, "l", E_DELAY }, /* call lbroff */ -{ "bc", 0x70000000, 0x8c000000, "l", 0 }, /* bc lbroff */ -{ "bc.t", 0x74000000, 0x88000000, "l", E_DELAY }, /* bc.t lbroff */ -{ "bnc", 0x78000000, 0x84000000, "l", 0 }, /* bnc lbroff */ -{ "bnc.t", 0x7c000000, 0x80000000, "l", E_DELAY }, /* bnc.t lbroff */ - -/* Floating Point Escape Instruction Format - pfam.p fsrc1,fsrc2,fdest. */ -{ "r2p1.ss", 0x48000400, 0xb40001ff, "e,f,g", 0 }, -{ "r2p1.sd", 0x48000480, 0xb400017f, "e,f,g", 0 }, -{ "r2p1.dd", 0x48000580, 0xb400007f, "e,f,g", 0 }, -{ "r2pt.ss", 0x48000401, 0xb40001fe, "e,f,g", 0 }, -{ "r2pt.sd", 0x48000481, 0xb400017e, "e,f,g", 0 }, -{ "r2pt.dd", 0x48000581, 0xb400007e, "e,f,g", 0 }, -{ "r2ap1.ss", 0x48000402, 0xb40001fd, "e,f,g", 0 }, -{ "r2ap1.sd", 0x48000482, 0xb400017d, "e,f,g", 0 }, -{ "r2ap1.dd", 0x48000582, 0xb400007d, "e,f,g", 0 }, -{ "r2apt.ss", 0x48000403, 0xb40001fc, "e,f,g", 0 }, -{ "r2apt.sd", 0x48000483, 0xb400017c, "e,f,g", 0 }, -{ "r2apt.dd", 0x48000583, 0xb400007c, "e,f,g", 0 }, -{ "i2p1.ss", 0x48000404, 0xb40001fb, "e,f,g", 0 }, -{ "i2p1.sd", 0x48000484, 0xb400017b, "e,f,g", 0 }, -{ "i2p1.dd", 0x48000584, 0xb400007b, "e,f,g", 0 }, -{ "i2pt.ss", 0x48000405, 0xb40001fa, "e,f,g", 0 }, -{ "i2pt.sd", 0x48000485, 0xb400017a, "e,f,g", 0 }, -{ "i2pt.dd", 0x48000585, 0xb400007a, "e,f,g", 0 }, -{ "i2ap1.ss", 0x48000406, 0xb40001f9, "e,f,g", 0 }, -{ "i2ap1.sd", 0x48000486, 0xb4000179, "e,f,g", 0 }, -{ "i2ap1.dd", 0x48000586, 0xb4000079, "e,f,g", 0 }, -{ "i2apt.ss", 0x48000407, 0xb40001f8, "e,f,g", 0 }, -{ "i2apt.sd", 0x48000487, 0xb4000178, "e,f,g", 0 }, -{ "i2apt.dd", 0x48000587, 0xb4000078, "e,f,g", 0 }, -{ "rat1p2.ss", 0x48000408, 0xb40001f7, "e,f,g", 0 }, -{ "rat1p2.sd", 0x48000488, 0xb4000177, "e,f,g", 0 }, -{ "rat1p2.dd", 0x48000588, 0xb4000077, "e,f,g", 0 }, -{ "m12apm.ss", 0x48000409, 0xb40001f6, "e,f,g", 0 }, -{ "m12apm.sd", 0x48000489, 0xb4000176, "e,f,g", 0 }, -{ "m12apm.dd", 0x48000589, 0xb4000076, "e,f,g", 0 }, -{ "ra1p2.ss", 0x4800040a, 0xb40001f5, "e,f,g", 0 }, -{ "ra1p2.sd", 0x4800048a, 0xb4000175, "e,f,g", 0 }, -{ "ra1p2.dd", 0x4800058a, 0xb4000075, "e,f,g", 0 }, -{ "m12ttpa.ss", 0x4800040b, 0xb40001f4, "e,f,g", 0 }, -{ "m12ttpa.sd", 0x4800048b, 0xb4000174, "e,f,g", 0 }, -{ "m12ttpa.dd", 0x4800058b, 0xb4000074, "e,f,g", 0 }, -{ "iat1p2.ss", 0x4800040c, 0xb40001f3, "e,f,g", 0 }, -{ "iat1p2.sd", 0x4800048c, 0xb4000173, "e,f,g", 0 }, -{ "iat1p2.dd", 0x4800058c, 0xb4000073, "e,f,g", 0 }, -{ "m12tpm.ss", 0x4800040d, 0xb40001f2, "e,f,g", 0 }, -{ "m12tpm.sd", 0x4800048d, 0xb4000172, "e,f,g", 0 }, -{ "m12tpm.dd", 0x4800058d, 0xb4000072, "e,f,g", 0 }, -{ "ia1p2.ss", 0x4800040e, 0xb40001f1, "e,f,g", 0 }, -{ "ia1p2.sd", 0x4800048e, 0xb4000171, "e,f,g", 0 }, -{ "ia1p2.dd", 0x4800058e, 0xb4000071, "e,f,g", 0 }, -{ "m12tpa.ss", 0x4800040f, 0xb40001f0, "e,f,g", 0 }, -{ "m12tpa.sd", 0x4800048f, 0xb4000170, "e,f,g", 0 }, -{ "m12tpa.dd", 0x4800058f, 0xb4000070, "e,f,g", 0 }, - -/* Floating Point Escape Instruction Format - pfsm.p fsrc1,fsrc2,fdest. */ -{ "r2s1.ss", 0x48000410, 0xb40001ef, "e,f,g", 0 }, -{ "r2s1.sd", 0x48000490, 0xb400016f, "e,f,g", 0 }, -{ "r2s1.dd", 0x48000590, 0xb400006f, "e,f,g", 0 }, -{ "r2st.ss", 0x48000411, 0xb40001ee, "e,f,g", 0 }, -{ "r2st.sd", 0x48000491, 0xb400016e, "e,f,g", 0 }, -{ "r2st.dd", 0x48000591, 0xb400006e, "e,f,g", 0 }, -{ "r2as1.ss", 0x48000412, 0xb40001ed, "e,f,g", 0 }, -{ "r2as1.sd", 0x48000492, 0xb400016d, "e,f,g", 0 }, -{ "r2as1.dd", 0x48000592, 0xb400006d, "e,f,g", 0 }, -{ "r2ast.ss", 0x48000413, 0xb40001ec, "e,f,g", 0 }, -{ "r2ast.sd", 0x48000493, 0xb400016c, "e,f,g", 0 }, -{ "r2ast.dd", 0x48000593, 0xb400006c, "e,f,g", 0 }, -{ "i2s1.ss", 0x48000414, 0xb40001eb, "e,f,g", 0 }, -{ "i2s1.sd", 0x48000494, 0xb400016b, "e,f,g", 0 }, -{ "i2s1.dd", 0x48000594, 0xb400006b, "e,f,g", 0 }, -{ "i2st.ss", 0x48000415, 0xb40001ea, "e,f,g", 0 }, -{ "i2st.sd", 0x48000495, 0xb400016a, "e,f,g", 0 }, -{ "i2st.dd", 0x48000595, 0xb400006a, "e,f,g", 0 }, -{ "i2as1.ss", 0x48000416, 0xb40001e9, "e,f,g", 0 }, -{ "i2as1.sd", 0x48000496, 0xb4000169, "e,f,g", 0 }, -{ "i2as1.dd", 0x48000596, 0xb4000069, "e,f,g", 0 }, -{ "i2ast.ss", 0x48000417, 0xb40001e8, "e,f,g", 0 }, -{ "i2ast.sd", 0x48000497, 0xb4000168, "e,f,g", 0 }, -{ "i2ast.dd", 0x48000597, 0xb4000068, "e,f,g", 0 }, -{ "rat1s2.ss", 0x48000418, 0xb40001e7, "e,f,g", 0 }, -{ "rat1s2.sd", 0x48000498, 0xb4000167, "e,f,g", 0 }, -{ "rat1s2.dd", 0x48000598, 0xb4000067, "e,f,g", 0 }, -{ "m12asm.ss", 0x48000419, 0xb40001e6, "e,f,g", 0 }, -{ "m12asm.sd", 0x48000499, 0xb4000166, "e,f,g", 0 }, -{ "m12asm.dd", 0x48000599, 0xb4000066, "e,f,g", 0 }, -{ "ra1s2.ss", 0x4800041a, 0xb40001e5, "e,f,g", 0 }, -{ "ra1s2.sd", 0x4800049a, 0xb4000165, "e,f,g", 0 }, -{ "ra1s2.dd", 0x4800059a, 0xb4000065, "e,f,g", 0 }, -{ "m12ttsa.ss", 0x4800041b, 0xb40001e4, "e,f,g", 0 }, -{ "m12ttsa.sd", 0x4800049b, 0xb4000164, "e,f,g", 0 }, -{ "m12ttsa.dd", 0x4800059b, 0xb4000064, "e,f,g", 0 }, -{ "iat1s2.ss", 0x4800041c, 0xb40001e3, "e,f,g", 0 }, -{ "iat1s2.sd", 0x4800049c, 0xb4000163, "e,f,g", 0 }, -{ "iat1s2.dd", 0x4800059c, 0xb4000063, "e,f,g", 0 }, -{ "m12tsm.ss", 0x4800041d, 0xb40001e2, "e,f,g", 0 }, -{ "m12tsm.sd", 0x4800049d, 0xb4000162, "e,f,g", 0 }, -{ "m12tsm.dd", 0x4800059d, 0xb4000062, "e,f,g", 0 }, -{ "ia1s2.ss", 0x4800041e, 0xb40001e1, "e,f,g", 0 }, -{ "ia1s2.sd", 0x4800049e, 0xb4000161, "e,f,g", 0 }, -{ "ia1s2.dd", 0x4800059e, 0xb4000061, "e,f,g", 0 }, -{ "m12tsa.ss", 0x4800041f, 0xb40001e0, "e,f,g", 0 }, -{ "m12tsa.sd", 0x4800049f, 0xb4000160, "e,f,g", 0 }, -{ "m12tsa.dd", 0x4800059f, 0xb4000060, "e,f,g", 0 }, - -/* Floating Point Escape Instruction Format - pfmam.p fsrc1,fsrc2,fdest. */ -{ "mr2p1.ss", 0x48000000, 0xb40005ff, "e,f,g", 0 }, -{ "mr2p1.sd", 0x48000080, 0xb400057f, "e,f,g", 0 }, -{ "mr2p1.dd", 0x48000180, 0xb400047f, "e,f,g", 0 }, -{ "mr2pt.ss", 0x48000001, 0xb40005fe, "e,f,g", 0 }, -{ "mr2pt.sd", 0x48000081, 0xb400057e, "e,f,g", 0 }, -{ "mr2pt.dd", 0x48000181, 0xb400047e, "e,f,g", 0 }, -{ "mr2mp1.ss", 0x48000002, 0xb40005fd, "e,f,g", 0 }, -{ "mr2mp1.sd", 0x48000082, 0xb400057d, "e,f,g", 0 }, -{ "mr2mp1.dd", 0x48000182, 0xb400047d, "e,f,g", 0 }, -{ "mr2mpt.ss", 0x48000003, 0xb40005fc, "e,f,g", 0 }, -{ "mr2mpt.sd", 0x48000083, 0xb400057c, "e,f,g", 0 }, -{ "mr2mpt.dd", 0x48000183, 0xb400047c, "e,f,g", 0 }, -{ "mi2p1.ss", 0x48000004, 0xb40005fb, "e,f,g", 0 }, -{ "mi2p1.sd", 0x48000084, 0xb400057b, "e,f,g", 0 }, -{ "mi2p1.dd", 0x48000184, 0xb400047b, "e,f,g", 0 }, -{ "mi2pt.ss", 0x48000005, 0xb40005fa, "e,f,g", 0 }, -{ "mi2pt.sd", 0x48000085, 0xb400057a, "e,f,g", 0 }, -{ "mi2pt.dd", 0x48000185, 0xb400047a, "e,f,g", 0 }, -{ "mi2mp1.ss", 0x48000006, 0xb40005f9, "e,f,g", 0 }, -{ "mi2mp1.sd", 0x48000086, 0xb4000579, "e,f,g", 0 }, -{ "mi2mp1.dd", 0x48000186, 0xb4000479, "e,f,g", 0 }, -{ "mi2mpt.ss", 0x48000007, 0xb40005f8, "e,f,g", 0 }, -{ "mi2mpt.sd", 0x48000087, 0xb4000578, "e,f,g", 0 }, -{ "mi2mpt.dd", 0x48000187, 0xb4000478, "e,f,g", 0 }, -{ "mrmt1p2.ss", 0x48000008, 0xb40005f7, "e,f,g", 0 }, -{ "mrmt1p2.sd", 0x48000088, 0xb4000577, "e,f,g", 0 }, -{ "mrmt1p2.dd", 0x48000188, 0xb4000477, "e,f,g", 0 }, -{ "mm12mpm.ss", 0x48000009, 0xb40005f6, "e,f,g", 0 }, -{ "mm12mpm.sd", 0x48000089, 0xb4000576, "e,f,g", 0 }, -{ "mm12mpm.dd", 0x48000189, 0xb4000476, "e,f,g", 0 }, -{ "mrm1p2.ss", 0x4800000a, 0xb40005f5, "e,f,g", 0 }, -{ "mrm1p2.sd", 0x4800008a, 0xb4000575, "e,f,g", 0 }, -{ "mrm1p2.dd", 0x4800018a, 0xb4000475, "e,f,g", 0 }, -{ "mm12ttpm.ss",0x4800000b, 0xb40005f4, "e,f,g", 0 }, -{ "mm12ttpm.sd",0x4800008b, 0xb4000574, "e,f,g", 0 }, -{ "mm12ttpm.dd",0x4800018b, 0xb4000474, "e,f,g", 0 }, -{ "mimt1p2.ss", 0x4800000c, 0xb40005f3, "e,f,g", 0 }, -{ "mimt1p2.sd", 0x4800008c, 0xb4000573, "e,f,g", 0 }, -{ "mimt1p2.dd", 0x4800018c, 0xb4000473, "e,f,g", 0 }, -{ "mm12tpm.ss", 0x4800000d, 0xb40005f2, "e,f,g", 0 }, -{ "mm12tpm.sd", 0x4800008d, 0xb4000572, "e,f,g", 0 }, -{ "mm12tpm.dd", 0x4800018d, 0xb4000472, "e,f,g", 0 }, -{ "mim1p2.ss", 0x4800000e, 0xb40005f1, "e,f,g", 0 }, -{ "mim1p2.sd", 0x4800008e, 0xb4000571, "e,f,g", 0 }, -{ "mim1p2.dd", 0x4800018e, 0xb4000471, "e,f,g", 0 }, - -/* Floating Point Escape Instruction Format - pfmsm.p fsrc1,fsrc2,fdest. */ -{ "mr2s1.ss", 0x48000010, 0xb40005ef, "e,f,g", 0 }, -{ "mr2s1.sd", 0x48000090, 0xb400056f, "e,f,g", 0 }, -{ "mr2s1.dd", 0x48000190, 0xb400046f, "e,f,g", 0 }, -{ "mr2st.ss", 0x48000011, 0xb40005ee, "e,f,g", 0 }, -{ "mr2st.sd", 0x48000091, 0xb400056e, "e,f,g", 0 }, -{ "mr2st.dd", 0x48000191, 0xb400046e, "e,f,g", 0 }, -{ "mr2ms1.ss", 0x48000012, 0xb40005ed, "e,f,g", 0 }, -{ "mr2ms1.sd", 0x48000092, 0xb400056d, "e,f,g", 0 }, -{ "mr2ms1.dd", 0x48000192, 0xb400046d, "e,f,g", 0 }, -{ "mr2mst.ss", 0x48000013, 0xb40005ec, "e,f,g", 0 }, -{ "mr2mst.sd", 0x48000093, 0xb400056c, "e,f,g", 0 }, -{ "mr2mst.dd", 0x48000193, 0xb400046c, "e,f,g", 0 }, -{ "mi2s1.ss", 0x48000014, 0xb40005eb, "e,f,g", 0 }, -{ "mi2s1.sd", 0x48000094, 0xb400056b, "e,f,g", 0 }, -{ "mi2s1.dd", 0x48000194, 0xb400046b, "e,f,g", 0 }, -{ "mi2st.ss", 0x48000015, 0xb40005ea, "e,f,g", 0 }, -{ "mi2st.sd", 0x48000095, 0xb400056a, "e,f,g", 0 }, -{ "mi2st.dd", 0x48000195, 0xb400046a, "e,f,g", 0 }, -{ "mi2ms1.ss", 0x48000016, 0xb40005e9, "e,f,g", 0 }, -{ "mi2ms1.sd", 0x48000096, 0xb4000569, "e,f,g", 0 }, -{ "mi2ms1.dd", 0x48000196, 0xb4000469, "e,f,g", 0 }, -{ "mi2mst.ss", 0x48000017, 0xb40005e8, "e,f,g", 0 }, -{ "mi2mst.sd", 0x48000097, 0xb4000568, "e,f,g", 0 }, -{ "mi2mst.dd", 0x48000197, 0xb4000468, "e,f,g", 0 }, -{ "mrmt1s2.ss", 0x48000018, 0xb40005e7, "e,f,g", 0 }, -{ "mrmt1s2.sd", 0x48000098, 0xb4000567, "e,f,g", 0 }, -{ "mrmt1s2.dd", 0x48000198, 0xb4000467, "e,f,g", 0 }, -{ "mm12msm.ss", 0x48000019, 0xb40005e6, "e,f,g", 0 }, -{ "mm12msm.sd", 0x48000099, 0xb4000566, "e,f,g", 0 }, -{ "mm12msm.dd", 0x48000199, 0xb4000466, "e,f,g", 0 }, -{ "mrm1s2.ss", 0x4800001a, 0xb40005e5, "e,f,g", 0 }, -{ "mrm1s2.sd", 0x4800009a, 0xb4000565, "e,f,g", 0 }, -{ "mrm1s2.dd", 0x4800019a, 0xb4000465, "e,f,g", 0 }, -{ "mm12ttsm.ss",0x4800001b, 0xb40005e4, "e,f,g", 0 }, -{ "mm12ttsm.sd",0x4800009b, 0xb4000564, "e,f,g", 0 }, -{ "mm12ttsm.dd",0x4800019b, 0xb4000464, "e,f,g", 0 }, -{ "mimt1s2.ss", 0x4800001c, 0xb40005e3, "e,f,g", 0 }, -{ "mimt1s2.sd", 0x4800009c, 0xb4000563, "e,f,g", 0 }, -{ "mimt1s2.dd", 0x4800019c, 0xb4000463, "e,f,g", 0 }, -{ "mm12tsm.ss", 0x4800001d, 0xb40005e2, "e,f,g", 0 }, -{ "mm12tsm.sd", 0x4800009d, 0xb4000562, "e,f,g", 0 }, -{ "mm12tsm.dd", 0x4800019d, 0xb4000462, "e,f,g", 0 }, -{ "mim1s2.ss", 0x4800001e, 0xb40005e1, "e,f,g", 0 }, -{ "mim1s2.sd", 0x4800009e, 0xb4000561, "e,f,g", 0 }, -{ "mim1s2.dd", 0x4800019e, 0xb4000461, "e,f,g", 0 }, - -{ "fmul.ss", 0x48000020, 0xb40005df, "e,f,g", 0 }, /* fmul.p fsrc1,fsrc2,fdest */ -{ "fmul.sd", 0x480000a0, 0xb400055f, "e,f,g", 0 }, /* fmul.p fsrc1,fsrc2,fdest */ -{ "fmul.dd", 0x480001a0, 0xb400045f, "e,f,g", 0 }, /* fmul.p fsrc1,fsrc2,fdest */ -{ "pfmul.ss", 0x48000420, 0xb40001df, "e,f,g", 0 }, /* pfmul.p fsrc1,fsrc2,fdest */ -{ "pfmul.sd", 0x480004a0, 0xb400015f, "e,f,g", 0 }, /* pfmul.p fsrc1,fsrc2,fdest */ -{ "pfmul.dd", 0x480005a0, 0xb400005f, "e,f,g", 0 }, /* pfmul.p fsrc1,fsrc2,fdest */ -{ "pfmul3.dd", 0x480005a4, 0xb400005b, "e,f,g", 0 }, /* pfmul3.p fsrc1,fsrc2,fdest */ -{ "fmlow.dd", 0x480001a1, 0xb400045e, "e,f,g", 0 }, /* fmlow.dd fsrc1,fsrc2,fdest */ -{ "frcp.ss", 0x48000022, 0xb40005dd, "f,g", 0 }, /* frcp.p fsrc2,fdest */ -{ "frcp.sd", 0x480000a2, 0xb400055d, "f,g", 0 }, /* frcp.p fsrc2,fdest */ -{ "frcp.dd", 0x480001a2, 0xb400045d, "f,g", 0 }, /* frcp.p fsrc2,fdest */ -{ "frsqr.ss", 0x48000023, 0xb40005dc, "f,g", 0 }, /* frsqr.p fsrc2,fdest */ -{ "frsqr.sd", 0x480000a3, 0xb400055c, "f,g", 0 }, /* frsqr.p fsrc2,fdest */ -{ "frsqr.dd", 0x480001a3, 0xb400045c, "f,g", 0 }, /* frsqr.p fsrc2,fdest */ -{ "fadd.ss", 0x48000030, 0xb40005cf, "e,f,g", 0 }, /* fadd.p fsrc1,fsrc2,fdest */ -{ "fadd.sd", 0x480000b0, 0xb400054f, "e,f,g", 0 }, /* fadd.p fsrc1,fsrc2,fdest */ -{ "fadd.dd", 0x480001b0, 0xb400044f, "e,f,g", 0 }, /* fadd.p fsrc1,fsrc2,fdest */ -{ "pfadd.ss", 0x48000430, 0xb40001cf, "e,f,g", 0 }, /* pfadd.p fsrc1,fsrc2,fdest */ -{ "pfadd.sd", 0x480004b0, 0xb400014f, "e,f,g", 0 }, /* pfadd.p fsrc1,fsrc2,fdest */ -{ "pfadd.dd", 0x480005b0, 0xb400004f, "e,f,g", 0 }, /* pfadd.p fsrc1,fsrc2,fdest */ -{ "fsub.ss", 0x48000031, 0xb40005ce, "e,f,g", 0 }, /* fsub.p fsrc1,fsrc2,fdest */ -{ "fsub.sd", 0x480000b1, 0xb400054e, "e,f,g", 0 }, /* fsub.p fsrc1,fsrc2,fdest */ -{ "fsub.dd", 0x480001b1, 0xb400044e, "e,f,g", 0 }, /* fsub.p fsrc1,fsrc2,fdest */ -{ "pfsub.ss", 0x48000431, 0xb40001ce, "e,f,g", 0 }, /* pfsub.p fsrc1,fsrc2,fdest */ -{ "pfsub.sd", 0x480004b1, 0xb400014e, "e,f,g", 0 }, /* pfsub.p fsrc1,fsrc2,fdest */ -{ "pfsub.dd", 0x480005b1, 0xb400004e, "e,f,g", 0 }, /* pfsub.p fsrc1,fsrc2,fdest */ -{ "fix.sd", 0x480000b2, 0xb400054d, "e,g", 0 }, /* fix.p fsrc1,fdest */ -{ "fix.dd", 0x480001b2, 0xb400044d, "e,g", 0 }, /* fix.p fsrc1,fdest */ -{ "pfix.sd", 0x480004b2, 0xb400014d, "e,g", 0 }, /* pfix.p fsrc1,fdest */ -{ "pfix.dd", 0x480005b2, 0xb400004d, "e,g", 0 }, /* pfix.p fsrc1,fdest */ -{ "famov.ss", 0x48000033, 0xb40005cc, "e,g", 0 }, /* famov.p fsrc1,fdest */ -{ "famov.ds", 0x48000133, 0xb40004cc, "e,g", 0 }, /* famov.p fsrc1,fdest */ -{ "famov.sd", 0x480000b3, 0xb400054c, "e,g", 0 }, /* famov.p fsrc1,fdest */ -{ "famov.dd", 0x480001b3, 0xb400044c, "e,g", 0 }, /* famov.p fsrc1,fdest */ -{ "pfamov.ss", 0x48000433, 0xb40001cc, "e,g", 0 }, /* pfamov.p fsrc1,fdest */ -{ "pfamov.ds", 0x48000533, 0xb40000cc, "e,g", 0 }, /* pfamov.p fsrc1,fdest */ -{ "pfamov.sd", 0x480004b3, 0xb400014c, "e,g", 0 }, /* pfamov.p fsrc1,fdest */ -{ "pfamov.dd", 0x480005b3, 0xb400004c, "e,g", 0 }, /* pfamov.p fsrc1,fdest */ -/* Opcode pfgt has R bit cleared; pfle has R bit set. */ -{ "pfgt.ss", 0x48000434, 0xb40001cb, "e,f,g", 0 }, /* pfgt.p fsrc1,fsrc2,fdest */ -{ "pfgt.dd", 0x48000534, 0xb40000cb, "e,f,g", 0 }, /* pfgt.p fsrc1,fsrc2,fdest */ -/* Opcode pfgt has R bit cleared; pfle has R bit set. */ -{ "pfle.ss", 0x480004b4, 0xb400014b, "e,f,g", 0 }, /* pfle.p fsrc1,fsrc2,fdest */ -{ "pfle.dd", 0x480005b4, 0xb400004b, "e,f,g", 0 }, /* pfle.p fsrc1,fsrc2,fdest */ -{ "pfeq.ss", 0x48000435, 0xb40001ca, "e,f,g", 0 }, /* pfeq.p fsrc1,fsrc2,fdest */ -{ "pfeq.dd", 0x48000535, 0xb40000ca, "e,f,g", 0 }, /* pfeq.p fsrc1,fsrc2,fdest */ -{ "ftrunc.sd", 0x480000ba, 0xb4000545, "e,g", 0 }, /* ftrunc.p fsrc1,fdest */ -{ "ftrunc.dd", 0x480001ba, 0xb4000445, "e,g", 0 }, /* ftrunc.p fsrc1,fdest */ -{ "pftrunc.sd", 0x480004ba, 0xb4000145, "e,g", 0 }, /* pftrunc.p fsrc1,fdest */ -{ "pftrunc.dd", 0x480005ba, 0xb4000045, "e,g", 0 }, /* pftrunc.p fsrc1,fdest */ -{ "fxfr", 0x48000040, 0xb40005bf, "e,d", 0 }, /* fxfr fsrc1,idest */ -{ "fiadd.ss", 0x48000049, 0xb40005b6, "e,f,g", 0 }, /* fiadd.w fsrc1,fsrc2,fdest */ -{ "fiadd.dd", 0x480001c9, 0xb4000436, "e,f,g", 0 }, /* fiadd.w fsrc1,fsrc2,fdest */ -{ "pfiadd.ss", 0x48000449, 0xb40001b6, "e,f,g", 0 }, /* pfiadd.w fsrc1,fsrc2,fdest */ -{ "pfiadd.dd", 0x480005c9, 0xb4000036, "e,f,g", 0 }, /* pfiadd.w fsrc1,fsrc2,fdest */ -{ "fisub.ss", 0x4800004d, 0xb40005b2, "e,f,g", 0 }, /* fisub.w fsrc1,fsrc2,fdest */ -{ "fisub.dd", 0x480001cd, 0xb4000432, "e,f,g", 0 }, /* fisub.w fsrc1,fsrc2,fdest */ -{ "pfisub.ss", 0x4800044d, 0xb40001b2, "e,f,g", 0 }, /* pfisub.w fsrc1,fsrc2,fdest */ -{ "pfisub.dd", 0x480005cd, 0xb4000032, "e,f,g", 0 }, /* pfisub.w fsrc1,fsrc2,fdest */ -{ "fzchkl", 0x480001d7, 0xb4000428, "e,f,g", 0 }, /* fzchkl fsrc1,fsrc2,fdest */ -{ "pfzchkl", 0x480005d7, 0xb4000028, "e,f,g", 0 }, /* pfzchkl fsrc1,fsrc2,fdest */ -{ "fzchks", 0x480001df, 0xb4000420, "e,f,g", 0 }, /* fzchks fsrc1,fsrc2,fdest */ -{ "pfzchks", 0x480005df, 0xb4000020, "e,f,g", 0 }, /* pfzchks fsrc1,fsrc2,fdest */ -{ "faddp", 0x480001d0, 0xb400042f, "e,f,g", 0 }, /* faddp fsrc1,fsrc2,fdest */ -{ "pfaddp", 0x480005d0, 0xb400002f, "e,f,g", 0 }, /* pfaddp fsrc1,fsrc2,fdest */ -{ "faddz", 0x480001d1, 0xb400042e, "e,f,g", 0 }, /* faddz fsrc1,fsrc2,fdest */ -{ "pfaddz", 0x480005d1, 0xb400002e, "e,f,g", 0 }, /* pfaddz fsrc1,fsrc2,fdest */ -{ "form", 0x480001da, 0xb4000425, "e,g", 0 }, /* form fsrc1,fdest */ -{ "pform", 0x480005da, 0xb4000025, "e,g", 0 }, /* pform fsrc1,fdest */ - -/* Floating point pseudo-instructions. */ -{ "fmov.ss", 0x48000049, 0xb7e005b6, "e,g", 0 }, /* fiadd.ss fsrc1,f0,fdest */ -{ "fmov.dd", 0x480001c9, 0xb7e00436, "e,g", 0 }, /* fiadd.dd fsrc1,f0,fdest */ -{ "fmov.sd", 0x480000b3, 0xb400054c, "e,g", 0 }, /* famov.sd fsrc1,fdest */ -{ "fmov.ds", 0x48000133, 0xb40004cc, "e,g", 0 }, /* famov.ds fsrc1,fdest */ -{ "pfmov.ds", 0x48000533, 0xb40000cc, "e,g", 0 }, /* pfamov.ds fsrc1,fdest */ -{ "pfmov.dd", 0x480005c9, 0xb7e00036, "e,g", 0 }, /* pfiadd.dd fsrc1,f0,fdest */ -{ 0, 0, 0, 0, 0 }, - -}; - -#define NUMOPCODES ((sizeof i860_opcodes)/(sizeof i860_opcodes[0])) - - diff --git a/external/gpl3/binutils.old/dist/include/opcode/i960.h b/external/gpl3/binutils.old/dist/include/opcode/i960.h deleted file mode 100644 index be3ac1069f4..00000000000 --- a/external/gpl3/binutils.old/dist/include/opcode/i960.h +++ /dev/null @@ -1,525 +0,0 @@ -/* Basic 80960 instruction formats. - - Copyright (C) 2001-2016 Free Software Foundation, Inc. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3, or (at your option) - any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, - Boston, MA 02110-1301, USA. */ - -/* The 'COJ' instructions are actually COBR instructions with the 'b' in - the mnemonic replaced by a 'j'; they are ALWAYS "de-optimized" if - necessary: if the displacement will not fit in 13 bits, the assembler will - replace them with the corresponding compare and branch instructions. - - All of the 'MEMn' instructions are the same format; the 'n' in the name - indicates the default index scale factor (the size of the datum operated on). - - The FBRA formats are not actually an instruction format. They are the - "convenience directives" for branching on floating-point comparisons, - each of which generates 2 instructions (a 'bno' and one other branch). - - The CALLJ format is not actually an instruction format. It indicates that - the instruction generated (a CTRL-format 'call') should have its relocation - specially flagged for link-time replacement with a 'bal' or 'calls' if - appropriate. */ - -#define CTRL 0 -#define COBR 1 -#define COJ 2 -#define REG 3 -#define MEM1 4 -#define MEM2 5 -#define MEM4 6 -#define MEM8 7 -#define MEM12 8 -#define MEM16 9 -#define FBRA 10 -#define CALLJ 11 - -/* Masks for the mode bits in REG format instructions */ -#define M1 0x0800 -#define M2 0x1000 -#define M3 0x2000 - -/* Generate the 12-bit opcode for a REG format instruction by placing the - * high 8 bits in instruction bits 24-31, the low 4 bits in instruction bits - * 7-10. - */ - -#define REG_OPC(opc) ((opc & 0xff0) << 20) | ((opc & 0xf) << 7) - -/* Generate a template for a REG format instruction: place the opcode bits - * in the appropriate fields and OR in mode bits for the operands that will not - * be used. I.e., - * set m1=1, if src1 will not be used - * set m2=1, if src2 will not be used - * set m3=1, if dst will not be used - * - * Setting the "unused" mode bits to 1 speeds up instruction execution(!). - * The information is also useful to us because some 1-operand REG instructions - * use the src1 field, others the dst field; and some 2-operand REG instructions - * use src1/src2, others src1/dst. The set mode bits enable us to distinguish. - */ -#define R_0(opc) ( REG_OPC(opc) | M1 | M2 | M3 ) /* No operands */ -#define R_1(opc) ( REG_OPC(opc) | M2 | M3 ) /* 1 operand: src1 */ -#define R_1D(opc) ( REG_OPC(opc) | M1 | M2 ) /* 1 operand: dst */ -#define R_2(opc) ( REG_OPC(opc) | M3 ) /* 2 ops: src1/src2 */ -#define R_2D(opc) ( REG_OPC(opc) | M2 ) /* 2 ops: src1/dst */ -#define R_3(opc) ( REG_OPC(opc) ) /* 3 operands */ - -/* DESCRIPTOR BYTES FOR REGISTER OPERANDS - * - * Interpret names as follows: - * R: global or local register only - * RS: global, local, or (if target allows) special-function register only - * RL: global or local register, or integer literal - * RSL: global, local, or (if target allows) special-function register; - * or integer literal - * F: global, local, or floating-point register - * FL: global, local, or floating-point register; or literal (including - * floating point) - * - * A number appended to a name indicates that registers must be aligned, - * as follows: - * 2: register number must be multiple of 2 - * 4: register number must be multiple of 4 - */ - -#define SFR 0x10 /* Mask for the "sfr-OK" bit */ -#define LIT 0x08 /* Mask for the "literal-OK" bit */ -#define FP 0x04 /* Mask for "floating-point-OK" bit */ - -/* This macro ors the bits together. Note that 'align' is a mask - * for the low 0, 1, or 2 bits of the register number, as appropriate. - */ -#define OP(align,lit,fp,sfr) ( align | lit | fp | sfr ) - -#define R OP( 0, 0, 0, 0 ) -#define RS OP( 0, 0, 0, SFR ) -#define RL OP( 0, LIT, 0, 0 ) -#define RSL OP( 0, LIT, 0, SFR ) -#define F OP( 0, 0, FP, 0 ) -#define FL OP( 0, LIT, FP, 0 ) -#define R2 OP( 1, 0, 0, 0 ) -#define RL2 OP( 1, LIT, 0, 0 ) -#define F2 OP( 1, 0, FP, 0 ) -#define FL2 OP( 1, LIT, FP, 0 ) -#define R4 OP( 3, 0, 0, 0 ) -#define RL4 OP( 3, LIT, 0, 0 ) -#define F4 OP( 3, 0, FP, 0 ) -#define FL4 OP( 3, LIT, FP, 0 ) - -#define M 0x7f /* Memory operand (MEMA & MEMB format instructions) */ - -/* Macros to extract info from the register operand descriptor byte 'od'. - */ -#define SFR_OK(od) (od & SFR) /* TRUE if sfr operand allowed */ -#define LIT_OK(od) (od & LIT) /* TRUE if literal operand allowed */ -#define FP_OK(od) (od & FP) /* TRUE if floating-point op allowed */ -#define REG_ALIGN(od,n) ((od & 0x3 & n) == 0) - /* TRUE if reg #n is properly aligned */ -#define MEMOP(od) (od == M) /* TRUE if operand is a memory operand*/ - -/* Description of a single i80960 instruction */ -struct i960_opcode { - long opcode; /* 32 bits, constant fields filled in, rest zeroed */ - const char *name; /* Assembler mnemonic */ - short iclass; /* Class: see #defines below */ - char format; /* REG, COBR, CTRL, MEMn, COJ, FBRA, or CALLJ */ - char num_ops; /* Number of operands */ - char operand[3];/* Operand descriptors; same order as assembler instr */ -}; - -/* Classes of 960 instructions: - * - each instruction falls into one class. - * - each target architecture supports one or more classes. - * - * EACH CONSTANT MUST CONTAIN 1 AND ONLY 1 SET BIT!: see targ_has_iclass(). - */ -#define I_BASE 0x01 /* 80960 base instruction set */ -#define I_CX 0x02 /* 80960Cx instruction */ -#define I_DEC 0x04 /* Decimal instruction */ -#define I_FP 0x08 /* Floating point instruction */ -#define I_KX 0x10 /* 80960Kx instruction */ -#define I_MIL 0x20 /* Military instruction */ -#define I_CASIM 0x40 /* CA simulator instruction */ -#define I_CX2 0x80 /* Cx/Jx/Hx instructions */ -#define I_JX 0x100 /* Jx/Hx instruction */ -#define I_HX 0x200 /* Hx instructions */ - -/****************************************************************************** - * - * TABLE OF i960 INSTRUCTION DESCRIPTIONS - * - ******************************************************************************/ - -const struct i960_opcode i960_opcodes[] = { - - /* if a CTRL instruction has an operand, it's always a displacement */ - - /* callj default=='call' */ - { 0x09000000, "callj", I_BASE, CALLJ, 1, { 0, 0, 0 } }, - { 0x08000000, "b", I_BASE, CTRL, 1, { 0, 0, 0 } }, - { 0x09000000, "call", I_BASE, CTRL, 1, { 0, 0, 0 } }, - { 0x0a000000, "ret", I_BASE, CTRL, 0, { 0, 0, 0 } }, - { 0x0b000000, "bal", I_BASE, CTRL, 1, { 0, 0, 0 } }, - { 0x10000000, "bno", I_BASE, CTRL, 1, { 0, 0, 0 } }, - /* bf same as bno */ - { 0x10000000, "bf", I_BASE, CTRL, 1, { 0, 0, 0 } }, - /* bru same as bno */ - { 0x10000000, "bru", I_BASE, CTRL, 1, { 0, 0, 0 } }, - { 0x11000000, "bg", I_BASE, CTRL, 1, { 0, 0, 0 } }, - /* brg same as bg */ - { 0x11000000, "brg", I_BASE, CTRL, 1, { 0, 0, 0 } }, - { 0x12000000, "be", I_BASE, CTRL, 1, { 0, 0, 0 } }, - /* bre same as be */ - { 0x12000000, "bre", I_BASE, CTRL, 1, { 0, 0, 0 } }, - { 0x13000000, "bge", I_BASE, CTRL, 1, { 0, 0, 0 } }, - /* brge same as bge */ - { 0x13000000, "brge", I_BASE, CTRL, 1, { 0, 0, 0 } }, - { 0x14000000, "bl", I_BASE, CTRL, 1, { 0, 0, 0 } }, - /* brl same as bl */ - { 0x14000000, "brl", I_BASE, CTRL, 1, { 0, 0, 0 } }, - { 0x15000000, "bne", I_BASE, CTRL, 1, { 0, 0, 0 } }, - /* brlg same as bne */ - { 0x15000000, "brlg", I_BASE, CTRL, 1, { 0, 0, 0 } }, - { 0x16000000, "ble", I_BASE, CTRL, 1, { 0, 0, 0 } }, - /* brle same as ble */ - { 0x16000000, "brle", I_BASE, CTRL, 1, { 0, 0, 0 } }, - { 0x17000000, "bo", I_BASE, CTRL, 1, { 0, 0, 0 } }, - /* bt same as bo */ - { 0x17000000, "bt", I_BASE, CTRL, 1, { 0, 0, 0 } }, - /* bro same as bo */ - { 0x17000000, "bro", I_BASE, CTRL, 1, { 0, 0, 0 } }, - { 0x18000000, "faultno", I_BASE, CTRL, 0, { 0, 0, 0 } }, - /* faultf same as faultno */ - { 0x18000000, "faultf", I_BASE, CTRL, 0, { 0, 0, 0 } }, - { 0x19000000, "faultg", I_BASE, CTRL, 0, { 0, 0, 0 } }, - { 0x1a000000, "faulte", I_BASE, CTRL, 0, { 0, 0, 0 } }, - { 0x1b000000, "faultge", I_BASE, CTRL, 0, { 0, 0, 0 } }, - { 0x1c000000, "faultl", I_BASE, CTRL, 0, { 0, 0, 0 } }, - { 0x1d000000, "faultne", I_BASE, CTRL, 0, { 0, 0, 0 } }, - { 0x1e000000, "faultle", I_BASE, CTRL, 0, { 0, 0, 0 } }, - { 0x1f000000, "faulto", I_BASE, CTRL, 0, { 0, 0, 0 } }, - /* faultt syn for faulto */ - { 0x1f000000, "faultt", I_BASE, CTRL, 0, { 0, 0, 0 } }, - - { 0x01000000, "syscall", I_CASIM,CTRL, 0, { 0, 0, 0 } }, - - /* If a COBR (or COJ) has 3 operands, the last one is always a - * displacement and does not appear explicitly in the table. - */ - - { 0x20000000, "testno", I_BASE, COBR, 1, { R, 0, 0 } }, - { 0x21000000, "testg", I_BASE, COBR, 1, { R, 0, 0 } }, - { 0x22000000, "teste", I_BASE, COBR, 1, { R, 0, 0 } }, - { 0x23000000, "testge", I_BASE, COBR, 1, { R, 0, 0 } }, - { 0x24000000, "testl", I_BASE, COBR, 1, { R, 0, 0 } }, - { 0x25000000, "testne", I_BASE, COBR, 1, { R, 0, 0 } }, - { 0x26000000, "testle", I_BASE, COBR, 1, { R, 0, 0 } }, - { 0x27000000, "testo", I_BASE, COBR, 1, { R, 0, 0 } }, - { 0x30000000, "bbc", I_BASE, COBR, 3, { RL, RS, 0 } }, - { 0x31000000, "cmpobg", I_BASE, COBR, 3, { RL, RS, 0 } }, - { 0x32000000, "cmpobe", I_BASE, COBR, 3, { RL, RS, 0 } }, - { 0x33000000, "cmpobge", I_BASE, COBR, 3, { RL, RS, 0 } }, - { 0x34000000, "cmpobl", I_BASE, COBR, 3, { RL, RS, 0 } }, - { 0x35000000, "cmpobne", I_BASE, COBR, 3, { RL, RS, 0 } }, - { 0x36000000, "cmpoble", I_BASE, COBR, 3, { RL, RS, 0 } }, - { 0x37000000, "bbs", I_BASE, COBR, 3, { RL, RS, 0 } }, - { 0x38000000, "cmpibno", I_BASE, COBR, 3, { RL, RS, 0 } }, - { 0x39000000, "cmpibg", I_BASE, COBR, 3, { RL, RS, 0 } }, - { 0x3a000000, "cmpibe", I_BASE, COBR, 3, { RL, RS, 0 } }, - { 0x3b000000, "cmpibge", I_BASE, COBR, 3, { RL, RS, 0 } }, - { 0x3c000000, "cmpibl", I_BASE, COBR, 3, { RL, RS, 0 } }, - { 0x3d000000, "cmpibne", I_BASE, COBR, 3, { RL, RS, 0 } }, - { 0x3e000000, "cmpible", I_BASE, COBR, 3, { RL, RS, 0 } }, - { 0x3f000000, "cmpibo", I_BASE, COBR, 3, { RL, RS, 0 } }, - { 0x31000000, "cmpojg", I_BASE, COJ, 3, { RL, RS, 0 } }, - { 0x32000000, "cmpoje", I_BASE, COJ, 3, { RL, RS, 0 } }, - { 0x33000000, "cmpojge", I_BASE, COJ, 3, { RL, RS, 0 } }, - { 0x34000000, "cmpojl", I_BASE, COJ, 3, { RL, RS, 0 } }, - { 0x35000000, "cmpojne", I_BASE, COJ, 3, { RL, RS, 0 } }, - { 0x36000000, "cmpojle", I_BASE, COJ, 3, { RL, RS, 0 } }, - { 0x38000000, "cmpijno", I_BASE, COJ, 3, { RL, RS, 0 } }, - { 0x39000000, "cmpijg", I_BASE, COJ, 3, { RL, RS, 0 } }, - { 0x3a000000, "cmpije", I_BASE, COJ, 3, { RL, RS, 0 } }, - { 0x3b000000, "cmpijge", I_BASE, COJ, 3, { RL, RS, 0 } }, - { 0x3c000000, "cmpijl", I_BASE, COJ, 3, { RL, RS, 0 } }, - { 0x3d000000, "cmpijne", I_BASE, COJ, 3, { RL, RS, 0 } }, - { 0x3e000000, "cmpijle", I_BASE, COJ, 3, { RL, RS, 0 } }, - { 0x3f000000, "cmpijo", I_BASE, COJ, 3, { RL, RS, 0 } }, - - { 0x80000000, "ldob", I_BASE, MEM1, 2, { M, R, 0 } }, - { 0x82000000, "stob", I_BASE, MEM1, 2, { R, M, 0 } }, - { 0x84000000, "bx", I_BASE, MEM1, 1, { M, 0, 0 } }, - { 0x85000000, "balx", I_BASE, MEM1, 2, { M, R, 0 } }, - { 0x86000000, "callx", I_BASE, MEM1, 1, { M, 0, 0 } }, - { 0x88000000, "ldos", I_BASE, MEM2, 2, { M, R, 0 } }, - { 0x8a000000, "stos", I_BASE, MEM2, 2, { R, M, 0 } }, - { 0x8c000000, "lda", I_BASE, MEM1, 2, { M, R, 0 } }, - { 0x90000000, "ld", I_BASE, MEM4, 2, { M, R, 0 } }, - { 0x92000000, "st", I_BASE, MEM4, 2, { R, M, 0 } }, - { 0x98000000, "ldl", I_BASE, MEM8, 2, { M, R2, 0 } }, - { 0x9a000000, "stl", I_BASE, MEM8, 2, { R2, M, 0 } }, - { 0xa0000000, "ldt", I_BASE, MEM12, 2, { M, R4, 0 } }, - { 0xa2000000, "stt", I_BASE, MEM12, 2, { R4, M, 0 } }, - { 0xb0000000, "ldq", I_BASE, MEM16, 2, { M, R4, 0 } }, - { 0xb2000000, "stq", I_BASE, MEM16, 2, { R4, M, 0 } }, - { 0xc0000000, "ldib", I_BASE, MEM1, 2, { M, R, 0 } }, - { 0xc2000000, "stib", I_BASE, MEM1, 2, { R, M, 0 } }, - { 0xc8000000, "ldis", I_BASE, MEM2, 2, { M, R, 0 } }, - { 0xca000000, "stis", I_BASE, MEM2, 2, { R, M, 0 } }, - - { R_3(0x580), "notbit", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x581), "and", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x582), "andnot", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x583), "setbit", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x584), "notand", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x586), "xor", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x587), "or", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x588), "nor", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x589), "xnor", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_2D(0x58a), "not", I_BASE, REG, 2, { RSL,RS, 0 } }, - { R_3(0x58b), "ornot", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x58c), "clrbit", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x58d), "notor", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x58e), "nand", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x58f), "alterbit", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x590), "addo", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x591), "addi", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x592), "subo", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x593), "subi", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x598), "shro", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x59a), "shrdi", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x59b), "shri", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x59c), "shlo", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x59d), "rotate", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x59e), "shli", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_2(0x5a0), "cmpo", I_BASE, REG, 2, { RSL,RSL, 0 } }, - { R_2(0x5a1), "cmpi", I_BASE, REG, 2, { RSL,RSL, 0 } }, - { R_2(0x5a2), "concmpo", I_BASE, REG, 2, { RSL,RSL, 0 } }, - { R_2(0x5a3), "concmpi", I_BASE, REG, 2, { RSL,RSL, 0 } }, - { R_3(0x5a4), "cmpinco", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x5a5), "cmpinci", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x5a6), "cmpdeco", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x5a7), "cmpdeci", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_2(0x5ac), "scanbyte", I_BASE, REG, 2, { RSL,RSL, 0 } }, - { R_2(0x5ae), "chkbit", I_BASE, REG, 2, { RSL,RSL, 0 } }, - { R_3(0x5b0), "addc", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x5b2), "subc", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_2D(0x5cc), "mov", I_BASE, REG, 2, { RSL,RS, 0 } }, - { R_2D(0x5dc), "movl", I_BASE, REG, 2, { RL2,R2, 0 } }, - { R_2D(0x5ec), "movt", I_BASE, REG, 2, { RL4,R4, 0 } }, - { R_2D(0x5fc), "movq", I_BASE, REG, 2, { RL4,R4, 0 } }, - { R_3(0x610), "atmod", I_BASE, REG, 3, { RS, RSL,R } }, - { R_3(0x612), "atadd", I_BASE, REG, 3, { RS, RSL,RS } }, - { R_2D(0x640), "spanbit", I_BASE, REG, 2, { RSL,RS, 0 } }, - { R_2D(0x641), "scanbit", I_BASE, REG, 2, { RSL,RS, 0 } }, - { R_3(0x645), "modac", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x650), "modify", I_BASE, REG, 3, { RSL,RSL,R } }, - { R_3(0x651), "extract", I_BASE, REG, 3, { RSL,RSL,R } }, - { R_3(0x654), "modtc", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x655), "modpc", I_BASE, REG, 3, { RSL,RSL,R } }, - { R_1(0x660), "calls", I_BASE, REG, 1, { RSL, 0, 0 } }, - { R_0(0x66b), "mark", I_BASE, REG, 0, { 0, 0, 0 } }, - { R_0(0x66c), "fmark", I_BASE, REG, 0, { 0, 0, 0 } }, - { R_0(0x66d), "flushreg", I_BASE, REG, 0, { 0, 0, 0 } }, - { R_0(0x66f), "syncf", I_BASE, REG, 0, { 0, 0, 0 } }, - { R_3(0x670), "emul", I_BASE, REG, 3, { RSL,RSL,R2 } }, - { R_3(0x671), "ediv", I_BASE, REG, 3, { RSL,RL2,RS } }, - { R_2D(0x672), "cvtadr", I_CASIM,REG, 2, { RL, R2, 0 } }, - { R_3(0x701), "mulo", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x708), "remo", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x70b), "divo", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x741), "muli", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x748), "remi", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x749), "modi", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x74b), "divi", I_BASE, REG, 3, { RSL,RSL,RS } }, - - /* Floating-point instructions */ - - { R_2D(0x674), "cvtir", I_FP, REG, 2, { RL, F, 0 } }, - { R_2D(0x675), "cvtilr", I_FP, REG, 2, { RL, F, 0 } }, - { R_3(0x676), "scalerl", I_FP, REG, 3, { RL, FL2,F2 } }, - { R_3(0x677), "scaler", I_FP, REG, 3, { RL, FL, F } }, - { R_3(0x680), "atanr", I_FP, REG, 3, { FL, FL, F } }, - { R_3(0x681), "logepr", I_FP, REG, 3, { FL, FL, F } }, - { R_3(0x682), "logr", I_FP, REG, 3, { FL, FL, F } }, - { R_3(0x683), "remr", I_FP, REG, 3, { FL, FL, F } }, - { R_2(0x684), "cmpor", I_FP, REG, 2, { FL, FL, 0 } }, - { R_2(0x685), "cmpr", I_FP, REG, 2, { FL, FL, 0 } }, - { R_2D(0x688), "sqrtr", I_FP, REG, 2, { FL, F, 0 } }, - { R_2D(0x689), "expr", I_FP, REG, 2, { FL, F, 0 } }, - { R_2D(0x68a), "logbnr", I_FP, REG, 2, { FL, F, 0 } }, - { R_2D(0x68b), "roundr", I_FP, REG, 2, { FL, F, 0 } }, - { R_2D(0x68c), "sinr", I_FP, REG, 2, { FL, F, 0 } }, - { R_2D(0x68d), "cosr", I_FP, REG, 2, { FL, F, 0 } }, - { R_2D(0x68e), "tanr", I_FP, REG, 2, { FL, F, 0 } }, - { R_1(0x68f), "classr", I_FP, REG, 1, { FL, 0, 0 } }, - { R_3(0x690), "atanrl", I_FP, REG, 3, { FL2,FL2,F2 } }, - { R_3(0x691), "logeprl", I_FP, REG, 3, { FL2,FL2,F2 } }, - { R_3(0x692), "logrl", I_FP, REG, 3, { FL2,FL2,F2 } }, - { R_3(0x693), "remrl", I_FP, REG, 3, { FL2,FL2,F2 } }, - { R_2(0x694), "cmporl", I_FP, REG, 2, { FL2,FL2, 0 } }, - { R_2(0x695), "cmprl", I_FP, REG, 2, { FL2,FL2, 0 } }, - { R_2D(0x698), "sqrtrl", I_FP, REG, 2, { FL2,F2, 0 } }, - { R_2D(0x699), "exprl", I_FP, REG, 2, { FL2,F2, 0 } }, - { R_2D(0x69a), "logbnrl", I_FP, REG, 2, { FL2,F2, 0 } }, - { R_2D(0x69b), "roundrl", I_FP, REG, 2, { FL2,F2, 0 } }, - { R_2D(0x69c), "sinrl", I_FP, REG, 2, { FL2,F2, 0 } }, - { R_2D(0x69d), "cosrl", I_FP, REG, 2, { FL2,F2, 0 } }, - { R_2D(0x69e), "tanrl", I_FP, REG, 2, { FL2,F2, 0 } }, - { R_1(0x69f), "classrl", I_FP, REG, 1, { FL2, 0, 0 } }, - { R_2D(0x6c0), "cvtri", I_FP, REG, 2, { FL, R, 0 } }, - { R_2D(0x6c1), "cvtril", I_FP, REG, 2, { FL, R2, 0 } }, - { R_2D(0x6c2), "cvtzri", I_FP, REG, 2, { FL, R, 0 } }, - { R_2D(0x6c3), "cvtzril", I_FP, REG, 2, { FL, R2, 0 } }, - { R_2D(0x6c9), "movr", I_FP, REG, 2, { FL, F, 0 } }, - { R_2D(0x6d9), "movrl", I_FP, REG, 2, { FL2,F2, 0 } }, - { R_2D(0x6e1), "movre", I_FP, REG, 2, { FL4,F4, 0 } }, - { R_3(0x6e2), "cpysre", I_FP, REG, 3, { FL4,FL4,F4 } }, - { R_3(0x6e3), "cpyrsre", I_FP, REG, 3, { FL4,FL4,F4 } }, - { R_3(0x78b), "divr", I_FP, REG, 3, { FL, FL, F } }, - { R_3(0x78c), "mulr", I_FP, REG, 3, { FL, FL, F } }, - { R_3(0x78d), "subr", I_FP, REG, 3, { FL, FL, F } }, - { R_3(0x78f), "addr", I_FP, REG, 3, { FL, FL, F } }, - { R_3(0x79b), "divrl", I_FP, REG, 3, { FL2,FL2,F2 } }, - { R_3(0x79c), "mulrl", I_FP, REG, 3, { FL2,FL2,F2 } }, - { R_3(0x79d), "subrl", I_FP, REG, 3, { FL2,FL2,F2 } }, - { R_3(0x79f), "addrl", I_FP, REG, 3, { FL2,FL2,F2 } }, - - /* These are the floating point branch instructions. Each actually - * generates 2 branch instructions: the first a CTRL instruction with - * the indicated opcode, and the second a 'bno'. - */ - - { 0x12000000, "brue", I_FP, FBRA, 1, { 0, 0, 0 } }, - { 0x11000000, "brug", I_FP, FBRA, 1, { 0, 0, 0 } }, - { 0x13000000, "bruge", I_FP, FBRA, 1, { 0, 0, 0 } }, - { 0x14000000, "brul", I_FP, FBRA, 1, { 0, 0, 0 } }, - { 0x16000000, "brule", I_FP, FBRA, 1, { 0, 0, 0 } }, - { 0x15000000, "brulg", I_FP, FBRA, 1, { 0, 0, 0 } }, - - - /* Decimal instructions */ - - { R_3(0x642), "daddc", I_DEC, REG, 3, { RSL,RSL,RS } }, - { R_3(0x643), "dsubc", I_DEC, REG, 3, { RSL,RSL,RS } }, - { R_2D(0x644), "dmovt", I_DEC, REG, 2, { RSL,RS, 0 } }, - - - /* KX extensions */ - - { R_2(0x600), "synmov", I_KX, REG, 2, { R, R, 0 } }, - { R_2(0x601), "synmovl", I_KX, REG, 2, { R, R, 0 } }, - { R_2(0x602), "synmovq", I_KX, REG, 2, { R, R, 0 } }, - { R_2D(0x615), "synld", I_KX, REG, 2, { R, R, 0 } }, - - - /* MC extensions */ - - { R_3(0x603), "cmpstr", I_MIL, REG, 3, { R, R, RL } }, - { R_3(0x604), "movqstr", I_MIL, REG, 3, { R, R, RL } }, - { R_3(0x605), "movstr", I_MIL, REG, 3, { R, R, RL } }, - { R_2D(0x613), "inspacc", I_MIL, REG, 2, { R, R, 0 } }, - { R_2D(0x614), "ldphy", I_MIL, REG, 2, { R, R, 0 } }, - { R_3(0x617), "fill", I_MIL, REG, 3, { R, RL, RL } }, - { R_2D(0x646), "condrec", I_MIL, REG, 2, { R, R, 0 } }, - { R_2D(0x656), "receive", I_MIL, REG, 2, { R, R, 0 } }, - { R_3(0x662), "send", I_MIL, REG, 3, { R, RL, R } }, - { R_1(0x663), "sendserv", I_MIL, REG, 1, { R, 0, 0 } }, - { R_1(0x664), "resumprcs", I_MIL, REG, 1, { R, 0, 0 } }, - { R_1(0x665), "schedprcs", I_MIL, REG, 1, { R, 0, 0 } }, - { R_0(0x666), "saveprcs", I_MIL, REG, 0, { 0, 0, 0 } }, - { R_1(0x668), "condwait", I_MIL, REG, 1, { R, 0, 0 } }, - { R_1(0x669), "wait", I_MIL, REG, 1, { R, 0, 0 } }, - { R_1(0x66a), "signal", I_MIL, REG, 1, { R, 0, 0 } }, - { R_1D(0x673), "ldtime", I_MIL, REG, 1, { R2, 0, 0 } }, - - - /* CX extensions */ - - { R_3(0x5d8), "eshro", I_CX2, REG, 3, { RSL,RSL,RS } }, - { R_3(0x630), "sdma", I_CX, REG, 3, { RSL,RSL,RL } }, - { R_3(0x631), "udma", I_CX, REG, 0, { 0, 0, 0 } }, - { R_3(0x659), "sysctl", I_CX2, REG, 3, { RSL,RSL,RL } }, - - - /* Jx extensions. */ - { R_3(0x780), "addono", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x790), "addog", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7a0), "addoe", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7b0), "addoge", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7c0), "addol", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7d0), "addone", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7e0), "addole", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7f0), "addoo", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x781), "addino", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x791), "addig", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7a1), "addie", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7b1), "addige", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7c1), "addil", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7d1), "addine", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7e1), "addile", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7f1), "addio", I_JX, REG, 3, { RSL,RSL,RS } }, - - { R_2D(0x5ad), "bswap", I_JX, REG, 2, { RSL, RS, 0 } }, - - { R_2(0x594), "cmpob", I_JX, REG, 2, { RSL,RSL, 0 } }, - { R_2(0x595), "cmpib", I_JX, REG, 2, { RSL,RSL, 0 } }, - { R_2(0x596), "cmpos", I_JX, REG, 2, { RSL,RSL, 0 } }, - { R_2(0x597), "cmpis", I_JX, REG, 2, { RSL,RSL, 0 } }, - - { R_3(0x784), "selno", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x794), "selg", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7a4), "sele", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7b4), "selge", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7c4), "sell", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7d4), "selne", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7e4), "selle", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7f4), "selo", I_JX, REG, 3, { RSL,RSL,RS } }, - - { R_3(0x782), "subono", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x792), "subog", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7a2), "suboe", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7b2), "suboge", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7c2), "subol", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7d2), "subone", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7e2), "subole", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7f2), "suboo", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x783), "subino", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x793), "subig", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7a3), "subie", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7b3), "subige", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7c3), "subil", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7d3), "subine", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7e3), "subile", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7f3), "subio", I_JX, REG, 3, { RSL,RSL,RS } }, - - { R_3(0x65c), "dcctl", I_JX, REG, 3, { RSL,RSL,RL } }, - { R_3(0x65b), "icctl", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_2D(0x658), "intctl", I_JX, REG, 2, { RSL, RS, 0 } }, - { R_0(0x5b4), "intdis", I_JX, REG, 0, { 0, 0, 0 } }, - { R_0(0x5b5), "inten", I_JX, REG, 0, { 0, 0, 0 } }, - { R_0(0x65d), "halt", I_JX, REG, 1, { RSL, 0, 0 } }, - - /* Hx extensions. */ - { 0xac000000, "dcinva", I_HX, MEM1, 1, { M, 0, 0 } }, - - /* END OF TABLE */ - - { 0, NULL, 0, 0, 0, { 0, 0, 0 } } -}; - - /* end of i960-opcode.h */ diff --git a/external/gpl3/binutils.old/dist/include/opcode/ia64.h b/external/gpl3/binutils.old/dist/include/opcode/ia64.h index 2463f5a1895..5078fa9c075 100644 --- a/external/gpl3/binutils.old/dist/include/opcode/ia64.h +++ b/external/gpl3/binutils.old/dist/include/opcode/ia64.h @@ -1,5 +1,5 @@ /* ia64.h -- Header file for ia64 opcode table - Copyright (C) 1998-2016 Free Software Foundation, Inc. + Copyright (C) 1998-2018 Free Software Foundation, Inc. Contributed by David Mosberger-Tang <davidm@hpl.hp.com> This file is part of BFD, the Binary File Descriptor library. diff --git a/external/gpl3/binutils.old/dist/include/opcode/m68hc11.h b/external/gpl3/binutils.old/dist/include/opcode/m68hc11.h index 5ac1c872b17..7d6a25ea01a 100644 --- a/external/gpl3/binutils.old/dist/include/opcode/m68hc11.h +++ b/external/gpl3/binutils.old/dist/include/opcode/m68hc11.h @@ -1,5 +1,5 @@ /* m68hc11.h -- Header file for Motorola 68HC11 & 68HC12 opcode table - Copyright (C) 1999-2016 Free Software Foundation, Inc. + Copyright (C) 1999-2018 Free Software Foundation, Inc. Written by Stephane Carrez (stcarrez@nerim.fr) This file is part of GDB, GAS, and the GNU binutils. diff --git a/external/gpl3/binutils.old/dist/include/opcode/m68k.h b/external/gpl3/binutils.old/dist/include/opcode/m68k.h index df37a562fef..39b43738f18 100644 --- a/external/gpl3/binutils.old/dist/include/opcode/m68k.h +++ b/external/gpl3/binutils.old/dist/include/opcode/m68k.h @@ -1,5 +1,5 @@ /* Opcode table header for m680[01234]0/m6888[12]/m68851. - Copyright (C) 1989-2016 Free Software Foundation, Inc. + Copyright (C) 1989-2018 Free Software Foundation, Inc. This file is part of GDB, GAS, and the GNU binutils. diff --git a/external/gpl3/binutils.old/dist/include/opcode/m88k.h b/external/gpl3/binutils.old/dist/include/opcode/m88k.h deleted file mode 100644 index 20c92a4f16f..00000000000 --- a/external/gpl3/binutils.old/dist/include/opcode/m88k.h +++ /dev/null @@ -1,454 +0,0 @@ -/* Table of opcodes for the Motorola M88k family. - Copyright (C) 1989-2016 Free Software Foundation, Inc. - - This file is part of GDB and GAS. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, - MA 02110-1301, USA. */ - -/* - * Disassembler Instruction Table - * - * The first field of the table is the opcode field. If an opcode - * is specified which has any non-opcode bits on, a system error - * will occur when the system attempts the install it into the - * instruction table. The second parameter is a pointer to the - * instruction mnemonic. Each operand is specified by offset, width, - * and type. The offset is the bit number of the least significant - * bit of the operand with bit 0 being the least significant bit of - * the instruction. The width is the number of bits used to specify - * the operand. The type specifies the output format to be used for - * the operand. The valid formats are: register, register indirect, - * hex constant, and bit field specification. The last field is a - * pointer to the next instruction in the linked list. These pointers - * are initialized by init_disasm(). - * - * Revision History - * - * Revision 1.0 11/08/85 Creation date - * 1.1 02/05/86 Updated instruction mnemonic table MD - * 1.2 06/16/86 Updated SIM_FLAGS for floating point - * 1.3 09/20/86 Updated for new encoding - * 05/11/89 R. Trawick adapted from Motorola disassembler - */ - -#include <stdio.h> - -/* Define the number of bits in the primary opcode field of the instruction, - the destination field, the source 1 and source 2 fields. */ - -/* Size of opcode field. */ -#define OP 8 - -/* Size of destination. */ -#define DEST 6 - -/* Size of source1. */ -#define SOURCE1 6 - -/* Size of source2. */ -#define SOURCE2 6 - -/* Number of registers. */ -#define REGs 32 - -/* Type definitions. */ - -typedef unsigned int UINT; -#define WORD long -#define FLAG unsigned -#define STATE short - -/* The next four equates define the priorities that the various classes - * of instructions have regarding writing results back into registers and - * signalling exceptions. */ - -/* PMEM is also defined in <sys/param.h> on Delta 88's. Sigh! */ -#undef PMEM - -/* Integer priority. */ -#define PINT 0 - -/* Floating point priority. */ -#define PFLT 1 - -/* Memory priority. */ -#define PMEM 2 - -/* Not applicable, instruction doesn't write to regs. */ -#define NA 3 - -/* Highest of these priorities. */ -#define HIPRI 3 - -/* The instruction registers are an artificial mechanism to speed up - * simulator execution. In the real processor, an instruction register - * is 32 bits wide. In the simulator, the 32 bit instruction is kept in - * a structure field called rawop, and the instruction is partially decoded, - * and split into various fields and flags which make up the other fields - * of the structure. - * The partial decode is done when the instructions are initially loaded - * into simulator memory. The simulator code memory is not an array of - * 32 bit words, but is an array of instruction register structures. - * Yes this wastes memory, but it executes much quicker. - */ - -struct IR_FIELDS -{ - unsigned op:OP, - dest: DEST, - src1: SOURCE1, - src2: SOURCE2; - int ltncy, - extime, - /* Writeback priority. */ - wb_pri; - /* Immediate size. */ - unsigned imm_flags:2, - /* Register source 1 used. */ - rs1_used:1, - /* Register source 2 used. */ - rs2_used:1, - /* Register source/dest. used. */ - rsd_used:1, - /* Complement. */ - c_flag:1, - /* Upper half word. */ - u_flag:1, - /* Execute next. */ - n_flag:1, - /* Uses writeback slot. */ - wb_flag:1, - /* Dest size. */ - dest_64:1, - /* Source 1 size. */ - s1_64:1, - /* Source 2 size. */ - s2_64:1, - scale_flag:1, - /* Scaled register. */ - brk_flg:1; -}; - -struct mem_segs -{ - /* Pointer (returned by calloc) to segment. */ - struct mem_wrd *seg; - - /* Base load address from file headers. */ - unsigned long baseaddr; - - /* Ending address of segment. */ - unsigned long endaddr; - - /* Segment control flags (none defined). */ - int flags; -}; - -#define MAXSEGS (10) /* max number of segment allowed */ -#define MEMSEGSIZE (sizeof(struct mem_segs))/* size of mem_segs structure */ - -#if 0 -#define BRK_RD (0x01) /* break on memory read */ -#define BRK_WR (0x02) /* break on memory write */ -#define BRK_EXEC (0x04) /* break on execution */ -#define BRK_CNT (0x08) /* break on terminal count */ -#endif - -struct mem_wrd -{ - /* Simulator instruction break down. */ - struct IR_FIELDS opcode; - union { - /* Memory element break down. */ - unsigned long l; - unsigned short s[2]; - unsigned char c[4]; - } mem; -}; - -/* Size of each 32 bit memory model. */ -#define MEMWRDSIZE (sizeof (struct mem_wrd)) - -extern struct mem_segs memory[]; -extern struct PROCESSOR m78000; - -struct PROCESSOR -{ - unsigned WORD - /* Execute instruction pointer. */ - ip, - /* Vector base register. */ - vbr, - /* Processor status register. */ - psr; - - /* Source 1. */ - WORD S1bus, - /* Source 2. */ - S2bus, - /* Destination. */ - Dbus, - /* Data address bus. */ - DAbus, - ALU, - /* Data registers. */ - Regs[REGs], - /* Max clocks before reg is available. */ - time_left[REGs], - /* Writeback priority of reg. */ - wb_pri[REGs], - /* Integer unit control regs. */ - SFU0_regs[REGs], - /* Floating point control regs. */ - SFU1_regs[REGs], - Scoreboard[REGs], - Vbr; - unsigned WORD scoreboard, - Psw, - Tpsw; - /* Waiting for a jump instruction. */ - FLAG jump_pending:1; -}; - -/* Size of immediate field. */ - -#define i26bit 1 -#define i16bit 2 -#define i10bit 3 - -/* Definitions for fields in psr. */ - -#define psr_mode 31 -#define psr_rbo 30 -#define psr_ser 29 -#define psr_carry 28 -#define psr_sf7m 11 -#define psr_sf6m 10 -#define psr_sf5m 9 -#define psr_sf4m 8 -#define psr_sf3m 7 -#define psr_sf2m 6 -#define psr_sf1m 5 -#define psr_mam 4 -#define psr_inm 3 -#define psr_exm 2 -#define psr_trm 1 -#define psr_ovfm 0 - -/* The 1 clock operations. */ - -#define ADDU 1 -#define ADDC 2 -#define ADDUC 3 -#define ADD 4 - -#define SUBU ADD+1 -#define SUBB ADD+2 -#define SUBUB ADD+3 -#define SUB ADD+4 - -#define AND_ ADD+5 -#define OR ADD+6 -#define XOR ADD+7 -#define CMP ADD+8 - -/* Loads. */ - -#define LDAB CMP+1 -#define LDAH CMP+2 -#define LDA CMP+3 -#define LDAD CMP+4 - -#define LDB LDAD+1 -#define LDH LDAD+2 -#define LD LDAD+3 -#define LDD LDAD+4 -#define LDBU LDAD+5 -#define LDHU LDAD+6 - -/* Stores. */ - -#define STB LDHU+1 -#define STH LDHU+2 -#define ST LDHU+3 -#define STD LDHU+4 - -/* Exchange. */ - -#define XMEMBU LDHU+5 -#define XMEM LDHU+6 - -/* Branches. */ - -#define JSR STD+1 -#define BSR STD+2 -#define BR STD+3 -#define JMP STD+4 -#define BB1 STD+5 -#define BB0 STD+6 -#define RTN STD+7 -#define BCND STD+8 - -/* Traps. */ - -#define TB1 BCND+1 -#define TB0 BCND+2 -#define TCND BCND+3 -#define RTE BCND+4 -#define TBND BCND+5 - -/* Misc. */ - -#define MUL TBND + 1 -#define DIV MUL +2 -#define DIVU MUL +3 -#define MASK MUL +4 -#define FF0 MUL +5 -#define FF1 MUL +6 -#define CLR MUL +7 -#define SET MUL +8 -#define EXT MUL +9 -#define EXTU MUL +10 -#define MAK MUL +11 -#define ROT MUL +12 - -/* Control register manipulations. */ - -#define LDCR ROT +1 -#define STCR ROT +2 -#define XCR ROT +3 - -#define FLDCR ROT +4 -#define FSTCR ROT +5 -#define FXCR ROT +6 - -#define NOP XCR +1 - -/* Floating point instructions. */ - -#define FADD NOP +1 -#define FSUB NOP +2 -#define FMUL NOP +3 -#define FDIV NOP +4 -#define FSQRT NOP +5 -#define FCMP NOP +6 -#define FIP NOP +7 -#define FLT NOP +8 -#define INT NOP +9 -#define NINT NOP +10 -#define TRNC NOP +11 -#define FLDC NOP +12 -#define FSTC NOP +13 -#define FXC NOP +14 - -#define UEXT(src,off,wid) \ - ((((unsigned int)(src)) >> (off)) & ((1 << (wid)) - 1)) - -#define SEXT(src,off,wid) \ - (((((int)(src))<<(32 - ((off) + (wid)))) >>(32 - (wid))) ) - -#define MAKE(src,off,wid) \ - ((((unsigned int)(src)) & ((1 << (wid)) - 1)) << (off)) - -#define opword(n) (unsigned long) (memaddr->mem.l) - -/* Constants and masks. */ - -#define SFU0 0x80000000 -#define SFU1 0x84000000 -#define SFU7 0x9c000000 -#define RRI10 0xf0000000 -#define RRR 0xf4000000 -#define SFUMASK 0xfc00ffe0 -#define RRRMASK 0xfc00ffe0 -#define RRI10MASK 0xfc00fc00 -#define DEFMASK 0xfc000000 -#define CTRL 0x0000f000 -#define CTRLMASK 0xfc00f800 - -/* Operands types. */ - -enum operand_type -{ - HEX = 1, - REG = 2, - CONT = 3, - IND = 3, - BF = 4, - /* Scaled register. */ - REGSC = 5, - /* Control register. */ - CRREG = 6, - /* Floating point control register. */ - FCRREG = 7, - PCREL = 8, - CONDMASK = 9, - /* Extended register. */ - XREG = 10, - /* Decimal. */ - DEC = 11 -}; - -/* Hashing specification. */ - -#define HASHVAL 79 - -/* Structure templates. */ - -typedef struct -{ - unsigned int offset; - unsigned int width; - enum operand_type type; -} OPSPEC; - -struct SIM_FLAGS -{ - int ltncy, /* latency (max number of clocks needed to execute). */ - extime, /* execution time (min number of clocks needed to execute). */ - wb_pri; /* writeback slot priority. */ - unsigned op:OP, /* simulator version of opcode. */ - imm_flags:2, /* 10,16 or 26 bit immediate flags. */ - rs1_used:1, /* register source 1 used. */ - rs2_used:1, /* register source 2 used. */ - rsd_used:1, /* register source/dest used. */ - c_flag:1, /* complement. */ - u_flag:1, /* upper half word. */ - n_flag:1, /* execute next. */ - wb_flag:1, /* uses writeback slot. */ - dest_64:1, /* double precision dest. */ - s1_64:1, /* double precision source 1. */ - s2_64:1, /* double precision source 2. */ - scale_flag:1; /* register is scaled. */ -}; - -typedef struct INSTRUCTAB { - unsigned int opcode; - char *mnemonic; - OPSPEC op1,op2,op3; - struct SIM_FLAGS flgs; -} INSTAB; - - -#define NO_OPERAND {0,0,0} - -extern const INSTAB instructions[]; - -/* - * Local Variables: - * fill-column: 131 - * End: - */ diff --git a/external/gpl3/binutils.old/dist/include/opcode/metag.h b/external/gpl3/binutils.old/dist/include/opcode/metag.h index 1ca6d9edcdf..8a44b6128fd 100644 --- a/external/gpl3/binutils.old/dist/include/opcode/metag.h +++ b/external/gpl3/binutils.old/dist/include/opcode/metag.h @@ -1,5 +1,5 @@ /* Imagination Technologies Meta opcode table. - Copyright (C) 2013-2016 Free Software Foundation, Inc. + Copyright (C) 2013-2018 Free Software Foundation, Inc. Contributed by Imagination Technologies Ltd. This file is part of GDB and GAS. diff --git a/external/gpl3/binutils.old/dist/include/opcode/mips.h b/external/gpl3/binutils.old/dist/include/opcode/mips.h index d9fa8317289..ca7fbfa0ef4 100644 --- a/external/gpl3/binutils.old/dist/include/opcode/mips.h +++ b/external/gpl3/binutils.old/dist/include/opcode/mips.h @@ -1,5 +1,5 @@ /* mips.h. Mips opcode list for GDB, the GNU debugger. - Copyright (C) 1993-2016 Free Software Foundation, Inc. + Copyright (C) 1993-2018 Free Software Foundation, Inc. Contributed by Ralph Campbell and OSF Commented and modified by Ian Lance Taylor, Cygnus Support @@ -409,6 +409,9 @@ enum mips_operand_type { /* $pc, which has no encoding in the architectural instruction. */ OP_PC, + /* $28, which has no encoding in the MIPS16e architectural instruction. */ + OP_REG28, + /* A 4-bit XYZW channel mask or 2-bit XYZW index; the size determines which. */ OP_VU0_SUFFIX, @@ -753,6 +756,14 @@ struct mips_opcode unsigned long exclusions; }; +/* Return true if MO is an instruction that requires 32-bit encoding. */ + +static inline bfd_boolean +mips_opcode_32bit_p (const struct mips_opcode *mo) +{ + return mo->mask >> 16 != 0; +} + /* These are the characters which may appear in the args field of an instruction. They appear in the order in which the fields appear when the instruction is used. Commas and parentheses in the args @@ -924,6 +935,9 @@ struct mips_opcode "+z" 5-bit rz register (OP_*_RZ) "+Z" 5-bit fz register (OP_*_FZ) + interAptiv MR2: + "-m" register list for SAVE/RESTORE instruction + Enhanced VA Scheme: "+j" 9-bit signed offset in bit 7 (OP_*_EVAOFFSET) @@ -975,6 +989,9 @@ struct mips_opcode "-A" symbolic offset (-262144 .. 262143) << 2 at bit 0 "-B" symbolic offset (-131072 .. 131071) << 3 at bit 0 + GINV ASE usage: + "+\" 2 bit Global TLB invalidate type at bit 8 + Other: "()" parens surrounding optional value "," separates operands @@ -989,14 +1006,14 @@ struct mips_opcode Extension character sequences used so far ("+" followed by the following), for quick reference when adding more: "1234567890" - "~!@#$%^&*|:'";" + "~!@#$%^&*|:'";\" "ABCEFGHIJKLMNOPQRSTUVWXZ" "abcdefghijklmnopqrstuvwxyz" Extension character sequences used so far ("-" followed by the following), for quick reference when adding more: "AB" - "abdstuvwxy" + "abdmstuvwxy" */ /* These are the bits which may be set in the pinfo field of an @@ -1106,6 +1123,15 @@ struct mips_opcode #define INSN2_VU0_CHANNEL_SUFFIX 0x00004000 /* Instruction has a forbidden slot. */ #define INSN2_FORBIDDEN_SLOT 0x00008000 +/* Opcode table entry is for a short MIPS16 form only. An extended + encoding may still exist, but with a separate opcode table entry + required. In disassembly the presence of this flag in an otherwise + successful match against an extended instruction encoding inhibits + matching against any subsequent short table entry even if it does + not have this flag set. A table entry matching the full extended + encoding is needed or otherwise the final EXTEND entry will apply, + for the disassembly of the prefix only. */ +#define INSN2_SHORT_ONLY 0x00010000 /* Masks used to mark instructions to indicate which MIPS ISA level they were introduced in. INSN_ISA_MASK masks an enumeration that @@ -1194,7 +1220,7 @@ static const unsigned int mips_isa_table[] = { #undef ISAF /* Masks used for Chip specific instructions. */ -#define INSN_CHIP_MASK 0xc3ff0f20 +#define INSN_CHIP_MASK 0xc7ff4f60 /* Cavium Networks Octeon instructions. */ #define INSN_OCTEON 0x00000800 @@ -1234,6 +1260,8 @@ static const unsigned int mips_isa_table[] = { #define INSN_LOONGSON_3A 0x00000400 /* RMI Xlr instruction */ #define INSN_XLR 0x00000020 +/* Imagination interAptiv MR2. */ +#define INSN_INTERAPTIV_MR2 0x04000000 /* DSP ASE */ #define ASE_DSP 0x00000001 @@ -1260,7 +1288,20 @@ static const unsigned int mips_isa_table[] = { #define ASE_MSA64 0x00001000 /* eXtended Physical Address (XPA) Extension. */ #define ASE_XPA 0x00002000 +/* DSP R3 Module. */ #define ASE_DSPR3 0x00004000 +/* MIPS16e2 ASE. */ +#define ASE_MIPS16E2 0x00008000 +/* MIPS16e2 MT ASE instructions. */ +#define ASE_MIPS16E2_MT 0x00010000 +/* The Virtualization ASE has eXtended Physical Addressing (XPA) + instructions which are only valid when both ASEs are enabled. */ +#define ASE_XPA_VIRT 0x00020000 +/* Cyclic redundancy check (CRC) ASE. */ +#define ASE_CRC 0x00040000 +#define ASE_CRC64 0x00080000 +/* Global INValidate Extension. */ +#define ASE_GINV 0x00100000 /* MIPS ISA defines, use instead of hardcoding ISA level. */ @@ -1331,6 +1372,7 @@ static const unsigned int mips_isa_table[] = { #define CPU_OCTEON2 6502 #define CPU_OCTEON3 6503 #define CPU_XLR 887682 /* decimal 'XLR' */ +#define CPU_INTERAPTIV_MR2 736550 /* decimal 'IA2' */ /* Return true if the given CPU is included in INSN_* mask MASK. */ @@ -1401,6 +1443,9 @@ cpu_is_member (int cpu, unsigned int mask) case CPU_XLR: return (mask & INSN_XLR) != 0; + case CPU_INTERAPTIV_MR2: + return (mask & INSN_INTERAPTIV_MR2) != 0; + case CPU_MIPS32R6: return (mask & INSN_ISA_MASK) == INSN_ISA32R6; @@ -1794,29 +1839,53 @@ extern int bfd_mips_num_opcodes; "Z" 3 bit register (MIPS16OP_*_MOVE32Z) "v" 3 bit same register as source and destination (MIPS16OP_*_RX) "w" 3 bit same register as source and destination (MIPS16OP_*_RY) - "0" zero register ($0) + "." zero register ($0) "S" stack pointer ($sp or $29) "P" program counter "R" return address register ($ra or $31) "X" 5 bit MIPS register (MIPS16OP_*_REGR32) "Y" 5 bit MIPS register (MIPS16OP_*_REG32R) + "0" 5-bit ASMACRO p0 immediate + "1" 3-bit ASMACRO p1 immediate + "2" 3-bit ASMACRO p2 immediate + "3" 5-bit ASMACRO p3 immediate + "4" 3-bit ASMACRO p4 immediate "6" 6 bit unsigned break code (MIPS16OP_*_IMM6) "a" 26 bit jump address "i" likewise, but flips bit 0 "e" 11 bit extension value "l" register list for entry instruction "L" register list for exit instruction + ">" 5-bit SYNC code + "9" 9-bit signed immediate + "G" global pointer ($gp or $28) + "N" 5-bit coprocessor register + "O" 3-bit sel field for MFC0/MTC0 + "Q" 5-bit hardware register + "T" 5-bit CACHE opcode or PREF hint + "b" 5-bit INS/EXT position, which becomes LSB + Enforces: 0 <= pos < 32. + "c" 5-bit INS size, which becomes MSB + Requires that "b" occurs first to set position. + Enforces: 0 < (pos+size) <= 32. + "d" 5-bit EXT size, which becomes MSBD + Requires that "b" occurs first to set position. + Enforces: 0 < (pos+size) <= 32. + "n" 2-bit immediate (1 .. 4) + "o" 5-bit unsigned immediate * 16 + "r" 3-bit register + "s" 3-bit ASMACRO select immediate + "u" 16-bit unsigned immediate "I" an immediate value used for macros The remaining codes may be extended. Except as otherwise noted, the full extended operand is a 16 bit signed value. "<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned) - ">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned) "[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned) "]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned) - "4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed) "5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5) + "F" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed) "H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5) "W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5) "D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5) @@ -1832,20 +1901,19 @@ extern int bfd_mips_num_opcodes; "A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8) "B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5) "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5) - "m" 7 bit register list for save instruction (18 bit extended) - "M" 7 bit register list for restore instruction (18 bit extended) + "m" 7 bit register list for SAVE/RESTORE instruction (18 bit extended) Characters used so far, for quick reference when adding more: - " 456 8 0" - "[]<>" - "ABCDE HI KLM P RS UVWXYZ" - "a e ijklm pq vwxyz" + "0123456 89" + ".[]<>" + "ABCDEFGHI KL NOPQRSTUVWXYZ" + "abcde ijklmnopqrs uvwxyz" */ /* Save/restore encoding for the args field when all 4 registers are either saved as arguments or saved/restored as statics. */ -#define MIPS16_ALL_ARGS 0xe -#define MIPS16_ALL_STATICS 0xb +#define MIPS_SVRS_ALL_ARGS 0xe +#define MIPS_SVRS_ALL_STATICS 0xb /* The following flags have the same value for the mips16 opcode table: diff --git a/external/gpl3/binutils.old/dist/include/opcode/mmix.h b/external/gpl3/binutils.old/dist/include/opcode/mmix.h index 5ca0d583b2b..7505de2b128 100644 --- a/external/gpl3/binutils.old/dist/include/opcode/mmix.h +++ b/external/gpl3/binutils.old/dist/include/opcode/mmix.h @@ -1,5 +1,5 @@ /* mmix.h -- Header file for MMIX opcode table - Copyright (C) 2001-2016 Free Software Foundation, Inc. + Copyright (C) 2001-2018 Free Software Foundation, Inc. Written by Hans-Peter Nilsson (hp@bitrange.com) This file is part of GDB, GAS, and the GNU binutils. diff --git a/external/gpl3/binutils.old/dist/include/opcode/mn10200.h b/external/gpl3/binutils.old/dist/include/opcode/mn10200.h index 1601dd095ac..35acba34ee4 100644 --- a/external/gpl3/binutils.old/dist/include/opcode/mn10200.h +++ b/external/gpl3/binutils.old/dist/include/opcode/mn10200.h @@ -1,5 +1,5 @@ /* mn10200.h -- Header file for Matsushita 10200 opcode table - Copyright (C) 1996-2016 Free Software Foundation, Inc. + Copyright (C) 1996-2018 Free Software Foundation, Inc. Written by Jeff Law, Cygnus Support This file is part of GDB, GAS, and the GNU binutils. diff --git a/external/gpl3/binutils.old/dist/include/opcode/mn10300.h b/external/gpl3/binutils.old/dist/include/opcode/mn10300.h index 8c9c58db292..0484669563d 100644 --- a/external/gpl3/binutils.old/dist/include/opcode/mn10300.h +++ b/external/gpl3/binutils.old/dist/include/opcode/mn10300.h @@ -1,5 +1,5 @@ /* mn10300.h -- Header file for Matsushita 10300 opcode table - Copyright (C) 1996-2016 Free Software Foundation, Inc. + Copyright (C) 1996-2018 Free Software Foundation, Inc. Written by Jeff Law, Cygnus Support This file is part of GDB, GAS, and the GNU binutils. diff --git a/external/gpl3/binutils.old/dist/include/opcode/moxie.h b/external/gpl3/binutils.old/dist/include/opcode/moxie.h index 900fd25a67b..851f5f5dd7a 100644 --- a/external/gpl3/binutils.old/dist/include/opcode/moxie.h +++ b/external/gpl3/binutils.old/dist/include/opcode/moxie.h @@ -1,5 +1,5 @@ /* Definitions for decoding the moxie opcode table. - Copyright (C) 2009-2016 Free Software Foundation, Inc. + Copyright (C) 2009-2018 Free Software Foundation, Inc. Contributed by Anthony Green (green@moxielogic.com). This program is free software; you can redistribute it and/or modify diff --git a/external/gpl3/binutils.old/dist/include/opcode/msp430-decode.h b/external/gpl3/binutils.old/dist/include/opcode/msp430-decode.h index f9e1b4c40a1..b7175e3aaa4 100644 --- a/external/gpl3/binutils.old/dist/include/opcode/msp430-decode.h +++ b/external/gpl3/binutils.old/dist/include/opcode/msp430-decode.h @@ -1,5 +1,5 @@ /* Opcode decoder for the TI MSP430 - Copyright (C) 2012-2016 Free Software Foundation, Inc. + Copyright (C) 2012-2018 Free Software Foundation, Inc. Written by DJ Delorie <dj@redhat.com> This file is part of GDB, the GNU Debugger. diff --git a/external/gpl3/binutils.old/dist/include/opcode/msp430.h b/external/gpl3/binutils.old/dist/include/opcode/msp430.h index a7762af10b6..15660fe41b3 100644 --- a/external/gpl3/binutils.old/dist/include/opcode/msp430.h +++ b/external/gpl3/binutils.old/dist/include/opcode/msp430.h @@ -1,6 +1,6 @@ /* Opcode table for the TI MSP430 microcontrollers - Copyright (C) 2002-2016 Free Software Foundation, Inc. + Copyright (C) 2002-2018 Free Software Foundation, Inc. Contributed by Dmitry Diky <diwil@mail.ru> This program is free software; you can redistribute it and/or modify diff --git a/external/gpl3/binutils.old/dist/include/opcode/nds32.h b/external/gpl3/binutils.old/dist/include/opcode/nds32.h index 5f29c04ace3..4d113be8b86 100644 --- a/external/gpl3/binutils.old/dist/include/opcode/nds32.h +++ b/external/gpl3/binutils.old/dist/include/opcode/nds32.h @@ -1,5 +1,5 @@ /* nds32.h -- Header file for nds32 opcode table - Copyright (C) 2012-2016 Free Software Foundation, Inc. + Copyright (C) 2012-2018 Free Software Foundation, Inc. Contributed by Andes Technology Corporation. This program is free software; you can redistribute it and/or modify @@ -50,8 +50,8 @@ static const int nds32_r54map[] ATTRIBUTE_UNUSED = -1, -1, -1, -1, -1, -1, -1, -1 }; -#define __BIT(n) (1 << (n)) -#define __MASK(n) (__BIT (n) - 1) +#define N32_BIT(n) (1 << (n)) +#define __MASK(n) (N32_BIT (n) - 1) #define __MF(v, off, bs) (((v) & __MASK (bs)) << (off)) #define __GF(v, off, bs) (((v) >> off) & __MASK (bs)) #define __SEXT(v, bs) ((((v) & ((1 << (bs)) - 1)) ^ (1 << ((bs) - 1))) - (1 << ((bs) - 1))) diff --git a/external/gpl3/binutils.old/dist/include/opcode/nios2.h b/external/gpl3/binutils.old/dist/include/opcode/nios2.h index 50b5c75d6d6..f1ef1caf800 100644 --- a/external/gpl3/binutils.old/dist/include/opcode/nios2.h +++ b/external/gpl3/binutils.old/dist/include/opcode/nios2.h @@ -1,9 +1,9 @@ /* Nios II opcode list for GAS, the GNU assembler. - Copyright (C) 2012-2016 Free Software Foundation, Inc. + Copyright (C) 2012-2018 Free Software Foundation, Inc. Contributed by Nigel Gray (ngray@altera.com). Contributed by Mentor Graphics, Inc. - This file is part of GAS, the GNU Assembler, and GDB, the GNU disassembler. + This file is part of the GNU opcodes library. GAS/GDB is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by diff --git a/external/gpl3/binutils.old/dist/include/opcode/nios2r1.h b/external/gpl3/binutils.old/dist/include/opcode/nios2r1.h index 763b54d2c70..23064b32d4e 100644 --- a/external/gpl3/binutils.old/dist/include/opcode/nios2r1.h +++ b/external/gpl3/binutils.old/dist/include/opcode/nios2r1.h @@ -1,8 +1,8 @@ /* Nios II R1 opcode list for GAS, the GNU assembler. - Copyright (C) 2013-2016 Free Software Foundation, Inc. + Copyright (C) 2013-2018 Free Software Foundation, Inc. Contributed by Mentor Graphics, Inc. - This file is part of GAS, the GNU Assembler, and GDB, the GNU disassembler. + This file is part of the GNU opcodes library. GAS/GDB is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by diff --git a/external/gpl3/binutils.old/dist/include/opcode/nios2r2.h b/external/gpl3/binutils.old/dist/include/opcode/nios2r2.h index 22f44e78fd2..6f7542c8208 100644 --- a/external/gpl3/binutils.old/dist/include/opcode/nios2r2.h +++ b/external/gpl3/binutils.old/dist/include/opcode/nios2r2.h @@ -1,8 +1,8 @@ /* Nios II R2 opcode list for GAS, the GNU assembler. - Copyright (C) 2013-2016 Free Software Foundation, Inc. + Copyright (C) 2013-2018 Free Software Foundation, Inc. Contributed by Mentor Graphics, Inc. - This file is part of GAS, the GNU Assembler, and GDB, the GNU disassembler. + This file is part of the GNU opcodes library. GAS/GDB is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by diff --git a/external/gpl3/binutils.old/dist/include/opcode/np1.h b/external/gpl3/binutils.old/dist/include/opcode/np1.h index 744bd2dcc8e..8c9dafe05e9 100644 --- a/external/gpl3/binutils.old/dist/include/opcode/np1.h +++ b/external/gpl3/binutils.old/dist/include/opcode/np1.h @@ -1,5 +1,5 @@ /* Print GOULD NPL instructions for GDB, the GNU debugger. - Copyright (C) 1986-2016 Free Software Foundation, Inc. + Copyright (C) 1986-2018 Free Software Foundation, Inc. This file is part of GDB. diff --git a/external/gpl3/binutils.old/dist/include/opcode/ns32k.h b/external/gpl3/binutils.old/dist/include/opcode/ns32k.h index ef70d6acc4d..4202a8c6eed 100644 --- a/external/gpl3/binutils.old/dist/include/opcode/ns32k.h +++ b/external/gpl3/binutils.old/dist/include/opcode/ns32k.h @@ -1,5 +1,5 @@ /* ns32k-opcode.h -- Opcode table for National Semi 32k processor - Copyright (C) 1987-2016 Free Software Foundation, Inc. + Copyright (C) 1987-2018 Free Software Foundation, Inc. This file is part of GAS, the GNU Assembler. diff --git a/external/gpl3/binutils.old/dist/include/opcode/pdp11.h b/external/gpl3/binutils.old/dist/include/opcode/pdp11.h index 2b9d89ee62f..582c862bf1d 100644 --- a/external/gpl3/binutils.old/dist/include/opcode/pdp11.h +++ b/external/gpl3/binutils.old/dist/include/opcode/pdp11.h @@ -1,5 +1,5 @@ /* PDP-11 opcde list. - Copyright (C) 2001-2016 Free Software Foundation, Inc. + Copyright (C) 2001-2018 Free Software Foundation, Inc. This file is part of GDB and GAS. diff --git a/external/gpl3/binutils.old/dist/include/opcode/pj.h b/external/gpl3/binutils.old/dist/include/opcode/pj.h index 3953966ea57..d9132564e77 100644 --- a/external/gpl3/binutils.old/dist/include/opcode/pj.h +++ b/external/gpl3/binutils.old/dist/include/opcode/pj.h @@ -1,5 +1,5 @@ /* Definitions for decoding the picoJava opcode table. - Copyright (C) 1999-2016 Free Software Foundation, Inc. + Copyright (C) 1999-2018 Free Software Foundation, Inc. Contributed by Steve Chamberlain of Transmeta (sac@pobox.com). This program is free software; you can redistribute it and/or modify diff --git a/external/gpl3/binutils.old/dist/include/opcode/pn.h b/external/gpl3/binutils.old/dist/include/opcode/pn.h index 700fbb82322..d1089c534b7 100644 --- a/external/gpl3/binutils.old/dist/include/opcode/pn.h +++ b/external/gpl3/binutils.old/dist/include/opcode/pn.h @@ -1,5 +1,5 @@ /* Print GOULD PN (PowerNode) instructions for GDB, the GNU debugger. - Copyright (C) 1986-2016 Free Software Foundation, Inc. + Copyright (C) 1986-2018 Free Software Foundation, Inc. This file is part of GDB. diff --git a/external/gpl3/binutils.old/dist/include/opcode/ppc.h b/external/gpl3/binutils.old/dist/include/opcode/ppc.h index 628a7a184bc..44445bcad22 100644 --- a/external/gpl3/binutils.old/dist/include/opcode/ppc.h +++ b/external/gpl3/binutils.old/dist/include/opcode/ppc.h @@ -1,5 +1,5 @@ /* ppc.h -- Header file for PowerPC opcode table - Copyright (C) 1994-2016 Free Software Foundation, Inc. + Copyright (C) 1994-2018 Free Software Foundation, Inc. Written by Ian Lance Taylor, Cygnus Support This file is part of GDB, GAS, and the GNU binutils. @@ -30,6 +30,14 @@ extern "C" { typedef uint64_t ppc_cpu_t; +#if BFD_HOST_64BIT_LONG +# define PPC_INT_FMT "l" +#elif defined (__MSVCRT__) +# define PPC_INT_FMT "I64" +#else +# define PPC_INT_FMT "ll" +#endif + /* The opcode table is an array of struct powerpc_opcode. */ struct powerpc_opcode @@ -39,13 +47,13 @@ struct powerpc_opcode /* The opcode itself. Those bits which will be filled in with operands are zeroes. */ - unsigned long opcode; + uint64_t opcode; /* The opcode mask. This is used by the disassembler. This is a mask containing ones indicating those bits which must match the opcode field, and zeroes indicating those bits which need not match (and are presumably filled in by operands). */ - unsigned long mask; + uint64_t mask; /* One bit flags for the opcode. These are used to indicate which specific processors support the instructions. The defined values @@ -67,152 +75,164 @@ struct powerpc_opcode in the order in which the disassembler should consider instructions. */ extern const struct powerpc_opcode powerpc_opcodes[]; -extern const int powerpc_num_opcodes; +extern const unsigned int powerpc_num_opcodes; extern const struct powerpc_opcode vle_opcodes[]; -extern const int vle_num_opcodes; +extern const unsigned int vle_num_opcodes; +extern const struct powerpc_opcode spe2_opcodes[]; +extern const unsigned int spe2_num_opcodes; /* Values defined for the flags field of a struct powerpc_opcode. */ /* Opcode is defined for the PowerPC architecture. */ -#define PPC_OPCODE_PPC 1 +#define PPC_OPCODE_PPC 0x1ull /* Opcode is defined for the POWER (RS/6000) architecture. */ -#define PPC_OPCODE_POWER 2 +#define PPC_OPCODE_POWER 0x2ull /* Opcode is defined for the POWER2 (Rios 2) architecture. */ -#define PPC_OPCODE_POWER2 4 +#define PPC_OPCODE_POWER2 0x4ull + +/* Opcode is only defined on 64 bit architectures. */ +#define PPC_OPCODE_64 0x8ull /* Opcode is supported by the Motorola PowerPC 601 processor. The 601 is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions, but it also supports many additional POWER instructions. */ -#define PPC_OPCODE_601 8 +#define PPC_OPCODE_601 0x10ull /* Opcode is supported in both the Power and PowerPC architectures (ie, compiler's -mcpu=common or assembler's -mcom). More than just the intersection of PPC_OPCODE_PPC with the union of PPC_OPCODE_POWER and PPC_OPCODE_POWER2 because many instructions changed mnemonics between POWER and POWERPC. */ -#define PPC_OPCODE_COMMON 0x10 +#define PPC_OPCODE_COMMON 0x20ull /* Opcode is supported for any Power or PowerPC platform (this is for the assembler's -many option, and it eliminates duplicates). */ -#define PPC_OPCODE_ANY 0x20 - -/* Opcode is only defined on 64 bit architectures. */ -#define PPC_OPCODE_64 0x40 +#define PPC_OPCODE_ANY 0x40ull /* Opcode is supported as part of the 64-bit bridge. */ -#define PPC_OPCODE_64_BRIDGE 0x80 +#define PPC_OPCODE_64_BRIDGE 0x80ull /* Opcode is supported by Altivec Vector Unit */ -#define PPC_OPCODE_ALTIVEC 0x100 +#define PPC_OPCODE_ALTIVEC 0x100ull /* Opcode is supported by PowerPC 403 processor. */ -#define PPC_OPCODE_403 0x200 +#define PPC_OPCODE_403 0x200ull /* Opcode is supported by PowerPC BookE processor. */ -#define PPC_OPCODE_BOOKE 0x400 - -/* Opcode is supported by PowerPC 440 processor. */ -#define PPC_OPCODE_440 0x800 +#define PPC_OPCODE_BOOKE 0x400ull /* Opcode is only supported by Power4 architecture. */ -#define PPC_OPCODE_POWER4 0x1000 - -/* Opcode is only supported by Power7 architecture. */ -#define PPC_OPCODE_POWER7 0x2000 +#define PPC_OPCODE_POWER4 0x800ull -/* Opcode is only supported by e500x2 Core. */ -#define PPC_OPCODE_SPE 0x4000 +/* Opcode is only supported by e500x2 Core. + This bit, PPC_OPCODE_EFS, PPC_OPCODE_VLE, and all those with APU in + their comment mark opcodes so that when those instructions are used + an APUinfo entry can be generated. */ +#define PPC_OPCODE_SPE 0x1000ull -/* Opcode is supported by e500x2 Integer select APU. */ -#define PPC_OPCODE_ISEL 0x8000 +/* Opcode is supported by Integer select APU. */ +#define PPC_OPCODE_ISEL 0x2000ull /* Opcode is an e500 SPE floating point instruction. */ -#define PPC_OPCODE_EFS 0x10000 +#define PPC_OPCODE_EFS 0x4000ull /* Opcode is supported by branch locking APU. */ -#define PPC_OPCODE_BRLOCK 0x20000 +#define PPC_OPCODE_BRLOCK 0x8000ull /* Opcode is supported by performance monitor APU. */ -#define PPC_OPCODE_PMR 0x40000 +#define PPC_OPCODE_PMR 0x10000ull /* Opcode is supported by cache locking APU. */ -#define PPC_OPCODE_CACHELCK 0x80000 +#define PPC_OPCODE_CACHELCK 0x20000ull /* Opcode is supported by machine check APU. */ -#define PPC_OPCODE_RFMCI 0x100000 +#define PPC_OPCODE_RFMCI 0x40000ull + +/* Opcode is supported by PowerPC 440 processor. */ +#define PPC_OPCODE_440 0x80000ull /* Opcode is only supported by Power5 architecture. */ -#define PPC_OPCODE_POWER5 0x200000 +#define PPC_OPCODE_POWER5 0x100000ull /* Opcode is supported by PowerPC e300 family. */ -#define PPC_OPCODE_E300 0x400000 +#define PPC_OPCODE_E300 0x200000ull /* Opcode is only supported by Power6 architecture. */ -#define PPC_OPCODE_POWER6 0x800000 +#define PPC_OPCODE_POWER6 0x400000ull /* Opcode is only supported by PowerPC Cell family. */ -#define PPC_OPCODE_CELL 0x1000000 +#define PPC_OPCODE_CELL 0x800000ull /* Opcode is supported by CPUs with paired singles support. */ -#define PPC_OPCODE_PPCPS 0x2000000 +#define PPC_OPCODE_PPCPS 0x1000000ull /* Opcode is supported by Power E500MC */ -#define PPC_OPCODE_E500MC 0x4000000 +#define PPC_OPCODE_E500MC 0x2000000ull /* Opcode is supported by PowerPC 405 processor. */ -#define PPC_OPCODE_405 0x8000000 +#define PPC_OPCODE_405 0x4000000ull /* Opcode is supported by Vector-Scalar (VSX) Unit */ -#define PPC_OPCODE_VSX 0x10000000 +#define PPC_OPCODE_VSX 0x8000000ull + +/* Opcode is only supported by Power7 architecture. */ +#define PPC_OPCODE_POWER7 0x10000000ull /* Opcode is supported by A2. */ -#define PPC_OPCODE_A2 0x20000000 +#define PPC_OPCODE_A2 0x20000000ull /* Opcode is supported by PowerPC 476 processor. */ -#define PPC_OPCODE_476 0x40000000 +#define PPC_OPCODE_476 0x40000000ull /* Opcode is supported by AppliedMicro Titan core */ -#define PPC_OPCODE_TITAN 0x80000000 +#define PPC_OPCODE_TITAN 0x80000000ull /* Opcode which is supported by the e500 family */ -#define PPC_OPCODE_E500 0x100000000ull - -/* Opcode is supported by Extended Altivec Vector Unit */ -#define PPC_OPCODE_ALTIVEC2 0x200000000ull +#define PPC_OPCODE_E500 0x100000000ull /* Opcode is supported by Power E6500 */ -#define PPC_OPCODE_E6500 0x400000000ull +#define PPC_OPCODE_E6500 0x200000000ull /* Opcode is supported by Thread management APU */ -#define PPC_OPCODE_TMR 0x800000000ull +#define PPC_OPCODE_TMR 0x400000000ull /* Opcode which is supported by the VLE extension. */ -#define PPC_OPCODE_VLE 0x1000000000ull +#define PPC_OPCODE_VLE 0x800000000ull /* Opcode is only supported by Power8 architecture. */ -#define PPC_OPCODE_POWER8 0x2000000000ull - -/* Opcode which is supported by the Hardware Transactional Memory extension. */ -/* Currently, this is the same as the POWER8 mask. If another cpu comes out - that isn't a superset of POWER8, we can define this to its own mask. */ -#define PPC_OPCODE_HTM PPC_OPCODE_POWER8 +#define PPC_OPCODE_POWER8 0x1000000000ull /* Opcode is supported by ppc750cl. */ -#define PPC_OPCODE_750 0x4000000000ull +#define PPC_OPCODE_750 0x2000000000ull /* Opcode is supported by ppc7450. */ -#define PPC_OPCODE_7450 0x8000000000ull +#define PPC_OPCODE_7450 0x4000000000ull /* Opcode is supported by ppc821/850/860. */ -#define PPC_OPCODE_860 0x10000000000ull +#define PPC_OPCODE_860 0x8000000000ull /* Opcode is only supported by Power9 architecture. */ -#define PPC_OPCODE_POWER9 0x20000000000ull +#define PPC_OPCODE_POWER9 0x10000000000ull + +/* Opcode is supported by e200z4. */ +#define PPC_OPCODE_E200Z4 0x20000000000ull + +/* Disassemble to instructions matching later in the opcode table + with fewer "mask" bits set rather than the earlist match. Fewer + "mask" bits set imply a more general form of the opcode, in fact + the underlying machine instruction. */ +#define PPC_OPCODE_RAW 0x40000000000ull + +/* Opcode is supported by PowerPC LSP */ +#define PPC_OPCODE_LSP 0x80000000000ull + +/* Opcode is only supported by Freescale SPE2 APU. */ +#define PPC_OPCODE_SPE2 0x100000000000ull -/* Opcode is supported by Vector-Scalar (VSX) Unit from ISA 2.08. */ -#define PPC_OPCODE_VSX3 0x40000000000ull +/* Opcode is supported by EFS2. */ +#define PPC_OPCODE_EFS2 0x200000000000ull /* A macro to extract the major opcode from an instruction. */ #define PPC_OP(i) (((i) >> 26) & 0x3f) @@ -225,13 +245,19 @@ extern const int vle_num_opcodes; /* A macro to convert a VLE opcode to a VLE opcode segment. */ #define VLE_OP_TO_SEG(i) ((i) >> 1) + +/* A macro to extract the extended opcode from a SPE2 instruction. */ +#define SPE2_XOP(i) ((i) & 0x7ff) + +/* A macro to convert a SPE2 extended opcode to a SPE2 xopcode segment. */ +#define SPE2_XOP_TO_SEG(i) ((i) >> 7) /* The operands table is an array of struct powerpc_operand. */ struct powerpc_operand { /* A bitmask of bits in the operand. */ - unsigned int bitm; + uint64_t bitm; /* The shift operation to be applied to the operand. No shift is made if this is zero. For positive values, the operand @@ -259,8 +285,8 @@ struct powerpc_operand string (the operand will be inserted in any case). If the operand value is legal, *ERRMSG will be unchanged (most operands can accept any value). */ - unsigned long (*insert) - (unsigned long instruction, long op, ppc_cpu_t dialect, const char **errmsg); + uint64_t (*insert) + (uint64_t instruction, int64_t op, ppc_cpu_t dialect, const char **errmsg); /* Extraction function. This is used by the disassembler. To extract this operand type from an instruction, check this field. @@ -281,7 +307,7 @@ struct powerpc_operand non-zero if this operand type can not actually be extracted from this operand (i.e., the instruction does not match). If the operand is valid, *INVALID will not be changed. */ - long (*extract) (unsigned long instruction, ppc_cpu_t dialect, int *invalid); + int64_t (*extract) (uint64_t instruction, ppc_cpu_t dialect, int *invalid); /* One bit syntax flags. */ unsigned long flags; @@ -298,59 +324,86 @@ extern const unsigned int num_powerpc_operands; goes in the insn. */ #define PPC_OPSHIFT_INV (-1U << 31) -/* Values defined for the flags field of a struct powerpc_operand. */ +/* Values defined for the flags field of a struct powerpc_operand. + Keep the register bits low: They need to fit in an unsigned short. */ -/* This operand takes signed values. */ -#define PPC_OPERAND_SIGNED (0x1) +/* This operand names a register. The disassembler uses this to print + register names with a leading 'r'. */ +#define PPC_OPERAND_GPR (0x1) -/* This operand takes signed values, but also accepts a full positive - range of values when running in 32 bit mode. That is, if bits is - 16, it takes any value from -0x8000 to 0xffff. In 64 bit mode, - this flag is ignored. */ -#define PPC_OPERAND_SIGNOPT (0x2) +/* Like PPC_OPERAND_GPR, but don't print a leading 'r' for r0. */ +#define PPC_OPERAND_GPR_0 (0x2) -/* This operand does not actually exist in the assembler input. This - is used to support extended mnemonics such as mr, for which two - operands fields are identical. The assembler should call the - insert function with any op value. The disassembler should call - the extract function, ignore the return value, and check the value - placed in the valid argument. */ -#define PPC_OPERAND_FAKE (0x4) +/* This operand names a floating point register. The disassembler + prints these with a leading 'f'. */ +#define PPC_OPERAND_FPR (0x4) -/* The next operand should be wrapped in parentheses rather than - separated from this one by a comma. This is used for the load and - store instructions which want their operands to look like - reg,displacement(reg) - */ -#define PPC_OPERAND_PARENS (0x8) +/* This operand names a vector unit register. The disassembler + prints these with a leading 'v'. */ +#define PPC_OPERAND_VR (0x8) -/* This operand may use the symbolic names for the CR fields, which - are +/* This operand names a vector-scalar unit register. The disassembler + prints these with a leading 'vs'. */ +#define PPC_OPERAND_VSR (0x10) + +/* This operand may use the symbolic names for the CR fields (even + without -mregnames), which are lt 0 gt 1 eq 2 so 3 un 3 cr0 0 cr1 1 cr2 2 cr3 3 cr4 4 cr5 5 cr6 6 cr7 7 These may be combined arithmetically, as in cr2*4+gt. These are only supported on the PowerPC, not the POWER. */ -#define PPC_OPERAND_CR_BIT (0x10) +#define PPC_OPERAND_CR_BIT (0x20) -/* This operand names a register. The disassembler uses this to print - register names with a leading 'r'. */ -#define PPC_OPERAND_GPR (0x20) +/* This is a CR FIELD that does not use symbolic names (unless + -mregnames is in effect). */ +#define PPC_OPERAND_CR_REG (0x40) -/* Like PPC_OPERAND_GPR, but don't print a leading 'r' for r0. */ -#define PPC_OPERAND_GPR_0 (0x40) +/* This operand names a special purpose register. */ +#define PPC_OPERAND_SPR (0x80) -/* This operand names a floating point register. The disassembler - prints these with a leading 'f'. */ -#define PPC_OPERAND_FPR (0x80) +/* This operand names a paired-single graphics quantization register. */ +#define PPC_OPERAND_GQR (0x100) /* This operand is a relative branch displacement. The disassembler prints these symbolically if possible. */ -#define PPC_OPERAND_RELATIVE (0x100) +#define PPC_OPERAND_RELATIVE (0x200) /* This operand is an absolute branch address. The disassembler prints these symbolically if possible. */ -#define PPC_OPERAND_ABSOLUTE (0x200) +#define PPC_OPERAND_ABSOLUTE (0x400) + +/* This operand takes signed values. */ +#define PPC_OPERAND_SIGNED (0x800) + +/* This operand takes signed values, but also accepts a full positive + range of values when running in 32 bit mode. That is, if bits is + 16, it takes any value from -0x8000 to 0xffff. In 64 bit mode, + this flag is ignored. */ +#define PPC_OPERAND_SIGNOPT (0x1000) + +/* The next operand should be wrapped in parentheses rather than + separated from this one by a comma. This is used for the load and + store instructions which want their operands to look like + reg,displacement(reg) + */ +#define PPC_OPERAND_PARENS (0x2000) + +/* This operand is for the DS field in a DS form instruction. */ +#define PPC_OPERAND_DS (0x4000) + +/* This operand is for the DQ field in a DQ form instruction. */ +#define PPC_OPERAND_DQ (0x8000) + +/* This operand should be regarded as a negative number for the + purposes of overflow checking (i.e., the normal most negative + number is disallowed and one more than the normal most positive + number is allowed). This flag will only be set for a signed + operand. */ +#define PPC_OPERAND_NEGATIVE (0x10000) + +/* Valid range of operand is 0..n rather than 0..n-1. */ +#define PPC_OPERAND_PLUS1 (0x20000) /* This operand is optional, and is zero if omitted. This is used for example, in the optional BF field in the comparison instructions. The @@ -358,7 +411,7 @@ extern const unsigned int num_powerpc_operands; and the number of operands remaining for the opcode, and decide whether this operand is present or not. The disassembler should print this operand out only if it is not zero. */ -#define PPC_OPERAND_OPTIONAL (0x400) +#define PPC_OPERAND_OPTIONAL (0x80000) /* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand is omitted, then for the next operand use this operand value plus @@ -366,44 +419,21 @@ extern const unsigned int num_powerpc_operands; hack is needed because the Power rotate instructions can take either 4 or 5 operands. The disassembler should print this operand out regardless of the PPC_OPERAND_OPTIONAL field. */ -#define PPC_OPERAND_NEXT (0x800) - -/* This operand should be regarded as a negative number for the - purposes of overflow checking (i.e., the normal most negative - number is disallowed and one more than the normal most positive - number is allowed). This flag will only be set for a signed - operand. */ -#define PPC_OPERAND_NEGATIVE (0x1000) - -/* This operand names a vector unit register. The disassembler - prints these with a leading 'v'. */ -#define PPC_OPERAND_VR (0x2000) - -/* This operand is for the DS field in a DS form instruction. */ -#define PPC_OPERAND_DS (0x4000) - -/* This operand is for the DQ field in a DQ form instruction. */ -#define PPC_OPERAND_DQ (0x8000) - -/* Valid range of operand is 0..n rather than 0..n-1. */ -#define PPC_OPERAND_PLUS1 (0x10000) - -/* Xilinx APU and FSL related operands */ -#define PPC_OPERAND_FSL (0x20000) -#define PPC_OPERAND_FCR (0x40000) -#define PPC_OPERAND_UDI (0x80000) - -/* This operand names a vector-scalar unit register. The disassembler - prints these with a leading 'vs'. */ -#define PPC_OPERAND_VSR (0x100000) - -/* This is a CR FIELD that does not use symbolic names. */ -#define PPC_OPERAND_CR_REG (0x200000) +#define PPC_OPERAND_NEXT (0x100000) /* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand is omitted, then the value it should use for the operand is stored in the SHIFT field of the immediatly following operand field. */ -#define PPC_OPERAND_OPTIONAL_VALUE (0x400000) +#define PPC_OPERAND_OPTIONAL_VALUE (0x200000) + +/* This flag is only used with PPC_OPERAND_OPTIONAL. The operand is + only optional when generating 32-bit code. */ +#define PPC_OPERAND_OPTIONAL32 (0x400000) + +/* Xilinx APU and FSL related operands */ +#define PPC_OPERAND_FSL (0x800000) +#define PPC_OPERAND_FCR (0x1000000) +#define PPC_OPERAND_UDI (0x2000000) /* The POWER and PowerPC assemblers use a few macros. We keep them with the operands table for simplicity. The macro table is an @@ -433,7 +463,7 @@ extern const int powerpc_num_macros; extern ppc_cpu_t ppc_parse_cpu (ppc_cpu_t, ppc_cpu_t *, const char *); -static inline long +static inline int64_t ppc_optional_operand_value (const struct powerpc_operand *operand) { if ((operand->flags & PPC_OPERAND_OPTIONAL_VALUE) != 0) @@ -441,6 +471,23 @@ ppc_optional_operand_value (const struct powerpc_operand *operand) return 0; } +/* PowerPC VLE insns. */ +/* Form I16L, uses 16A relocs. */ +#define E_OR2I_INSN 0x7000C000 +#define E_AND2I_DOT_INSN 0x7000C800 +#define E_OR2IS_INSN 0x7000D000 +#define E_LIS_INSN 0x7000E000 +#define E_AND2IS_DOT_INSN 0x7000E800 + +/* Form I16A, uses 16D relocs. */ +#define E_ADD2I_DOT_INSN 0x70008800 +#define E_ADD2IS_INSN 0x70009000 +#define E_CMP16I_INSN 0x70009800 +#define E_MULL2I_INSN 0x7000A000 +#define E_CMPL16I_INSN 0x7000A800 +#define E_CMPH16I_INSN 0x7000B000 +#define E_CMPHL16I_INSN 0x7000B800 + #ifdef __cplusplus } #endif diff --git a/external/gpl3/binutils.old/dist/include/opcode/pyr.h b/external/gpl3/binutils.old/dist/include/opcode/pyr.h index 27bed839fa4..f56afeef3ce 100644 --- a/external/gpl3/binutils.old/dist/include/opcode/pyr.h +++ b/external/gpl3/binutils.old/dist/include/opcode/pyr.h @@ -1,6 +1,6 @@ /* pyramid.opcode.h -- gdb initial attempt. - Copyright (C) 2001-2016 Free Software Foundation, Inc. + Copyright (C) 2001-2018 Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by diff --git a/external/gpl3/binutils.old/dist/include/opcode/riscv-opc.h b/external/gpl3/binutils.old/dist/include/opcode/riscv-opc.h index 23ae81a3af1..60bd2f999e8 100644 --- a/external/gpl3/binutils.old/dist/include/opcode/riscv-opc.h +++ b/external/gpl3/binutils.old/dist/include/opcode/riscv-opc.h @@ -1,1234 +1,1382 @@ -/* Automatically generated by parse-opcodes */ +/* Automatically generated by parse-opcodes. */ #ifndef RISCV_ENCODING_H #define RISCV_ENCODING_H -#define MATCH_CUSTOM3_RD_RS1_RS2 0x707b -#define MASK_CUSTOM3_RD_RS1_RS2 0x707f -#define MATCH_VLSEGSTWU 0xc00305b -#define MASK_VLSEGSTWU 0x1e00707f -#define MATCH_C_LW0 0x12 -#define MASK_C_LW0 0x801f -#define MATCH_FMV_D_X 0xf2000053 -#define MASK_FMV_D_X 0xfff0707f -#define MATCH_VLH 0x200205b -#define MASK_VLH 0xfff0707f -#define MATCH_C_LI 0x0 -#define MASK_C_LI 0x1f -#define MATCH_FADD_D 0x2000053 -#define MASK_FADD_D 0xfe00007f -#define MATCH_C_LD 0x9 -#define MASK_C_LD 0x1f -#define MATCH_VLD 0x600205b -#define MASK_VLD 0xfff0707f -#define MATCH_FADD_S 0x53 -#define MASK_FADD_S 0xfe00007f -#define MATCH_C_LW 0xa -#define MASK_C_LW 0x1f -#define MATCH_VLW 0x400205b -#define MASK_VLW 0xfff0707f -#define MATCH_VSSEGSTW 0x400307b -#define MASK_VSSEGSTW 0x1e00707f -#define MATCH_UTIDX 0x6077 -#define MASK_UTIDX 0xfffff07f -#define MATCH_C_FLW 0x14 -#define MASK_C_FLW 0x1f -#define MATCH_FSUB_D 0xa000053 -#define MASK_FSUB_D 0xfe00007f -#define MATCH_VSSEGSTD 0x600307b -#define MASK_VSSEGSTD 0x1e00707f -#define MATCH_VSSEGSTB 0x307b -#define MASK_VSSEGSTB 0x1e00707f -#define MATCH_DIV 0x2004033 -#define MASK_DIV 0xfe00707f -#define MATCH_FMV_H_X 0xf4000053 -#define MASK_FMV_H_X 0xfff0707f -#define MATCH_C_FLD 0x15 -#define MASK_C_FLD 0x1f +#define MATCH_SLLI_RV32 0x1013 +#define MASK_SLLI_RV32 0xfe00707f +#define MATCH_SRLI_RV32 0x5013 +#define MASK_SRLI_RV32 0xfe00707f +#define MATCH_SRAI_RV32 0x40005013 +#define MASK_SRAI_RV32 0xfe00707f +#define MATCH_FRFLAGS 0x102073 +#define MASK_FRFLAGS 0xfffff07f +#define MATCH_FSFLAGS 0x101073 +#define MASK_FSFLAGS 0xfff0707f +#define MATCH_FSFLAGSI 0x105073 +#define MASK_FSFLAGSI 0xfff0707f #define MATCH_FRRM 0x202073 #define MASK_FRRM 0xfffff07f -#define MATCH_VFMSV_S 0x1000202b -#define MASK_VFMSV_S 0xfff0707f -#define MATCH_C_LWSP 0x5 -#define MASK_C_LWSP 0x1f -#define MATCH_FENCE 0xf -#define MASK_FENCE 0x707f -#define MATCH_FNMSUB_S 0x4b -#define MASK_FNMSUB_S 0x600007f -#define MATCH_FLE_S 0xa0000053 -#define MASK_FLE_S 0xfe00707f -#define MATCH_FNMSUB_H 0x400004b -#define MASK_FNMSUB_H 0x600007f -#define MATCH_FLE_H 0xbc000053 -#define MASK_FLE_H 0xfe00707f -#define MATCH_FLW 0x2007 -#define MASK_FLW 0x707f -#define MATCH_VSETVL 0x600b -#define MASK_VSETVL 0xfff0707f -#define MATCH_VFMSV_D 0x1200202b -#define MASK_VFMSV_D 0xfff0707f -#define MATCH_FLE_D 0xa2000053 -#define MASK_FLE_D 0xfe00707f -#define MATCH_FENCE_I 0x100f -#define MASK_FENCE_I 0x707f -#define MATCH_FNMSUB_D 0x200004b -#define MASK_FNMSUB_D 0x600007f -#define MATCH_ADDW 0x3b -#define MASK_ADDW 0xfe00707f -#define MATCH_XOR 0x4033 -#define MASK_XOR 0xfe00707f -#define MATCH_SUB 0x40000033 -#define MASK_SUB 0xfe00707f -#define MATCH_VSSTW 0x400307b -#define MASK_VSSTW 0xfe00707f -#define MATCH_VSSTH 0x200307b -#define MASK_VSSTH 0xfe00707f -#define MATCH_SC_W 0x1800202f -#define MASK_SC_W 0xf800707f -#define MATCH_VSSTB 0x307b -#define MASK_VSSTB 0xfe00707f -#define MATCH_VSSTD 0x600307b -#define MASK_VSSTD 0xfe00707f -#define MATCH_ADDI 0x13 -#define MASK_ADDI 0x707f -#define MATCH_RDTIMEH 0xc8102073 -#define MASK_RDTIMEH 0xfffff07f -#define MATCH_MULH 0x2001033 -#define MASK_MULH 0xfe00707f -#define MATCH_CSRRSI 0x6073 -#define MASK_CSRRSI 0x707f -#define MATCH_FCVT_D_WU 0xd2100053 -#define MASK_FCVT_D_WU 0xfff0007f -#define MATCH_MULW 0x200003b -#define MASK_MULW 0xfe00707f -#define MATCH_CUSTOM1_RD_RS1_RS2 0x702b -#define MASK_CUSTOM1_RD_RS1_RS2 0x707f -#define MATCH_VENQIMM1 0xc00302b -#define MASK_VENQIMM1 0xfe007fff -#define MATCH_VENQIMM2 0xe00302b -#define MASK_VENQIMM2 0xfe007fff +#define MATCH_FSRM 0x201073 +#define MASK_FSRM 0xfff0707f +#define MATCH_FSRMI 0x205073 +#define MASK_FSRMI 0xfff0707f +#define MATCH_FSCSR 0x301073 +#define MASK_FSCSR 0xfff0707f +#define MATCH_FRCSR 0x302073 +#define MASK_FRCSR 0xfffff07f +#define MATCH_RDCYCLE 0xc0002073 +#define MASK_RDCYCLE 0xfffff07f +#define MATCH_RDTIME 0xc0102073 +#define MASK_RDTIME 0xfffff07f #define MATCH_RDINSTRET 0xc0202073 #define MASK_RDINSTRET 0xfffff07f -#define MATCH_C_SWSP 0x8 -#define MASK_C_SWSP 0x1f -#define MATCH_VLSTW 0x400305b -#define MASK_VLSTW 0xfe00707f -#define MATCH_VLSTH 0x200305b -#define MASK_VLSTH 0xfe00707f -#define MATCH_VLSTB 0x305b -#define MASK_VLSTB 0xfe00707f -#define MATCH_VLSTD 0x600305b -#define MASK_VLSTD 0xfe00707f -#define MATCH_ANDI 0x7013 -#define MASK_ANDI 0x707f -#define MATCH_FMV_X_S 0xe0000053 -#define MASK_FMV_X_S 0xfff0707f -#define MATCH_CUSTOM0_RD_RS1_RS2 0x700b -#define MASK_CUSTOM0_RD_RS1_RS2 0x707f -#define MATCH_FNMADD_S 0x4f -#define MASK_FNMADD_S 0x600007f -#define MATCH_LWU 0x6003 -#define MASK_LWU 0x707f -#define MATCH_CUSTOM0_RS1 0x200b -#define MASK_CUSTOM0_RS1 0x707f -#define MATCH_VLSEGSTBU 0x800305b -#define MASK_VLSEGSTBU 0x1e00707f -#define MATCH_FNMADD_D 0x200004f -#define MASK_FNMADD_D 0x600007f -#define MATCH_FCVT_W_S 0xc0000053 -#define MASK_FCVT_W_S 0xfff0007f -#define MATCH_C_SRAI 0x1019 -#define MASK_C_SRAI 0x1c1f -#define MATCH_MULHSU 0x2002033 -#define MASK_MULHSU 0xfe00707f -#define MATCH_FCVT_D_LU 0xd2300053 -#define MASK_FCVT_D_LU 0xfff0007f -#define MATCH_FCVT_W_D 0xc2000053 -#define MASK_FCVT_W_D 0xfff0007f -#define MATCH_FSUB_H 0xc000053 -#define MASK_FSUB_H 0xfe00007f -#define MATCH_DIVUW 0x200503b -#define MASK_DIVUW 0xfe00707f -#define MATCH_SLTI 0x2013 -#define MASK_SLTI 0x707f -#define MATCH_VLSTBU 0x800305b -#define MASK_VLSTBU 0xfe00707f -#define MATCH_SLTU 0x3033 -#define MASK_SLTU 0xfe00707f -#define MATCH_FLH 0x1007 -#define MASK_FLH 0x707f -#define MATCH_CUSTOM2_RD_RS1_RS2 0x705b -#define MASK_CUSTOM2_RD_RS1_RS2 0x707f -#define MATCH_FLD 0x3007 -#define MASK_FLD 0x707f -#define MATCH_FSUB_S 0x8000053 -#define MASK_FSUB_S 0xfe00007f -#define MATCH_FCVT_H_LU 0x6c000053 -#define MASK_FCVT_H_LU 0xfff0007f -#define MATCH_CUSTOM0 0xb -#define MASK_CUSTOM0 0x707f -#define MATCH_CUSTOM1 0x2b -#define MASK_CUSTOM1 0x707f -#define MATCH_CUSTOM2 0x5b -#define MASK_CUSTOM2 0x707f -#define MATCH_CUSTOM3 0x7b -#define MASK_CUSTOM3 0x707f -#define MATCH_VXCPTSAVE 0x302b -#define MASK_VXCPTSAVE 0xfff07fff -#define MATCH_VMSV 0x200202b -#define MASK_VMSV 0xfff0707f -#define MATCH_FCVT_LU_S 0xc0300053 -#define MASK_FCVT_LU_S 0xfff0007f +#define MATCH_RDCYCLEH 0xc8002073 +#define MASK_RDCYCLEH 0xfffff07f +#define MATCH_RDTIMEH 0xc8102073 +#define MASK_RDTIMEH 0xfffff07f +#define MATCH_RDINSTRETH 0xc8202073 +#define MASK_RDINSTRETH 0xfffff07f +#define MATCH_SCALL 0x73 +#define MASK_SCALL 0xffffffff +#define MATCH_SBREAK 0x100073 +#define MASK_SBREAK 0xffffffff +#define MATCH_BEQ 0x63 +#define MASK_BEQ 0x707f +#define MATCH_BNE 0x1063 +#define MASK_BNE 0x707f +#define MATCH_BLT 0x4063 +#define MASK_BLT 0x707f +#define MATCH_BGE 0x5063 +#define MASK_BGE 0x707f +#define MATCH_BLTU 0x6063 +#define MASK_BLTU 0x707f +#define MATCH_BGEU 0x7063 +#define MASK_BGEU 0x707f +#define MATCH_JALR 0x67 +#define MASK_JALR 0x707f +#define MATCH_JAL 0x6f +#define MASK_JAL 0x7f +#define MATCH_LUI 0x37 +#define MASK_LUI 0x7f #define MATCH_AUIPC 0x17 #define MASK_AUIPC 0x7f -#define MATCH_FRFLAGS 0x102073 -#define MASK_FRFLAGS 0xfffff07f -#define MATCH_FCVT_LU_D 0xc2300053 -#define MASK_FCVT_LU_D 0xfff0007f -#define MATCH_CSRRWI 0x5073 -#define MASK_CSRRWI 0x707f -#define MATCH_FADD_H 0x4000053 -#define MASK_FADD_H 0xfe00007f -#define MATCH_FSQRT_S 0x58000053 -#define MASK_FSQRT_S 0xfff0007f -#define MATCH_VXCPTKILL 0x400302b -#define MASK_VXCPTKILL 0xffffffff -#define MATCH_STOP 0x5077 -#define MASK_STOP 0xffffffff -#define MATCH_FSGNJN_S 0x20001053 -#define MASK_FSGNJN_S 0xfe00707f -#define MATCH_FSGNJN_H 0x34000053 -#define MASK_FSGNJN_H 0xfe00707f -#define MATCH_FSQRT_D 0x5a000053 -#define MASK_FSQRT_D 0xfff0007f +#define MATCH_ADDI 0x13 +#define MASK_ADDI 0x707f +#define MATCH_SLLI 0x1013 +#define MASK_SLLI 0xfc00707f +#define MATCH_SLTI 0x2013 +#define MASK_SLTI 0x707f +#define MATCH_SLTIU 0x3013 +#define MASK_SLTIU 0x707f #define MATCH_XORI 0x4013 #define MASK_XORI 0x707f -#define MATCH_DIVU 0x2005033 -#define MASK_DIVU 0xfe00707f -#define MATCH_FSGNJN_D 0x22001053 -#define MASK_FSGNJN_D 0xfe00707f -#define MATCH_FSQRT_H 0x24000053 -#define MASK_FSQRT_H 0xfff0007f -#define MATCH_VSSEGSTH 0x200307b -#define MASK_VSSEGSTH 0x1e00707f -#define MATCH_SW 0x2023 -#define MASK_SW 0x707f -#define MATCH_VLSTWU 0xc00305b -#define MASK_VLSTWU 0xfe00707f -#define MATCH_VFSSEGW 0x1400207b -#define MASK_VFSSEGW 0x1ff0707f -#define MATCH_LHU 0x5003 -#define MASK_LHU 0x707f -#define MATCH_SH 0x1023 -#define MASK_SH 0x707f -#define MATCH_FMSUB_H 0x4000047 -#define MASK_FMSUB_H 0x600007f -#define MATCH_VXCPTAUX 0x200402b -#define MASK_VXCPTAUX 0xfffff07f -#define MATCH_FMSUB_D 0x2000047 -#define MASK_FMSUB_D 0x600007f -#define MATCH_VFSSEGD 0x1600207b -#define MASK_VFSSEGD 0x1ff0707f -#define MATCH_VLSEGHU 0xa00205b -#define MASK_VLSEGHU 0x1ff0707f -#define MATCH_MOVN 0x2007077 -#define MASK_MOVN 0xfe00707f -#define MATCH_CUSTOM1_RS1 0x202b -#define MASK_CUSTOM1_RS1 0x707f -#define MATCH_VLSTHU 0xa00305b -#define MASK_VLSTHU 0xfe00707f -#define MATCH_MOVZ 0x7077 -#define MASK_MOVZ 0xfe00707f -#define MATCH_CSRRW 0x1073 -#define MASK_CSRRW 0x707f -#define MATCH_LD 0x3003 -#define MASK_LD 0x707f -#define MATCH_LB 0x3 -#define MASK_LB 0x707f -#define MATCH_VLWU 0xc00205b -#define MASK_VLWU 0xfff0707f -#define MATCH_LH 0x1003 -#define MASK_LH 0x707f -#define MATCH_LW 0x2003 -#define MASK_LW 0x707f -#define MATCH_CSRRC 0x3073 -#define MASK_CSRRC 0x707f -#define MATCH_FCVT_LU_H 0x4c000053 -#define MASK_FCVT_LU_H 0xfff0007f -#define MATCH_FCVT_S_D 0x40100053 -#define MASK_FCVT_S_D 0xfff0007f -#define MATCH_BGEU 0x7063 -#define MASK_BGEU 0x707f -#define MATCH_VFLSTD 0x1600305b -#define MASK_VFLSTD 0xfe00707f -#define MATCH_FCVT_S_L 0xd0200053 -#define MASK_FCVT_S_L 0xfff0007f -#define MATCH_FCVT_S_H 0x84000053 -#define MASK_FCVT_S_H 0xfff0007f -#define MATCH_FSCSR 0x301073 -#define MASK_FSCSR 0xfff0707f -#define MATCH_FCVT_S_W 0xd0000053 -#define MASK_FCVT_S_W 0xfff0007f -#define MATCH_VFLSTW 0x1400305b -#define MASK_VFLSTW 0xfe00707f -#define MATCH_VXCPTEVAC 0x600302b -#define MASK_VXCPTEVAC 0xfff07fff -#define MATCH_AMOMINU_D 0xc000302f -#define MASK_AMOMINU_D 0xf800707f -#define MATCH_FSFLAGS 0x101073 -#define MASK_FSFLAGS 0xfff0707f #define MATCH_SRLI 0x5013 #define MASK_SRLI 0xfc00707f -#define MATCH_C_SRLI 0x819 -#define MASK_C_SRLI 0x1c1f -#define MATCH_AMOMINU_W 0xc000202f -#define MASK_AMOMINU_W 0xf800707f -#define MATCH_SRLW 0x503b -#define MASK_SRLW 0xfe00707f -#define MATCH_VFLSEGW 0x1400205b -#define MASK_VFLSEGW 0x1ff0707f -#define MATCH_C_LD0 0x8012 -#define MASK_C_LD0 0x801f -#define MATCH_VLSEGBU 0x800205b -#define MASK_VLSEGBU 0x1ff0707f -#define MATCH_JALR 0x67 -#define MASK_JALR 0x707f -#define MATCH_BLT 0x4063 -#define MASK_BLT 0x707f -#define MATCH_CUSTOM2_RD_RS1 0x605b -#define MASK_CUSTOM2_RD_RS1 0x707f -#define MATCH_FCLASS_S 0xe0001053 -#define MASK_FCLASS_S 0xfff0707f -#define MATCH_SFENCE_VM 0x10100073 -#define MASK_SFENCE_VM 0xfff07fff -#define MATCH_REM 0x2006033 -#define MASK_REM 0xfe00707f -#define MATCH_FCLASS_D 0xe2001053 -#define MASK_FCLASS_D 0xfff0707f -#define MATCH_FMUL_S 0x10000053 -#define MASK_FMUL_S 0xfe00007f -#define MATCH_RDCYCLEH 0xc8002073 -#define MASK_RDCYCLEH 0xfffff07f -#define MATCH_VLSEGSTHU 0xa00305b -#define MASK_VLSEGSTHU 0x1e00707f -#define MATCH_FMUL_D 0x12000053 -#define MASK_FMUL_D 0xfe00007f +#define MATCH_SRAI 0x40005013 +#define MASK_SRAI 0xfc00707f #define MATCH_ORI 0x6013 #define MASK_ORI 0x707f -#define MATCH_FMUL_H 0x14000053 -#define MASK_FMUL_H 0xfe00007f -#define MATCH_VFLSEGD 0x1600205b -#define MASK_VFLSEGD 0x1ff0707f -#define MATCH_FEQ_S 0xa0002053 -#define MASK_FEQ_S 0xfe00707f -#define MATCH_FSGNJX_D 0x22002053 -#define MASK_FSGNJX_D 0xfe00707f +#define MATCH_ANDI 0x7013 +#define MASK_ANDI 0x707f +#define MATCH_ADD 0x33 +#define MASK_ADD 0xfe00707f +#define MATCH_SUB 0x40000033 +#define MASK_SUB 0xfe00707f +#define MATCH_SLL 0x1033 +#define MASK_SLL 0xfe00707f +#define MATCH_SLT 0x2033 +#define MASK_SLT 0xfe00707f +#define MATCH_SLTU 0x3033 +#define MASK_SLTU 0xfe00707f +#define MATCH_XOR 0x4033 +#define MASK_XOR 0xfe00707f +#define MATCH_SRL 0x5033 +#define MASK_SRL 0xfe00707f +#define MATCH_SRA 0x40005033 +#define MASK_SRA 0xfe00707f +#define MATCH_OR 0x6033 +#define MASK_OR 0xfe00707f +#define MATCH_AND 0x7033 +#define MASK_AND 0xfe00707f +#define MATCH_ADDIW 0x1b +#define MASK_ADDIW 0x707f +#define MATCH_SLLIW 0x101b +#define MASK_SLLIW 0xfe00707f +#define MATCH_SRLIW 0x501b +#define MASK_SRLIW 0xfe00707f #define MATCH_SRAIW 0x4000501b #define MASK_SRAIW 0xfe00707f -#define MATCH_FSGNJX_H 0x3c000053 -#define MASK_FSGNJX_H 0xfe00707f -#define MATCH_FSGNJX_S 0x20002053 -#define MASK_FSGNJX_S 0xfe00707f -#define MATCH_FEQ_D 0xa2002053 -#define MASK_FEQ_D 0xfe00707f -#define MATCH_CUSTOM1_RD_RS1 0x602b -#define MASK_CUSTOM1_RD_RS1 0x707f -#define MATCH_FEQ_H 0xac000053 -#define MASK_FEQ_H 0xfe00707f -#define MATCH_AMOMAXU_D 0xe000302f -#define MASK_AMOMAXU_D 0xf800707f -#define MATCH_DIVW 0x200403b -#define MASK_DIVW 0xfe00707f -#define MATCH_AMOMAXU_W 0xe000202f -#define MASK_AMOMAXU_W 0xf800707f -#define MATCH_SRAI_RV32 0x40005013 -#define MASK_SRAI_RV32 0xfe00707f -#define MATCH_C_SRLI32 0xc19 -#define MASK_C_SRLI32 0x1c1f -#define MATCH_VFSSTW 0x1400307b -#define MASK_VFSSTW 0xfe00707f -#define MATCH_CUSTOM0_RD 0x400b -#define MASK_CUSTOM0_RD 0x707f -#define MATCH_C_BEQ 0x10 -#define MASK_C_BEQ 0x1f -#define MATCH_VFSSTD 0x1600307b -#define MASK_VFSSTD 0xfe00707f -#define MATCH_CUSTOM3_RD_RS1 0x607b -#define MASK_CUSTOM3_RD_RS1 0x707f -#define MATCH_LR_D 0x1000302f -#define MASK_LR_D 0xf9f0707f -#define MATCH_LR_W 0x1000202f -#define MASK_LR_W 0xf9f0707f -#define MATCH_FCVT_H_WU 0x7c000053 -#define MASK_FCVT_H_WU 0xfff0007f -#define MATCH_VMVV 0x200002b -#define MASK_VMVV 0xfff0707f +#define MATCH_ADDW 0x3b +#define MASK_ADDW 0xfe00707f +#define MATCH_SUBW 0x4000003b +#define MASK_SUBW 0xfe00707f #define MATCH_SLLW 0x103b #define MASK_SLLW 0xfe00707f -#define MATCH_SLLI 0x1013 -#define MASK_SLLI 0xfc00707f -#define MATCH_BEQ 0x63 -#define MASK_BEQ 0x707f -#define MATCH_AND 0x7033 -#define MASK_AND 0xfe00707f +#define MATCH_SRLW 0x503b +#define MASK_SRLW 0xfe00707f +#define MATCH_SRAW 0x4000503b +#define MASK_SRAW 0xfe00707f +#define MATCH_LB 0x3 +#define MASK_LB 0x707f +#define MATCH_LH 0x1003 +#define MASK_LH 0x707f +#define MATCH_LW 0x2003 +#define MASK_LW 0x707f +#define MATCH_LD 0x3003 +#define MASK_LD 0x707f #define MATCH_LBU 0x4003 #define MASK_LBU 0x707f -#define MATCH_FSGNJ_S 0x20000053 -#define MASK_FSGNJ_S 0xfe00707f -#define MATCH_FMSUB_S 0x47 -#define MASK_FMSUB_S 0x600007f -#define MATCH_C_SUB3 0x11c -#define MASK_C_SUB3 0x31f -#define MATCH_FSGNJ_H 0x2c000053 -#define MASK_FSGNJ_H 0xfe00707f -#define MATCH_VLB 0x205b -#define MASK_VLB 0xfff0707f -#define MATCH_C_ADDIW 0x1d -#define MASK_C_ADDIW 0x1f -#define MATCH_CUSTOM3_RS1_RS2 0x307b -#define MASK_CUSTOM3_RS1_RS2 0x707f -#define MATCH_FSGNJ_D 0x22000053 -#define MASK_FSGNJ_D 0xfe00707f -#define MATCH_VLSEGWU 0xc00205b -#define MASK_VLSEGWU 0x1ff0707f -#define MATCH_FCVT_S_WU 0xd0100053 -#define MASK_FCVT_S_WU 0xfff0007f -#define MATCH_CUSTOM3_RS1 0x207b -#define MASK_CUSTOM3_RS1 0x707f -#define MATCH_SC_D 0x1800302f -#define MASK_SC_D 0xf800707f -#define MATCH_VFSW 0x1400207b -#define MASK_VFSW 0xfff0707f -#define MATCH_AMOSWAP_D 0x800302f -#define MASK_AMOSWAP_D 0xf800707f +#define MATCH_LHU 0x5003 +#define MASK_LHU 0x707f +#define MATCH_LWU 0x6003 +#define MASK_LWU 0x707f #define MATCH_SB 0x23 #define MASK_SB 0x707f -#define MATCH_AMOSWAP_W 0x800202f -#define MASK_AMOSWAP_W 0xf800707f -#define MATCH_VFSD 0x1600207b -#define MASK_VFSD 0xfff0707f -#define MATCH_CUSTOM2_RS1 0x205b -#define MASK_CUSTOM2_RS1 0x707f +#define MATCH_SH 0x1023 +#define MASK_SH 0x707f +#define MATCH_SW 0x2023 +#define MASK_SW 0x707f #define MATCH_SD 0x3023 #define MASK_SD 0x707f -#define MATCH_FMV_S_X 0xf0000053 -#define MASK_FMV_S_X 0xfff0707f -#define MATCH_REMUW 0x200703b -#define MASK_REMUW 0xfe00707f -#define MATCH_JAL 0x6f -#define MASK_JAL 0x7f -#define MATCH_C_FSD 0x18 -#define MASK_C_FSD 0x1f -#define MATCH_RDCYCLE 0xc0002073 -#define MASK_RDCYCLE 0xfffff07f -#define MATCH_C_BNE 0x11 -#define MASK_C_BNE 0x1f -#define MATCH_C_ADD 0x1a -#define MASK_C_ADD 0x801f -#define MATCH_VXCPTCAUSE 0x402b -#define MASK_VXCPTCAUSE 0xfffff07f -#define MATCH_VGETCFG 0x400b -#define MASK_VGETCFG 0xfffff07f -#define MATCH_LUI 0x37 -#define MASK_LUI 0x7f -#define MATCH_VSETCFG 0x200b -#define MASK_VSETCFG 0x7fff -#define MATCH_C_SDSP 0x6 -#define MASK_C_SDSP 0x1f -#define MATCH_C_LDSP 0x4 -#define MASK_C_LDSP 0x1f -#define MATCH_FNMADD_H 0x400004f -#define MASK_FNMADD_H 0x600007f -#define MATCH_CUSTOM0_RS1_RS2 0x300b -#define MASK_CUSTOM0_RS1_RS2 0x707f -#define MATCH_SLLI_RV32 0x1013 -#define MASK_SLLI_RV32 0xfe00707f +#define MATCH_FENCE 0xf +#define MASK_FENCE 0x707f +#define MATCH_FENCE_I 0x100f +#define MASK_FENCE_I 0x707f #define MATCH_MUL 0x2000033 #define MASK_MUL 0xfe00707f -#define MATCH_CSRRCI 0x7073 -#define MASK_CSRRCI 0x707f -#define MATCH_C_SRAI32 0x1419 -#define MASK_C_SRAI32 0x1c1f -#define MATCH_FLT_H 0xb4000053 -#define MASK_FLT_H 0xfe00707f -#define MATCH_SRAI 0x40005013 -#define MASK_SRAI 0xfc00707f -#define MATCH_AMOAND_D 0x6000302f -#define MASK_AMOAND_D 0xf800707f -#define MATCH_FLT_D 0xa2001053 -#define MASK_FLT_D 0xfe00707f -#define MATCH_SRAW 0x4000503b -#define MASK_SRAW 0xfe00707f -#define MATCH_CSRRS 0x2073 -#define MASK_CSRRS 0x707f -#define MATCH_FLT_S 0xa0001053 -#define MASK_FLT_S 0xfe00707f -#define MATCH_ADDIW 0x1b -#define MASK_ADDIW 0x707f -#define MATCH_AMOAND_W 0x6000202f -#define MASK_AMOAND_W 0xf800707f -#define MATCH_CUSTOM2_RD 0x405b -#define MASK_CUSTOM2_RD 0x707f -#define MATCH_MRTS 0x30500073 -#define MASK_MRTS 0xffffffff -#define MATCH_FCVT_WU_D 0xc2100053 -#define MASK_FCVT_WU_D 0xfff0007f -#define MATCH_AMOXOR_W 0x2000202f -#define MASK_AMOXOR_W 0xf800707f -#define MATCH_FCVT_D_L 0xd2200053 -#define MASK_FCVT_D_L 0xfff0007f -#define MATCH_FCVT_WU_H 0x5c000053 -#define MASK_FCVT_WU_H 0xfff0007f -#define MATCH_C_SLLI 0x19 -#define MASK_C_SLLI 0x1c1f -#define MATCH_AMOXOR_D 0x2000302f -#define MASK_AMOXOR_D 0xf800707f -#define MATCH_FCVT_WU_S 0xc0100053 -#define MASK_FCVT_WU_S 0xfff0007f -#define MATCH_CUSTOM3_RD 0x407b -#define MASK_CUSTOM3_RD 0x707f -#define MATCH_FMAX_H 0xcc000053 -#define MASK_FMAX_H 0xfe00707f -#define MATCH_VENQCNT 0x1000302b -#define MASK_VENQCNT 0xfe007fff -#define MATCH_VLBU 0x800205b -#define MASK_VLBU 0xfff0707f -#define MATCH_VLHU 0xa00205b -#define MASK_VLHU 0xfff0707f -#define MATCH_C_SW 0xd -#define MASK_C_SW 0x1f -#define MATCH_C_SD 0xc -#define MASK_C_SD 0x1f -#define MATCH_C_OR3 0x21c -#define MASK_C_OR3 0x31f -#define MATCH_C_AND3 0x31c -#define MASK_C_AND3 0x31f -#define MATCH_VFSSEGSTW 0x1400307b -#define MASK_VFSSEGSTW 0x1e00707f -#define MATCH_SLT 0x2033 -#define MASK_SLT 0xfe00707f -#define MATCH_AMOOR_D 0x4000302f -#define MASK_AMOOR_D 0xf800707f +#define MATCH_MULH 0x2001033 +#define MASK_MULH 0xfe00707f +#define MATCH_MULHSU 0x2002033 +#define MASK_MULHSU 0xfe00707f +#define MATCH_MULHU 0x2003033 +#define MASK_MULHU 0xfe00707f +#define MATCH_DIV 0x2004033 +#define MASK_DIV 0xfe00707f +#define MATCH_DIVU 0x2005033 +#define MASK_DIVU 0xfe00707f +#define MATCH_REM 0x2006033 +#define MASK_REM 0xfe00707f #define MATCH_REMU 0x2007033 #define MASK_REMU 0xfe00707f +#define MATCH_MULW 0x200003b +#define MASK_MULW 0xfe00707f +#define MATCH_DIVW 0x200403b +#define MASK_DIVW 0xfe00707f +#define MATCH_DIVUW 0x200503b +#define MASK_DIVUW 0xfe00707f #define MATCH_REMW 0x200603b #define MASK_REMW 0xfe00707f -#define MATCH_SLL 0x1033 -#define MASK_SLL 0xfe00707f -#define MATCH_VFSSEGSTD 0x1600307b -#define MASK_VFSSEGSTD 0x1e00707f +#define MATCH_REMUW 0x200703b +#define MASK_REMUW 0xfe00707f +#define MATCH_AMOADD_W 0x202f +#define MASK_AMOADD_W 0xf800707f +#define MATCH_AMOXOR_W 0x2000202f +#define MASK_AMOXOR_W 0xf800707f #define MATCH_AMOOR_W 0x4000202f #define MASK_AMOOR_W 0xf800707f -#define MATCH_CUSTOM2_RS1_RS2 0x305b -#define MASK_CUSTOM2_RS1_RS2 0x707f -#define MATCH_VF 0x10202b -#define MASK_VF 0x1f0707f -#define MATCH_VFMVV 0x1000002b -#define MASK_VFMVV 0xfff0707f -#define MATCH_VFLSEGSTW 0x1400305b -#define MASK_VFLSEGSTW 0x1e00707f -#define MATCH_VXCPTRESTORE 0x200302b -#define MASK_VXCPTRESTORE 0xfff07fff -#define MATCH_VXCPTHOLD 0x800302b -#define MASK_VXCPTHOLD 0xfff07fff -#define MATCH_SLTIU 0x3013 -#define MASK_SLTIU 0x707f -#define MATCH_VFLSEGSTD 0x1600305b -#define MASK_VFLSEGSTD 0x1e00707f -#define MATCH_VFLD 0x1600205b -#define MASK_VFLD 0xfff0707f -#define MATCH_FMADD_S 0x43 -#define MASK_FMADD_S 0x600007f -#define MATCH_VFLW 0x1400205b -#define MASK_VFLW 0xfff0707f -#define MATCH_FMADD_D 0x2000043 -#define MASK_FMADD_D 0x600007f -#define MATCH_FMADD_H 0x4000043 -#define MASK_FMADD_H 0x600007f -#define MATCH_SRET 0x10000073 +#define MATCH_AMOAND_W 0x6000202f +#define MASK_AMOAND_W 0xf800707f +#define MATCH_AMOMIN_W 0x8000202f +#define MASK_AMOMIN_W 0xf800707f +#define MATCH_AMOMAX_W 0xa000202f +#define MASK_AMOMAX_W 0xf800707f +#define MATCH_AMOMINU_W 0xc000202f +#define MASK_AMOMINU_W 0xf800707f +#define MATCH_AMOMAXU_W 0xe000202f +#define MASK_AMOMAXU_W 0xf800707f +#define MATCH_AMOSWAP_W 0x800202f +#define MASK_AMOSWAP_W 0xf800707f +#define MATCH_LR_W 0x1000202f +#define MASK_LR_W 0xf9f0707f +#define MATCH_SC_W 0x1800202f +#define MASK_SC_W 0xf800707f +#define MATCH_AMOADD_D 0x302f +#define MASK_AMOADD_D 0xf800707f +#define MATCH_AMOXOR_D 0x2000302f +#define MASK_AMOXOR_D 0xf800707f +#define MATCH_AMOOR_D 0x4000302f +#define MASK_AMOOR_D 0xf800707f +#define MATCH_AMOAND_D 0x6000302f +#define MASK_AMOAND_D 0xf800707f +#define MATCH_AMOMIN_D 0x8000302f +#define MASK_AMOMIN_D 0xf800707f +#define MATCH_AMOMAX_D 0xa000302f +#define MASK_AMOMAX_D 0xf800707f +#define MATCH_AMOMINU_D 0xc000302f +#define MASK_AMOMINU_D 0xf800707f +#define MATCH_AMOMAXU_D 0xe000302f +#define MASK_AMOMAXU_D 0xf800707f +#define MATCH_AMOSWAP_D 0x800302f +#define MASK_AMOSWAP_D 0xf800707f +#define MATCH_LR_D 0x1000302f +#define MASK_LR_D 0xf9f0707f +#define MATCH_SC_D 0x1800302f +#define MASK_SC_D 0xf800707f +#define MATCH_ECALL 0x73 +#define MASK_ECALL 0xffffffff +#define MATCH_EBREAK 0x100073 +#define MASK_EBREAK 0xffffffff +#define MATCH_URET 0x200073 +#define MASK_URET 0xffffffff +#define MATCH_SRET 0x10200073 #define MASK_SRET 0xffffffff -#define MATCH_VSSEGW 0x400207b -#define MASK_VSSEGW 0x1ff0707f -#define MATCH_CUSTOM0_RD_RS1 0x600b -#define MASK_CUSTOM0_RD_RS1 0x707f -#define MATCH_VSSEGH 0x200207b -#define MASK_VSSEGH 0x1ff0707f -#define MATCH_FRCSR 0x302073 -#define MASK_FRCSR 0xfffff07f -#define MATCH_VSSEGD 0x600207b -#define MASK_VSSEGD 0x1ff0707f -#define MATCH_VSSEGB 0x207b -#define MASK_VSSEGB 0x1ff0707f -#define MATCH_FMIN_H 0xc4000053 -#define MASK_FMIN_H 0xfe00707f -#define MATCH_FMIN_D 0x2a000053 -#define MASK_FMIN_D 0xfe00707f -#define MATCH_BLTU 0x6063 -#define MASK_BLTU 0x707f +#define MATCH_HRET 0x20200073 +#define MASK_HRET 0xffffffff +#define MATCH_MRET 0x30200073 +#define MASK_MRET 0xffffffff +#define MATCH_DRET 0x7b200073 +#define MASK_DRET 0xffffffff +#define MATCH_SFENCE_VM 0x10400073 +#define MASK_SFENCE_VM 0xfff07fff +#define MATCH_SFENCE_VMA 0x12000073 +#define MASK_SFENCE_VMA 0xfe007fff +#define MATCH_WFI 0x10500073 +#define MASK_WFI 0xffffffff +#define MATCH_CSRRW 0x1073 +#define MASK_CSRRW 0x707f +#define MATCH_CSRRS 0x2073 +#define MASK_CSRRS 0x707f +#define MATCH_CSRRC 0x3073 +#define MASK_CSRRC 0x707f +#define MATCH_CSRRWI 0x5073 +#define MASK_CSRRWI 0x707f +#define MATCH_CSRRSI 0x6073 +#define MASK_CSRRSI 0x707f +#define MATCH_CSRRCI 0x7073 +#define MASK_CSRRCI 0x707f +#define MATCH_FADD_S 0x53 +#define MASK_FADD_S 0xfe00007f +#define MATCH_FSUB_S 0x8000053 +#define MASK_FSUB_S 0xfe00007f +#define MATCH_FMUL_S 0x10000053 +#define MASK_FMUL_S 0xfe00007f +#define MATCH_FDIV_S 0x18000053 +#define MASK_FDIV_S 0xfe00007f +#define MATCH_FSGNJ_S 0x20000053 +#define MASK_FSGNJ_S 0xfe00707f +#define MATCH_FSGNJN_S 0x20001053 +#define MASK_FSGNJN_S 0xfe00707f +#define MATCH_FSGNJX_S 0x20002053 +#define MASK_FSGNJX_S 0xfe00707f #define MATCH_FMIN_S 0x28000053 #define MASK_FMIN_S 0xfe00707f -#define MATCH_SRLI_RV32 0x5013 -#define MASK_SRLI_RV32 0xfe00707f -#define MATCH_SLLIW 0x101b -#define MASK_SLLIW 0xfe00707f #define MATCH_FMAX_S 0x28001053 #define MASK_FMAX_S 0xfe00707f -#define MATCH_FCVT_D_H 0x8c000053 -#define MASK_FCVT_D_H 0xfff0007f -#define MATCH_FCVT_D_W 0xd2000053 -#define MASK_FCVT_D_W 0xfff0007f -#define MATCH_ADD 0x33 -#define MASK_ADD 0xfe00707f -#define MATCH_FCVT_D_S 0x42000053 -#define MASK_FCVT_D_S 0xfff0007f -#define MATCH_FMAX_D 0x2a001053 -#define MASK_FMAX_D 0xfe00707f -#define MATCH_BNE 0x1063 -#define MASK_BNE 0x707f -#define MATCH_CUSTOM1_RD 0x402b -#define MASK_CUSTOM1_RD 0x707f -#define MATCH_FSRM 0x201073 -#define MASK_FSRM 0xfff0707f +#define MATCH_FSQRT_S 0x58000053 +#define MASK_FSQRT_S 0xfff0007f +#define MATCH_FADD_D 0x2000053 +#define MASK_FADD_D 0xfe00007f +#define MATCH_FSUB_D 0xa000053 +#define MASK_FSUB_D 0xfe00007f +#define MATCH_FMUL_D 0x12000053 +#define MASK_FMUL_D 0xfe00007f #define MATCH_FDIV_D 0x1a000053 #define MASK_FDIV_D 0xfe00007f -#define MATCH_VSW 0x400207b -#define MASK_VSW 0xfff0707f +#define MATCH_FSGNJ_D 0x22000053 +#define MASK_FSGNJ_D 0xfe00707f +#define MATCH_FSGNJN_D 0x22001053 +#define MASK_FSGNJN_D 0xfe00707f +#define MATCH_FSGNJX_D 0x22002053 +#define MASK_FSGNJX_D 0xfe00707f +#define MATCH_FMIN_D 0x2a000053 +#define MASK_FMIN_D 0xfe00707f +#define MATCH_FMAX_D 0x2a001053 +#define MASK_FMAX_D 0xfe00707f +#define MATCH_FCVT_S_D 0x40100053 +#define MASK_FCVT_S_D 0xfff0007f +#define MATCH_FCVT_D_S 0x42000053 +#define MASK_FCVT_D_S 0xfff0007f +#define MATCH_FSQRT_D 0x5a000053 +#define MASK_FSQRT_D 0xfff0007f +#define MATCH_FADD_Q 0x6000053 +#define MASK_FADD_Q 0xfe00007f +#define MATCH_FSUB_Q 0xe000053 +#define MASK_FSUB_Q 0xfe00007f +#define MATCH_FMUL_Q 0x16000053 +#define MASK_FMUL_Q 0xfe00007f +#define MATCH_FDIV_Q 0x1e000053 +#define MASK_FDIV_Q 0xfe00007f +#define MATCH_FSGNJ_Q 0x26000053 +#define MASK_FSGNJ_Q 0xfe00707f +#define MATCH_FSGNJN_Q 0x26001053 +#define MASK_FSGNJN_Q 0xfe00707f +#define MATCH_FSGNJX_Q 0x26002053 +#define MASK_FSGNJX_Q 0xfe00707f +#define MATCH_FMIN_Q 0x2e000053 +#define MASK_FMIN_Q 0xfe00707f +#define MATCH_FMAX_Q 0x2e001053 +#define MASK_FMAX_Q 0xfe00707f +#define MATCH_FCVT_S_Q 0x40300053 +#define MASK_FCVT_S_Q 0xfff0007f +#define MATCH_FCVT_Q_S 0x46000053 +#define MASK_FCVT_Q_S 0xfff0007f +#define MATCH_FCVT_D_Q 0x42300053 +#define MASK_FCVT_D_Q 0xfff0007f +#define MATCH_FCVT_Q_D 0x46100053 +#define MASK_FCVT_Q_D 0xfff0007f +#define MATCH_FSQRT_Q 0x5e000053 +#define MASK_FSQRT_Q 0xfff0007f +#define MATCH_FLE_S 0xa0000053 +#define MASK_FLE_S 0xfe00707f +#define MATCH_FLT_S 0xa0001053 +#define MASK_FLT_S 0xfe00707f +#define MATCH_FEQ_S 0xa0002053 +#define MASK_FEQ_S 0xfe00707f +#define MATCH_FLE_D 0xa2000053 +#define MASK_FLE_D 0xfe00707f +#define MATCH_FLT_D 0xa2001053 +#define MASK_FLT_D 0xfe00707f +#define MATCH_FEQ_D 0xa2002053 +#define MASK_FEQ_D 0xfe00707f +#define MATCH_FLE_Q 0xa6000053 +#define MASK_FLE_Q 0xfe00707f +#define MATCH_FLT_Q 0xa6001053 +#define MASK_FLT_Q 0xfe00707f +#define MATCH_FEQ_Q 0xa6002053 +#define MASK_FEQ_Q 0xfe00707f +#define MATCH_FCVT_W_S 0xc0000053 +#define MASK_FCVT_W_S 0xfff0007f +#define MATCH_FCVT_WU_S 0xc0100053 +#define MASK_FCVT_WU_S 0xfff0007f #define MATCH_FCVT_L_S 0xc0200053 #define MASK_FCVT_L_S 0xfff0007f -#define MATCH_FDIV_H 0x1c000053 -#define MASK_FDIV_H 0xfe00007f -#define MATCH_VSB 0x207b -#define MASK_VSB 0xfff0707f -#define MATCH_FDIV_S 0x18000053 -#define MASK_FDIV_S 0xfe00007f -#define MATCH_FSRMI 0x205073 -#define MASK_FSRMI 0xfff0707f -#define MATCH_FCVT_L_H 0x44000053 -#define MASK_FCVT_L_H 0xfff0007f -#define MATCH_VSH 0x200207b -#define MASK_VSH 0xfff0707f +#define MATCH_FCVT_LU_S 0xc0300053 +#define MASK_FCVT_LU_S 0xfff0007f +#define MATCH_FMV_X_S 0xe0000053 +#define MASK_FMV_X_S 0xfff0707f +#define MATCH_FCLASS_S 0xe0001053 +#define MASK_FCLASS_S 0xfff0707f +#define MATCH_FCVT_W_D 0xc2000053 +#define MASK_FCVT_W_D 0xfff0007f +#define MATCH_FCVT_WU_D 0xc2100053 +#define MASK_FCVT_WU_D 0xfff0007f #define MATCH_FCVT_L_D 0xc2200053 #define MASK_FCVT_L_D 0xfff0007f -#define MATCH_FCVT_H_S 0x90000053 -#define MASK_FCVT_H_S 0xfff0007f -#define MATCH_SCALL 0x73 -#define MASK_SCALL 0xffffffff -#define MATCH_FSFLAGSI 0x105073 -#define MASK_FSFLAGSI 0xfff0707f -#define MATCH_FCVT_H_W 0x74000053 -#define MASK_FCVT_H_W 0xfff0007f -#define MATCH_FCVT_H_L 0x64000053 -#define MASK_FCVT_H_L 0xfff0007f -#define MATCH_SRLIW 0x501b -#define MASK_SRLIW 0xfe00707f -#define MATCH_FCVT_S_LU 0xd0300053 -#define MASK_FCVT_S_LU 0xfff0007f -#define MATCH_FCVT_H_D 0x92000053 -#define MASK_FCVT_H_D 0xfff0007f -#define MATCH_SBREAK 0x100073 -#define MASK_SBREAK 0xffffffff -#define MATCH_RDINSTRETH 0xc8202073 -#define MASK_RDINSTRETH 0xfffff07f -#define MATCH_SRA 0x40005033 -#define MASK_SRA 0xfe00707f -#define MATCH_BGE 0x5063 -#define MASK_BGE 0x707f -#define MATCH_SRL 0x5033 -#define MASK_SRL 0xfe00707f -#define MATCH_VENQCMD 0xa00302b -#define MASK_VENQCMD 0xfe007fff -#define MATCH_OR 0x6033 -#define MASK_OR 0xfe00707f -#define MATCH_SUBW 0x4000003b -#define MASK_SUBW 0xfe00707f +#define MATCH_FCVT_LU_D 0xc2300053 +#define MASK_FCVT_LU_D 0xfff0007f #define MATCH_FMV_X_D 0xe2000053 #define MASK_FMV_X_D 0xfff0707f -#define MATCH_RDTIME 0xc0102073 -#define MASK_RDTIME 0xfffff07f -#define MATCH_AMOADD_D 0x302f -#define MASK_AMOADD_D 0xf800707f -#define MATCH_AMOMAX_W 0xa000202f -#define MASK_AMOMAX_W 0xf800707f -#define MATCH_C_MOVE 0x2 -#define MASK_C_MOVE 0x801f -#define MATCH_FMOVN 0x6007077 -#define MASK_FMOVN 0xfe00707f -#define MATCH_C_FSW 0x16 -#define MASK_C_FSW 0x1f -#define MATCH_AMOADD_W 0x202f -#define MASK_AMOADD_W 0xf800707f -#define MATCH_AMOMAX_D 0xa000302f -#define MASK_AMOMAX_D 0xf800707f -#define MATCH_FMOVZ 0x4007077 -#define MASK_FMOVZ 0xfe00707f -#define MATCH_CUSTOM1_RS1_RS2 0x302b -#define MASK_CUSTOM1_RS1_RS2 0x707f -#define MATCH_FMV_X_H 0xe4000053 -#define MASK_FMV_X_H 0xfff0707f -#define MATCH_VSD 0x600207b -#define MASK_VSD 0xfff0707f -#define MATCH_VLSEGSTW 0x400305b -#define MASK_VLSEGSTW 0x1e00707f -#define MATCH_C_ADDI 0x1 -#define MASK_C_ADDI 0x1f -#define MATCH_C_SLLIW 0x1819 -#define MASK_C_SLLIW 0x1c1f -#define MATCH_VLSEGSTB 0x305b -#define MASK_VLSEGSTB 0x1e00707f -#define MATCH_VLSEGSTD 0x600305b -#define MASK_VLSEGSTD 0x1e00707f -#define MATCH_VLSEGSTH 0x200305b -#define MASK_VLSEGSTH 0x1e00707f -#define MATCH_MULHU 0x2003033 -#define MASK_MULHU 0xfe00707f -#define MATCH_AMOMIN_W 0x8000202f -#define MASK_AMOMIN_W 0xf800707f -#define MATCH_C_SLLI32 0x419 -#define MASK_C_SLLI32 0x1c1f -#define MATCH_C_ADD3 0x1c -#define MASK_C_ADD3 0x31f -#define MATCH_VGETVL 0x200400b -#define MASK_VGETVL 0xfffff07f -#define MATCH_AMOMIN_D 0x8000302f -#define MASK_AMOMIN_D 0xf800707f -#define MATCH_FCVT_W_H 0x54000053 -#define MASK_FCVT_W_H 0xfff0007f -#define MATCH_VLSEGB 0x205b -#define MASK_VLSEGB 0x1ff0707f -#define MATCH_FSD 0x3027 -#define MASK_FSD 0x707f -#define MATCH_VLSEGD 0x600205b -#define MASK_VLSEGD 0x1ff0707f -#define MATCH_FSH 0x1027 -#define MASK_FSH 0x707f -#define MATCH_VLSEGH 0x200205b -#define MASK_VLSEGH 0x1ff0707f -#define MATCH_C_SUB 0x801a -#define MASK_C_SUB 0x801f -#define MATCH_VLSEGW 0x400205b -#define MASK_VLSEGW 0x1ff0707f +#define MATCH_FCLASS_D 0xe2001053 +#define MASK_FCLASS_D 0xfff0707f +#define MATCH_FCVT_W_Q 0xc6000053 +#define MASK_FCVT_W_Q 0xfff0007f +#define MATCH_FCVT_WU_Q 0xc6100053 +#define MASK_FCVT_WU_Q 0xfff0007f +#define MATCH_FCVT_L_Q 0xc6200053 +#define MASK_FCVT_L_Q 0xfff0007f +#define MATCH_FCVT_LU_Q 0xc6300053 +#define MASK_FCVT_LU_Q 0xfff0007f +#define MATCH_FMV_X_Q 0xe6000053 +#define MASK_FMV_X_Q 0xfff0707f +#define MATCH_FCLASS_Q 0xe6001053 +#define MASK_FCLASS_Q 0xfff0707f +#define MATCH_FCVT_S_W 0xd0000053 +#define MASK_FCVT_S_W 0xfff0007f +#define MATCH_FCVT_S_WU 0xd0100053 +#define MASK_FCVT_S_WU 0xfff0007f +#define MATCH_FCVT_S_L 0xd0200053 +#define MASK_FCVT_S_L 0xfff0007f +#define MATCH_FCVT_S_LU 0xd0300053 +#define MASK_FCVT_S_LU 0xfff0007f +#define MATCH_FMV_S_X 0xf0000053 +#define MASK_FMV_S_X 0xfff0707f +#define MATCH_FCVT_D_W 0xd2000053 +#define MASK_FCVT_D_W 0xfff0007f +#define MATCH_FCVT_D_WU 0xd2100053 +#define MASK_FCVT_D_WU 0xfff0007f +#define MATCH_FCVT_D_L 0xd2200053 +#define MASK_FCVT_D_L 0xfff0007f +#define MATCH_FCVT_D_LU 0xd2300053 +#define MASK_FCVT_D_LU 0xfff0007f +#define MATCH_FMV_D_X 0xf2000053 +#define MASK_FMV_D_X 0xfff0707f +#define MATCH_FCVT_Q_W 0xd6000053 +#define MASK_FCVT_Q_W 0xfff0007f +#define MATCH_FCVT_Q_WU 0xd6100053 +#define MASK_FCVT_Q_WU 0xfff0007f +#define MATCH_FCVT_Q_L 0xd6200053 +#define MASK_FCVT_Q_L 0xfff0007f +#define MATCH_FCVT_Q_LU 0xd6300053 +#define MASK_FCVT_Q_LU 0xfff0007f +#define MATCH_FMV_Q_X 0xf6000053 +#define MASK_FMV_Q_X 0xfff0707f +#define MATCH_FLW 0x2007 +#define MASK_FLW 0x707f +#define MATCH_FLD 0x3007 +#define MASK_FLD 0x707f +#define MATCH_FLQ 0x4007 +#define MASK_FLQ 0x707f #define MATCH_FSW 0x2027 #define MASK_FSW 0x707f -#define MATCH_C_J 0x8002 -#define MASK_C_J 0x801f +#define MATCH_FSD 0x3027 +#define MASK_FSD 0x707f +#define MATCH_FSQ 0x4027 +#define MASK_FSQ 0x707f +#define MATCH_FMADD_S 0x43 +#define MASK_FMADD_S 0x600007f +#define MATCH_FMSUB_S 0x47 +#define MASK_FMSUB_S 0x600007f +#define MATCH_FNMSUB_S 0x4b +#define MASK_FNMSUB_S 0x600007f +#define MATCH_FNMADD_S 0x4f +#define MASK_FNMADD_S 0x600007f +#define MATCH_FMADD_D 0x2000043 +#define MASK_FMADD_D 0x600007f +#define MATCH_FMSUB_D 0x2000047 +#define MASK_FMSUB_D 0x600007f +#define MATCH_FNMSUB_D 0x200004b +#define MASK_FNMSUB_D 0x600007f +#define MATCH_FNMADD_D 0x200004f +#define MASK_FNMADD_D 0x600007f +#define MATCH_FMADD_Q 0x6000043 +#define MASK_FMADD_Q 0x600007f +#define MATCH_FMSUB_Q 0x6000047 +#define MASK_FMSUB_Q 0x600007f +#define MATCH_FNMSUB_Q 0x600004b +#define MASK_FNMSUB_Q 0x600007f +#define MATCH_FNMADD_Q 0x600004f +#define MASK_FNMADD_Q 0x600007f +#define MATCH_C_ADDI4SPN 0x0 +#define MASK_C_ADDI4SPN 0xe003 +#define MATCH_C_FLD 0x2000 +#define MASK_C_FLD 0xe003 +#define MATCH_C_LW 0x4000 +#define MASK_C_LW 0xe003 +#define MATCH_C_FLW 0x6000 +#define MASK_C_FLW 0xe003 +#define MATCH_C_FSD 0xa000 +#define MASK_C_FSD 0xe003 +#define MATCH_C_SW 0xc000 +#define MASK_C_SW 0xe003 +#define MATCH_C_FSW 0xe000 +#define MASK_C_FSW 0xe003 +#define MATCH_C_ADDI 0x1 +#define MASK_C_ADDI 0xe003 +#define MATCH_C_JAL 0x2001 +#define MASK_C_JAL 0xe003 +#define MATCH_C_LI 0x4001 +#define MASK_C_LI 0xe003 +#define MATCH_C_LUI 0x6001 +#define MASK_C_LUI 0xe003 +#define MATCH_C_SRLI 0x8001 +#define MASK_C_SRLI 0xec03 +#define MATCH_C_SRLI64 0x8001 +#define MASK_C_SRLI64 0xfc7f +#define MATCH_C_SRAI 0x8401 +#define MASK_C_SRAI 0xec03 +#define MATCH_C_SRAI64 0x8401 +#define MASK_C_SRAI64 0xfc7f +#define MATCH_C_ANDI 0x8801 +#define MASK_C_ANDI 0xec03 +#define MATCH_C_SUB 0x8c01 +#define MASK_C_SUB 0xfc63 +#define MATCH_C_XOR 0x8c21 +#define MASK_C_XOR 0xfc63 +#define MATCH_C_OR 0x8c41 +#define MASK_C_OR 0xfc63 +#define MATCH_C_AND 0x8c61 +#define MASK_C_AND 0xfc63 +#define MATCH_C_SUBW 0x9c01 +#define MASK_C_SUBW 0xfc63 +#define MATCH_C_ADDW 0x9c21 +#define MASK_C_ADDW 0xfc63 +#define MATCH_C_J 0xa001 +#define MASK_C_J 0xe003 +#define MATCH_C_BEQZ 0xc001 +#define MASK_C_BEQZ 0xe003 +#define MATCH_C_BNEZ 0xe001 +#define MASK_C_BNEZ 0xe003 +#define MATCH_C_SLLI 0x2 +#define MASK_C_SLLI 0xe003 +#define MATCH_C_SLLI64 0x2 +#define MASK_C_SLLI64 0xf07f +#define MATCH_C_FLDSP 0x2002 +#define MASK_C_FLDSP 0xe003 +#define MATCH_C_LWSP 0x4002 +#define MASK_C_LWSP 0xe003 +#define MATCH_C_FLWSP 0x6002 +#define MASK_C_FLWSP 0xe003 +#define MATCH_C_MV 0x8002 +#define MASK_C_MV 0xf003 +#define MATCH_C_ADD 0x9002 +#define MASK_C_ADD 0xf003 +#define MATCH_C_FSDSP 0xa002 +#define MASK_C_FSDSP 0xe003 +#define MATCH_C_SWSP 0xc002 +#define MASK_C_SWSP 0xe003 +#define MATCH_C_FSWSP 0xe002 +#define MASK_C_FSWSP 0xe003 +#define MATCH_C_NOP 0x1 +#define MASK_C_NOP 0xffff +#define MATCH_C_ADDI16SP 0x6101 +#define MASK_C_ADDI16SP 0xef83 +#define MATCH_C_JR 0x8002 +#define MASK_C_JR 0xf07f +#define MATCH_C_JALR 0x9002 +#define MASK_C_JALR 0xf07f +#define MATCH_C_EBREAK 0x9002 +#define MASK_C_EBREAK 0xffff +#define MATCH_C_LD 0x6000 +#define MASK_C_LD 0xe003 +#define MATCH_C_SD 0xe000 +#define MASK_C_SD 0xe003 +#define MATCH_C_ADDIW 0x2001 +#define MASK_C_ADDIW 0xe003 +#define MATCH_C_LDSP 0x6002 +#define MASK_C_LDSP 0xe003 +#define MATCH_C_SDSP 0xe002 +#define MASK_C_SDSP 0xe003 +#define MATCH_CUSTOM0 0xb +#define MASK_CUSTOM0 0x707f +#define MATCH_CUSTOM0_RS1 0x200b +#define MASK_CUSTOM0_RS1 0x707f +#define MATCH_CUSTOM0_RS1_RS2 0x300b +#define MASK_CUSTOM0_RS1_RS2 0x707f +#define MATCH_CUSTOM0_RD 0x400b +#define MASK_CUSTOM0_RD 0x707f +#define MATCH_CUSTOM0_RD_RS1 0x600b +#define MASK_CUSTOM0_RD_RS1 0x707f +#define MATCH_CUSTOM0_RD_RS1_RS2 0x700b +#define MASK_CUSTOM0_RD_RS1_RS2 0x707f +#define MATCH_CUSTOM1 0x2b +#define MASK_CUSTOM1 0x707f +#define MATCH_CUSTOM1_RS1 0x202b +#define MASK_CUSTOM1_RS1 0x707f +#define MATCH_CUSTOM1_RS1_RS2 0x302b +#define MASK_CUSTOM1_RS1_RS2 0x707f +#define MATCH_CUSTOM1_RD 0x402b +#define MASK_CUSTOM1_RD 0x707f +#define MATCH_CUSTOM1_RD_RS1 0x602b +#define MASK_CUSTOM1_RD_RS1 0x707f +#define MATCH_CUSTOM1_RD_RS1_RS2 0x702b +#define MASK_CUSTOM1_RD_RS1_RS2 0x707f +#define MATCH_CUSTOM2 0x5b +#define MASK_CUSTOM2 0x707f +#define MATCH_CUSTOM2_RS1 0x205b +#define MASK_CUSTOM2_RS1 0x707f +#define MATCH_CUSTOM2_RS1_RS2 0x305b +#define MASK_CUSTOM2_RS1_RS2 0x707f +#define MATCH_CUSTOM2_RD 0x405b +#define MASK_CUSTOM2_RD 0x707f +#define MATCH_CUSTOM2_RD_RS1 0x605b +#define MASK_CUSTOM2_RD_RS1 0x707f +#define MATCH_CUSTOM2_RD_RS1_RS2 0x705b +#define MASK_CUSTOM2_RD_RS1_RS2 0x707f +#define MATCH_CUSTOM3 0x7b +#define MASK_CUSTOM3 0x707f +#define MATCH_CUSTOM3_RS1 0x207b +#define MASK_CUSTOM3_RS1 0x707f +#define MATCH_CUSTOM3_RS1_RS2 0x307b +#define MASK_CUSTOM3_RS1_RS2 0x707f +#define MATCH_CUSTOM3_RD 0x407b +#define MASK_CUSTOM3_RD 0x707f +#define MATCH_CUSTOM3_RD_RS1 0x607b +#define MASK_CUSTOM3_RD_RS1 0x707f +#define MATCH_CUSTOM3_RD_RS1_RS2 0x707b +#define MASK_CUSTOM3_RD_RS1_RS2 0x707f +#define CSR_USTATUS 0x0 +#define CSR_UIE 0x4 +#define CSR_UTVEC 0x5 +#define CSR_USCRATCH 0x40 +#define CSR_UEPC 0x41 +#define CSR_UCAUSE 0x42 +#define CSR_UTVAL 0x43 +#define CSR_UIP 0x44 #define CSR_FFLAGS 0x1 #define CSR_FRM 0x2 #define CSR_FCSR 0x3 #define CSR_CYCLE 0xc00 #define CSR_TIME 0xc01 #define CSR_INSTRET 0xc02 -#define CSR_STATS 0xc0 -#define CSR_UARCH0 0xcc0 -#define CSR_UARCH1 0xcc1 -#define CSR_UARCH2 0xcc2 -#define CSR_UARCH3 0xcc3 -#define CSR_UARCH4 0xcc4 -#define CSR_UARCH5 0xcc5 -#define CSR_UARCH6 0xcc6 -#define CSR_UARCH7 0xcc7 -#define CSR_UARCH8 0xcc8 -#define CSR_UARCH9 0xcc9 -#define CSR_UARCH10 0xcca -#define CSR_UARCH11 0xccb -#define CSR_UARCH12 0xccc -#define CSR_UARCH13 0xccd -#define CSR_UARCH14 0xcce -#define CSR_UARCH15 0xccf +#define CSR_HPMCOUNTER3 0xc03 +#define CSR_HPMCOUNTER4 0xc04 +#define CSR_HPMCOUNTER5 0xc05 +#define CSR_HPMCOUNTER6 0xc06 +#define CSR_HPMCOUNTER7 0xc07 +#define CSR_HPMCOUNTER8 0xc08 +#define CSR_HPMCOUNTER9 0xc09 +#define CSR_HPMCOUNTER10 0xc0a +#define CSR_HPMCOUNTER11 0xc0b +#define CSR_HPMCOUNTER12 0xc0c +#define CSR_HPMCOUNTER13 0xc0d +#define CSR_HPMCOUNTER14 0xc0e +#define CSR_HPMCOUNTER15 0xc0f +#define CSR_HPMCOUNTER16 0xc10 +#define CSR_HPMCOUNTER17 0xc11 +#define CSR_HPMCOUNTER18 0xc12 +#define CSR_HPMCOUNTER19 0xc13 +#define CSR_HPMCOUNTER20 0xc14 +#define CSR_HPMCOUNTER21 0xc15 +#define CSR_HPMCOUNTER22 0xc16 +#define CSR_HPMCOUNTER23 0xc17 +#define CSR_HPMCOUNTER24 0xc18 +#define CSR_HPMCOUNTER25 0xc19 +#define CSR_HPMCOUNTER26 0xc1a +#define CSR_HPMCOUNTER27 0xc1b +#define CSR_HPMCOUNTER28 0xc1c +#define CSR_HPMCOUNTER29 0xc1d +#define CSR_HPMCOUNTER30 0xc1e +#define CSR_HPMCOUNTER31 0xc1f +#define CSR_CYCLEH 0xc80 +#define CSR_TIMEH 0xc81 +#define CSR_INSTRETH 0xc82 +#define CSR_HPMCOUNTER3H 0xc83 +#define CSR_HPMCOUNTER4H 0xc84 +#define CSR_HPMCOUNTER5H 0xc85 +#define CSR_HPMCOUNTER6H 0xc86 +#define CSR_HPMCOUNTER7H 0xc87 +#define CSR_HPMCOUNTER8H 0xc88 +#define CSR_HPMCOUNTER9H 0xc89 +#define CSR_HPMCOUNTER10H 0xc8a +#define CSR_HPMCOUNTER11H 0xc8b +#define CSR_HPMCOUNTER12H 0xc8c +#define CSR_HPMCOUNTER13H 0xc8d +#define CSR_HPMCOUNTER14H 0xc8e +#define CSR_HPMCOUNTER15H 0xc8f +#define CSR_HPMCOUNTER16H 0xc90 +#define CSR_HPMCOUNTER17H 0xc91 +#define CSR_HPMCOUNTER18H 0xc92 +#define CSR_HPMCOUNTER19H 0xc93 +#define CSR_HPMCOUNTER20H 0xc94 +#define CSR_HPMCOUNTER21H 0xc95 +#define CSR_HPMCOUNTER22H 0xc96 +#define CSR_HPMCOUNTER23H 0xc97 +#define CSR_HPMCOUNTER24H 0xc98 +#define CSR_HPMCOUNTER25H 0xc99 +#define CSR_HPMCOUNTER26H 0xc9a +#define CSR_HPMCOUNTER27H 0xc9b +#define CSR_HPMCOUNTER28H 0xc9c +#define CSR_HPMCOUNTER29H 0xc9d +#define CSR_HPMCOUNTER30H 0xc9e +#define CSR_HPMCOUNTER31H 0xc9f #define CSR_SSTATUS 0x100 -#define CSR_STVEC 0x101 -#define CSR_STIMECMP 0x121 +#define CSR_SEDELEG 0x102 +#define CSR_SIDELEG 0x103 +#define CSR_SIE 0x104 +#define CSR_STVEC 0x105 +#define CSR_SCOUNTEREN 0x106 #define CSR_SSCRATCH 0x140 #define CSR_SEPC 0x141 -#define CSR_SPTBR 0x188 -#define CSR_SASID 0x189 -#define CSR_SCYCLE 0x900 -#define CSR_STIME 0x901 -#define CSR_SINSTRET 0x902 -#define CSR_SCAUSE 0xd40 -#define CSR_SBADADDR 0xd41 +#define CSR_SCAUSE 0x142 +#define CSR_STVAL 0x143 +#define CSR_SIP 0x144 +#define CSR_SATP 0x180 +#define CSR_MVENDORID 0xf11 +#define CSR_MARCHID 0xf12 +#define CSR_MIMPID 0xf13 +#define CSR_MHARTID 0xf14 #define CSR_MSTATUS 0x300 +#define CSR_MISA 0x301 +#define CSR_MEDELEG 0x302 +#define CSR_MIDELEG 0x303 +#define CSR_MIE 0x304 +#define CSR_MTVEC 0x305 +#define CSR_MCOUNTEREN 0x306 #define CSR_MSCRATCH 0x340 #define CSR_MEPC 0x341 #define CSR_MCAUSE 0x342 -#define CSR_MBADADDR 0x343 -#define CSR_RESET 0x780 -#define CSR_TOHOST 0x781 -#define CSR_FROMHOST 0x782 -#define CSR_SEND_IPI 0x783 -#define CSR_HARTID 0xfc0 -#define CSR_CYCLEH 0xc80 -#define CSR_TIMEH 0xc81 -#define CSR_INSTRETH 0xc82 -#define CSR_SCYCLEH 0x980 -#define CSR_STIMEH 0x981 -#define CSR_SINSTRETH 0x982 +#define CSR_MTVAL 0x343 +#define CSR_MIP 0x344 +#define CSR_PMPCFG0 0x3a0 +#define CSR_PMPCFG1 0x3a1 +#define CSR_PMPCFG2 0x3a2 +#define CSR_PMPCFG3 0x3a3 +#define CSR_PMPADDR0 0x3b0 +#define CSR_PMPADDR1 0x3b1 +#define CSR_PMPADDR2 0x3b2 +#define CSR_PMPADDR3 0x3b3 +#define CSR_PMPADDR4 0x3b4 +#define CSR_PMPADDR5 0x3b5 +#define CSR_PMPADDR6 0x3b6 +#define CSR_PMPADDR7 0x3b7 +#define CSR_PMPADDR8 0x3b8 +#define CSR_PMPADDR9 0x3b9 +#define CSR_PMPADDR10 0x3ba +#define CSR_PMPADDR11 0x3bb +#define CSR_PMPADDR12 0x3bc +#define CSR_PMPADDR13 0x3bd +#define CSR_PMPADDR14 0x3be +#define CSR_PMPADDR15 0x3bf +#define CSR_MCYCLE 0xb00 +#define CSR_MINSTRET 0xb02 +#define CSR_MHPMCOUNTER3 0xb03 +#define CSR_MHPMCOUNTER4 0xb04 +#define CSR_MHPMCOUNTER5 0xb05 +#define CSR_MHPMCOUNTER6 0xb06 +#define CSR_MHPMCOUNTER7 0xb07 +#define CSR_MHPMCOUNTER8 0xb08 +#define CSR_MHPMCOUNTER9 0xb09 +#define CSR_MHPMCOUNTER10 0xb0a +#define CSR_MHPMCOUNTER11 0xb0b +#define CSR_MHPMCOUNTER12 0xb0c +#define CSR_MHPMCOUNTER13 0xb0d +#define CSR_MHPMCOUNTER14 0xb0e +#define CSR_MHPMCOUNTER15 0xb0f +#define CSR_MHPMCOUNTER16 0xb10 +#define CSR_MHPMCOUNTER17 0xb11 +#define CSR_MHPMCOUNTER18 0xb12 +#define CSR_MHPMCOUNTER19 0xb13 +#define CSR_MHPMCOUNTER20 0xb14 +#define CSR_MHPMCOUNTER21 0xb15 +#define CSR_MHPMCOUNTER22 0xb16 +#define CSR_MHPMCOUNTER23 0xb17 +#define CSR_MHPMCOUNTER24 0xb18 +#define CSR_MHPMCOUNTER25 0xb19 +#define CSR_MHPMCOUNTER26 0xb1a +#define CSR_MHPMCOUNTER27 0xb1b +#define CSR_MHPMCOUNTER28 0xb1c +#define CSR_MHPMCOUNTER29 0xb1d +#define CSR_MHPMCOUNTER30 0xb1e +#define CSR_MHPMCOUNTER31 0xb1f +#define CSR_MCYCLEH 0xb80 +#define CSR_MINSTRETH 0xb82 +#define CSR_MHPMCOUNTER3H 0xb83 +#define CSR_MHPMCOUNTER4H 0xb84 +#define CSR_MHPMCOUNTER5H 0xb85 +#define CSR_MHPMCOUNTER6H 0xb86 +#define CSR_MHPMCOUNTER7H 0xb87 +#define CSR_MHPMCOUNTER8H 0xb88 +#define CSR_MHPMCOUNTER9H 0xb89 +#define CSR_MHPMCOUNTER10H 0xb8a +#define CSR_MHPMCOUNTER11H 0xb8b +#define CSR_MHPMCOUNTER12H 0xb8c +#define CSR_MHPMCOUNTER13H 0xb8d +#define CSR_MHPMCOUNTER14H 0xb8e +#define CSR_MHPMCOUNTER15H 0xb8f +#define CSR_MHPMCOUNTER16H 0xb90 +#define CSR_MHPMCOUNTER17H 0xb91 +#define CSR_MHPMCOUNTER18H 0xb92 +#define CSR_MHPMCOUNTER19H 0xb93 +#define CSR_MHPMCOUNTER20H 0xb94 +#define CSR_MHPMCOUNTER21H 0xb95 +#define CSR_MHPMCOUNTER22H 0xb96 +#define CSR_MHPMCOUNTER23H 0xb97 +#define CSR_MHPMCOUNTER24H 0xb98 +#define CSR_MHPMCOUNTER25H 0xb99 +#define CSR_MHPMCOUNTER26H 0xb9a +#define CSR_MHPMCOUNTER27H 0xb9b +#define CSR_MHPMCOUNTER28H 0xb9c +#define CSR_MHPMCOUNTER29H 0xb9d +#define CSR_MHPMCOUNTER30H 0xb9e +#define CSR_MHPMCOUNTER31H 0xb9f +#define CSR_MHPMEVENT3 0x323 +#define CSR_MHPMEVENT4 0x324 +#define CSR_MHPMEVENT5 0x325 +#define CSR_MHPMEVENT6 0x326 +#define CSR_MHPMEVENT7 0x327 +#define CSR_MHPMEVENT8 0x328 +#define CSR_MHPMEVENT9 0x329 +#define CSR_MHPMEVENT10 0x32a +#define CSR_MHPMEVENT11 0x32b +#define CSR_MHPMEVENT12 0x32c +#define CSR_MHPMEVENT13 0x32d +#define CSR_MHPMEVENT14 0x32e +#define CSR_MHPMEVENT15 0x32f +#define CSR_MHPMEVENT16 0x330 +#define CSR_MHPMEVENT17 0x331 +#define CSR_MHPMEVENT18 0x332 +#define CSR_MHPMEVENT19 0x333 +#define CSR_MHPMEVENT20 0x334 +#define CSR_MHPMEVENT21 0x335 +#define CSR_MHPMEVENT22 0x336 +#define CSR_MHPMEVENT23 0x337 +#define CSR_MHPMEVENT24 0x338 +#define CSR_MHPMEVENT25 0x339 +#define CSR_MHPMEVENT26 0x33a +#define CSR_MHPMEVENT27 0x33b +#define CSR_MHPMEVENT28 0x33c +#define CSR_MHPMEVENT29 0x33d +#define CSR_MHPMEVENT30 0x33e +#define CSR_MHPMEVENT31 0x33f +#define CSR_TSELECT 0x7a0 +#define CSR_TDATA1 0x7a1 +#define CSR_TDATA2 0x7a2 +#define CSR_TDATA3 0x7a3 +#define CSR_DCSR 0x7b0 +#define CSR_DPC 0x7b1 +#define CSR_DSCRATCH 0x7b2 +/* These registers are present in priv spec 1.9.1, dropped in 1.10. */ +#define CSR_HSTATUS 0x200 +#define CSR_HEDELEG 0x202 +#define CSR_HIDELEG 0x203 +#define CSR_HIE 0x204 +#define CSR_HTVEC 0x205 +#define CSR_HSCRATCH 0x240 +#define CSR_HEPC 0x241 +#define CSR_HCAUSE 0x242 +#define CSR_HBADADDR 0x243 +#define CSR_HIP 0x244 +/* CSR_MISA is 0xf10 in 1.9, but 0x301 in 1.9.1. */ +#define CSR_MBASE 0x380 +#define CSR_MBOUND 0x381 +#define CSR_MIBASE 0x382 +#define CSR_MIBOUND 0x383 +#define CSR_MDBASE 0x384 +#define CSR_MDBOUND 0x385 +#define CSR_MUCOUNTEREN 0x320 +#define CSR_MSCOUNTEREN 0x321 +#define CSR_MHCOUNTEREN 0x322 #define CAUSE_MISALIGNED_FETCH 0x0 #define CAUSE_FAULT_FETCH 0x1 #define CAUSE_ILLEGAL_INSTRUCTION 0x2 +#define CAUSE_BREAKPOINT 0x3 #define CAUSE_MISALIGNED_LOAD 0x4 #define CAUSE_FAULT_LOAD 0x5 #define CAUSE_MISALIGNED_STORE 0x6 #define CAUSE_FAULT_STORE 0x7 -#define CAUSE_ECALL 0x8 -#define CAUSE_BREAKPOINT 0x9 +#define CAUSE_USER_ECALL 0x8 +#define CAUSE_SUPERVISOR_ECALL 0x9 +#define CAUSE_HYPERVISOR_ECALL 0xa +#define CAUSE_MACHINE_ECALL 0xb #endif #ifdef DECLARE_INSN -DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2) -DECLARE_INSN(vlsegstwu, MATCH_VLSEGSTWU, MASK_VLSEGSTWU) -DECLARE_INSN(c_lw0, MATCH_C_LW0, MASK_C_LW0) -DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X) -DECLARE_INSN(vlh, MATCH_VLH, MASK_VLH) -DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI) -DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D) -DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD) -DECLARE_INSN(vld, MATCH_VLD, MASK_VLD) -DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S) -DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW) -DECLARE_INSN(vlw, MATCH_VLW, MASK_VLW) -DECLARE_INSN(vssegstw, MATCH_VSSEGSTW, MASK_VSSEGSTW) -DECLARE_INSN(utidx, MATCH_UTIDX, MASK_UTIDX) -DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW) -DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D) -DECLARE_INSN(vssegstd, MATCH_VSSEGSTD, MASK_VSSEGSTD) -DECLARE_INSN(vssegstb, MATCH_VSSEGSTB, MASK_VSSEGSTB) -DECLARE_INSN(div, MATCH_DIV, MASK_DIV) -DECLARE_INSN(fmv_h_x, MATCH_FMV_H_X, MASK_FMV_H_X) -DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD) +DECLARE_INSN(slli_rv32, MATCH_SLLI_RV32, MASK_SLLI_RV32) +DECLARE_INSN(srli_rv32, MATCH_SRLI_RV32, MASK_SRLI_RV32) +DECLARE_INSN(srai_rv32, MATCH_SRAI_RV32, MASK_SRAI_RV32) +DECLARE_INSN(frflags, MATCH_FRFLAGS, MASK_FRFLAGS) +DECLARE_INSN(fsflags, MATCH_FSFLAGS, MASK_FSFLAGS) +DECLARE_INSN(fsflagsi, MATCH_FSFLAGSI, MASK_FSFLAGSI) DECLARE_INSN(frrm, MATCH_FRRM, MASK_FRRM) -DECLARE_INSN(vfmsv_s, MATCH_VFMSV_S, MASK_VFMSV_S) -DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP) -DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE) -DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S) -DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S) -DECLARE_INSN(fnmsub_h, MATCH_FNMSUB_H, MASK_FNMSUB_H) -DECLARE_INSN(fle_h, MATCH_FLE_H, MASK_FLE_H) -DECLARE_INSN(flw, MATCH_FLW, MASK_FLW) -DECLARE_INSN(vsetvl, MATCH_VSETVL, MASK_VSETVL) -DECLARE_INSN(vfmsv_d, MATCH_VFMSV_D, MASK_VFMSV_D) -DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D) -DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I) -DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D) -DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW) -DECLARE_INSN(xor, MATCH_XOR, MASK_XOR) -DECLARE_INSN(sub, MATCH_SUB, MASK_SUB) -DECLARE_INSN(vsstw, MATCH_VSSTW, MASK_VSSTW) -DECLARE_INSN(vssth, MATCH_VSSTH, MASK_VSSTH) -DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W) -DECLARE_INSN(vsstb, MATCH_VSSTB, MASK_VSSTB) -DECLARE_INSN(vsstd, MATCH_VSSTD, MASK_VSSTD) -DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI) -DECLARE_INSN(rdtimeh, MATCH_RDTIMEH, MASK_RDTIMEH) -DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH) -DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI) -DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU) -DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW) -DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, MASK_CUSTOM1_RD_RS1_RS2) -DECLARE_INSN(venqimm1, MATCH_VENQIMM1, MASK_VENQIMM1) -DECLARE_INSN(venqimm2, MATCH_VENQIMM2, MASK_VENQIMM2) +DECLARE_INSN(fsrm, MATCH_FSRM, MASK_FSRM) +DECLARE_INSN(fsrmi, MATCH_FSRMI, MASK_FSRMI) +DECLARE_INSN(fscsr, MATCH_FSCSR, MASK_FSCSR) +DECLARE_INSN(frcsr, MATCH_FRCSR, MASK_FRCSR) +DECLARE_INSN(rdcycle, MATCH_RDCYCLE, MASK_RDCYCLE) +DECLARE_INSN(rdtime, MATCH_RDTIME, MASK_RDTIME) DECLARE_INSN(rdinstret, MATCH_RDINSTRET, MASK_RDINSTRET) -DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP) -DECLARE_INSN(vlstw, MATCH_VLSTW, MASK_VLSTW) -DECLARE_INSN(vlsth, MATCH_VLSTH, MASK_VLSTH) -DECLARE_INSN(vlstb, MATCH_VLSTB, MASK_VLSTB) -DECLARE_INSN(vlstd, MATCH_VLSTD, MASK_VLSTD) -DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI) -DECLARE_INSN(fmv_x_s, MATCH_FMV_X_S, MASK_FMV_X_S) -DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, MASK_CUSTOM0_RD_RS1_RS2) -DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S) -DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU) -DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1) -DECLARE_INSN(vlsegstbu, MATCH_VLSEGSTBU, MASK_VLSEGSTBU) -DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D) -DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S) -DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI) -DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU) -DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU) -DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D) -DECLARE_INSN(fsub_h, MATCH_FSUB_H, MASK_FSUB_H) -DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW) -DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI) -DECLARE_INSN(vlstbu, MATCH_VLSTBU, MASK_VLSTBU) -DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU) -DECLARE_INSN(flh, MATCH_FLH, MASK_FLH) -DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, MASK_CUSTOM2_RD_RS1_RS2) -DECLARE_INSN(fld, MATCH_FLD, MASK_FLD) -DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S) -DECLARE_INSN(fcvt_h_lu, MATCH_FCVT_H_LU, MASK_FCVT_H_LU) -DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0) -DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1) -DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2) -DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3) -DECLARE_INSN(vxcptsave, MATCH_VXCPTSAVE, MASK_VXCPTSAVE) -DECLARE_INSN(vmsv, MATCH_VMSV, MASK_VMSV) -DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S) +DECLARE_INSN(rdcycleh, MATCH_RDCYCLEH, MASK_RDCYCLEH) +DECLARE_INSN(rdtimeh, MATCH_RDTIMEH, MASK_RDTIMEH) +DECLARE_INSN(rdinstreth, MATCH_RDINSTRETH, MASK_RDINSTRETH) +DECLARE_INSN(scall, MATCH_SCALL, MASK_SCALL) +DECLARE_INSN(sbreak, MATCH_SBREAK, MASK_SBREAK) +DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ) +DECLARE_INSN(bne, MATCH_BNE, MASK_BNE) +DECLARE_INSN(blt, MATCH_BLT, MASK_BLT) +DECLARE_INSN(bge, MATCH_BGE, MASK_BGE) +DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU) +DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU) +DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR) +DECLARE_INSN(jal, MATCH_JAL, MASK_JAL) +DECLARE_INSN(lui, MATCH_LUI, MASK_LUI) DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC) -DECLARE_INSN(frflags, MATCH_FRFLAGS, MASK_FRFLAGS) -DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D) -DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI) -DECLARE_INSN(fadd_h, MATCH_FADD_H, MASK_FADD_H) -DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S) -DECLARE_INSN(vxcptkill, MATCH_VXCPTKILL, MASK_VXCPTKILL) -DECLARE_INSN(stop, MATCH_STOP, MASK_STOP) -DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S) -DECLARE_INSN(fsgnjn_h, MATCH_FSGNJN_H, MASK_FSGNJN_H) -DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D) +DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI) +DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI) +DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI) +DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU) DECLARE_INSN(xori, MATCH_XORI, MASK_XORI) -DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU) -DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D) -DECLARE_INSN(fsqrt_h, MATCH_FSQRT_H, MASK_FSQRT_H) -DECLARE_INSN(vssegsth, MATCH_VSSEGSTH, MASK_VSSEGSTH) -DECLARE_INSN(sw, MATCH_SW, MASK_SW) -DECLARE_INSN(vlstwu, MATCH_VLSTWU, MASK_VLSTWU) -DECLARE_INSN(vfssegw, MATCH_VFSSEGW, MASK_VFSSEGW) -DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU) -DECLARE_INSN(sh, MATCH_SH, MASK_SH) -DECLARE_INSN(fmsub_h, MATCH_FMSUB_H, MASK_FMSUB_H) -DECLARE_INSN(vxcptaux, MATCH_VXCPTAUX, MASK_VXCPTAUX) -DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D) -DECLARE_INSN(vfssegd, MATCH_VFSSEGD, MASK_VFSSEGD) -DECLARE_INSN(vlseghu, MATCH_VLSEGHU, MASK_VLSEGHU) -DECLARE_INSN(movn, MATCH_MOVN, MASK_MOVN) -DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1) -DECLARE_INSN(vlsthu, MATCH_VLSTHU, MASK_VLSTHU) -DECLARE_INSN(movz, MATCH_MOVZ, MASK_MOVZ) -DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW) -DECLARE_INSN(ld, MATCH_LD, MASK_LD) -DECLARE_INSN(lb, MATCH_LB, MASK_LB) -DECLARE_INSN(vlwu, MATCH_VLWU, MASK_VLWU) -DECLARE_INSN(lh, MATCH_LH, MASK_LH) -DECLARE_INSN(lw, MATCH_LW, MASK_LW) -DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC) -DECLARE_INSN(fcvt_lu_h, MATCH_FCVT_LU_H, MASK_FCVT_LU_H) -DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D) -DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU) -DECLARE_INSN(vflstd, MATCH_VFLSTD, MASK_VFLSTD) -DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L) -DECLARE_INSN(fcvt_s_h, MATCH_FCVT_S_H, MASK_FCVT_S_H) -DECLARE_INSN(fscsr, MATCH_FSCSR, MASK_FSCSR) -DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W) -DECLARE_INSN(vflstw, MATCH_VFLSTW, MASK_VFLSTW) -DECLARE_INSN(vxcptevac, MATCH_VXCPTEVAC, MASK_VXCPTEVAC) -DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D) -DECLARE_INSN(fsflags, MATCH_FSFLAGS, MASK_FSFLAGS) DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI) -DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI) -DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W) -DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW) -DECLARE_INSN(vflsegw, MATCH_VFLSEGW, MASK_VFLSEGW) -DECLARE_INSN(c_ld0, MATCH_C_LD0, MASK_C_LD0) -DECLARE_INSN(vlsegbu, MATCH_VLSEGBU, MASK_VLSEGBU) -DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR) -DECLARE_INSN(blt, MATCH_BLT, MASK_BLT) -DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1) -DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S) -DECLARE_INSN(sfence_vm, MATCH_SFENCE_VM, MASK_SFENCE_VM) -DECLARE_INSN(rem, MATCH_REM, MASK_REM) -DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D) -DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S) -DECLARE_INSN(rdcycleh, MATCH_RDCYCLEH, MASK_RDCYCLEH) -DECLARE_INSN(vlsegsthu, MATCH_VLSEGSTHU, MASK_VLSEGSTHU) -DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D) +DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI) DECLARE_INSN(ori, MATCH_ORI, MASK_ORI) -DECLARE_INSN(fmul_h, MATCH_FMUL_H, MASK_FMUL_H) -DECLARE_INSN(vflsegd, MATCH_VFLSEGD, MASK_VFLSEGD) -DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S) -DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D) +DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI) +DECLARE_INSN(add, MATCH_ADD, MASK_ADD) +DECLARE_INSN(sub, MATCH_SUB, MASK_SUB) +DECLARE_INSN(sll, MATCH_SLL, MASK_SLL) +DECLARE_INSN(slt, MATCH_SLT, MASK_SLT) +DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU) +DECLARE_INSN(xor, MATCH_XOR, MASK_XOR) +DECLARE_INSN(srl, MATCH_SRL, MASK_SRL) +DECLARE_INSN(sra, MATCH_SRA, MASK_SRA) +DECLARE_INSN(or, MATCH_OR, MASK_OR) +DECLARE_INSN(and, MATCH_AND, MASK_AND) +DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW) +DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW) +DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW) DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW) -DECLARE_INSN(fsgnjx_h, MATCH_FSGNJX_H, MASK_FSGNJX_H) -DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S) -DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D) -DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1) -DECLARE_INSN(feq_h, MATCH_FEQ_H, MASK_FEQ_H) -DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D) -DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW) -DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W) -DECLARE_INSN(srai_rv32, MATCH_SRAI_RV32, MASK_SRAI_RV32) -DECLARE_INSN(c_srli32, MATCH_C_SRLI32, MASK_C_SRLI32) -DECLARE_INSN(vfsstw, MATCH_VFSSTW, MASK_VFSSTW) -DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD) -DECLARE_INSN(c_beq, MATCH_C_BEQ, MASK_C_BEQ) -DECLARE_INSN(vfsstd, MATCH_VFSSTD, MASK_VFSSTD) -DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1) -DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D) -DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W) -DECLARE_INSN(fcvt_h_wu, MATCH_FCVT_H_WU, MASK_FCVT_H_WU) -DECLARE_INSN(vmvv, MATCH_VMVV, MASK_VMVV) +DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW) +DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW) DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW) -DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI) -DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ) -DECLARE_INSN(and, MATCH_AND, MASK_AND) +DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW) +DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW) +DECLARE_INSN(lb, MATCH_LB, MASK_LB) +DECLARE_INSN(lh, MATCH_LH, MASK_LH) +DECLARE_INSN(lw, MATCH_LW, MASK_LW) +DECLARE_INSN(ld, MATCH_LD, MASK_LD) DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU) -DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S) -DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S) -DECLARE_INSN(c_sub3, MATCH_C_SUB3, MASK_C_SUB3) -DECLARE_INSN(fsgnj_h, MATCH_FSGNJ_H, MASK_FSGNJ_H) -DECLARE_INSN(vlb, MATCH_VLB, MASK_VLB) -DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW) -DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2) -DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D) -DECLARE_INSN(vlsegwu, MATCH_VLSEGWU, MASK_VLSEGWU) -DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU) -DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1) -DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D) -DECLARE_INSN(vfsw, MATCH_VFSW, MASK_VFSW) -DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D) +DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU) +DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU) DECLARE_INSN(sb, MATCH_SB, MASK_SB) -DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W) -DECLARE_INSN(vfsd, MATCH_VFSD, MASK_VFSD) -DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1) +DECLARE_INSN(sh, MATCH_SH, MASK_SH) +DECLARE_INSN(sw, MATCH_SW, MASK_SW) DECLARE_INSN(sd, MATCH_SD, MASK_SD) -DECLARE_INSN(fmv_s_x, MATCH_FMV_S_X, MASK_FMV_S_X) -DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW) -DECLARE_INSN(jal, MATCH_JAL, MASK_JAL) -DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD) -DECLARE_INSN(rdcycle, MATCH_RDCYCLE, MASK_RDCYCLE) -DECLARE_INSN(c_bne, MATCH_C_BNE, MASK_C_BNE) -DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD) -DECLARE_INSN(vxcptcause, MATCH_VXCPTCAUSE, MASK_VXCPTCAUSE) -DECLARE_INSN(vgetcfg, MATCH_VGETCFG, MASK_VGETCFG) -DECLARE_INSN(lui, MATCH_LUI, MASK_LUI) -DECLARE_INSN(vsetcfg, MATCH_VSETCFG, MASK_VSETCFG) -DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP) -DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP) -DECLARE_INSN(fnmadd_h, MATCH_FNMADD_H, MASK_FNMADD_H) -DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2) -DECLARE_INSN(slli_rv32, MATCH_SLLI_RV32, MASK_SLLI_RV32) +DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE) +DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I) DECLARE_INSN(mul, MATCH_MUL, MASK_MUL) -DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI) -DECLARE_INSN(c_srai32, MATCH_C_SRAI32, MASK_C_SRAI32) -DECLARE_INSN(flt_h, MATCH_FLT_H, MASK_FLT_H) -DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI) -DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D) -DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D) -DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW) -DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS) -DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S) -DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW) -DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W) -DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD) -DECLARE_INSN(mrts, MATCH_MRTS, MASK_MRTS) -DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D) -DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W) -DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L) -DECLARE_INSN(fcvt_wu_h, MATCH_FCVT_WU_H, MASK_FCVT_WU_H) -DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI) -DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D) -DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S) -DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD) -DECLARE_INSN(fmax_h, MATCH_FMAX_H, MASK_FMAX_H) -DECLARE_INSN(venqcnt, MATCH_VENQCNT, MASK_VENQCNT) -DECLARE_INSN(vlbu, MATCH_VLBU, MASK_VLBU) -DECLARE_INSN(vlhu, MATCH_VLHU, MASK_VLHU) -DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW) -DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD) -DECLARE_INSN(c_or3, MATCH_C_OR3, MASK_C_OR3) -DECLARE_INSN(c_and3, MATCH_C_AND3, MASK_C_AND3) -DECLARE_INSN(vfssegstw, MATCH_VFSSEGSTW, MASK_VFSSEGSTW) -DECLARE_INSN(slt, MATCH_SLT, MASK_SLT) -DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D) +DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH) +DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU) +DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU) +DECLARE_INSN(div, MATCH_DIV, MASK_DIV) +DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU) +DECLARE_INSN(rem, MATCH_REM, MASK_REM) DECLARE_INSN(remu, MATCH_REMU, MASK_REMU) +DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW) +DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW) +DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW) DECLARE_INSN(remw, MATCH_REMW, MASK_REMW) -DECLARE_INSN(sll, MATCH_SLL, MASK_SLL) -DECLARE_INSN(vfssegstd, MATCH_VFSSEGSTD, MASK_VFSSEGSTD) +DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW) +DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W) +DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W) DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W) -DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2) -DECLARE_INSN(vf, MATCH_VF, MASK_VF) -DECLARE_INSN(vfmvv, MATCH_VFMVV, MASK_VFMVV) -DECLARE_INSN(vflsegstw, MATCH_VFLSEGSTW, MASK_VFLSEGSTW) -DECLARE_INSN(vxcptrestore, MATCH_VXCPTRESTORE, MASK_VXCPTRESTORE) -DECLARE_INSN(vxcpthold, MATCH_VXCPTHOLD, MASK_VXCPTHOLD) -DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU) -DECLARE_INSN(vflsegstd, MATCH_VFLSEGSTD, MASK_VFLSEGSTD) -DECLARE_INSN(vfld, MATCH_VFLD, MASK_VFLD) -DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S) -DECLARE_INSN(vflw, MATCH_VFLW, MASK_VFLW) -DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D) -DECLARE_INSN(fmadd_h, MATCH_FMADD_H, MASK_FMADD_H) +DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W) +DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W) +DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W) +DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W) +DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W) +DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W) +DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W) +DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W) +DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D) +DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D) +DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D) +DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D) +DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D) +DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D) +DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D) +DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D) +DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D) +DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D) +DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D) +DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL) +DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK) +DECLARE_INSN(uret, MATCH_URET, MASK_URET) DECLARE_INSN(sret, MATCH_SRET, MASK_SRET) -DECLARE_INSN(vssegw, MATCH_VSSEGW, MASK_VSSEGW) -DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1) -DECLARE_INSN(vssegh, MATCH_VSSEGH, MASK_VSSEGH) -DECLARE_INSN(frcsr, MATCH_FRCSR, MASK_FRCSR) -DECLARE_INSN(vssegd, MATCH_VSSEGD, MASK_VSSEGD) -DECLARE_INSN(vssegb, MATCH_VSSEGB, MASK_VSSEGB) -DECLARE_INSN(fmin_h, MATCH_FMIN_H, MASK_FMIN_H) -DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D) -DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU) +DECLARE_INSN(hret, MATCH_HRET, MASK_HRET) +DECLARE_INSN(mret, MATCH_MRET, MASK_MRET) +DECLARE_INSN(dret, MATCH_DRET, MASK_DRET) +DECLARE_INSN(sfence_vm, MATCH_SFENCE_VM, MASK_SFENCE_VM) +DECLARE_INSN(sfence_vma, MATCH_SFENCE_VMA, MASK_SFENCE_VMA) +DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI) +DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW) +DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS) +DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC) +DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI) +DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI) +DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI) +DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S) +DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S) +DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S) +DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S) +DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S) +DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S) +DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S) DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S) -DECLARE_INSN(srli_rv32, MATCH_SRLI_RV32, MASK_SRLI_RV32) -DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW) DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S) -DECLARE_INSN(fcvt_d_h, MATCH_FCVT_D_H, MASK_FCVT_D_H) -DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W) -DECLARE_INSN(add, MATCH_ADD, MASK_ADD) -DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S) -DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D) -DECLARE_INSN(bne, MATCH_BNE, MASK_BNE) -DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD) -DECLARE_INSN(fsrm, MATCH_FSRM, MASK_FSRM) +DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S) +DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D) +DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D) +DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D) DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D) -DECLARE_INSN(vsw, MATCH_VSW, MASK_VSW) +DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D) +DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D) +DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D) +DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D) +DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D) +DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D) +DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S) +DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D) +DECLARE_INSN(fadd_q, MATCH_FADD_Q, MASK_FADD_Q) +DECLARE_INSN(fsub_q, MATCH_FSUB_Q, MASK_FSUB_Q) +DECLARE_INSN(fmul_q, MATCH_FMUL_Q, MASK_FMUL_Q) +DECLARE_INSN(fdiv_q, MATCH_FDIV_Q, MASK_FDIV_Q) +DECLARE_INSN(fsgnj_q, MATCH_FSGNJ_Q, MASK_FSGNJ_Q) +DECLARE_INSN(fsgnjn_q, MATCH_FSGNJN_Q, MASK_FSGNJN_Q) +DECLARE_INSN(fsgnjx_q, MATCH_FSGNJX_Q, MASK_FSGNJX_Q) +DECLARE_INSN(fmin_q, MATCH_FMIN_Q, MASK_FMIN_Q) +DECLARE_INSN(fmax_q, MATCH_FMAX_Q, MASK_FMAX_Q) +DECLARE_INSN(fcvt_s_q, MATCH_FCVT_S_Q, MASK_FCVT_S_Q) +DECLARE_INSN(fcvt_q_s, MATCH_FCVT_Q_S, MASK_FCVT_Q_S) +DECLARE_INSN(fcvt_d_q, MATCH_FCVT_D_Q, MASK_FCVT_D_Q) +DECLARE_INSN(fcvt_q_d, MATCH_FCVT_Q_D, MASK_FCVT_Q_D) +DECLARE_INSN(fsqrt_q, MATCH_FSQRT_Q, MASK_FSQRT_Q) +DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S) +DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S) +DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S) +DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D) +DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D) +DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D) +DECLARE_INSN(fle_q, MATCH_FLE_Q, MASK_FLE_Q) +DECLARE_INSN(flt_q, MATCH_FLT_Q, MASK_FLT_Q) +DECLARE_INSN(feq_q, MATCH_FEQ_Q, MASK_FEQ_Q) +DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S) +DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S) DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S) -DECLARE_INSN(fdiv_h, MATCH_FDIV_H, MASK_FDIV_H) -DECLARE_INSN(vsb, MATCH_VSB, MASK_VSB) -DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S) -DECLARE_INSN(fsrmi, MATCH_FSRMI, MASK_FSRMI) -DECLARE_INSN(fcvt_l_h, MATCH_FCVT_L_H, MASK_FCVT_L_H) -DECLARE_INSN(vsh, MATCH_VSH, MASK_VSH) +DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S) +DECLARE_INSN(fmv_x_s, MATCH_FMV_X_S, MASK_FMV_X_S) +DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S) +DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D) +DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D) DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D) -DECLARE_INSN(fcvt_h_s, MATCH_FCVT_H_S, MASK_FCVT_H_S) -DECLARE_INSN(scall, MATCH_SCALL, MASK_SCALL) -DECLARE_INSN(fsflagsi, MATCH_FSFLAGSI, MASK_FSFLAGSI) -DECLARE_INSN(fcvt_h_w, MATCH_FCVT_H_W, MASK_FCVT_H_W) -DECLARE_INSN(fcvt_h_l, MATCH_FCVT_H_L, MASK_FCVT_H_L) -DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW) -DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU) -DECLARE_INSN(fcvt_h_d, MATCH_FCVT_H_D, MASK_FCVT_H_D) -DECLARE_INSN(sbreak, MATCH_SBREAK, MASK_SBREAK) -DECLARE_INSN(rdinstreth, MATCH_RDINSTRETH, MASK_RDINSTRETH) -DECLARE_INSN(sra, MATCH_SRA, MASK_SRA) -DECLARE_INSN(bge, MATCH_BGE, MASK_BGE) -DECLARE_INSN(srl, MATCH_SRL, MASK_SRL) -DECLARE_INSN(venqcmd, MATCH_VENQCMD, MASK_VENQCMD) -DECLARE_INSN(or, MATCH_OR, MASK_OR) -DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW) +DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D) DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D) -DECLARE_INSN(rdtime, MATCH_RDTIME, MASK_RDTIME) -DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D) -DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W) -DECLARE_INSN(c_move, MATCH_C_MOVE, MASK_C_MOVE) -DECLARE_INSN(fmovn, MATCH_FMOVN, MASK_FMOVN) +DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D) +DECLARE_INSN(fcvt_w_q, MATCH_FCVT_W_Q, MASK_FCVT_W_Q) +DECLARE_INSN(fcvt_wu_q, MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q) +DECLARE_INSN(fcvt_l_q, MATCH_FCVT_L_Q, MASK_FCVT_L_Q) +DECLARE_INSN(fcvt_lu_q, MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q) +DECLARE_INSN(fmv_x_q, MATCH_FMV_X_Q, MASK_FMV_X_Q) +DECLARE_INSN(fclass_q, MATCH_FCLASS_Q, MASK_FCLASS_Q) +DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W) +DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU) +DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L) +DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU) +DECLARE_INSN(fmv_s_x, MATCH_FMV_S_X, MASK_FMV_S_X) +DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W) +DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU) +DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L) +DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU) +DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X) +DECLARE_INSN(fcvt_q_w, MATCH_FCVT_Q_W, MASK_FCVT_Q_W) +DECLARE_INSN(fcvt_q_wu, MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU) +DECLARE_INSN(fcvt_q_l, MATCH_FCVT_Q_L, MASK_FCVT_Q_L) +DECLARE_INSN(fcvt_q_lu, MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU) +DECLARE_INSN(fmv_q_x, MATCH_FMV_Q_X, MASK_FMV_Q_X) +DECLARE_INSN(flw, MATCH_FLW, MASK_FLW) +DECLARE_INSN(fld, MATCH_FLD, MASK_FLD) +DECLARE_INSN(flq, MATCH_FLQ, MASK_FLQ) +DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW) +DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD) +DECLARE_INSN(fsq, MATCH_FSQ, MASK_FSQ) +DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S) +DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S) +DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S) +DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S) +DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D) +DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D) +DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D) +DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D) +DECLARE_INSN(fmadd_q, MATCH_FMADD_Q, MASK_FMADD_Q) +DECLARE_INSN(fmsub_q, MATCH_FMSUB_Q, MASK_FMSUB_Q) +DECLARE_INSN(fnmsub_q, MATCH_FNMSUB_Q, MASK_FNMSUB_Q) +DECLARE_INSN(fnmadd_q, MATCH_FNMADD_Q, MASK_FNMADD_Q) +DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN) +DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD) +DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW) +DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW) +DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD) +DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW) DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW) -DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W) -DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D) -DECLARE_INSN(fmovz, MATCH_FMOVZ, MASK_FMOVZ) -DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2) -DECLARE_INSN(fmv_x_h, MATCH_FMV_X_H, MASK_FMV_X_H) -DECLARE_INSN(vsd, MATCH_VSD, MASK_VSD) -DECLARE_INSN(vlsegstw, MATCH_VLSEGSTW, MASK_VLSEGSTW) DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI) -DECLARE_INSN(c_slliw, MATCH_C_SLLIW, MASK_C_SLLIW) -DECLARE_INSN(vlsegstb, MATCH_VLSEGSTB, MASK_VLSEGSTB) -DECLARE_INSN(vlsegstd, MATCH_VLSEGSTD, MASK_VLSEGSTD) -DECLARE_INSN(vlsegsth, MATCH_VLSEGSTH, MASK_VLSEGSTH) -DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU) -DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W) -DECLARE_INSN(c_slli32, MATCH_C_SLLI32, MASK_C_SLLI32) -DECLARE_INSN(c_add3, MATCH_C_ADD3, MASK_C_ADD3) -DECLARE_INSN(vgetvl, MATCH_VGETVL, MASK_VGETVL) -DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D) -DECLARE_INSN(fcvt_w_h, MATCH_FCVT_W_H, MASK_FCVT_W_H) -DECLARE_INSN(vlsegb, MATCH_VLSEGB, MASK_VLSEGB) -DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD) -DECLARE_INSN(vlsegd, MATCH_VLSEGD, MASK_VLSEGD) -DECLARE_INSN(fsh, MATCH_FSH, MASK_FSH) -DECLARE_INSN(vlsegh, MATCH_VLSEGH, MASK_VLSEGH) +DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL) +DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI) +DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI) +DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI) +DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI) +DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI) DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB) -DECLARE_INSN(vlsegw, MATCH_VLSEGW, MASK_VLSEGW) -DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW) +DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR) +DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR) +DECLARE_INSN(c_and, MATCH_C_AND, MASK_C_AND) +DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW) +DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW) DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J) +DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ) +DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ) +DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI) +DECLARE_INSN(c_fldsp, MATCH_C_FLDSP, MASK_C_FLDSP) +DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP) +DECLARE_INSN(c_flwsp, MATCH_C_FLWSP, MASK_C_FLWSP) +DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV) +DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD) +DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP) +DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP) +DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP) +DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP) +DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP) +DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR) +DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR) +DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK) +DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD) +DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD) +DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW) +DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP) +DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP) +DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0) +DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1) +DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2) +DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD) +DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1) +DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, MASK_CUSTOM0_RD_RS1_RS2) +DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1) +DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1) +DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2) +DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD) +DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1) +DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, MASK_CUSTOM1_RD_RS1_RS2) +DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2) +DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1) +DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2) +DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD) +DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1) +DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, MASK_CUSTOM2_RD_RS1_RS2) +DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3) +DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1) +DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2) +DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD) +DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1) +DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2) #endif #ifdef DECLARE_CSR +DECLARE_CSR(ustatus, CSR_USTATUS) +DECLARE_CSR(uie, CSR_UIE) +DECLARE_CSR(utvec, CSR_UTVEC) +DECLARE_CSR(uscratch, CSR_USCRATCH) +DECLARE_CSR(uepc, CSR_UEPC) +DECLARE_CSR(ucause, CSR_UCAUSE) +DECLARE_CSR(utval, CSR_UTVAL) +DECLARE_CSR(uip, CSR_UIP) DECLARE_CSR(fflags, CSR_FFLAGS) DECLARE_CSR(frm, CSR_FRM) DECLARE_CSR(fcsr, CSR_FCSR) DECLARE_CSR(cycle, CSR_CYCLE) DECLARE_CSR(time, CSR_TIME) DECLARE_CSR(instret, CSR_INSTRET) -DECLARE_CSR(stats, CSR_STATS) -DECLARE_CSR(uarch0, CSR_UARCH0) -DECLARE_CSR(uarch1, CSR_UARCH1) -DECLARE_CSR(uarch2, CSR_UARCH2) -DECLARE_CSR(uarch3, CSR_UARCH3) -DECLARE_CSR(uarch4, CSR_UARCH4) -DECLARE_CSR(uarch5, CSR_UARCH5) -DECLARE_CSR(uarch6, CSR_UARCH6) -DECLARE_CSR(uarch7, CSR_UARCH7) -DECLARE_CSR(uarch8, CSR_UARCH8) -DECLARE_CSR(uarch9, CSR_UARCH9) -DECLARE_CSR(uarch10, CSR_UARCH10) -DECLARE_CSR(uarch11, CSR_UARCH11) -DECLARE_CSR(uarch12, CSR_UARCH12) -DECLARE_CSR(uarch13, CSR_UARCH13) -DECLARE_CSR(uarch14, CSR_UARCH14) -DECLARE_CSR(uarch15, CSR_UARCH15) +DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3) +DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4) +DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5) +DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6) +DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7) +DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8) +DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9) +DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10) +DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11) +DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12) +DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13) +DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14) +DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15) +DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16) +DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17) +DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18) +DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19) +DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20) +DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21) +DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22) +DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23) +DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24) +DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25) +DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26) +DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27) +DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28) +DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29) +DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30) +DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31) +DECLARE_CSR(cycleh, CSR_CYCLEH) +DECLARE_CSR(timeh, CSR_TIMEH) +DECLARE_CSR(instreth, CSR_INSTRETH) +DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H) +DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H) +DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H) +DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H) +DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H) +DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H) +DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H) +DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H) +DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H) +DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H) +DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H) +DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H) +DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H) +DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H) +DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H) +DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H) +DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H) +DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H) +DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H) +DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H) +DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H) +DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H) +DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H) +DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H) +DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H) +DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H) +DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H) +DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H) +DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H) DECLARE_CSR(sstatus, CSR_SSTATUS) +DECLARE_CSR(sedeleg, CSR_SEDELEG) +DECLARE_CSR(sideleg, CSR_SIDELEG) +DECLARE_CSR(sie, CSR_SIE) DECLARE_CSR(stvec, CSR_STVEC) -DECLARE_CSR(stimecmp, CSR_STIMECMP) +DECLARE_CSR(scounteren, CSR_SCOUNTEREN) DECLARE_CSR(sscratch, CSR_SSCRATCH) DECLARE_CSR(sepc, CSR_SEPC) -DECLARE_CSR(sptbr, CSR_SPTBR) -DECLARE_CSR(sasid, CSR_SASID) -DECLARE_CSR(scycle, CSR_SCYCLE) -DECLARE_CSR(stime, CSR_STIME) -DECLARE_CSR(sinstret, CSR_SINSTRET) DECLARE_CSR(scause, CSR_SCAUSE) -DECLARE_CSR(sbadaddr, CSR_SBADADDR) +DECLARE_CSR(stval, CSR_STVAL) +DECLARE_CSR(sip, CSR_SIP) +DECLARE_CSR(satp, CSR_SATP) +DECLARE_CSR(mvendorid, CSR_MVENDORID) +DECLARE_CSR(marchid, CSR_MARCHID) +DECLARE_CSR(mimpid, CSR_MIMPID) +DECLARE_CSR(mhartid, CSR_MHARTID) DECLARE_CSR(mstatus, CSR_MSTATUS) +DECLARE_CSR(misa, CSR_MISA) +DECLARE_CSR(medeleg, CSR_MEDELEG) +DECLARE_CSR(mideleg, CSR_MIDELEG) +DECLARE_CSR(mie, CSR_MIE) +DECLARE_CSR(mtvec, CSR_MTVEC) +DECLARE_CSR(mcounteren, CSR_MCOUNTEREN) DECLARE_CSR(mscratch, CSR_MSCRATCH) DECLARE_CSR(mepc, CSR_MEPC) DECLARE_CSR(mcause, CSR_MCAUSE) -DECLARE_CSR(mbadaddr, CSR_MBADADDR) -DECLARE_CSR(reset, CSR_RESET) -DECLARE_CSR(tohost, CSR_TOHOST) -DECLARE_CSR(fromhost, CSR_FROMHOST) -DECLARE_CSR(send_ipi, CSR_SEND_IPI) -DECLARE_CSR(hartid, CSR_HARTID) -DECLARE_CSR(cycleh, CSR_CYCLEH) -DECLARE_CSR(timeh, CSR_TIMEH) -DECLARE_CSR(instreth, CSR_INSTRETH) -DECLARE_CSR(scycleh, CSR_SCYCLEH) -DECLARE_CSR(stimeh, CSR_STIMEH) -DECLARE_CSR(sinstreth, CSR_SINSTRETH) +DECLARE_CSR(mtval, CSR_MTVAL) +DECLARE_CSR(mip, CSR_MIP) +DECLARE_CSR(pmpcfg0, CSR_PMPCFG0) +DECLARE_CSR(pmpcfg1, CSR_PMPCFG1) +DECLARE_CSR(pmpcfg2, CSR_PMPCFG2) +DECLARE_CSR(pmpcfg3, CSR_PMPCFG3) +DECLARE_CSR(pmpaddr0, CSR_PMPADDR0) +DECLARE_CSR(pmpaddr1, CSR_PMPADDR1) +DECLARE_CSR(pmpaddr2, CSR_PMPADDR2) +DECLARE_CSR(pmpaddr3, CSR_PMPADDR3) +DECLARE_CSR(pmpaddr4, CSR_PMPADDR4) +DECLARE_CSR(pmpaddr5, CSR_PMPADDR5) +DECLARE_CSR(pmpaddr6, CSR_PMPADDR6) +DECLARE_CSR(pmpaddr7, CSR_PMPADDR7) +DECLARE_CSR(pmpaddr8, CSR_PMPADDR8) +DECLARE_CSR(pmpaddr9, CSR_PMPADDR9) +DECLARE_CSR(pmpaddr10, CSR_PMPADDR10) +DECLARE_CSR(pmpaddr11, CSR_PMPADDR11) +DECLARE_CSR(pmpaddr12, CSR_PMPADDR12) +DECLARE_CSR(pmpaddr13, CSR_PMPADDR13) +DECLARE_CSR(pmpaddr14, CSR_PMPADDR14) +DECLARE_CSR(pmpaddr15, CSR_PMPADDR15) +DECLARE_CSR(mcycle, CSR_MCYCLE) +DECLARE_CSR(minstret, CSR_MINSTRET) +DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3) +DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4) +DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5) +DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6) +DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7) +DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8) +DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9) +DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10) +DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11) +DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12) +DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13) +DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14) +DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15) +DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16) +DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17) +DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18) +DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19) +DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20) +DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21) +DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22) +DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23) +DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24) +DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25) +DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26) +DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27) +DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28) +DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29) +DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30) +DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31) +DECLARE_CSR(mcycleh, CSR_MCYCLEH) +DECLARE_CSR(minstreth, CSR_MINSTRETH) +DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H) +DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H) +DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H) +DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H) +DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H) +DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H) +DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H) +DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H) +DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H) +DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H) +DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H) +DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H) +DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H) +DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H) +DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H) +DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H) +DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H) +DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H) +DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H) +DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H) +DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H) +DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H) +DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H) +DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H) +DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H) +DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H) +DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H) +DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H) +DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H) +DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3) +DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4) +DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5) +DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6) +DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7) +DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8) +DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9) +DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10) +DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11) +DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12) +DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13) +DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14) +DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15) +DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16) +DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17) +DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18) +DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19) +DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20) +DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21) +DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22) +DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23) +DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24) +DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25) +DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26) +DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27) +DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28) +DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29) +DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30) +DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31) +DECLARE_CSR(tselect, CSR_TSELECT) +DECLARE_CSR(tdata1, CSR_TDATA1) +DECLARE_CSR(tdata2, CSR_TDATA2) +DECLARE_CSR(tdata3, CSR_TDATA3) +DECLARE_CSR(dcsr, CSR_DCSR) +DECLARE_CSR(dpc, CSR_DPC) +DECLARE_CSR(dscratch, CSR_DSCRATCH) +/* These registers are present in priv spec 1.9.1, dropped in 1.10. */ +DECLARE_CSR(hstatus, CSR_HSTATUS) +DECLARE_CSR(hedeleg, CSR_HEDELEG) +DECLARE_CSR(hideleg, CSR_HIDELEG) +DECLARE_CSR(hie, CSR_HIE) +DECLARE_CSR(htvec, CSR_HTVEC) +DECLARE_CSR(hscratch, CSR_HSCRATCH) +DECLARE_CSR(hepc, CSR_HEPC) +DECLARE_CSR(hcause, CSR_HCAUSE) +DECLARE_CSR(hbadaddr, CSR_HBADADDR) +DECLARE_CSR(hip, CSR_HIP) +DECLARE_CSR(mbase, CSR_MBASE) +DECLARE_CSR(mbound, CSR_MBOUND) +DECLARE_CSR(mibase, CSR_MIBASE) +DECLARE_CSR(mibound, CSR_MIBOUND) +DECLARE_CSR(mdbase, CSR_MDBASE) +DECLARE_CSR(mdbound, CSR_MDBOUND) +DECLARE_CSR(mucounteren, CSR_MUCOUNTEREN) +DECLARE_CSR(mscounteren, CSR_MSCOUNTEREN) +DECLARE_CSR(mhcounteren, CSR_MHCOUNTEREN) +#endif +#ifdef DECLARE_CSR_ALIAS +/* Ubadaddr is 0x043 in 1.9.1, but 0x043 is utval in 1.10. */ +DECLARE_CSR_ALIAS(ubadaddr, CSR_UTVAL) +/* Sbadaddr is 0x143 in 1.9.1, but 0x143 is stval in 1.10. */ +DECLARE_CSR_ALIAS(sbadaddr, CSR_STVAL) +/* Sptbr is 0x180 in 1.9.1, but 0x180 is satp in 1.10. */ +DECLARE_CSR_ALIAS(sptbr, CSR_SATP) +/* Mbadaddr is 0x343 in 1.9.1, but 0x343 is mtval in 1.10. */ +DECLARE_CSR_ALIAS(mbadaddr, CSR_MTVAL) #endif #ifdef DECLARE_CAUSE -DECLARE_CAUSE("fflags", CAUSE_FFLAGS) -DECLARE_CAUSE("frm", CAUSE_FRM) -DECLARE_CAUSE("fcsr", CAUSE_FCSR) -DECLARE_CAUSE("cycle", CAUSE_CYCLE) -DECLARE_CAUSE("time", CAUSE_TIME) -DECLARE_CAUSE("instret", CAUSE_INSTRET) -DECLARE_CAUSE("stats", CAUSE_STATS) -DECLARE_CAUSE("uarch0", CAUSE_UARCH0) -DECLARE_CAUSE("uarch1", CAUSE_UARCH1) -DECLARE_CAUSE("uarch2", CAUSE_UARCH2) -DECLARE_CAUSE("uarch3", CAUSE_UARCH3) -DECLARE_CAUSE("uarch4", CAUSE_UARCH4) -DECLARE_CAUSE("uarch5", CAUSE_UARCH5) -DECLARE_CAUSE("uarch6", CAUSE_UARCH6) -DECLARE_CAUSE("uarch7", CAUSE_UARCH7) -DECLARE_CAUSE("uarch8", CAUSE_UARCH8) -DECLARE_CAUSE("uarch9", CAUSE_UARCH9) -DECLARE_CAUSE("uarch10", CAUSE_UARCH10) -DECLARE_CAUSE("uarch11", CAUSE_UARCH11) -DECLARE_CAUSE("uarch12", CAUSE_UARCH12) -DECLARE_CAUSE("uarch13", CAUSE_UARCH13) -DECLARE_CAUSE("uarch14", CAUSE_UARCH14) -DECLARE_CAUSE("uarch15", CAUSE_UARCH15) -DECLARE_CAUSE("sstatus", CAUSE_SSTATUS) -DECLARE_CAUSE("stvec", CAUSE_STVEC) -DECLARE_CAUSE("stimecmp", CAUSE_STIMECMP) -DECLARE_CAUSE("sscratch", CAUSE_SSCRATCH) -DECLARE_CAUSE("sepc", CAUSE_SEPC) -DECLARE_CAUSE("sptbr", CAUSE_SPTBR) -DECLARE_CAUSE("sasid", CAUSE_SASID) -DECLARE_CAUSE("scycle", CAUSE_SCYCLE) -DECLARE_CAUSE("stime", CAUSE_STIME) -DECLARE_CAUSE("sinstret", CAUSE_SINSTRET) -DECLARE_CAUSE("scause", CAUSE_SCAUSE) -DECLARE_CAUSE("sbadaddr", CAUSE_SBADADDR) -DECLARE_CAUSE("mstatus", CAUSE_MSTATUS) -DECLARE_CAUSE("mscratch", CAUSE_MSCRATCH) -DECLARE_CAUSE("mepc", CAUSE_MEPC) -DECLARE_CAUSE("mcause", CAUSE_MCAUSE) -DECLARE_CAUSE("mbadaddr", CAUSE_MBADADDR) -DECLARE_CAUSE("reset", CAUSE_RESET) -DECLARE_CAUSE("tohost", CAUSE_TOHOST) -DECLARE_CAUSE("fromhost", CAUSE_FROMHOST) -DECLARE_CAUSE("send_ipi", CAUSE_SEND_IPI) -DECLARE_CAUSE("hartid", CAUSE_HARTID) -DECLARE_CAUSE("cycleh", CAUSE_CYCLEH) -DECLARE_CAUSE("timeh", CAUSE_TIMEH) -DECLARE_CAUSE("instreth", CAUSE_INSTRETH) -DECLARE_CAUSE("scycleh", CAUSE_SCYCLEH) -DECLARE_CAUSE("stimeh", CAUSE_STIMEH) -DECLARE_CAUSE("sinstreth", CAUSE_SINSTRETH) +DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH) +DECLARE_CAUSE("fault fetch", CAUSE_FAULT_FETCH) +DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION) +DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT) +DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD) +DECLARE_CAUSE("fault load", CAUSE_FAULT_LOAD) +DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE) +DECLARE_CAUSE("fault store", CAUSE_FAULT_STORE) +DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL) +DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL) +DECLARE_CAUSE("hypervisor_ecall", CAUSE_HYPERVISOR_ECALL) +DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL) #endif diff --git a/external/gpl3/binutils.old/dist/include/opcode/riscv.h b/external/gpl3/binutils.old/dist/include/opcode/riscv.h index 5965ff68a39..ac6f7735b06 100644 --- a/external/gpl3/binutils.old/dist/include/opcode/riscv.h +++ b/external/gpl3/binutils.old/dist/include/opcode/riscv.h @@ -1,23 +1,22 @@ /* riscv.h. RISC-V opcode list for GDB, the GNU debugger. - Copyright 2011 - Free Software Foundation, Inc. - Contributed by Andrew Waterman + Copyright (C) 2011-2018 Free Software Foundation, Inc. + Contributed by Andrew Waterman -This file is part of GDB, GAS, and the GNU binutils. + This file is part of GDB, GAS, and the GNU binutils. -GDB, GAS, and the GNU binutils are free software; you can redistribute -them and/or modify them under the terms of the GNU General Public -License as published by the Free Software Foundation; either version -1, or (at your option) any later version. + GDB, GAS, and the GNU binutils are free software; you can redistribute + them and/or modify them under the terms of the GNU General Public + License as published by the Free Software Foundation; either version + 3, or (at your option) any later version. -GDB, GAS, and the GNU binutils are distributed in the hope that they -will be useful, but WITHOUT ANY WARRANTY; without even the implied -warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -the GNU General Public License for more details. + GDB, GAS, and the GNU binutils are distributed in the hope that they + will be useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + the GNU General Public License for more details. -You should have received a copy of the GNU General Public License -along with this file; see the file COPYING. If not, write to the Free -Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + You should have received a copy of the GNU General Public License + along with this program; see the file COPYING3. If not, + see <http://www.gnu.org/licenses/>. */ #ifndef _RISCV_H_ #define _RISCV_H_ @@ -26,69 +25,40 @@ Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, US #include <stdlib.h> #include <stdint.h> -/* RVC fields */ - -#define OP_MASK_CRD 0x1f -#define OP_SH_CRD 5 -#define OP_MASK_CRS2 0x1f -#define OP_SH_CRS2 5 -#define OP_MASK_CRS1 0x1f -#define OP_SH_CRS1 10 -#define OP_MASK_CRDS 0x7 -#define OP_SH_CRDS 13 -#define OP_MASK_CRS2S 0x7 -#define OP_SH_CRS2S 13 -#define OP_MASK_CRS2BS 0x7 -#define OP_SH_CRS2BS 5 -#define OP_MASK_CRS1S 0x7 -#define OP_SH_CRS1S 10 -#define OP_MASK_CIMM6 0x3f -#define OP_SH_CIMM6 10 -#define OP_MASK_CIMM5 0x1f -#define OP_SH_CIMM5 5 -#define OP_MASK_CIMM10 0x3ff -#define OP_SH_CIMM10 5 - -static const char rvc_rs1_regmap[8] = { 20, 21, 2, 3, 4, 5, 6, 7 }; -#define rvc_rd_regmap rvc_rs1_regmap -#define rvc_rs2b_regmap rvc_rs1_regmap -static const char rvc_rs2_regmap[8] = { 20, 21, 2, 3, 4, 5, 6, 0 }; - typedef uint64_t insn_t; static inline unsigned int riscv_insn_length (insn_t insn) { - if ((insn & 0x3) != 3) /* RVC */ + if ((insn & 0x3) != 0x3) /* RVC. */ return 2; - if ((insn & 0x1f) != 0x1f) /* base ISA and extensions in 32-bit space */ + if ((insn & 0x1f) != 0x1f) /* Base ISA and extensions in 32-bit space. */ return 4; - if ((insn & 0x3f) == 0x1f) /* 48-bit extensions */ + if ((insn & 0x3f) == 0x1f) /* 48-bit extensions. */ return 6; - if ((insn & 0x7f) == 0x3f) /* 64-bit extensions */ + if ((insn & 0x7f) == 0x3f) /* 64-bit extensions. */ return 8; - /* longer instructions not supported at the moment */ + /* Longer instructions not supported at the moment. */ return 2; } -static const char * const riscv_rm[8] = { +static const char * const riscv_rm[8] = +{ "rne", "rtz", "rdn", "rup", "rmm", 0, 0, "dyn" }; -static const char* const riscv_pred_succ[16] = { + +static const char * const riscv_pred_succ[16] = +{ 0, "w", "r", "rw", "o", "ow", "or", "orw", - "i", "iw", "ir", "irw", "io", "iow", "ior", "iorw", + "i", "iw", "ir", "irw", "io", "iow", "ior", "iorw" }; -#define RVC_JUMP_BITS 10 -#define RVC_JUMP_ALIGN_BITS 1 -#define RVC_JUMP_ALIGN (1 << RVC_JUMP_ALIGN_BITS) -#define RVC_JUMP_REACH ((1ULL<<RVC_JUMP_BITS)*RVC_JUMP_ALIGN) +#define RVC_JUMP_BITS 11 +#define RVC_JUMP_REACH ((1ULL << RVC_JUMP_BITS) * RISCV_JUMP_ALIGN) -#define RVC_BRANCH_BITS 5 -#define RVC_BRANCH_ALIGN_BITS RVC_JUMP_ALIGN_BITS -#define RVC_BRANCH_ALIGN (1 << RVC_BRANCH_ALIGN_BITS) -#define RVC_BRANCH_REACH ((1ULL<<RVC_BRANCH_BITS)*RVC_BRANCH_ALIGN) +#define RVC_BRANCH_BITS 8 +#define RVC_BRANCH_REACH ((1ULL << RVC_BRANCH_BITS) * RISCV_BRANCH_ALIGN) -#define RV_X(x, s, n) (((x) >> (s)) & ((1<<(n))-1)) +#define RV_X(x, s, n) (((x) >> (s)) & ((1 << (n)) - 1)) #define RV_IMM_SIGN(x) (-(((x) >> 31) & 1)) #define EXTRACT_ITYPE_IMM(x) \ @@ -101,6 +71,34 @@ static const char* const riscv_pred_succ[16] = { ((RV_X(x, 12, 20) << 12) | (RV_IMM_SIGN(x) << 32)) #define EXTRACT_UJTYPE_IMM(x) \ ((RV_X(x, 21, 10) << 1) | (RV_X(x, 20, 1) << 11) | (RV_X(x, 12, 8) << 12) | (RV_IMM_SIGN(x) << 20)) +#define EXTRACT_RVC_IMM(x) \ + (RV_X(x, 2, 5) | (-RV_X(x, 12, 1) << 5)) +#define EXTRACT_RVC_LUI_IMM(x) \ + (EXTRACT_RVC_IMM (x) << RISCV_IMM_BITS) +#define EXTRACT_RVC_SIMM3(x) \ + (RV_X(x, 10, 2) | (-RV_X(x, 12, 1) << 2)) +#define EXTRACT_RVC_UIMM8(x) \ + (RV_X(x, 5, 8)) +#define EXTRACT_RVC_ADDI4SPN_IMM(x) \ + ((RV_X(x, 6, 1) << 2) | (RV_X(x, 5, 1) << 3) | (RV_X(x, 11, 2) << 4) | (RV_X(x, 7, 4) << 6)) +#define EXTRACT_RVC_ADDI16SP_IMM(x) \ + ((RV_X(x, 6, 1) << 4) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 5, 1) << 6) | (RV_X(x, 3, 2) << 7) | (-RV_X(x, 12, 1) << 9)) +#define EXTRACT_RVC_LW_IMM(x) \ + ((RV_X(x, 6, 1) << 2) | (RV_X(x, 10, 3) << 3) | (RV_X(x, 5, 1) << 6)) +#define EXTRACT_RVC_LD_IMM(x) \ + ((RV_X(x, 10, 3) << 3) | (RV_X(x, 5, 2) << 6)) +#define EXTRACT_RVC_LWSP_IMM(x) \ + ((RV_X(x, 4, 3) << 2) | (RV_X(x, 12, 1) << 5) | (RV_X(x, 2, 2) << 6)) +#define EXTRACT_RVC_LDSP_IMM(x) \ + ((RV_X(x, 5, 2) << 3) | (RV_X(x, 12, 1) << 5) | (RV_X(x, 2, 3) << 6)) +#define EXTRACT_RVC_SWSP_IMM(x) \ + ((RV_X(x, 9, 4) << 2) | (RV_X(x, 7, 2) << 6)) +#define EXTRACT_RVC_SDSP_IMM(x) \ + ((RV_X(x, 10, 3) << 3) | (RV_X(x, 7, 3) << 6)) +#define EXTRACT_RVC_B_IMM(x) \ + ((RV_X(x, 3, 2) << 1) | (RV_X(x, 10, 2) << 3) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 5, 2) << 6) | (-RV_X(x, 12, 1) << 8)) +#define EXTRACT_RVC_J_IMM(x) \ + ((RV_X(x, 3, 3) << 1) | (RV_X(x, 11, 1) << 4) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 7, 1) << 6) | (RV_X(x, 6, 1) << 7) | (RV_X(x, 9, 2) << 8) | (RV_X(x, 8, 1) << 10) | (-RV_X(x, 12, 1) << 11)) #define ENCODE_ITYPE_IMM(x) \ (RV_X(x, 0, 12) << 20) @@ -112,12 +110,54 @@ static const char* const riscv_pred_succ[16] = { (RV_X(x, 12, 20) << 12) #define ENCODE_UJTYPE_IMM(x) \ ((RV_X(x, 1, 10) << 21) | (RV_X(x, 11, 1) << 20) | (RV_X(x, 12, 8) << 12) | (RV_X(x, 20, 1) << 31)) +#define ENCODE_RVC_IMM(x) \ + ((RV_X(x, 0, 5) << 2) | (RV_X(x, 5, 1) << 12)) +#define ENCODE_RVC_LUI_IMM(x) \ + ENCODE_RVC_IMM ((x) >> RISCV_IMM_BITS) +#define ENCODE_RVC_SIMM3(x) \ + (RV_X(x, 0, 3) << 10) +#define ENCODE_RVC_UIMM8(x) \ + (RV_X(x, 0, 8) << 5) +#define ENCODE_RVC_ADDI4SPN_IMM(x) \ + ((RV_X(x, 2, 1) << 6) | (RV_X(x, 3, 1) << 5) | (RV_X(x, 4, 2) << 11) | (RV_X(x, 6, 4) << 7)) +#define ENCODE_RVC_ADDI16SP_IMM(x) \ + ((RV_X(x, 4, 1) << 6) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 1) << 5) | (RV_X(x, 7, 2) << 3) | (RV_X(x, 9, 1) << 12)) +#define ENCODE_RVC_LW_IMM(x) \ + ((RV_X(x, 2, 1) << 6) | (RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 1) << 5)) +#define ENCODE_RVC_LD_IMM(x) \ + ((RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 2) << 5)) +#define ENCODE_RVC_LWSP_IMM(x) \ + ((RV_X(x, 2, 3) << 4) | (RV_X(x, 5, 1) << 12) | (RV_X(x, 6, 2) << 2)) +#define ENCODE_RVC_LDSP_IMM(x) \ + ((RV_X(x, 3, 2) << 5) | (RV_X(x, 5, 1) << 12) | (RV_X(x, 6, 3) << 2)) +#define ENCODE_RVC_SWSP_IMM(x) \ + ((RV_X(x, 2, 4) << 9) | (RV_X(x, 6, 2) << 7)) +#define ENCODE_RVC_SDSP_IMM(x) \ + ((RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 3) << 7)) +#define ENCODE_RVC_B_IMM(x) \ + ((RV_X(x, 1, 2) << 3) | (RV_X(x, 3, 2) << 10) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 2) << 5) | (RV_X(x, 8, 1) << 12)) +#define ENCODE_RVC_J_IMM(x) \ + ((RV_X(x, 1, 3) << 3) | (RV_X(x, 4, 1) << 11) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 1) << 7) | (RV_X(x, 7, 1) << 6) | (RV_X(x, 8, 2) << 9) | (RV_X(x, 10, 1) << 8) | (RV_X(x, 11, 1) << 12)) #define VALID_ITYPE_IMM(x) (EXTRACT_ITYPE_IMM(ENCODE_ITYPE_IMM(x)) == (x)) #define VALID_STYPE_IMM(x) (EXTRACT_STYPE_IMM(ENCODE_STYPE_IMM(x)) == (x)) #define VALID_SBTYPE_IMM(x) (EXTRACT_SBTYPE_IMM(ENCODE_SBTYPE_IMM(x)) == (x)) #define VALID_UTYPE_IMM(x) (EXTRACT_UTYPE_IMM(ENCODE_UTYPE_IMM(x)) == (x)) #define VALID_UJTYPE_IMM(x) (EXTRACT_UJTYPE_IMM(ENCODE_UJTYPE_IMM(x)) == (x)) +#define VALID_RVC_IMM(x) (EXTRACT_RVC_IMM(ENCODE_RVC_IMM(x)) == (x)) +#define VALID_RVC_LUI_IMM(x) (ENCODE_RVC_LUI_IMM(x) != 0 && EXTRACT_RVC_LUI_IMM(ENCODE_RVC_LUI_IMM(x)) == (x)) +#define VALID_RVC_SIMM3(x) (EXTRACT_RVC_SIMM3(ENCODE_RVC_SIMM3(x)) == (x)) +#define VALID_RVC_UIMM8(x) (EXTRACT_RVC_UIMM8(ENCODE_RVC_UIMM8(x)) == (x)) +#define VALID_RVC_ADDI4SPN_IMM(x) (EXTRACT_RVC_ADDI4SPN_IMM(ENCODE_RVC_ADDI4SPN_IMM(x)) == (x)) +#define VALID_RVC_ADDI16SP_IMM(x) (EXTRACT_RVC_ADDI16SP_IMM(ENCODE_RVC_ADDI16SP_IMM(x)) == (x)) +#define VALID_RVC_LW_IMM(x) (EXTRACT_RVC_LW_IMM(ENCODE_RVC_LW_IMM(x)) == (x)) +#define VALID_RVC_LD_IMM(x) (EXTRACT_RVC_LD_IMM(ENCODE_RVC_LD_IMM(x)) == (x)) +#define VALID_RVC_LWSP_IMM(x) (EXTRACT_RVC_LWSP_IMM(ENCODE_RVC_LWSP_IMM(x)) == (x)) +#define VALID_RVC_LDSP_IMM(x) (EXTRACT_RVC_LDSP_IMM(ENCODE_RVC_LDSP_IMM(x)) == (x)) +#define VALID_RVC_SWSP_IMM(x) (EXTRACT_RVC_SWSP_IMM(ENCODE_RVC_SWSP_IMM(x)) == (x)) +#define VALID_RVC_SDSP_IMM(x) (EXTRACT_RVC_SDSP_IMM(ENCODE_RVC_SDSP_IMM(x)) == (x)) +#define VALID_RVC_B_IMM(x) (EXTRACT_RVC_B_IMM(ENCODE_RVC_B_IMM(x)) == (x)) +#define VALID_RVC_J_IMM(x) (EXTRACT_RVC_J_IMM(ENCODE_RVC_J_IMM(x)) == (x)) #define RISCV_RTYPE(insn, rd, rs1, rs2) \ ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2)) @@ -133,6 +173,7 @@ static const char* const riscv_pred_succ[16] = { ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ENCODE_UJTYPE_IMM(target)) #define RISCV_NOP RISCV_ITYPE(ADDI, 0, 0, 0) +#define RVC_NOP MATCH_C_ADDI #define RISCV_CONST_HIGH_PART(VALUE) \ (((VALUE) + (RISCV_IMM_REACH/2)) & ~(RISCV_IMM_REACH-1)) @@ -140,7 +181,22 @@ static const char* const riscv_pred_succ[16] = { #define RISCV_PCREL_HIGH_PART(VALUE, PC) RISCV_CONST_HIGH_PART((VALUE) - (PC)) #define RISCV_PCREL_LOW_PART(VALUE, PC) RISCV_CONST_LOW_PART((VALUE) - (PC)) -/* RV fields */ +#define RISCV_JUMP_BITS RISCV_BIGIMM_BITS +#define RISCV_JUMP_ALIGN_BITS 1 +#define RISCV_JUMP_ALIGN (1 << RISCV_JUMP_ALIGN_BITS) +#define RISCV_JUMP_REACH ((1ULL << RISCV_JUMP_BITS) * RISCV_JUMP_ALIGN) + +#define RISCV_IMM_BITS 12 +#define RISCV_BIGIMM_BITS (32 - RISCV_IMM_BITS) +#define RISCV_IMM_REACH (1LL << RISCV_IMM_BITS) +#define RISCV_BIGIMM_REACH (1LL << RISCV_BIGIMM_BITS) +#define RISCV_RVC_IMM_REACH (1LL << 6) +#define RISCV_BRANCH_BITS RISCV_IMM_BITS +#define RISCV_BRANCH_ALIGN_BITS RISCV_JUMP_ALIGN_BITS +#define RISCV_BRANCH_ALIGN (1 << RISCV_BRANCH_ALIGN_BITS) +#define RISCV_BRANCH_REACH (RISCV_IMM_REACH * RISCV_BRANCH_ALIGN) + +/* RV fields. */ #define OP_MASK_OP 0x7f #define OP_SH_OP 0 @@ -167,34 +223,36 @@ static const char* const riscv_pred_succ[16] = { #define OP_MASK_RL 0x1 #define OP_SH_RL 25 -#define OP_MASK_VRD 0x1f -#define OP_SH_VRD 7 -#define OP_MASK_VRS 0x1f -#define OP_SH_VRS 15 -#define OP_MASK_VRT 0x1f -#define OP_SH_VRT 20 -#define OP_MASK_VRR 0x1f -#define OP_SH_VRR 27 - -#define OP_MASK_VFD 0x1f -#define OP_SH_VFD 7 -#define OP_MASK_VFS 0x1f -#define OP_SH_VFS 15 -#define OP_MASK_VFT 0x1f -#define OP_SH_VFT 20 -#define OP_MASK_VFR 0x1f -#define OP_SH_VFR 27 - -#define OP_MASK_IMMNGPR 0x3f -#define OP_SH_IMMNGPR 20 -#define OP_MASK_IMMNFPR 0x3f -#define OP_SH_IMMNFPR 26 -#define OP_MASK_IMMSEGNELM 0x7 -#define OP_SH_IMMSEGNELM 29 -#define OP_MASK_CUSTOM_IMM 0x7f -#define OP_SH_CUSTOM_IMM 25 -#define OP_MASK_CSR 0xfff -#define OP_SH_CSR 20 +#define OP_MASK_CUSTOM_IMM 0x7f +#define OP_SH_CUSTOM_IMM 25 +#define OP_MASK_CSR 0xfff +#define OP_SH_CSR 20 + +#define OP_MASK_FUNCT3 0x7 +#define OP_SH_FUNCT3 12 +#define OP_MASK_FUNCT7 0x7f +#define OP_SH_FUNCT7 25 +#define OP_MASK_FUNCT2 0x3 +#define OP_SH_FUNCT2 25 + +/* RVC fields. */ + +#define OP_MASK_OP2 0x3 +#define OP_SH_OP2 0 + +#define OP_MASK_CRS2 0x1f +#define OP_SH_CRS2 2 +#define OP_MASK_CRS1S 0x7 +#define OP_SH_CRS1S 7 +#define OP_MASK_CRS2S 0x7 +#define OP_SH_CRS2S 2 + +#define OP_MASK_CFUNCT4 0xf +#define OP_SH_CFUNCT4 12 +#define OP_MASK_CFUNCT3 0x7 +#define OP_SH_CFUNCT3 13 + +/* ABI names for selected x-registers. */ #define X_RA 1 #define X_SP 2 @@ -207,22 +265,21 @@ static const char* const riscv_pred_succ[16] = { #define NGPR 32 #define NFPR 32 -#define NVGPR 32 -#define NVFPR 32 -#define RISCV_JUMP_BITS RISCV_BIGIMM_BITS -#define RISCV_JUMP_ALIGN_BITS 1 -#define RISCV_JUMP_ALIGN (1 << RISCV_JUMP_ALIGN_BITS) -#define RISCV_JUMP_REACH ((1ULL<<RISCV_JUMP_BITS)*RISCV_JUMP_ALIGN) +/* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in + VALUE << SHIFT. VALUE is evaluated exactly once. */ +#define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \ + (STRUCT) = (((STRUCT) & ~((insn_t)(MASK) << (SHIFT))) \ + | ((insn_t)((VALUE) & (MASK)) << (SHIFT))) -#define RISCV_IMM_BITS 12 -#define RISCV_BIGIMM_BITS (32-RISCV_IMM_BITS) -#define RISCV_IMM_REACH (1LL<<RISCV_IMM_BITS) -#define RISCV_BIGIMM_REACH (1LL<<RISCV_BIGIMM_BITS) -#define RISCV_BRANCH_BITS RISCV_IMM_BITS -#define RISCV_BRANCH_ALIGN_BITS RISCV_JUMP_ALIGN_BITS -#define RISCV_BRANCH_ALIGN (1 << RISCV_BRANCH_ALIGN_BITS) -#define RISCV_BRANCH_REACH (RISCV_IMM_REACH*RISCV_BRANCH_ALIGN) +/* Extract bits MASK << SHIFT from STRUCT and shift them right + SHIFT places. */ +#define EXTRACT_BITS(STRUCT, MASK, SHIFT) \ + (((STRUCT) >> (SHIFT)) & (MASK)) + +/* Extract the operand given by FIELD from integer INSN. */ +#define EXTRACT_OPERAND(FIELD, INSN) \ + EXTRACT_BITS ((INSN), OP_MASK_##FIELD, OP_SH_##FIELD) /* This structure holds information for a particular instruction. */ @@ -230,7 +287,7 @@ struct riscv_opcode { /* The name of the instruction. */ const char *name; - /* The ISA subset name (I, M, A, F, D, Xextension). */ + /* The ISA subset name (I, M, A, F, D, Xextension). */ const char *subset; /* A string describing the arguments for this instruction. */ const char *args; @@ -245,27 +302,19 @@ struct riscv_opcode INSN_MACRO, then this field is the macro identifier. */ insn_t mask; /* A function to determine if a word corresponds to this instruction. - Usually, this computes ((word & mask) == match). */ - int (*match_func)(const struct riscv_opcode *op, insn_t word); + Usually, this computes ((word & mask) == match). */ + int (*match_func) (const struct riscv_opcode *op, insn_t word); /* For a macro, this is INSN_MACRO. Otherwise, it is a collection of bits describing the instruction, notably any relevant hazard information. */ unsigned long pinfo; }; -#define INSN_WRITE_GPR_D 0x00000001 -#define INSN_WRITE_GPR_RA 0x00000004 -#define INSN_WRITE_FPR_D 0x00000008 -#define INSN_READ_GPR_S 0x00000040 -#define INSN_READ_GPR_T 0x00000080 -#define INSN_READ_FPR_S 0x00000100 -#define INSN_READ_FPR_T 0x00000200 -#define INSN_READ_FPR_R 0x00000400 -/* Instruction is a simple alias (I.E. "move" for daddu/addu/or) */ -#define INSN_ALIAS 0x00001000 +/* Instruction is a simple alias (e.g. "mv" for "addi"). */ +#define INSN_ALIAS 0x00000001 /* Instruction is actually a macro. It should be ignored by the disassembler, and requires special treatment by the assembler. */ -#define INSN_MACRO 0xffffffff +#define INSN_MACRO 0xffffffff /* This is a list of macro expanded instructions. @@ -294,12 +343,13 @@ enum M_SD, M_FLW, M_FLD, + M_FLQ, M_FSW, M_FSD, + M_FSQ, M_CALL, M_J, M_LI, - M_VF, M_NUM_MACROS }; @@ -308,13 +358,8 @@ extern const char * const riscv_gpr_names_numeric[NGPR]; extern const char * const riscv_gpr_names_abi[NGPR]; extern const char * const riscv_fpr_names_numeric[NFPR]; extern const char * const riscv_fpr_names_abi[NFPR]; -extern const char * const riscv_vec_gpr_names[NVGPR]; -extern const char * const riscv_vec_fpr_names[NVFPR]; - -extern const struct riscv_opcode riscv_builtin_opcodes[]; -extern const int bfd_riscv_num_builtin_opcodes; -extern struct riscv_opcode *riscv_opcodes; -extern int bfd_riscv_num_opcodes; -#define NUMOPCODES bfd_riscv_num_opcodes + +extern const struct riscv_opcode riscv_opcodes[]; +extern const struct riscv_opcode riscv_insn_types[]; #endif /* _RISCV_H_ */ diff --git a/external/gpl3/binutils.old/dist/include/opcode/rl78.h b/external/gpl3/binutils.old/dist/include/opcode/rl78.h index f472262b1ea..b061670609f 100644 --- a/external/gpl3/binutils.old/dist/include/opcode/rl78.h +++ b/external/gpl3/binutils.old/dist/include/opcode/rl78.h @@ -1,5 +1,5 @@ /* Opcode decoder for the Renesas RL78 - Copyright (C) 2011-2016 Free Software Foundation, Inc. + Copyright (C) 2011-2018 Free Software Foundation, Inc. Written by DJ Delorie <dj@redhat.com> This file is part of GDB, the GNU Debugger and GAS, the GNU Assembler. diff --git a/external/gpl3/binutils.old/dist/include/opcode/rx.h b/external/gpl3/binutils.old/dist/include/opcode/rx.h index 2d089d73270..54ff409df64 100644 --- a/external/gpl3/binutils.old/dist/include/opcode/rx.h +++ b/external/gpl3/binutils.old/dist/include/opcode/rx.h @@ -1,5 +1,5 @@ /* Opcode decoder for the Renesas RX - Copyright (C) 2008-2016 Free Software Foundation, Inc. + Copyright (C) 2008-2018 Free Software Foundation, Inc. Written by DJ Delorie <dj@redhat.com> This file is part of GDB, the GNU Debugger and GAS, the GNU Assembler. diff --git a/external/gpl3/binutils.old/dist/include/opcode/s390.h b/external/gpl3/binutils.old/dist/include/opcode/s390.h index 1afa86eeda0..db42c58a0a9 100644 --- a/external/gpl3/binutils.old/dist/include/opcode/s390.h +++ b/external/gpl3/binutils.old/dist/include/opcode/s390.h @@ -1,5 +1,5 @@ /* s390.h -- Header file for S390 opcode table - Copyright (C) 2000-2016 Free Software Foundation, Inc. + Copyright (C) 2000-2018 Free Software Foundation, Inc. Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com). This file is part of BFD, the Binary File Descriptor library. @@ -42,14 +42,17 @@ enum s390_opcode_cpu_val S390_OPCODE_Z196, S390_OPCODE_ZEC12, S390_OPCODE_Z13, + S390_OPCODE_ARCH12, S390_OPCODE_MAXCPU }; /* Instruction specific flags. */ #define S390_INSTR_FLAG_OPTPARM 0x1 -#define S390_INSTR_FLAG_HTM 0x2 -#define S390_INSTR_FLAG_VX 0x4 -#define S390_INSTR_FLAG_FACILITY_MASK 0x6 +#define S390_INSTR_FLAG_OPTPARM2 0x2 + +#define S390_INSTR_FLAG_HTM 0x4 +#define S390_INSTR_FLAG_VX 0x8 +#define S390_INSTR_FLAG_FACILITY_MASK 0xc /* The opcode table is an array of struct s390_opcode. */ @@ -154,21 +157,17 @@ extern const struct s390_operand s390_operands[]; /* This operand is a length. */ #define S390_OPERAND_LENGTH 0x200 -/* This operand is optional. Only a single operand at the end of - the instruction may be optional. */ -#define S390_OPERAND_OPTIONAL 0x400 - /* The operand needs to be a valid GP or FP register pair. */ -#define S390_OPERAND_REG_PAIR 0x800 +#define S390_OPERAND_REG_PAIR 0x400 /* This operand names a vector register. The disassembler uses this to print register names with a leading 'v'. */ -#define S390_OPERAND_VR 0x1000 +#define S390_OPERAND_VR 0x800 -#define S390_OPERAND_CP16 0x2000 +#define S390_OPERAND_CP16 0x1000 -#define S390_OPERAND_OR1 0x4000 -#define S390_OPERAND_OR2 0x8000 -#define S390_OPERAND_OR8 0x10000 +#define S390_OPERAND_OR1 0x2000 +#define S390_OPERAND_OR2 0x4000 +#define S390_OPERAND_OR8 0x8000 #endif /* S390_H */ diff --git a/external/gpl3/binutils.old/dist/include/opcode/score-datadep.h b/external/gpl3/binutils.old/dist/include/opcode/score-datadep.h index 4a1ba244290..aba99034cfb 100644 --- a/external/gpl3/binutils.old/dist/include/opcode/score-datadep.h +++ b/external/gpl3/binutils.old/dist/include/opcode/score-datadep.h @@ -1,5 +1,5 @@ /* score-datadep.h -- Score Instructions data dependency table - Copyright (C) 2006-2016 Free Software Foundation, Inc. + Copyright (C) 2006-2018 Free Software Foundation, Inc. Contributed by: Brain.lin (brain.lin@sunplusct.com) Mei Ligang (ligang@sunnorth.com.cn) diff --git a/external/gpl3/binutils.old/dist/include/opcode/score-inst.h b/external/gpl3/binutils.old/dist/include/opcode/score-inst.h index ec5cb8dbb7c..83bdd045ec2 100644 --- a/external/gpl3/binutils.old/dist/include/opcode/score-inst.h +++ b/external/gpl3/binutils.old/dist/include/opcode/score-inst.h @@ -1,5 +1,5 @@ /* score-inst.h -- Score Instructions Table - Copyright (C) 2006-2016 Free Software Foundation, Inc. + Copyright (C) 2006-2018 Free Software Foundation, Inc. Contributed by: Brain.lin (brain.lin@sunplusct.com) Mei Ligang (ligang@sunnorth.com.cn) diff --git a/external/gpl3/binutils.old/dist/include/opcode/sparc.h b/external/gpl3/binutils.old/dist/include/opcode/sparc.h index 7e44408789a..794a9d15ed1 100644 --- a/external/gpl3/binutils.old/dist/include/opcode/sparc.h +++ b/external/gpl3/binutils.old/dist/include/opcode/sparc.h @@ -1,5 +1,5 @@ /* Definitions for opcode table for the sparc. - Copyright (C) 1989-2016 Free Software Foundation, Inc. + Copyright (C) 1989-2018 Free Software Foundation, Inc. This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and the GNU Binutils. @@ -58,7 +58,8 @@ enum sparc_opcode_arch_val SPARC_OPCODE_ARCH_V9V, /* V9 with OSA2011 and T4 additions, integer multiply and Fujitsu fp multiply-add. */ SPARC_OPCODE_ARCH_V9M, /* V9 with OSA2015 and M7 additions. */ - SPARC_OPCODE_ARCH_MAX = SPARC_OPCODE_ARCH_V9M, + SPARC_OPCODE_ARCH_M8, /* V9 with OSA2017 and M8 additions. */ + SPARC_OPCODE_ARCH_MAX = SPARC_OPCODE_ARCH_M8, SPARC_OPCODE_ARCH_BAD /* Error return from sparc_opcode_lookup_arch. */ }; @@ -80,6 +81,10 @@ typedef struct sparc_opcode_arch (SPARC_OPCODE_ARCH_MASK (..._V6) | SPARC_OPCODE_ARCH_MASK (..._V7)). These are short's because sparc_opcode.architecture is. */ short supported; + /* Bitmaps describing the set of hardware capabilities implemented + by the opcode arch. */ + int hwcaps; + int hwcaps2; } sparc_opcode_arch; extern const struct sparc_opcode_arch sparc_opcode_archs[]; @@ -113,6 +118,14 @@ typedef struct sparc_opcode short architecture; /* Bitmask of sparc_opcode_arch_val's. */ } sparc_opcode; +/* Struct for ASIs - to handle ASIs introduced in a specific architecture */ +typedef struct +{ + int value; + const char *name; + short architecture; +} sparc_asi; + /* FIXME: Add F_ANACHRONISTIC flag for v9. */ #define F_DELAYED 0x00000001 /* Delayed branch. */ #define F_ALIAS 0x00000002 /* Alias for a "real" instruction. */ @@ -172,6 +185,15 @@ typedef struct sparc_opcode #define HWCAP2_FJDES 0x00002000 /* Fujitsu DES instrs */ #define HWCAP2_FJAES 0x00010000 /* Fujitsu AES instrs */ +#define HWCAP2_SPARC6 0x00020000 /* OSA2017 new instructions */ +#define HWCAP2_ONADDSUB 0x00040000 /* Oracle Number add/subtract */ +#define HWCAP2_ONMUL 0x00080000 /* Oracle Number multiply */ +#define HWCAP2_ONDIV 0x00100000 /* Oracle Number divide */ +#define HWCAP2_DICTUNP 0x00200000 /* Dictionary unpack instruction */ +#define HWCAP2_FPCMPSHL 0x00400000 /* Partition compare with shifted result */ +#define HWCAP2_RLE 0x00800000 /* Run-length encoded burst and length */ +#define HWCAP2_SHA3 0x01000000 /* SHA3 instruction */ + /* All sparc opcodes are 32 bits, except for the `set' instruction (really a macro), which is 64 bits. It is handled as a special case. @@ -190,15 +212,19 @@ typedef struct sparc_opcode e frs1 floating point register. v frs1 floating point register (double/even). V frs1 floating point register (quad/multiple of 4). + ; frs1 floating piont register (multiple of 8). f frs2 floating point register. B frs2 floating point register (double/even). R frs2 floating point register (quad/multiple of 4). + : frs2 floating point register (multiple of 8). + ' rs2m floating point register (double/even) in FPCMPSHL. (m8) 4 frs3 floating point register. 5 frs3 floating point register (doube/even). g frsd floating point register. H frsd floating point register (double/even). J frsd floating point register (quad/multiple of 4). } frsd floating point register (double/even) that is == frs2 + ^ frsd floating piont register in ON instructions. b crs1 coprocessor register c crs2 coprocessor register D crsd coprocessor register @@ -241,6 +267,7 @@ typedef struct sparc_opcode P %pc. (v9) W %tick. (v9) { %mcdper. (v9b) + & %entropy. (m8) o %asi. (v9) 6 %fcc0. (v9) 7 %fcc1. (v9) @@ -257,7 +284,8 @@ typedef struct sparc_opcode / Ancillary state register in rs1 (v9a) ( entire floating point state register (%efsr) ) 5 bit immediate placed in RS3 field - = 2+8 bit PC relative immediate. (v9) */ + = 2+8 bit PC relative immediate. (v9) + | FPCMPSHL 2 bit immediate. (m8) */ #define OP2(x) (((x) & 0x7) << 22) /* Op2 field of format2 insns. */ #define OP3(x) (((x) & 0x3f) << 19) /* Op3 field of format3 insns. */ @@ -265,6 +293,10 @@ typedef struct sparc_opcode #define OPF(x) (((x) & 0x1ff) << 5) /* Opf field of float insns. */ #define OPF_LOW5(x) OPF ((x) & 0x1f) /* V9. */ #define OPF_LOW4(x) OPF ((x) & 0xf) /* V9. */ +#define OPM(x) (((x) & 0x7) << 10) /* opm field of misaligned load/store insns. */ +#define OPMI(x) (((x) & 0x1) << 9) /* opm i field of misaligned load/store insns. */ +#define ONFCN(x) (((x) & 0x3) << 26) /* fcn field of Oracle Number insns. */ +#define REVFCN(x) (((x) & 0x3) << 0) /* fcn field of REV* insns. */ #define F3F(x, y, z) (OP (x) | OP3 (y) | OPF (z)) /* Format3 float insns. */ #define F3F4(x, y, z) (OP (x) | OP3 (y) | OPF_LOW4 (z)) #define F3I(x) (((x) & 0x1) << 13) /* Immediate field of format 3 insns. */ @@ -275,6 +307,7 @@ typedef struct sparc_opcode #define ASI(x) (((x) & 0xff) << 5) /* Asi field of format3 insns. */ #define RS2(x) ((x) & 0x1f) /* Rs2 field. */ #define SIMM13(x) ((x) & 0x1fff) /* Simm13 field. */ +#define SIMM10(x) ((x) & 0x3ff) /* Simm10 field. */ #define RD(x) (((x) & 0x1f) << 25) /* Destination register field. */ #define RS1(x) (((x) & 0x1f) << 14) /* Rs1 field. */ #define RS3(x) (((x) & 0x1f) << 9) /* Rs3 field. */ @@ -292,7 +325,7 @@ typedef struct sparc_opcode extern const struct sparc_opcode sparc_opcodes[]; extern const int sparc_num_opcodes; -extern int sparc_encode_asi (const char *); +extern const sparc_asi *sparc_encode_asi (const char *); extern const char *sparc_decode_asi (int); extern int sparc_encode_membar (const char *); extern const char *sparc_decode_membar (int); diff --git a/external/gpl3/binutils.old/dist/include/opcode/spu-insns.h b/external/gpl3/binutils.old/dist/include/opcode/spu-insns.h index cdc3679aba0..3cd41b6bf03 100644 --- a/external/gpl3/binutils.old/dist/include/opcode/spu-insns.h +++ b/external/gpl3/binutils.old/dist/include/opcode/spu-insns.h @@ -1,6 +1,6 @@ /* SPU ELF support for BFD. - Copyright (C) 2006-2016 Free Software Foundation, Inc. + Copyright (C) 2006-2018 Free Software Foundation, Inc. This file is part of BFD, the Binary File Descriptor library. diff --git a/external/gpl3/binutils.old/dist/include/opcode/spu.h b/external/gpl3/binutils.old/dist/include/opcode/spu.h index d51a5470873..fc7f5f7f853 100644 --- a/external/gpl3/binutils.old/dist/include/opcode/spu.h +++ b/external/gpl3/binutils.old/dist/include/opcode/spu.h @@ -1,6 +1,6 @@ /* SPU ELF support for BFD. - Copyright (C) 2006-2016 Free Software Foundation, Inc. + Copyright (C) 2006-2018 Free Software Foundation, Inc. This file is part of GDB, GAS, and the GNU binutils. diff --git a/external/gpl3/binutils.old/dist/include/opcode/tahoe.h b/external/gpl3/binutils.old/dist/include/opcode/tahoe.h deleted file mode 100644 index e35f71563d0..00000000000 --- a/external/gpl3/binutils.old/dist/include/opcode/tahoe.h +++ /dev/null @@ -1,232 +0,0 @@ -/* - * Ported by the State University of New York at Buffalo by the Distributed - * Computer Systems Lab, Department of Computer Science, 1991. - */ -/* Copyright (C) 2012-2016 Free Software Foundation, Inc. - - This file is part of GDB and BINUTILS. - - GDB and BINUTILS are free software; you can redistribute them and/or - modify them under the terms of the GNU General Public License as - published by the Free Software Foundation; either version 3, or (at - your option) any later version. - - GDB and BINUTILS are distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - General Public License for more details. - - You should have received a copy of the GNU General Public License - along with GDB or BINUTILS; see the file COPYING3. If not, write - to the Free Software Foundation, 51 Franklin Street - Fifth Floor, - Boston, MA 02110-1301, USA. */ - - -#ifndef tahoe_opcodeT -#define tahoe_opcodeT int -#endif /* no tahoe_opcodeT */ - -struct vot_wot /* tahoe opcode table: wot to do with this */ - /* particular opcode */ -{ - char * args; /* how to compile said opcode */ - tahoe_opcodeT code; /* op-code (may be > 8 bits!) */ -}; - -struct vot /* tahoe opcode text */ -{ - char * name; /* opcode name: lowercase string [key] */ - struct vot_wot detail; /* rest of opcode table [datum] */ -}; - -#define vot_how args -#define vot_code code -#define vot_detail detail -#define vot_name name - -static struct vot -votstrs[] = -{ -{ "halt", {"", 0x00 } }, -{ "sinf", {"", 0x05 } }, -{ "ldf", {"rl", 0x06 } }, -{ "ldd", {"rq", 0x07 } }, -{ "addb2", {"rbmb", 0x08 } }, -{ "movb", {"rbwb", 0x09 } }, -{ "addw2", {"rwmw", 0x0a } }, -{ "movw", {"rwww", 0x0b } }, -{ "addl2", {"rlml", 0x0c } }, -{ "movl", {"rlwl", 0x0d } }, -{ "bbs", {"rlvlbw", 0x0e } }, -{ "nop", {"", 0x10 } }, -{ "brb", {"bb", 0x11 } }, -{ "brw", {"bw", 0x13 } }, -{ "cosf", {"", 0x15 } }, -{ "lnf", {"rl", 0x16 } }, -{ "lnd", {"rq", 0x17 } }, -{ "addb3", {"rbrbwb", 0x18 } }, -{ "cmpb", {"rbwb", 0x19 } }, -{ "addw3", {"rwrwww", 0x1a } }, -{ "cmpw", {"rwww", 0x1b } }, -{ "addl3", {"rlrlwl", 0x1c } }, -{ "cmpl", {"rlwl", 0x1d } }, -{ "bbc", {"rlvlbw", 0x1e } }, -{ "rei", {"", 0x20 } }, -{ "bneq", {"bb", 0x21 } }, -{ "bnequ", {"bb", 0x21 } }, -{ "cvtwl", {"rwwl", 0x23 } }, -{ "stf", {"wl", 0x26 } }, -{ "std", {"wq", 0x27 } }, -{ "subb2", {"rbmb", 0x28 } }, -{ "mcomb", {"rbwb", 0x29 } }, -{ "subw2", {"rwmw", 0x2a } }, -{ "mcomw", {"rwww", 0x2b } }, -{ "subl2", {"rlml", 0x2c } }, -{ "mcoml", {"rlwl", 0x2d } }, -{ "emul", {"rlrlrlwq", 0x2e } }, -{ "aoblss", {"rlmlbw", 0x2f } }, -{ "bpt", {"", 0x30 } }, -{ "beql", {"bb", 0x31 } }, -{ "beqlu", {"bb", 0x31 } }, -{ "cvtwb", {"rwwb", 0x33 } }, -{ "logf", {"", 0x35 } }, -{ "cmpf", {"rl", 0x36 } }, -{ "cmpd", {"rq", 0x37 } }, -{ "subb3", {"rbrbwb", 0x38 } }, -{ "bitb", {"rbrb", 0x39 } }, -{ "subw3", {"rwrwww", 0x3a } }, -{ "bitw", {"rwrw", 0x3b } }, -{ "subl3", {"rlrlwl", 0x3c } }, -{ "bitl", {"rlrl", 0x3d } }, -{ "ediv", {"rlrqwlwl", 0x3e } }, -{ "aobleq", {"rlmlbw", 0x3f } }, -{ "ret", {"", 0x40 } }, -{ "bgtr", {"bb", 0x41 } }, -{ "sqrtf", {"", 0x45 } }, -{ "cmpf2", {"rl", 0x46 } }, -{ "cmpd2", {"rqrq", 0x47 } }, -{ "shll", {"rbrlwl", 0x48 } }, -{ "clrb", {"wb", 0x49 } }, -{ "shlq", {"rbrqwq", 0x4a } }, -{ "clrw", {"ww", 0x4b } }, -{ "mull2", {"rlml", 0x4c } }, -{ "clrl", {"wl", 0x4d } }, -{ "shal", {"rbrlwl", 0x4e } }, -{ "bleq", {"bb", 0x51 } }, -{ "expf", {"", 0x55 } }, -{ "tstf", {"", 0x56 } }, -{ "tstd", {"", 0x57 } }, -{ "shrl", {"rbrlwl", 0x58 } }, -{ "tstb", {"rb", 0x59 } }, -{ "shrq", {"rbrqwq", 0x5a } }, -{ "tstw", {"rw", 0x5b } }, -{ "mull3", {"rlrlwl", 0x5c } }, -{ "tstl", {"rl", 0x5d } }, -{ "shar", {"rbrlwl", 0x5e } }, -{ "bbssi", {"rlmlbw", 0x5f } }, -{ "ldpctx", {"", 0x60 } }, -{ "pushd", {"", 0x67 } }, -{ "incb", {"mb", 0x69 } }, -{ "incw", {"mw", 0x6b } }, -{ "divl2", {"rlml", 0x6c } }, -{ "incl", {"ml", 0x6d } }, -{ "cvtlb", {"rlwb", 0x6f } }, -{ "svpctx", {"", 0x70 } }, -{ "jmp", {"ab", 0x71 } }, -{ "cvlf", {"rl", 0x76 } }, -{ "cvld", {"rl", 0x77 } }, -{ "decb", {"mb", 0x79 } }, -{ "decw", {"mw", 0x7b } }, -{ "divl3", {"rlrlwl", 0x7c } }, -{ "decl", {"ml", 0x7d } }, -{ "cvtlw", {"rlww", 0x7f } }, -{ "bgeq", {"bb", 0x81 } }, -{ "movs2", {"abab", 0x82 } }, -{ "cvfl", {"wl", 0x86 } }, -{ "cvdl", {"wl", 0x87 } }, -{ "orb2", {"rbmb", 0x88 } }, -{ "cvtbl", {"rbwl", 0x89 } }, -{ "orw2", {"rwmw", 0x8a } }, -{ "bispsw", {"rw", 0x8b } }, -{ "orl2", {"rlml", 0x8c } }, -{ "adwc", {"rlml", 0x8d } }, -{ "adda", {"rlml", 0x8e } }, -{ "blss", {"bb", 0x91 } }, -{ "cmps2", {"abab", 0x92 } }, -{ "ldfd", {"rl", 0x97 } }, -{ "orb3", {"rbrbwb", 0x98 } }, -{ "cvtbw", {"rbww", 0x99 } }, -{ "orw3", {"rwrwww", 0x9a } }, -{ "bicpsw", {"rw", 0x9b } }, -{ "orl3", {"rlrlwl", 0x9c } }, -{ "sbwc", {"rlml", 0x9d } }, -{ "suba", {"rlml", 0x9e } }, -{ "bgtru", {"bb", 0xa1 } }, -{ "cvdf", {"", 0xa6 } }, -{ "andb2", {"rbmb", 0xa8 } }, -{ "movzbl", {"rbwl", 0xa9 } }, -{ "andw2", {"rwmw", 0xaa } }, -{ "loadr", {"rwal", 0xab } }, -{ "andl2", {"rlml", 0xac } }, -{ "mtpr", {"rlrl", 0xad } }, -{ "ffs", {"rlwl", 0xae } }, -{ "blequ", {"bb", 0xb1 } }, -{ "negf", {"", 0xb6 } }, -{ "negd", {"", 0xb7 } }, -{ "andb3", {"rbrbwb", 0xb8 } }, -{ "movzbw", {"rbww", 0xb9 } }, -{ "andw3", {"rwrwww", 0xba } }, -{ "storer", {"rwal", 0xbb } }, -{ "andl3", {"rlrlwl", 0xbc } }, -{ "mfpr", {"rlwl", 0xbd } }, -{ "ffc", {"rlwl", 0xbe } }, -{ "calls", {"rbab", 0xbf } }, -{ "prober", {"rbabrl", 0xc0 } }, -{ "bvc", {"bb", 0xc1 } }, -{ "movs3", {"ababrw", 0xc2 } }, -{ "movzwl", {"rwwl", 0xc3 } }, -{ "addf", {"rl", 0xc6 } }, -{ "addd", {"rq", 0xc7 } }, -{ "xorb2", {"rbmb", 0xc8 } }, -{ "movob", {"rbwb", 0xc9 } }, -{ "xorw2", {"rwmw", 0xca } }, -{ "movow", {"rwww", 0xcb } }, -{ "xorl2", {"rlml", 0xcc } }, -{ "movpsl", {"wl", 0xcd } }, -{ "kcall", {"rw", 0xcf } }, -{ "probew", {"rbabrl", 0xd0 } }, -{ "bvs", {"bb", 0xd1 } }, -{ "cmps3", {"ababrw", 0xd2 } }, -{ "subf", {"rq", 0xd6 } }, -{ "subd", {"rq", 0xd7 } }, -{ "xorb3", {"rbrbwb", 0xd8 } }, -{ "pushb", {"rb", 0xd9 } }, -{ "xorw3", {"rwrwww", 0xda } }, -{ "pushw", {"rw", 0xdb } }, -{ "xorl3", {"rlrlwl", 0xdc } }, -{ "pushl", {"rl", 0xdd } }, -{ "insque", {"abab", 0xe0 } }, -{ "bcs", {"bb", 0xe1 } }, -{ "bgequ", {"bb", 0xe1 } }, -{ "mulf", {"rq", 0xe6 } }, -{ "muld", {"rq", 0xe7 } }, -{ "mnegb", {"rbwb", 0xe8 } }, -{ "movab", {"abwl", 0xe9 } }, -{ "mnegw", {"rwww", 0xea } }, -{ "movaw", {"awwl", 0xeb } }, -{ "mnegl", {"rlwl", 0xec } }, -{ "moval", {"alwl", 0xed } }, -{ "remque", {"ab", 0xf0 } }, -{ "bcc", {"bb", 0xf1 } }, -{ "blssu", {"bb", 0xf1 } }, -{ "divf", {"rq", 0xf6 } }, -{ "divd", {"rq", 0xf7 } }, -{ "movblk", {"alalrw", 0xf8 } }, -{ "pushab", {"ab", 0xf9 } }, -{ "pushaw", {"aw", 0xfb } }, -{ "casel", {"rlrlrl", 0xfc } }, -{ "pushal", {"al", 0xfd } }, -{ "callf", {"rbab", 0xfe } }, -{ "" , "" } /* empty is end sentinel */ - -}; diff --git a/external/gpl3/binutils.old/dist/include/opcode/tic30.h b/external/gpl3/binutils.old/dist/include/opcode/tic30.h index 1ca2f8b0a2b..30123bb3bd3 100644 --- a/external/gpl3/binutils.old/dist/include/opcode/tic30.h +++ b/external/gpl3/binutils.old/dist/include/opcode/tic30.h @@ -1,5 +1,5 @@ /* tic30.h -- Header file for TI TMS320C30 opcode table - Copyright (C) 1998-2016 Free Software Foundation, Inc. + Copyright (C) 1998-2018 Free Software Foundation, Inc. Contributed by Steven Haworth (steve@pm.cse.rmit.edu.au) This file is part of GDB, GAS, and the GNU binutils. diff --git a/external/gpl3/binutils.old/dist/include/opcode/tic4x.h b/external/gpl3/binutils.old/dist/include/opcode/tic4x.h index b4209a1deb1..30254123653 100644 --- a/external/gpl3/binutils.old/dist/include/opcode/tic4x.h +++ b/external/gpl3/binutils.old/dist/include/opcode/tic4x.h @@ -1,6 +1,6 @@ /* Table of opcodes for the Texas Instruments TMS320C[34]X family. - Copyright (C) 2002-2016 Free Software Foundation, Inc. + Copyright (C) 2002-2018 Free Software Foundation, Inc. Contributed by Michael P. Hayes (m.hayes@elec.canterbury.ac.nz) diff --git a/external/gpl3/binutils.old/dist/include/opcode/tic54x.h b/external/gpl3/binutils.old/dist/include/opcode/tic54x.h index b0af407c9ea..8c147123b22 100644 --- a/external/gpl3/binutils.old/dist/include/opcode/tic54x.h +++ b/external/gpl3/binutils.old/dist/include/opcode/tic54x.h @@ -1,5 +1,5 @@ /* tic54x.h -- Header file for TI TMS320C54X opcode table - Copyright (C) 1999-2016 Free Software Foundation, Inc. + Copyright (C) 1999-2018 Free Software Foundation, Inc. Written by Timothy Wall (twall@cygnus.com) This file is part of GDB, GAS, and the GNU binutils. diff --git a/external/gpl3/binutils.old/dist/include/opcode/tic6x-control-registers.h b/external/gpl3/binutils.old/dist/include/opcode/tic6x-control-registers.h index fead0820dce..fc5cfa6f387 100644 --- a/external/gpl3/binutils.old/dist/include/opcode/tic6x-control-registers.h +++ b/external/gpl3/binutils.old/dist/include/opcode/tic6x-control-registers.h @@ -1,5 +1,5 @@ /* TI C6X control register information. - Copyright (C) 2010-2016 Free Software Foundation, Inc. + Copyright (C) 2010-2018 Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by diff --git a/external/gpl3/binutils.old/dist/include/opcode/tic6x-insn-formats.h b/external/gpl3/binutils.old/dist/include/opcode/tic6x-insn-formats.h index f93142f25e6..7e93fd3947c 100644 --- a/external/gpl3/binutils.old/dist/include/opcode/tic6x-insn-formats.h +++ b/external/gpl3/binutils.old/dist/include/opcode/tic6x-insn-formats.h @@ -1,5 +1,5 @@ /* TI C6X instruction format information. - Copyright (C) 2010-2016 Free Software Foundation, Inc. + Copyright (C) 2010-2018 Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by diff --git a/external/gpl3/binutils.old/dist/include/opcode/tic6x-opcode-table.h b/external/gpl3/binutils.old/dist/include/opcode/tic6x-opcode-table.h index c9bf0666fb0..2a7e6905dac 100644 --- a/external/gpl3/binutils.old/dist/include/opcode/tic6x-opcode-table.h +++ b/external/gpl3/binutils.old/dist/include/opcode/tic6x-opcode-table.h @@ -1,5 +1,5 @@ /* TI C6X opcode table. - Copyright (C) 2010-2016 Free Software Foundation, Inc. + Copyright (C) 2010-2018 Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by diff --git a/external/gpl3/binutils.old/dist/include/opcode/tic6x.h b/external/gpl3/binutils.old/dist/include/opcode/tic6x.h index 3a9a63ad65c..3347eaee75d 100644 --- a/external/gpl3/binutils.old/dist/include/opcode/tic6x.h +++ b/external/gpl3/binutils.old/dist/include/opcode/tic6x.h @@ -1,5 +1,5 @@ /* TI C6X opcode information. - Copyright (C) 2010-2016 Free Software Foundation, Inc. + Copyright (C) 2010-2018 Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by diff --git a/external/gpl3/binutils.old/dist/include/opcode/tic80.h b/external/gpl3/binutils.old/dist/include/opcode/tic80.h index 510da051079..71230e7dac2 100644 --- a/external/gpl3/binutils.old/dist/include/opcode/tic80.h +++ b/external/gpl3/binutils.old/dist/include/opcode/tic80.h @@ -1,5 +1,5 @@ /* tic80.h -- Header file for TI TMS320C80 (MV) opcode table - Copyright (C) 1996-2016 Free Software Foundation, Inc. + Copyright (C) 1996-2018 Free Software Foundation, Inc. Written by Fred Fish (fnf@cygnus.com), Cygnus Support This file is part of GDB, GAS, and the GNU binutils. diff --git a/external/gpl3/binutils.old/dist/include/opcode/tilegx.h b/external/gpl3/binutils.old/dist/include/opcode/tilegx.h index 598541032c1..78bbfcdee70 100644 --- a/external/gpl3/binutils.old/dist/include/opcode/tilegx.h +++ b/external/gpl3/binutils.old/dist/include/opcode/tilegx.h @@ -1,6 +1,6 @@ /* TILE-Gx opcode information. * - * Copyright (C) 2011-2016 Free Software Foundation, Inc. + * Copyright (C) 2011-2018 Free Software Foundation, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/external/gpl3/binutils.old/dist/include/opcode/tilepro.h b/external/gpl3/binutils.old/dist/include/opcode/tilepro.h index 96f20307ef9..38e5013b158 100644 --- a/external/gpl3/binutils.old/dist/include/opcode/tilepro.h +++ b/external/gpl3/binutils.old/dist/include/opcode/tilepro.h @@ -1,6 +1,6 @@ /* TILEPro opcode information. * - * Copyright (C) 2011-2016 Free Software Foundation, Inc. + * Copyright (C) 2011-2018 Free Software Foundation, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/external/gpl3/binutils.old/dist/include/opcode/v850.h b/external/gpl3/binutils.old/dist/include/opcode/v850.h index 5e317da57ee..92a64c9b0a2 100644 --- a/external/gpl3/binutils.old/dist/include/opcode/v850.h +++ b/external/gpl3/binutils.old/dist/include/opcode/v850.h @@ -1,5 +1,5 @@ /* v850.h -- Header file for NEC V850 opcode table - Copyright (C) 1996-2016 Free Software Foundation, Inc. + Copyright (C) 1996-2018 Free Software Foundation, Inc. Written by J.T. Conklin, Cygnus Support This file is part of GDB, GAS, and the GNU binutils. @@ -230,10 +230,10 @@ extern const struct v850_operand v850_operands[]; /* The operand has '%' prefix. */ #define V850_OPERAND_PERCENT 0x200000 -/* This operand is a cache oparation. */ +/* This operand is a cache operation. */ #define V850_OPERAND_CACHEOP 0x400000 -/* This operand is a prefetch oparation. */ +/* This operand is a prefetch operation. */ #define V850_OPERAND_PREFOP 0x800000 /* A PC-relative displacement where a positive value indicates a backwards displacement. */ diff --git a/external/gpl3/binutils.old/dist/include/opcode/vax.h b/external/gpl3/binutils.old/dist/include/opcode/vax.h index 6649e2b6a13..fbbf4f9372f 100644 --- a/external/gpl3/binutils.old/dist/include/opcode/vax.h +++ b/external/gpl3/binutils.old/dist/include/opcode/vax.h @@ -1,5 +1,5 @@ /* Vax opcde list. - Copyright (C) 1989-2016 Free Software Foundation, Inc. + Copyright (C) 1989-2018 Free Software Foundation, Inc. This file is part of GDB and GAS. diff --git a/external/gpl3/binutils.old/dist/include/opcode/visium.h b/external/gpl3/binutils.old/dist/include/opcode/visium.h index bc8a2b76dd3..243ac957b4c 100644 --- a/external/gpl3/binutils.old/dist/include/opcode/visium.h +++ b/external/gpl3/binutils.old/dist/include/opcode/visium.h @@ -1,6 +1,6 @@ /* Opcode table header for Visium. - Copyright (C) 2003-2016 Free Software Foundation, Inc. + Copyright (C) 2003-2018 Free Software Foundation, Inc. This file is part of GDB, GAS, and GNU binutils. diff --git a/external/gpl3/binutils.old/dist/include/opcode/xgate.h b/external/gpl3/binutils.old/dist/include/opcode/xgate.h index 737c0d9e834..8d45480215c 100644 --- a/external/gpl3/binutils.old/dist/include/opcode/xgate.h +++ b/external/gpl3/binutils.old/dist/include/opcode/xgate.h @@ -1,5 +1,5 @@ /* xgate.h -- Freescale XGATE opcode list - Copyright (C) 2010-2016 Free Software Foundation, Inc. + Copyright (C) 2010-2018 Free Software Foundation, Inc. Written by Sean Keys (skeys@ipdatasys.com) This file is part of the GNU opcodes library. @@ -29,14 +29,14 @@ #define XGATE_C_BIT 0x01 /* XGC - Carry Flag */ /* Access Detail Notation - V — Vector fetch: always an aligned word read, lasts for at least one RISC core cycle - P — Program word fetch: always an aligned word read, lasts for at least one RISC core cycle - r — 8-bit data read: lasts for at least one RISC core cycle - R — 16-bit data read: lasts for at least one RISC core cycle - w — 8-bit data write: lasts for at least one RISC core cycle - W — 16-bit data write: lasts for at least one RISC core cycle - A — Alignment cycle: no read or write, lasts for zero or one RISC core cycles - f — Free cycle: no read or write, lasts for one RISC core cycles. */ + V - Vector fetch: always an aligned word read, lasts for at least one RISC core cycle + P - Program word fetch: always an aligned word read, lasts for at least one RISC core cycle + r - 8-bit data read: lasts for at least one RISC core cycle + R - 16-bit data read: lasts for at least one RISC core cycle + w - 8-bit data write: lasts for at least one RISC core cycle + W - 16-bit data write: lasts for at least one RISC core cycle + A - Alignment cycle: no read or write, lasts for zero or one RISC core cycles + f - Free cycle: no read or write, lasts for one RISC core cycles. */ #define XGATE_CYCLE_V 0x01 #define XGATE_CYCLE_P 0x02 #define XGATE_CYCLE_r 0x04 |
