diff options
| author | christos <christos@NetBSD.org> | 2022-12-23 19:00:44 +0000 |
|---|---|---|
| committer | christos <christos@NetBSD.org> | 2022-12-23 19:00:44 +0000 |
| commit | f22f0ef4091609aa3a6b17544204fc90df3efe19 (patch) | |
| tree | 0818cbaf63718f7659f5a62e0def16451948be60 /external/gpl3/binutils/dist/include/opcode | |
| parent | 6f732d6582cf3097c7f1a98490f52af220016a0b (diff) | |
Update binutils from 2.34 to 2.39
2022-07-08 Nick Clifton <nickc@redhat.com>
* 2.39 branch created.
2022-07-04 Nick Clifton <nickc@redhat.com>
* libiberty: Synchronize with GCC. Bring in:
2022-07-01 Nick Clifton <nickc@redhat.com>
PR demangler/105039
* rust-demangle.c (demangle_const): Add recursion limit.
2022-06-26 Simon Marchi <simon.marchi@efficios.com>
* configure.ac: Add AC_CONFIG_MACRO_DIRS call.
* configure: Re-generate.
2022-04-12 Nick Clifton <nickc@redhat.com>
* zlib: Rebase to the 1.2.12 release.
2022-04-08 Simon Marchi <simon.marchi@efficios.com>
* configure.ac: Add AC_SUBST(PKG_CONFIG_PATH).
* configure: Re-generate.
* Makefile.tpl (HOST_EXPORTS): Pass PKG_CONFIG_PATH.
(PKG_CONFIG_PATH): New.
* Makefile.in: Re-generate.
2022-03-15 Jose E. Marchesi <jose.marchesi@oracle.com>
* gprofng/src/gp-collect-app.cc (collect::check_args): Use
fallthrough comment instead of attribute.
2022-03-11 Vladimir Mezentsev <vladimir.mezentsev@oracle.com>
* Makefile.def: Add gprofng module.
* configure.ac: Add --enable-gprofng option.
* src-release.sh: Add gprofng.
* Makefile.in: Regenerate.
* configure: Regenerate.
* gprofng: New directory.
2022-01-22 Nick Clifton <nickc@redhat.com>
* 2.38 release branch created.
2022-01-17 Nick Clifton <nickc@redhat.com>
Update config.[guess|sub] from upstream:
2022-01-09 Idan Horowitz <idan.horowitz@gmail.com>
config.guess: recognize SerenityOS
* config.guess (*:SerenityOS:*:*): Recognize.
(timestamp): Update.
2022-01-03 Bernhard Voelker <mail@bernhard-voelker.de>
Fix GPLv3 license headers to use a comma instead of semicolon
See: https://www.gnu.org/licenses/gpl-3.0.html#howto
Update license headers automatically using the following script:
$ git grep -l 'Foundation; either version 3' \
| xargs sed -i '/Foundation; either version 3/ s/n; e/n, e/'
* config.guess: Adjust via the above command.
(timestamp): Update.
* config.sub: Likewise.
* doc/config.guess.1: Regenerate.
* doc/config.sub.1: Likewise.
2022-01-01 Dmitry V. Levin <ldv@altlinux.org>
Update copyright years
* config.guess: Update copyright years.
* config.sub: Likewise.
2021-12-25 Dmitry V. Levin <ldv@altlinux.org>
config.sub: alias armh to armv7l
ALT uses armh as an alias for armv7l-alt-linux-gnueabihf since 2012.
* config.sub (armh-unknown|armh-alt): Set cpu, vendor, and basic_os.
(timestamp): Update.
2021-12-24 Dmitry V. Levin <ldv@altlinux.org>
config.sub: alias aarch64le to aarch64
Apparently, QNX reports aarch64 as aarch64le on little-endian machines.
* config.sub (aarch64le-*): Set cpu to aarch64.
(timestamp): Update.
2021-12-13 Dmitry V. Levin <ldv@altlinux.org>
config.sub: fix typo in timestamp
* config.sub: Fix timestamp.
2021-11-30 Andreas F. Borchert <github@andreas-borchert.de>
config.guess: x86_64-pc-solaris2.11 is not properly recognized
config.guess guesses Solaris 11 to run on a 32-bit platform
despite Solaris 11 no longer supporting any 32-bit platform.
See the following code at lines 434 to 445:
| SUN_ARCH=i386
| # If there is a compiler, see if it is configured for 64-bit objects.
| # Note that the Sun cc does not turn __LP64__ into 1 like gcc does.
| # This test works for both compilers.
| if test "$CC_FOR_BUILD" != no_compiler_found; then
| if (echo '#ifdef __amd64'; echo IS_64BIT_ARCH; echo '#endif') | \
| (CCOPTS="" $CC_FOR_BUILD -E - 2>/dev/null) | \
| grep IS_64BIT_ARCH >/dev/null
| then
| SUN_ARCH=x86_64
| fi
| fi
If "cc" is installed, i.e. the Oracle Studio compiler, this one is
chosen for $CC_FOR_BUILD. This compiler, the gcc provided by Oracle
and also gcc bootstrapped from sources on that platform with a default
configuration will by default generate 32-bit binaries -- even on
a 64-bit platform. And __amd64 will not be defined for compilations
targeting a 32-bit platform. This is different from the corresponding
behaviour on GNU/Linux systems where the local platform is targeted by
default.
Thus, as long as you do not add "-m64" or if you have a custom-built
gcc which defaults to 64 bit, you will get 32-bit binaries on Solaris
despite living on a 64-bit platform.
* config.guess (i86pc:SunOS:5.*:* || i86xen:SunOS:5.*:*): Adapt the
test by adding the "-m64" flag. This will work properly for Solaris
10 as well (the last Solaris release that supported x86 32-bit
platforms).
2021-10-27 Jordi Sanfeliu <jordi@fibranet.cat>
Recognize Fiwix
$ make check
cd testsuite && bash config-guess.sh && rm uname
PASS: config.guess checks (137 tests)
cd testsuite && bash config-sub.sh
PASS: config.sub checks (882 tests)
PASS: config.sub idempotency checks (819 tests)
PASS: config.sub canonicalise each config.guess testcase (137 tests)
* config.guess (i*86:Fiwix:*:*): Recognize.
* config.sub (fiwix*): Likewise.
2021-10-18 Kinshuk Dua <kinshukdua@gmail.com>
config.sub: Fix typo in comment
Fixes: 5e531d391852a54e7fab2d8ff55625fca514b305
2021-08-14 Nick Bowler <nbowler@draconx.ca>
config.sub: work around command assignment bug in some shells
When combining variable assignments with a shell command, some older
shells (notably heirloom-sh and presumably also Solaris 10 /bin/sh)
have a bug which causes the assignment to alter the current execution
environment whenever the command is a shell built-in. For example:
% dash -c 'x=good; x=bad echo >/dev/null; echo $x'
good
% jsh -c 'x=good; x=bad echo >/dev/null; echo $x'
bad
The config.sub script contains a few commands of the form:
IFS=- read ...
which triggers this bug, causing the IFS assignment to persist for the
remainder of the script. This can cause misbehaviour in certain cases,
for example:
% jsh config.sub i386-linux-gnu
config.sub: test: unknown operator gnu
% jsh config.sub i386-gnu/linux
sed: can't read s|gnu/linux|gnu|: No such file or directory
Invalid configuration `i386-gnu/linux': OS `' not recognized
* config.sub: Save and restore IFS explicitly to avoid shell bugs.
* doc/config.sub.1: Regenerate.
2021-08-04 Jeremy Soller <jackpot51@gmail.com>
config.sub: add Linux Relibc Target
$ make check
cd testsuite && bash config-guess.sh && rm uname
PASS: config.guess checks (136 tests)
cd testsuite && bash config-sub.sh
PASS: config.sub checks (881 tests)
PASS: config.sub idempotency checks (818 tests)
PASS: config.sub canonicalise each config.guess testcase (136 tests)
* config.sub (relibc*): Recognize.
* doc/config.sub.1: Regenerate.
* testsuite/config-sub.data (x86_64-linux-relibc): New test.
2021-07-06 Stephanos Ioannidis <root@stephanos.io>
config.sub: add Zephyr RTOS support
This adds the Zephyr RTOS targets in preparation for implementing the
Zephyr RTOS-specific toolchain support.
$ make check
cd testsuite && bash config-guess.sh && rm uname
PASS: config.guess checks (136 tests)
cd testsuite && bash config-sub.sh
PASS: config.sub checks (880 tests)
PASS: config.sub idempotency checks (817 tests)
PASS: config.sub canonicalise each config.guess testcase (136 tests)
* config.sub (zephyr*): Recognize.
* doc/config.sub.1: Regenerate.
* testsuite/config-sub.data: Add testcases for *-zephyr.
2021-07-03 Ozkan Sezer <sezero@users.sourceforge.net>
config.sub: disable shellcheck SC2006 / SC2268 warnings
This is in line with the recent config.guess change in commit
12fcf67c9108f4c4b581eaa302088782f0ee40ea
* config.sub (shellcheck disable): Add SC2006,SC2268.
Suggested-by: Jacob Bachmeyer <jcb@gnu.org>
2021-07-03 Ozkan Sezer <sezero@users.sourceforge.net>
config.sub: normalize the quoting in the `echo FOO | sed ...`
Some cases quote the argument to echo and some do not. At runtime
it probably does not matter because the substituted values will never
contain whitespace, but quoting them all would make shellcheck more
useful.
* config.sub: Consistently quote the argument of echo.
* doc/config.sub.1: Regenerate.
Suggested-by: Jacob Bachmeyer <jcb@gnu.org>
2021-07-02 Ozkan Sezer <sezero@users.sourceforge.net>
config.sub: replace POSIX $( ) with classic ` ` throughout
This is in line with the recent config.guess change in commit
d70c4fa934de164178054c3a60aaa0024ed07c91.
The patch was generated using patch-6.gawk script introduced in that
commit.
* config.sub: Revert POSIX command substitutions to classic form.
2021-06-04 Vineet Gupta <Vineet.Gupta1@synopsys.com>
Recognize arc32
This is the 32-bit variant of ARCv3 ISA (which is not compatible with the
32-bit ARCv2 ISA)
| make check
| cd testsuite && bash config-guess.sh && rm uname
| PASS: config.guess checks (136 tests)
| cd testsuite && bash config-sub.sh
| PASS: config.sub checks (864 tests)
| PASS: config.sub idempotency checks (801 tests)
| PASS: config.sub canonicalise each config.guess testcase (136 tests)
* config.guess (arc32:Linux:*:*): Recognize.
* config.sub (arc32): Likewise.
2021-05-27 Jacob Bachmeyer <jcb@gnu.org>
Remove automatic patch generators
These tools have served their purposes and need not be kept outside of
the repository history any longer. This patch as a diff also collects
the contents of the various tools in one convenient place.
* patch-1.gawk: Remove.
* patch-3.gawk: Likewise.
* patch-6.gawk: Likewise.
2021-05-26 Jacob Bachmeyer <jcb@gnu.org>
config.guess: manual fixups after previous automatic patch
The tool could not handle command substitutions that span lines, but
fortunately there were only two such substitutions in the script.
The test for which universe is active on Pyramid is rewritten into a
case block because it was the only use of a command substitution as an
argument to the test command, which would require quoting.
* config.guess: Rewrite "if" for Pyramid systems to "case".
2021-05-26 Jacob Bachmeyer <jcb@gnu.org>
config.guess: replace POSIX $( ) with classic ` ` throughout
The previous replacement of backticks with POSIX command substitutions
was ill-considered and illogical: this script recognizes many archaic
machine types that probably never had POSIX shells, therefore it needs
to be able to run successfully under pre-POSIX shells.
This patch was generated using the included GNU Awk program.
* config.guess: Revert POSIX command substitutions to classic form.
* patch-6.gawk: Store the tool that produced the automated patch.
2021-05-26 Jacob Bachmeyer <jcb@gnu.org>
config.guess: manual fixup after previous automated patches
This patch provides the special handling for the GNU system. As these
were two small and unique edits, they were not included in the scripts.
This patch also cleans up other minor issues that must be addressed
before reverting to classic command substitutions and updates
"shellcheck" directives to account for changes in this script and the
change in "shellcheck" towards reporting individual portability issues.
2021-05-26 Jacob Bachmeyer <jcb@gnu.org>
config.guess: automatic fixups after previous automated patch
This patch was generated using the following command:
sed -i config.guess \
-e '/="[^"]\+"\(-\|$\)/s/="\([^"([:space:])]\+\)"/=\1/' \
-e '/="[^"]\+"[[:alnum:]]/s/="\$\([^([:space:])]\+\)"/=${\1}/' \
-e \
'/\$(echo[^|]\+|/s/\([^[:space:]]\)[[:space:]]*|[[:space:]]*sed/\1 | sed/g'
* config.guess: Remove unneeded quotes in other variable assignments,
standardize spacing for "echo ... | sed" substitutions.
2021-05-26 Jacob Bachmeyer <jcb@gnu.org>
config.guess: remove unneeded quotes and factor command substitutions
This is further cleanup and simplifies some constructs that can confuse
Emacs' syntax highlighting while generally reducing required quoting.
This patch was generated using the included GNU Awk program.
* config.guess: Remove unneeded variable quotes and factor out command
substitutions when setting GUESS.
* patch-3.gawk: Store the tool that produced the automated patch.
2021-05-25 Jacob Bachmeyer <jcb@gnu.org>
config.guess: manual fixups after previous automatic patch
* config.guess: Adjust a few "leftover" cases that the tool could not
easily recognize and fixes comment indentation in a few other special
cases.
2021-05-25 Jacob Bachmeyer <jcb@gnu.org>
config.guess: use intermediate variable with uname results
This will allow quoting to be significantly simplified in another
pass through the file.
This patch was generated using the included GNU Awk program.
* config.guess: Use GUESS variable to hold results of uname analysis.
* patch-1.gawk: Store the tool that produced the automated patch.
2021-05-25 Jacob Bachmeyer <jcb@gnu.org>
config.guess: introduce intermediate variable with uname results
This will allow quoting to be significantly simplified in another
pass through the file.
* config.guess: Introduce GUESS variable to hold results of uname analysis.
2021-05-24 Dmitry V. Levin <ldv@altlinux.org>
config.guess: fix shellcheck warning SC2154
While, according to Plan 9 documentation, the environment variable
$cputype is set to the name of the kernel's CPU's architecture,
shellcheck warns that cputype is referenced but not assigned.
Be on the safe side and do not use cputype if it is not defined
or empty.
* config.guess (*:Plan9:*:*): Fix shellcheck warning SC2154.
2021-05-24 Dmitry V. Levin <ldv@altlinux.org>
config.guess: remove redundant quotes in case commands
According to the GNU Autoconf Portable Shell Programming manual,
the Bourne shell does not systematically split variables and back-quoted
expressions, in particular on the right-hand side of assignments and in
the argument of 'case'.
The change is made automatically using the following command:
$ sed -E -i 's/(\<case )"(\$[^"]+)"( in\>)/\1\2\3/' config.guess
* config.guess: Simplify case commands by removing quotes around the
argument.
Suggested-by: Jacob Bachmeyer <jcb@gnu.org>
2021-05-24 Dmitry V. Levin <ldv@altlinux.org>
config.guess: simplify exit status workaround on alphaev67-dec-osf5.1
Commit 29865ea8a5622cdd80b7a69a0afa78004b4cd311 introduced an exit trap
reset before exiting to avoid a spurious non-zero exit status on
alphaev67-dec-osf5.1. Simplify that code a bit by moving the exit trap
reset around.
* config.guess (alpha:OSF1:*:*): Reset exit trap earlier.
* doc/config.guess.1: Regenerate.
2021-10-29 Eli Zaretskii <eliz@gnu.org>
* gdb/doc/gdb.texinfo (Command Options): (Data): Document
'-memory-tag-violations'. Update the example.
2021-09-28 Andrew Burgess <andrew.burgess@embecosm.com>
* src-release.sh (GDB_SUPPPORT_DIRS): Add libbacktrace.
2021-09-27 Nick Alcock <nick.alcock@oracle.com>
PR libctf/27967
* libtool.m4 (LT_PATH_NM): Try BSDization flags with a user-provided
NM, if there is one. Run nm on itself, not on /dev/null, to avoid
errors from nms that refuse to work on non-regular files. Remove
other workarounds for this problem. Strip out blank lines from the
nm output.
2021-09-27 Nick Alcock <nick.alcock@oracle.com>
PR libctf/27967
* libtool.m4 (lt_cv_sys_global_symbol_pipe): Augment symcode for
Solaris 11.
2021-07-03 Nick Clifton <nickc@redhat.com>
* 2.37 release branch created.
2021-07-03 Nick Clifton <nickc@redhat.com>
* libiberty: Sync with gcc. Bring in:
2021-06-30 Gerald Pfeifer <gerald@pfeifer.com>
* make-temp-file.c (usrtmp): Remove.
(choose_tmpdir): Remove use of usrtmp.
2021-06-28 Indu Bhagat <indu.bhagat@oracle.com>
* simple-object.c (handle_lto_debug_sections): Copy over .BTF section.
2021-06-28 Indu Bhagat <indu.bhagat@oracle.com>
David Faust <david.faust@oracle.com>
Jose E. Marchesi <jose.marchesi@oracle.com>
Weimin Pan <weimin.pan@oracle.com>
* simple-object.c (handle_lto_debug_sections): Copy over .ctf
sections.
2021-06-05 John David Anglin <danglin@gcc.gnu.org>
PR target/100734
* configure.ac: Use libiberty snprintf and vsnprintf on
hppa*-*-hpux*.
* configure: Regenerate.
2021-05-06 Tom Tromey <tom@tromey.com>
* hashtab.c (htab_eq_string): New function.
2021-05-04 Eric Botcazou <ebotcazou@adacore.com>
* configure.ac: Make test for variables more robust.
* configure: Regenerate.
2021-05-03 H.J. Lu <hjl.tools@gmail.com>
PR bootstrap/99703
* configure: Regenerated.
2021-04-21 Andreas Schwab <schwab@linux-m68k.org>
PR demangler/100177
* rust-demangle.c (demangle_const_char): Properly print the
character value.
2021-03-31 Patrick Palka <ppalka@redhat.com>
PR c++/88115
* cp-demangle.c (d_dump, d_make_comp, d_expression_1)
(d_count_templates_scopes): Handle DEMANGLE_COMPONENT_VENDOR_EXPR.
(d_print_comp_inner): Likewise.
<case DEMANGLE_COMPONENT_EXTENDED_OPERATOR>: Revert r11-4926
change.
<case DEMANGLE_COMPONENT_UNARY>: Likewise.
* testsuite/demangle-expected: Adjust __alignof__ tests.
2021-03-16 Nick Clifton <nickc@redhat.com>
* sha1.c (sha1_process_bytes): Use memmove in place of memcpy.
2021-02-20 Mike Frysinger <vapier@gentoo.org>
* Makefile.in (ACLOCAL, ACLOCAL_AMFLAGS, $(srcdir)/aclocal.m4): Define.
(configure_deps): Rename to ...
(aclocal_deps): ... this. Replace aclocal.m4 with acinclude.m4.
($(srcdir)/configure): Replace $(configure_deps) with
$(srcdir)/aclocal.m4.
* aclocal.m4: Move libiberty macros to acinclude.m4, then regenerate.
* acinclude.m4: New file.
* configure: Regenerate.
2021-02-19 Ayush Mittal <ayush.m@samsung.com>
* argv.c (expandargv): free allocated buffer if read fails.
2021-02-01 Martin Sebor <msebor@redhat.com>
* dyn-string.c (dyn_string_insert_cstr): Use memcpy instead of strncpy
to avoid -Wstringop-truncation.
2021-05-29 Mike Frysinger <vapier@gentoo.org>
* configure.ac: Add gnulib to configdirs for sim.
* configure: Regenerate.
2021-05-24 Maciej W. Rozycki <macro@orcam.me.uk>
* MAINTAINERS: Update path to readline config.{sub,guess} files.
2021-05-24 Maciej W. Rozycki <macro@orcam.me.uk>
* config.guess: Import from upstream.
* config.sub: Likewise.
2021-05-18 Mike Frysinger <vapier@gentoo.org>
* Makefile.def: Add configure-sim dependency on all-gnulib.
* Makefile.in: Regenerated.
2021-05-04 Nick Clifton <nickc@redhat.com>
* configure.ac (AC_PROG_CC): Replace with AC_PROG_CC_C99.
* configure: Regenerate.
2021-03-18 Nick Alcock <nick.alcock@oracle.com>
PR libctf/27482
* Makefile.def: Add install-bfd dependencies for install-libctf and
install-ld, and install-strip-bfd dependencies for
install-strip-libctf and install-strip-ld; move the install-ld
dependency on install-libctf to join it.
* Makefile.in: Regenerated.
2021-03-12 Mike Frysinger <vapier@gentoo.org>
* Makefile.def: Remove all-sim dependency on configure-gdb.
* Makefile.in: Regenerated.
2021-02-28 H.J. Lu <hongjiu.lu@intel.com>
PR binutils/26766
* Makefile.tpl (PGO_BUILD_TRAINING_FLAGS_TO_PASS): Add
PGO_BUILD_TRAINING=yes.
(PGO_BUILD_TRAINING_MFLAGS): New.
(all): Pass $(PGO_BUILD_TRAINING_MFLAGS) to the PGO build.
2021-02-09 Alan Modra <amodra@gmail.com>
* configure.ac: Delete arm*-*-symbianelf* entry.
* configure: Regenerate.
2021-01-26 Nick Alcock <nick.alcock@oracle.com>
* Makefile.def: Add install-libctf dependency to install-ld.
* Makefile.in: Regenerated.
2021-01-12 Mike Frysinger <vapier@gentoo.org>
* src-release.sh (do_proto_toplev): Rewrite indentation.
2021-01-11 H.J. Lu <hongjiu.lu@intel.com>
PR binutils/26766
* configure.ac:
* configure: Regenerated.
2021-01-11 H.J. Lu <hongjiu.lu@intel.com>
PR ld/27173
* configure: Regenerated.
* libtool.m4 (_LT_CMD_OLD_ARCHIVE): Check if AR works with
--plugin and rc before enabling --plugin.
2021-01-09 H.J. Lu <hongjiu.lu@intel.com>
PR binutils/26766
* Makefile.tpl (BUILD_CFLAGS): New.
(CFLAGS): Append $(BUILD_CFLAGS).
(CXXFLAGS): Likewise.
(PGO_BUILD_GEN_FLAGS_TO_PASS): New.
(PGO_BUILD_TRAINING_CFLAGS): Likewise.
(PGO_BUILD_TRAINING_CXXFLAGS): Likewise.
(PGO_BUILD_TRAINING_FLAGS_TO_PASS): Likewise.
(PGO_BUILD_TRAINING_MFLAGS): Likewise.
(PGO_BUILD_USE_FLAGS_TO_PASS): Likewise.
(PGO-TRAINING-TARGETS): Likewise.
(PGO_BUILD_TRAINING): Likewise.
(all): Add '+' to the command line for recursive make. Support
the PGO build.
* configure.ac: Add --enable-pgo-build[=lto].
AC_SUBST PGO_BUILD_GEN_CFLAGS, PGO_BUILD_USE_CFLAGS and
PGO_BUILD_LTO_CFLAGS. Enable the PGO build in Makefile.
* Makefile.in: Regenerated.
* configure: Likewise.
2021-01-09 H.J. Lu <hongjiu.lu@intel.com>
* Makefile.tpl (AR): Add @AR_PLUGIN_OPTION@
(RANLIB): Add @RANLIB_PLUGIN_OPTION@.
* configure.ac: Include config/gcc-plugin.m4.
AC_SUBST AR_PLUGIN_OPTION and RANLIB_PLUGIN_OPTION.
* libtool.m4 (_LT_CMD_OLD_ARCHIVE): Pass --plugin to AR and
RANLIB if possible.
* Makefile.in: Regenerated.
* configure: Likewise.
2021-01-09 Nick Clifton <nickc@redhat.com>
* 2.36 release branch crated.
2021-01-07 Samuel Thibault <samuel.thibault@gnu.org>
* libtool.m4: Match gnu* along with other GNU systems.
2021-01-07 Alan Modra <amodra@gmail.com>
* config.sub: Accept OS of eabi* and gnueabi*.
2021-01-05 Nick Alcock <nick.alcock@oracle.com>
* Makefile.def (libctf): No longer no_check. Checking depends on
all-ld.
* Makefile.in: Regenerated.
2021-01-05 Nick Clifton <nickc@redhat.com>
* libiberty: Sync with gcc. Bring in:
2021-01-04 Martin Liska <mliska@suse.cz>
* strverscmp.c: Convert to utf8 from iso8859.
2020-12-22 Jason Merrill <jason@redhat.com>
PR c++/67343
* cp-demangle.h (struct d_info): Add unresolved_name_state.
* cp-demangle.c (d_prefix): Add subst parm.
(d_nested_name): Pass it.
(d_unresolved_name): Split out from...
(d_expression_1): ...here.
(d_demangle_callback): Maybe retry with old sr mangling.
* testsuite/demangle-expected: Add test.
2020-12-21 Jason Merrill <jason@redhat.com>
* cp-demangle.c (d_expression_1): Recognize qualified-id
on RHS of dt/pt.
* testsuite/demangle-expected: Add test.
2020-12-21 Jason Merrill <jason@redhat.com>
* cp-demangle.c (d_unqualified_name): Clear is_expression.
* testsuite/demangle-expected: Add tests.
2020-11-25 Matthew Malcomson <matthew.malcomson@arm.com>
* configure: Regenerate.
* configure.ac: Avoid using sanitizer.
2020-11-13 Eduard-Mihai Burtescu <eddyb@lyken.rs>
* rust-demangle.c (struct rust_demangler): Add
skipping_printing and bound_lifetime_depth fields.
(eat): Add (v0-only).
(parse_integer_62): Add (v0-only).
(parse_opt_integer_62): Add (v0-only).
(parse_disambiguator): Add (v0-only).
(struct rust_mangled_ident): Add punycode{,_len} fields.
(parse_ident): Support v0 identifiers.
(print_str): Respect skipping_printing.
(print_uint64): Add (v0-only).
(print_uint64_hex): Add (v0-only).
(print_ident): Respect skipping_printing,
Support v0 identifiers.
(print_lifetime_from_index): Add (v0-only).
(demangle_binder): Add (v0-only).
(demangle_path): Add (v0-only).
(demangle_generic_arg): Add (v0-only).
(demangle_type): Add (v0-only).
(demangle_path_maybe_open_generics): Add (v0-only).
(demangle_dyn_trait): Add (v0-only).
(demangle_const): Add (v0-only).
(demangle_const_uint): Add (v0-only).
(basic_type): Add (v0-only).
(rust_demangle_callback): Support v0 symbols.
* testsuite/rust-demangle-expected: Add v0 testcases.
2020-11-13 Seija Kijin <doremylover456@gmail.com>
* strstr.c (strstr): Make implementation ANSI/POSIX compliant.
2020-11-11 Patrick Palka <ppalka@redhat.com>
PR c++/88115
* cp-demangle.c (d_print_comp_inner)
<case DEMANGLE_COMPONENT_EXTENDED_OPERATOR>: Don't print the
"operator " prefix for __alignof__.
<case DEMANGLE_COMPONENT_UNARY>: Always print parens around the
operand of __alignof__.
* testsuite/demangle-expected: Test demangling for __alignof__.
2020-11-09 Christophe Lyon <christophe.lyon@linaro.org>
* pex-win32.c (pex_win32_exec_child): Initialize orig_err.
2020-10-06 Martin Liska <mliska@suse.cz>
PR lto/97290
* simple-object-elf.c (simple_object_elf_copy_lto_debug_sections):
Use sh_link of a .symtab_shndx section.
2021-01-05 Alan Modra <amodra@gmail.com>
* config.guess: Import from upstream.
* config.sub: Likewise.
2020-12-16 Martin Liska <mliska@suse.cz>
Tom de Vries <tdevries@suse.de>
* gdb/debuginfod-support.c (struct user_data): Remove has_printed
field. Add meter field.
(progressfn): Print progress using meter.
2020-12-02 Enze Li <lienze2010@hotmail.com>
* .gitignore: Add gnu global outputs.
2020-12-02 Simon Marchi <simon.marchi@polymtl.ca>
* .gitignore: Sync with gcc.
2020-10-26 Andreas Rammhold <andreas@rammhold.de>
* src-release.sh: Use sha256sum instead of md5sum.
2020-10-14 Andrew Burgess <andrew.burgess@embecosm.com>
* Makefile.in: Rebuild.
* Makefile.def: Make distclean-gnulib depend on distclean-gdb and
distclean-gdbserver.
2020-07-24 Aaron Merey <amerey@redhat.com>
* configure: Rebuild.
* configure.ac: Remove AC_DEBUGINFOD.
2020-07-04 Nick Clifton <nickc@redhat.com>
Binutils 2.35 branch created.
2020-04-21 Stephen Casner <casner@acm.org>
PR 25830
* configure.ac (noconfigdirs): Exclude gdb & gprof for pdp11.
* configure: Rebuild.
2020-03-12 Tom Tromey <tom@tromey.com>
* Makefile.in: Rebuild.
* Makefile.def (gdbserver): Depend on gdbsupport.
2020-03-12 Tom Tromey <tom@tromey.com>
* Makefile.in: Rebuild.
* Makefile.def (gdbsupport): Don't depend on bfd.
2020-03-12 Tom Tromey <tom@tromey.com>
* Makefile.in: Rebuild.
* Makefile.def (gdbsupport): Depend on intl.
2020-02-17 Tom Tromey <tom@tromey.com>
* configure: Rebuild.
* configure.ac (configdirs): Add gnulib and gdbsupport when building
gdbserver.
2020-02-14 Tom Tromey <tom@tromey.com>
* Makefile.in: Rebuild.
* Makefile.def: Make gdbserver require gnulib and libiberty.
2020-02-07 Tom Tromey <tom@tromey.com>
Pedro Alves <palves@redhat.com>
* src-release.sh (GDB_SUPPORT_DIRS): Add gdbserver.
* gdbserver: New directory, moved from gdb/gdbserver.
* configure.ac (host_tools): Add gdbserver.
Only build gdbserver on certain systems.
* Makefile.in, configure: Rebuild.
* Makefile.def (host_modules, dependencies): Add gdbserver.
* MAINTAINERS: Add gdbserver.
2020-01-28 Sergio Durigan Junior <sergiodj@redhat.com>
* src-release.sh (getver): Look for gdbsupport's
create-version.sh script at the current directory if tool is
"gdb".
2020-01-19 Simon Marchi <simon.marchi@polymtl.ca>
* remote-sim.c (gdbsim_target::wait): Return
sim_data->remote_sim_ptid instead of inferior_ptid.
Diffstat (limited to 'external/gpl3/binutils/dist/include/opcode')
65 files changed, 695 insertions, 290 deletions
diff --git a/external/gpl3/binutils/dist/include/opcode/aarch64.h b/external/gpl3/binutils/dist/include/opcode/aarch64.h index c15295240ee..186ba9a4800 100644 --- a/external/gpl3/binutils/dist/include/opcode/aarch64.h +++ b/external/gpl3/binutils/dist/include/opcode/aarch64.h @@ -1,6 +1,6 @@ /* AArch64 assembler/disassembler support. - Copyright (C) 2009-2020 Free Software Foundation, Inc. + Copyright (C) 2009-2022 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GNU Binutils. @@ -23,7 +23,7 @@ #define OPCODE_AARCH64_H #include "bfd.h" -#include "bfd_stdint.h" +#include <stdint.h> #include <assert.h> #include <stdlib.h> @@ -37,111 +37,147 @@ extern "C" { typedef uint32_t aarch64_insn; /* The following bitmasks control CPU features. */ -#define AARCH64_FEATURE_SHA2 0x200000000ULL /* SHA2 instructions. */ -#define AARCH64_FEATURE_AES 0x800000000ULL /* AES instructions. */ -#define AARCH64_FEATURE_V8_4 0x000000800ULL /* ARMv8.4 processors. */ -#define AARCH64_FEATURE_SM4 0x100000000ULL /* SM3 & SM4 instructions. */ -#define AARCH64_FEATURE_SHA3 0x400000000ULL /* SHA3 instructions. */ -#define AARCH64_FEATURE_V8 0x00000001 /* All processors. */ -#define AARCH64_FEATURE_V8_2 0x00000020 /* ARMv8.2 processors. */ -#define AARCH64_FEATURE_V8_3 0x00000040 /* ARMv8.3 processors. */ -#define AARCH64_FEATURE_FP 0x00020000 /* FP instructions. */ -#define AARCH64_FEATURE_SIMD 0x00040000 /* SIMD instructions. */ -#define AARCH64_FEATURE_CRC 0x00080000 /* CRC instructions. */ -#define AARCH64_FEATURE_LSE 0x00100000 /* LSE instructions. */ -#define AARCH64_FEATURE_PAN 0x00200000 /* PAN instructions. */ -#define AARCH64_FEATURE_LOR 0x00400000 /* LOR instructions. */ -#define AARCH64_FEATURE_RDMA 0x00800000 /* v8.1 SIMD instructions. */ -#define AARCH64_FEATURE_V8_1 0x01000000 /* v8.1 features. */ -#define AARCH64_FEATURE_F16 0x02000000 /* v8.2 FP16 instructions. */ -#define AARCH64_FEATURE_RAS 0x04000000 /* RAS Extensions. */ -#define AARCH64_FEATURE_PROFILE 0x08000000 /* Statistical Profiling. */ -#define AARCH64_FEATURE_SVE 0x10000000 /* SVE instructions. */ -#define AARCH64_FEATURE_RCPC 0x20000000 /* RCPC instructions. */ -#define AARCH64_FEATURE_COMPNUM 0x40000000 /* Complex # instructions. */ -#define AARCH64_FEATURE_DOTPROD 0x080000000 /* Dot Product instructions. */ -#define AARCH64_FEATURE_F16_FML 0x1000000000ULL /* v8.2 FP16FML ins. */ -#define AARCH64_FEATURE_V8_5 0x2000000000ULL /* ARMv8.5 processors. */ -#define AARCH64_FEATURE_V8_6 0x00000002 /* ARMv8.6 processors. */ -#define AARCH64_FEATURE_BFLOAT16 0x00000004 /* Bfloat16 insns. */ - -/* Flag Manipulation insns. */ -#define AARCH64_FEATURE_FLAGMANIP 0x4000000000ULL -/* FRINT[32,64][Z,X] insns. */ -#define AARCH64_FEATURE_FRINTTS 0x8000000000ULL -/* SB instruction. */ -#define AARCH64_FEATURE_SB 0x10000000000ULL -/* Execution and Data Prediction Restriction instructions. */ -#define AARCH64_FEATURE_PREDRES 0x20000000000ULL -/* DC CVADP. */ -#define AARCH64_FEATURE_CVADP 0x40000000000ULL -/* Random Number instructions. */ -#define AARCH64_FEATURE_RNG 0x80000000000ULL -/* BTI instructions. */ -#define AARCH64_FEATURE_BTI 0x100000000000ULL -/* SCXTNUM_ELx. */ -#define AARCH64_FEATURE_SCXTNUM 0x200000000000ULL -/* ID_PFR2 instructions. */ -#define AARCH64_FEATURE_ID_PFR2 0x400000000000ULL -/* SSBS mechanism enabled. */ -#define AARCH64_FEATURE_SSBS 0x800000000000ULL -/* Memory Tagging Extension. */ -#define AARCH64_FEATURE_MEMTAG 0x1000000000000ULL -/* Transactional Memory Extension. */ -#define AARCH64_FEATURE_TME 0x2000000000000ULL - -/* Matrix Multiply instructions */ -#define AARCH64_FEATURE_I8MM 0x10000000000000ULL -#define AARCH64_FEATURE_F32MM 0x20000000000000ULL -#define AARCH64_FEATURE_F64MM 0x40000000000000ULL - -/* SVE2 instructions. */ -#define AARCH64_FEATURE_SVE2 0x000000010 -#define AARCH64_FEATURE_SVE2_AES 0x000000080 -#define AARCH64_FEATURE_SVE2_BITPERM 0x000000100 -#define AARCH64_FEATURE_SVE2_SM4 0x000000200 -#define AARCH64_FEATURE_SVE2_SHA3 0x000000400 +#define AARCH64_FEATURE_V8 (1ULL << 0) /* All processors. */ +#define AARCH64_FEATURE_V8_6 (1ULL << 1) /* ARMv8.6 processors. */ +#define AARCH64_FEATURE_BFLOAT16 (1ULL << 2) /* Bfloat16 insns. */ +#define AARCH64_FEATURE_V8_A (1ULL << 3) /* Armv8-A processors. */ +#define AARCH64_FEATURE_SVE2 (1ULL << 4) /* SVE2 instructions. */ +#define AARCH64_FEATURE_V8_2 (1ULL << 5) /* ARMv8.2 processors. */ +#define AARCH64_FEATURE_V8_3 (1ULL << 6) /* ARMv8.3 processors. */ +#define AARCH64_FEATURE_SVE2_AES (1ULL << 7) +#define AARCH64_FEATURE_SVE2_BITPERM (1ULL << 8) +#define AARCH64_FEATURE_SVE2_SM4 (1ULL << 9) +#define AARCH64_FEATURE_SVE2_SHA3 (1ULL << 10) +#define AARCH64_FEATURE_V8_4 (1ULL << 11) /* ARMv8.4 processors. */ +#define AARCH64_FEATURE_V8_R (1ULL << 12) /* Armv8-R processors. */ +#define AARCH64_FEATURE_V8_7 (1ULL << 13) /* Armv8.7 processors. */ +#define AARCH64_FEATURE_SME (1ULL << 14) /* Scalable Matrix Extension. */ +#define AARCH64_FEATURE_LS64 (1ULL << 15) /* Atomic 64-byte load/store. */ +#define AARCH64_FEATURE_PAC (1ULL << 16) /* v8.3 Pointer Authentication. */ +#define AARCH64_FEATURE_FP (1ULL << 17) /* FP instructions. */ +#define AARCH64_FEATURE_SIMD (1ULL << 18) /* SIMD instructions. */ +#define AARCH64_FEATURE_CRC (1ULL << 19) /* CRC instructions. */ +#define AARCH64_FEATURE_LSE (1ULL << 20) /* LSE instructions. */ +#define AARCH64_FEATURE_PAN (1ULL << 21) /* PAN instructions. */ +#define AARCH64_FEATURE_LOR (1ULL << 22) /* LOR instructions. */ +#define AARCH64_FEATURE_RDMA (1ULL << 23) /* v8.1 SIMD instructions. */ +#define AARCH64_FEATURE_V8_1 (1ULL << 24) /* v8.1 features. */ +#define AARCH64_FEATURE_F16 (1ULL << 25) /* v8.2 FP16 instructions. */ +#define AARCH64_FEATURE_RAS (1ULL << 26) /* RAS Extensions. */ +#define AARCH64_FEATURE_PROFILE (1ULL << 27) /* Statistical Profiling. */ +#define AARCH64_FEATURE_SVE (1ULL << 28) /* SVE instructions. */ +#define AARCH64_FEATURE_RCPC (1ULL << 29) /* RCPC instructions. */ +#define AARCH64_FEATURE_COMPNUM (1ULL << 30) /* Complex # instructions. */ +#define AARCH64_FEATURE_DOTPROD (1ULL << 31) /* Dot Product instructions. */ +#define AARCH64_FEATURE_SM4 (1ULL << 32) /* SM3 & SM4 instructions. */ +#define AARCH64_FEATURE_SHA2 (1ULL << 33) /* SHA2 instructions. */ +#define AARCH64_FEATURE_SHA3 (1ULL << 34) /* SHA3 instructions. */ +#define AARCH64_FEATURE_AES (1ULL << 35) /* AES instructions. */ +#define AARCH64_FEATURE_F16_FML (1ULL << 36) /* v8.2 FP16FML ins. */ +#define AARCH64_FEATURE_V8_5 (1ULL << 37) /* ARMv8.5 processors. */ +#define AARCH64_FEATURE_FLAGMANIP (1ULL << 38) /* v8.5 Flag Manipulation version 2. */ +#define AARCH64_FEATURE_FRINTTS (1ULL << 39) /* FRINT[32,64][Z,X] insns. */ +#define AARCH64_FEATURE_SB (1ULL << 40) /* SB instruction. */ +#define AARCH64_FEATURE_PREDRES (1ULL << 41) /* Execution and Data Prediction Restriction instructions. */ +#define AARCH64_FEATURE_CVADP (1ULL << 42) /* DC CVADP. */ +#define AARCH64_FEATURE_RNG (1ULL << 43) /* Random Number instructions. */ +#define AARCH64_FEATURE_BTI (1ULL << 44) /* BTI instructions. */ +#define AARCH64_FEATURE_SCXTNUM (1ULL << 45) /* SCXTNUM_ELx. */ +#define AARCH64_FEATURE_ID_PFR2 (1ULL << 46) /* ID_PFR2 instructions. */ +#define AARCH64_FEATURE_SSBS (1ULL << 47) /* SSBS mechanism enabled. */ +#define AARCH64_FEATURE_MEMTAG (1ULL << 48) /* Memory Tagging Extension. */ +#define AARCH64_FEATURE_TME (1ULL << 49) /* Transactional Memory Extension. */ +#define AARCH64_FEATURE_MOPS (1ULL << 50) /* Standardization of memory operations. */ +#define AARCH64_FEATURE_HBC (1ULL << 51) /* Hinted conditional branches. */ +#define AARCH64_FEATURE_I8MM (1ULL << 52) /* Matrix Multiply instructions. */ +#define AARCH64_FEATURE_F32MM (1ULL << 53) +#define AARCH64_FEATURE_F64MM (1ULL << 54) +#define AARCH64_FEATURE_FLAGM (1ULL << 55) /* v8.4 Flag Manipulation. */ +#define AARCH64_FEATURE_V9 (1ULL << 56) /* Armv9.0-A processors. */ +#define AARCH64_FEATURE_SME_F64 (1ULL << 57) /* SME F64. */ +#define AARCH64_FEATURE_SME_I64 (1ULL << 58) /* SME I64. */ +#define AARCH64_FEATURE_V8_8 (1ULL << 59) /* Armv8.8 processors. */ /* Crypto instructions are the combination of AES and SHA2. */ #define AARCH64_FEATURE_CRYPTO (AARCH64_FEATURE_SHA2 | AARCH64_FEATURE_AES) +#define AARCH64_ARCH_V8_FEATURES (AARCH64_FEATURE_V8_A \ + | AARCH64_FEATURE_FP \ + | AARCH64_FEATURE_RAS \ + | AARCH64_FEATURE_SIMD) +#define AARCH64_ARCH_V8_1_FEATURES (AARCH64_FEATURE_V8_1 \ + | AARCH64_FEATURE_CRC \ + | AARCH64_FEATURE_LSE \ + | AARCH64_FEATURE_PAN \ + | AARCH64_FEATURE_LOR \ + | AARCH64_FEATURE_RDMA) +#define AARCH64_ARCH_V8_2_FEATURES (AARCH64_FEATURE_V8_2) +#define AARCH64_ARCH_V8_3_FEATURES (AARCH64_FEATURE_V8_3 \ + | AARCH64_FEATURE_PAC \ + | AARCH64_FEATURE_RCPC \ + | AARCH64_FEATURE_COMPNUM) +#define AARCH64_ARCH_V8_4_FEATURES (AARCH64_FEATURE_V8_4 \ + | AARCH64_FEATURE_DOTPROD \ + | AARCH64_FEATURE_FLAGM \ + | AARCH64_FEATURE_F16_FML) +#define AARCH64_ARCH_V8_5_FEATURES (AARCH64_FEATURE_V8_5 \ + | AARCH64_FEATURE_FLAGMANIP \ + | AARCH64_FEATURE_FRINTTS \ + | AARCH64_FEATURE_SB \ + | AARCH64_FEATURE_PREDRES \ + | AARCH64_FEATURE_CVADP \ + | AARCH64_FEATURE_BTI \ + | AARCH64_FEATURE_SCXTNUM \ + | AARCH64_FEATURE_ID_PFR2 \ + | AARCH64_FEATURE_SSBS) +#define AARCH64_ARCH_V8_6_FEATURES (AARCH64_FEATURE_V8_6 \ + | AARCH64_FEATURE_BFLOAT16 \ + | AARCH64_FEATURE_I8MM) +#define AARCH64_ARCH_V8_7_FEATURES (AARCH64_FEATURE_V8_7 \ + | AARCH64_FEATURE_LS64) +#define AARCH64_ARCH_V8_8_FEATURES (AARCH64_FEATURE_V8_8 \ + | AARCH64_FEATURE_MOPS \ + | AARCH64_FEATURE_HBC) + +#define AARCH64_ARCH_V9_FEATURES (AARCH64_FEATURE_V9 \ + | AARCH64_FEATURE_F16 \ + | AARCH64_FEATURE_SVE \ + | AARCH64_FEATURE_SVE2) +#define AARCH64_ARCH_V9_1_FEATURES (AARCH64_ARCH_V8_6_FEATURES) +#define AARCH64_ARCH_V9_2_FEATURES (AARCH64_ARCH_V8_7_FEATURES) +#define AARCH64_ARCH_V9_3_FEATURES (AARCH64_ARCH_V8_8_FEATURES) + /* Architectures are the sum of the base and extensions. */ #define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \ - AARCH64_FEATURE_FP \ - | AARCH64_FEATURE_SIMD) + AARCH64_ARCH_V8_FEATURES) #define AARCH64_ARCH_V8_1 AARCH64_FEATURE (AARCH64_ARCH_V8, \ - AARCH64_FEATURE_CRC \ - | AARCH64_FEATURE_V8_1 \ - | AARCH64_FEATURE_LSE \ - | AARCH64_FEATURE_PAN \ - | AARCH64_FEATURE_LOR \ - | AARCH64_FEATURE_RDMA) + AARCH64_ARCH_V8_1_FEATURES) #define AARCH64_ARCH_V8_2 AARCH64_FEATURE (AARCH64_ARCH_V8_1, \ - AARCH64_FEATURE_V8_2 \ - | AARCH64_FEATURE_RAS) + AARCH64_ARCH_V8_2_FEATURES) #define AARCH64_ARCH_V8_3 AARCH64_FEATURE (AARCH64_ARCH_V8_2, \ - AARCH64_FEATURE_V8_3 \ - | AARCH64_FEATURE_RCPC \ - | AARCH64_FEATURE_COMPNUM) + AARCH64_ARCH_V8_3_FEATURES) #define AARCH64_ARCH_V8_4 AARCH64_FEATURE (AARCH64_ARCH_V8_3, \ - AARCH64_FEATURE_V8_4 \ - | AARCH64_FEATURE_DOTPROD \ - | AARCH64_FEATURE_F16_FML) + AARCH64_ARCH_V8_4_FEATURES) #define AARCH64_ARCH_V8_5 AARCH64_FEATURE (AARCH64_ARCH_V8_4, \ - AARCH64_FEATURE_V8_5 \ - | AARCH64_FEATURE_FLAGMANIP \ - | AARCH64_FEATURE_FRINTTS \ - | AARCH64_FEATURE_SB \ - | AARCH64_FEATURE_PREDRES \ - | AARCH64_FEATURE_CVADP \ - | AARCH64_FEATURE_BTI \ - | AARCH64_FEATURE_SCXTNUM \ - | AARCH64_FEATURE_ID_PFR2 \ - | AARCH64_FEATURE_SSBS) + AARCH64_ARCH_V8_5_FEATURES) #define AARCH64_ARCH_V8_6 AARCH64_FEATURE (AARCH64_ARCH_V8_5, \ - AARCH64_FEATURE_V8_6 \ - | AARCH64_FEATURE_BFLOAT16 \ - | AARCH64_FEATURE_I8MM) + AARCH64_ARCH_V8_6_FEATURES) +#define AARCH64_ARCH_V8_7 AARCH64_FEATURE (AARCH64_ARCH_V8_6, \ + AARCH64_ARCH_V8_7_FEATURES) +#define AARCH64_ARCH_V8_8 AARCH64_FEATURE (AARCH64_ARCH_V8_7, \ + AARCH64_ARCH_V8_8_FEATURES) +#define AARCH64_ARCH_V8_R (AARCH64_FEATURE (AARCH64_ARCH_V8_4, \ + AARCH64_FEATURE_V8_R) \ + & ~(AARCH64_FEATURE_V8_A | AARCH64_FEATURE_LOR)) + +#define AARCH64_ARCH_V9 AARCH64_FEATURE (AARCH64_ARCH_V8_5, \ + AARCH64_ARCH_V9_FEATURES) +#define AARCH64_ARCH_V9_1 AARCH64_FEATURE (AARCH64_ARCH_V9, \ + AARCH64_ARCH_V9_1_FEATURES) +#define AARCH64_ARCH_V9_2 AARCH64_FEATURE (AARCH64_ARCH_V9_1, \ + AARCH64_ARCH_V9_2_FEATURES) +#define AARCH64_ARCH_V9_3 AARCH64_FEATURE (AARCH64_ARCH_V9_2, \ + AARCH64_ARCH_V9_3_FEATURES) #define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0) #define AARCH64_ANY AARCH64_FEATURE (-1, 0) /* Any basic core. */ @@ -204,6 +240,7 @@ enum aarch64_opnd AARCH64_OPND_Rm, /* Integer register as source. */ AARCH64_OPND_Rt, /* Integer register used in ld/st instructions. */ AARCH64_OPND_Rt2, /* Integer register used in ld/st pair instructions. */ + AARCH64_OPND_Rt_LS64, /* Integer register used in LS64 instructions. */ AARCH64_OPND_Rt_SP, /* Integer Rt or SP used in STG instructions. */ AARCH64_OPND_Rs, /* Integer register used in ld/st exclusive. */ AARCH64_OPND_Ra, /* Integer register used in ddp_3src instructions. */ @@ -272,6 +309,7 @@ enum aarch64_opnd AARCH64_OPND_UIMM10, /* Unsigned 10-bit immediate in addg/subg. */ AARCH64_OPND_BIT_NUM, /* Immediate. */ AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions. */ + AARCH64_OPND_UNDEFINED,/* imm16 operand in undefined instruction. */ AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions. */ AARCH64_OPND_SIMM5, /* 5-bit signed immediate in the imm5 field. */ AARCH64_OPND_NZCV, /* Flag bit specifier giving an alternative value for @@ -324,11 +362,11 @@ enum aarch64_opnd AARCH64_OPND_SYSREG_TLBI, /* System register <tlbi_op> operand. */ AARCH64_OPND_SYSREG_SR, /* System register RCTX operand. */ AARCH64_OPND_BARRIER, /* Barrier operand. */ + AARCH64_OPND_BARRIER_DSB_NXS, /* Barrier operand for DSB nXS variant. */ AARCH64_OPND_BARRIER_ISB, /* Barrier operand for ISB. */ AARCH64_OPND_PRFOP, /* Prefetch operation. */ AARCH64_OPND_BARRIER_PSB, /* Barrier operand for PSB. */ AARCH64_OPND_BTI_TARGET, /* BTI {<target>}. */ - AARCH64_OPND_SVE_ADDR_RI_S4x16, /* SVE [<Xn|SP>, #<simm4>*16]. */ AARCH64_OPND_SVE_ADDR_RI_S4x32, /* SVE [<Xn|SP>, #<simm4>*32]. */ AARCH64_OPND_SVE_ADDR_RI_S4xVL, /* SVE [<Xn|SP>, #<simm4>, MUL VL]. */ @@ -346,6 +384,7 @@ enum aarch64_opnd AARCH64_OPND_SVE_ADDR_RR_LSL1, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #1]. */ AARCH64_OPND_SVE_ADDR_RR_LSL2, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #2]. */ AARCH64_OPND_SVE_ADDR_RR_LSL3, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #3]. */ + AARCH64_OPND_SVE_ADDR_RR_LSL4, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #4]. */ AARCH64_OPND_SVE_ADDR_RX, /* SVE [<Xn|SP>, <Xm>]. */ AARCH64_OPND_SVE_ADDR_RX_LSL1, /* SVE [<Xn|SP>, <Xm>, LSL #1]. */ AARCH64_OPND_SVE_ADDR_RX_LSL2, /* SVE [<Xn|SP>, <Xm>, LSL #2]. */ @@ -436,8 +475,22 @@ enum aarch64_opnd AARCH64_OPND_SVE_ZnxN, /* SVE vector register list in Zn. */ AARCH64_OPND_SVE_Zt, /* SVE vector register in Zt. */ AARCH64_OPND_SVE_ZtxN, /* SVE vector register list in Zt. */ + AARCH64_OPND_SME_ZAda_2b, /* SME <ZAda>.S, 2-bits. */ + AARCH64_OPND_SME_ZAda_3b, /* SME <ZAda>.D, 3-bits. */ + AARCH64_OPND_SME_ZA_HV_idx_src, /* SME source ZA tile vector. */ + AARCH64_OPND_SME_ZA_HV_idx_dest, /* SME destination ZA tile vector. */ + AARCH64_OPND_SME_Pm, /* SME scalable predicate register, bits [15:13]. */ + AARCH64_OPND_SME_list_of_64bit_tiles, /* SME list of ZA tiles. */ + AARCH64_OPND_SME_ZA_HV_idx_ldstr, /* SME destination ZA tile vector. */ + AARCH64_OPND_SME_ZA_array, /* SME ZA[<Wv>{, #<imm>}]. */ + AARCH64_OPND_SME_ADDR_RI_U4xVL, /* SME [<Xn|SP>{, #<imm>, MUL VL}]. */ + AARCH64_OPND_SME_SM_ZA, /* SME {SM | ZA}. */ + AARCH64_OPND_SME_PnT_Wm_imm, /* SME <Pn>.<T>[<Wm>, #<imm>]. */ AARCH64_OPND_TME_UIMM16, /* TME unsigned 16-bit immediate. */ AARCH64_OPND_SM3_IMM2, /* SM3 encodes lane in bits [13, 14]. */ + AARCH64_OPND_MOPS_ADDR_Rd, /* [Rd]!, in bits [0, 4]. */ + AARCH64_OPND_MOPS_ADDR_Rs, /* [Rs]!, in bits [16, 20]. */ + AARCH64_OPND_MOPS_WB_Rn /* Rn!, in bits [5, 9]. */ }; /* Qualifier constrains an operand. It either specifies a variant of an @@ -600,6 +653,11 @@ enum aarch64_insn_class movewide, pcreladdr, ic_system, + sme_misc, + sme_ldr, + sme_str, + sme_start, + sme_stop, sve_cpy, sve_index, sve_limm, @@ -752,14 +810,14 @@ typedef aarch64_opnd_qualifier_t \ aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM]; /* FIXME: improve the efficiency. */ -static inline bfd_boolean +static inline bool empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers) { int i; for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i) if (qualifiers[i] != AARCH64_OPND_QLF_NIL) - return FALSE; - return TRUE; + return false; + return true; } /* Forward declare error reporting type. */ @@ -818,14 +876,14 @@ struct aarch64_opcode /* If non-NULL, a function to verify that a given instruction is valid. */ enum err_type (* verifier) (const struct aarch64_inst *, const aarch64_insn, - bfd_vma, bfd_boolean, aarch64_operand_error *, + bfd_vma, bool, aarch64_operand_error *, struct aarch64_instr_sequence *); }; typedef struct aarch64_opcode aarch64_opcode; /* Table describing all the AArch64 opcodes. */ -extern aarch64_opcode aarch64_opcode_table[]; +extern const aarch64_opcode aarch64_opcode_table[]; /* Opcode flags. */ #define F_ALIAS (1 << 0) @@ -894,18 +952,22 @@ extern aarch64_opcode aarch64_opcode_table[]; /* This instruction's operation width is determined by the operand with the largest element size. */ #define C_MAX_ELEM (1U << 1) -/* Next bit is 2. */ +#define C_SCAN_MOPS_P (1U << 2) +#define C_SCAN_MOPS_M (2U << 2) +#define C_SCAN_MOPS_E (3U << 2) +#define C_SCAN_MOPS_PME (3U << 2) +/* Next bit is 4. */ -static inline bfd_boolean +static inline bool alias_opcode_p (const aarch64_opcode *opcode) { - return (opcode->flags & F_ALIAS) ? TRUE : FALSE; + return (opcode->flags & F_ALIAS) != 0; } -static inline bfd_boolean +static inline bool opcode_has_alias (const aarch64_opcode *opcode) { - return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE; + return (opcode->flags & F_HAS_ALIAS) != 0; } /* Priority for disassembling preference. */ @@ -915,17 +977,16 @@ opcode_priority (const aarch64_opcode *opcode) return (opcode->flags >> 2) & 0x3; } -static inline bfd_boolean +static inline bool pseudo_opcode_p (const aarch64_opcode *opcode) { - return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE; + return (opcode->flags & F_PSEUDO) != 0lu; } -static inline bfd_boolean +static inline bool optional_operand_p (const aarch64_opcode *opcode, unsigned int idx) { - return (((opcode->flags >> 12) & 0x7) == idx + 1) - ? TRUE : FALSE; + return ((opcode->flags >> 12) & 0x7) == idx + 1; } static inline aarch64_insn @@ -940,12 +1001,11 @@ get_opcode_dependent_value (const aarch64_opcode *opcode) return (opcode->flags >> 24) & 0x7; } -static inline bfd_boolean +static inline bool opcode_has_special_coder (const aarch64_opcode *opcode) { return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T - | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE - : FALSE; + | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) != 0; } struct aarch64_name_value_pair @@ -956,23 +1016,28 @@ struct aarch64_name_value_pair extern const struct aarch64_name_value_pair aarch64_operand_modifiers []; extern const struct aarch64_name_value_pair aarch64_barrier_options [16]; +extern const struct aarch64_name_value_pair aarch64_barrier_dsb_nxs_options [4]; extern const struct aarch64_name_value_pair aarch64_prfops [32]; extern const struct aarch64_name_value_pair aarch64_hint_options []; +#define AARCH64_MAX_SYSREG_NAME_LEN 32 + typedef struct { const char * name; aarch64_insn value; uint32_t flags; + + /* A set of features, all of which are required for this system register to be + available. */ + aarch64_feature_set features; } aarch64_sys_reg; extern const aarch64_sys_reg aarch64_sys_regs []; extern const aarch64_sys_reg aarch64_pstatefields []; -extern bfd_boolean aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *); -extern bfd_boolean aarch64_sys_reg_supported_p (const aarch64_feature_set, - const aarch64_sys_reg *); -extern bfd_boolean aarch64_pstatefield_supported_p (const aarch64_feature_set, - const aarch64_sys_reg *); +extern bool aarch64_sys_reg_deprecated_p (const uint32_t); +extern bool aarch64_pstatefield_supported_p (const aarch64_feature_set, + const aarch64_sys_reg *); typedef struct { @@ -981,10 +1046,11 @@ typedef struct uint32_t flags ; } aarch64_sys_ins_reg; -extern bfd_boolean aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *); -extern bfd_boolean +extern bool aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *); +extern bool aarch64_sys_ins_reg_supported_p (const aarch64_feature_set, - const aarch64_sys_ins_reg *); + const char *reg_name, aarch64_insn, + uint32_t, aarch64_feature_set); extern const aarch64_sys_ins_reg aarch64_sys_regs_ic []; extern const aarch64_sys_ins_reg aarch64_sys_regs_dc []; @@ -1014,7 +1080,7 @@ enum aarch64_modifier_kind AARCH64_MOD_MUL_VL, }; -bfd_boolean +bool aarch64_extend_operator_p (enum aarch64_modifier_kind); enum aarch64_modifier_kind @@ -1097,6 +1163,18 @@ struct aarch64_opnd_info uint32_t flags; } sysreg; + /* ZA tile vector, e.g. <ZAn><HV>.D[<Wv>{, <imm>}] */ + struct + { + int regno; /* <ZAn> */ + struct + { + int regno; /* <Wv> */ + int imm; /* <imm> */ + } index; + unsigned v : 1; /* <HV> horizontal or vertical vector indicator. */ + } za_tile_vector; + const aarch64_cond *cond; /* The encoding of the PSTATE field. */ aarch64_insn pstatefield; @@ -1172,6 +1250,17 @@ struct aarch64_inst Less severe error found during the parsing, very possibly because that GAS has picked up a wrong instruction template for the parsing. + AARCH64_OPDE_A_SHOULD_FOLLOW_B + The instruction forms (or is expected to form) part of a sequence, + but the preceding instruction in the sequence wasn't the expected one. + The message refers to two strings: the name of the current instruction, + followed by the name of the expected preceding instruction. + + AARCH64_OPDE_EXPECTED_A_AFTER_B + Same as AARCH64_OPDE_A_SHOULD_FOLLOW_B, but shifting the focus + so that the current instruction is assumed to be the incorrect one: + "since the previous instruction was B, the current one should be A". + AARCH64_OPDE_SYNTAX_ERROR General syntax error; it can be either a user error, or simply because that GAS is trying a wrong instruction template. @@ -1183,6 +1272,10 @@ struct aarch64_inst No syntax error, but the operands are not a valid combination, e.g. FMOV D0,S0 + AARCH64_OPDE_UNTIED_IMMS + The asm failed to use the same immediate for a destination operand + and a tied source operand. + AARCH64_OPDE_UNTIED_OPERAND The asm failed to use the same register for a destination operand and a tied source operand. @@ -1202,11 +1295,8 @@ struct aarch64_inst Error of the highest severity and used for any severe issue that does not fall into any of the above categories. - The enumerators are only interesting to GAS. They are declared here (in - libopcodes) because that some errors are detected (and then notified to GAS) - by libopcodes (rather than by GAS solely). - - The first three errors are only deteced by GAS while the + AARCH64_OPDE_RECOVERABLE, AARCH64_OPDE_SYNTAX_ERROR and + AARCH64_OPDE_FATAL_SYNTAX_ERROR are only deteced by GAS while the AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as only libopcodes has the information about the valid variants of each instruction. @@ -1220,9 +1310,12 @@ enum aarch64_operand_error_kind { AARCH64_OPDE_NIL, AARCH64_OPDE_RECOVERABLE, + AARCH64_OPDE_A_SHOULD_FOLLOW_B, + AARCH64_OPDE_EXPECTED_A_AFTER_B, AARCH64_OPDE_SYNTAX_ERROR, AARCH64_OPDE_FATAL_SYNTAX_ERROR, AARCH64_OPDE_INVALID_VARIANT, + AARCH64_OPDE_UNTIED_IMMS, AARCH64_OPDE_UNTIED_OPERAND, AARCH64_OPDE_OUT_OF_RANGE, AARCH64_OPDE_UNALIGNED, @@ -1236,28 +1329,30 @@ struct aarch64_operand_error enum aarch64_operand_error_kind kind; int index; const char *error; - int data[3]; /* Some data for extra information. */ - bfd_boolean non_fatal; + /* Some data for extra information. */ + union { + int i; + const char *s; + } data[3]; + bool non_fatal; }; /* AArch64 sequence structure used to track instructions with F_SCAN dependencies for both assembler and disassembler. */ struct aarch64_instr_sequence { - /* The instruction that caused this sequence to be opened. */ + /* The instructions in the sequence, starting with the one that + caused it to be opened. */ aarch64_inst *instr; - /* The number of instructions the above instruction allows to be kept in the - sequence before an automatic close is done. */ - int num_insns; - /* The instructions currently added to the sequence. */ - aarch64_inst **current_insns; /* The number of instructions already in the sequence. */ - int next_insn; + int num_added_insns; + /* The number of instructions allocated to the sequence. */ + int num_allocated_insns; }; /* Encoding entrypoint. */ -extern int +extern bool aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *, aarch64_insn *, aarch64_opnd_qualifier_t *, aarch64_operand_error *, aarch64_instr_sequence *); @@ -1276,7 +1371,8 @@ aarch64_get_opcode (enum aarch64_op); extern void aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *, const aarch64_opnd_info *, int, int *, bfd_vma *, - char **); + char **, char *, size_t, + aarch64_feature_set features); /* Miscellaneous interface. */ @@ -1287,7 +1383,7 @@ extern aarch64_opnd_qualifier_t aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int, const aarch64_opnd_qualifier_t, int); -extern bfd_boolean +extern bool aarch64_is_destructive_by_operands (const aarch64_opcode *); extern int @@ -1300,7 +1396,7 @@ extern int aarch64_zero_register_p (const aarch64_opnd_info *); extern enum err_type -aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean, +aarch64_decode_insn (aarch64_insn, aarch64_inst *, bool, aarch64_operand_error *); extern void @@ -1320,7 +1416,7 @@ aarch64_get_operand_name (enum aarch64_opnd); extern const char * aarch64_get_operand_desc (enum aarch64_opnd); -extern bfd_boolean +extern bool aarch64_sve_dupm_mov_immediate_p (uint64_t, int); #ifdef DEBUG_AARCH64 diff --git a/external/gpl3/binutils/dist/include/opcode/alpha.h b/external/gpl3/binutils/dist/include/opcode/alpha.h index 9f2938d9614..91dee002662 100644 --- a/external/gpl3/binutils/dist/include/opcode/alpha.h +++ b/external/gpl3/binutils/dist/include/opcode/alpha.h @@ -1,5 +1,5 @@ /* alpha.h -- Header file for Alpha opcode table - Copyright (C) 1996-2020 Free Software Foundation, Inc. + Copyright (C) 1996-2022 Free Software Foundation, Inc. Contributed by Richard Henderson <rth@tamu.edu>, patterned after the PPC opcode table written by Ian Lance Taylor. diff --git a/external/gpl3/binutils/dist/include/opcode/arc-attrs.h b/external/gpl3/binutils/dist/include/opcode/arc-attrs.h index 5162db01113..18f6653603a 100644 --- a/external/gpl3/binutils/dist/include/opcode/arc-attrs.h +++ b/external/gpl3/binutils/dist/include/opcode/arc-attrs.h @@ -1,4 +1,4 @@ -/* Copyright (C) 1994-2020 Free Software Foundation, Inc. +/* Copyright (C) 1994-2022 Free Software Foundation, Inc. Contributed by Claudiu Zissulescu (claziss@synopsys.com) @@ -58,7 +58,7 @@ const struct feature_type #endif /* A table with conflicting features. */ -unsigned CONFLICT_LIST [] = { +const unsigned CONFLICT_LIST [] = { NPS400 | SPX, NPS400 | DPX, DPX | DPA, diff --git a/external/gpl3/binutils/dist/include/opcode/arc-func.h b/external/gpl3/binutils/dist/include/opcode/arc-func.h index d0e84d8251f..34666e9fe0c 100644 --- a/external/gpl3/binutils/dist/include/opcode/arc-func.h +++ b/external/gpl3/binutils/dist/include/opcode/arc-func.h @@ -1,5 +1,5 @@ /* Replace functions for the ARC relocs. - Copyright (C) 2015-2020 Free Software Foundation, Inc. + Copyright (C) 2015-2022 Free Software Foundation, Inc. This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and the GNU Binutils. diff --git a/external/gpl3/binutils/dist/include/opcode/arc.h b/external/gpl3/binutils/dist/include/opcode/arc.h index 3a05cd89332..b83150782b7 100644 --- a/external/gpl3/binutils/dist/include/opcode/arc.h +++ b/external/gpl3/binutils/dist/include/opcode/arc.h @@ -1,5 +1,5 @@ /* Opcode table for the ARC. - Copyright (C) 1994-2020 Free Software Foundation, Inc. + Copyright (C) 1994-2022 Free Software Foundation, Inc. Contributed by Claudiu Zissulescu (claziss@synopsys.com) @@ -260,8 +260,7 @@ struct arc_operand TRUE if this operand type can not actually be extracted from this operand (i.e., the instruction does not match). If the operand is valid, *INVALID will not be changed. */ - long long int (*extract) (unsigned long long instruction, - bfd_boolean *invalid); + long long int (*extract) (unsigned long long instruction, bool *invalid); }; /* Elements in the table are retrieved by indexing with values from diff --git a/external/gpl3/binutils/dist/include/opcode/arm.h b/external/gpl3/binutils/dist/include/opcode/arm.h index 6d8c3d00861..8d6f8db34ab 100644 --- a/external/gpl3/binutils/dist/include/opcode/arm.h +++ b/external/gpl3/binutils/dist/include/opcode/arm.h @@ -1,5 +1,5 @@ /* ARM assembler/disassembler support. - Copyright (C) 2004-2020 Free Software Foundation, Inc. + Copyright (C) 2004-2022 Free Software Foundation, Inc. This file is part of GDB and GAS. @@ -79,6 +79,22 @@ #define ARM_EXT2_CRC 0x00080000 /* ARMv8 CRC32 */ #define ARM_EXT2_MVE 0x00100000 /* MVE Integer extension. */ #define ARM_EXT2_MVE_FP 0x00200000 /* MVE Floating Point extension. */ +#define ARM_EXT2_CDE 0x00400000 /* Custom Datapath Extension. */ +#define ARM_EXT2_CDE0 0x00800000 /* Using CDE coproc 0. */ +#define ARM_EXT2_CDE1 0x01000000 /* Using CDE coproc 1. */ +#define ARM_EXT2_CDE2 0x02000000 /* Using CDE coproc 2. */ +#define ARM_EXT2_CDE3 0x04000000 /* Using CDE coproc 3. */ +#define ARM_EXT2_CDE4 0x08000000 /* Using CDE coproc 4. */ +#define ARM_EXT2_CDE5 0x10000000 /* Using CDE coproc 5. */ +#define ARM_EXT2_CDE6 0x20000000 /* Using CDE coproc 6. */ +#define ARM_EXT2_CDE7 0x40000000 /* Using CDE coproc 7. */ +#define ARM_EXT2_V8R 0x80000000 /* Arm V8R. */ + +#define ARM_EXT3_PACBTI 0x00000001 /* Arm v8-M Mainline Pointer + Authentication and Branch + Target Identification + Extension. */ +#define ARM_EXT3_V9A 0x00000002 /* Armv9-A. */ /* Co-processor space extensions. */ #define ARM_CEXT_XSCALE 0x00000001 /* Allow MIA etc. */ @@ -182,11 +198,13 @@ #define ARM_AEXT2_V8M_MAIN (ARM_AEXT2_V8M_BASE | ARM_EXT2_V8M_MAIN) #define ARM_AEXT2_V8M_MAIN_DSP ARM_AEXT2_V8M_MAIN #define ARM_AEXT_V8R ARM_AEXT_V8A -#define ARM_AEXT2_V8R ARM_AEXT2_V8AR +#define ARM_AEXT2_V8R (ARM_EXT2_V8R | ARM_AEXT2_V8AR) #define ARM_AEXT_V8_1M_MAIN ARM_AEXT_V8M_MAIN #define ARM_AEXT2_V8_1M_MAIN (ARM_AEXT2_V8M_MAIN | ARM_EXT2_V8_1M_MAIN \ | ARM_EXT2_FP16_INST) +#define ARM_AEXT3_V8_1M_MAIN_PACBTI (ARM_AEXT2_V8M_MAIN | ARM_EXT3_PACBTI) + /* Processors with specific extensions in the co-processor space. */ #define ARM_ARCH_XSCALE ARM_FEATURE_LOW (ARM_AEXT_V5TE, ARM_CEXT_XSCALE) #define ARM_ARCH_IWMMXT \ @@ -359,6 +377,8 @@ #define ARM_ARCH_V8_6A ARM_FEATURE (ARM_AEXT_V8A, ARM_AEXT2_V8_6A \ | ARM_EXT2_CRC, FPU_NEON_EXT_RDMA \ | FPU_NEON_EXT_DOTPROD) +#define ARM_ARCH_V8_7A ARM_ARCH_V8_6A +#define ARM_ARCH_V8_8A ARM_ARCH_V8_7A #define ARM_ARCH_V8M_BASE ARM_FEATURE_CORE (ARM_AEXT_V8M_BASE, \ ARM_AEXT2_V8M_BASE) #define ARM_ARCH_V8M_MAIN ARM_FEATURE_CORE (ARM_AEXT_V8M_MAIN, \ @@ -368,12 +388,24 @@ #define ARM_ARCH_V8R ARM_FEATURE_CORE (ARM_AEXT_V8R, ARM_AEXT2_V8R) #define ARM_ARCH_V8_1M_MAIN ARM_FEATURE_CORE (ARM_AEXT_V8_1M_MAIN, \ ARM_AEXT2_V8_1M_MAIN) +#define ARM_ARCH_V9A ARM_FEATURE_ALL(ARM_AEXT_V8A, \ + ARM_AEXT2_V8_5A | ARM_EXT2_CRC, \ + ARM_EXT3_V9A, \ + FPU_NEON_EXT_RDMA | FPU_NEON_EXT_DOTPROD) +#define ARM_ARCH_V9_1A ARM_FEATURE_ALL (ARM_AEXT_V8A, \ + ARM_AEXT2_V8_6A | ARM_EXT2_CRC, \ + ARM_EXT3_V9A, \ + FPU_NEON_EXT_RDMA \ + | FPU_NEON_EXT_DOTPROD) +#define ARM_ARCH_V9_2A ARM_ARCH_V9_1A +#define ARM_ARCH_V9_3A ARM_ARCH_V9_2A /* Some useful combinations: */ -#define ARM_ARCH_NONE ARM_FEATURE_LOW (0, 0) -#define FPU_NONE ARM_FEATURE_LOW (0, 0) -#define ARM_ANY ARM_FEATURE (-1, -1 & ~ (ARM_EXT2_MVE | ARM_EXT2_MVE_FP), 0) /* Any basic core. */ -#define FPU_ANY ARM_FEATURE_COPROC (-1) /* Any FPU. */ +#define ARM_ARCH_NONE ARM_FEATURE_ALL (0, 0, 0, 0) +#define FPU_NONE ARM_FEATURE_ALL (0, 0, 0, 0) +#define ARM_ARCH_UNKNOWN ARM_FEATURE_ALL (-1, -1 & ~(ARM_EXT2_MVE | ARM_EXT2_MVE_FP), -1, -1) /* Machine type is unknown. */ +#define ARM_ANY ARM_FEATURE_ALL (-1, -1 & ~(ARM_EXT2_MVE | ARM_EXT2_MVE_FP), -1, 0) /* Any basic core. */ +#define FPU_ANY ARM_FEATURE_COPROC (-1 & ~(ARM_CEXT_XSCALE | ARM_CEXT_IWMMXT | ARM_CEXT_IWMMXT2)) /* Any FPU. */ #define FPU_ANY_HARD ARM_FEATURE_COPROC (FPU_FPA | FPU_VFP_HARD | FPU_MAVERICK) /* Extensions containing some Thumb-2 instructions. If any is present, Thumb ISA is Thumb-2. */ @@ -412,12 +444,12 @@ /* There are too many feature bits to fit in a single word, so use a structure. For simplicity we put all core features in array CORE - and everything else in the other. All the bits in element core[0] - have been occupied, so new feature should use bit in element core[1] + and everything else in the other. All the bits in element core[0:1] + have been occupied, so new feature should use bit in element core[2] and use macro ARM_FEATURE to initialize the feature set variable. */ typedef struct { - unsigned long core[2]; + unsigned long core[3]; unsigned long coproc; } arm_feature_set; @@ -425,23 +457,27 @@ typedef struct #define ARM_CPU_HAS_FEATURE(CPU,FEAT) \ (((CPU).core[0] & (FEAT).core[0]) != 0 \ || ((CPU).core[1] & (FEAT).core[1]) != 0 \ + || ((CPU).core[2] & (FEAT).core[2]) != 0 \ || ((CPU).coproc & (FEAT).coproc) != 0) /* Tests whether the features of A are a subset of B. */ #define ARM_FSET_CPU_SUBSET(A,B) \ (((A).core[0] & (B).core[0]) == (A).core[0] \ && ((A).core[1] & (B).core[1]) == (A).core[1] \ + && ((A).core[2] & (B).core[2]) == (A).core[2] \ && ((A).coproc & (B).coproc) == (A).coproc) #define ARM_CPU_IS_ANY(CPU) \ ((CPU).core[0] == ((arm_feature_set)ARM_ANY).core[0] \ - && (CPU).core[1] == ((arm_feature_set)ARM_ANY).core[1]) + && (CPU).core[1] == ((arm_feature_set)ARM_ANY).core[1] \ + && (CPU).core[2] == ((arm_feature_set)ARM_ANY).core[2]) #define ARM_MERGE_FEATURE_SETS(TARG,F1,F2) \ do \ { \ (TARG).core[0] = (F1).core[0] | (F2).core[0]; \ (TARG).core[1] = (F1).core[1] | (F2).core[1]; \ + (TARG).core[2] = (F1).core[2] | (F2).core[2]; \ (TARG).coproc = (F1).coproc | (F2).coproc; \ } \ while (0) @@ -451,6 +487,7 @@ typedef struct { \ (TARG).core[0] = (F1).core[0] &~ (F2).core[0]; \ (TARG).core[1] = (F1).core[1] &~ (F2).core[1]; \ + (TARG).core[2] = (F1).core[2] &~ (F2).core[2]; \ (TARG).coproc = (F1).coproc &~ (F2).coproc; \ } \ while (0) @@ -458,17 +495,27 @@ typedef struct #define ARM_FEATURE_EQUAL(T1,T2) \ ( (T1).core[0] == (T2).core[0] \ && (T1).core[1] == (T2).core[1] \ + && (T1).core[2] == (T2).core[2] \ && (T1).coproc == (T2).coproc) #define ARM_FEATURE_ZERO(T) \ - ((T).core[0] == 0 && (T).core[1] == 0 && (T).coproc == 0) + ((T).core[0] == 0 \ + && (T).core[1] == 0 \ + && (T).core[2] == 0 \ + && (T).coproc == 0) #define ARM_FEATURE_CORE_EQUAL(T1, T2) \ - ((T1).core[0] == (T2).core[0] && (T1).core[1] == (T2).core[1]) - -#define ARM_FEATURE_LOW(core, coproc) {{(core), 0}, (coproc)} -#define ARM_FEATURE_CORE(core1, core2) {{(core1), (core2)}, 0} -#define ARM_FEATURE_CORE_LOW(core) {{(core), 0}, 0} -#define ARM_FEATURE_CORE_HIGH(core) {{0, (core)}, 0} -#define ARM_FEATURE_COPROC(coproc) {{0, 0}, (coproc)} -#define ARM_FEATURE(core1, core2, coproc) {{(core1), (core2)}, (coproc)} + ((T1).core[0] == (T2).core[0] \ + && (T1).core[1] == (T2).core[1] \ + && (T1).core[2] == (T2).core[2]) + +#define ARM_FEATURE_LOW(core, coproc) {{(core), 0, 0}, (coproc)} +#define ARM_FEATURE_CORE(core1, core2) {{(core1), (core2), 0}, 0} +#define ARM_FEATURE_CORE_LOW(core) {{(core), 0, 0}, 0} +#define ARM_FEATURE_CORE_HIGH(core) {{0, (core), 0}, 0} +#define ARM_FEATURE_CORE_HIGH_HIGH(core) {{0, 0, (core)}, 0} +#define ARM_FEATURE_COPROC(coproc) {{0, 0, 0}, (coproc)} +#define ARM_FEATURE(core1, core2, coproc) {{(core1), (core2), 0}, (coproc)} +/* Below macro is used to set all fields in arm_feature_set struct. +*/ +#define ARM_FEATURE_ALL(core1, core2, core3, coproc) {{(core1), (core2), (core3)}, (coproc)} diff --git a/external/gpl3/binutils/dist/include/opcode/avr.h b/external/gpl3/binutils/dist/include/opcode/avr.h index 90cebbdc3cb..33db369815c 100644 --- a/external/gpl3/binutils/dist/include/opcode/avr.h +++ b/external/gpl3/binutils/dist/include/opcode/avr.h @@ -1,6 +1,6 @@ /* Opcode table for the Atmel AVR micro controllers. - Copyright (C) 2000-2020 Free Software Foundation, Inc. + Copyright (C) 2000-2022 Free Software Foundation, Inc. Contributed by Denis Chertykov <denisc@overta.ru> This program is free software; you can redistribute it and/or modify diff --git a/external/gpl3/binutils/dist/include/opcode/bfin.h b/external/gpl3/binutils/dist/include/opcode/bfin.h index 06796822d87..b2494abb07b 100644 --- a/external/gpl3/binutils/dist/include/opcode/bfin.h +++ b/external/gpl3/binutils/dist/include/opcode/bfin.h @@ -1,5 +1,5 @@ /* bfin.h -- Header file for ADI Blackfin opcode table - Copyright (C) 2005-2020 Free Software Foundation, Inc. + Copyright (C) 2005-2022 Free Software Foundation, Inc. This file is part of GDB, GAS, and the GNU binutils. diff --git a/external/gpl3/binutils/dist/include/opcode/cgen.h b/external/gpl3/binutils/dist/include/opcode/cgen.h index 95bbdf43e35..25a82768120 100644 --- a/external/gpl3/binutils/dist/include/opcode/cgen.h +++ b/external/gpl3/binutils/dist/include/opcode/cgen.h @@ -1,6 +1,6 @@ /* Header file for targets using CGEN: Cpu tools GENerator. - Copyright (C) 1996-2020 Free Software Foundation, Inc. + Copyright (C) 1996-2022 Free Software Foundation, Inc. This file is part of GDB, the GNU debugger, and the GNU Binutils. @@ -24,8 +24,7 @@ #include "symcat.h" #include "cgen/bitset.h" -/* ??? IWBN to replace bfd in the name. */ -#include "bfd_stdint.h" +#include <stdint.h> #ifdef __cplusplus extern "C" { @@ -1392,7 +1391,9 @@ enum cgen_cpu_open_arg { Multiple machines can be specified by repeated use. */ CGEN_CPU_OPEN_BFDMACH, /* Select endian, arg is CGEN_ENDIAN_*. */ - CGEN_CPU_OPEN_ENDIAN + CGEN_CPU_OPEN_ENDIAN, + /* Select instruction endian, arg is CGEN_ENDIAN_*. */ + CGEN_CPU_OPEN_INSN_ENDIAN, }; /* Open a cpu descriptor table for use. @@ -1461,8 +1462,13 @@ extern const CGEN_INSN * cgen_lookup_get_insn_operands /* Cover fns to bfd_get/set. */ extern CGEN_INSN_INT cgen_get_insn_value - (CGEN_CPU_DESC, unsigned char *, int); + (CGEN_CPU_DESC, unsigned char *, int, int); extern void cgen_put_insn_value + (CGEN_CPU_DESC, unsigned char *, int, CGEN_INSN_INT, int); + +extern CGEN_INSN_INT cgen_get_base_insn_value + (CGEN_CPU_DESC, unsigned char *, int); +extern void cgen_put_base_insn_value (CGEN_CPU_DESC, unsigned char *, int, CGEN_INSN_INT); /* Read in a cpu description file. diff --git a/external/gpl3/binutils/dist/include/opcode/convex.h b/external/gpl3/binutils/dist/include/opcode/convex.h index 28723055117..ae8916346af 100644 --- a/external/gpl3/binutils/dist/include/opcode/convex.h +++ b/external/gpl3/binutils/dist/include/opcode/convex.h @@ -1,5 +1,5 @@ /* Information for instruction disassembly on the Convex. - Copyright (C) 1989-2020 Free Software Foundation, Inc. + Copyright (C) 1989-2022 Free Software Foundation, Inc. This file is part of GDB. diff --git a/external/gpl3/binutils/dist/include/opcode/cr16.h b/external/gpl3/binutils/dist/include/opcode/cr16.h index 78053e4396d..64b04039695 100644 --- a/external/gpl3/binutils/dist/include/opcode/cr16.h +++ b/external/gpl3/binutils/dist/include/opcode/cr16.h @@ -1,5 +1,5 @@ /* cr16.h -- Header file for CR16 opcode and register tables. - Copyright (C) 2007-2020 Free Software Foundation, Inc. + Copyright (C) 2007-2022 Free Software Foundation, Inc. Contributed by M R Swami Reddy This file is part of GAS, GDB and the GNU binutils. @@ -425,7 +425,6 @@ extern const char * cr16_no_op_insn[]; /* Utility macros for string comparison. */ #define streq(a, b) (strcmp (a, b) == 0) -#define strneq(a, b, c) (strncmp (a, b, c) == 0) /* Long long type handling. */ /* Replace all appearances of 'long long int' with LONGLONG. */ diff --git a/external/gpl3/binutils/dist/include/opcode/cris.h b/external/gpl3/binutils/dist/include/opcode/cris.h index b3cc808f4f1..27d3646c103 100644 --- a/external/gpl3/binutils/dist/include/opcode/cris.h +++ b/external/gpl3/binutils/dist/include/opcode/cris.h @@ -1,5 +1,5 @@ /* cris.h -- Header file for CRIS opcode and register tables. - Copyright (C) 2000-2020 Free Software Foundation, Inc. + Copyright (C) 2000-2022 Free Software Foundation, Inc. Contributed by Axis Communications AB, Lund, Sweden. Originally written for GAS 1.38.1 by Mikael Asker. Updated, BFDized and GNUified by Hans-Peter Nilsson. diff --git a/external/gpl3/binutils/dist/include/opcode/crx.h b/external/gpl3/binutils/dist/include/opcode/crx.h index 45d331dd2a2..f69cbbfabbe 100644 --- a/external/gpl3/binutils/dist/include/opcode/crx.h +++ b/external/gpl3/binutils/dist/include/opcode/crx.h @@ -1,5 +1,5 @@ /* crx.h -- Header file for CRX opcode and register tables. - Copyright (C) 2004-2020 Free Software Foundation, Inc. + Copyright (C) 2004-2022 Free Software Foundation, Inc. Contributed by Tomer Levi, NSC, Israel. Originally written for GAS 2.12 by Tomer Levi, NSC, Israel. Updates, BFDizing, GNUifying and ELF support by Tomer Levi. diff --git a/external/gpl3/binutils/dist/include/opcode/csky.h b/external/gpl3/binutils/dist/include/opcode/csky.h index aa6bcce3d27..faecba11611 100644 --- a/external/gpl3/binutils/dist/include/opcode/csky.h +++ b/external/gpl3/binutils/dist/include/opcode/csky.h @@ -1,5 +1,5 @@ /* C-SKY assembler/disassembler support. - Copyright (C) 2004-2020 Free Software Foundation, Inc. + Copyright (C) 2004-2022 Free Software Foundation, Inc. Contributed by C-SKY Microsystems and Mentor Graphics. This file is part of GDB and GAS. @@ -22,39 +22,46 @@ #include "dis-asm.h" /* The following bitmasks control instruction set architecture. */ -#define CSKYV1_ISA_E1 (1 << 0) -#define CSKYV2_ISA_E1 (1 << 1) -#define CSKYV2_ISA_1E2 (1 << 2) -#define CSKYV2_ISA_2E3 (1 << 3) -#define CSKYV2_ISA_3E7 (1 << 4) -#define CSKYV2_ISA_7E10 (1 << 5) -#define CSKYV2_ISA_3E3R1 (1 << 6) - -#define CSKY_ISA_TRUST (1 << 11) -#define CSKY_ISA_CACHE (1 << 12) -#define CSKY_ISA_NVIC (1 << 13) -#define CSKY_ISA_CP (1 << 14) -#define CSKY_ISA_MP (1 << 15) -#define CSKY_ISA_MP_1E2 (1 << 16) -#define CSKY_ISA_JAVA (1 << 17) -#define CSKY_ISA_MAC (1 << 18) -#define CSKY_ISA_MAC_DSP (1 << 19) +#define CSKYV1_ISA_E1 ((uint64_t) 1 << 0) +#define CSKYV2_ISA_E1 ((uint64_t) 1 << 1) +#define CSKYV2_ISA_1E2 ((uint64_t) 1 << 2) +#define CSKYV2_ISA_2E3 ((uint64_t) 1 << 3) +#define CSKYV2_ISA_3E7 ((uint64_t) 1 << 4) +#define CSKYV2_ISA_7E10 ((uint64_t) 1 << 5) +#define CSKYV2_ISA_3E3R1 ((uint64_t) 1 << 6) +#define CSKYV2_ISA_3E3R2 ((uint64_t) 1 << 7) +#define CSKYV2_ISA_10E60 ((uint64_t) 1 << 8) +#define CSKYV2_ISA_3E3R3 ((uint64_t) 1 << 9) + +#define CSKY_ISA_TRUST ((uint64_t) 1 << 11) +#define CSKY_ISA_CACHE ((uint64_t) 1 << 12) +#define CSKY_ISA_NVIC ((uint64_t) 1 << 13) +#define CSKY_ISA_CP ((uint64_t) 1 << 14) +#define CSKY_ISA_MP ((uint64_t) 1 << 15) +#define CSKY_ISA_MP_1E2 ((uint64_t) 1 << 16) +#define CSKY_ISA_JAVA ((uint64_t) 1 << 17) +#define CSKY_ISA_MAC ((uint64_t) 1 << 18) +#define CSKY_ISA_MAC_DSP ((uint64_t) 1 << 19) /* Base ISA for csky v1 and v2. */ -#define CSKY_ISA_DSP (1 << 20) -#define CSKY_ISA_DSP_1E2 (1 << 21) -#define CSKY_ISA_DSP_ENHANCE (1 << 22) +#define CSKY_ISA_DSP ((uint64_t) 1 << 20) +#define CSKY_ISA_DSP_1E2 ((uint64_t) 1 << 21) +#define CSKY_ISA_DSP_ENHANCE ((uint64_t) 1 << 22) +#define CSKY_ISA_DSPE60 ((uint64_t) 1 << 23) /* Base float instruction (803f & 810f). */ -#define CSKY_ISA_FLOAT_E1 (1 << 25) +#define CSKY_ISA_FLOAT_E1 ((uint64_t) 1 << 25) /* M_FLOAT support (810f). */ -#define CSKY_ISA_FLOAT_1E2 (1 << 26) +#define CSKY_ISA_FLOAT_1E2 ((uint64_t) 1 << 26) /* 803 support (803f). */ -#define CSKY_ISA_FLOAT_1E3 (1 << 27) +#define CSKY_ISA_FLOAT_1E3 ((uint64_t) 1 << 27) /* 807 support (803f & 807f). */ -#define CSKY_ISA_FLOAT_3E4 (1 << 28) +#define CSKY_ISA_FLOAT_3E4 ((uint64_t) 1 << 28) +/* 860 support. */ +#define CSKY_ISA_FLOAT_7E60 ((uint64_t) 1 << 36) /* Vector DSP support. */ -#define CSKY_ISA_VDSP (1 << 29) +#define CSKY_ISA_VDSP ((uint64_t) 1 << 29) +#define CSKY_ISA_VDSP_2 ((uint64_t) 1 << 30) /* The following bitmasks control cpu architecture for CSKY. */ #define CSKY_ABI_V1 (1 << 28) @@ -67,8 +74,14 @@ #define CSKY_ARCH_801 0xa #define CSKY_ARCH_802 0x10 #define CSKY_ARCH_803 0x9 +/* 804 use the same arch flag as 803 yet. */ +#define CSKY_ARCH_804 0x9 +#define CSKY_ARCH_805 0x11 #define CSKY_ARCH_807 0x6 #define CSKY_ARCH_810 0x8 +#define CSKY_ARCH_860 0xb +/* 800 is a special arch supporting all instructions for ABIV2. */ +#define CSKY_ARCH_800 0x1f #define CSKY_ARCH_MAC (1 << 15) #define CSKY_ARCH_DSP (1 << 14) @@ -80,6 +93,11 @@ #define CSKY_ARCH_JAVA (1 << 8) #define CSKY_ARCH_APS (1 << 7) +/* eflag's Versions. */ +#define CSKY_VERSION_V1 (1 << 24) +#define CSKY_VERSION_V2 (2 << 24) +#define CSKY_VERSION_V3 (3 << 24) + #define IS_CSKY_V1(a) \ (((a) & CSKY_ABI_MASK) == CSKY_ABI_V1) #define IS_CSKY_V2(a) \ diff --git a/external/gpl3/binutils/dist/include/opcode/d10v.h b/external/gpl3/binutils/dist/include/opcode/d10v.h index d068879f321..6b80659bcc5 100644 --- a/external/gpl3/binutils/dist/include/opcode/d10v.h +++ b/external/gpl3/binutils/dist/include/opcode/d10v.h @@ -1,5 +1,5 @@ /* d10v.h -- Header file for D10V opcode table - Copyright (C) 1996-2020 Free Software Foundation, Inc. + Copyright (C) 1996-2022 Free Software Foundation, Inc. Written by Martin Hunt (hunt@cygnus.com), Cygnus Support This file is part of GDB, GAS, and the GNU binutils. diff --git a/external/gpl3/binutils/dist/include/opcode/d30v.h b/external/gpl3/binutils/dist/include/opcode/d30v.h index 2694d6d0e9a..bc01e779dde 100644 --- a/external/gpl3/binutils/dist/include/opcode/d30v.h +++ b/external/gpl3/binutils/dist/include/opcode/d30v.h @@ -1,5 +1,5 @@ /* d30v.h -- Header file for D30V opcode table - Copyright (C) 1997-2020 Free Software Foundation, Inc. + Copyright (C) 1997-2022 Free Software Foundation, Inc. Written by Martin Hunt (hunt@cygnus.com), Cygnus Solutions This file is part of GDB, GAS, and the GNU binutils. @@ -33,7 +33,7 @@ struct pd_reg { char *name; /* name to recognize */ char *pname; /* name to print for this register */ - int value; + unsigned int value; }; extern const struct pd_reg pre_defined_registers[]; diff --git a/external/gpl3/binutils/dist/include/opcode/dlx.h b/external/gpl3/binutils/dist/include/opcode/dlx.h index b0c984a686b..c52d76c745e 100644 --- a/external/gpl3/binutils/dist/include/opcode/dlx.h +++ b/external/gpl3/binutils/dist/include/opcode/dlx.h @@ -1,5 +1,5 @@ /* Table of opcodes for the DLX microprocess. - Copyright (C) 2002-2020 Free Software Foundation, Inc. + Copyright (C) 2002-2022 Free Software Foundation, Inc. This file is part of GDB and GAS. diff --git a/external/gpl3/binutils/dist/include/opcode/ft32.h b/external/gpl3/binutils/dist/include/opcode/ft32.h index 42cd64965db..7030f5a5564 100644 --- a/external/gpl3/binutils/dist/include/opcode/ft32.h +++ b/external/gpl3/binutils/dist/include/opcode/ft32.h @@ -1,5 +1,5 @@ /* Definitions for decoding the ft32 opcode table. - Copyright (C) 2013-2020 Free Software Foundation, Inc. + Copyright (C) 2013-2022 Free Software Foundation, Inc. Contributed by FTDI (support@ftdichip.com) This program is free software; you can redistribute it and/or modify diff --git a/external/gpl3/binutils/dist/include/opcode/h8300.h b/external/gpl3/binutils/dist/include/opcode/h8300.h index bc4f58b5774..f0628406e00 100644 --- a/external/gpl3/binutils/dist/include/opcode/h8300.h +++ b/external/gpl3/binutils/dist/include/opcode/h8300.h @@ -1,5 +1,5 @@ /* Opcode table for the H8/300 - Copyright (C) 1991-2020 Free Software Foundation, Inc. + Copyright (C) 1991-2022 Free Software Foundation, Inc. Written by Steve Chamberlain <sac@cygnus.com>. This file is part of GDB, the GNU Debugger and GAS, the GNU Assembler. diff --git a/external/gpl3/binutils/dist/include/opcode/i386.h b/external/gpl3/binutils/dist/include/opcode/i386.h index b01026a48c0..e34a98a3f2e 100644 --- a/external/gpl3/binutils/dist/include/opcode/i386.h +++ b/external/gpl3/binutils/dist/include/opcode/i386.h @@ -1,5 +1,5 @@ /* opcode/i386.h -- Intel 80386 opcode macros - Copyright (C) 1989-2020 Free Software Foundation, Inc. + Copyright (C) 1989-2022 Free Software Foundation, Inc. This file is part of GAS, the GNU Assembler, and GDB, the GNU Debugger. diff --git a/external/gpl3/binutils/dist/include/opcode/ia64.h b/external/gpl3/binutils/dist/include/opcode/ia64.h index bb557b81e3d..42a6812c3f8 100644 --- a/external/gpl3/binutils/dist/include/opcode/ia64.h +++ b/external/gpl3/binutils/dist/include/opcode/ia64.h @@ -1,5 +1,5 @@ /* ia64.h -- Header file for ia64 opcode table - Copyright (C) 1998-2020 Free Software Foundation, Inc. + Copyright (C) 1998-2022 Free Software Foundation, Inc. Contributed by David Mosberger-Tang <davidm@hpl.hp.com> This file is part of BFD, the Binary File Descriptor library. @@ -29,7 +29,7 @@ extern "C" { #endif -typedef BFD_HOST_U_64_BIT ia64_insn; +typedef uint64_t ia64_insn; enum ia64_insn_type { diff --git a/external/gpl3/binutils/dist/include/opcode/loongarch.h b/external/gpl3/binutils/dist/include/opcode/loongarch.h new file mode 100644 index 00000000000..c3922348a56 --- /dev/null +++ b/external/gpl3/binutils/dist/include/opcode/loongarch.h @@ -0,0 +1,239 @@ +/* LoongArch assembler/disassembler support. + + Copyright (C) 2021-2022 Free Software Foundation, Inc. + Contributed by Loongson Ltd. + + This file is part of GNU Binutils. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the license, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; see the file COPYING3. If not, + see <http://www.gnu.org/licenses/>. */ + +#ifndef _LOONGARCH_H_ +#define _LOONGARCH_H_ +#include <stdint.h> + +#ifdef __cplusplus +extern "C" +{ +#endif + + typedef uint32_t insn_t; + + struct loongarch_opcode + { + const insn_t match; + const insn_t mask; /* High 1 byte is main opcode and it must be 0xf. */ +#define LARCH_INSN_OPC(insn) ((insn & 0xf0000000) >> 28) + const char *const name; + + /* ACTUAL PARAMETER: + + // BNF with regular expression. +args : token* end + + // just few char separate 'iden' +token : ',' +| '(' +| ')' +| iden // maybe a label (include at least one alphabet), + maybe a number, maybe a expr +| regname + +regname : '$' iden + +iden : [a-zA-Z0-9\.\+\-]+ + +end : '\0' + + +FORMAT: A string to describe the format of actual parameter including +bit field infomation. For example, "r5:5,r0:5,sr10:16<<2" matches +"$12,$13,12345" and "$4,$7,a_label". That 'sr' means the instruction +may need relocate. '10:16' means bit field of instruction. +In a 'format', every 'escape's can be replaced to 'iden' or 'regname' +acrroding to its meaning. We fill all information needed by +disassembing and assembing to 'format'. + + // BNF with regular expression. +format : escape (literal+ escape)* literal* end +| (literal+ escape)* literal* end + +end : '\0' // Get here means parse end. + + // The intersection between any two among FIRST (end), FIRST + // (literal) and FIRST (escape) must be empty. + // So we can build a simple parser. +literal : ',' +| '(' +| ')' + + // Double '<'s means the real number is the immediate after shifting left. +escape : esc_ch bit_field '<' '<' dec2 +| esc_ch bit_field +| esc_ch // for MACRO. non-macro format must indicate 'bit_field' + + // '|' means to concatenate nonadjacent bit fields + // For example, "10:16|0:4" means + // "16 bits starting from the 10th bit concatenating with 4 bits + // starting from the 0th bit". + // This is to say "[25..10]||[3..0]" (little endian). +b_field : dec2 ':' dec2 +| dec2 ':' dec2 '|' bit_field + +esc_ch : 's' 'r' // signed immediate or label need relocate +| 's' // signed immediate no need relocate +| 'u' // unsigned immediate +| 'l' // label needed relocate +| 'r' // general purpose registers +| 'f' // FPU registers +| 'v' // 128 bit SIMD register +| 'x' // 256 bit SIMD register + +dec2 : [1-9][0-9]? +| 0 + +*/ + const char *const format; + + /* MACRO: Indicate how a macro instruction expand for assembling. + The main is to replace the '%num'(means the 'num'th 'escape' in + 'format') in 'macro' string to get the real instruction. + + Maybe need + */ + const char *const macro; + const int *include; + const int *exclude; + + const unsigned long pinfo; +#define USELESS 0x0l + }; + + struct hash_control; + + struct loongarch_ase + { + const int *enabled; + struct loongarch_opcode *const opcodes; + const int *include; + const int *exclude; + + /* For disassemble to create main opcode hash table. */ + const struct loongarch_opcode *opc_htab[16]; + unsigned char opc_htab_inited; + + /* For GAS to create hash table. */ + struct htab *name_hash_entry; + }; + + extern int is_unsigned (const char *); + extern int is_signed (const char *); + extern int is_branch_label (const char *); + + extern int loongarch_get_bit_field_width (const char *bit_field, char **end); + extern int32_t loongarch_decode_imm (const char *bit_field, insn_t insn, + int si); + +#define MAX_ARG_NUM_PLUS_2 9 + + extern size_t loongarch_split_args_by_comma (char *args, + const char *arg_strs[]); + extern char *loongarch_cat_splited_strs (const char *arg_strs[]); + extern insn_t loongarch_foreach_args ( + const char *format, const char *arg_strs[], + int32_t (*helper) (char esc1, char esc2, const char *bit_field, + const char *arg, void *context), + void *context); + + extern int loongarch_check_format (const char *format); + extern int loongarch_check_macro (const char *format, const char *macro); + + extern char *loongarch_expand_macro_with_format_map ( + const char *format, const char *macro, const char *const arg_strs[], + const char *(*map) (char esc1, char esc2, const char *arg), + char *(*helper) (const char *const arg_strs[], void *context), + void *context, size_t len_str); + extern char *loongarch_expand_macro ( + const char *macro, const char *const arg_strs[], + char *(*helper) (const char *const arg_strs[], void *context), + void *context, size_t len_str); + extern size_t loongarch_bits_imm_needed (int64_t imm, int si); + + extern void loongarch_eliminate_adjacent_repeat_char (char *dest, char c); + + extern int loongarch_parse_dis_options (const char *opts_in); + extern void loongarch_disassemble_one ( + int64_t pc, insn_t insn, + int (*fprintf_func) (void *stream, const char *format, ...), void *stream); + + extern const char *const loongarch_r_normal_name[32]; + extern const char *const loongarch_r_lp64_name[32]; + extern const char *const loongarch_r_lp64_name1[32]; + extern const char *const loongarch_f_normal_name[32]; + extern const char *const loongarch_f_lp64_name[32]; + extern const char *const loongarch_f_lp64_name1[32]; + extern const char *const loongarch_c_normal_name[8]; + extern const char *const loongarch_cr_normal_name[4]; + extern const char *const loongarch_v_normal_name[32]; + extern const char *const loongarch_x_normal_name[32]; + + extern struct loongarch_ase loongarch_ASEs[]; + + extern struct loongarch_ASEs_option + { + struct opt_abi + { + int elf_abi; + } abi; +#define ase_abi abi.elf_abi + + struct opt_isa + { + int use_ilp32; + int use_lp64; + + int use_soft_float; + int use_single_float; + int use_double_float; + + int use_lsx; + int use_lasx; + + int use_la_local_with_abs; + int use_la_global_with_pcrel; + int use_la_global_with_abs; + } isa; +#define ase_ilp32 isa.use_ilp32 +#define ase_lp64 isa.use_lp64 + +#define ase_nf isa.use_soft_float +#define ase_sf isa.use_single_float +#define ase_df isa.use_double_float + +#define ase_lsx isa.use_lsx +#define ase_lasx isa.use_lasx + +#define ase_labs isa.use_la_local_with_abs +#define ase_gpcr isa.use_la_global_with_pcrel +#define ase_gabs isa.use_la_global_with_abs + + } LARCH_opts; + + extern size_t loongarch_insn_length (insn_t insn); + +#ifdef __cplusplus +} +#endif + +#endif /* _LOONGARCH_H_ */ diff --git a/external/gpl3/binutils/dist/include/opcode/m68hc11.h b/external/gpl3/binutils/dist/include/opcode/m68hc11.h index 1c2b7c0304d..0911a287e54 100644 --- a/external/gpl3/binutils/dist/include/opcode/m68hc11.h +++ b/external/gpl3/binutils/dist/include/opcode/m68hc11.h @@ -1,5 +1,5 @@ /* m68hc11.h -- Header file for Motorola 68HC11 & 68HC12 opcode table - Copyright (C) 1999-2020 Free Software Foundation, Inc. + Copyright (C) 1999-2022 Free Software Foundation, Inc. Written by Stephane Carrez (stcarrez@nerim.fr) This file is part of GDB, GAS, and the GNU binutils. diff --git a/external/gpl3/binutils/dist/include/opcode/m68k.h b/external/gpl3/binutils/dist/include/opcode/m68k.h index 7f8243c4819..20784f7a283 100644 --- a/external/gpl3/binutils/dist/include/opcode/m68k.h +++ b/external/gpl3/binutils/dist/include/opcode/m68k.h @@ -1,5 +1,5 @@ /* Opcode table header for m680[01234]0/m6888[12]/m68851. - Copyright (C) 1989-2020 Free Software Foundation, Inc. + Copyright (C) 1989-2022 Free Software Foundation, Inc. This file is part of GDB, GAS, and the GNU binutils. diff --git a/external/gpl3/binutils/dist/include/opcode/metag.h b/external/gpl3/binutils/dist/include/opcode/metag.h index 0f85ec1e024..b1ade3df18d 100644 --- a/external/gpl3/binutils/dist/include/opcode/metag.h +++ b/external/gpl3/binutils/dist/include/opcode/metag.h @@ -1,5 +1,5 @@ /* Imagination Technologies Meta opcode table. - Copyright (C) 2013-2020 Free Software Foundation, Inc. + Copyright (C) 2013-2022 Free Software Foundation, Inc. Contributed by Imagination Technologies Ltd. This file is part of GDB and GAS. diff --git a/external/gpl3/binutils/dist/include/opcode/mmix.h b/external/gpl3/binutils/dist/include/opcode/mmix.h index 1efbe7f0ef7..e158827b8c4 100644 --- a/external/gpl3/binutils/dist/include/opcode/mmix.h +++ b/external/gpl3/binutils/dist/include/opcode/mmix.h @@ -1,5 +1,5 @@ /* mmix.h -- Header file for MMIX opcode table - Copyright (C) 2001-2020 Free Software Foundation, Inc. + Copyright (C) 2001-2022 Free Software Foundation, Inc. Written by Hans-Peter Nilsson (hp@bitrange.com) This file is part of GDB, GAS, and the GNU binutils. diff --git a/external/gpl3/binutils/dist/include/opcode/mn10200.h b/external/gpl3/binutils/dist/include/opcode/mn10200.h index 9d1d7b6450c..780be663945 100644 --- a/external/gpl3/binutils/dist/include/opcode/mn10200.h +++ b/external/gpl3/binutils/dist/include/opcode/mn10200.h @@ -1,5 +1,5 @@ /* mn10200.h -- Header file for Matsushita 10200 opcode table - Copyright (C) 1996-2020 Free Software Foundation, Inc. + Copyright (C) 1996-2022 Free Software Foundation, Inc. Written by Jeff Law, Cygnus Support This file is part of GDB, GAS, and the GNU binutils. diff --git a/external/gpl3/binutils/dist/include/opcode/mn10300.h b/external/gpl3/binutils/dist/include/opcode/mn10300.h index 406403ceca8..713616affb6 100644 --- a/external/gpl3/binutils/dist/include/opcode/mn10300.h +++ b/external/gpl3/binutils/dist/include/opcode/mn10300.h @@ -1,5 +1,5 @@ /* mn10300.h -- Header file for Matsushita 10300 opcode table - Copyright (C) 1996-2020 Free Software Foundation, Inc. + Copyright (C) 1996-2022 Free Software Foundation, Inc. Written by Jeff Law, Cygnus Support This file is part of GDB, GAS, and the GNU binutils. diff --git a/external/gpl3/binutils/dist/include/opcode/moxie.h b/external/gpl3/binutils/dist/include/opcode/moxie.h index 94af2faf0ab..09895aa736c 100644 --- a/external/gpl3/binutils/dist/include/opcode/moxie.h +++ b/external/gpl3/binutils/dist/include/opcode/moxie.h @@ -1,5 +1,5 @@ /* Definitions for decoding the moxie opcode table. - Copyright (C) 2009-2020 Free Software Foundation, Inc. + Copyright (C) 2009-2022 Free Software Foundation, Inc. Contributed by Anthony Green (green@moxielogic.com). This program is free software; you can redistribute it and/or modify diff --git a/external/gpl3/binutils/dist/include/opcode/msp430-decode.h b/external/gpl3/binutils/dist/include/opcode/msp430-decode.h index fde77bc6e9c..336c88fa129 100644 --- a/external/gpl3/binutils/dist/include/opcode/msp430-decode.h +++ b/external/gpl3/binutils/dist/include/opcode/msp430-decode.h @@ -1,5 +1,5 @@ /* Opcode decoder for the TI MSP430 - Copyright (C) 2012-2020 Free Software Foundation, Inc. + Copyright (C) 2012-2022 Free Software Foundation, Inc. Written by DJ Delorie <dj@redhat.com> This file is part of GDB, the GNU Debugger. diff --git a/external/gpl3/binutils/dist/include/opcode/msp430.h b/external/gpl3/binutils/dist/include/opcode/msp430.h index 96fe674c8fb..b55fd720799 100644 --- a/external/gpl3/binutils/dist/include/opcode/msp430.h +++ b/external/gpl3/binutils/dist/include/opcode/msp430.h @@ -1,6 +1,6 @@ /* Opcode table for the TI MSP430 microcontrollers - Copyright (C) 2002-2020 Free Software Foundation, Inc. + Copyright (C) 2002-2022 Free Software Foundation, Inc. Contributed by Dmitry Diky <diwil@mail.ru> This program is free software; you can redistribute it and/or modify diff --git a/external/gpl3/binutils/dist/include/opcode/nds32.h b/external/gpl3/binutils/dist/include/opcode/nds32.h index 9ab1cbdf086..8aabc3f15ea 100644 --- a/external/gpl3/binutils/dist/include/opcode/nds32.h +++ b/external/gpl3/binutils/dist/include/opcode/nds32.h @@ -1,5 +1,5 @@ /* nds32.h -- Header file for nds32 opcode table - Copyright (C) 2012-2020 Free Software Foundation, Inc. + Copyright (C) 2012-2022 Free Software Foundation, Inc. Contributed by Andes Technology Corporation. This program is free software; you can redistribute it and/or modify diff --git a/external/gpl3/binutils/dist/include/opcode/nfp.h b/external/gpl3/binutils/dist/include/opcode/nfp.h index 59d4527c0da..c649a689cdb 100644 --- a/external/gpl3/binutils/dist/include/opcode/nfp.h +++ b/external/gpl3/binutils/dist/include/opcode/nfp.h @@ -1,5 +1,5 @@ /* nfp.h. NFP opcode list. - Copyright (C) 2017-2020 Free Software Foundation, Inc. + Copyright (C) 2017-2022 Free Software Foundation, Inc. Contributed by Francois H. Theron <francois.theron@netronome.com> This file is part of the GNU opcodes library. @@ -23,7 +23,7 @@ #define _NFP_H_ #include "bfd.h" -#include "bfd_stdint.h" +#include <stdint.h> #include "elf/nfp.h" #ifdef __cplusplus diff --git a/external/gpl3/binutils/dist/include/opcode/nios2.h b/external/gpl3/binutils/dist/include/opcode/nios2.h index a23c182a4f0..f2080d9aca7 100644 --- a/external/gpl3/binutils/dist/include/opcode/nios2.h +++ b/external/gpl3/binutils/dist/include/opcode/nios2.h @@ -1,5 +1,5 @@ /* Nios II opcode list for GAS, the GNU assembler. - Copyright (C) 2012-2020 Free Software Foundation, Inc. + Copyright (C) 2012-2022 Free Software Foundation, Inc. Contributed by Nigel Gray (ngray@altera.com). Contributed by Mentor Graphics, Inc. diff --git a/external/gpl3/binutils/dist/include/opcode/nios2r1.h b/external/gpl3/binutils/dist/include/opcode/nios2r1.h index 4daa2b207b6..15e8fbf9357 100644 --- a/external/gpl3/binutils/dist/include/opcode/nios2r1.h +++ b/external/gpl3/binutils/dist/include/opcode/nios2r1.h @@ -1,5 +1,5 @@ /* Nios II R1 opcode list for GAS, the GNU assembler. - Copyright (C) 2013-2020 Free Software Foundation, Inc. + Copyright (C) 2013-2022 Free Software Foundation, Inc. Contributed by Mentor Graphics, Inc. This file is part of the GNU opcodes library. diff --git a/external/gpl3/binutils/dist/include/opcode/nios2r2.h b/external/gpl3/binutils/dist/include/opcode/nios2r2.h index 49722e8d1a9..e51863d947b 100644 --- a/external/gpl3/binutils/dist/include/opcode/nios2r2.h +++ b/external/gpl3/binutils/dist/include/opcode/nios2r2.h @@ -1,5 +1,5 @@ /* Nios II R2 opcode list for GAS, the GNU assembler. - Copyright (C) 2013-2020 Free Software Foundation, Inc. + Copyright (C) 2013-2022 Free Software Foundation, Inc. Contributed by Mentor Graphics, Inc. This file is part of the GNU opcodes library. diff --git a/external/gpl3/binutils/dist/include/opcode/np1.h b/external/gpl3/binutils/dist/include/opcode/np1.h index 8af9aa154fa..9c8cc4ebadc 100644 --- a/external/gpl3/binutils/dist/include/opcode/np1.h +++ b/external/gpl3/binutils/dist/include/opcode/np1.h @@ -1,5 +1,5 @@ /* Print GOULD NPL instructions for GDB, the GNU debugger. - Copyright (C) 1986-2020 Free Software Foundation, Inc. + Copyright (C) 1986-2022 Free Software Foundation, Inc. This file is part of GDB. diff --git a/external/gpl3/binutils/dist/include/opcode/ns32k.h b/external/gpl3/binutils/dist/include/opcode/ns32k.h index 24699b5f0ea..bf46254cf0e 100644 --- a/external/gpl3/binutils/dist/include/opcode/ns32k.h +++ b/external/gpl3/binutils/dist/include/opcode/ns32k.h @@ -1,5 +1,5 @@ /* ns32k-opcode.h -- Opcode table for National Semi 32k processor - Copyright (C) 1987-2020 Free Software Foundation, Inc. + Copyright (C) 1987-2022 Free Software Foundation, Inc. This file is part of GAS, the GNU Assembler. diff --git a/external/gpl3/binutils/dist/include/opcode/pdp11.h b/external/gpl3/binutils/dist/include/opcode/pdp11.h index 196011c0de4..407f49c6589 100644 --- a/external/gpl3/binutils/dist/include/opcode/pdp11.h +++ b/external/gpl3/binutils/dist/include/opcode/pdp11.h @@ -1,5 +1,5 @@ /* PDP-11 opcde list. - Copyright (C) 2001-2020 Free Software Foundation, Inc. + Copyright (C) 2001-2022 Free Software Foundation, Inc. This file is part of GDB and GAS. diff --git a/external/gpl3/binutils/dist/include/opcode/pj.h b/external/gpl3/binutils/dist/include/opcode/pj.h index e4af02bfaf2..19a730be6a8 100644 --- a/external/gpl3/binutils/dist/include/opcode/pj.h +++ b/external/gpl3/binutils/dist/include/opcode/pj.h @@ -1,5 +1,5 @@ /* Definitions for decoding the picoJava opcode table. - Copyright (C) 1999-2020 Free Software Foundation, Inc. + Copyright (C) 1999-2022 Free Software Foundation, Inc. Contributed by Steve Chamberlain of Transmeta (sac@pobox.com). This program is free software; you can redistribute it and/or modify diff --git a/external/gpl3/binutils/dist/include/opcode/pn.h b/external/gpl3/binutils/dist/include/opcode/pn.h index e0f1bc5fa62..ef6450562a6 100644 --- a/external/gpl3/binutils/dist/include/opcode/pn.h +++ b/external/gpl3/binutils/dist/include/opcode/pn.h @@ -1,5 +1,5 @@ /* Print GOULD PN (PowerNode) instructions for GDB, the GNU debugger. - Copyright (C) 1986-2020 Free Software Foundation, Inc. + Copyright (C) 1986-2022 Free Software Foundation, Inc. This file is part of GDB. diff --git a/external/gpl3/binutils/dist/include/opcode/pru.h b/external/gpl3/binutils/dist/include/opcode/pru.h index 74cc27a544f..f45da919d37 100644 --- a/external/gpl3/binutils/dist/include/opcode/pru.h +++ b/external/gpl3/binutils/dist/include/opcode/pru.h @@ -1,5 +1,5 @@ /* TI PRU opcode list for GAS, the GNU assembler. - Copyright (C) 2014-2020 Free Software Foundation, Inc. + Copyright (C) 2014-2022 Free Software Foundation, Inc. Contributed by Dimitar Dimitrov <dimitar@dinux.eu> This file is part of the GNU opcodes library. @@ -44,25 +44,27 @@ enum overflow_type no_overflow }; -enum opcode_format_type { - opcode_format1, - opcode_format2ab, - opcode_format2abl, - opcode_format2c, - opcode_format2de, - opcode_format45, - opcode_format6 +enum opcode_format_type +{ + opcode_format1, + opcode_format2ab, + opcode_format2abl, + opcode_format2c, + opcode_format2de, + opcode_format45, + opcode_format6 }; /* Opcode ID listing. Used for indexing by the simulator. */ -enum pru_instr_type { - prui_add, prui_adc, prui_sub, prui_suc, prui_lsl, prui_lsr, prui_rsb, - prui_rsc, prui_and, prui_or, prui_xor, prui_min, prui_max, prui_clr, - prui_set, prui_not, prui_jmp, prui_jal, prui_ldi, prui_halt, prui_slp, - prui_xin, prui_xout, prui_xchg, prui_sxin, prui_sxout, prui_sxchg, - prui_loop, prui_iloop, prui_qbgt, prui_qbge, prui_qblt, prui_qble, - prui_qbeq, prui_qbne, prui_qba, prui_qbbs, prui_qbbc, prui_lbbo, - prui_sbbo, prui_lbco, prui_sbco +enum pru_instr_type +{ + prui_add, prui_adc, prui_sub, prui_suc, prui_lsl, prui_lsr, prui_rsb, + prui_rsc, prui_and, prui_or, prui_xor, prui_min, prui_max, prui_clr, + prui_set, prui_not, prui_jmp, prui_jal, prui_ldi, prui_lmbd, + prui_halt, prui_slp, prui_xin, prui_xout, prui_xchg, prui_sxin, + prui_sxout, prui_sxchg, prui_loop, prui_iloop, prui_qbgt, prui_qbge, + prui_qblt, prui_qble, prui_qbeq, prui_qbne, prui_qba, prui_qbbs, + prui_qbbc, prui_lbbo, prui_sbbo, prui_lbco, prui_sbco }; /* This structure holds information for a particular instruction. diff --git a/external/gpl3/binutils/dist/include/opcode/pyr.h b/external/gpl3/binutils/dist/include/opcode/pyr.h index 8041ea4c417..374468ef7f2 100644 --- a/external/gpl3/binutils/dist/include/opcode/pyr.h +++ b/external/gpl3/binutils/dist/include/opcode/pyr.h @@ -1,6 +1,6 @@ /* pyramid.opcode.h -- gdb initial attempt. - Copyright (C) 2001-2020 Free Software Foundation, Inc. + Copyright (C) 2001-2022 Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by diff --git a/external/gpl3/binutils/dist/include/opcode/rl78.h b/external/gpl3/binutils/dist/include/opcode/rl78.h index bcc5e6dfba0..de4b2c2d315 100644 --- a/external/gpl3/binutils/dist/include/opcode/rl78.h +++ b/external/gpl3/binutils/dist/include/opcode/rl78.h @@ -1,5 +1,5 @@ /* Opcode decoder for the Renesas RL78 - Copyright (C) 2011-2020 Free Software Foundation, Inc. + Copyright (C) 2011-2022 Free Software Foundation, Inc. Written by DJ Delorie <dj@redhat.com> This file is part of GDB, the GNU Debugger and GAS, the GNU Assembler. diff --git a/external/gpl3/binutils/dist/include/opcode/rx.h b/external/gpl3/binutils/dist/include/opcode/rx.h index 95b94b68b67..c490d2f5d1a 100644 --- a/external/gpl3/binutils/dist/include/opcode/rx.h +++ b/external/gpl3/binutils/dist/include/opcode/rx.h @@ -1,5 +1,5 @@ /* Opcode decoder for the Renesas RX - Copyright (C) 2008-2020 Free Software Foundation, Inc. + Copyright (C) 2008-2022 Free Software Foundation, Inc. Written by DJ Delorie <dj@redhat.com> This file is part of GDB, the GNU Debugger and GAS, the GNU Assembler. diff --git a/external/gpl3/binutils/dist/include/opcode/s390.h b/external/gpl3/binutils/dist/include/opcode/s390.h index c4af871ae0b..3362d999081 100644 --- a/external/gpl3/binutils/dist/include/opcode/s390.h +++ b/external/gpl3/binutils/dist/include/opcode/s390.h @@ -1,5 +1,5 @@ /* s390.h -- Header file for S390 opcode table - Copyright (C) 2000-2020 Free Software Foundation, Inc. + Copyright (C) 2000-2022 Free Software Foundation, Inc. Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com). This file is part of BFD, the Binary File Descriptor library. @@ -44,6 +44,7 @@ enum s390_opcode_cpu_val S390_OPCODE_Z13, S390_OPCODE_ARCH12, S390_OPCODE_ARCH13, + S390_OPCODE_ARCH14, S390_OPCODE_MAXCPU }; diff --git a/external/gpl3/binutils/dist/include/opcode/score-datadep.h b/external/gpl3/binutils/dist/include/opcode/score-datadep.h index 41394e9553d..b3beb93c5d3 100644 --- a/external/gpl3/binutils/dist/include/opcode/score-datadep.h +++ b/external/gpl3/binutils/dist/include/opcode/score-datadep.h @@ -1,5 +1,5 @@ /* score-datadep.h -- Score Instructions data dependency table - Copyright (C) 2006-2020 Free Software Foundation, Inc. + Copyright (C) 2006-2022 Free Software Foundation, Inc. Contributed by: Brain.lin (brain.lin@sunplusct.com) Mei Ligang (ligang@sunnorth.com.cn) diff --git a/external/gpl3/binutils/dist/include/opcode/score-inst.h b/external/gpl3/binutils/dist/include/opcode/score-inst.h index 25d2d2b81dc..ca79e87a50d 100644 --- a/external/gpl3/binutils/dist/include/opcode/score-inst.h +++ b/external/gpl3/binutils/dist/include/opcode/score-inst.h @@ -1,5 +1,5 @@ /* score-inst.h -- Score Instructions Table - Copyright (C) 2006-2020 Free Software Foundation, Inc. + Copyright (C) 2006-2022 Free Software Foundation, Inc. Contributed by: Brain.lin (brain.lin@sunplusct.com) Mei Ligang (ligang@sunnorth.com.cn) diff --git a/external/gpl3/binutils/dist/include/opcode/sparc.h b/external/gpl3/binutils/dist/include/opcode/sparc.h index 18a7b812683..8b16f3e8732 100644 --- a/external/gpl3/binutils/dist/include/opcode/sparc.h +++ b/external/gpl3/binutils/dist/include/opcode/sparc.h @@ -1,5 +1,5 @@ /* Definitions for opcode table for the sparc. - Copyright (C) 1989-2020 Free Software Foundation, Inc. + Copyright (C) 1989-2022 Free Software Foundation, Inc. This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and the GNU Binutils. diff --git a/external/gpl3/binutils/dist/include/opcode/spu-insns.h b/external/gpl3/binutils/dist/include/opcode/spu-insns.h index cc8b7760491..2d5313def2e 100644 --- a/external/gpl3/binutils/dist/include/opcode/spu-insns.h +++ b/external/gpl3/binutils/dist/include/opcode/spu-insns.h @@ -1,6 +1,6 @@ /* SPU ELF support for BFD. - Copyright (C) 2006-2020 Free Software Foundation, Inc. + Copyright (C) 2006-2022 Free Software Foundation, Inc. This file is part of BFD, the Binary File Descriptor library. diff --git a/external/gpl3/binutils/dist/include/opcode/spu.h b/external/gpl3/binutils/dist/include/opcode/spu.h index d8505ef6da3..194dbe336b7 100644 --- a/external/gpl3/binutils/dist/include/opcode/spu.h +++ b/external/gpl3/binutils/dist/include/opcode/spu.h @@ -1,6 +1,6 @@ /* SPU ELF support for BFD. - Copyright (C) 2006-2020 Free Software Foundation, Inc. + Copyright (C) 2006-2022 Free Software Foundation, Inc. This file is part of GDB, GAS, and the GNU binutils. diff --git a/external/gpl3/binutils/dist/include/opcode/tic30.h b/external/gpl3/binutils/dist/include/opcode/tic30.h index 34ae57faab5..b18408d4f41 100644 --- a/external/gpl3/binutils/dist/include/opcode/tic30.h +++ b/external/gpl3/binutils/dist/include/opcode/tic30.h @@ -1,5 +1,5 @@ /* tic30.h -- Header file for TI TMS320C30 opcode table - Copyright (C) 1998-2020 Free Software Foundation, Inc. + Copyright (C) 1998-2022 Free Software Foundation, Inc. Contributed by Steven Haworth (steve@pm.cse.rmit.edu.au) This file is part of GDB, GAS, and the GNU binutils. diff --git a/external/gpl3/binutils/dist/include/opcode/tic4x.h b/external/gpl3/binutils/dist/include/opcode/tic4x.h index 04e3f0853d2..e6ce8b629a4 100644 --- a/external/gpl3/binutils/dist/include/opcode/tic4x.h +++ b/external/gpl3/binutils/dist/include/opcode/tic4x.h @@ -1,6 +1,6 @@ /* Table of opcodes for the Texas Instruments TMS320C[34]X family. - Copyright (C) 2002-2020 Free Software Foundation, Inc. + Copyright (C) 2002-2022 Free Software Foundation, Inc. Contributed by Michael P. Hayes (m.hayes@elec.canterbury.ac.nz) diff --git a/external/gpl3/binutils/dist/include/opcode/tic54x.h b/external/gpl3/binutils/dist/include/opcode/tic54x.h index 153e4f00191..444073494b1 100644 --- a/external/gpl3/binutils/dist/include/opcode/tic54x.h +++ b/external/gpl3/binutils/dist/include/opcode/tic54x.h @@ -1,5 +1,5 @@ /* tic54x.h -- Header file for TI TMS320C54X opcode table - Copyright (C) 1999-2020 Free Software Foundation, Inc. + Copyright (C) 1999-2022 Free Software Foundation, Inc. Written by Timothy Wall (twall@cygnus.com) This file is part of GDB, GAS, and the GNU binutils. @@ -152,10 +152,10 @@ typedef struct _template extern const insn_template tic54x_unknown_opcode; extern const insn_template tic54x_optab[]; extern const insn_template tic54x_paroptab[]; -extern const tic54x_symbol mmregs[], regs[]; -extern const tic54x_symbol condition_codes[], cc2_codes[], status_bits[]; -extern const tic54x_symbol cc3_codes[]; -extern const char *misc_symbols[]; +extern const tic54x_symbol tic54x_mmregs[], tic54x_regs[]; +extern const tic54x_symbol tic54x_condition_codes[], tic54x_cc2_codes[]; +extern const tic54x_symbol tic54x_status_bits[], tic54x_cc3_codes[]; +extern const char *tic54x_misc_symbols[]; struct disassemble_info; extern const insn_template* tic54x_get_insn (struct disassemble_info *, bfd_vma, unsigned short, int *); diff --git a/external/gpl3/binutils/dist/include/opcode/tic6x-control-registers.h b/external/gpl3/binutils/dist/include/opcode/tic6x-control-registers.h index 3623e30e513..5f7153ebb89 100644 --- a/external/gpl3/binutils/dist/include/opcode/tic6x-control-registers.h +++ b/external/gpl3/binutils/dist/include/opcode/tic6x-control-registers.h @@ -1,5 +1,5 @@ /* TI C6X control register information. - Copyright (C) 2010-2020 Free Software Foundation, Inc. + Copyright (C) 2010-2022 Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by diff --git a/external/gpl3/binutils/dist/include/opcode/tic6x-insn-formats.h b/external/gpl3/binutils/dist/include/opcode/tic6x-insn-formats.h index 28bff392064..5c9daea93c5 100644 --- a/external/gpl3/binutils/dist/include/opcode/tic6x-insn-formats.h +++ b/external/gpl3/binutils/dist/include/opcode/tic6x-insn-formats.h @@ -1,5 +1,5 @@ /* TI C6X instruction format information. - Copyright (C) 2010-2020 Free Software Foundation, Inc. + Copyright (C) 2010-2022 Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by diff --git a/external/gpl3/binutils/dist/include/opcode/tic6x-opcode-table.h b/external/gpl3/binutils/dist/include/opcode/tic6x-opcode-table.h index dff2d71ff79..a766125c516 100644 --- a/external/gpl3/binutils/dist/include/opcode/tic6x-opcode-table.h +++ b/external/gpl3/binutils/dist/include/opcode/tic6x-opcode-table.h @@ -1,5 +1,5 @@ /* TI C6X opcode table. - Copyright (C) 2010-2020 Free Software Foundation, Inc. + Copyright (C) 2010-2022 Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by @@ -38,7 +38,7 @@ #define FIX2(a, b) 2, { a, b } #define FIX3(a, b, c) 3, { a, b, c } #define FIX4(a, b, c, d) 4, { a, b, c, d } -#define OP0() 0, { { 0, 0, FALSE, 0, 0, 0, 0 } } +#define OP0() 0, { { 0, 0, false, 0, 0, 0, 0 } } #define OP1(a) 1, { a } #define OP2(a, b) 2, { a, b } #define OP3(a, b, c) 3, { a, b, c } diff --git a/external/gpl3/binutils/dist/include/opcode/tic6x.h b/external/gpl3/binutils/dist/include/opcode/tic6x.h index 2914d8e3f1f..1c6c84ea639 100644 --- a/external/gpl3/binutils/dist/include/opcode/tic6x.h +++ b/external/gpl3/binutils/dist/include/opcode/tic6x.h @@ -1,5 +1,5 @@ /* TI C6X opcode information. - Copyright (C) 2010-2020 Free Software Foundation, Inc. + Copyright (C) 2010-2022 Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by @@ -697,26 +697,26 @@ typedef struct unsigned int header; /* Whether each word uses compact instructions. */ - bfd_boolean word_compact[7]; + bool word_compact[7]; /* Whether loads are protected. */ - bfd_boolean prot; + bool prot; /* Whether instructions use the high register set. */ - bfd_boolean rs; + bool rs; /* Data size. */ unsigned int dsz; /* Whether compact instructions in the S unit are decoded as branches. */ - bfd_boolean br; + bool br; /* Whether compact instructions saturate. */ - bfd_boolean sat; + bool sat; /* P-bits. */ - bfd_boolean p_bits[14]; + bool p_bits[14]; } tic6x_fetch_packet_header; #ifdef __cplusplus diff --git a/external/gpl3/binutils/dist/include/opcode/tilegx.h b/external/gpl3/binutils/dist/include/opcode/tilegx.h index 2c982790420..df0ed71d33a 100644 --- a/external/gpl3/binutils/dist/include/opcode/tilegx.h +++ b/external/gpl3/binutils/dist/include/opcode/tilegx.h @@ -1,6 +1,6 @@ /* TILE-Gx opcode information. * - * Copyright (C) 2011-2020 Free Software Foundation, Inc. + * Copyright (C) 2011-2022 Free Software Foundation, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/external/gpl3/binutils/dist/include/opcode/tilepro.h b/external/gpl3/binutils/dist/include/opcode/tilepro.h index 511df96a44a..1c30bdf9b8c 100644 --- a/external/gpl3/binutils/dist/include/opcode/tilepro.h +++ b/external/gpl3/binutils/dist/include/opcode/tilepro.h @@ -1,6 +1,6 @@ /* TILEPro opcode information. * - * Copyright (C) 2011-2020 Free Software Foundation, Inc. + * Copyright (C) 2011-2022 Free Software Foundation, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -1412,6 +1412,7 @@ typedef enum TILEPRO_PIPELINE_Y0, TILEPRO_PIPELINE_Y1, TILEPRO_PIPELINE_Y2, + TILEPRO_NUM_PIPELINE_ENCODINGS } tilepro_pipeline; #define tilepro_is_x_pipeline(p) ((int)(p) <= (int)TILEPRO_PIPELINE_X1) @@ -1432,9 +1433,6 @@ enum /* Maximum number of instructions in a bundle (2 for X, 3 for Y). */ TILEPRO_MAX_INSTRUCTIONS_PER_BUNDLE = 3, - /* How many different pipeline encodings are there? X0, X1, Y0, Y1, Y2. */ - TILEPRO_NUM_PIPELINE_ENCODINGS = 5, - /* Log base 2 of TILEPRO_BUNDLE_SIZE_IN_BYTES. */ TILEPRO_LOG2_BUNDLE_SIZE_IN_BYTES = 3, diff --git a/external/gpl3/binutils/dist/include/opcode/v850.h b/external/gpl3/binutils/dist/include/opcode/v850.h index 214f9526ceb..d0374562d34 100644 --- a/external/gpl3/binutils/dist/include/opcode/v850.h +++ b/external/gpl3/binutils/dist/include/opcode/v850.h @@ -1,5 +1,5 @@ /* v850.h -- Header file for NEC V850 opcode table - Copyright (C) 1996-2020 Free Software Foundation, Inc. + Copyright (C) 1996-2022 Free Software Foundation, Inc. Written by J.T. Conklin, Cygnus Support This file is part of GDB, GAS, and the GNU binutils. @@ -133,7 +133,7 @@ struct v850_operand operand value is legal, *ERRMSG will be unchanged (most operands can accept any value). */ unsigned long (* insert) - (unsigned long instruction, long op, const char ** errmsg); + (unsigned long instruction, unsigned long op, const char ** errmsg); /* Extraction function. This is used by the disassembler. To extract this operand type from an instruction, check this field. diff --git a/external/gpl3/binutils/dist/include/opcode/vax.h b/external/gpl3/binutils/dist/include/opcode/vax.h index 2eddc5cc068..baf9c226fa5 100644 --- a/external/gpl3/binutils/dist/include/opcode/vax.h +++ b/external/gpl3/binutils/dist/include/opcode/vax.h @@ -1,5 +1,5 @@ /* Vax opcde list. - Copyright (C) 1989-2020 Free Software Foundation, Inc. + Copyright (C) 1989-2022 Free Software Foundation, Inc. This file is part of GDB and GAS. diff --git a/external/gpl3/binutils/dist/include/opcode/visium.h b/external/gpl3/binutils/dist/include/opcode/visium.h index 44d9c184fb1..5a435b660fb 100644 --- a/external/gpl3/binutils/dist/include/opcode/visium.h +++ b/external/gpl3/binutils/dist/include/opcode/visium.h @@ -1,6 +1,6 @@ /* Opcode table header for Visium. - Copyright (C) 2003-2020 Free Software Foundation, Inc. + Copyright (C) 2003-2022 Free Software Foundation, Inc. This file is part of GDB, GAS, and GNU binutils. diff --git a/external/gpl3/binutils/dist/include/opcode/wasm.h b/external/gpl3/binutils/dist/include/opcode/wasm.h index 1ada9e9fd3e..ab51fbf3017 100644 --- a/external/gpl3/binutils/dist/include/opcode/wasm.h +++ b/external/gpl3/binutils/dist/include/opcode/wasm.h @@ -1,5 +1,5 @@ /* WebAssembly assembler/disassembler support. - Copyright (C) 2017-2020 Free Software Foundation, Inc. + Copyright (C) 2017-2022 Free Software Foundation, Inc. This file is part of GAS, the GNU assembler. diff --git a/external/gpl3/binutils/dist/include/opcode/xgate.h b/external/gpl3/binutils/dist/include/opcode/xgate.h index 2134f5dcb9b..febec6842b3 100644 --- a/external/gpl3/binutils/dist/include/opcode/xgate.h +++ b/external/gpl3/binutils/dist/include/opcode/xgate.h @@ -1,5 +1,5 @@ /* xgate.h -- Freescale XGATE opcode list - Copyright (C) 2010-2020 Free Software Foundation, Inc. + Copyright (C) 2010-2022 Free Software Foundation, Inc. Written by Sean Keys (skeys@ipdatasys.com) This file is part of the GNU opcodes library. |
