diff options
| author | tv <tv@NetBSD.org> | 1999-02-02 19:51:16 +0000 |
|---|---|---|
| committer | tv <tv@NetBSD.org> | 1999-02-02 19:51:16 +0000 |
| commit | 2e8b57510c512922b01977bf9c07cb986ddbaa67 (patch) | |
| tree | 99f0ff2ba55134ad127492d887b5b6567773ef25 /gnu/dist/include/opcode | |
| parent | 269cb58003ce63bbb1763517287a25b909583ae4 (diff) | |
By popular demand, import binutils 2.9.1.
Diffstat (limited to 'gnu/dist/include/opcode')
| -rw-r--r-- | gnu/dist/include/opcode/ChangeLog | 267 | ||||
| -rw-r--r-- | gnu/dist/include/opcode/arc.h | 274 | ||||
| -rw-r--r-- | gnu/dist/include/opcode/cgen.h | 671 | ||||
| -rw-r--r-- | gnu/dist/include/opcode/d10v.h | 27 | ||||
| -rw-r--r-- | gnu/dist/include/opcode/h8300.h | 391 | ||||
| -rw-r--r-- | gnu/dist/include/opcode/m68k.h | 41 | ||||
| -rw-r--r-- | gnu/dist/include/opcode/mips.h | 64 | ||||
| -rw-r--r-- | gnu/dist/include/opcode/sparc.h | 4 | ||||
| -rw-r--r-- | gnu/dist/include/opcode/tic30.h | 691 | ||||
| -rw-r--r-- | gnu/dist/include/opcode/v850.h | 154 |
10 files changed, 2097 insertions, 487 deletions
diff --git a/gnu/dist/include/opcode/ChangeLog b/gnu/dist/include/opcode/ChangeLog index 8a1b7d75f2b..40ea655e561 100644 --- a/gnu/dist/include/opcode/ChangeLog +++ b/gnu/dist/include/opcode/ChangeLog @@ -1,3 +1,218 @@ +Mon Mar 30 21:31:56 1998 Ian Lance Taylor <ian@cygnus.com> + + * i386.h: Revert March 24 patch; no more LinearAddress. + +Mon Mar 30 10:25:54 1998 Alan Modra <alan@spri.levels.unisa.edu.au> + + * i386.h (i386_optab): Remove fwait (9b) from all floating point + instructions, and instead add FWait opcode modifier. Add short + form of fldenv and fstenv. + (FWAIT_OPCODE): Define. + + * i386.h (i386_optab): Change second operand constraint of `mov + sreg,reg|mem' instruction from Reg16|Mem to WordReg|WordMem to + allow legal instructions such as `movl %gs,%esi' + +Fri Mar 27 18:30:52 1998 Ian Lance Taylor <ian@cygnus.com> + + * h8300.h: Various changes to fully bracket initializers. + +Tue Mar 24 18:32:47 1998 H.J. Lu <hjl@gnu.org> + + * i386.h: Set LinearAddress for lidt and lgdt. + +Mon Mar 2 10:44:07 1998 Doug Evans <devans@seba.cygnus.com> + + * cgen.h (CGEN_BOOL_ATTR): New macro. + +Mon Feb 23 10:38:21 1998 Doug Evans <devans@seba.cygnus.com> + + * cgen.h (CGEN_CAT3): Delete. Use CONCAT3 now. + (cgen_insn): Record syntax and format entries here, rather than + separately. + +Tue Feb 17 21:42:56 1998 Nick Clifton <nickc@cygnus.com> + + * cgen.h (CGEN_SYNTAX_MAKE_FIELD): New macro. + +Tue Feb 17 16:00:56 1998 Doug Evans <devans@seba.cygnus.com> + + * cgen.h (cgen_insert_fn): Change type of result to const char *. + (cgen_parse_{signed,unsigned}_integer): Delete min,max arguments. + (CGEN_{INSN,KEYWORD,OPERAND}_NBOOL_ATTRS): Renamed from ..._MAX_ATTRS. + +Thu Feb 12 18:30:41 1998 Doug Evans <devans@canuck.cygnus.com> + + * cgen.h (lookup_insn): New argument alias_p. + +Thu Feb 12 03:41:00 1998 J"orn Rennecke <amylaar@cygnus.co.uk> + +Fix rac to accept only a0: + * d10v.h (OPERAND_ACC): Split into: + (OPERAND_ACC0, OPERAND_ACC1) . + (OPERAND_GPR): Define. + +Wed Feb 11 17:31:53 1998 Doug Evans <devans@seba.cygnus.com> + + * cgen.h (CGEN_FIELDS): Define here. + (CGEN_HW_ENTRY): New member `type'. + (hw_list): Delete decl. + (enum cgen_mode): Declare. + (CGEN_OPERAND): New member `hw'. + (enum cgen_operand_instance_type): Declare. + (CGEN_OPERAND_INSTANCE): New type. + (CGEN_INSN): New member `operands'. + (CGEN_OPCODE_DATA): Make hw_list const. + (get_insn_operands,lookup_insn): Add prototypes for. + +Tue Feb 3 17:11:23 1998 Doug Evans <devans@seba.cygnus.com> + + * cgen.h (CGEN_INSN_MAX_ATTRS): Renamed from CGEN_MAX_INSN_ATTRS. + (CGEN_HW_ENTRY): Move `next' entry to end of struct. + (CGEN_KEYWORD_MAX_ATTRS): Renamed from CGEN_MAX_KEYWORD_ATTRS. + (CGEN_OPERAND_MAX_ATTRS): Renamed from CGEN_MAX_OPERAND_ATTRS. + +Mon Feb 2 19:19:15 1998 Ian Lance Taylor <ian@cygnus.com> + + * cgen.h: Correct typo in comment end marker. + +Mon Feb 2 17:10:38 1998 Steve Haworth <steve@pm.cse.rmit.EDU.AU> + + * tic30.h: New file. + +Thu Jan 22 17:54:56 1998 Nick Clifton <nickc@cygnus.com> + + * cgen.h: Add prototypes for cgen_save_fixups(), + cgen_restore_fixups(), and cgen_swap_fixups(). Change prototype + of cgen_asm_finish_insn() to return a char *. + +Wed Jan 14 17:21:43 1998 Nick Clifton <nickc@cygnus.com> + + * cgen.h: Formatting changes to improve readability. + +Mon Jan 12 11:37:36 1998 Doug Evans <devans@seba.cygnus.com> + + * cgen.h (*): Clean up pass over `struct foo' usage. + (CGEN_ATTR): Make unsigned char. + (CGEN_ATTR_TYPE): Update. + (CGEN_ATTR_{ENTRY,TABLE}): New types. + (cgen_base): Move member `attrs' to cgen_insn. + (CGEN_KEYWORD): New member `null_entry'. + (CGEN_{SYNTAX,FORMAT}): New types. + (cgen_insn): Format and syntax separated from each other. + +Mon Dec 1 12:24:44 1997 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de> + + * m68k.h: Fix comment describing operand types. + +Tue Nov 18 18:45:14 1997 J"orn Rennecke <amylaar@cygnus.co.uk> + + * d10v.h (OPERAND_FLAG): Split into: + (OPERAND_FFLAG, OPERAND_CFLAG) . + +Thu Nov 13 11:04:24 1997 Gavin Koch <gavin@cygnus.com> + + * mips.h (struct mips_opcode): Changed comments to reflect new + field usage. + +Fri Oct 24 22:36:20 1997 Ken Raeburn <raeburn@cygnus.com> + + * mips.h: Added to comments a quick-ref list of all assigned + operand type characters. + (OP_{MASK,SH}_PERFREG): New macros. + +Wed Oct 22 17:28:33 1997 Richard Henderson <rth@cygnus.com> + + * sparc.h: Add '_' and '/' for v9a asr's. + Patch from David Miller <davem@vger.rutgers.edu> + +Tue Oct 14 13:22:29 1997 Jeffrey A Law (law@cygnus.com) + + * h8300.h: Bit ops with absolute addresses not in the 8 bit + area are not available in the base model (H8/300). + +Thu Sep 25 13:03:41 1997 Ian Lance Taylor <ian@cygnus.com> + + * m68k.h: Remove documentation of ` operand specifier. + +Wed Sep 24 19:00:34 1997 Ian Lance Taylor <ian@cygnus.com> + + * m68k.h: Document q and v operand specifiers. + +Mon Sep 15 18:28:37 1997 Nick Clifton <nickc@cygnus.com> + + * v850.h (struct v850_opcode): Add processors field. + (PROCESSOR_V850, PROCESSOR_ALL): New bit constants. + +Mon Sep 8 14:05:45 1997 Doug Evans <dje@canuck.cygnus.com> + + * cgen.h: Move assembler interface section + up so cgen_parse_operand_result is defined for cgen_parse_address. + (cgen_parse_address): Update prototype. + +Tue Sep 2 15:32:32 1997 Nick Clifton <nickc@cygnus.com> + + * v850.h (V850_OPREAND_ADJUST_SHORT_MEMORY): Removed. + +Tue Aug 26 12:21:52 1997 Ian Lance Taylor <ian@cygnus.com> + + * i386.h (two_byte_segment_defaults): Correct base register 5 in + modes 1 and 2 to be ss rather than ds. From Gabriel Paubert + <paubert@iram.es>. + + * i386.h: Set ud2 to 0x0f0b. From Gabriel Paubert + <paubert@iram.es>. + + * i386.h: Comment fixes for ficom[p]?{s,l} from Gabriel Paubert + <paubert@iram.es>. + + * i386.h (JUMP_ON_CX_ZERO): Uncomment (define again). + (JUMP_ON_ECX_ZERO): Remove commented out macro. + +Fri Aug 22 10:38:29 1997 Nick Clifton <nickc@cygnus.com> + + * v850.h (V850_NOT_R0): New flag. + +Mon Aug 18 11:05:58 1997 Nick Clifton <nickc@cygnus.com> + + * v850.h (struct v850_opcode): Remove flags field. + +Wed Aug 13 18:45:48 1997 Nick Clifton <nickc@cygnus.com> + + * v850.h (struct v850_opcode): Add flags field. + (struct v850_operand): Extend meaning of 'bits' and 'shift' + fields. + + +Fri Aug 8 16:58:42 1997 Doug Evans <dje@canuck.cygnus.com> + + * arc.h: New file. + +Thu Jul 24 21:16:58 1997 Doug Evans <dje@canuck.cygnus.com> + + * sparc.h (sparc_opcodes): Declare as const. + +Thu Jul 10 12:53:25 1997 Jeffrey A Law (law@cygnus.com) + + * mips.h (FP_S, FP_D): Define. Bitmasks indicating if an insn + uses single or double precision floating point resources. + (INSN_NO_ISA, INSN_ISA1): Define. + (cpu specific INSN macros): Tweak into bitmasks outside the range + of INSN_ISA field. + +Mon Jun 16 14:10:00 1997 H.J. Lu <hjl@gnu.ai.mit.edu> + + * i386.h: Fix pand opcode. + +Mon Jun 2 11:35:09 1997 Gavin Koch <gavin@cygnus.com> + + * mips.h: Widen INSN_ISA and move it to a more convenient + bit position. Add INSN_3900. + +Tue May 20 11:25:29 1997 Gavin Koch <gavin@cygnus.com> + + * mips.h (struct mips_opcode): added new field membership. + Mon May 12 16:26:50 1997 H.J. Lu <hjl@gnu.ai.mit.edu> * i386.h (movd): only Reg32 is allowed. @@ -42,6 +257,10 @@ Fri Apr 4 14:02:32 1997 Ian Lance Taylor <ian@cygnus.com> * i386.h: Correct opcode values for fsubp, fsubrp, fdivp, and fdivrp. +Tue Mar 25 22:57:26 1997 Stu Grossman (grossman@critters.cygnus.com) + + * v850.h (extract): Make unsigned. + Mon Mar 24 14:38:15 1997 Ian Lance Taylor <ian@cygnus.com> * i386.h: Add iclr. @@ -81,6 +300,11 @@ Wed Jan 29 09:37:25 1997 Jeffrey A Law (law@cygnus.com) * mn10200.h (MN10200_OPERAND_RELAX): Define. +Tue Dec 31 15:05:41 1996 Michael Meissner <meissner@tiktok.cygnus.com> + + * v850.h (V850_OPERAND_ADJUST_SHORT_MEMORY): New flag to adjust + type IV instruction offsets. + Wed Dec 18 10:06:31 1996 Jeffrey A Law (law@cygnus.com) * mn10200.h (MN10200_OPERAND_NOCHECK): Define. @@ -89,6 +313,7 @@ Sat Dec 14 10:48:31 1996 Fred Fish <fnf@ninemoons.com> * mn10200.h: Fix comment, mn10200_operand not powerpc_operand. * mn10300.h: Fix comment, mn10300_operand not powerpc_operand. + * v850.h: Fix comment, v850_operand not powerpc_operand. Mon Dec 9 16:45:39 1996 Jeffrey A Law (law@cygnus.com) @@ -132,6 +357,10 @@ Fri Nov 1 10:31:02 1996 Richard Henderson <rth@tamu.edu> implementation. (struct alpha_operand): Move flags slot for better packing. +Tue Oct 29 12:19:10 1996 Jeffrey A Law (law@cygnus.com) + + * v850.h (V850_OPERAND_RELAX): New operand flag. + Thu Oct 10 14:29:11 1996 Jeffrey A Law (law@cygnus.com) * mn10300.h (FMT_*): Move operand format definitions @@ -155,10 +384,42 @@ Wed Oct 2 21:31:26 1996 Jeffrey A Law (law@cygnus.com) * mn10x00.h: New file. +Fri Sep 27 18:26:46 1996 Stu Grossman (grossman@critters.cygnus.com) + + * v850.h: Add new flag to indicate this instruction uses a PC + displacement. + Fri Sep 13 14:58:13 1996 Jeffrey A Law (law@cygnus.com) * h8300.h (stmac): Add missing instruction. +Sat Aug 31 16:02:03 1996 Jeffrey A Law (law@cygnus.com) + + * v850.h (v850_opcode): Remove "size" field. Add "memop" + field. + +Fri Aug 23 10:39:08 1996 Jeffrey A Law (law@cygnus.com) + + * v850.h (V850_OPERAND_EP): Define. + + * v850.h (v850_opcode): Add size field. + +Thu Aug 22 16:51:25 1996 J.T. Conklin <jtc@rtl.cygnus.com> + + * v850.h (v850_operands): Add insert and extract fields, pointers + to functions used to handle unusual operand encoding. + (V850_OPERAND_REG, V850_OPERAND_SRG, V850_OPERAND_CC, + V850_OPERAND_SIGNED): Defined. + +Wed Aug 21 17:45:10 1996 J.T. Conklin <jtc@rtl.cygnus.com> + + * v850.h (v850_operands): Add flags field. + (OPERAND_REG, OPERAND_NUM): Defined. + +Tue Aug 20 14:52:02 1996 J.T. Conklin <jtc@rtl.cygnus.com> + + * v850.h: New file. + Fri Aug 16 14:44:15 1996 James G. Smith <jsmith@cygnus.co.uk> * mips.h (OP_SH_LOCC, OP_SH_HICC, OP_MASK_CC, OP_SH_COP1NORM, @@ -419,14 +680,12 @@ Wed Jun 21 18:49:51 1995 Ken Raeburn <raeburn@cujo.cygnus.com> [!NO_DEFAULT_SIZES]: An omitted size defaults to `w'. (m68k_opcode_aliases): Add more aliases. - Fri Apr 14 22:15:34 1995 Ken Raeburn <raeburn@cujo.cygnus.com> * m68k.h: Added explcitly short-sized conditional branches, and a bunch of aliases (fmov*, ftest*, tdivul) to support gcc's svr4-based configurations. - Mon Mar 13 21:30:01 1995 Ken Raeburn <raeburn@cujo.cygnus.com> Mon Feb 27 08:36:39 1995 Bryan Ford <baford@cs.utah.edu> @@ -455,7 +714,6 @@ Wed Mar 8 03:13:23 1995 Ken Raeburn <raeburn@cujo.cygnus.com> [DONT_DEFINE_TABLE]: Declare numopcodes, numaliases, and m68k_opcode_aliases; update declaration of m68k_opcodes. - Mon Mar 6 10:02:00 1995 Jeff Law (law@snake.cs.utah.edu) * hppa.h (delay_type): Delete unused enumeration. @@ -479,7 +737,6 @@ Wed Feb 15 12:19:52 1995 Ian Lance Taylor <ian@cygnus.com> * mips.h (M_ULD, M_ULD_A, M_USD, M_USD_A): Define. - Mon Feb 6 10:35:23 1995 J.T. Conklin <jtc@rtl.cygnus.com> * i386.h: added cpuid instruction , and dr[0-7] aliases for the @@ -510,8 +767,6 @@ Tue Jan 17 10:55:30 1995 Ian Lance Taylor <ian@sanguine.cygnus.com> * mips.h (INSN_ISA, INSN_4650): Define. - - Wed Oct 19 13:34:17 1994 Ian Lance Taylor <ian@sanguine.cygnus.com> * a29k.h: Add operand type 'I' for `inv' and `iretinv'. On diff --git a/gnu/dist/include/opcode/arc.h b/gnu/dist/include/opcode/arc.h new file mode 100644 index 00000000000..a1e0ca15263 --- /dev/null +++ b/gnu/dist/include/opcode/arc.h @@ -0,0 +1,274 @@ +/* Opcode table for the ARC. + Copyright 1994, 1995, 1997 Free Software Foundation, Inc. + Contributed by Doug Evans (dje@cygnus.com). + +This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and +the GNU Binutils. + +GAS/GDB is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GAS/GDB is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GAS or GDB; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* List of the various cpu types. + The tables currently use bit masks to say whether the instruction or + whatever is supported by a particular cpu. This lets us have one entry + apply to several cpus. + + This duplicates bfd_mach_arc_xxx. For now I wish to isolate this from bfd + and bfd from this. Also note that these numbers are bit values as we want + to allow for things available on more than one ARC (but not necessarily all + ARCs). */ + +/* The `base' cpu must be 0 (table entries are omitted for the base cpu). + The cpu type is treated independently of endianness. + The complete `mach' number includes endianness. + These values are internal to opcodes/bfd/binutils/gas. */ +#define ARC_MACH_BASE 0 +#define ARC_MACH_UNUSED1 1 +#define ARC_MACH_UNUSED2 2 +#define ARC_MACH_UNUSED4 4 +/* Additional cpu values can be inserted here and ARC_MACH_BIG moved down. */ +#define ARC_MACH_BIG 8 + +/* Mask of number of bits necessary to record cpu type. */ +#define ARC_MACH_CPU_MASK 7 +/* Mask of number of bits necessary to record cpu type + endianness. */ +#define ARC_MACH_MASK 15 + +/* Type to denote an ARC instruction (at least a 32 bit unsigned int). */ +typedef unsigned int arc_insn; + +struct arc_opcode { + char *syntax; /* syntax of insn */ + unsigned long mask, value; /* recognize insn if (op&mask)==value */ + int flags; /* various flag bits */ + +/* Values for `flags'. */ + +/* Return CPU number, given flag bits. */ +#define ARC_OPCODE_CPU(bits) ((bits) & ARC_MACH_CPU_MASK) +/* Return MACH number, given flag bits. */ +#define ARC_OPCODE_MACH(bits) ((bits) & ARC_MACH_MASK) +/* First opcode flag bit available after machine mask. */ +#define ARC_OPCODE_FLAG_START ((ARC_MACH_MASK + 1) << 0) +/* This insn is a conditional branch. */ +#define ARC_OPCODE_COND_BRANCH (ARC_OPCODE_FLAG_START) + + /* These values are used to optimize assembly and disassembly. Each insn is + on a list of related insns (same first letter for assembly, same insn code + for disassembly). */ + struct arc_opcode *next_asm; /* Next instruction to try during assembly. */ + struct arc_opcode *next_dis; /* Next instruction to try during disassembly. */ + + /* Macros to create the hash values for the lists. */ +#define ARC_HASH_OPCODE(string) \ + ((string)[0] >= 'a' && (string)[0] <= 'z' ? (string)[0] - 'a' : 26) +#define ARC_HASH_ICODE(insn) \ + ((unsigned int) (insn) >> 27) + + /* Macros to access `next_asm', `next_dis' so users needn't care about the + underlying mechanism. */ +#define ARC_OPCODE_NEXT_ASM(op) ((op)->next_asm) +#define ARC_OPCODE_NEXT_DIS(op) ((op)->next_dis) +}; + +struct arc_operand_value { + char *name; /* eg: "eq" */ + short value; /* eg: 1 */ + unsigned char type; /* index into `arc_operands' */ + unsigned char flags; /* various flag bits */ + +/* Values for `flags'. */ + +/* Return CPU number, given flag bits. */ +#define ARC_OPVAL_CPU(bits) ((bits) & ARC_MACH_CPU_MASK) +/* Return MACH number, given flag bits. */ +#define ARC_OPVAL_MACH(bits) ((bits) & ARC_MACH_MASK) +}; + +struct arc_operand { + /* One of the insn format chars. */ + unsigned char fmt; + + /* The number of bits in the operand (may be unused for a modifier). */ + unsigned char bits; + + /* How far the operand is left shifted in the instruction, or + the modifier's flag bit (may be unused for a modifier. */ + unsigned char shift; + + /* Various flag bits. */ + int flags; + +/* Values for `flags'. */ + +/* This operand is a suffix to the opcode. */ +#define ARC_OPERAND_SUFFIX 1 + +/* This operand is a relative branch displacement. The disassembler + prints these symbolically if possible. */ +#define ARC_OPERAND_RELATIVE_BRANCH 2 + +/* This operand is an absolute branch address. The disassembler + prints these symbolically if possible. */ +#define ARC_OPERAND_ABSOLUTE_BRANCH 4 + +/* This operand is an address. The disassembler + prints these symbolically if possible. */ +#define ARC_OPERAND_ADDRESS 8 + +/* This operand is a long immediate value. */ +#define ARC_OPERAND_LIMM 0x10 + +/* This operand takes signed values. */ +#define ARC_OPERAND_SIGNED 0x20 + +/* This operand takes signed values, but also accepts a full positive + range of values. That is, if bits is 16, it takes any value from + -0x8000 to 0xffff. */ +#define ARC_OPERAND_SIGNOPT 0x40 + +/* This operand should be regarded as a negative number for the + purposes of overflow checking (i.e., the normal most negative + number is disallowed and one more than the normal most positive + number is allowed). This flag will only be set for a signed + operand. */ +#define ARC_OPERAND_NEGATIVE 0x80 + +/* This operand doesn't really exist. The program uses these operands + in special ways. */ +#define ARC_OPERAND_FAKE 0x100 + +/* Modifier values. */ +/* A dot is required before a suffix. Eg: .le */ +#define ARC_MOD_DOT 0x1000 + +/* A normal register is allowed (not used, but here for completeness). */ +#define ARC_MOD_REG 0x2000 + +/* An auxiliary register name is expected. */ +#define ARC_MOD_AUXREG 0x4000 + +/* Sum of all ARC_MOD_XXX bits. */ +#define ARC_MOD_BITS 0x7000 + +/* Non-zero if the operand type is really a modifier. */ +#define ARC_MOD_P(X) ((X) & ARC_MOD_BITS) + + /* Insertion function. This is used by the assembler. To insert an + operand value into an instruction, check this field. + + If it is NULL, execute + i |= (p & ((1 << o->bits) - 1)) << o->shift; + (I is the instruction which we are filling in, O is a pointer to + this structure, and OP is the opcode value; this assumes twos + complement arithmetic). + + If this field is not NULL, then simply call it with the + instruction and the operand value. It will return the new value + of the instruction. If the ERRMSG argument is not NULL, then if + the operand value is illegal, *ERRMSG will be set to a warning + string (the operand will be inserted in any case). If the + operand value is legal, *ERRMSG will be unchanged. + + REG is non-NULL when inserting a register value. */ + + arc_insn (*insert) PARAMS ((arc_insn insn, + const struct arc_operand *operand, int mods, + const struct arc_operand_value *reg, long value, + const char **errmsg)); + + /* Extraction function. This is used by the disassembler. To + extract this operand type from an instruction, check this field. + + If it is NULL, compute + op = ((i) >> o->shift) & ((1 << o->bits) - 1); + if ((o->flags & ARC_OPERAND_SIGNED) != 0 + && (op & (1 << (o->bits - 1))) != 0) + op -= 1 << o->bits; + (I is the instruction, O is a pointer to this structure, and OP + is the result; this assumes twos complement arithmetic). + + If this field is not NULL, then simply call it with the + instruction value. It will return the value of the operand. If + the INVALID argument is not NULL, *INVALID will be set to + non-zero if this operand type can not actually be extracted from + this operand (i.e., the instruction does not match). If the + operand is valid, *INVALID will not be changed. + + INSN is a pointer to an array of two `arc_insn's. The first element is + the insn, the second is the limm if present. + + Operands that have a printable form like registers and suffixes have + their struct arc_operand_value pointer stored in OPVAL. */ + + long (*extract) PARAMS ((arc_insn *insn, + const struct arc_operand *operand, + int mods, const struct arc_operand_value **opval, + int *invalid)); +}; + +/* Bits that say what version of cpu we have. + These should be passed to arc_init_opcode_tables. + At present, all there is is the cpu type. */ + +/* CPU number, given value passed to `arc_init_opcode_tables'. */ +#define ARC_HAVE_CPU(bits) ((bits) & ARC_MACH_CPU_MASK) +/* MACH number, given value passed to `arc_init_opcode_tables'. */ +#define ARC_HAVE_MACH(bits) ((bits) & ARC_MACH_MASK) + +/* Special register values: */ +#define ARC_REG_SHIMM_UPDATE 61 +#define ARC_REG_SHIMM 63 +#define ARC_REG_LIMM 62 + +/* Non-zero if REG is a constant marker. */ +#define ARC_REG_CONSTANT_P(REG) ((REG) >= 61) + +/* Positions and masks of various fields: */ +#define ARC_SHIFT_REGA 21 +#define ARC_SHIFT_REGB 15 +#define ARC_SHIFT_REGC 9 +#define ARC_MASK_REG 63 + +/* Delay slot types. */ +#define ARC_DELAY_NONE 0 /* no delay slot */ +#define ARC_DELAY_NORMAL 1 /* delay slot in both cases */ +#define ARC_DELAY_JUMP 2 /* delay slot only if branch taken */ + +/* Non-zero if X will fit in a signed 9 bit field. */ +#define ARC_SHIMM_CONST_P(x) ((long) (x) >= -256 && (long) (x) <= 255) + +extern const struct arc_operand arc_operands[]; +extern const int arc_operand_count; +extern /*const*/ struct arc_opcode arc_opcodes[]; +extern const int arc_opcodes_count; +extern const struct arc_operand_value arc_suffixes[]; +extern const int arc_suffixes_count; +extern const struct arc_operand_value arc_reg_names[]; +extern const int arc_reg_names_count; +extern unsigned char arc_operand_map[]; + +/* Utility fns in arc-opc.c. */ +int arc_get_opcode_mach PARAMS ((int, int)); +/* `arc_opcode_init_tables' must be called before `arc_xxx_supported'. */ +void arc_opcode_init_tables PARAMS ((int)); +void arc_opcode_init_insert PARAMS ((void)); +void arc_opcode_init_extract PARAMS ((void)); +const struct arc_opcode *arc_opcode_lookup_asm PARAMS ((const char *)); +const struct arc_opcode *arc_opcode_lookup_dis PARAMS ((unsigned int)); +int arc_opcode_limm_p PARAMS ((long *)); +const struct arc_operand_value *arc_opcode_lookup_suffix PARAMS ((const struct arc_operand *type, int value)); +int arc_opcode_supported PARAMS ((const struct arc_opcode *)); +int arc_opval_supported PARAMS ((const struct arc_operand_value *)); diff --git a/gnu/dist/include/opcode/cgen.h b/gnu/dist/include/opcode/cgen.h index cda3373fd33..ab59f24694a 100644 --- a/gnu/dist/include/opcode/cgen.h +++ b/gnu/dist/include/opcode/cgen.h @@ -1,6 +1,6 @@ /* Header file for targets using CGEN: Cpu tools GENerator. -Copyright (C) 1996, 1997 Free Software Foundation, Inc. +Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc. This file is part of GDB, the GNU debugger, and the GNU Binutils. @@ -14,22 +14,13 @@ but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #ifndef CGEN_H #define CGEN_H -#ifndef CGEN_CAT3 -#if defined(__STDC__) || defined(ALMOST_STDC) -#define CGEN_XCAT3(a,b,c) a ## b ## c -#define CGEN_CAT3(a,b,c) CGEN_XCAT3 (a, b, c) -#else -#define CGEN_CAT3(a,b,c) a/**/b/**/c -#endif -#endif - /* Prepend the cpu name, defined in cpu-opc.h, and _cgen_ to symbol S. The lack of spaces in the arg list is important for non-stdc systems. This file is included by <cpu>-opc.h. @@ -37,7 +28,7 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ dependent portions will be declared as "unknown_cgen_foo". */ #ifndef CGEN_SYM -#define CGEN_SYM(s) CGEN_CAT3 (unknown,_cgen_,s) +#define CGEN_SYM(s) CONCAT3 (unknown,_cgen_,s) #endif /* This file contains the static (unchanging) pieces and as much other stuff @@ -60,7 +51,7 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #ifdef CGEN_INT_INSN typedef unsigned int cgen_insn_t; #else -typedef char *cgen_insn_t; +typedef char * cgen_insn_t; #endif #ifdef __GNUC__ @@ -71,7 +62,8 @@ typedef char *cgen_insn_t; /* Perhaps we should just use bfd.h, but it's not clear one would want to require that yet. */ -enum cgen_endian { +enum cgen_endian +{ CGEN_ENDIAN_UNKNOWN, CGEN_ENDIAN_LITTLE, CGEN_ENDIAN_BIG @@ -81,8 +73,9 @@ enum cgen_endian { Attributes are used to describe various random things. */ /* Struct to record attribute information. */ -typedef struct { - unsigned int num_nonbools; +typedef struct +{ + unsigned char num_nonbools; unsigned int bool; unsigned int nonbool[1]; } CGEN_ATTR; @@ -94,13 +87,17 @@ typedef struct { nonbool: values of non-boolean attributes There is a maximum of 32 attributes total. */ #define CGEN_ATTR_TYPE(n) \ -const struct { unsigned int num_nonbools; \ +const struct { unsigned char num_nonbools; \ unsigned int bool; \ unsigned int nonbool[(n) ? (n) : 1]; } /* Given an attribute number, return its mask. */ #define CGEN_ATTR_MASK(attr) (1 << (attr)) +/* Return the value of boolean attribute ATTR in ATTRS. */ +#define CGEN_BOOL_ATTR(attrs, attr) \ +((CGEN_ATTR_MASK (attr) & (attrs)) != 0) + /* Return value of attribute ATTR in ATTR_TABLE for OBJ. OBJ is a pointer to the entity that has the attributes. It's not used at present but is reserved for future purposes. */ @@ -108,6 +105,24 @@ const struct { unsigned int num_nonbools; \ ((unsigned int) (attr) < (attr_table)->num_nonbools \ ? ((attr_table)->nonbool[attr]) \ : (((attr_table)->bool & (1 << (attr))) != 0)) + +/* Attribute name/value tables. + These are used to assist parsing of descriptions at runtime. */ + +typedef struct +{ + const char * name; + int value; +} CGEN_ATTR_ENTRY; + +/* For each domain (fld,operand,insn), list of attributes. */ + +typedef struct +{ + const char * name; + /* NULL for boolean attributes. */ + const CGEN_ATTR_ENTRY * vals; +} CGEN_ATTR_TABLE; /* Parse result (also extraction result). @@ -125,7 +140,7 @@ const struct { unsigned int num_nonbools; \ where it varies. */ -struct cgen_fields; +typedef struct cgen_fields CGEN_FIELDS; /* Total length of the insn, as recorded in the `fields' struct. */ /* ??? The field insert handler has lots of opportunities for optimization @@ -151,7 +166,7 @@ typedef struct cgen_insn CGEN_INSN; The result is NULL if success or an error message. */ typedef const char * (cgen_parse_fn) PARAMS ((const struct cgen_insn *, const char **, - struct cgen_fields *)); + CGEN_FIELDS *)); /* Print handler. The first argument is a pointer to the disassembly info. @@ -165,7 +180,7 @@ typedef const char * (cgen_parse_fn) PARAMS ((const struct cgen_insn *, /* Don't require bfd.h unnecessarily. */ #ifdef BFD_VERSION typedef void (cgen_print_fn) PARAMS ((PTR, const struct cgen_insn *, - struct cgen_fields *, bfd_vma, int)); + CGEN_FIELDS *, bfd_vma, int)); #else typedef void (cgen_print_fn) (); #endif @@ -175,9 +190,10 @@ typedef void (cgen_print_fn) (); parsed. The second argument is a pointer to a cgen_fields struct from which the values are fetched. - The third argument is a pointer to a buffer in which to place the insn. */ -typedef void (cgen_insert_fn) PARAMS ((const struct cgen_insn *, - struct cgen_fields *, cgen_insn_t *)); + The third argument is a pointer to a buffer in which to place the insn. + The result is an error message or NULL if success. */ +typedef const char * (cgen_insert_fn) PARAMS ((const struct cgen_insn *, + CGEN_FIELDS *, cgen_insn_t *)); /* Extract handler. The first argument is a pointer to a struct describing the insn being @@ -190,7 +206,7 @@ typedef void (cgen_insert_fn) PARAMS ((const struct cgen_insn *, The result is the length of the insn or zero if not recognized. */ typedef int (cgen_extract_fn) PARAMS ((const struct cgen_insn *, void *, cgen_insn_t, - struct cgen_fields *)); + CGEN_FIELDS *)); /* The `parse' and `insert' fields are indices into these tables. The elements are pointer to specialized handler functions. @@ -207,127 +223,155 @@ extern cgen_print_fn * CGEN_SYM (print_handlers) []; #define CGEN_PRINT_FN(x) (CGEN_SYM (print_handlers)[(x)->base.print]) /* Base class of parser/printer. - (Don't read too much into the use of the phrase "base class"). + (Don't read too much into the use of the phrase "base class". + It's a name I'm using to organize my thoughts.) Instructions and expressions all share this data in common. - It's a collection of the common elements needed to parse and print - each of them. */ + It's a collection of the common elements needed to parse, insert, extract, + and print each of them. */ -#ifndef CGEN_MAX_INSN_ATTRS -#define CGEN_MAX_INSN_ATTRS 1 -#endif - -struct cgen_base { +struct cgen_base +{ /* Indices into the handler tables. We could use pointers here instead, but in the case of the insn table, 90% of them would be identical and that's a lot of redundant data. 0 means use the default (what the default is is up to the code). */ unsigned char parse, insert, extract, print; - - /* Attributes. */ - CGEN_ATTR_TYPE (CGEN_MAX_INSN_ATTRS) attrs; }; -/* Syntax table. +/* Assembler interface. - Each insn and subexpression has one of these. + The interface to the assembler is intended to be clean in the sense that + libopcodes.a is a standalone entity and could be used with any assembler. + Not that one would necessarily want to do that but rather that it helps + keep a clean interface. The interface will obviously be slanted towards + GAS, but at least it's a start. - The syntax "string" consists of characters (n > 0 && n < 128), and operand - values (n >= 128), and is terminated by 0. Operand values are 128 + index - into the operand table. The operand table doesn't exist in C, per se, as - the data is recorded in the parse/insert/extract/print switch statements. + Parsing is controlled by the assembler which calls + CGEN_SYM (assemble_insn). If it can parse and build the entire insn + it doesn't call back to the assembler. If it needs/wants to call back + to the assembler, (*cgen_parse_operand_fn) is called which can either - ??? Whether we want to use yacc instead is unclear, but we do make an - effort to not make doing that difficult. At least that's the intent. -*/ + - return a number to be inserted in the insn + - return a "register" value to be inserted + (the register might not be a register per pe) + - queue the argument and return a marker saying the expression has been + queued (eg: a fix-up) + - return an error message indicating the expression wasn't recognizable -struct cgen_syntax { - /* Original syntax string, for debugging purposes. */ - char *orig; + The result is an error message or NULL for success. + The parsed value is stored in the bfd_vma *. */ - /* Name of entry (that distinguishes it from all other entries). - This is used, for example, in simulator profiling results. */ - char *name; +/* Values for indicating what the caller wants. */ +enum cgen_parse_operand_type +{ + CGEN_PARSE_OPERAND_INIT, + CGEN_PARSE_OPERAND_INTEGER, + CGEN_PARSE_OPERAND_ADDRESS +}; + +/* Values for indicating what was parsed. + ??? Not too useful at present but in time. */ +enum cgen_parse_operand_result +{ + CGEN_PARSE_OPERAND_RESULT_NUMBER, + CGEN_PARSE_OPERAND_RESULT_REGISTER, + CGEN_PARSE_OPERAND_RESULT_QUEUED, + CGEN_PARSE_OPERAND_RESULT_ERROR +}; -#if 0 /* not needed yet */ - /* Format of this insn. - This doesn't closely follow the notion of instruction formats for more - complex instruction sets. This is the value computed at runtime. */ - enum cgen_fmt_type fmt; +/* Don't require bfd.h unnecessarily. */ +#ifdef BFD_VERSION +extern const char * (*cgen_parse_operand_fn) + PARAMS ((enum cgen_parse_operand_type, const char **, int, int, + enum cgen_parse_operand_result *, bfd_vma *)); #endif - /* Mnemonic (or name if expression). */ - char *mnemonic; +/* Called before trying to match a table entry with the insn. */ +void cgen_init_parse_operand PARAMS ((void)); - /* Syntax string. */ - /* FIXME: If each insn's mnemonic is constant, do we want to record just - the arguments here? */ -#ifndef CGEN_MAX_SYNTAX_BYTES -#define CGEN_MAX_SYNTAX_BYTES 16 -#endif - unsigned char syntax[CGEN_MAX_SYNTAX_BYTES]; +/* Called from <cpu>-asm.c to initialize operand parsing. */ -#define CGEN_SYNTAX_CHAR_P(c) ((c) < 128) -#define CGEN_SYNTAX_CHAR(c) (c) -#define CGEN_SYNTAX_FIELD(c) ((c) - 128) +/* These are GAS specific. They're not here as part of the interface, + but rather that we need to put them somewhere. */ - /* recognize insn if (op & mask) == value - For architectures with variable length insns, this is just a preliminary - test. */ - /* FIXME: Might want a selectable type (rather than always - unsigned long). */ - unsigned long mask, value; +/* Call this from md_assemble to initialize the assembler callback. */ +void cgen_asm_init_parse PARAMS ((void)); - /* length, in bits - This is the size that `mask' and `value' have been calculated to. - Normally it is CGEN_BASE_INSN_BITSIZE. On vliw architectures where - the base insn size may be larger than the size of an insn, this field is - less than CGEN_BASE_INSN_BITSIZE. - On architectures like the 386 and m68k the real size of the insn may - be computed while parsing. */ - /* FIXME: wip, of course */ - int length; -}; +/* Don't require bfd.h unnecessarily. */ +#ifdef BFD_VERSION +/* The result is an error message or NULL for success. + The parsed value is stored in the bfd_vma *. */ +const char * cgen_parse_operand PARAMS ((enum cgen_parse_operand_type, + const char **, int, int, + enum cgen_parse_operand_result *, + bfd_vma *)); +#endif + +void cgen_save_fixups PARAMS ((void)); +void cgen_restore_fixups PARAMS ((void)); +void cgen_swap_fixups PARAMS ((void)); + +/* Add a register to the assembler's hash table. + This makes lets GAS parse registers for us. + ??? This isn't currently used, but it could be in the future. */ +void cgen_asm_record_register PARAMS ((char *, int)); + +/* After CGEN_SYM (assemble_insn) is done, this is called to + output the insn and record any fixups. The address of the + assembled instruction is returned in case it is needed by + the caller. */ +char * cgen_asm_finish_insn PARAMS ((const struct cgen_insn *, cgen_insn_t *, + unsigned int)); /* Operand values (keywords, integers, symbols, etc.) */ /* Types of assembler elements. */ -enum cgen_asm_type { +enum cgen_asm_type +{ CGEN_ASM_KEYWORD, CGEN_ASM_MAX }; /* List of hardware elements. */ -typedef struct cgen_hw_entry { - struct cgen_hw_entry *next; - char *name; - enum cgen_asm_type asm_type; - PTR asm_data; +typedef struct cgen_hw_entry +{ + /* The type of this entry, one of `enum hw_type'. + This is an int and not the enum as the latter may not be declared yet. */ + int type; + const struct cgen_hw_entry * next; + char * name; + enum cgen_asm_type asm_type; + PTR asm_data; } CGEN_HW_ENTRY; -extern CGEN_HW_ENTRY *CGEN_SYM (hw_list); - -CGEN_HW_ENTRY *cgen_hw_lookup PARAMS ((const char *)); - -#ifndef CGEN_MAX_KEYWORD_ATTRS -#define CGEN_MAX_KEYWORD_ATTRS 1 -#endif +const CGEN_HW_ENTRY * cgen_hw_lookup PARAMS ((const char *)); /* This struct is used to describe things like register names, etc. */ -typedef struct cgen_keyword_entry { +typedef struct cgen_keyword_entry +{ /* Name (as in register name). */ - char *name; + char * name; /* Value (as in register number). The value cannot be -1 as that is used to indicate "not found". IDEA: Have "FUNCTION" attribute? [function is called to fetch value]. */ int value; - /* Attributes. */ + /* Attributes. + This should, but technically needn't, appear last. It is a variable sized + array in that one architecture may have 1 nonbool attribute and another + may have more. Having this last means the non-architecture specific code + needn't care. */ + /* ??? Moving this last should be done by treating keywords like insn lists + and moving the `next' fields into a CGEN_KEYWORD_LIST struct. */ /* FIXME: Not used yet. */ - CGEN_ATTR_TYPE (CGEN_MAX_KEYWORD_ATTRS) attrs; +#ifndef CGEN_KEYWORD_NBOOL_ATTRS +#define CGEN_KEYWORD_NBOOL_ATTRS 1 +#endif + CGEN_ATTR_TYPE (CGEN_KEYWORD_NBOOL_ATTRS) attrs; /* Next name hash table entry. */ struct cgen_keyword_entry *next_name; @@ -340,93 +384,138 @@ typedef struct cgen_keyword_entry { This struct supports runtime entry of new values, and hashed lookups. */ -typedef struct cgen_keyword { +typedef struct cgen_keyword +{ /* Pointer to initial [compiled in] values. */ - struct cgen_keyword_entry *init_entries; + CGEN_KEYWORD_ENTRY * init_entries; + /* Number of entries in `init_entries'. */ unsigned int num_init_entries; + /* Hash table used for name lookup. */ - struct cgen_keyword_entry **name_hash_table; + CGEN_KEYWORD_ENTRY ** name_hash_table; + /* Hash table used for value lookup. */ - struct cgen_keyword_entry **value_hash_table; + CGEN_KEYWORD_ENTRY ** value_hash_table; + /* Number of entries in the hash_tables. */ unsigned int hash_table_size; + + /* Pointer to null keyword "" entry if present. */ + const CGEN_KEYWORD_ENTRY * null_entry; } CGEN_KEYWORD; /* Structure used for searching. */ -typedef struct cgen_keyword_search { +typedef struct +{ /* Table being searched. */ - const struct cgen_keyword *table; + const CGEN_KEYWORD * table; + /* Specification of what is being searched for. */ - const char *spec; + const char * spec; + /* Current index in hash table. */ unsigned int current_hash; + /* Current element in current hash chain. */ - struct cgen_keyword_entry *current_entry; + CGEN_KEYWORD_ENTRY * current_entry; } CGEN_KEYWORD_SEARCH; /* Lookup a keyword from its name. */ -const struct cgen_keyword_entry * cgen_keyword_lookup_name - PARAMS ((struct cgen_keyword *, const char *)); +const CGEN_KEYWORD_ENTRY * cgen_keyword_lookup_name + PARAMS ((CGEN_KEYWORD *, const char *)); /* Lookup a keyword from its value. */ -const struct cgen_keyword_entry * cgen_keyword_lookup_value - PARAMS ((struct cgen_keyword *, int)); +const CGEN_KEYWORD_ENTRY * cgen_keyword_lookup_value + PARAMS ((CGEN_KEYWORD *, int)); /* Add a keyword. */ -void cgen_keyword_add PARAMS ((struct cgen_keyword *, - struct cgen_keyword_entry *)); +void cgen_keyword_add PARAMS ((CGEN_KEYWORD *, CGEN_KEYWORD_ENTRY *)); /* Keyword searching. This can be used to retrieve every keyword, or a subset. */ -struct cgen_keyword_search cgen_keyword_search_init - PARAMS ((struct cgen_keyword *, const char *)); -const struct cgen_keyword_entry *cgen_keyword_search_next - PARAMS ((struct cgen_keyword_search *)); +CGEN_KEYWORD_SEARCH cgen_keyword_search_init + PARAMS ((CGEN_KEYWORD *, const char *)); +const CGEN_KEYWORD_ENTRY *cgen_keyword_search_next + PARAMS ((CGEN_KEYWORD_SEARCH *)); /* Operand value support routines. */ /* FIXME: some of the long's here will need to be bfd_vma or some such. */ const char * cgen_parse_keyword PARAMS ((const char **, - struct cgen_keyword *, + CGEN_KEYWORD *, long *)); -const char * cgen_parse_signed_integer PARAMS ((const char **, int, - long, long, long *)); +const char * cgen_parse_signed_integer PARAMS ((const char **, int, long *)); const char * cgen_parse_unsigned_integer PARAMS ((const char **, int, - unsigned long, unsigned long, unsigned long *)); -const char * cgen_parse_address PARAMS ((const char **, int, - int, long *)); +const char * cgen_parse_address PARAMS ((const char **, int, int, + enum cgen_parse_operand_result *, + long *)); const char * cgen_validate_signed_integer PARAMS ((long, long, long)); const char * cgen_validate_unsigned_integer PARAMS ((unsigned long, unsigned long, unsigned long)); +/* Operand modes. */ + +/* ??? This duplicates the values in arch.h. Revisit. + These however need the CGEN_ prefix [as does everything in this file]. */ +/* ??? Targets may need to add their own modes so we may wish to move this + to <arch>-opc.h, or add a hook. */ + +enum cgen_mode { + CGEN_MODE_VOID, /* FIXME: rename simulator's VM to VOID */ + CGEN_MODE_BI, CGEN_MODE_QI, CGEN_MODE_HI, CGEN_MODE_SI, CGEN_MODE_DI, + CGEN_MODE_UBI, CGEN_MODE_UQI, CGEN_MODE_UHI, CGEN_MODE_USI, CGEN_MODE_UDI, + CGEN_MODE_SF, CGEN_MODE_DF, CGEN_MODE_XF, CGEN_MODE_TF, + CGEN_MODE_MAX +}; + +/* FIXME: Until simulator is updated. */ +#define CGEN_MODE_VM CGEN_MODE_VOID + /* This struct defines each entry in the operand table. */ -#ifndef CGEN_MAX_OPERAND_ATTRS -#define CGEN_MAX_OPERAND_ATTRS 1 -#endif +typedef struct cgen_operand +{ + /* Name as it appears in the syntax string. */ + char * name; -typedef struct cgen_operand { - /* For debugging. */ - char *name; + /* The hardware element associated with this operand. */ + const CGEN_HW_ENTRY *hw; + + /* FIXME: We don't yet record ifield definitions, which we should. + When we do it might make sense to delete start/length (since they will + be duplicated in the ifield's definition) and replace them with a + pointer to the ifield entry. Note that as more complicated situations + need to be handled, going more and more with an OOP paradigm will help + keep the complication under control. Of course, this was the goal from + the start, but getting there in one step was too much too soon. */ /* Bit position (msb of first byte = bit 0). + This is just a hint, and may be unused in more complex operands. May be unused for a modifier. */ unsigned char start; /* The number of bits in the operand. + This is just a hint, and may be unused in more complex operands. May be unused for a modifier. */ unsigned char length; - /* Attributes. */ - CGEN_ATTR_TYPE (CGEN_MAX_OPERAND_ATTRS) attrs; -#define CGEN_OPERAND_ATTRS(operand) (&(operand)->attrs) - -#if 0 /* ??? Interesting idea but relocs tend to get too complicated for - simple table lookups to work. */ +#if 0 /* ??? Interesting idea but relocs tend to get too complicated, + and ABI dependent, for simple table lookups to work. */ /* Ideally this would be the internal (external?) reloc type. */ int reloc_type; #endif + + /* Attributes. + This should, but technically needn't, appear last. It is a variable sized + array in that one architecture may have 1 nonbool attribute and another + may have more. Having this last means the non-architecture specific code + needn't care, now or tomorrow. */ +#ifndef CGEN_OPERAND_NBOOL_ATTRS +#define CGEN_OPERAND_NBOOL_ATTRS 1 +#endif + CGEN_ATTR_TYPE (CGEN_OPERAND_NBOOL_ATTRS) attrs; +#define CGEN_OPERAND_ATTRS(operand) (&(operand)->attrs) } CGEN_OPERAND; /* Return value of attribute ATTR in OPERAND. */ @@ -442,48 +531,207 @@ enum cgen_operand_type; /* FIXME: Rename, cpu-opc.h defines this as the typedef of the enum. */ #define CGEN_OPERAND_TYPE(operand) ((enum cgen_operand_type) CGEN_OPERAND_INDEX (operand)) #define CGEN_OPERAND_ENTRY(n) (& CGEN_SYM (operand_table) [n]) + +/* Types of parse/insert/extract/print cover-fn handlers. */ +/* FIXME: move opindex first to match caller. */ +/* FIXME: also need types of insert/extract/print fns. */ +/* FIXME: not currently used as type of 3rd arg varies. */ +typedef const char * (CGEN_PARSE_OPERAND_FN) PARAMS ((const char **, int, + long *)); + +/* Instruction operand instances. + + For each instruction, a list of the hardware elements that are read and + written are recorded. */ + +/* The type of the instance. */ +enum cgen_operand_instance_type { + /* End of table marker. */ + CGEN_OPERAND_INSTANCE_END = 0, + CGEN_OPERAND_INSTANCE_INPUT, CGEN_OPERAND_INSTANCE_OUTPUT +}; + +typedef struct +{ + /* The type of this operand. */ + enum cgen_operand_instance_type type; +#define CGEN_OPERAND_INSTANCE_TYPE(opinst) ((opinst)->type) + + /* The hardware element referenced. */ + const CGEN_HW_ENTRY *hw; +#define CGEN_OPERAND_INSTANCE_HW(opinst) ((opinst)->hw) + + /* The mode in which the operand is being used. */ + enum cgen_mode mode; +#define CGEN_OPERAND_INSTANCE_MODE(opinst) ((opinst)->mode) + + /* The operand table entry or NULL if there is none (i.e. an explicit + hardware reference). */ + const CGEN_OPERAND *operand; +#define CGEN_OPERAND_INSTANCE_OPERAND(opinst) ((opinst)->operand) + + /* If `operand' is NULL, the index (e.g. into array of registers). */ + int index; +#define CGEN_OPERAND_INSTANCE_INDEX(opinst) ((opinst)->index) +} CGEN_OPERAND_INSTANCE; + +/* Syntax string. + + Each insn format and subexpression has one of these. + + The syntax "string" consists of characters (n > 0 && n < 128), and operand + values (n >= 128), and is terminated by 0. Operand values are 128 + index + into the operand table. The operand table doesn't exist in C, per se, as + the data is recorded in the parse/insert/extract/print switch statements. */ + +#ifndef CGEN_MAX_SYNTAX_BYTES +#define CGEN_MAX_SYNTAX_BYTES 16 +#endif + +typedef struct +{ + unsigned char syntax[CGEN_MAX_SYNTAX_BYTES]; +} CGEN_SYNTAX; + +#define CGEN_SYNTAX_STRING(syn) (syn->syntax) +#define CGEN_SYNTAX_CHAR_P(c) ((c) < 128) +#define CGEN_SYNTAX_CHAR(c) (c) +#define CGEN_SYNTAX_FIELD(c) ((c) - 128) +#define CGEN_SYNTAX_MAKE_FIELD(c) ((c) + 128) + +/* ??? I can't currently think of any case where the mnemonic doesn't come + first [and if one ever doesn't building the hash tables will be tricky]. + However, we treat mnemonics as just another operand of the instruction. + A value of 1 means "this is where the mnemonic appears". 1 isn't + special other than it's a non-printable ASCII char. */ +#define CGEN_SYNTAX_MNEMONIC 1 +#define CGEN_SYNTAX_MNEMONIC_P(ch) ((ch) == CGEN_SYNTAX_MNEMONIC) + +/* Instruction formats. + + Instructions are grouped by format. Associated with an instruction is its + format. Each opcode table entry contains a format table entry. + ??? There is usually very few formats compared with the number of insns, + so one can reduce the size of the opcode table by recording the format table + as a separate entity. Given that we currently don't, format table entries + are also distinguished by their operands. This increases the size of the + table, but reduces the number of tables. It's all minutiae anyway so it + doesn't really matter [at this point in time]. + + ??? Support for variable length ISA's is wip. */ + +typedef struct +{ + /* Length that MASK and VALUE have been calculated to + [VALUE is recorded elsewhere]. + Normally it is CGEN_BASE_INSN_BITSIZE. On [V]LIW architectures where + the base insn size may be larger than the size of an insn, this field is + less than CGEN_BASE_INSN_BITSIZE. */ + unsigned char mask_length; + + /* Total length of instruction, in bits. */ + unsigned char length; + + /* Mask to apply to the first MASK_LENGTH bits. + Each insn's value is stored with the insn. + The first step in recognizing an insn for disassembly is + (opcode & mask) == value. */ + unsigned int mask; +} CGEN_FORMAT; /* This struct defines each entry in the instruction table. */ -struct cgen_insn { +struct cgen_insn +{ + /* ??? Further table size reductions can be had by moving this element + either to the format table or to a separate table of its own. Not + sure this is desirable yet. */ struct cgen_base base; + /* Given a pointer to a cgen_insn struct, return a pointer to `base'. */ #define CGEN_INSN_BASE(insn) (&(insn)->base) -#define CGEN_INSN_ATTRS(insn) (&(insn)->base.attrs) - struct cgen_syntax syntax; -#define CGEN_INSN_SYNTAX(insn) (&(insn)->syntax) -#define CGEN_INSN_FMT(insn) ((insn)->syntax.fmt) -#define CGEN_INSN_BITSIZE(insn) ((insn)->syntax.length) -}; + /* Name of entry (that distinguishes it from all other entries). + This is used, for example, in simulator profiling results. */ + /* ??? If mnemonics have operands, try to print full mnemonic. */ + const char * name; +#define CGEN_INSN_NAME(insn) ((insn)->name) + /* Mnemonic. This is used when parsing and printing the insn. + In the case of insns that have operands on the mnemonics, this is + only the constant part. E.g. for conditional execution of an `add' insn, + where the full mnemonic is addeq, addne, etc., this is only "add". */ + const char * mnemonic; +#define CGEN_INSN_MNEMONIC(insn) ((insn)->mnemonic) + + /* Syntax string. */ + const CGEN_SYNTAX syntax; +#define CGEN_INSN_SYNTAX(insn) (& (insn)->syntax) + + /* Format entry. */ + const CGEN_FORMAT format; +#define CGEN_INSN_MASK_BITSIZE(insn) ((insn)->format.mask_length) +#define CGEN_INSN_BITSIZE(insn) ((insn)->format.length) + + /* Instruction opcode value. */ + unsigned int value; +#define CGEN_INSN_VALUE(insn) ((insn)->value) +#define CGEN_INSN_MASK(insn) ((insn)->format.mask) + + /* Pointer to NULL entry terminated table of operands used, + or NULL if none. */ + const CGEN_OPERAND_INSTANCE *operands; +#define CGEN_INSN_OPERANDS(insn) ((insn)->operands) + + /* Attributes. + This must appear last. It is a variable sized array in that one + architecture may have 1 nonbool attribute and another may have more. + Having this last means the non-architecture specific code needn't + care. */ +#ifndef CGEN_INSN_NBOOL_ATTRS +#define CGEN_INSN_NBOOL_ATTRS 1 +#endif + CGEN_ATTR_TYPE (CGEN_INSN_NBOOL_ATTRS) attrs; +#define CGEN_INSN_ATTRS(insn) (&(insn)->attrs) /* Return value of attribute ATTR in INSN. */ #define CGEN_INSN_ATTR(insn, attr) \ CGEN_ATTR_VALUE (insn, CGEN_INSN_ATTRS (insn), attr) +}; /* Instruction lists. This is used for adding new entries and for creating the hash lists. */ -typedef struct cgen_insn_list { - struct cgen_insn_list *next; - const struct cgen_insn *insn; +typedef struct cgen_insn_list +{ + struct cgen_insn_list * next; + const CGEN_INSN * insn; } CGEN_INSN_LIST; /* The table of instructions. */ -typedef struct cgen_insn_table { +typedef struct +{ /* Pointer to initial [compiled in] entries. */ - const struct cgen_insn *init_entries; + const CGEN_INSN * init_entries; + + /* Size of an entry (since the attribute member is variable sized). */ + unsigned int entry_size; + /* Number of entries in `init_entries', including trailing NULL entry. */ unsigned int num_init_entries; + /* Values added at runtime. */ - struct cgen_insn_list *new_entries; + CGEN_INSN_LIST * new_entries; + /* Assembler hash function. */ - unsigned int (*asm_hash) PARAMS ((const char *)); + unsigned int (* asm_hash) PARAMS ((const char *)); + /* Number of entries in assembler hash table. */ unsigned int asm_hash_table_size; + /* Disassembler hash function. */ - unsigned int (*dis_hash) PARAMS ((const char *, unsigned long)); + unsigned int (* dis_hash) PARAMS ((const char *, unsigned long)); + /* Number of entries in disassembler hash table. */ unsigned int dis_hash_table_size; } CGEN_INSN_TABLE; @@ -498,7 +746,7 @@ extern const CGEN_INSN CGEN_SYM (insn_table_entries)[]; /* Return number of instructions. This includes any added at runtime. */ -int cgen_insn_count PARAMS (()); +int cgen_insn_count PARAMS ((void)); /* The assembler insn table is hashed based on some function of the mnemonic (the actually hashing done is up to the target, but we provide a few @@ -541,10 +789,11 @@ CGEN_INSN_LIST * cgen_dis_lookup_insn PARAMS ((const char *, unsigned long)); /* Top level structures and functions. */ -typedef struct cgen_opcode_data { - CGEN_HW_ENTRY *hw_list; - /*CGEN_OPERAND_TABLE *operand_table; - FIXME:wip */ - CGEN_INSN_TABLE *insn_table; +typedef struct +{ + const CGEN_HW_ENTRY * hw_list; + /*CGEN_OPERAND_TABLE * operand_table; - FIXME:wip */ + CGEN_INSN_TABLE * insn_table; } CGEN_OPCODE_DATA; /* Each CPU has one of these. */ @@ -562,7 +811,7 @@ extern enum cgen_endian cgen_current_endian; /* Prototypes of major functions. */ -/* Set the current cpu (+ mach number, endian, etc.). *? +/* Set the current cpu (+ mach number, endian, etc.). */ void cgen_set_cpu PARAMS ((CGEN_OPCODE_DATA *, int, enum cgen_endian)); /* Initialize the assembler, disassembler. */ @@ -577,28 +826,40 @@ void CGEN_SYM (init_parse) PARAMS ((void)); void CGEN_SYM (init_print) PARAMS ((void)); void CGEN_SYM (init_insert) PARAMS ((void)); void CGEN_SYM (init_extract) PARAMS ((void)); + +/* FIXME: This prototype is wrong ifndef CGEN_INT_INSN. + Furthermore, ifdef CGEN_INT_INSN, the insn is created in + target byte order (in which case why use int's at all). + Perhaps replace cgen_insn_t * with char *? */ const struct cgen_insn * -CGEN_SYM (assemble_insn) PARAMS ((const char *, struct cgen_fields *, +CGEN_SYM (assemble_insn) PARAMS ((const char *, CGEN_FIELDS *, cgen_insn_t *, char **)); -int CGEN_SYM (insn_supported) PARAMS ((const struct cgen_syntax *)); #if 0 /* old */ +int CGEN_SYM (insn_supported) PARAMS ((const struct cgen_insn *)); int CGEN_SYM (opval_supported) PARAMS ((const struct cgen_opval *)); #endif -extern const struct cgen_keyword CGEN_SYM (operand_mach); +extern const CGEN_KEYWORD CGEN_SYM (operand_mach); int CGEN_SYM (get_mach) PARAMS ((const char *)); +const CGEN_INSN * +CGEN_SYM (get_insn_operands) PARAMS ((const CGEN_INSN *, cgen_insn_t, + int, int *)); +const CGEN_INSN * +CGEN_SYM (lookup_insn) PARAMS ((const CGEN_INSN *, cgen_insn_t, + int, CGEN_FIELDS *, int)); + CGEN_INLINE void CGEN_SYM (put_operand) PARAMS ((int, const long *, - struct cgen_fields *)); + CGEN_FIELDS *)); CGEN_INLINE long -CGEN_SYM (get_operand) PARAMS ((int, const struct cgen_fields *)); +CGEN_SYM (get_operand) PARAMS ((int, const CGEN_FIELDS *)); -CGEN_INLINE const char * -CGEN_SYM (parse_operand) PARAMS ((int, const char **, struct cgen_fields *)); +const char * +CGEN_SYM (parse_operand) PARAMS ((int, const char **, CGEN_FIELDS *)); -CGEN_INLINE const char * -CGEN_SYM (validate_operand) PARAMS ((int, const struct cgen_fields *)); +const char * +CGEN_SYM (insert_operand) PARAMS ((int, CGEN_FIELDS *, char *)); /* Default insn parser, printer. */ extern cgen_parse_fn CGEN_SYM (parse_insn); @@ -608,79 +869,5 @@ extern cgen_print_fn CGEN_SYM (print_insn); /* Read in a cpu description file. */ const char * cgen_read_cpu_file PARAMS ((const char *)); - -/* Assembler interface. - - The interface to the assembler is intended to be clean in the sense that - libopcodes.a is a standalone entity and could be used with any assembler. - Not that one would necessarily want to do that but rather that it helps - keep a clean interface. The interface will obviously be slanted towards - GAS, but at least it's a start. - - Parsing is controlled by the assembler which calls - CGEN_SYM (assemble_insn). If it can parse and build the entire insn - it doesn't call back to the assembler. If it needs/wants to call back - to the assembler, (*cgen_parse_operand_fn) is called which can either - - - return a number to be inserted in the insn - - return a "register" value to be inserted - (the register might not be a register per pe) - - queue the argument and return a marker saying the expression has been - queued (eg: a fix-up) - - return an error message indicating the expression wasn't recognizable - - The result is an error message or NULL for success. - The parsed value is stored in the bfd_vma *. */ - -/* Values for indicating what the caller wants. */ -enum cgen_parse_operand_type { - CGEN_PARSE_OPERAND_INIT, CGEN_PARSE_OPERAND_INTEGER, - CGEN_PARSE_OPERAND_ADDRESS -}; - -/* Values for indicating what was parsed. - ??? Not too useful at present but in time. */ -enum cgen_parse_operand_result { - CGEN_PARSE_OPERAND_RESULT_NUMBER, CGEN_PARSE_OPERAND_RESULT_REGISTER, - CGEN_PARSE_OPERAND_RESULT_QUEUED, CGEN_PARSE_OPERAND_RESULT_ERROR -}; - -/* Don't require bfd.h unnecessarily. */ -#ifdef BFD_VERSION -extern const char * (*cgen_parse_operand_fn) - PARAMS ((enum cgen_parse_operand_type, const char **, int, int, - enum cgen_parse_operand_result *, bfd_vma *)); -#endif - -/* Called before trying to match a table entry with the insn. */ -void cgen_init_parse_operand PARAMS ((void)); - -/* Called from <cpu>-asm.c to initialize operand parsing. */ - -/* These are GAS specific. They're not here as part of the interface, - but rather that we need to put them somewhere. */ - -/* Call this from md_assemble to initialize the assembler callback. */ -void cgen_asm_init_parse PARAMS ((void)); - -/* Don't require bfd.h unnecessarily. */ -#ifdef BFD_VERSION -/* The result is an error message or NULL for success. - The parsed value is stored in the bfd_vma *. */ -const char *cgen_parse_operand PARAMS ((enum cgen_parse_operand_type, - const char **, int, int, - enum cgen_parse_operand_result *, - bfd_vma *)); -#endif - -/* Add a register to the assembler's hash table. - This makes lets GAS parse registers for us. - ??? This isn't currently used, but it could be in the future. */ -void cgen_asm_record_register PARAMS ((char *, int)); - -/* After CGEN_SYM (assemble_insn) is done, this is called to - output the insn and record any fixups. */ -void cgen_asm_finish_insn PARAMS ((const struct cgen_insn *, cgen_insn_t *, - unsigned int)); #endif /* CGEN_H */ diff --git a/gnu/dist/include/opcode/d10v.h b/gnu/dist/include/opcode/d10v.h index 33d1af40c84..4b74c9862d4 100644 --- a/gnu/dist/include/opcode/d10v.h +++ b/gnu/dist/include/opcode/d10v.h @@ -1,5 +1,5 @@ /* d10v.h -- Header file for D10V opcode table - Copyright 1996 Free Software Foundation, Inc. + Copyright 1996, 1997, 1998 Free Software Foundation, Inc. Written by Martin Hunt (hunt@cygnus.com), Cygnus Support This file is part of GDB, GAS, and the GNU binutils. @@ -148,24 +148,33 @@ extern const struct d10v_operand d10v_operands[]; /* @( */ #define OPERAND_ATPAR (0x200) -/* accumulator */ -#define OPERAND_ACC (0x400) +/* accumulator 0 */ +#define OPERAND_ACC0 (0x400) -/* flag register */ -#define OPERAND_FLAG (0x800) +/* accumulator 1 */ +#define OPERAND_ACC1 (0x800) + +/* f0 / f1 flag register */ +#define OPERAND_FFLAG (0x1000) + +/* c flag register */ +#define OPERAND_CFLAG (0x2000) /* control register */ -#define OPERAND_CONTROL (0x1000) +#define OPERAND_CONTROL (0x4000) /* predecrement mode '@-sp' */ -#define OPERAND_ATMINUS (0x2000) +#define OPERAND_ATMINUS (0x8000) /* signed number */ -#define OPERAND_SIGNED (0x4000) +#define OPERAND_SIGNED (0x10000) /* special accumulator shifts need a 4-bit number */ /* 1 <= x <= 16 */ -#define OPERAND_SHIFT (0x8000) +#define OPERAND_SHIFT (0x20000) + +/* general purpose register */ +#define OPERAND_GPR (0x40000) /* Structure to hold information about predefined registers. */ struct pd_reg diff --git a/gnu/dist/include/opcode/h8300.h b/gnu/dist/include/opcode/h8300.h index c9cf9e250cd..3a05e4ee21c 100644 --- a/gnu/dist/include/opcode/h8300.h +++ b/gnu/dist/include/opcode/h8300.h @@ -1,5 +1,5 @@ /* Opcode table for the H8-300 - Copyright (C) 1991,1992 Free Software Foundation. + Copyright (C) 1991, 92, 93, 95, 96, 97, 1998 Free Software Foundation. Written by Steve Chamberlain, sac@cygnus.com. This file is part of GDB, the GNU Debugger and GAS, the GNU Assembler. @@ -16,7 +16,8 @@ You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software - Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ /* Instructions are stored as a sequence of nibbles. If the nibble has value 15 or less then the representation is complete. @@ -158,11 +159,11 @@ struct h8_opcode #ifdef DEFINE_TABLE #define BITOP(code, imm, name, op00, op01,op10,op11, op20,op21,op30)\ -{ code, 1, 2, name, {imm,RD8,E}, {op00, op01, imm, RD8, E, 0, 0, 0, 0}, 0, 0, 0, 0},\ -{ code, 1, 6, name, {imm,RDIND,E}, {op10, op11, B30|RDIND, 0, op00,op01, imm, 0, E}, 0, 0, 0, 0},\ -{ code, 1, 6, name, {imm,ABS8DST,E},{op20, op21, ABS8DST, IGNORE, op00,op01, imm, 0,E}, 0, 0, 0, 0}\ -,{ code, 1, 6, name, {imm,ABS16DST,E},{0x6,0xa,0x1,op30,ABS16DST,IGNORE,IGNORE,IGNORE, op00,op01, imm, 0,E}, 0, 0, 0, 0},\ -{ code, 1, 6, name, {imm,ABS32DST,E},{0x6,0xa,0x3,op30,ABS32DST,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE, op00,op01, imm, 0,E}, 0, 0, 0, 0} +{ code, 1, 2, name, {{imm,RD8,E}}, {{op00, op01, imm, RD8, E, 0, 0, 0, 0}}, 0, 0, 0, 0},\ +{ code, 1, 6, name, {{imm,RDIND,E}},{{op10, op11, B30|RDIND, 0, op00,op01, imm, 0, E}}, 0, 0, 0, 0},\ +{ code, 1, 6, name, {{imm,ABS8DST,E}},{{op20, op21, ABS8DST, IGNORE, op00,op01, imm, 0,E}}, 0, 0, 0, 0}\ +,{ code, 0, 6, name, {{imm,ABS16DST,E}},{{0x6,0xa,0x1,op30,ABS16DST,IGNORE,IGNORE,IGNORE, op00,op01, imm, 0,E}}, 0, 0, 0, 0},\ +{ code, 0, 6, name, {{imm,ABS32DST,E}},{{0x6,0xa,0x3,op30,ABS32DST,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE, op00,op01, imm, 0,E}}, 0, 0, 0, 0} #define EBITOP(code, imm, name, op00, op01,op10,op11, op20,op21,op30)\ @@ -170,11 +171,11 @@ struct h8_opcode BITOP(code,RS8, name, op00, op01, op10,op11, op20,op21,op30) #define WTWOP(code,name, op1, op2) \ -{ code, 1, 2, name, {RS16, RD16, E}, { op1, op2, RS16, RD16, E, 0, 0, 0, 0}, 0, 0, 0, 0} +{ code, 1, 2, name, {{RS16, RD16, E}}, {{ op1, op2, RS16, RD16, E, 0, 0, 0, 0}}, 0, 0, 0, 0} #define BRANCH(code, name, op) \ -{ code, 1, 4,name,{DISP8,E,0}, { 0x4, op, DISP8, IGNORE, E, 0, 0, 0, 0}, 0, 0, 0, 0}, \ -{ code, 0, 6,name,{DISP16,E,0}, { 0x5, 0x8, op, 0x0, DISP16, IGNORE, IGNORE, IGNORE, E,0}, 0, 0, 0, 0} +{ code, 1, 4,name,{{DISP8,E,0}}, {{ 0x4, op, DISP8, IGNORE, E, 0, 0, 0, 0}}, 0, 0, 0, 0}, \ +{ code, 0, 6,name,{{DISP16,E,0}}, {{ 0x5, 0x8, op, 0x0, DISP16, IGNORE, IGNORE, IGNORE, E,0}}, 0, 0, 0, 0} #define SOP(code, x,name) \ {code, 1, x, name @@ -184,19 +185,19 @@ struct h8_opcode #define EOP ,0,0,0 } #define TWOOP(code, name, op1, op2,op3) \ -{ code,1, 2,name, {IMM8, RD8, E}, { op1, RD8, IMM8, IGNORE, E, 0, 0, 0, 0}, 0, 0, 0, 0},\ -{ code, 1, 2,name, {RS8, RD8, E}, { op2, op3, RS8, RD8, E, 0, 0, 0, 0}, 0, 0, 0, 0} +{ code,1, 2,name, {{IMM8, RD8, E}}, {{ op1, RD8, IMM8, IGNORE, E, 0, 0, 0, 0}}, 0, 0, 0, 0},\ +{ code, 1, 2,name, {{RS8, RD8, E}}, {{ op2, op3, RS8, RD8, E, 0, 0, 0, 0}}, 0, 0, 0, 0} #define UNOP(code,name, op1, op2) \ -{ code, 1, 2, name, {OR8, E, 0}, { op1, op2, 0, OR8, E, 0, 0, 0, 0}, 0, 0, 0, 0} +{ code, 1, 2, name, {{OR8, E, 0}}, {{ op1, op2, 0, OR8, E, 0, 0, 0, 0}}, 0, 0, 0, 0} #define UNOP3(code, name, op1, op2, op3) \ -{ O(code,SB), 1, 2, name, {OR8, E, 0}, {op1, op2, op3+0, OR8, E, 0, 0, 0, 0}, 0, 0, 0, 0}, \ -{ O(code,SW), 0, 2, name, {OR16, E, 0}, {op1, op2, op3+1, OR16, E, 0, 0, 0, 0}, 0, 0, 0, 0}, \ -{ O(code,SL), 0, 2, name, {OR32, E, 0}, {op1, op2, op3+3, OR32|B30, E, 0, 0, 0, 0}, 0, 0, 0, 0} \ -,{ O(code,SB), 1, 2, name, {IMM, OR8 | SRC_IN_DST, E}, {op1, op2, op3+4, OR8 | SRC_IN_DST, E, 0, 0, 0, 0}, 0, 0, 0, 0}, \ -{ O(code,SW), 0, 2, name, {IMM, OR16 | SRC_IN_DST, E}, {op1, op2, op3+5, OR16 | SRC_IN_DST, E, 0, 0, 0, 0}, 0, 0, 0, 0}, \ -{ O(code,SL), 0, 2, name, {IMM, OR32 | SRC_IN_DST, E}, {op1, op2, op3+7, OR32 | SRC_IN_DST|B30 , E, 0, 0, 0, 0}, 0, 0, 0, 0} +{ O(code,SB), 1, 2, name, {{OR8, E, 0}}, {{op1, op2, op3+0, OR8, E, 0, 0, 0, 0}}, 0, 0, 0, 0}, \ +{ O(code,SW), 0, 2, name, {{OR16, E, 0}}, {{op1, op2, op3+1, OR16, E, 0, 0, 0, 0}}, 0, 0, 0, 0}, \ +{ O(code,SL), 0, 2, name, {{OR32, E, 0}}, {{op1, op2, op3+3, OR32|B30, E, 0, 0, 0, 0}}, 0, 0, 0, 0} \ +,{ O(code,SB), 1, 2, name, {{IMM, OR8 | SRC_IN_DST, E}}, {{op1, op2, op3+4, OR8 | SRC_IN_DST, E, 0, 0, 0, 0}}, 0, 0, 0, 0}, \ +{ O(code,SW), 0, 2, name, {{IMM, OR16 | SRC_IN_DST, E}}, {{op1, op2, op3+5, OR16 | SRC_IN_DST, E, 0, 0, 0, 0}}, 0, 0, 0, 0}, \ +{ O(code,SL), 0, 2, name, {{IMM, OR32 | SRC_IN_DST, E}}, {{op1, op2, op3+7, OR32 | SRC_IN_DST|B30 , E, 0, 0, 0, 0}}, 0, 0, 0, 0} #define IMM32LIST IMM32,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE @@ -316,23 +317,23 @@ struct h8_opcode h8_opcodes[] = { TWOOP(O(O_ADD,SB),"add.b", 0x8, 0x0,0x8), - NEW_SOP(O(O_ADD,SW),1,2,"add.w"),{RS16,RD16,E },{0x0,0x9,RS16,RD16,E} EOP, - NEW_SOP(O(O_ADD,SW),0,4,"add.w"),{IMM16,RD16,E },{0x7,0x9,0x1,RD16,IMM16,IGNORE,IGNORE,IGNORE,E} EOP, - NEW_SOP(O(O_ADD,SL),0,2,"add.l"),{RS32,RD32,E }, {0x0,0xA,B31|RS32,B30|RD32,E} EOP, - NEW_SOP(O(O_ADD,SL),0,6,"add.l"),{IMM32,RD32,E },{0x7,0xA,0x1,B30|RD32,IMM32LIST,E} EOP, - NEW_SOP(O(O_ADDS,SL),1,2,"adds"), {KBIT,RDP,E}, {0x0,0xB,KBIT,RDP,E,0,0,0,0} EOP, + NEW_SOP(O(O_ADD,SW),1,2,"add.w"),{{RS16,RD16,E}},{{0x0,0x9,RS16,RD16,E}} EOP, + NEW_SOP(O(O_ADD,SW),0,4,"add.w"),{{IMM16,RD16,E}},{{0x7,0x9,0x1,RD16,IMM16,IGNORE,IGNORE,IGNORE,E}} EOP, + NEW_SOP(O(O_ADD,SL),0,2,"add.l"),{{RS32,RD32,E }}, {{0x0,0xA,B31|RS32,B30|RD32,E}} EOP, + NEW_SOP(O(O_ADD,SL),0,6,"add.l"),{{IMM32,RD32,E }},{{0x7,0xA,0x1,B30|RD32,IMM32LIST,E}} EOP, + NEW_SOP(O(O_ADDS,SL),1,2,"adds"), {{KBIT,RDP,E}}, {{0x0,0xB,KBIT,RDP,E,0,0,0,0}} EOP, TWOOP(O(O_ADDX,SB),"addx",0x9,0x0,0xE), TWOOP(O(O_AND,SB), "and.b",0xE,0x1,0x6), - NEW_SOP(O(O_AND,SW),0,2,"and.w"),{RS16,RD16,E },{0x6,0x6,RS16,RD16,E} EOP, - NEW_SOP(O(O_AND,SW),0,4,"and.w"),{IMM16,RD16,E },{0x7,0x9,0x6,RD16,IMM16,IGNORE,IGNORE,IGNORE,E} EOP, + NEW_SOP(O(O_AND,SW),0,2,"and.w"),{{RS16,RD16,E }},{{0x6,0x6,RS16,RD16,E}} EOP, + NEW_SOP(O(O_AND,SW),0,4,"and.w"),{{IMM16,RD16,E }},{{0x7,0x9,0x6,RD16,IMM16,IGNORE,IGNORE,IGNORE,E}} EOP, - NEW_SOP(O(O_AND,SL),0,6,"and.l"),{IMM32,RD32,E },{0x7,0xA,0x6,B30|RD32,IMM32LIST,E} EOP, - NEW_SOP(O(O_AND,SL),0,2,"and.l") ,{RS32,RD32,E },{0x0,0x1,0xF,0x0,0x6,0x6,B30|RS32,B30|RD32,E} EOP, + NEW_SOP(O(O_AND,SL),0,6,"and.l"),{{IMM32,RD32,E }},{{0x7,0xA,0x6,B30|RD32,IMM32LIST,E}} EOP, + NEW_SOP(O(O_AND,SL),0,2,"and.l") ,{{RS32,RD32,E }},{{0x0,0x1,0xF,0x0,0x6,0x6,B30|RS32,B30|RD32,E}} EOP, - NEW_SOP(O(O_ANDC,SB),1,2,"andc"), {IMM8,CCR,E},{ 0x0,0x6,IMM8,IGNORE,E,0,0,0,0} EOP, - NEW_SOP(O(O_ANDC,SB),1,2,"andc"), {IMM8,EXR,E},{ 0x0,0x1,0x4,0x1,0x0,0x6,IMM8,IGNORE,E,0,0,0,0} EOP, + NEW_SOP(O(O_ANDC,SB),1,2,"andc"), {{IMM8,CCR,E}},{{ 0x0,0x6,IMM8,IGNORE,E,0,0,0,0}} EOP, + NEW_SOP(O(O_ANDC,SB),1,2,"andc"), {{IMM8,EXR,E}},{{ 0x0,0x1,0x4,0x1,0x0,0x6,IMM8,IGNORE,E,0,0,0,0}} EOP, BITOP(O(O_BAND,SB), IMM3|B30,"band",0x7,0x6,0x7,0xC,0x7,0xE,0x0), BRANCH(O(O_BRA,SB),"bra",0x0), @@ -367,8 +368,8 @@ struct h8_opcode h8_opcodes[] = BITOP(O(O_BOR,SB), IMM3|B30,"bor", 0x7,0x4,0x7,0xC,0x7,0xE,0x0), EBITOP(O(O_BSET,SB),IMM3|B30,"bset", 0x6,0x0,0x7,0xD,0x7,0xF,0x8), - SOP(O(O_BSR,SB),6,"bsr"),{DISP8,E,0},{ 0x5,0x5,DISP8,IGNORE,E,0,0,0,0} EOP, - SOP(O(O_BSR,SB),6,"bsr"),{DISP16,E,0},{ 0x5,0xC,0x0,0x0,DISP16,IGNORE,IGNORE,IGNORE,E,0,0,0,0} EOP, + SOP(O(O_BSR,SB),6,"bsr"),{{DISP8,E,0}},{{ 0x5,0x5,DISP8,IGNORE,E,0,0,0,0}} EOP, + SOP(O(O_BSR,SB),6,"bsr"),{{DISP16,E,0}},{{ 0x5,0xC,0x0,0x0,DISP16,IGNORE,IGNORE,IGNORE,E,0,0,0,0}} EOP, BITOP(O(O_BST,SB), IMM3|B30,"bst",0x6,0x7,0x7,0xD,0x7,0xF,0x8), EBITOP(O(O_BTST,SB), IMM3|B30,"btst",0x6,0x3,0x7,0xC,0x7,0xE,0x0), BITOP(O(O_BXOR,SB), IMM3|B30,"bxor",0x7,0x5,0x7,0xC,0x7,0xE,0x0), @@ -376,223 +377,223 @@ struct h8_opcode h8_opcodes[] = TWOOP(O(O_CMP,SB), "cmp.b",0xA,0x1,0xC), WTWOP(O(O_CMP,SW), "cmp.w",0x1,0xD), - NEW_SOP(O(O_CMP,SW),1,2,"cmp.w"),{RS16,RD16,E },{0x1,0xD,RS16,RD16,E} EOP, - NEW_SOP(O(O_CMP,SW),0,4,"cmp.w"),{IMM16,RD16,E },{0x7,0x9,0x2,RD16,IMM16,IGNORE,IGNORE,IGNORE,E} EOP, + NEW_SOP(O(O_CMP,SW),1,2,"cmp.w"),{{RS16,RD16,E }},{{0x1,0xD,RS16,RD16,E}} EOP, + NEW_SOP(O(O_CMP,SW),0,4,"cmp.w"),{{IMM16,RD16,E }},{{0x7,0x9,0x2,RD16,IMM16,IGNORE,IGNORE,IGNORE,E}} EOP, - NEW_SOP(O(O_CMP,SL),0,6,"cmp.l"),{IMM32,RD32,E },{0x7,0xA,0x2,B30|RD32,IMM32LIST,E} EOP, - NEW_SOP(O(O_CMP,SL),0,2,"cmp.l") ,{RS32,RD32,E },{0x1,0xF,B31|RS32,B30|RD32,E} EOP, + NEW_SOP(O(O_CMP,SL),0,6,"cmp.l"),{{IMM32,RD32,E }},{{0x7,0xA,0x2,B30|RD32,IMM32LIST,E}} EOP, + NEW_SOP(O(O_CMP,SL),0,2,"cmp.l") ,{{RS32,RD32,E }},{{0x1,0xF,B31|RS32,B30|RD32,E}} EOP, UNOP(O(O_DAA,SB), "daa",0x0,0xF), UNOP(O(O_DAS,SB), "das",0x1,0xF), UNOP(O(O_DEC,SB), "dec.b",0x1,0xA), - NEW_SOP(O(O_DEC, SW),0,2,"dec.w") ,{DBIT,RD16,E },{0x1,0xB,0x5|DBIT,RD16,E} EOP, - NEW_SOP(O(O_DEC, SL),0,2,"dec.l") ,{DBIT,RD32,E },{0x1,0xB,0x7|DBIT,RD32|B30,E} EOP, + NEW_SOP(O(O_DEC, SW),0,2,"dec.w") ,{{DBIT,RD16,E }},{{0x1,0xB,0x5|DBIT,RD16,E}} EOP, + NEW_SOP(O(O_DEC, SL),0,2,"dec.l") ,{{DBIT,RD32,E }},{{0x1,0xB,0x7|DBIT,RD32|B30,E}} EOP, - NEW_SOP(O(O_DIVU,SB),1,6,"divxu.b"), {RS8,RD16,E}, {0x5,0x1,RS8,RD16,E,0,0,0,0}EOP, - NEW_SOP(O(O_DIVU,SW),0,20,"divxu.w"),{RS16,RD32,E},{0x5,0x3,RS16,B30|RD32,E}EOP, + NEW_SOP(O(O_DIVU,SB),1,6,"divxu.b"), {{RS8,RD16,E}}, {{0x5,0x1,RS8,RD16,E,0,0,0,0}}EOP, + NEW_SOP(O(O_DIVU,SW),0,20,"divxu.w"),{{RS16,RD32,E}},{{0x5,0x3,RS16,B30|RD32,E}}EOP, - NEW_SOP(O(O_DIVS,SB),0,20,"divxs.b") ,{RS8,RD16,E },{0x0,0x1,0xD,0x0,0x5,0x1,RS8,RD16,E} EOP, - NEW_SOP(O(O_DIVS,SW),0,02,"divxs.w") ,{RS16,RD32,E },{0x0,0x1,0xD,0x0,0x5,0x3,RS16,B30|RD32,E} EOP, + NEW_SOP(O(O_DIVS,SB),0,20,"divxs.b") ,{{RS8,RD16,E }},{{0x0,0x1,0xD,0x0,0x5,0x1,RS8,RD16,E}} EOP, + NEW_SOP(O(O_DIVS,SW),0,02,"divxs.w") ,{{RS16,RD32,E }},{{0x0,0x1,0xD,0x0,0x5,0x3,RS16,B30|RD32,E}} EOP, - NEW_SOP(O(O_EEPMOV,SB),1,50,"eepmov.b"),{E,0,0},{0x7,0xB,0x5,0xC,0x5,0x9,0x8,0xF,E}EOP, - NEW_SOP(O(O_EEPMOV,SW),0,50,"eepmov.w"),{E,0,0},{0x7,0xB,0xD,0x4,0x5,0x9,0x8,0xF,E} EOP, + NEW_SOP(O(O_EEPMOV,SB),1,50,"eepmov.b"),{{E,0,0}},{{0x7,0xB,0x5,0xC,0x5,0x9,0x8,0xF,E}}EOP, + NEW_SOP(O(O_EEPMOV,SW),0,50,"eepmov.w"),{{E,0,0}},{{0x7,0xB,0xD,0x4,0x5,0x9,0x8,0xF,E}} EOP, - NEW_SOP(O(O_EXTS,SW),0,2,"exts.w"),{OR16,E,0},{0x1,0x7,0xD,OR16,E }EOP, - NEW_SOP(O(O_EXTS,SL),0,2,"exts.l"),{OR32,E,0},{0x1,0x7,0xF,OR32|B30,E }EOP, + NEW_SOP(O(O_EXTS,SW),0,2,"exts.w"),{{OR16,E,0}},{{0x1,0x7,0xD,OR16,E }}EOP, + NEW_SOP(O(O_EXTS,SL),0,2,"exts.l"),{{OR32,E,0}},{{0x1,0x7,0xF,OR32|B30,E }}EOP, - NEW_SOP(O(O_EXTU,SW),0,2,"extu.w"),{OR16,E,0},{0x1,0x7,0x5,OR16,E }EOP, - NEW_SOP(O(O_EXTU,SL),0,2,"extu.l"),{OR32,E,0},{0x1,0x7,0x7,OR32|B30,E }EOP, + NEW_SOP(O(O_EXTU,SW),0,2,"extu.w"),{{OR16,E,0}},{{0x1,0x7,0x5,OR16,E }}EOP, + NEW_SOP(O(O_EXTU,SL),0,2,"extu.l"),{{OR32,E,0}},{{0x1,0x7,0x7,OR32|B30,E }}EOP, UNOP(O(O_INC,SB), "inc",0x0,0xA), - NEW_SOP(O(O_INC,SW),0,2,"inc.w") ,{DBIT,RD16,E },{0x0,0xB,0x5|DBIT,RD16,E} EOP, - NEW_SOP(O(O_INC,SL),0,2,"inc.l") ,{DBIT,RD32,E },{0x0,0xB,0x7|DBIT,RD32|B30,E} EOP, - - SOP(O(O_JMP,SB),4,"jmp"),{RSIND,E,0},{0x5,0x9,B30|RSIND,0x0,E,0,0,0,0}EOP, - SOP(O(O_JMP,SB),6,"jmp"),{SRC|ABSJMP,E,0},{0x5,0xA,SRC|ABSJMP,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,E}EOP, - SOP(O(O_JMP,SB),8,"jmp"),{SRC|MEMIND,E,0},{0x5,0xB,SRC|MEMIND,IGNORE,E,0,0,0,0}EOP, - - SOP(O(O_JSR,SB),6,"jsr"),{SRC|RSIND,E,0}, {0x5,0xD,B30|RSIND,0x0,E,0,0,0,0}EOP, - SOP(O(O_JSR,SB),8,"jsr"),{SRC|ABSJMP,E,0},{0x5,0xE,SRC|ABSJMP,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,E}EOP, - SOP(O(O_JSR,SB),8,"jsr"),{SRC|MEMIND,E,0},{0x5,0xF,SRC|MEMIND,IGNORE,E,0,0,0,0}EOP, - - NEW_SOP(O(O_LDC,SB),1,2,"ldc"),{IMM8,CCR,E}, { 0x0,0x7,IMM8,IGNORE,E,0,0,0,0}EOP, - NEW_SOP(O(O_LDC,SB),1,2,"ldc"),{OR8,CCR,E}, { 0x0,0x3,0x0,OR8,E,0,0,0,0}EOP, - NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{ABS16SRC,CCR,E}, {PREFIXLDC,0x6,0xB,0x0,0x0,ABS16SRC,IGNORE,IGNORE,IGNORE,E}EOP, - NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{ABS32SRC,CCR,E}, {PREFIXLDC,0x6,0xB,0x2,0x0,SRC|ABS32LIST,E}EOP, - NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{DISP|SRC|L_16,CCR,E},{PREFIXLDC,0x6,0xF,B30|DISPREG,0,DISP|L_16,IGNORE,IGNORE,IGNORE,E}EOP, - NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{DISP|SRC|L_32,CCR,E},{PREFIXLDC,0x7,0x8,B30|DISPREG,0,0x6,0xB,0x2,0x0,SRC|DISP32LIST,E}EOP, - NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{RSINC,CCR,E}, {PREFIXLDC,0x6,0xD,B30|RSINC,0x0,E}EOP, - NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{RSIND,CCR,E}, {PREFIXLDC,0x6,0x9,B30|RDIND,0x0,E} EOP, - - NEW_SOP(O(O_LDC,SB),1,2,"ldc"),{IMM8,EXR,E}, { 0x0,0x1,0x4,0x1,0x0,0x7,IMM8,IGNORE,E,0,0,0,0}EOP, - NEW_SOP(O(O_LDC,SB),1,2,"ldc"),{OR8,EXR,E}, { 0x0,0x3,0x1,OR8,E,0,0,0,0}EOP, - NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{ABS16SRC,EXR,E}, { 0x0,0x1,0x4,0x1,0x6,0xb,0x0,0x0,ABS16SRC,IGNORE,IGNORE,IGNORE,E}EOP, - NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{ABS32SRC,EXR,E}, { 0x0,0x1,0x4,0x1,0x6,0xb,0x2,0x0,SRC|ABS32LIST,E}EOP, - NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{DISP|SRC|L_16,EXR,E},{ 0x0,0x1,0x4,0x1,0x6,0xf,B30|DISPREG,0,DISP|L_16,IGNORE,IGNORE,IGNORE,E}EOP, - NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{DISP|SRC|L_32,EXR,E},{ 0x0,0x1,0x4,0x1,0x7,0x8,B30|DISPREG,0,0x6,0xB,0x2,0x0,SRC|DISP32LIST,E}EOP, - NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{RSINC,EXR,E}, { 0x0,0x1,0x4,0x1,0x6,0xd,B30|RSINC,0x0,E}EOP, - NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{RSIND,EXR,E}, { 0x0,0x1,0x4,0x1,0x6,0x9,B30|RDIND,0x0,E} EOP, - - SOP(O(O_MOV_TO_REG,SB),4,"mov.b"),{ABS|SRC|L_16|MEMRELAX,RD8,E}, { 0x6,0xA,0x0,RD8,SRC|ABS|MEMRELAX|A16LIST,E}EOP, - SOP(O(O_MOV_TO_REG,SB),6,"mov.b"),{ABS|SRC|L_32|MEMRELAX,RD8,E }, { 0x6,0xA,0x2,RD8,SRC|ABS|MEMRELAX|A32LIST,E }EOP, - SOP(O(O_MOV_TO_MEM,SB),4,"mov.b"),{RS8,ABS|L_16|MEMRELAX|DST,E}, { 0x6,0xA,0x8,RS8,DST|ABS|MEMRELAX|A16LIST,E}EOP, - SOP(O(O_MOV_TO_MEM,SB),6,"mov.b"),{RS8,ABS|DST|L_32|MEMRELAX,E }, { 0x6,0xA,0xA,RS8,DST|ABS|MEMRELAX|A32LIST,E }EOP, + NEW_SOP(O(O_INC,SW),0,2,"inc.w") ,{{DBIT,RD16,E }},{{0x0,0xB,0x5|DBIT,RD16,E}} EOP, + NEW_SOP(O(O_INC,SL),0,2,"inc.l") ,{{DBIT,RD32,E }},{{0x0,0xB,0x7|DBIT,RD32|B30,E}} EOP, + + SOP(O(O_JMP,SB),4,"jmp"),{{RSIND,E,0}},{{0x5,0x9,B30|RSIND,0x0,E,0,0,0,0}}EOP, + SOP(O(O_JMP,SB),6,"jmp"),{{SRC|ABSJMP,E,0}},{{0x5,0xA,SRC|ABSJMP,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,E}}EOP, + SOP(O(O_JMP,SB),8,"jmp"),{{SRC|MEMIND,E,0}},{{0x5,0xB,SRC|MEMIND,IGNORE,E,0,0,0,0}}EOP, + + SOP(O(O_JSR,SB),6,"jsr"),{{SRC|RSIND,E,0}}, {{0x5,0xD,B30|RSIND,0x0,E,0,0,0,0}}EOP, + SOP(O(O_JSR,SB),8,"jsr"),{{SRC|ABSJMP,E,0}},{{0x5,0xE,SRC|ABSJMP,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,E}}EOP, + SOP(O(O_JSR,SB),8,"jsr"),{{SRC|MEMIND,E,0}},{{0x5,0xF,SRC|MEMIND,IGNORE,E,0,0,0,0}}EOP, + + NEW_SOP(O(O_LDC,SB),1,2,"ldc"),{{IMM8,CCR,E}}, {{ 0x0,0x7,IMM8,IGNORE,E,0,0,0,0}}EOP, + NEW_SOP(O(O_LDC,SB),1,2,"ldc"),{{OR8,CCR,E}}, {{ 0x0,0x3,0x0,OR8,E,0,0,0,0}}EOP, + NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{ABS16SRC,CCR,E}}, {{PREFIXLDC,0x6,0xB,0x0,0x0,ABS16SRC,IGNORE,IGNORE,IGNORE,E}}EOP, + NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{ABS32SRC,CCR,E}}, {{PREFIXLDC,0x6,0xB,0x2,0x0,SRC|ABS32LIST,E}}EOP, + NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{DISP|SRC|L_16,CCR,E}},{{PREFIXLDC,0x6,0xF,B30|DISPREG,0,DISP|L_16,IGNORE,IGNORE,IGNORE,E}}EOP, + NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{DISP|SRC|L_32,CCR,E}},{{PREFIXLDC,0x7,0x8,B30|DISPREG,0,0x6,0xB,0x2,0x0,SRC|DISP32LIST,E}}EOP, + NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{RSINC,CCR,E}}, {{PREFIXLDC,0x6,0xD,B30|RSINC,0x0,E}}EOP, + NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{RSIND,CCR,E}}, {{PREFIXLDC,0x6,0x9,B30|RDIND,0x0,E}} EOP, + + NEW_SOP(O(O_LDC,SB),1,2,"ldc"),{{IMM8,EXR,E}}, {{ 0x0,0x1,0x4,0x1,0x0,0x7,IMM8,IGNORE,E,0,0,0,0}}EOP, + NEW_SOP(O(O_LDC,SB),1,2,"ldc"),{{OR8,EXR,E}}, {{ 0x0,0x3,0x1,OR8,E,0,0,0,0}}EOP, + NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{ABS16SRC,EXR,E}}, {{ 0x0,0x1,0x4,0x1,0x6,0xb,0x0,0x0,ABS16SRC,IGNORE,IGNORE,IGNORE,E}}EOP, + NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{ABS32SRC,EXR,E}}, {{ 0x0,0x1,0x4,0x1,0x6,0xb,0x2,0x0,SRC|ABS32LIST,E}}EOP, + NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{DISP|SRC|L_16,EXR,E}},{{ 0x0,0x1,0x4,0x1,0x6,0xf,B30|DISPREG,0,DISP|L_16,IGNORE,IGNORE,IGNORE,E}}EOP, + NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{DISP|SRC|L_32,EXR,E}},{{ 0x0,0x1,0x4,0x1,0x7,0x8,B30|DISPREG,0,0x6,0xB,0x2,0x0,SRC|DISP32LIST,E}}EOP, + NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{RSINC,EXR,E}}, {{ 0x0,0x1,0x4,0x1,0x6,0xd,B30|RSINC,0x0,E}}EOP, + NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{RSIND,EXR,E}}, {{ 0x0,0x1,0x4,0x1,0x6,0x9,B30|RDIND,0x0,E}} EOP, + + SOP(O(O_MOV_TO_REG,SB),4,"mov.b"),{{ABS|SRC|L_16|MEMRELAX,RD8,E}}, {{ 0x6,0xA,0x0,RD8,SRC|ABS|MEMRELAX|A16LIST,E}}EOP, + SOP(O(O_MOV_TO_REG,SB),6,"mov.b"),{{ABS|SRC|L_32|MEMRELAX,RD8,E }}, {{ 0x6,0xA,0x2,RD8,SRC|ABS|MEMRELAX|A32LIST,E }}EOP, + SOP(O(O_MOV_TO_MEM,SB),4,"mov.b"),{{RS8,ABS|L_16|MEMRELAX|DST,E}}, {{ 0x6,0xA,0x8,RS8,DST|ABS|MEMRELAX|A16LIST,E}}EOP, + SOP(O(O_MOV_TO_MEM,SB),6,"mov.b"),{{RS8,ABS|DST|L_32|MEMRELAX,E }}, {{ 0x6,0xA,0xA,RS8,DST|ABS|MEMRELAX|A32LIST,E }}EOP, - SOP(O(O_MOV_TO_REG,SB),6,"mov.b"),{DISP|L_32|SRC,RD8,E}, { 0x7,0x8,B30|DISPREG,0x0,0x6,0xA,0x2,RD8,SRC|DISP32LIST,E}EOP, - SOP(O(O_MOV_TO_MEM,SB),6,"mov.b"),{RS8,DISP|L_32|DST,E}, { 0x7,0x8,B30|DISPREG,0x0,0x6,0xA,0xA,RS8,DST|DISP32LIST,E}EOP, - - - - SOP(O(O_MOV_TO_REG,SB),2,"mov.b"),{RS8,RD8,E}, { 0x0,0xC,RS8,RD8,E,0,0,0,0}EOP, - SOP(O(O_MOV_TO_REG,SB),2,"mov.b"),{IMM8,RD8,E}, { 0xF,RD8,IMM8,IGNORE,E,0,0,0,0}EOP, - SOP(O(O_MOV_TO_REG,SB),4,"mov.b"),{RSIND,RD8,E}, { 0x6,0x8,B30|RSIND,RD8,E,0,0,0,0}EOP, - SOP(O(O_MOV_TO_REG,SB),6,"mov.b"),{DISP16SRC,RD8,E}, { 0x6,0xE,B30|DISPREG,RD8,DISP16SRC,IGNORE,IGNORE,IGNORE,E}EOP, - SOP(O(O_MOV_TO_REG,SB),6,"mov.b"),{RSINC,RD8,E}, { 0x6,0xC,B30|RSINC,RD8,E,0,0,0,0}EOP, - - SOP(O(O_MOV_TO_REG,SB),4,"mov.b"),{ABS8SRC,RD8,E}, { 0x2,RD8,ABS8SRC,IGNORE,E,0,0,0,0}EOP, - SOP(O(O_MOV_TO_MEM,SB),4,"mov.b"),{RS8,RDIND,E}, { 0x6,0x8,RDIND|B31,RS8,E,0,0,0,0}EOP, - SOP(O(O_MOV_TO_MEM,SB),6,"mov.b"),{RS8,DISP16DST,E}, { 0x6,0xE,DISPREG|B31,RS8,DISP16DST,IGNORE,IGNORE,IGNORE,E}EOP, - SOP(O(O_MOV_TO_MEM,SB),6,"mov.b"),{RS8,RDDEC|B31,E}, { 0x6,0xC,RDDEC|B31,RS8,E,0,0,0,0}EOP, - - SOP(O(O_MOV_TO_MEM,SB),4,"mov.b"),{RS8,ABS8DST,E}, { 0x3,RS8,ABS8DST,IGNORE,E,0,0,0,0}EOP, - - SOP(O(O_MOV_TO_MEM,SW),6,"mov.w"),{RS16,RDIND,E}, { 0x6,0x9,RDIND|B31,RS16,E,0,0,0,0}EOP, - SOP(O(O_MOV_TO_REG,SW),6,"mov.w"),{DISP|L_32|SRC,RD16,E},{ 0x7,0x8,B30|DISPREG,0x0,0x6,0xB,0x2,RD16,SRC|DISP32LIST,E}EOP, - SOP(O(O_MOV_TO_MEM,SW),6,"mov.w"),{RS16,DISP|L_32|DST,E},{ 0x7,0x8,B30|DISPREG,0x0,0x6,0xB,0xA,RS16,DST|DISP32LIST,E}EOP, - SOP(O(O_MOV_TO_REG,SW),6,"mov.w"),{ABS|L_32|MEMRELAX|SRC,RD16,E },{ 0x6,0xB,0x2,RD16,SRC|MEMRELAX|ABS32LIST,E }EOP, - SOP(O(O_MOV_TO_MEM,SW),6,"mov.w"),{RS16,ABS|L_32|MEMRELAX|DST,E },{ 0x6,0xB,0xA,RS16,DST|MEMRELAX|ABS32LIST,E }EOP, - SOP(O(O_MOV_TO_REG,SW),2,"mov.w"),{RS16,RD16,E}, { 0x0,0xD,RS16, RD16,E,0,0,0,0}EOP, - SOP(O(O_MOV_TO_REG,SW),4,"mov.w"),{IMM16,RD16,E}, { 0x7,0x9,0x0,RD16,IMM16,IGNORE,IGNORE,IGNORE,E}EOP, - SOP(O(O_MOV_TO_REG,SW),4,"mov.w"),{RSIND,RD16,E}, { 0x6,0x9,B30|RSIND,RD16,E,0,0,0,0}EOP, - SOP(O(O_MOV_TO_REG,SW),6,"mov.w"),{DISP16SRC,RD16,E}, { 0x6,0xF,B30|DISPREG,RD16,DISP16SRC,IGNORE,IGNORE,IGNORE,E}EOP, - SOP(O(O_MOV_TO_REG,SW),6,"mov.w"),{RSINC,RD16,E}, { 0x6,0xD,B30|RSINC,RD16,E,0,0,0,0}EOP, - SOP(O(O_MOV_TO_REG,SW),6,"mov.w"),{ABS16SRC,RD16,E}, { 0x6,0xB,0x0,RD16,ABS16SRC,IGNORE,IGNORE,IGNORE,E}EOP, - - SOP(O(O_MOV_TO_MEM,SW),6,"mov.w"),{RS16,DISP16DST,E}, { 0x6,0xF,DISPREG|B31,RS16,DISP16DST,IGNORE,IGNORE,IGNORE,E}EOP, - SOP(O(O_MOV_TO_MEM,SW),6,"mov.w"),{RS16,RDDEC,E}, { 0x6,0xD,RDDEC|B31,RS16,E,0,0,0,0}EOP, - SOP(O(O_MOV_TO_MEM,SW),6,"mov.w"),{RS16,ABS16DST,E}, { 0x6,0xB,0x8,RS16,ABS16DST,IGNORE,IGNORE,IGNORE,E}EOP, - - SOP(O(O_MOV_TO_REG,SL),4,"mov.l"),{IMM32,RD32,E}, { 0x7,0xA,0x0,B30|RD32,IMM32LIST,E}EOP, - SOP(O(O_MOV_TO_REG,SL),2,"mov.l"),{RS32,RD32,E}, { 0x0,0xF,B31|RS32,B30|RD32,E,0,0,0,0}EOP, - - SOP(O(O_MOV_TO_REG,SL),4,"mov.l"),{RSIND,RD32,E}, { PREFIX32,0x6,0x9,RSIND|B30,B30|RD32,E,0,0,0,0 }EOP, - SOP(O(O_MOV_TO_REG,SL),6,"mov.l"),{DISP16SRC,RD32,E}, { PREFIX32,0x6,0xF,DISPREG|B30,B30|RD32,DISP16SRC,IGNORE,IGNORE,IGNORE,E }EOP, - SOP(O(O_MOV_TO_REG,SL),6,"mov.l"),{DISP|L_32|SRC,RD32,E},{ PREFIX32,0x7,0x8,B30|DISPREG,0x0,0x6,0xB,0x2,B30|RD32,SRC|DISP32LIST,E }EOP, - SOP(O(O_MOV_TO_REG,SL),6,"mov.l"),{RSINC,RD32,E}, { PREFIX32,0x6,0xD,B30|RSINC,B30|RD32,E,0,0,0,0 }EOP, - SOP(O(O_MOV_TO_REG,SL),6,"mov.l"),{ABS16SRC,RD32,E}, { PREFIX32,0x6,0xB,0x0,B30|RD32,ABS16SRC,IGNORE,IGNORE,IGNORE,E }EOP, - SOP(O(O_MOV_TO_REG,SL),6,"mov.l"),{ABS32SRC|MEMRELAX,RD32,E }, { PREFIX32,0x6,0xB,0x2,B30|RD32,SRC|MEMRELAX|ABS32LIST,E }EOP, - SOP(O(O_MOV_TO_MEM,SL),6,"mov.l"),{RS32,RDIND,E}, { PREFIX32,0x6,0x9,RDIND|B31,B30|RS32,E,0,0,0,0 }EOP, - SOP(O(O_MOV_TO_MEM,SL),6,"mov.l"),{RS32,DISP16DST,E}, { PREFIX32,0x6,0xF,DISPREG|B31,B30|RS32,DISP16DST,IGNORE,IGNORE,IGNORE,E }EOP, - SOP(O(O_MOV_TO_MEM,SL),6,"mov.l"),{RS32,DISP|L_32|DST,E},{ PREFIX32,0x7,0x8,B31|DISPREG,0x0,0x6,0xB,0xA,B30|RS32,DST|DISP32LIST,E }EOP, - SOP(O(O_MOV_TO_MEM,SL),6,"mov.l"),{RS32,RDDEC,E}, { PREFIX32,0x6,0xD,RDDEC|B31,B30|RS32,E,0,0,0,0 }EOP, - SOP(O(O_MOV_TO_MEM,SL),6,"mov.l"),{RS32,ABS16DST,E}, { PREFIX32,0x6,0xB,0x8,B30|RS32,ABS16DST,IGNORE,IGNORE,IGNORE,E }EOP, - SOP(O(O_MOV_TO_MEM,SL),6,"mov.l"),{RS32,ABS32DST|MEMRELAX,E }, { PREFIX32,0x6,0xB,0xA,B30|RS32,DST|MEMRELAX|ABS32LIST,E }EOP, - - SOP(O(O_MOV_TO_REG,SB),10,"movfpe"),{ABS16SRC,RD8,E},{ 0x6,0xA,0x4,RD8,ABS16SRC,IGNORE,IGNORE,IGNORE,E}EOP, - SOP(O(O_MOV_TO_MEM,SB),10,"movtpe"),{RS8,ABS16DST,E},{ 0x6,0xA,0xC,RS8,ABS16DST,IGNORE,IGNORE,IGNORE,E}EOP, - - NEW_SOP(O(O_MULU,SB),1,14,"mulxu.b"),{RS8,RD16,E}, { 0x5,0x0,RS8,RD16,E,0,0,0,0}EOP, - NEW_SOP(O(O_MULU,SW),0,14,"mulxu.w"),{RS16,RD32,E},{ 0x5,0x2,RS16,B30|RD32,E,0,0,0,0}EOP, - - NEW_SOP(O(O_MULS,SB),0,20,"mulxs.b"),{RS8,RD16,E}, { 0x0,0x1,0xc,0x0,0x5,0x0,RS8,RD16,E}EOP, - NEW_SOP(O(O_MULS,SW),0,20,"mulxs.w"),{RS16,RD32,E},{ 0x0,0x1,0xc,0x0,0x5,0x2,RS16,B30|RD32,E}EOP, + SOP(O(O_MOV_TO_REG,SB),6,"mov.b"),{{DISP|L_32|SRC,RD8,E}}, {{ 0x7,0x8,B30|DISPREG,0x0,0x6,0xA,0x2,RD8,SRC|DISP32LIST,E}}EOP, + SOP(O(O_MOV_TO_MEM,SB),6,"mov.b"),{{RS8,DISP|L_32|DST,E}}, {{ 0x7,0x8,B30|DISPREG,0x0,0x6,0xA,0xA,RS8,DST|DISP32LIST,E}}EOP, + + + + SOP(O(O_MOV_TO_REG,SB),2,"mov.b"),{{RS8,RD8,E}}, {{ 0x0,0xC,RS8,RD8,E,0,0,0,0}}EOP, + SOP(O(O_MOV_TO_REG,SB),2,"mov.b"),{{IMM8,RD8,E}}, {{ 0xF,RD8,IMM8,IGNORE,E,0,0,0,0}}EOP, + SOP(O(O_MOV_TO_REG,SB),4,"mov.b"),{{RSIND,RD8,E}}, {{ 0x6,0x8,B30|RSIND,RD8,E,0,0,0,0}}EOP, + SOP(O(O_MOV_TO_REG,SB),6,"mov.b"),{{DISP16SRC,RD8,E}}, {{ 0x6,0xE,B30|DISPREG,RD8,DISP16SRC,IGNORE,IGNORE,IGNORE,E}}EOP, + SOP(O(O_MOV_TO_REG,SB),6,"mov.b"),{{RSINC,RD8,E}}, {{ 0x6,0xC,B30|RSINC,RD8,E,0,0,0,0}}EOP, + + SOP(O(O_MOV_TO_REG,SB),4,"mov.b"),{{ABS8SRC,RD8,E}}, {{ 0x2,RD8,ABS8SRC,IGNORE,E,0,0,0,0}}EOP, + SOP(O(O_MOV_TO_MEM,SB),4,"mov.b"),{{RS8,RDIND,E}}, {{ 0x6,0x8,RDIND|B31,RS8,E,0,0,0,0}}EOP, + SOP(O(O_MOV_TO_MEM,SB),6,"mov.b"),{{RS8,DISP16DST,E}}, {{ 0x6,0xE,DISPREG|B31,RS8,DISP16DST,IGNORE,IGNORE,IGNORE,E}}EOP, + SOP(O(O_MOV_TO_MEM,SB),6,"mov.b"),{{RS8,RDDEC|B31,E}}, {{ 0x6,0xC,RDDEC|B31,RS8,E,0,0,0,0}}EOP, + + SOP(O(O_MOV_TO_MEM,SB),4,"mov.b"),{{RS8,ABS8DST,E}}, {{ 0x3,RS8,ABS8DST,IGNORE,E,0,0,0,0}}EOP, + + SOP(O(O_MOV_TO_MEM,SW),6,"mov.w"),{{RS16,RDIND,E}}, {{ 0x6,0x9,RDIND|B31,RS16,E,0,0,0,0}}EOP, + SOP(O(O_MOV_TO_REG,SW),6,"mov.w"),{{DISP|L_32|SRC,RD16,E}},{{ 0x7,0x8,B30|DISPREG,0x0,0x6,0xB,0x2,RD16,SRC|DISP32LIST,E}}EOP, + SOP(O(O_MOV_TO_MEM,SW),6,"mov.w"),{{RS16,DISP|L_32|DST,E}},{{ 0x7,0x8,B30|DISPREG,0x0,0x6,0xB,0xA,RS16,DST|DISP32LIST,E}}EOP, + SOP(O(O_MOV_TO_REG,SW),6,"mov.w"),{{ABS|L_32|MEMRELAX|SRC,RD16,E }},{{ 0x6,0xB,0x2,RD16,SRC|MEMRELAX|ABS32LIST,E }}EOP, + SOP(O(O_MOV_TO_MEM,SW),6,"mov.w"),{{RS16,ABS|L_32|MEMRELAX|DST,E }},{{ 0x6,0xB,0xA,RS16,DST|MEMRELAX|ABS32LIST,E }}EOP, + SOP(O(O_MOV_TO_REG,SW),2,"mov.w"),{{RS16,RD16,E}}, {{ 0x0,0xD,RS16, RD16,E,0,0,0,0}}EOP, + SOP(O(O_MOV_TO_REG,SW),4,"mov.w"),{{IMM16,RD16,E}}, {{ 0x7,0x9,0x0,RD16,IMM16,IGNORE,IGNORE,IGNORE,E}}EOP, + SOP(O(O_MOV_TO_REG,SW),4,"mov.w"),{{RSIND,RD16,E}}, {{ 0x6,0x9,B30|RSIND,RD16,E,0,0,0,0}}EOP, + SOP(O(O_MOV_TO_REG,SW),6,"mov.w"),{{DISP16SRC,RD16,E}}, {{ 0x6,0xF,B30|DISPREG,RD16,DISP16SRC,IGNORE,IGNORE,IGNORE,E}}EOP, + SOP(O(O_MOV_TO_REG,SW),6,"mov.w"),{{RSINC,RD16,E}}, {{ 0x6,0xD,B30|RSINC,RD16,E,0,0,0,0}}EOP, + SOP(O(O_MOV_TO_REG,SW),6,"mov.w"),{{ABS16SRC,RD16,E}}, {{ 0x6,0xB,0x0,RD16,ABS16SRC,IGNORE,IGNORE,IGNORE,E}}EOP, + + SOP(O(O_MOV_TO_MEM,SW),6,"mov.w"),{{RS16,DISP16DST,E}}, {{ 0x6,0xF,DISPREG|B31,RS16,DISP16DST,IGNORE,IGNORE,IGNORE,E}}EOP, + SOP(O(O_MOV_TO_MEM,SW),6,"mov.w"),{{RS16,RDDEC,E}}, {{ 0x6,0xD,RDDEC|B31,RS16,E,0,0,0,0}}EOP, + SOP(O(O_MOV_TO_MEM,SW),6,"mov.w"),{{RS16,ABS16DST,E}}, {{ 0x6,0xB,0x8,RS16,ABS16DST,IGNORE,IGNORE,IGNORE,E}}EOP, + + SOP(O(O_MOV_TO_REG,SL),4,"mov.l"),{{IMM32,RD32,E}}, {{ 0x7,0xA,0x0,B30|RD32,IMM32LIST,E}}EOP, + SOP(O(O_MOV_TO_REG,SL),2,"mov.l"),{{RS32,RD32,E}}, {{ 0x0,0xF,B31|RS32,B30|RD32,E,0,0,0,0}}EOP, + + SOP(O(O_MOV_TO_REG,SL),4,"mov.l"),{{RSIND,RD32,E}}, {{ PREFIX32,0x6,0x9,RSIND|B30,B30|RD32,E,0,0,0,0 }}EOP, + SOP(O(O_MOV_TO_REG,SL),6,"mov.l"),{{DISP16SRC,RD32,E}}, {{ PREFIX32,0x6,0xF,DISPREG|B30,B30|RD32,DISP16SRC,IGNORE,IGNORE,IGNORE,E }}EOP, + SOP(O(O_MOV_TO_REG,SL),6,"mov.l"),{{DISP|L_32|SRC,RD32,E}},{{ PREFIX32,0x7,0x8,B30|DISPREG,0x0,0x6,0xB,0x2,B30|RD32,SRC|DISP32LIST,E }}EOP, + SOP(O(O_MOV_TO_REG,SL),6,"mov.l"),{{RSINC,RD32,E}}, {{ PREFIX32,0x6,0xD,B30|RSINC,B30|RD32,E,0,0,0,0 }}EOP, + SOP(O(O_MOV_TO_REG,SL),6,"mov.l"),{{ABS16SRC,RD32,E}}, {{ PREFIX32,0x6,0xB,0x0,B30|RD32,ABS16SRC,IGNORE,IGNORE,IGNORE,E }}EOP, + SOP(O(O_MOV_TO_REG,SL),6,"mov.l"),{{ABS32SRC|MEMRELAX,RD32,E }}, {{ PREFIX32,0x6,0xB,0x2,B30|RD32,SRC|MEMRELAX|ABS32LIST,E }}EOP, + SOP(O(O_MOV_TO_MEM,SL),6,"mov.l"),{{RS32,RDIND,E}}, {{ PREFIX32,0x6,0x9,RDIND|B31,B30|RS32,E,0,0,0,0 }}EOP, + SOP(O(O_MOV_TO_MEM,SL),6,"mov.l"),{{RS32,DISP16DST,E}}, {{ PREFIX32,0x6,0xF,DISPREG|B31,B30|RS32,DISP16DST,IGNORE,IGNORE,IGNORE,E }}EOP, + SOP(O(O_MOV_TO_MEM,SL),6,"mov.l"),{{RS32,DISP|L_32|DST,E}},{{ PREFIX32,0x7,0x8,B31|DISPREG,0x0,0x6,0xB,0xA,B30|RS32,DST|DISP32LIST,E }}EOP, + SOP(O(O_MOV_TO_MEM,SL),6,"mov.l"),{{RS32,RDDEC,E}}, {{ PREFIX32,0x6,0xD,RDDEC|B31,B30|RS32,E,0,0,0,0 }}EOP, + SOP(O(O_MOV_TO_MEM,SL),6,"mov.l"),{{RS32,ABS16DST,E}}, {{ PREFIX32,0x6,0xB,0x8,B30|RS32,ABS16DST,IGNORE,IGNORE,IGNORE,E }}EOP, + SOP(O(O_MOV_TO_MEM,SL),6,"mov.l"),{{RS32,ABS32DST|MEMRELAX,E }}, {{ PREFIX32,0x6,0xB,0xA,B30|RS32,DST|MEMRELAX|ABS32LIST,E }}EOP, + + SOP(O(O_MOV_TO_REG,SB),10,"movfpe"),{{ABS16SRC,RD8,E}},{{ 0x6,0xA,0x4,RD8,ABS16SRC,IGNORE,IGNORE,IGNORE,E}}EOP, + SOP(O(O_MOV_TO_MEM,SB),10,"movtpe"),{{RS8,ABS16DST,E}},{{ 0x6,0xA,0xC,RS8,ABS16DST,IGNORE,IGNORE,IGNORE,E}}EOP, + + NEW_SOP(O(O_MULU,SB),1,14,"mulxu.b"),{{RS8,RD16,E}}, {{ 0x5,0x0,RS8,RD16,E,0,0,0,0}}EOP, + NEW_SOP(O(O_MULU,SW),0,14,"mulxu.w"),{{RS16,RD32,E}},{{ 0x5,0x2,RS16,B30|RD32,E,0,0,0,0}}EOP, + + NEW_SOP(O(O_MULS,SB),0,20,"mulxs.b"),{{RS8,RD16,E}}, {{ 0x0,0x1,0xc,0x0,0x5,0x0,RS8,RD16,E}}EOP, + NEW_SOP(O(O_MULS,SW),0,20,"mulxs.w"),{{RS16,RD32,E}},{{ 0x0,0x1,0xc,0x0,0x5,0x2,RS16,B30|RD32,E}}EOP, /* ??? This can use UNOP3. */ - NEW_SOP(O(O_NEG,SB),1,2,"neg.b"),{ OR8,E, 0},{ 0x1,0x7,0x8,OR8,E,0,0,0,0}EOP, - NEW_SOP(O(O_NEG,SW),0,2,"neg.w"),{ OR16,E,0},{ 0x1,0x7,0x9,OR16,E}EOP, - NEW_SOP(O(O_NEG,SL),0,2,"neg.l"),{ OR32,E,0},{ 0x1,0x7,0xB,B30|OR32,E}EOP, + NEW_SOP(O(O_NEG,SB),1,2,"neg.b"),{{ OR8,E, 0}},{{ 0x1,0x7,0x8,OR8,E,0,0,0,0}}EOP, + NEW_SOP(O(O_NEG,SW),0,2,"neg.w"),{{ OR16,E,0}},{{ 0x1,0x7,0x9,OR16,E}}EOP, + NEW_SOP(O(O_NEG,SL),0,2,"neg.l"),{{ OR32,E,0}},{{ 0x1,0x7,0xB,B30|OR32,E}}EOP, - NEW_SOP(O(O_NOP,SN),1,2,"nop"),{E,0,0},{ 0x0,0x0,0x0,0x0,E,0,0,0,0}EOP, + NEW_SOP(O(O_NOP,SN),1,2,"nop"),{{E,0,0}},{{ 0x0,0x0,0x0,0x0,E,0,0,0,0}}EOP, /* ??? This can use UNOP3. */ - NEW_SOP(O(O_NOT,SB),1,2,"not.b"),{ OR8,E, 0},{ 0x1,0x7,0x0,OR8,E,0,0,0,0}EOP, - NEW_SOP(O(O_NOT,SW),0,2,"not.w"),{ OR16,E,0},{ 0x1,0x7,0x1,OR16,E}EOP, - NEW_SOP(O(O_NOT,SL),0,2,"not.l"),{ OR32,E,0},{ 0x1,0x7,0x3,B30|OR32,E}EOP, + NEW_SOP(O(O_NOT,SB),1,2,"not.b"),{{ OR8,E, 0}},{{ 0x1,0x7,0x0,OR8,E,0,0,0,0}}EOP, + NEW_SOP(O(O_NOT,SW),0,2,"not.w"),{{ OR16,E,0}},{{ 0x1,0x7,0x1,OR16,E}}EOP, + NEW_SOP(O(O_NOT,SL),0,2,"not.l"),{{ OR32,E,0}},{{ 0x1,0x7,0x3,B30|OR32,E}}EOP, TWOOP(O(O_OR, SB),"or.b",0xC,0x1,0x4), - NEW_SOP(O(O_OR,SW),0,4,"or.w"),{IMM16,RD16,E },{0x7,0x9,0x4,RD16,IMM16,IGNORE,IGNORE,IGNORE,E} EOP, - NEW_SOP(O(O_OR,SW),0,2,"or.w"),{RS16,RD16,E },{0x6,0x4,RS16,RD16,E} EOP, + NEW_SOP(O(O_OR,SW),0,4,"or.w"),{{IMM16,RD16,E }},{{0x7,0x9,0x4,RD16,IMM16,IGNORE,IGNORE,IGNORE,E}} EOP, + NEW_SOP(O(O_OR,SW),0,2,"or.w"),{{RS16,RD16,E }},{{0x6,0x4,RS16,RD16,E}} EOP, - NEW_SOP(O(O_OR,SL),0,6,"or.l"),{IMM32,RD32,E },{0x7,0xA,0x4,B30|RD32,IMM32LIST,E} EOP, - NEW_SOP(O(O_OR,SL),0,2,"or.l"),{RS32,RD32,E },{0x0,0x1,0xF,0x0,0x6,0x4,B30|RS32,B30|RD32,E} EOP, + NEW_SOP(O(O_OR,SL),0,6,"or.l"),{{IMM32,RD32,E }},{{0x7,0xA,0x4,B30|RD32,IMM32LIST,E}} EOP, + NEW_SOP(O(O_OR,SL),0,2,"or.l"),{{RS32,RD32,E }},{{0x0,0x1,0xF,0x0,0x6,0x4,B30|RS32,B30|RD32,E}} EOP, - NEW_SOP(O(O_ORC,SB),1,2,"orc"),{IMM8,CCR,E},{ 0x0,0x4,IMM8,IGNORE,E,0,0,0,0}EOP, - NEW_SOP(O(O_ORC,SB),1,2,"orc"),{IMM8,EXR,E},{ 0x0,0x1,0x4,0x1,0x0,0x4,IMM8,IGNORE,E,0,0,0,0}EOP, + NEW_SOP(O(O_ORC,SB),1,2,"orc"),{{IMM8,CCR,E}},{{ 0x0,0x4,IMM8,IGNORE,E,0,0,0,0}}EOP, + NEW_SOP(O(O_ORC,SB),1,2,"orc"),{{IMM8,EXR,E}},{{ 0x0,0x1,0x4,0x1,0x0,0x4,IMM8,IGNORE,E,0,0,0,0}}EOP, - NEW_SOP(O(O_MOV_TO_REG,SW),1,6,"pop.w"),{OR16,E,0},{ 0x6,0xD,0x7,OR16,E,0,0,0,0}EOP, - NEW_SOP(O(O_MOV_TO_REG,SL),0,6,"pop.l"),{OR32,E,0},{ PREFIX32,0x6,0xD,0x7,OR32|B30,E,0,0,0,0}EOP, - NEW_SOP(O(O_MOV_TO_MEM,SW),1,6,"push.w"),{OR16,E,0},{ 0x6,0xD,0xF,OR16,E,0,0,0,0}EOP, - NEW_SOP(O(O_MOV_TO_MEM,SL),0,6,"push.l"),{OR32,E,0},{ PREFIX32,0x6,0xD,0xF,OR32|B30,E,0,0,0,0}EOP, + NEW_SOP(O(O_MOV_TO_REG,SW),1,6,"pop.w"),{{OR16,E,0}},{{ 0x6,0xD,0x7,OR16,E,0,0,0,0}}EOP, + NEW_SOP(O(O_MOV_TO_REG,SL),0,6,"pop.l"),{{OR32,E,0}},{{ PREFIX32,0x6,0xD,0x7,OR32|B30,E,0,0,0,0}}EOP, + NEW_SOP(O(O_MOV_TO_MEM,SW),1,6,"push.w"),{{OR16,E,0}},{{ 0x6,0xD,0xF,OR16,E,0,0,0,0}}EOP, + NEW_SOP(O(O_MOV_TO_MEM,SL),0,6,"push.l"),{{OR32,E,0}},{{ PREFIX32,0x6,0xD,0xF,OR32|B30,E,0,0,0,0}}EOP, UNOP3(O_ROTL, "rotl", 0x1,0x2,0x8), UNOP3(O_ROTR, "rotr", 0x1,0x3,0x8), UNOP3(O_ROTXL, "rotxl",0x1,0x2,0x0), UNOP3(O_ROTXR, "rotxr",0x1,0x3,0x0), - SOP(O(O_BPT,SN), 10,"bpt"),{E,0,0},{ 0x7,0xA,0xF,0xF,E,0,0,0,0}EOP, - SOP(O(O_RTE,SN), 10,"rte"),{E,0,0},{ 0x5,0x6,0x7,0x0,E,0,0,0,0}EOP, - SOP(O(O_RTS,SN), 8,"rts"),{E,0,0},{ 0x5,0x4,0x7,0x0,E,0,0,0,0}EOP, + SOP(O(O_BPT,SN), 10,"bpt"),{{E,0,0}},{{ 0x7,0xA,0xF,0xF,E,0,0,0,0}}EOP, + SOP(O(O_RTE,SN), 10,"rte"),{{E,0,0}},{{ 0x5,0x6,0x7,0x0,E,0,0,0,0}}EOP, + SOP(O(O_RTS,SN), 8,"rts"),{{E,0,0}},{{ 0x5,0x4,0x7,0x0,E,0,0,0,0}}EOP, UNOP3(O_SHAL, "shal",0x1,0x0,0x8), UNOP3(O_SHAR, "shar",0x1,0x1,0x8), UNOP3(O_SHLL, "shll",0x1,0x0,0x0), UNOP3(O_SHLR, "shlr",0x1,0x1,0x0), - SOP(O(O_SLEEP,SN),2,"sleep"),{E,0,0},{ 0x0,0x1,0x8,0x0,E,0,0,0,0} EOP, + SOP(O(O_SLEEP,SN),2,"sleep"),{{E,0,0}},{{ 0x0,0x1,0x8,0x0,E,0,0,0,0}} EOP, - NEW_SOP(O(O_STC,SB), 1,2,"stc"),{CCR,RD8,E},{ 0x0,0x2,0x0,RD8,E,0,0,0,0} EOP, + NEW_SOP(O(O_STC,SB), 1,2,"stc"),{{CCR,RD8,E}},{{ 0x0,0x2,0x0,RD8,E,0,0,0,0}} EOP, - NEW_SOP(O(O_STC,SB),0,2,"stc"),{CCR,RSIND,E}, {PREFIXLDC,0x6,0x9,B31|RDIND,0x0,E} EOP, - NEW_SOP(O(O_STC,SB),0,2,"stc"),{CCR,DISP|DST|L_16,E},{PREFIXLDC,0x6,0xF,B31|DISPREG,0,DST|DISP|L_16,IGNORE,IGNORE,IGNORE,E}EOP, - NEW_SOP(O(O_STC,SB),0,2,"stc"),{CCR,DISP|DST|L_32,E},{PREFIXLDC,0x7,0x8,B30|DISPREG,0,0x6,0xB,0xA,0x0,DST|DISP32LIST,E}EOP, - NEW_SOP(O(O_STC,SB),0,2,"stc"),{CCR,RDDEC,E}, {PREFIXLDC,0x6,0xD,B31|RDDEC,0x0,E}EOP, + NEW_SOP(O(O_STC,SB),0,2,"stc"),{{CCR,RSIND,E}}, {{PREFIXLDC,0x6,0x9,B31|RDIND,0x0,E}} EOP, + NEW_SOP(O(O_STC,SB),0,2,"stc"),{{CCR,DISP|DST|L_16,E}},{{PREFIXLDC,0x6,0xF,B31|DISPREG,0,DST|DISP|L_16,IGNORE,IGNORE,IGNORE,E}}EOP, + NEW_SOP(O(O_STC,SB),0,2,"stc"),{{CCR,DISP|DST|L_32,E}},{{PREFIXLDC,0x7,0x8,B30|DISPREG,0,0x6,0xB,0xA,0x0,DST|DISP32LIST,E}}EOP, + NEW_SOP(O(O_STC,SB),0,2,"stc"),{{CCR,RDDEC,E}}, {{PREFIXLDC,0x6,0xD,B31|RDDEC,0x0,E}}EOP, - NEW_SOP(O(O_STC,SB),0,2,"stc"),{CCR,ABS16SRC,E}, {PREFIXLDC,0x6,0xB,0x8,0x0,ABS16DST,IGNORE,IGNORE,IGNORE,E}EOP, - NEW_SOP(O(O_STC,SB),0,2,"stc"),{CCR,ABS32SRC,E}, {PREFIXLDC,0x6,0xB,0xA,0x0,DST|ABS32LIST,E}EOP, + NEW_SOP(O(O_STC,SB),0,2,"stc"),{{CCR,ABS16SRC,E}}, {{PREFIXLDC,0x6,0xB,0x8,0x0,ABS16DST,IGNORE,IGNORE,IGNORE,E}}EOP, + NEW_SOP(O(O_STC,SB),0,2,"stc"),{{CCR,ABS32SRC,E}}, {{PREFIXLDC,0x6,0xB,0xA,0x0,DST|ABS32LIST,E}}EOP, - NEW_SOP(O(O_STC,SB), 1,2,"stc"),{EXR,RD8,E},{ 0x0,0x2,0x1,RD8,E,0,0,0,0} EOP, + NEW_SOP(O(O_STC,SB), 1,2,"stc"),{{EXR,RD8,E}},{{ 0x0,0x2,0x1,RD8,E,0,0,0,0}} EOP, - NEW_SOP(O(O_STC,SB),0,2,"stc"),{EXR,RSIND,E}, {0x0,0x1,0x4,0x1,0x6,0x9,B31|RDIND,0x0,E} EOP, - NEW_SOP(O(O_STC,SB),0,2,"stc"),{EXR,DISP|DST|L_16,E},{0x0,0x1,0x4,0x1,0x6,0xF,B31|DISPREG,0,DST|DISP|L_16,IGNORE,IGNORE,IGNORE,E}EOP, - NEW_SOP(O(O_STC,SB),0,2,"stc"),{EXR,DISP|DST|L_32,E},{0x0,0x1,0x4,0x1,0x7,0x8,B30|DISPREG,0,0x6,0xB,0xA,0x0,DST|DISP32LIST,E}EOP, - NEW_SOP(O(O_STC,SB),0,2,"stc"),{EXR,RDDEC,E}, {0x0,0x1,0x4,0x1,0x6,0xD,B31|RDDEC,0x0,E}EOP, + NEW_SOP(O(O_STC,SB),0,2,"stc"),{{EXR,RSIND,E}}, {{0x0,0x1,0x4,0x1,0x6,0x9,B31|RDIND,0x0,E}} EOP, + NEW_SOP(O(O_STC,SB),0,2,"stc"),{{EXR,DISP|DST|L_16,E}},{{0x0,0x1,0x4,0x1,0x6,0xF,B31|DISPREG,0,DST|DISP|L_16,IGNORE,IGNORE,IGNORE,E}}EOP, + NEW_SOP(O(O_STC,SB),0,2,"stc"),{{EXR,DISP|DST|L_32,E}},{{0x0,0x1,0x4,0x1,0x7,0x8,B30|DISPREG,0,0x6,0xB,0xA,0x0,DST|DISP32LIST,E}}EOP, + NEW_SOP(O(O_STC,SB),0,2,"stc"),{{EXR,RDDEC,E}}, {{0x0,0x1,0x4,0x1,0x6,0xD,B31|RDDEC,0x0,E}}EOP, - NEW_SOP(O(O_STC,SB),0,2,"stc"),{EXR,ABS16SRC,E}, {0x0,0x1,0x4,0x1,0x6,0xB,0x8,0x0,ABS16DST,IGNORE,IGNORE,IGNORE,E}EOP, - NEW_SOP(O(O_STC,SB),0,2,"stc"),{EXR,ABS32SRC,E}, {0x0,0x1,0x4,0x1,0x6,0xB,0xA,0x0,DST|ABS32LIST,E}EOP, + NEW_SOP(O(O_STC,SB),0,2,"stc"),{{EXR,ABS16SRC,E}}, {{0x0,0x1,0x4,0x1,0x6,0xB,0x8,0x0,ABS16DST,IGNORE,IGNORE,IGNORE,E}}EOP, + NEW_SOP(O(O_STC,SB),0,2,"stc"),{{EXR,ABS32SRC,E}}, {{0x0,0x1,0x4,0x1,0x6,0xB,0xA,0x0,DST|ABS32LIST,E}}EOP, - SOP(O(O_SUB,SB),2,"sub.b"),{RS8,RD8,E},{ 0x1,0x8,RS8,RD8,E,0,0,0,0}EOP, + SOP(O(O_SUB,SB),2,"sub.b"),{{RS8,RD8,E}},{{ 0x1,0x8,RS8,RD8,E,0,0,0,0}}EOP, - NEW_SOP(O(O_SUB,SW),1,2,"sub.w"),{RS16,RD16,E }, {0x1,0x9,RS16,RD16,E} EOP, - NEW_SOP(O(O_SUB,SW),0,4,"sub.w"),{IMM16,RD16,E }, {0x7,0x9,0x3,RD16,IMM16,IGNORE,IGNORE,IGNORE,E} EOP, - NEW_SOP(O(O_SUB,SL),0,2,"sub.l") ,{RS32,RD32,E }, {0x1,0xA,B31|RS32,B30|RD32,E} EOP, - NEW_SOP(O(O_SUB,SL),0,6,"sub.l"), {IMM32,RD32,E },{0x7,0xA,0x3,B30|RD32,IMM32LIST,E} EOP, + NEW_SOP(O(O_SUB,SW),1,2,"sub.w"),{{RS16,RD16,E }}, {{0x1,0x9,RS16,RD16,E}} EOP, + NEW_SOP(O(O_SUB,SW),0,4,"sub.w"),{{IMM16,RD16,E }}, {{0x7,0x9,0x3,RD16,IMM16,IGNORE,IGNORE,IGNORE,E}} EOP, + NEW_SOP(O(O_SUB,SL),0,2,"sub.l") ,{{RS32,RD32,E }}, {{0x1,0xA,B31|RS32,B30|RD32,E}} EOP, + NEW_SOP(O(O_SUB,SL),0,6,"sub.l"), {{IMM32,RD32,E }},{{0x7,0xA,0x3,B30|RD32,IMM32LIST,E}} EOP, - SOP(O(O_SUBS,SL),2,"subs"),{KBIT,RDP,E},{ 0x1,0xB,KBIT,RDP,E,0,0,0,0}EOP, + SOP(O(O_SUBS,SL),2,"subs"),{{KBIT,RDP,E}},{{ 0x1,0xB,KBIT,RDP,E,0,0,0,0}}EOP, TWOOP(O(O_SUBX,SB),"subx",0xB,0x1,0xE), - NEW_SOP(O(O_TRAPA,SB),0,2,"trapa"),{ IMM2,E}, {0x5,0x7,IMM2,IGNORE,E }EOP, - NEW_SOP(O(O_TAS,SB),0,2,"tas"),{RSIND,E}, {0x0,0x1,0xe,0x0,0x7,0xb,B30|RSIND,0xc,E }EOP, + NEW_SOP(O(O_TRAPA,SB),0,2,"trapa"),{{ IMM2,E}}, {{0x5,0x7,IMM2,IGNORE,E }}EOP, + NEW_SOP(O(O_TAS,SB),0,2,"tas"),{{RSIND,E}}, {{0x0,0x1,0xe,0x0,0x7,0xb,B30|RSIND,0xc,E }}EOP, TWOOP(O(O_XOR, SB),"xor",0xD,0x1,0x5), - NEW_SOP(O(O_XOR,SW),0,4,"xor.w"),{IMM16,RD16,E },{0x7,0x9,0x5,RD16,IMM16,IGNORE,IGNORE,IGNORE,E} EOP, - NEW_SOP(O(O_XOR,SW),0,2,"xor.w"),{RS16,RD16,E },{0x6,0x5,RS16,RD16,E} EOP, + NEW_SOP(O(O_XOR,SW),0,4,"xor.w"),{{IMM16,RD16,E }},{{0x7,0x9,0x5,RD16,IMM16,IGNORE,IGNORE,IGNORE,E}} EOP, + NEW_SOP(O(O_XOR,SW),0,2,"xor.w"),{{RS16,RD16,E }},{{0x6,0x5,RS16,RD16,E}} EOP, - NEW_SOP(O(O_XOR,SL),0,6,"xor.l"),{IMM32,RD32,E },{0x7,0xA,0x5,B30|RD32,IMM32LIST,E} EOP, - NEW_SOP(O(O_XOR,SL),0,2,"xor.l") ,{RS32,RD32,E },{0x0,0x1,0xF,0x0,0x6,0x5,B30|RS32,B30|RD32,E} EOP, + NEW_SOP(O(O_XOR,SL),0,6,"xor.l"),{{IMM32,RD32,E }},{{0x7,0xA,0x5,B30|RD32,IMM32LIST,E}} EOP, + NEW_SOP(O(O_XOR,SL),0,2,"xor.l") ,{{RS32,RD32,E }},{{0x0,0x1,0xF,0x0,0x6,0x5,B30|RS32,B30|RD32,E}} EOP, - SOP(O(O_XORC,SB),2,"xorc"),{IMM8,CCR,E},{ 0x0,0x5,IMM8,IGNORE,E,0,0,0,0}EOP, - SOP(O(O_XORC,SB),2,"xorc"),{IMM8,EXR,E},{ 0x0,0x1,0x4,0x1,0x0,0x5,IMM8,IGNORE,E,0,0,0,0}EOP, + SOP(O(O_XORC,SB),2,"xorc"),{{IMM8,CCR,E}},{{ 0x0,0x5,IMM8,IGNORE,E,0,0,0,0}}EOP, + SOP(O(O_XORC,SB),2,"xorc"),{{IMM8,EXR,E}},{{ 0x0,0x1,0x4,0x1,0x0,0x5,IMM8,IGNORE,E,0,0,0,0}}EOP, - NEW_SOP(O(O_CLRMAC,SN),1,2,"clrmac"),{E, 0, 0},{0x0,0x1,0xa,0x0,E} EOP, - NEW_SOP(O(O_MAC,SL),1,2,"mac"),{RSINC,RDINC,E},{0x0,0x1,0x6,0x0,0x6,0xd,B30|RSINC,B30|RDINC,E} EOP, - NEW_SOP(O(O_LDMAC,SL),1,2,"ldmac"),{RS32,MACREG,E},{0x0,0x3,MACREG,RS32,E} EOP, - NEW_SOP(O(O_STMAC,SL),1,2,"stmac"),{MACREG,RD32,E},{0x0,0x2,MACREG,RD32,E} EOP, - NEW_SOP(O(O_LDM,SL),0,6,"ldm.l"),{RSINC, RS32, E},{ 0x0,0x1,IGNORE,0x0,0x6,0xD,0x7,IGNORE,E}EOP, - NEW_SOP(O(O_STM,SL),0,6,"stm.l"),{RS32, RDDEC, E},{0x0,0x1,IGNORE,0x0,0x6,0xD,0xF,IGNORE,E}EOP, - 0 + NEW_SOP(O(O_CLRMAC,SN),1,2,"clrmac"),{{E, 0, 0}},{{0x0,0x1,0xa,0x0,E}} EOP, + NEW_SOP(O(O_MAC,SL),1,2,"mac"),{{RSINC,RDINC,E}},{{0x0,0x1,0x6,0x0,0x6,0xd,B30|RSINC,B30|RDINC,E}} EOP, + NEW_SOP(O(O_LDMAC,SL),1,2,"ldmac"),{{RS32,MACREG,E}},{{0x0,0x3,MACREG,RS32,E}} EOP, + NEW_SOP(O(O_STMAC,SL),1,2,"stmac"),{{MACREG,RD32,E}},{{0x0,0x2,MACREG,RD32,E}} EOP, + NEW_SOP(O(O_LDM,SL),0,6,"ldm.l"),{{RSINC, RS32, E}},{{ 0x0,0x1,IGNORE,0x0,0x6,0xD,0x7,IGNORE,E}}EOP, + NEW_SOP(O(O_STM,SL),0,6,"stm.l"),{{RS32, RDDEC, E}},{{0x0,0x1,IGNORE,0x0,0x6,0xD,0xF,IGNORE,E}}EOP, + { 0 } }; #else extern struct h8_opcode h8_opcodes[] ; diff --git a/gnu/dist/include/opcode/m68k.h b/gnu/dist/include/opcode/m68k.h index a8c422d4677..4d27d7f7ffb 100644 --- a/gnu/dist/include/opcode/m68k.h +++ b/gnu/dist/include/opcode/m68k.h @@ -1,5 +1,5 @@ /* Opcode table header for m680[01234]0/m6888[12]/m68851. - Copyright 1989, 1991, 1992, 1993, 1994, 1995 Free Software Foundation. + Copyright 1989, 91, 92, 93, 94, 95, 96, 1997 Free Software Foundation. This file is part of GDB, GAS, and the GNU binutils. @@ -87,7 +87,7 @@ struct m68k_opcode_alias operand; the second, the place it is stored. */ /* Kinds of operands: - Characters used: AaBCcDdFfIJkLlMOQRrSsTtUVWXYZ0123|*~%;@!&$?/#^+- + Characters used: AaBCcDdFfIJkLlMmnOopQqRrSsTtUVvWXYZ0123|*~%;@!&$?/<>#^+- D data register only. Stored as 3 bits. A address register only. Stored as 3 bits. @@ -173,36 +173,39 @@ struct m68k_opcode_alias The remainder are all stored as 6 bits using an address mode and a register number; they differ in which addressing modes they match. - * all (modes 0-6,7.*) + * all (modes 0-6,7.0-4) ~ alterable memory (modes 2-6,7.0,7.1) - (not 0,1,7.~) + (not 0,1,7.2-4) % alterable (modes 0-6,7.0,7.1) - (not 7.~) - ; data (modes 0,2-6,7.*)(not 1) - @ data, but not immediate (modes 0,2-6,7.? ? ?) - (not 1,7.?) - This may really be ;, - the 68020 book says it is - ! control (modes 2,5,6,7.*-) + (not 7.2-4) + ; data (modes 0,2-6,7.0-4) + (not 1) + @ data, but not immediate (modes 0,2-6,7.0-3) + (not 1,7.4) + ! control (modes 2,5,6,7.0-3) (not 0,1,3,4,7.4) & alterable control (modes 2,5,6,7.0,7.1) - (not 0,1,7.? ? ?) + (not 0,1,7.2-4) $ alterable data (modes 0,2-6,7.0,7.1) - (not 1,7.~) + (not 1,7.2-4) ? alterable control, or data register (modes 0,2,5,6,7.0,7.1) - (not 1,3,4,7.~) - / control, or data register (modes 0,2,5,6,7.0,7.1,7.2,7.3) + (not 1,3,4,7.2-4) + / control, or data register (modes 0,2,5,6,7.0-3) (not 1,3,4,7.4) - ` control, plus pre-dec, not simple indir. (modes 4,5,6,7.*-) - (not 0,1,2,3,7.4) > *save operands (modes 2,4,5,6,7.0,7.1) - < *restore operands (modes 2,3,5,6,7.0,7.1,7.2,7.3) + (not 0,1,3,7.2-4) + < *restore operands (modes 2,3,5,6,7.0-3) + (not 0,1,4,7.4) coldfire move operands: m (modes 0-4) n (modes 5,7.2) - o (modes 6,7.0,7.1,7.3) + o (modes 6,7.0,7.1,7.3,7.4) p (modes 0-5) + + coldfire bset/bclr/btst operands: + q (modes 0,2-5) + v (modes 0,2-5,7.0,7.1) */ /* For the 68851: */ diff --git a/gnu/dist/include/opcode/mips.h b/gnu/dist/include/opcode/mips.h index 517aa096a8b..ee5ee82d3cb 100644 --- a/gnu/dist/include/opcode/mips.h +++ b/gnu/dist/include/opcode/mips.h @@ -120,7 +120,9 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * #define OP_SH_MMI 0 /* Multimedia (parallel) op */ #define OP_MASK_MMI 0x3f #define OP_SH_MMISUB 6 -#define OP_MASK_MMISUB 0x1f +#define OP_MASK_MMISUB 0x1f +#define OP_MASK_PERFREG 0x1f /* Performance monitoring */ +#define OP_SH_PERFREG 1 /* This structure holds information for a particular instruction. */ @@ -132,9 +134,7 @@ struct mips_opcode const char *args; /* The basic opcode for the instruction. When assembling, this opcode is modified by the arguments to produce the actual opcode - that is used. If pinfo is INSN_MACRO, then this is instead the - ISA level of the macro (0 or 1 is always supported, 2 is ISA 2, - etc.). */ + that is used. If pinfo is INSN_MACRO, then this is 0. */ unsigned long match; /* If pinfo is not INSN_MACRO, then this is a bit mask for the relevant portions of the opcode when disassembling. If the @@ -146,6 +146,9 @@ struct mips_opcode of bits describing the instruction, notably any relevant hazard information. */ unsigned long pinfo; + /* A collection of bits describing the instruction sets of which this + instruction or macro is a member. */ + unsigned long membership; }; /* These are the characters which may appears in the args field of an @@ -192,6 +195,7 @@ struct mips_opcode Coprocessor instructions: "E" 5 bit target register (OP_*_RT) "G" 5 bit destination register (OP_*_RD) + "P" 5 bit performance-monitor register (OP_*_PERFREG) Macro instructions: "A" General 32 bit expression @@ -200,6 +204,15 @@ struct mips_opcode "L" 64 bit floating point constant in .lit8 "f" 32 bit floating point constant "l" 32 bit floating point constant in .lit4 + + Other: + "()" parens surrounding optional value + "," separates operands + + Characters used so far, for quick reference when adding more: + "<>()," + "ABCDEFGILMNSTRVW" + "abcdfhijkloprstuvwxz" */ /* These are the bits which may be set in the pinfo field of an @@ -261,24 +274,45 @@ struct mips_opcode #define INSN_TRAP 0x04000000 /* Instruction stores value into memory. */ #define INSN_STORE_MEMORY 0x08000000 +/* Instruction uses single precision floating point. */ +#define FP_S 0x10000000 +/* Instruction uses double precision floating point. */ +#define FP_D 0x20000000 + +/* As yet unused bits: 0x40000000 */ + +/* Instruction is actually a macro. It should be ignored by the + disassembler, and requires special treatment by the assembler. */ +#define INSN_MACRO 0xffffffff + + + + + /* MIPS ISA field--CPU level at which insn is supported. */ -#define INSN_ISA 0x70000000 +#define INSN_ISA 0x0000000F +/* An instruction which is not part of any basic MIPS ISA. + (ie it is a chip specific instruction) */ +#define INSN_NO_ISA 0x00000000 +/* MIPS ISA 1 instruction. */ +#define INSN_ISA1 0x00000001 /* MIPS ISA 2 instruction (R6000 or R4000). */ -#define INSN_ISA2 0x10000000 +#define INSN_ISA2 0x00000002 /* MIPS ISA 3 instruction (R4000). */ -#define INSN_ISA3 0x20000000 -/* MIPS R4650 instruction. */ -#define INSN_4650 0x30000000 +#define INSN_ISA3 0x00000003 /* MIPS ISA 4 instruction (R8000). */ -#define INSN_ISA4 0x40000000 +#define INSN_ISA4 0x00000004 + +/* Chip specific instructions. These are bitmasks. */ +/* MIPS R4650 instruction. */ +#define INSN_4650 0x00000010 /* LSI R4010 instruction. */ -#define INSN_4010 0x50000000 +#define INSN_4010 0x00000020 /* NEC VR4100 instruction. */ -#define INSN_4100 0x60000000 +#define INSN_4100 0x00000040 +/* Toshiba R3900 instruction. */ +#define INSN_3900 0x00000080 -/* Instruction is actually a macro. It should be ignored by the - disassembler, and requires special treatment by the assembler. */ -#define INSN_MACRO 0xffffffff /* This is a list of macro expanded instructions. * diff --git a/gnu/dist/include/opcode/sparc.h b/gnu/dist/include/opcode/sparc.h index 79ca7586e84..4f159bd896f 100644 --- a/gnu/dist/include/opcode/sparc.h +++ b/gnu/dist/include/opcode/sparc.h @@ -183,6 +183,8 @@ Kinds of operands: * Prefetch function constant. (v9) x OPF field (v9 impdep). 0 32/64 bit immediate for set or setx (v9) insns + _ Ancillary state register in rd (v9a) + / Ancillary state register in rs1 (v9a) The following chars are unused: (note: ,[] are used as punctuation) [345] @@ -216,7 +218,7 @@ The following chars are unused: (note: ,[] are used as punctuation) #define RS1_G0 RS1(~0) #define RS2_G0 RS2(~0) -extern struct sparc_opcode sparc_opcodes[]; +extern const struct sparc_opcode sparc_opcodes[]; extern const int sparc_num_opcodes; extern int sparc_encode_asi PARAMS ((const char *)); diff --git a/gnu/dist/include/opcode/tic30.h b/gnu/dist/include/opcode/tic30.h new file mode 100644 index 00000000000..a7002759118 --- /dev/null +++ b/gnu/dist/include/opcode/tic30.h @@ -0,0 +1,691 @@ +/* tic30.h -- Header file for TI TMS320C30 opcode table + Copyright 1998 Free Software Foundation, Inc. + Contributed by Steven Haworth (steve@pm.cse.rmit.edu.au) + +This file is part of GDB, GAS, and the GNU binutils. + +GDB, GAS, and the GNU binutils are free software; you can redistribute +them and/or modify them under the terms of the GNU General Public +License as published by the Free Software Foundation; either version +1, or (at your option) any later version. + +GDB, GAS, and the GNU binutils are distributed in the hope that they +will be useful, but WITHOUT ANY WARRANTY; without even the implied +warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See +the GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this file; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ + +/* FIXME: The opcode table should be in opcodes/tic30-opc.c, not in a + header file. */ + +#ifndef _TMS320_H_ +#define _TMS320_H_ + +struct _register +{ + char *name; + unsigned char opcode; + unsigned char regtype; +}; + +typedef struct _register reg; + +#define REG_Rn 0x01 +#define REG_ARn 0x02 +#define REG_DP 0x03 +#define REG_OTHER 0x04 + +static const reg tic30_regtab[] = { + { "r0", 0x00, REG_Rn }, + { "r1", 0x01, REG_Rn }, + { "r2", 0x02, REG_Rn }, + { "r3", 0x03, REG_Rn }, + { "r4", 0x04, REG_Rn }, + { "r5", 0x05, REG_Rn }, + { "r6", 0x06, REG_Rn }, + { "r7", 0x07, REG_Rn }, + { "ar0",0x08, REG_ARn }, + { "ar1",0x09, REG_ARn }, + { "ar2",0x0A, REG_ARn }, + { "ar3",0x0B, REG_ARn }, + { "ar4",0x0C, REG_ARn }, + { "ar5",0x0D, REG_ARn }, + { "ar6",0x0E, REG_ARn }, + { "ar7",0x0F, REG_ARn }, + { "dp", 0x10, REG_DP }, + { "ir0",0x11, REG_OTHER }, + { "ir1",0x12, REG_OTHER }, + { "bk", 0x13, REG_OTHER }, + { "sp", 0x14, REG_OTHER }, + { "st", 0x15, REG_OTHER }, + { "ie", 0x16, REG_OTHER }, + { "if", 0x17, REG_OTHER }, + { "iof",0x18, REG_OTHER }, + { "rs", 0x19, REG_OTHER }, + { "re", 0x1A, REG_OTHER }, + { "rc", 0x1B, REG_OTHER }, + { "R0", 0x00, REG_Rn }, + { "R1", 0x01, REG_Rn }, + { "R2", 0x02, REG_Rn }, + { "R3", 0x03, REG_Rn }, + { "R4", 0x04, REG_Rn }, + { "R5", 0x05, REG_Rn }, + { "R6", 0x06, REG_Rn }, + { "R7", 0x07, REG_Rn }, + { "AR0",0x08, REG_ARn }, + { "AR1",0x09, REG_ARn }, + { "AR2",0x0A, REG_ARn }, + { "AR3",0x0B, REG_ARn }, + { "AR4",0x0C, REG_ARn }, + { "AR5",0x0D, REG_ARn }, + { "AR6",0x0E, REG_ARn }, + { "AR7",0x0F, REG_ARn }, + { "DP", 0x10, REG_DP }, + { "IR0",0x11, REG_OTHER }, + { "IR1",0x12, REG_OTHER }, + { "BK", 0x13, REG_OTHER }, + { "SP", 0x14, REG_OTHER }, + { "ST", 0x15, REG_OTHER }, + { "IE", 0x16, REG_OTHER }, + { "IF", 0x17, REG_OTHER }, + { "IOF",0x18, REG_OTHER }, + { "RS", 0x19, REG_OTHER }, + { "RE", 0x1A, REG_OTHER }, + { "RC", 0x1B, REG_OTHER }, + { "", 0, 0 } +}; + +static const reg *const tic30_regtab_end + = tic30_regtab + sizeof(tic30_regtab)/sizeof(tic30_regtab[0]); + +/* Indirect Addressing Modes Modification Fields */ +/* Indirect Addressing with Displacement */ +#define PreDisp_Add 0x00 +#define PreDisp_Sub 0x01 +#define PreDisp_Add_Mod 0x02 +#define PreDisp_Sub_Mod 0x03 +#define PostDisp_Add_Mod 0x04 +#define PostDisp_Sub_Mod 0x05 +#define PostDisp_Add_Circ 0x06 +#define PostDisp_Sub_Circ 0x07 +/* Indirect Addressing with Index Register IR0 */ +#define PreIR0_Add 0x08 +#define PreIR0_Sub 0x09 +#define PreIR0_Add_Mod 0x0A +#define PreIR0_Sub_Mod 0x0B +#define PostIR0_Add_Mod 0x0C +#define PostIR0_Sub_Mod 0x0D +#define PostIR0_Add_Circ 0x0E +#define PostIR0_Sub_Circ 0x0F +/* Indirect Addressing with Index Register IR1 */ +#define PreIR1_Add 0x10 +#define PreIR1_Sub 0x11 +#define PreIR1_Add_Mod 0x12 +#define PreIR1_Sub_Mod 0x13 +#define PostIR1_Add_Mod 0x14 +#define PostIR1_Sub_Mod 0x15 +#define PostIR1_Add_Circ 0x16 +#define PostIR1_Sub_Circ 0x17 +/* Indirect Addressing (Special Cases) */ +#define IndirectOnly 0x18 +#define PostIR0_Add_BitRev 0x19 + +typedef struct { + char *syntax; + unsigned char modfield; + unsigned char displacement; +} ind_addr_type; + +#define IMPLIED_DISP 0x01 +#define DISP_REQUIRED 0x02 +#define NO_DISP 0x03 + +static const ind_addr_type tic30_indaddr_tab[] = { + { "*+ar", PreDisp_Add, IMPLIED_DISP }, + { "*-ar", PreDisp_Sub, IMPLIED_DISP }, + { "*++ar", PreDisp_Add_Mod, IMPLIED_DISP }, + { "*--ar", PreDisp_Sub_Mod, IMPLIED_DISP }, + { "*ar++", PostDisp_Add_Mod, IMPLIED_DISP }, + { "*ar--", PostDisp_Sub_Mod, IMPLIED_DISP }, + { "*ar++%", PostDisp_Add_Circ, IMPLIED_DISP }, + { "*ar--%", PostDisp_Sub_Circ, IMPLIED_DISP }, + { "*+ar()", PreDisp_Add, DISP_REQUIRED }, + { "*-ar()", PreDisp_Sub, DISP_REQUIRED }, + { "*++ar()", PreDisp_Add_Mod, DISP_REQUIRED }, + { "*--ar()", PreDisp_Sub_Mod, DISP_REQUIRED }, + { "*ar++()", PostDisp_Add_Mod, DISP_REQUIRED }, + { "*ar--()", PostDisp_Sub_Mod, DISP_REQUIRED }, + { "*ar++()%", PostDisp_Add_Circ, DISP_REQUIRED }, + { "*ar--()%", PostDisp_Sub_Circ, DISP_REQUIRED }, + { "*+ar(ir0)", PreIR0_Add, NO_DISP }, + { "*-ar(ir0)", PreIR0_Sub, NO_DISP }, + { "*++ar(ir0)", PreIR0_Add_Mod, NO_DISP }, + { "*--ar(ir0)", PreIR0_Sub_Mod, NO_DISP }, + { "*ar++(ir0)", PostIR0_Add_Mod, NO_DISP }, + { "*ar--(ir0)", PostIR0_Sub_Mod, NO_DISP }, + { "*ar++(ir0)%",PostIR0_Add_Circ, NO_DISP }, + { "*ar--(ir0)%",PostIR0_Sub_Circ, NO_DISP }, + { "*+ar(ir1)", PreIR1_Add, NO_DISP }, + { "*-ar(ir1)", PreIR1_Sub, NO_DISP }, + { "*++ar(ir1)", PreIR1_Add_Mod, NO_DISP }, + { "*--ar(ir1)", PreIR1_Sub_Mod, NO_DISP }, + { "*ar++(ir1)", PostIR1_Add_Mod, NO_DISP }, + { "*ar--(ir1)", PostIR1_Sub_Mod, NO_DISP }, + { "*ar++(ir1)%",PostIR1_Add_Circ, NO_DISP }, + { "*ar--(ir1)%",PostIR1_Sub_Circ, NO_DISP }, + { "*ar", IndirectOnly, NO_DISP }, + { "*ar++(ir0)b",PostIR0_Add_BitRev, NO_DISP }, + { "", 0,0 } +}; + +static const ind_addr_type *const tic30_indaddrtab_end + = tic30_indaddr_tab + sizeof(tic30_indaddr_tab)/sizeof(tic30_indaddr_tab[0]); + +/* Possible operand types */ +/* Register types */ +#define Rn 0x0001 +#define ARn 0x0002 +#define DPReg 0x0004 +#define OtherReg 0x0008 +/* Addressing mode types */ +#define Direct 0x0010 +#define Indirect 0x0020 +#define Imm16 0x0040 +#define Disp 0x0080 +#define Imm24 0x0100 +#define Abs24 0x0200 +/* 3 operand addressing mode types */ +#define op3T1 0x0400 +#define op3T2 0x0800 +/* Interrupt vector */ +#define IVector 0x1000 +/* Not required */ +#define NotReq 0x2000 + +#define GAddr1 Rn | Direct | Indirect | Imm16 +#define GAddr2 GAddr1 | AllReg +#define TAddr1 op3T1 | Rn | Indirect +#define TAddr2 op3T2 | Rn | Indirect +#define Reg Rn | ARn +#define AllReg Reg | DPReg | OtherReg + +typedef struct _template +{ + char *name; + unsigned int operands; /* how many operands */ + unsigned int base_opcode; /* base_opcode is the fundamental opcode byte */ + /* the bits in opcode_modifier are used to generate the final opcode from + the base_opcode. These bits also are used to detect alternate forms of + the same instruction */ + unsigned int opcode_modifier; + + /* opcode_modifier bits: */ +#define AddressMode 0x00600000 +#define PCRel 0x02000000 +#define StackOp 0x001F0000 +#define Rotate StackOp + + /* operand_types[i] describes the type of operand i. This is made + by OR'ing together all of the possible type masks. (e.g. + 'operand_types[i] = Reg|Imm' specifies that operand i can be + either a register or an immediate operand */ + unsigned int operand_types[3]; + /* This defines the number type of an immediate argument to an instruction. */ + int imm_arg_type; +#define Imm_None 0 +#define Imm_Float 1 +#define Imm_SInt 2 +#define Imm_UInt 3 +} +template; + +static const template tic30_optab[] = { + { "absf" ,2,0x00000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "absi" ,2,0x00800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "addc" ,2,0x01000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "addc3" ,3,0x20000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, + { "addf" ,2,0x01800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "addf3" ,3,0x20800000,AddressMode, { TAddr1, TAddr2, Rn }, Imm_None }, + { "addi" ,2,0x02000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "addi3" ,3,0x21000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, + { "and" ,2,0x02800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt }, + { "and3" ,3,0x21800000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, + { "andn" ,2,0x03000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt }, + { "andn3" ,3,0x22000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, + { "ash" ,2,0x03800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ash3" ,3,0x22800000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, + { "b" ,1,0x68000000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bu" ,1,0x68000000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "blo" ,1,0x68010000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bls" ,1,0x68020000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bhi" ,1,0x68030000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bhs" ,1,0x68040000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "beq" ,1,0x68050000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bne" ,1,0x68060000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "blt" ,1,0x68070000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "ble" ,1,0x68080000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bgt" ,1,0x68090000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bge" ,1,0x680A0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bz" ,1,0x68050000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bnz" ,1,0x68060000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bp" ,1,0x68090000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bn" ,1,0x68070000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bnn" ,1,0x680A0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bnv" ,1,0x680C0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bv" ,1,0x680D0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bnuf" ,1,0x680E0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "buf" ,1,0x680F0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bnc" ,1,0x68040000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bc" ,1,0x68010000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bnlv" ,1,0x68100000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "blv" ,1,0x68110000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bnluf" ,1,0x68120000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bluf" ,1,0x68130000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bzuf" ,1,0x68140000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bd" ,1,0x68200000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bud" ,1,0x68200000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "blod" ,1,0x68210000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "blsd" ,1,0x68220000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bhid" ,1,0x68230000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bhsd" ,1,0x68240000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "beqd" ,1,0x68250000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bned" ,1,0x68260000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bltd" ,1,0x68270000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bled" ,1,0x68280000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bgtd" ,1,0x68290000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bged" ,1,0x682A0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bzd" ,1,0x68250000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bnzd" ,1,0x68260000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bpd" ,1,0x68290000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bnd" ,1,0x68270000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bnnd" ,1,0x682A0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bnvd" ,1,0x682C0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bvd" ,1,0x682D0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bnufd" ,1,0x682E0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bufd" ,1,0x682F0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bncd" ,1,0x68240000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bcd" ,1,0x68210000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bnlvd" ,1,0x68300000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "blvd" ,1,0x68310000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bnlufd" ,1,0x68320000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "blufd" ,1,0x68330000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bzufd" ,1,0x68340000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "br" ,1,0x60000000,0, { Imm24, 0, 0 }, Imm_UInt }, + { "brd" ,1,0x61000000,0, { Imm24, 0, 0 }, Imm_UInt }, + { "call" ,1,0x62000000,0, { Imm24, 0, 0 }, Imm_UInt }, + { "callu" ,1,0x70000000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "calllo" ,1,0x70010000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callls" ,1,0x70020000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callhi" ,1,0x70030000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callhs" ,1,0x70040000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "calleq" ,1,0x70050000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callne" ,1,0x70060000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "calllt" ,1,0x70070000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callle" ,1,0x70080000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callgt" ,1,0x70090000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callge" ,1,0x700A0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callz" ,1,0x70050000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callnz" ,1,0x70060000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callp" ,1,0x70090000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "calln" ,1,0x70070000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callnn" ,1,0x700A0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callnv" ,1,0x700C0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callv" ,1,0x700D0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callnuf",1,0x700E0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "calluf" ,1,0x700F0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callnc" ,1,0x70040000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callc" ,1,0x70010000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callnlv",1,0x70100000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "calllv" ,1,0x70110000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callnluf",1,0x70120000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callluf",1,0x70130000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callzuf",1,0x70140000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "cmpf" ,2,0x04000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "cmpf3" ,2,0x23000000,AddressMode, { TAddr1, TAddr2, 0 }, Imm_None }, + { "cmpi" ,2,0x04800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "cmpi3" ,2,0x23800000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, 0 }, Imm_None }, + { "db" ,2,0x6C000000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbu" ,2,0x6C000000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dblo" ,2,0x6C010000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbls" ,2,0x6C020000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbhi" ,2,0x6C030000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbhs" ,2,0x6C040000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbeq" ,2,0x6C050000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbne" ,2,0x6C060000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dblt" ,2,0x6C070000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dble" ,2,0x6C080000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbgt" ,2,0x6C090000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbge" ,2,0x6C0A0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbz" ,2,0x6C050000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbnz" ,2,0x6C060000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbp" ,2,0x6C090000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbn" ,2,0x6C070000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbnn" ,2,0x6C0A0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbnv" ,2,0x6C0C0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbv" ,2,0x6C0D0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbnuf" ,2,0x6C0E0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbuf" ,2,0x6C0F0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbnc" ,2,0x6C040000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbc" ,2,0x6C010000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbnlv" ,2,0x6C100000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dblv" ,2,0x6C110000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbnluf" ,2,0x6C120000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbluf" ,2,0x6C130000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbzuf" ,2,0x6C140000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbd" ,2,0x6C200000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbud" ,2,0x6C200000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dblod" ,2,0x6C210000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dblsd" ,2,0x6C220000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbhid" ,2,0x6C230000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbhsd" ,2,0x6C240000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbeqd" ,2,0x6C250000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbned" ,2,0x6C260000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbltd" ,2,0x6C270000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbled" ,2,0x6C280000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbgtd" ,2,0x6C290000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbged" ,2,0x6C2A0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbzd" ,2,0x6C250000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbnzd" ,2,0x6C260000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbpd" ,2,0x6C290000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbnd" ,2,0x6C270000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbnnd" ,2,0x6C2A0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbnvd" ,2,0x6C2C0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbvd" ,2,0x6C2D0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbnufd" ,2,0x6C2E0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbufd" ,2,0x6C2F0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbncd" ,2,0x6C240000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbcd" ,2,0x6C210000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbnlvd" ,2,0x6C300000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dblvd" ,2,0x6C310000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbnlufd",2,0x6C320000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dblufd" ,2,0x6C330000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbzufd" ,2,0x6C340000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "fix" ,2,0x05000000,AddressMode, { GAddr1, AllReg, 0 }, Imm_Float }, + { "float" ,2,0x05800000,AddressMode, { GAddr2, Rn, 0 }, Imm_SInt }, + { "iack" ,1,0x1B000000,AddressMode, { Direct|Indirect, 0, 0 }, Imm_None }, + { "idle" ,0,0x06000000,0, { 0, 0, 0 }, Imm_None }, + { "idle2" ,0,0x06000001,0, { 0, 0, 0 }, Imm_None }, /* LC31 Only */ + { "lde" ,2,0x06800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldf" ,2,0x07000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfu" ,2,0x40000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldflo" ,2,0x40800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfls" ,2,0x41000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfhi" ,2,0x41800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfhs" ,2,0x42000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfeq" ,2,0x42800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfne" ,2,0x43000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldflt" ,2,0x43800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfle" ,2,0x44000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfgt" ,2,0x44800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfge" ,2,0x45000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfz" ,2,0x42800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfnz" ,2,0x43000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfp" ,2,0x44800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfn" ,2,0x43800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfnn" ,2,0x45000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfnv" ,2,0x46000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfv" ,2,0x46800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfnuf" ,2,0x47000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfuf" ,2,0x47800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfnc" ,2,0x42000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfc" ,2,0x40800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfnlv" ,2,0x48000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldflv" ,2,0x48800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfnluf",2,0x49000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfluf" ,2,0x49800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfzuf" ,2,0x4A000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfi" ,2,0x07800000,AddressMode, { Direct|Indirect, Rn, 0 }, Imm_None }, + { "ldi" ,2,0x08000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldiu" ,2,0x50000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldilo" ,2,0x50800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldils" ,2,0x51000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldihi" ,2,0x51800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldihs" ,2,0x52000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldieq" ,2,0x52800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldine" ,2,0x53000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldilt" ,2,0x53800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldile" ,2,0x54000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldigt" ,2,0x54800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldige" ,2,0x55000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldiz" ,2,0x52800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldinz" ,2,0x53000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldip" ,2,0x54800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldin" ,2,0x53800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldinn" ,2,0x55000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldinv" ,2,0x56000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldiv" ,2,0x56800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldinuf" ,2,0x57000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldiuf" ,2,0x57800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldinc" ,2,0x52000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldic" ,2,0x50800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldinlv" ,2,0x58000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldilv" ,2,0x58800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldinluf",2,0x59000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldiluf" ,2,0x59800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldizuf" ,2,0x5A000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldii" ,2,0x08800000,AddressMode, { Direct|Indirect, AllReg, 0 }, Imm_None }, + { "ldm" ,2,0x09000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldp" ,2,0x08700000,0, { Abs24|Direct, DPReg|NotReq, 0 }, Imm_UInt }, + { "lopower",0,0x10800001,0, { 0, 0, 0 }, Imm_None }, /* LC31 Only */ + { "lsh" ,2,0x09800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt }, + { "lsh3" ,3,0x24000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, + { "maxspeed",0,0x10800000,0, { 0, 0, 0 }, Imm_None }, /* LC31 Only */ + { "mpyf" ,2,0x0A000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "mpyf3" ,3,0x24800000,AddressMode, { TAddr1, TAddr2, Rn }, Imm_None }, + { "mpyi" ,2,0x0A800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "mpyi3" ,3,0x25000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, + { "negb" ,2,0x0B000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "negf" ,2,0x0B800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "negi" ,2,0x0C000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "nop" ,1,0x0C800000,AddressMode, { AllReg|Indirect|NotReq, 0, 0 }, Imm_None }, + { "norm" ,2,0x0D000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, /*Check another source*/ + { "not" ,2,0x0D800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt }, + { "or" ,2,0x10000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt }, + { "or3" ,3,0x25800000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, + { "pop" ,1,0x0E200000,StackOp, { AllReg, 0, 0 }, Imm_None }, + { "popf" ,1,0x0EA00000,StackOp, { Rn, 0, 0 }, Imm_None }, + { "push" ,1,0x0F200000,StackOp, { AllReg, 0, 0 }, Imm_None }, + { "pushf" ,1,0x0FA00000,StackOp, { Rn, 0, 0 }, Imm_None }, + { "reti" ,0,0x78000000,0, { 0, 0, 0 }, Imm_None }, + { "retiu" ,0,0x78000000,0, { 0, 0, 0 }, Imm_None }, + { "retilo" ,0,0x78010000,0, { 0, 0, 0 }, Imm_None }, + { "retils" ,0,0x78020000,0, { 0, 0, 0 }, Imm_None }, + { "retihi" ,0,0x78030000,0, { 0, 0, 0 }, Imm_None }, + { "retihs" ,0,0x78040000,0, { 0, 0, 0 }, Imm_None }, + { "retieq" ,0,0x78050000,0, { 0, 0, 0 }, Imm_None }, + { "retine" ,0,0x78060000,0, { 0, 0, 0 }, Imm_None }, + { "retilt" ,0,0x78070000,0, { 0, 0, 0 }, Imm_None }, + { "retile" ,0,0x78080000,0, { 0, 0, 0 }, Imm_None }, + { "retigt" ,0,0x78090000,0, { 0, 0, 0 }, Imm_None }, + { "retige" ,0,0x780A0000,0, { 0, 0, 0 }, Imm_None }, + { "retiz" ,0,0x78050000,0, { 0, 0, 0 }, Imm_None }, + { "retinz" ,0,0x78060000,0, { 0, 0, 0 }, Imm_None }, + { "retip" ,0,0x78090000,0, { 0, 0, 0 }, Imm_None }, + { "retin" ,0,0x78070000,0, { 0, 0, 0 }, Imm_None }, + { "retinn" ,0,0x780A0000,0, { 0, 0, 0 }, Imm_None }, + { "retinv" ,0,0x780C0000,0, { 0, 0, 0 }, Imm_None }, + { "retiv" ,0,0x780D0000,0, { 0, 0, 0 }, Imm_None }, + { "retinuf",0,0x780E0000,0, { 0, 0, 0 }, Imm_None }, + { "retiuf" ,0,0x780F0000,0, { 0, 0, 0 }, Imm_None }, + { "retinc" ,0,0x78040000,0, { 0, 0, 0 }, Imm_None }, + { "retic" ,0,0x78010000,0, { 0, 0, 0 }, Imm_None }, + { "retinlv",0,0x78100000,0, { 0, 0, 0 }, Imm_None }, + { "retilv" ,0,0x78110000,0, { 0, 0, 0 }, Imm_None }, + { "retinluf",0,0x78120000,0, { 0, 0, 0 }, Imm_None }, + { "retiluf",0,0x78130000,0, { 0, 0, 0 }, Imm_None }, + { "retizuf",0,0x78140000,0, { 0, 0, 0 }, Imm_None }, + { "rets" ,0,0x78800000,0, { 0, 0, 0 }, Imm_None }, + { "retsu" ,0,0x78800000,0, { 0, 0, 0 }, Imm_None }, + { "retslo" ,0,0x78810000,0, { 0, 0, 0 }, Imm_None }, + { "retsls" ,0,0x78820000,0, { 0, 0, 0 }, Imm_None }, + { "retshi" ,0,0x78830000,0, { 0, 0, 0 }, Imm_None }, + { "retshs" ,0,0x78840000,0, { 0, 0, 0 }, Imm_None }, + { "retseq" ,0,0x78850000,0, { 0, 0, 0 }, Imm_None }, + { "retsne" ,0,0x78860000,0, { 0, 0, 0 }, Imm_None }, + { "retslt" ,0,0x78870000,0, { 0, 0, 0 }, Imm_None }, + { "retsle" ,0,0x78880000,0, { 0, 0, 0 }, Imm_None }, + { "retsgt" ,0,0x78890000,0, { 0, 0, 0 }, Imm_None }, + { "retsge" ,0,0x788A0000,0, { 0, 0, 0 }, Imm_None }, + { "retsz" ,0,0x78850000,0, { 0, 0, 0 }, Imm_None }, + { "retsnz" ,0,0x78860000,0, { 0, 0, 0 }, Imm_None }, + { "retsp" ,0,0x78890000,0, { 0, 0, 0 }, Imm_None }, + { "retsn" ,0,0x78870000,0, { 0, 0, 0 }, Imm_None }, + { "retsnn" ,0,0x788A0000,0, { 0, 0, 0 }, Imm_None }, + { "retsnv" ,0,0x788C0000,0, { 0, 0, 0 }, Imm_None }, + { "retsv" ,0,0x788D0000,0, { 0, 0, 0 }, Imm_None }, + { "retsnuf",0,0x788E0000,0, { 0, 0, 0 }, Imm_None }, + { "retsuf" ,0,0x788F0000,0, { 0, 0, 0 }, Imm_None }, + { "retsnc" ,0,0x78840000,0, { 0, 0, 0 }, Imm_None }, + { "retsc" ,0,0x78810000,0, { 0, 0, 0 }, Imm_None }, + { "retsnlv",0,0x78900000,0, { 0, 0, 0 }, Imm_None }, + { "retslv" ,0,0x78910000,0, { 0, 0, 0 }, Imm_None }, + { "retsnluf",0,0x78920000,0, { 0, 0, 0 }, Imm_None }, + { "retsluf",0,0x78930000,0, { 0, 0, 0 }, Imm_None }, + { "retszuf",0,0x78940000,0, { 0, 0, 0 }, Imm_None }, + { "rnd" ,2,0x11000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "rol" ,1,0x11E00001,Rotate, { AllReg, 0, 0 }, Imm_None }, + { "rolc" ,1,0x12600001,Rotate, { AllReg, 0, 0 }, Imm_None }, + { "ror" ,1,0x12E0FFFF,Rotate, { AllReg, 0, 0 }, Imm_None }, + { "rorc" ,1,0x1360FFFF,Rotate, { AllReg, 0, 0 }, Imm_None }, + { "rptb" ,1,0x64000000,0, { Imm24, 0, 0 }, Imm_UInt }, + { "rpts" ,1,0x139B0000,AddressMode, { GAddr2, 0, 0 }, Imm_UInt }, + { "sigi" ,0,0x16000000,0, { 0, 0, 0 }, Imm_None }, + { "stf" ,2,0x14000000,AddressMode, { Rn, Direct|Indirect, 0 }, Imm_Float }, + { "stfi" ,2,0x14800000,AddressMode, { Rn, Direct|Indirect, 0 }, Imm_Float }, + { "sti" ,2,0x15000000,AddressMode, { AllReg, Direct|Indirect, 0 }, Imm_SInt }, + { "stii" ,2,0x15800000,AddressMode, { AllReg, Direct|Indirect, 0 }, Imm_SInt }, + { "subb" ,2,0x16800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "subb3" ,3,0x26000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, + { "subc" ,2,0x17000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt }, + { "subf" ,2,0x17800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "subf3" ,3,0x26800000,AddressMode, { TAddr1, TAddr2, Rn }, Imm_None }, + { "subi" ,2,0x18000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "subi3" ,3,0x27000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, + { "subrb" ,2,0x18800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "subrf" ,2,0x19000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "subri" ,2,0x19800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "swi" ,0,0x66000000,0, { 0, 0, 0 }, Imm_None }, + { "trap" ,1,0x74800020,0, { IVector, 0, 0 }, Imm_None }, + { "trapu" ,1,0x74800020,0, { IVector, 0, 0 }, Imm_None }, + { "traplo" ,1,0x74810020,0, { IVector, 0, 0 }, Imm_None }, + { "trapls" ,1,0x74820020,0, { IVector, 0, 0 }, Imm_None }, + { "traphi" ,1,0x74830020,0, { IVector, 0, 0 }, Imm_None }, + { "traphs" ,1,0x74840020,0, { IVector, 0, 0 }, Imm_None }, + { "trapeq" ,1,0x74850020,0, { IVector, 0, 0 }, Imm_None }, + { "trapne" ,1,0x74860020,0, { IVector, 0, 0 }, Imm_None }, + { "traplt" ,1,0x74870020,0, { IVector, 0, 0 }, Imm_None }, + { "traple" ,1,0x74880020,0, { IVector, 0, 0 }, Imm_None }, + { "trapgt" ,1,0x74890020,0, { IVector, 0, 0 }, Imm_None }, + { "trapge" ,1,0x748A0020,0, { IVector, 0, 0 }, Imm_None }, + { "trapz" ,1,0x74850020,0, { IVector, 0, 0 }, Imm_None }, + { "trapnz" ,1,0x74860020,0, { IVector, 0, 0 }, Imm_None }, + { "trapp" ,1,0x74890020,0, { IVector, 0, 0 }, Imm_None }, + { "trapn" ,1,0x74870020,0, { IVector, 0, 0 }, Imm_None }, + { "trapnn" ,1,0x748A0020,0, { IVector, 0, 0 }, Imm_None }, + { "trapnv" ,1,0x748C0020,0, { IVector, 0, 0 }, Imm_None }, + { "trapv" ,1,0x748D0020,0, { IVector, 0, 0 }, Imm_None }, + { "trapnuf",1,0x748E0020,0, { IVector, 0, 0 }, Imm_None }, + { "trapuf" ,1,0x748F0020,0, { IVector, 0, 0 }, Imm_None }, + { "trapnc" ,1,0x74840020,0, { IVector, 0, 0 }, Imm_None }, + { "trapc" ,1,0x74810020,0, { IVector, 0, 0 }, Imm_None }, + { "trapnlv",1,0x74900020,0, { IVector, 0, 0 }, Imm_None }, + { "traplv" ,1,0x74910020,0, { IVector, 0, 0 }, Imm_None }, + { "trapnluf",1,0x74920020,0, { IVector, 0, 0 }, Imm_None }, + { "trapluf",1,0x74930020,0, { IVector, 0, 0 }, Imm_None }, + { "trapzuf",1,0x74940020,0, { IVector, 0, 0 }, Imm_None }, + { "tstb" ,2,0x1A000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt }, + { "tstb3" ,2,0x27800000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, 0 }, Imm_None }, + { "xor" ,2,0x1A800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt }, + { "xor3" ,3,0x28000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, + { "" ,0,0x00000000,0, { 0, 0, 0 }, 0 } +}; + +static const template *const tic30_optab_end = + tic30_optab + sizeof(tic30_optab)/sizeof(tic30_optab[0]); + +typedef struct { + char *name; + unsigned int operands_1; + unsigned int operands_2; + unsigned int base_opcode; + unsigned int operand_types[2][3]; + /* Which operand fits into which part of the final opcode word. */ + int oporder; +} partemplate; + +/* oporder defines - not very descriptive. */ +#define OO_4op1 0 +#define OO_4op2 1 +#define OO_4op3 2 +#define OO_5op1 3 +#define OO_5op2 4 +#define OO_PField 5 + +static const partemplate tic30_paroptab[] = { + { "q_absf_stf", 2,2,0xC8000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } }, + OO_4op1 }, + { "q_absi_sti", 2,2,0xCA000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } }, + OO_4op1 }, + { "q_addf3_stf", 3,2,0xCC000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } }, + OO_5op1 }, + { "q_addi3_sti", 3,2,0xCE000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } }, + OO_5op1 }, + { "q_and3_sti", 3,2,0xD0000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } }, + OO_5op1 }, + { "q_ash3_sti", 3,2,0xD2000000, { { Rn, Indirect, Rn }, { Rn, Indirect, 0 } }, + OO_5op2 }, + { "q_fix_sti", 2,2,0xD4000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } }, + OO_4op1 }, + { "q_float_stf", 2,2,0xD6000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } }, + OO_4op1 }, + { "q_ldf_ldf", 2,2,0xC4000000, { { Indirect, Rn, 0 }, { Indirect, Rn, 0 } }, + OO_4op2 }, + { "q_ldf_stf", 2,2,0xD8000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } }, + OO_4op1 }, + { "q_ldi_ldi", 2,2,0xC6000000, { { Indirect, Rn, 0 }, { Indirect, Rn, 0 } }, + OO_4op2 }, + { "q_ldi_sti", 2,2,0xDA000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } }, + OO_4op1 }, + { "q_lsh3_sti", 3,2,0xDC000000, { { Rn, Indirect, Rn }, { Rn, Indirect, 0 } }, + OO_5op2 }, + { "q_mpyf3_addf3",3,3,0x80000000, { { Rn | Indirect, Rn | Indirect, Rn }, + { Rn | Indirect, Rn | Indirect, Rn } }, OO_PField }, + { "q_mpyf3_stf", 3,2,0xDE000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } }, + OO_5op1 }, + { "q_mpyf3_subf3",3,3,0x84000000, { { Rn | Indirect, Rn | Indirect, Rn }, + { Rn | Indirect, Rn | Indirect, Rn } }, OO_PField }, + { "q_mpyi3_addi3",3,3,0x88000000, { { Rn | Indirect, Rn | Indirect, Rn }, + { Rn | Indirect, Rn | Indirect, Rn } }, OO_PField }, + { "q_mpyi3_sti", 3,2,0xE0000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } }, + OO_5op1 }, + { "q_mpyi3_subi3",3,3,0x8C000000, { { Rn | Indirect, Rn | Indirect, Rn }, + { Rn | Indirect, Rn | Indirect, Rn } }, OO_PField }, + { "q_negf_stf", 2,2,0xE2000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } }, + OO_4op1 }, + { "q_negi_sti", 2,2,0xE4000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } }, + OO_4op1 }, + { "q_not_sti", 2,2,0xE6000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } }, + OO_4op1 }, + { "q_or3_sti", 3,2,0xE8000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } }, + OO_5op1 }, + { "q_stf_stf", 2,2,0xC0000000, { { Rn, Indirect, 0 }, { Rn, Indirect, 0 } }, + OO_4op3 }, + { "q_sti_sti", 2,2,0xC2000000, { { Rn, Indirect, 0 }, { Rn, Indirect, 0 } }, + OO_4op3 }, + { "q_subf3_stf", 3,2,0xEA000000, { { Rn, Indirect, Rn }, { Rn, Indirect, 0 } }, + OO_5op2 }, + { "q_subi3_sti", 3,2,0xEC000000, { { Rn, Indirect, Rn }, { Rn, Indirect, 0 } }, + OO_5op2 }, + { "q_xor3_sti", 3,2,0xEE000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } }, + OO_5op1 }, + { "", 0,0,0x00000000, { { 0, 0, 0 }, { 0, 0, 0 } }, 0 } +}; + +static const partemplate *const tic30_paroptab_end = + tic30_paroptab + sizeof(tic30_paroptab)/sizeof(tic30_paroptab[0]); + +#endif diff --git a/gnu/dist/include/opcode/v850.h b/gnu/dist/include/opcode/v850.h new file mode 100644 index 00000000000..0c10adeb84b --- /dev/null +++ b/gnu/dist/include/opcode/v850.h @@ -0,0 +1,154 @@ +/* v850.h -- Header file for NEC V850 opcode table + Copyright 1996 Free Software Foundation, Inc. + Written by J.T. Conklin, Cygnus Support + +This file is part of GDB, GAS, and the GNU binutils. + +GDB, GAS, and the GNU binutils are free software; you can redistribute +them and/or modify them under the terms of the GNU General Public +License as published by the Free Software Foundation; either version +1, or (at your option) any later version. + +GDB, GAS, and the GNU binutils are distributed in the hope that they +will be useful, but WITHOUT ANY WARRANTY; without even the implied +warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See +the GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this file; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef V850_H +#define V850_H + +/* The opcode table is an array of struct v850_opcode. */ + +struct v850_opcode +{ + /* The opcode name. */ + const char *name; + + /* The opcode itself. Those bits which will be filled in with + operands are zeroes. */ + unsigned long opcode; + + /* The opcode mask. This is used by the disassembler. This is a + mask containing ones indicating those bits which must match the + opcode field, and zeroes indicating those bits which need not + match (and are presumably filled in by operands). */ + unsigned long mask; + + /* An array of operand codes. Each code is an index into the + operand table. They appear in the order which the operands must + appear in assembly code, and are terminated by a zero. */ + unsigned char operands[8]; + + /* Which (if any) operand is a memory operand. */ + unsigned int memop; + + /* Target processor(s). A bit field of processors which support + this instruction. Note a bit field is used as some instructions + are available on multiple, different processor types, whereas + other instructions are only available on one specific type. */ + unsigned int processors; +}; + +/* Values for the processors field in the v850_opcode structure. */ +#define PROCESSOR_V850 (1 << 0) /* Just the V850. */ +#define PROCESSOR_ALL -1 /* Any processor. */ + +/* The table itself is sorted by major opcode number, and is otherwise + in the order in which the disassembler should consider + instructions. */ +extern const struct v850_opcode v850_opcodes[]; +extern const int v850_num_opcodes; + + +/* The operands table is an array of struct v850_operand. */ + +struct v850_operand +{ + /* The number of bits in the operand. */ + /* If this value is -1 then the operand's bits are in a discontinous distribution in the instruction. */ + int bits; + + /* (bits >= 0): How far the operand is left shifted in the instruction. */ + /* (bits == -1): Bit mask of the bits in the operand. */ + int shift; + + /* Insertion function. This is used by the assembler. To insert an + operand value into an instruction, check this field. + + If it is NULL, execute + i |= (op & ((1 << o->bits) - 1)) << o->shift; + (i is the instruction which we are filling in, o is a pointer to + this structure, and op is the opcode value; this assumes twos + complement arithmetic). + + If this field is not NULL, then simply call it with the + instruction and the operand value. It will return the new value + of the instruction. If the ERRMSG argument is not NULL, then if + the operand value is illegal, *ERRMSG will be set to a warning + string (the operand will be inserted in any case). If the + operand value is legal, *ERRMSG will be unchanged (most operands + can accept any value). */ + unsigned long (* insert) PARAMS ((unsigned long instruction, long op, + const char ** errmsg)); + + /* Extraction function. This is used by the disassembler. To + extract this operand type from an instruction, check this field. + + If it is NULL, compute + op = o->bits == -1 ? ((i) & o->shift) : ((i) >> o->shift) & ((1 << o->bits) - 1); + if (o->flags & V850_OPERAND_SIGNED) + op = (op << (32 - o->bits)) >> (32 - o->bits); + (i is the instruction, o is a pointer to this structure, and op + is the result; this assumes twos complement arithmetic). + + If this field is not NULL, then simply call it with the + instruction value. It will return the value of the operand. If + the INVALID argument is not NULL, *INVALID will be set to + non-zero if this operand type can not actually be extracted from + this operand (i.e., the instruction does not match). If the + operand is valid, *INVALID will not be changed. */ + unsigned long (* extract) PARAMS ((unsigned long instruction, int * invalid)); + + /* One bit syntax flags. */ + int flags; +}; + +/* Elements in the table are retrieved by indexing with values from + the operands field of the v850_opcodes table. */ + +extern const struct v850_operand v850_operands[]; + +/* Values defined for the flags field of a struct v850_operand. */ + +/* This operand names a general purpose register */ +#define V850_OPERAND_REG 0x01 + +/* This operand names a system register */ +#define V850_OPERAND_SRG 0x02 + +/* This operand names a condition code used in the setf instruction */ +#define V850_OPERAND_CC 0x04 + +/* This operand takes signed values */ +#define V850_OPERAND_SIGNED 0x08 + +/* This operand is the ep register. */ +#define V850_OPERAND_EP 0x10 + +/* This operand is a PC displacement */ +#define V850_OPERAND_DISP 0x20 + +/* This is a relaxable operand. Only used for D9->D22 branch relaxing + right now. We may need others in the future (or maybe handle them like + promoted operands on the mn10300?) */ +#define V850_OPERAND_RELAX 0x40 + +/* The register specified must not be r0 */ +#define V850_NOT_R0 0x80 + + +#endif /* V850_H */ |
