diff options
| author | mrg <mrg@NetBSD.org> | 2003-03-01 10:06:40 +0000 |
|---|---|---|
| committer | mrg <mrg@NetBSD.org> | 2003-03-01 10:06:40 +0000 |
| commit | ee06049914f7d60076c9eb4cee2d8fcf30a8eb8c (patch) | |
| tree | 3be2cd5598f559cc3eece358dc41662b15813788 /gnu/dist/toolchain/include/opcode | |
| parent | ddb9465f5fd2b174e59c55db790a491cc6ff8d3f (diff) | |
import of (most of) binutils 2.13.2.1. no top level, and cut down include/
libiberty. (gcc update later can update libiberty properly.)
Diffstat (limited to 'gnu/dist/toolchain/include/opcode')
24 files changed, 1900 insertions, 626 deletions
diff --git a/gnu/dist/toolchain/include/opcode/ChangeLog b/gnu/dist/toolchain/include/opcode/ChangeLog index 9e40d0ce9ac..385b1915298 100644 --- a/gnu/dist/toolchain/include/opcode/ChangeLog +++ b/gnu/dist/toolchain/include/opcode/ChangeLog @@ -1,26 +1,249 @@ -2001-06-11 Alan Modra <amodra@bigpond.net.au> +2002-07-09 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de> - Merge from mainline. - 2001-05-23 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de> - * mips.h (CPU_R12000): Define. + * mips.h (INSN_MIPS16): New define. - 2001-05-15 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de> - * mips.h (INSN_ISA_MASK): Define. +2002-07-08 Alan Modra <amodra@bigpond.net.au> - 2001-03-21 Kazu Hirata <kazu@hxi.com> - * h8300.h: Fix formatting. + * i386.h: Remove IgnoreSize from movsx and movzx. - 2001-02-28 Igor Shevlyakov <igor@windriver.com> - * m68k.h: new defines for Coldfire V4. Update mcf to know - about mcf5407. +2002-06-08 Alan Modra <amodra@bigpond.net.au> - 2001-02-10 Nick Clifton <nickc@redhat.com> - * mips.h: Remove extraneous whitespace. Formating change to allow - for future contribution. + * a29k.h: Replace CONST with const. + (CONST): Don't define. + * convex.h: Replace CONST with const. + (CONST): Don't define. + * dlx.h: Replace CONST with const. + * or32.h (CONST): Don't define. + +2002-05-30 Chris G. Demetriou <cgd@broadcom.com> + + * mips.h (OP_SH_ALN, OP_MASK_ALN, OP_SH_VSEL, OP_MASK_VSEL) + (MDMX_FMTSEL_IMM_QH, MDMX_FMTSEL_IMM_OB, MDMX_FMTSEL_VEC_QH) + (MDMX_FMTSEL_VEC_OB, INSN_READ_MDMX_ACC, INSN_WRITE_MDMX_ACC) + (INSN_MDMX): New constants, for MDMX support. + (opcode character list): Add "O", "Q", "X", "Y", and "Z" for MDMX. + +2002-05-28 Kuang Hwa Lin <kuang@sbcglobal.net> + + * dlx.h: New file. + +2002-05-25 Alan Modra <amodra@bigpond.net.au> + + * ia64.h: Use #include "" instead of <> for local header files. + * sparc.h: Likewise. + +2002-05-22 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de> + + * mips.h: Add M_DROL, M_DROL_I, M_DROR, M_DROR_I macro cases. + +2002-05-17 Andrey Volkov <avolkov@sources.redhat.com> + + * h8300.h: Corrected defs of all control regs + and eepmov instr. + +2002-04-11 Alan Modra <amodra@bigpond.net.au> + + * i386.h: Add intel mode cmpsd and movsd. + Put them before SSE2 insns, so that rep prefix works. + +2002-03-15 Chris G. Demetriou <cgd@broadcom.com> + + * mips.h (INSN_MIPS3D): New definition used to mark MIPS-3D + instructions. + (OPCODE_IS_MEMBER): Adjust comments to indicate that ASE bit masks + may be passed along with the ISA bitmask. + +2002-03-05 Paul Koning <pkoning@equallogic.com> + + * pdp11.h: Add format codes for float instruction formats. + +2002-02-25 Alan Modra <amodra@bigpond.net.au> + + * ppc.h (PPC_OPCODE_POWER4, PPC_OPCODE_NOPOWER4): Define. + +Mon Feb 18 17:31:48 CET 2002 Jan Hubicka <jh@suse.cz> + + * i386.h (push,pop): Fix Reg64 to WordReg to allow 16bit operands. + +Mon Feb 11 12:53:19 CET 2002 Jan Hubicka <jh@suse.cz> + + * i386.h (push,pop): Allow 16bit operands in 64bit mode. + (xchg): Fix. + (in, out): Disable 64bit operands. + (call, jmp): Avoid REX prefixes. + (jcxz): Prohibit in 64bit mode + (jrcxz, loop): Add 64bit variants. + (movq): Fix patterns. + (movmskps, pextrw, pinstrw): Add 64bit variants. + +2002-01-31 Ivan Guzvinec <ivang@opencores.org> + + * or32.h: New file. + +2002-01-22 Graydon Hoare <graydon@redhat.com> + + * cgen.h (CGEN_MAYBE_MULTI_IFLD): New structure. + (CGEN_OPERAND): Add CGEN_MAYBE_MULTI_IFLD field. + +2002-01-21 Thomas Klausner <wiz@danbala.ifoer.tuwien.ac.at> + + * h8300.h: Comment typo fix. + +2002-01-03 matthew green <mrg@redhat.com> + + * ppc.h (PPC_OPCODE_BOOKE): BookE is not Motorola specific. + (PPC_OPCODE_BOOKE64): Likewise. + +Mon Dec 31 16:45:41 2001 Jeffrey A Law (law@cygnus.com) + + * hppa.h (call, ret): Move to end of table. + (addb, addib): PA2.0 variants should have been PA2.0W. + (ldw, ldh, ldb, stw, sth, stb, stwa): Reorder to keep disassembler + happy. + (fldw, fldd, fstw, fstd, bb): Likewise. + (short loads/stores): Tweak format specifier slightly to keep + disassembler happy. + (indexed loads/stores): Likewise. + (absolute loads/stores): Likewise. + +2001-12-04 Alexandre Oliva <aoliva@redhat.com> + + * d10v.h (OPERAND_NOSP): New macro. + +2001-11-29 Alexandre Oliva <aoliva@redhat.com> + + * d10v.h (OPERAND_SP): New macro. + +2001-11-15 Alan Modra <amodra@bigpond.net.au> + + * ppc.h (struct powerpc_operand <insert, extract>): Add dialect param. + +2001-11-11 Timothy Wall <twall@alum.mit.edu> + + * tic54x.h: Revise opcode layout; don't really need a separate + structure for parallel opcodes. + +2001-11-13 Zack Weinberg <zack@codesourcery.com> + Alan Modra <amodra@bigpond.net.au> + + * i386.h (i386_optab): Add entries for "sldr", "smsw" and "str" to + accept WordReg. + +2001-11-04 Chris Demetriou <cgd@broadcom.com> + + * mips.h (OPCODE_IS_MEMBER): Remove extra space. + +2001-10-30 Hans-Peter Nilsson <hp@bitrange.com> + + * mmix.h: New file. + +2001-10-18 Chris Demetriou <cgd@broadcom.com> + + * mips.h (OPCODE_IS_MEMBER): Add a no-op term to the end + of the expression, to make source code merging easier. + +2001-10-17 Chris Demetriou <cgd@broadcom.com> + + * mips.h: Sort coprocessor instruction argument characters + in comment, add a few more words of description for "H". + +2001-10-17 Chris Demetriou <cgd@broadcom.com> + + * mips.h (INSN_SB1): New cpu-specific instruction bit. + (OPCODE_IS_MEMBER): Allow instructions matching INSN_SB1 + if cpu is CPU_SB1. + +2001-10-17 matthew green <mrg@redhat.com> + + * ppc.h (PPC_OPCODE_BOOKE64): Fix typo. + +2001-10-12 matthew green <mrg@redhat.com> + + * ppc.h (PPC_OPCODE_BOOKE, PPC_OPCODE_BOOKE64, PPC_OPCODE_403): New + opcode flags for BookE 32-bit, BookE 64-bit and PowerPC 403 + instructions, respectively. + +2001-09-27 Nick Clifton <nickc@cambridge.redhat.com> + + * v850.h: Remove spurious comment. -2001-06-07 Alan Modra <amodra@bigpond.net.au> +2001-09-21 Nick Clifton <nickc@cambridge.redhat.com> - * Many files: Update copyright notices. + * h8300.h: Fix compile time warning messages + +2001-09-04 Richard Henderson <rth@redhat.com> + + * alpha.h (struct alpha_operand): Pack elements into bitfields. + +2001-08-31 Eric Christopher <echristo@redhat.com> + + * mips.h: Remove CPU_MIPS32_4K. + +2001-08-27 Torbjorn Granlund <tege@swox.com> + + * ppc.h (PPC_OPERAND_DS): Define. + +2001-08-25 Andreas Jaeger <aj@suse.de> + + * d30v.h: Fix declaration of reg_name_cnt. + + * d10v.h: Fix declaration of d10v_reg_name_cnt. + + * arc.h: Add prototypes from opcodes/arc-opc.c. + +2001-08-16 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de> + + * mips.h (INSN_10000): Define. + (OPCODE_IS_MEMBER): Check for INSN_10000. + +2001-08-10 Alan Modra <amodra@one.net.au> + + * ppc.h: Revert 2001-08-08. + +2001-08-10 Richard Sandiford <rsandifo@redhat.com> + + * mips.h (INSN_GP32): Remove. + (OPCODE_IS_MEMBER): Remove gp32 parameter. + (M_MOVE): New macro identifier. + +2001-08-08 Alan Modra <amodra@one.net.au> + + 1999-10-25 Torbjorn Granlund <tege@swox.com> + * ppc.h (struct powerpc_operand): New field `reloc'. + +2001-08-01 Aldy Hernandez <aldyh@redhat.com> + + * mips.h (INSN_ISA_MASK): Nuke bits 12-15. + +2001-07-12 Jeff Johnston <jjohnstn@redhat.com> + + * cgen.h (CGEN_INSN): Add regex support. + (build_insn_regex): Declare. + +2001-07-11 Frank Ch. Eigler <fche@redhat.com> + + * cgen.h (CGEN_MACH): Add insn_chunk_bitsize field. + (cgen_cpu_desc): Ditto. + +2001-07-07 Ben Elliston <bje@redhat.com> + + * m88k.h: Clean up and reformat. Remove unused code. + +2001-06-14 Geoffrey Keating <geoffk@redhat.com> + + * cgen.h (cgen_keyword): Add nonalpha_chars field. + +2001-05-23 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de> + + * mips.h (CPU_R12000): Define. + +2001-05-23 John Healy <jhealy@redhat.com> + + * cgen.h: Increased CGEN_MAX_SYNTAX_ELEMENTS to 48. + +2001-05-15 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de> + + * mips.h (INSN_ISA_MASK): Define. 2001-05-12 Alan Modra <amodra@one.net.au> @@ -33,11 +256,24 @@ * i386.h (i386_optab): Move InvMem to first operand of pmovmskb and pextrw to swap reg/rm assignments. +2001-04-05 Hans-Peter Nilsson <hp@axis.com> + + * cris.h (enum cris_insn_version_usage): Correct comment for + cris_ver_v3p. + 2001-03-24 Alan Modra <alan@linuxcare.com.au> * i386.h (i386_optab): Correct entry for "movntdq". Add "punpcklqdq". Add InvMem to first operand of "maskmovdqu". +2001-03-22 Hans-Peter Nilsson <hp@axis.com> + + * cris.h (ADD_PC_INCR_OPCODE): New macro. + +2001-03-21 Kazu Hirata <kazu@hxi.com> + + * h8300.h: Fix formatting. + 2001-03-22 Alan Modra <alan@linuxcare.com.au> * i386.h (i386_optab): Add paddq, psubq. @@ -46,11 +282,35 @@ * i386.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Define. -Mon Feb 12 17:39:31 CET 2001 Jan Hubicka <jh@suse.cz> +2001-02-28 Igor Shevlyakov <igor@windriver.com> + + * m68k.h: new defines for Coldfire V4. Update mcf to know + about mcf5407. + +2001-02-18 lars brinkhoff <lars@nocrew.org> + + * pdp11.h: New file. + +2001-02-12 Jan Hubicka <jh@suse.cz> * i386.h (i386_optab): SSE integer converison instructions have 64bit versions on x86-64. +2001-02-10 Nick Clifton <nickc@redhat.com> + + * mips.h: Remove extraneous whitespace. Formating change to allow + for future contribution. + +2001-02-09 Martin Schwidefsky <schwidefsky@de.ibm.com> + + * s390.h: New file. + +2001-02-02 Patrick Macdonald <patrickm@redhat.com> + + * cgen.h (CGEN_SYNTAX_CHAR_TYPE): Typedef as unsigned short. + (CGEN_MAX_SYNTAX_ELEMENTS): Rename from CGEN_MAX_SYNTAX_BYTES. + (CGEN_SYNTAX): Define using CGEN_MAX_SYNTAX_ELEMENTS. + 2001-01-24 Karsten Keil <kkeil@suse.de> * i386.h (i386_optab): Fix swapgs @@ -62,7 +322,7 @@ Mon Feb 12 17:39:31 CET 2001 Jan Hubicka <jh@suse.cz> (pa_opcodes): Add entries for missing wide mode ldi,ldo,ldw,stw. Remove duplicate "ldw j(s,b),x". Sort some entries. -Sat Jan 13 09:56:32 MET 2001 Jan Hubicka <jh@suse.cz> +2001-01-13 Jan Hubicka <jh@suse.cz> * i386.h (i386_optab): Fix pusha and ret templates. @@ -117,7 +377,7 @@ Sat Jan 13 09:56:32 MET 2001 Jan Hubicka <jh@suse.cz> * i386.h (i386_optab): Replace "Imm" with "EncImm". (i386_regtab): Add flags field. - + 2000-12-12 Nick Clifton <nickc@redhat.com> * mips.h: Fix formatting. @@ -142,7 +402,7 @@ Sat Jan 13 09:56:32 MET 2001 Jan Hubicka <jh@suse.cz> (ISA_UNKNOWN): New constant to indicate unknown ISA. (ISA_MIPS1, ISA_MIPS2, ISA_MIPS3, ISA_MIPS4, ISA_MIPS5, ISA_MIPS32): New constants, defined to be the mask of INSN_* - constants available at that ISA level. + constants available at that ISA level. (CPU_UNKNOWN): New constant to indicate unknown CPU. (CPU_4K, CPU_MIPS32_4K): Rename the former to the latter, define it with a unique value. @@ -150,7 +410,7 @@ Sat Jan 13 09:56:32 MET 2001 Jan Hubicka <jh@suse.cz> constant meanings. * mips.h (INSN_ISA64, ISA_MIPS5, ISA_MIPS64): New - definitions. + definitions. * mips.h (CPU_SB1): New constant. @@ -164,21 +424,21 @@ Sat Jan 13 09:56:32 MET 2001 Jan Hubicka <jh@suse.cz> * ia64.h (enum ia64_dependency_semantics): Add IA64_DVS_STOP. 2000-09-13 Anders Norlander <anorland@acc.umu.se> - + * mips.h: Use defines instead of hard-coded processor numbers. (CPU_R2000, CPU_R3000, CPU_R3900, CPU_R4000, CPU_R4010, - CPU_VR4100, CPU_R4111, CPU_R4300, CPU_R4400, CPU_R4600, CPU_R4650, + CPU_VR4100, CPU_R4111, CPU_R4300, CPU_R4400, CPU_R4600, CPU_R4650, CPU_R5000, CPU_R6000, CPU_R8000, CPU_R10000, CPU_MIPS32, CPU_4K, CPU_4KC, CPU_4KM, CPU_4KP): Define.. (OPCODE_IS_MEMBER): Use new defines. - (OP_MASK_SEL, OP_SH_SEL): Define. + (OP_MASK_SEL, OP_SH_SEL): Define. (OP_MASK_CODE20, OP_SH_CODE20): Define. - Add 'P' to used characters. - Use 'H' for coprocessor select field. + Add 'P' to used characters. + Use 'H' for coprocessor select field. Use 'm' for 20 bit breakpoint code. - Document new arg characters and add to used characters. - (INSN_MIPS32): New define for MIPS32 extensions. - (OPCODE_IS_MEMBER): Recognize MIPS32 instructions. + Document new arg characters and add to used characters. + (INSN_MIPS32): New define for MIPS32 extensions. + (OPCODE_IS_MEMBER): Recognize MIPS32 instructions. 2000-09-05 Alan Modra <alan@linuxcare.com.au> @@ -358,7 +618,7 @@ Fri Apr 21 13:20:53 2000 Richard Henderson <rth@cygnus.com> * cgen.h (CGEN_INSN_MACH_HAS_P): New macro. (CGEN_CPU_TABLE): flags: new field. Add prototypes for new functions. - + 2000-02-24 Alan Modra <alan@spri.levels.unisa.edu.au> * i386.h: Add some more UNIXWARE_COMPAT comments. @@ -476,7 +736,7 @@ Sun Sep 19 10:40:59 1999 Jeffrey A Law (law@cygnus.com) Sat Sep 18 11:41:16 1999 Jeffrey A Law (law@cygnus.com) * hppa.h (pa_opcodes): Use 'fX' for first register operand - in xmpyu. + in xmpyu. * hppa.h (pa_opcodes): Fix mask for probe and probei. @@ -562,7 +822,7 @@ Wed Jul 28 02:04:24 1999 Jerry Quinn <jquinn@nortelnetworks.com> * hppa.h (pa_opcodes): Mark all PA2.0 opcodes with FLAG_STRICT. - * hppa.h (pa_opcodes): Change xmpyu, fmpyfadd, + * hppa.h (pa_opcodes): Change xmpyu, fmpyfadd, and fmpynfadd to use 'J' and 'K' instead of 'E' and 'X'. 1999-07-13 Alan Modra <alan@spri.levels.unisa.edu.au> @@ -590,7 +850,7 @@ Fri Jun 25 04:22:04 1999 Jerry Quinn <jquinn@nortelnetworks.com> Fri May 28 15:26:11 1999 Jeffrey A Law (law@cygnus.com) * hppa.h (pa_opcodes): Move integer arithmetic instructions after - integer logical instructions. + integer logical instructions. 1999-05-28 Linus Nordberg <linus.nordberg@canit.se> @@ -607,7 +867,7 @@ Thu May 27 04:13:54 1999 Joel Sherrill (joel@OARcorp.com Wed May 26 16:57:44 1999 Jeffrey A Law (law@cygnus.com) - * hppa.h (pa_opcodes): Add second entry for "comb", "comib", + * hppa.h (pa_opcodes): Add second entry for "comb", "comib", "addb", and "addib" to be used by the disassembler. 1999-05-12 Alan Modra <alan@apri.levels.unisa.edu.au> @@ -718,7 +978,7 @@ Sat Feb 13 14:13:44 1999 Richard Henderson <rth@cygnus.com> (CGEN_INSN_ATTR): New type. Mon Feb 1 21:09:14 1999 Catherine Moore <clm@cygnus.com> - + * i386.h (d_Suf, x_Suf, sld_Suf, sldx_Suf, bwld_Suf): Define. (x_FP, d_FP, dls_FP, sldx_FP): Define. Change *Suf definitions to include x and d suffixes. @@ -741,7 +1001,7 @@ Mon Feb 1 21:09:14 1999 Catherine Moore <clm@cygnus.com> * cgen.h (enum cgen_mode): Add CGEN_MODE_TARGET_MAX, CGEN_MODE_INT, CGEN_MODE_UINT. -Sat Jan 16 01:29:25 1999 Jeffrey A Law (law@cygnus.com) +1999-01-16 Jeffrey A Law (law@cygnus.com) * hppa.h (bv): Fix mask. @@ -759,16 +1019,16 @@ Sat Jan 16 01:29:25 1999 Jeffrey A Law (law@cygnus.com) Wed Dec 9 10:38:48 1998 David Taylor <taylor@texas.cygnus.com> The following is part of a change made by Edith Epstein - <eepstein@sophia.cygnus.com> as part of a project to merge in - changes by HP; HP did not create ChangeLog entries. + <eepstein@sophia.cygnus.com> as part of a project to merge in + changes by HP; HP did not create ChangeLog entries. * hppa.h (completer_chars): list of chars to not put a space - after. + after. Sun Dec 6 13:21:34 1998 Ian Lance Taylor <ian@cygnus.com> * i386.h (i386_optab): Permit w suffix on processor control and - status word instructions. + status word instructions. 1998-11-30 Doug Evans <devans@casey.cygnus.com> @@ -829,7 +1089,7 @@ Fri Oct 9 13:38:13 1998 Doug Evans <devans@seba.cygnus.com> Mon Oct 5 00:21:07 1998 Jeffrey A Law (law@cygnus.com) * hppa.h: Add "fid". - + Sun Oct 4 21:00:00 1998 Alan Modra <alan@spri.levels.unisa.edu.au> From Robert Andrew Dale <rob@nb.net> @@ -883,7 +1143,7 @@ Fri Jun 26 11:09:06 1998 Jeffrey A Law (law@cygnus.com) * mn10300.h: Add "machine" field for instructions. (MN103, AM30): Define machine types. - + Fri Jun 19 16:09:09 1998 Alan Modra <alan@spri.levels.unisa.edu.au> * i386.h: Use FP, not sl_Suf, for fxsave and fxrstor. @@ -1488,9 +1748,9 @@ Mon Nov 4 12:52:48 1996 Jeffrey A Law (law@cygnus.com) Fri Nov 1 10:31:02 1996 Richard Henderson <rth@tamu.edu> * alpha.h: Don't include "bfd.h"; private relocation types are now - negative to minimize problems with shared libraries. Organize - instruction subsets by AMASK extensions and PALcode - implementation. + negative to minimize problems with shared libraries. Organize + instruction subsets by AMASK extensions and PALcode + implementation. (struct alpha_operand): Move flags slot for better packing. Tue Oct 29 12:19:10 1996 Jeffrey A Law (law@cygnus.com) @@ -1543,9 +1803,9 @@ Fri Aug 23 10:39:08 1996 Jeffrey A Law (law@cygnus.com) Thu Aug 22 16:51:25 1996 J.T. Conklin <jtc@rtl.cygnus.com> * v850.h (v850_operands): Add insert and extract fields, pointers - to functions used to handle unusual operand encoding. + to functions used to handle unusual operand encoding. (V850_OPERAND_REG, V850_OPERAND_SRG, V850_OPERAND_CC, - V850_OPERAND_SIGNED): Defined. + V850_OPERAND_SIGNED): Defined. Wed Aug 21 17:45:10 1996 J.T. Conklin <jtc@rtl.cygnus.com> @@ -1559,11 +1819,11 @@ Tue Aug 20 14:52:02 1996 J.T. Conklin <jtc@rtl.cygnus.com> Fri Aug 16 14:44:15 1996 James G. Smith <jsmith@cygnus.co.uk> * mips.h (OP_SH_LOCC, OP_SH_HICC, OP_MASK_CC, OP_SH_COP1NORM, - OP_MASK_COP1NORM, OP_SH_COP1SPEC, OP_MASK_COP1SPEC, - OP_MASK_COP1SCLR, OP_MASK_COP1CMP, OP_SH_COP1CMP, OP_SH_FORMAT, - OP_MASK_FORMAT, OP_SH_TRUE, OP_MASK_TRUE, OP_SH_GE, OP_MASK_GE, - OP_SH_UNSIGNED, OP_MASK_UNSIGNED, OP_SH_HINT, OP_MASK_HINT): - Defined. + OP_MASK_COP1NORM, OP_SH_COP1SPEC, OP_MASK_COP1SPEC, + OP_MASK_COP1SCLR, OP_MASK_COP1CMP, OP_SH_COP1CMP, OP_SH_FORMAT, + OP_MASK_FORMAT, OP_SH_TRUE, OP_MASK_TRUE, OP_SH_GE, OP_MASK_GE, + OP_SH_UNSIGNED, OP_MASK_UNSIGNED, OP_SH_HINT, OP_MASK_HINT): + Defined. Fri Aug 16 00:15:15 1996 Jeffrey A Law (law@cygnus.com) @@ -1573,7 +1833,7 @@ Fri Aug 16 00:15:15 1996 Jeffrey A Law (law@cygnus.com) Thu Aug 15 13:11:46 1996 Martin M. Hunt <hunt@pizza.cygnus.com> * d10v.h: Add some additional defines to support the - assembler in determining which operations can be done in parallel. + assembler in determining which operations can be done in parallel. Tue Aug 6 11:13:22 1996 Jeffrey A Law (law@cygnus.com) @@ -1589,7 +1849,7 @@ Fri Jul 26 11:47:10 1996 Martin M. Hunt <hunt@pizza.cygnus.com> Thu Jul 25 12:06:22 1996 Martin M. Hunt <hunt@pizza.cygnus.com> * d10v.h: Changes for divs, parallel-only instructions, and - signed numbers. + signed numbers. Mon Jul 22 11:21:15 1996 Martin M. Hunt <hunt@pizza.cygnus.com> @@ -1611,7 +1871,7 @@ Thu Jul 11 12:09:15 1996 Jeffrey A Law (law@cygnus.com) Wed Jul 3 14:30:12 1996 J.T. Conklin <jtc@rtl.cygnus.com> - * m68k.h (mcf5200): New macro. + * m68k.h (mcf5200): New macro. Document names of coldfire control registers. Tue Jul 2 23:05:45 1996 Jeffrey A Law (law@cygnus.com) @@ -1761,7 +2021,7 @@ Tue Oct 24 10:49:10 1995 Jeffrey A Law (law@cygnus.com) Mon Oct 23 11:09:16 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk> * mips.h: Added INSN_4100 flag to mark NEC VR4100 specific - instructions. + instructions. Mon Oct 16 10:28:15 1995 Michael Meissner <meissner@tiktok.cygnus.com> diff --git a/gnu/dist/toolchain/include/opcode/a29k.h b/gnu/dist/toolchain/include/opcode/a29k.h index 399be67ca5a..c6c8c370003 100644 --- a/gnu/dist/toolchain/include/opcode/a29k.h +++ b/gnu/dist/toolchain/include/opcode/a29k.h @@ -1,5 +1,5 @@ /* Table of opcodes for the AMD 29000 family. - Copyright 1990, 1991, 1993, 1994 Free Software Foundation, Inc. + Copyright 1990, 1991, 1993, 1994, 2002 Free Software Foundation, Inc. This file is part of GDB and GAS. @@ -62,11 +62,7 @@ struct a29k_opcode { char *args; }; -#ifndef CONST -#define CONST -#endif /* CONST */ - -static CONST struct a29k_opcode a29k_opcodes[] = +static const struct a29k_opcode a29k_opcodes[] = { { "add", 0x14000000, "c,a,b" }, @@ -282,4 +278,4 @@ static CONST struct a29k_opcode a29k_opcodes[] = if we've run off the end of the table. */ }; -CONST unsigned int num_opcodes = (((sizeof a29k_opcodes) / (sizeof a29k_opcodes[0])) - 1); +const unsigned int num_opcodes = (((sizeof a29k_opcodes) / (sizeof a29k_opcodes[0])) - 1); diff --git a/gnu/dist/toolchain/include/opcode/alpha.h b/gnu/dist/toolchain/include/opcode/alpha.h index 6f31e9ae09c..487b69605a3 100644 --- a/gnu/dist/toolchain/include/opcode/alpha.h +++ b/gnu/dist/toolchain/include/opcode/alpha.h @@ -81,16 +81,16 @@ extern const unsigned alpha_num_opcodes; struct alpha_operand { /* The number of bits in the operand. */ - int bits; + unsigned int bits : 5; /* How far the operand is left shifted in the instruction. */ - int shift; + unsigned int shift : 5; /* The default relocation type for this operand. */ - int default_reloc; + signed int default_reloc : 16; /* One bit syntax flags. */ - unsigned flags; + unsigned int flags : 16; /* Insertion function. This is used by the assembler. To insert an operand value into an instruction, check this field. diff --git a/gnu/dist/toolchain/include/opcode/arc.h b/gnu/dist/toolchain/include/opcode/arc.h index 81e5bd847dc..b137840156c 100644 --- a/gnu/dist/toolchain/include/opcode/arc.h +++ b/gnu/dist/toolchain/include/opcode/arc.h @@ -313,3 +313,9 @@ const struct arc_operand_value *arc_opcode_lookup_suffix PARAMS ((const struct arc_operand *type, int value)); int arc_opcode_supported PARAMS ((const struct arc_opcode *)); int arc_opval_supported PARAMS ((const struct arc_operand_value *)); +int arc_limm_fixup_adjust PARAMS ((arc_insn)); +int arc_insn_is_j PARAMS ((arc_insn)); +int arc_insn_not_jl PARAMS ((arc_insn)); +int arc_operand_type PARAMS ((int)); +struct arc_operand_value *get_ext_suffix PARAMS ((char *)); +int arc_get_noshortcut_flag PARAMS ((void)); diff --git a/gnu/dist/toolchain/include/opcode/avr.h b/gnu/dist/toolchain/include/opcode/avr.h index 393ca22d66b..bcc093d302b 100644 --- a/gnu/dist/toolchain/include/opcode/avr.h +++ b/gnu/dist/toolchain/include/opcode/avr.h @@ -25,17 +25,20 @@ supported, no 8K wrap on RJMP and RCALL) */ #define AVR_ISA_MUL 0x0040 /* device has new core (MUL, MOVW, ...) */ #define AVR_ISA_ELPM 0x0080 /* device has >64K program memory (ELPM) */ -#define AVR_ISA_ELPMX 0x0100 /* device has ELPM Rd,Z[+] (none yet) */ +#define AVR_ISA_ELPMX 0x0100 /* device has ELPM Rd,Z[+] */ #define AVR_ISA_SPM 0x0200 /* device can program itself */ +#define AVR_ISA_BRK 0x0400 /* device has BREAK (on-chip debug) */ #define AVR_ISA_EIND 0x0800 /* device has >128K program memory (none yet) */ #define AVR_ISA_TINY1 (AVR_ISA_1200 | AVR_ISA_LPM) #define AVR_ISA_2xxx (AVR_ISA_TINY1 | AVR_ISA_SRAM) -#define AVR_ISA_M83 (AVR_ISA_2xxx | AVR_ISA_MUL | AVR_ISA_LPMX | AVR_ISA_SPM) +#define AVR_ISA_M8 (AVR_ISA_2xxx | AVR_ISA_MUL | AVR_ISA_LPMX | AVR_ISA_SPM) #define AVR_ISA_M603 (AVR_ISA_2xxx | AVR_ISA_MEGA) #define AVR_ISA_M103 (AVR_ISA_M603 | AVR_ISA_ELPM) #define AVR_ISA_M161 (AVR_ISA_M603 | AVR_ISA_MUL | AVR_ISA_LPMX | AVR_ISA_SPM) #define AVR_ISA_94K (AVR_ISA_M603 | AVR_ISA_MUL | AVR_ISA_LPMX) +#define AVR_ISA_M323 (AVR_ISA_M161 | AVR_ISA_BRK) +#define AVR_ISA_M128 (AVR_ISA_M323 | AVR_ISA_ELPM | AVR_ISA_ELPMX) #define AVR_ISA_ALL 0xFFFF @@ -86,7 +89,7 @@ Order is important - some binary opcodes have more than one name, the disassembler will only see the first match. - Remaining undefined opcodes (1700 total - some of them might work + Remaining undefined opcodes (1699 total - some of them might work as normal instructions if not all of the bits are decoded): 0x0001...0x00ff (255) (known to be decoded as `nop' by the old core) @@ -100,7 +103,7 @@ "1001010xxxxx1011" (32) 0x9[45][0-9a-f]b "10010101001x1000" (2) 0x95[23]8 "1001010101xx1000" (4) 0x95[4-7]8 - "1001010110x11000" (2) 0x95[9b]8 + "1001010110111000" (1) 0x95b8 "1001010111111000" (1) 0x95f8 (`espm' removed in databook update) "11111xxxxxxx1xxx" (1024) 0xf[8-9a-f][0-9a-f][8-9a-f] */ @@ -139,6 +142,7 @@ AVR_INSN (nop, "", "0000000000000000", 1, AVR_ISA_1200, 0x0000) AVR_INSN (ret, "", "1001010100001000", 1, AVR_ISA_1200, 0x9508) AVR_INSN (reti, "", "1001010100011000", 1, AVR_ISA_1200, 0x9518) AVR_INSN (sleep,"", "1001010110001000", 1, AVR_ISA_1200, 0x9588) +AVR_INSN (break,"", "1001010110011000", 1, AVR_ISA_BRK, 0x9598) AVR_INSN (wdr, "", "1001010110101000", 1, AVR_ISA_1200, 0x95a8) AVR_INSN (spm, "", "1001010111101000", 1, AVR_ISA_SPM, 0x95e8) diff --git a/gnu/dist/toolchain/include/opcode/cgen.h b/gnu/dist/toolchain/include/opcode/cgen.h index 8cf31232225..09c5cbf03a6 100644 --- a/gnu/dist/toolchain/include/opcode/cgen.h +++ b/gnu/dist/toolchain/include/opcode/cgen.h @@ -26,7 +26,7 @@ with this program; if not, write to the Free Software Foundation, Inc., Perhaps the definition of bfd_vma can be moved outside of bfd.h. Or perhaps one could duplicate its definition in another file. Until such time, this file conditionally compiles definitions that require - bfd_vma using BFD_VERSION. */ + bfd_vma using BFD_VERSION_DATE. */ /* Enums must be defined before they can be used. Allow them to be used in struct definitions, even though the enum must @@ -199,6 +199,8 @@ typedef struct { const char *bfd_name; /* one of enum mach_attr */ int num; + /* parameter from mach->cpu */ + unsigned int insn_chunk_bitsize; } CGEN_MACH; /* Parse result (also extraction result). @@ -274,7 +276,7 @@ typedef const char * (cgen_parse_fn) PC is the pc value of the insn. The result is an error message or NULL if success. */ -#ifdef BFD_VERSION +#ifdef BFD_VERSION_DATE typedef const char * (cgen_insert_fn) PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *insn_, CGEN_FIELDS *fields_, CGEN_INSN_BYTES_PTR insnp_, @@ -295,7 +297,7 @@ typedef const char * (cgen_insert_fn) (); PC is the pc value of the insn. The result is the length of the insn in bits or zero if not recognized. */ -#ifdef BFD_VERSION +#ifdef BFD_VERSION_DATE typedef int (cgen_extract_fn) PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *insn_, CGEN_EXTRACT_INFO *ex_info_, CGEN_INSN_INT base_insn_, @@ -314,7 +316,7 @@ typedef int (cgen_extract_fn) (); PC is the pc value of the insn. LEN is the length of the insn, in bits. */ -#ifdef BFD_VERSION +#ifdef BFD_VERSION_DATE typedef void (cgen_print_fn) PARAMS ((CGEN_CPU_DESC, PTR info_, const CGEN_INSN *insn_, CGEN_FIELDS *fields_, bfd_vma pc_, int len_)); @@ -379,7 +381,7 @@ enum cgen_parse_operand_result CGEN_PARSE_OPERAND_RESULT_ERROR }; -#ifdef BFD_VERSION /* Don't require bfd.h unnecessarily. */ +#ifdef BFD_VERSION_DATE /* Don't require bfd.h unnecessarily. */ typedef const char * (cgen_parse_operand_fn) PARAMS ((CGEN_CPU_DESC, enum cgen_parse_operand_type, const char **, int, int, @@ -513,6 +515,11 @@ typedef struct cgen_keyword /* Pointer to null keyword "" entry if present. */ const CGEN_KEYWORD_ENTRY *null_entry; + + /* String containing non-alphanumeric characters used + in keywords. + At present, the highest number of entries used is 1. */ + char nonalpha_chars[8]; } CGEN_KEYWORD; /* Structure used for searching. */ @@ -558,7 +565,7 @@ const CGEN_KEYWORD_ENTRY *cgen_keyword_search_next extern const char *cgen_parse_keyword PARAMS ((CGEN_CPU_DESC, const char **, CGEN_KEYWORD *, long *)); -#ifdef BFD_VERSION /* Don't require bfd.h unnecessarily. */ +#ifdef BFD_VERSION_DATE /* Don't require bfd.h unnecessarily. */ extern const char *cgen_parse_signed_integer PARAMS ((CGEN_CPU_DESC, const char **, int, long *)); extern const char *cgen_parse_unsigned_integer @@ -602,6 +609,23 @@ enum cgen_operand_type { CGEN_OPERAND_MAX }; /* "nil" indicator for the operand instance table */ #define CGEN_OPERAND_NIL CGEN_OPERAND_MAX +/* A tree of these structs represents the multi-ifield + structure of an operand's hw-index value, if it exists. */ + +struct cgen_ifld; + +typedef struct cgen_maybe_multi_ifield +{ + int count; /* 0: indexed by single cgen_ifld (possibly null: dead entry); + n: indexed by array of more cgen_maybe_multi_ifields. */ + union + { + struct cgen_maybe_multi_ifield * multi; + struct cgen_ifld * leaf; + } val; +} +CGEN_MAYBE_MULTI_IFLD; + /* This struct defines each entry in the operand table. */ typedef struct @@ -630,6 +654,11 @@ typedef struct May be unused for a modifier. */ unsigned char length; + /* The (possibly-multi) ifield used as an index for this operand, if it + is indexed by a field at all. This substitutes / extends the start and + length fields above, but unsure at this time whether they are used + anywhere. */ + CGEN_MAYBE_MULTI_IFLD index_fields; #if 0 /* ??? Interesting idea but relocs tend to get too complicated, and ABI dependent, for simple table lookups to work. */ /* Ideally this would be the internal (external?) reloc type. */ @@ -736,25 +765,21 @@ typedef struct the data is recorded in the parse/insert/extract/print switch statements. */ /* This should be at least as large as necessary for any target. */ -#define CGEN_MAX_SYNTAX_BYTES 40 +#define CGEN_MAX_SYNTAX_ELEMENTS 48 /* A target may know its own precise maximum. Assert that it falls below the above limit. */ -#ifdef CGEN_ACTUAL_MAX_SYNTAX_BYTES -#if CGEN_ACTUAL_MAX_SYNTAX_BYTES > CGEN_MAX_SYNTAX_BYTES -#error "CGEN_ACTUAL_MAX_SYNTAX_BYTES too high - enlarge CGEN_MAX_SYNTAX_BYTES" +#ifdef CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS +#if CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS > CGEN_MAX_SYNTAX_ELEMENTS +#error "CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS too high - enlarge CGEN_MAX_SYNTAX_ELEMENTS" #endif #endif -#if !defined(MAX_OPERANDS) || MAX_OPERANDS <= 127 -typedef unsigned char CGEN_SYNTAX_CHAR_TYPE; -#else typedef unsigned short CGEN_SYNTAX_CHAR_TYPE; -#endif typedef struct { - CGEN_SYNTAX_CHAR_TYPE syntax[CGEN_MAX_SYNTAX_BYTES]; + CGEN_SYNTAX_CHAR_TYPE syntax[CGEN_MAX_SYNTAX_ELEMENTS]; } CGEN_SYNTAX; #define CGEN_SYNTAX_STRING(syn) (syn->syntax) @@ -1006,6 +1031,11 @@ struct cgen_insn const CGEN_IBASE *base; const CGEN_OPCODE *opcode; const CGEN_OPINST *opinst; + + /* Regex to disambiguate overloaded opcodes */ + void *rx; +#define CGEN_INSN_RX(insn) ((insn)->rx) +#define CGEN_MAX_RX_ELEMENTS (CGEN_MAX_SYNTAX_ELEMENTS * 5) }; /* Instruction lists. @@ -1165,6 +1195,10 @@ typedef struct cgen_cpu_desc lazily fetch the data from there. */ unsigned int word_bitsize; + /* Instruction chunk size (in bits), for purposes of endianness + conversion. */ + unsigned int insn_chunk_bitsize; + /* Indicator if sizes are unknown. This is used by default_insn_bitsize,base_insn_bitsize if there is a difference between the selected isa's. */ @@ -1219,7 +1253,7 @@ typedef struct cgen_cpu_desc const char * (*parse_operand) PARAMS ((CGEN_CPU_DESC, int opindex_, const char **, CGEN_FIELDS *fields_)); -#ifdef BFD_VERSION +#ifdef BFD_VERSION_DATE const char * (*insert_operand) PARAMS ((CGEN_CPU_DESC, int opindex_, CGEN_FIELDS *fields_, CGEN_INSN_BYTES_PTR, bfd_vma pc_)); @@ -1252,7 +1286,7 @@ typedef struct cgen_cpu_desc PARAMS ((CGEN_CPU_DESC, int opindex_, const CGEN_FIELDS *fields_)); void (*set_int_operand) PARAMS ((CGEN_CPU_DESC, int opindex_, CGEN_FIELDS *fields_, int value_)); -#ifdef BFD_VERSION +#ifdef BFD_VERSION_DATE bfd_vma (*get_vma_operand) PARAMS ((CGEN_CPU_DESC, int opindex_, const CGEN_FIELDS *fields_)); void (*set_vma_operand) @@ -1357,6 +1391,11 @@ extern void CGEN_SYM (cpu_close) PARAMS ((CGEN_CPU_DESC)); extern void CGEN_SYM (init_opcode_table) PARAMS ((CGEN_CPU_DESC cd_)); +/* build the insn selection regex. + called by init_opcode_table */ + +extern char * CGEN_SYM(build_insn_regex) PARAMS ((CGEN_INSN *insn_)); + /* Initialize the ibld table for use. Called by init_asm/init_dis. */ diff --git a/gnu/dist/toolchain/include/opcode/convex.h b/gnu/dist/toolchain/include/opcode/convex.h index 780b12d481a..ccf55682915 100644 --- a/gnu/dist/toolchain/include/opcode/convex.h +++ b/gnu/dist/toolchain/include/opcode/convex.h @@ -1,5 +1,5 @@ /* Information for instruction disassembly on the Convex. - Copyright 1989, 1993 Free Software Foundation, Inc. + Copyright 1989, 1993, 2002 Free Software Foundation, Inc. This file is part of GDB. @@ -17,10 +17,6 @@ You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ -#ifndef CONST -#define CONST -#endif /* CONST */ - #define xxx 0 #define rrr 1 #define rr 2 @@ -67,7 +63,7 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #define CPUID 20 #define TID 21 -CONST char *op[] = { +const char *op[] = { "", "v0\0v1\0v2\0v3\0v4\0v5\0v6\0v7", "s0\0s1\0s2\0s3\0s4\0s5\0s6\0s7", @@ -92,7 +88,7 @@ CONST char *op[] = { "tid", }; -CONST struct formstr format0[] = { +const struct formstr format0[] = { {0,0,rrr,V,S,S}, /* mov */ {0,0,rrr,S,S,V}, /* mov */ {1,1,rrr,V,V,V}, /* merg.t */ @@ -159,7 +155,7 @@ CONST struct formstr format0[] = { {4,8,rrr,V,S,V}, /* div.l */ }; -CONST struct formstr format1[] = { +const struct formstr format1[] = { {11,0,xxx,0,0,0}, /* exit */ {12,0,a3,0,0,0}, /* jmp */ {13,2,a3,0,0,0}, /* jmpi.f */ @@ -226,7 +222,7 @@ CONST struct formstr format1[] = { {21,8,a2r,V,0,0}, /* st.l */ }; -CONST struct formstr format2[] = { +const struct formstr format2[] = { {28,5,rr,A,A,0}, /* cvtw.b */ {28,6,rr,A,A,0}, /* cvtw.h */ {29,7,rr,A,A,0}, /* cvtb.w */ @@ -357,7 +353,7 @@ CONST struct formstr format2[] = { {4,8,rr,S,S,0}, /* div.l */ }; -CONST struct formstr format3[] = { +const struct formstr format3[] = { {32,3,rr,V,V,0}, /* cvtd.s */ {31,4,rr,V,V,0}, /* cvts.d */ {33,4,rr,V,V,0}, /* cvtl.d */ @@ -424,7 +420,7 @@ CONST struct formstr format3[] = { {43,8,rr,S,S,0}, /* neg.l */ }; -CONST struct formstr format4[] = { +const struct formstr format4[] = { {46,0,nops,0,0,0}, /* nop */ {47,0,pcrel,0,0,0}, /* br */ {48,2,pcrel,0,0,0}, /* bri.f */ @@ -435,7 +431,7 @@ CONST struct formstr format4[] = { {50,1,pcrel,0,0,0}, /* brs.t */ }; -CONST struct formstr format5[] = { +const struct formstr format5[] = { {51,5,rr,V,V,0}, /* ldvi.b */ {51,6,rr,V,V,0}, /* ldvi.h */ {51,7,rr,V,V,0}, /* ldvi.w */ @@ -454,7 +450,7 @@ CONST struct formstr format5[] = { {52,8,rxr,S,V,0}, /* stvi.l */ }; -CONST struct formstr format6[] = { +const struct formstr format6[] = { {53,0,r,A,0,0}, /* ldsdr */ {54,0,r,A,0,0}, /* ldkdr */ {55,3,r,S,0,0}, /* ln.s */ @@ -521,7 +517,7 @@ CONST struct formstr format6[] = { {83,4,r,S,0,0}, /* atan.d */ }; -CONST struct formstr format7[] = { +const struct formstr format7[] = { {84,5,r,V,0,0}, /* sum.b */ {84,6,r,V,0,0}, /* sum.h */ {84,7,r,V,0,0}, /* sum.w */ @@ -556,11 +552,11 @@ CONST struct formstr format7[] = { {0,0,0,0,0,0}, }; -CONST struct formstr formatx[] = { +const struct formstr formatx[] = { {0,0,0,0,0,0}, }; -CONST struct formstr format1a[] = { +const struct formstr format1a[] = { {91,0,imr,A,0,0}, /* halt */ {92,0,a4,0,0,0}, /* sysc */ {18,6,imr,A,0,0}, /* ld.h */ @@ -595,7 +591,7 @@ CONST struct formstr format1a[] = { {41,7,imr,A,0,0}, /* lt.w */ }; -CONST struct formstr format1b[] = { +const struct formstr format1b[] = { {18,4,imr,S,0,0}, /* ld.d */ {18,10,imr,S,0,0}, /* ld.u */ {18,8,imr,S,0,0}, /* ld.l */ @@ -630,7 +626,7 @@ CONST struct formstr format1b[] = { {41,7,imr,S,0,0}, /* lt.w */ }; -CONST struct formstr e0_format0[] = { +const struct formstr e0_format0[] = { {10,3,rrr,S,V,V}, /* sub.s */ {10,4,rrr,S,V,V}, /* sub.d */ {4,3,rrr,S,V,V}, /* div.s */ @@ -697,7 +693,7 @@ CONST struct formstr e0_format0[] = { {4,16,rrr,V,S,V}, /* div.l.f */ }; -CONST struct formstr e0_format1[] = { +const struct formstr e0_format1[] = { {0,0,0,0,0,0}, {94,0,a3,0,0,0}, /* tst */ {95,0,a3,0,0,0}, /* lck */ @@ -764,7 +760,7 @@ CONST struct formstr e0_format1[] = { {21,16,a2r,V,0,0}, /* st.l.f */ }; -CONST struct formstr e0_format2[] = { +const struct formstr e0_format2[] = { {28,5,rr,V,V,0}, /* cvtw.b */ {28,6,rr,V,V,0}, /* cvtw.h */ {29,7,rr,V,V,0}, /* cvtb.w */ @@ -895,7 +891,7 @@ CONST struct formstr e0_format2[] = { {0,0,0,0,0,0}, }; -CONST struct formstr e0_format3[] = { +const struct formstr e0_format3[] = { {32,11,rr,V,V,0}, /* cvtd.s.f */ {31,12,rr,V,V,0}, /* cvts.d.f */ {33,12,rr,V,V,0}, /* cvtl.d.f */ @@ -962,7 +958,7 @@ CONST struct formstr e0_format3[] = { {0,0,0,0,0,0}, }; -CONST struct formstr e0_format4[] = { +const struct formstr e0_format4[] = { {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, @@ -973,7 +969,7 @@ CONST struct formstr e0_format4[] = { {0,0,0,0,0,0}, }; -CONST struct formstr e0_format5[] = { +const struct formstr e0_format5[] = { {51,13,rr,V,V,0}, /* ldvi.b.f */ {51,14,rr,V,V,0}, /* ldvi.h.f */ {51,15,rr,V,V,0}, /* ldvi.w.f */ @@ -992,7 +988,7 @@ CONST struct formstr e0_format5[] = { {52,16,rxr,S,V,0}, /* stvi.l.f */ }; -CONST struct formstr e0_format6[] = { +const struct formstr e0_format6[] = { {0,0,rxl,S,CIR,0}, /* mov */ {0,0,lr,CIR,S,0}, /* mov */ {0,0,lr,TOC,S,0}, /* mov */ @@ -1059,7 +1055,7 @@ CONST struct formstr e0_format6[] = { {0,0,0,0,0,0}, }; -CONST struct formstr e0_format7[] = { +const struct formstr e0_format7[] = { {84,13,r,V,0,0}, /* sum.b.f */ {84,14,r,V,0,0}, /* sum.h.f */ {84,15,r,V,0,0}, /* sum.w.f */ @@ -1094,7 +1090,7 @@ CONST struct formstr e0_format7[] = { {0,0,0,0,0,0}, }; -CONST struct formstr e1_format0[] = { +const struct formstr e1_format0[] = { {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, @@ -1161,7 +1157,7 @@ CONST struct formstr e1_format0[] = { {4,23,rrr,V,S,V}, /* div.l.t */ }; -CONST struct formstr e1_format1[] = { +const struct formstr e1_format1[] = { {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, @@ -1228,7 +1224,7 @@ CONST struct formstr e1_format1[] = { {21,23,a2r,V,0,0}, /* st.l.t */ }; -CONST struct formstr e1_format2[] = { +const struct formstr e1_format2[] = { {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, @@ -1359,7 +1355,7 @@ CONST struct formstr e1_format2[] = { {0,0,0,0,0,0}, }; -CONST struct formstr e1_format3[] = { +const struct formstr e1_format3[] = { {32,18,rr,V,V,0}, /* cvtd.s.t */ {31,19,rr,V,V,0}, /* cvts.d.t */ {33,19,rr,V,V,0}, /* cvtl.d.t */ @@ -1426,7 +1422,7 @@ CONST struct formstr e1_format3[] = { {0,0,0,0,0,0}, }; -CONST struct formstr e1_format4[] = { +const struct formstr e1_format4[] = { {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, @@ -1437,7 +1433,7 @@ CONST struct formstr e1_format4[] = { {0,0,0,0,0,0}, }; -CONST struct formstr e1_format5[] = { +const struct formstr e1_format5[] = { {51,20,rr,V,V,0}, /* ldvi.b.t */ {51,21,rr,V,V,0}, /* ldvi.h.t */ {51,22,rr,V,V,0}, /* ldvi.w.t */ @@ -1456,7 +1452,7 @@ CONST struct formstr e1_format5[] = { {52,23,rxr,S,V,0}, /* stvi.l.t */ }; -CONST struct formstr e1_format6[] = { +const struct formstr e1_format6[] = { {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, @@ -1523,7 +1519,7 @@ CONST struct formstr e1_format6[] = { {0,0,0,0,0,0}, }; -CONST struct formstr e1_format7[] = { +const struct formstr e1_format7[] = { {84,20,r,V,0,0}, /* sum.b.t */ {84,21,r,V,0,0}, /* sum.h.t */ {84,22,r,V,0,0}, /* sum.w.t */ diff --git a/gnu/dist/toolchain/include/opcode/cris.h b/gnu/dist/toolchain/include/opcode/cris.h index 83f26d1f83e..1f10034c304 100644 --- a/gnu/dist/toolchain/include/opcode/cris.h +++ b/gnu/dist/toolchain/include/opcode/cris.h @@ -50,7 +50,7 @@ enum cris_insn_version_usage /* Only for v0..3 (Etrax 1..4). */ cris_ver_v0_3, - /* Only for v3 or higher (ETRAX 1..4 and beyond). */ + /* Only for v3 or higher (ETRAX 4 and beyond). */ cris_ver_v3p, /* Only for v8 (Etrax 100). */ @@ -160,6 +160,8 @@ extern const char *const cris_cc_strings[]; #define JUMP_INDIR_Z_BITS (0xf2c0) #define JUMP_PC_INCR_OPCODE \ (JUMP_INDIR_OPCODE + AUTOINCR_BIT * 0x0100 + REG_PC) +#define ADD_PC_INCR_OPCODE \ + (0xfa00 + (2 << 4) + AUTOINCR_BIT * 0x0100 + REG_PC) /* Nop. */ #define NOP_OPCODE (0x050F) diff --git a/gnu/dist/toolchain/include/opcode/d10v.h b/gnu/dist/toolchain/include/opcode/d10v.h index a1fe770a7c6..cc27850b033 100644 --- a/gnu/dist/toolchain/include/opcode/d10v.h +++ b/gnu/dist/toolchain/include/opcode/d10v.h @@ -1,5 +1,5 @@ /* d10v.h -- Header file for D10V opcode table - Copyright 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc. + Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. Written by Martin Hunt (hunt@cygnus.com), Cygnus Support This file is part of GDB, GAS, and the GNU binutils. @@ -181,6 +181,14 @@ extern const struct d10v_operand d10v_operands[]; /* needed for rac/rachi */ #define RESTRICTED_NUM3 (0x80000) +/* Pre-decrement is only supported for SP. */ +#define OPERAND_SP (0x100000) + +/* Post-decrement is not supported for SP. Like OPERAND_EVEN, and + unlike OPERAND_SP, this flag doesn't prevent the instruction from + matching, it only fails validation later on. */ +#define OPERAND_NOSP (0x200000) + /* Structure to hold information about predefined registers. */ struct pd_reg { @@ -190,7 +198,7 @@ struct pd_reg }; extern const struct pd_reg d10v_predefined_registers[]; -int d10v_reg_name_cnt(); +int d10v_reg_name_cnt PARAMS ((void)); /* an expressionS only has one register type, so we fake it */ /* by setting high bits to indicate type */ diff --git a/gnu/dist/toolchain/include/opcode/d30v.h b/gnu/dist/toolchain/include/opcode/d30v.h index 6cbc2576e01..c18874b66b3 100644 --- a/gnu/dist/toolchain/include/opcode/d30v.h +++ b/gnu/dist/toolchain/include/opcode/d30v.h @@ -32,7 +32,7 @@ struct pd_reg }; extern const struct pd_reg pre_defined_registers[]; -int reg_name_cnt(); +int reg_name_cnt PARAMS ((void)); /* the number of control registers */ #define MAX_CONTROL_REG 64 diff --git a/gnu/dist/toolchain/include/opcode/dlx.h b/gnu/dist/toolchain/include/opcode/dlx.h new file mode 100644 index 00000000000..e1b249f8523 --- /dev/null +++ b/gnu/dist/toolchain/include/opcode/dlx.h @@ -0,0 +1,282 @@ +/* Table of opcodes for the DLX microprocess. + Copyright 2002 Free Software Foundation, Inc. + + This file is part of GDB and GAS. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + + Initially created by Kuang Hwa Lin, 2002. */ + +/* Following are the function codes for the Special OP (ALU). */ +#define ALUOP 0x00000000 +#define SPECIALOP 0x00000000 + +#define NOPF 0x00000000 +#define SLLF 0x00000004 +#define SRLF 0x00000006 +#define SRAF 0x00000007 + +#define SEQUF 0x00000010 +#define SNEUF 0x00000011 +#define SLTUF 0x00000012 +#define SGTUF 0x00000013 +#define SLEUF 0x00000014 +#define SGEUF 0x00000015 + +#define ADDF 0x00000020 +#define ADDUF 0x00000021 +#define SUBF 0x00000022 +#define SUBUF 0x00000023 +#define ANDF 0x00000024 +#define ORF 0x00000025 +#define XORF 0x00000026 + +#define SEQF 0x00000028 +#define SNEF 0x00000029 +#define SLTF 0x0000002A +#define SGTF 0x0000002B +#define SLEF 0x0000002C +#define SGEF 0x0000002D + /* Following special functions was not mentioned in the + Hennessy's book but was implemented in the RTL. */ +#define MVTSF 0x00000030 +#define MVFSF 0x00000031 +#define BSWAPF 0x00000032 +#define LUTF 0x00000033 +/* Following special functions was mentioned in the + Hennessy's book but was not implemented in the RTL. */ +#define MULTF 0x00000005 +#define MULTUF 0x00000006 +#define DIVF 0x00000007 +#define DIVUF 0x00000008 + + +/* Following are the rest of the OPcodes: + JOP = (0x002 << 26), JALOP = (0x003 << 26), BEQOP = (0x004 << 26), BNEOP = (0x005 << 26) + ADDIOP = (0x008 << 26), ADDUIOP= (0x009 << 26), SUBIOP = (0x00A << 26), SUBUIOP= (0x00B << 26) + ANDIOP = (0x00C << 26), ORIOP = (0x00D << 26), XORIOP = (0x00E << 26), LHIOP = (0x00F << 26) + RFEOP = (0x010 << 26), TRAPOP = (0x011 << 26), JROP = (0x012 << 26), JALROP = (0x013 << 26) + BREAKOP= (0x014 << 26) + SEQIOP = (0x018 << 26), SNEIOP = (0x019 << 26), SLTIOP = (0x01A << 26), SGTIOP = (0x01B << 26) + SLEIOP = (0x01C << 26), SGEIOP = (0x01D << 26) + LBOP = (0x020 << 26), LHOP = (0x021 << 26), LWOP = (0x023 << 26), LBUOP = (0x024 << 26) + LHUOP = (0x025 << 26), SBOP = (0x028 << 26), SHOP = (0x029 << 26), SWOP = (0x02B << 26) + LSBUOP = (0x026 << 26), LSHU = (0x027 << 26), LSW = (0x02C << 26), + SEQUIOP= (0x030 << 26), SNEUIOP= (0x031 << 26), SLTUIOP= (0x032 << 26), SGTUIOP= (0x033 << 26) + SLEUIOP= (0x034 << 26), SGEUIOP= (0x035 << 26) + SLLIOP = (0x036 << 26), SRLIOP = (0x037 << 26), SRAIOP = (0x038 << 26). */ +#define JOP 0x08000000 +#define JALOP 0x0c000000 +#define BEQOP 0x10000000 +#define BNEOP 0x14000000 + +#define ADDIOP 0x20000000 +#define ADDUIOP 0x24000000 +#define SUBIOP 0x28000000 +#define SUBUIOP 0x2c000000 +#define ANDIOP 0x30000000 +#define ORIOP 0x34000000 +#define XORIOP 0x38000000 +#define LHIOP 0x3c000000 +#define RFEOP 0x40000000 +#define TRAPOP 0x44000000 +#define JROP 0x48000000 +#define JALROP 0x4c000000 +#define BREAKOP 0x50000000 + +#define SEQIOP 0x60000000 +#define SNEIOP 0x64000000 +#define SLTIOP 0x68000000 +#define SGTIOP 0x6c000000 +#define SLEIOP 0x70000000 +#define SGEIOP 0x74000000 + +#define LBOP 0x80000000 +#define LHOP 0x84000000 +#define LWOP 0x8c000000 +#define LBUOP 0x90000000 +#define LHUOP 0x94000000 +#define LDSTBU +#define LDSTHU +#define SBOP 0xa0000000 +#define SHOP 0xa4000000 +#define SWOP 0xac000000 +#define LDST + +#define SEQUIOP 0xc0000000 +#define SNEUIOP 0xc4000000 +#define SLTUIOP 0xc8000000 +#define SGTUIOP 0xcc000000 +#define SLEUIOP 0xd0000000 +#define SGEUIOP 0xd4000000 + +#define SLLIOP 0xd8000000 +#define SRLIOP 0xdc000000 +#define SRAIOP 0xe0000000 + +/* Following 3 ops was added to provide the MP atonmic operation. */ +#define LSBUOP 0x98000000 +#define LSHUOP 0x9c000000 +#define LSWOP 0xb0000000 + +/* Following opcode was defined in the Hennessy's book as + "normal" opcode but was implemented in the RTL as special + functions. */ +#if 0 +#define MVTSOP 0x50000000 +#define MVFSOP 0x54000000 +#endif + +struct dlx_opcode +{ + /* Name of the instruction. */ + char *name; + + /* Opcode word. */ + unsigned long opcode; + + /* A string of characters which describe the operands. + Valid characters are: + , Itself. The character appears in the assembly code. + a rs1 The register number is in bits 21-25 of the instruction. + b rs2/rd The register number is in bits 16-20 of the instruction. + c rd. The register number is in bits 11-15 of the instruction. + f FUNC bits 0-10 of the instruction. + i An immediate operand is in bits 0-16 of the instruction. 0 extended + I An immediate operand is in bits 0-16 of the instruction. sign extended + d An 16 bit PC relative displacement. + D An immediate operand is in bits 0-25 of the instruction. + N No opperands needed, for nops. + P it can be a register or a 16 bit operand. */ + char *args; +}; + +static const struct dlx_opcode dlx_opcodes[] = + { + /* Arithmetic and Logic R-TYPE instructions. */ + { "nop", (ALUOP|NOPF), "N" }, /* NOP */ + { "add", (ALUOP|ADDF), "c,a,b" }, /* Add */ + { "addu", (ALUOP|ADDUF), "c,a,b" }, /* Add Unsigned */ + { "sub", (ALUOP|SUBF), "c,a,b" }, /* SUB */ + { "subu", (ALUOP|SUBUF), "c,a,b" }, /* Sub Unsigned */ + { "mult", (ALUOP|MULTF), "c,a,b" }, /* MULTIPLY */ + { "multu", (ALUOP|MULTUF), "c,a,b" }, /* MULTIPLY Unsigned */ + { "div", (ALUOP|DIVF), "c,a,b" }, /* DIVIDE */ + { "divu", (ALUOP|DIVUF), "c,a,b" }, /* DIVIDE Unsigned */ + { "and", (ALUOP|ANDF), "c,a,b" }, /* AND */ + { "or", (ALUOP|ORF), "c,a,b" }, /* OR */ + { "xor", (ALUOP|XORF), "c,a,b" }, /* Exclusive OR */ + { "sll", (ALUOP|SLLF), "c,a,b" }, /* SHIFT LEFT LOGICAL */ + { "sra", (ALUOP|SRAF), "c,a,b" }, /* SHIFT RIGHT ARITHMETIC */ + { "srl", (ALUOP|SRLF), "c,a,b" }, /* SHIFT RIGHT LOGICAL */ + { "seq", (ALUOP|SEQF), "c,a,b" }, /* Set if equal */ + { "sne", (ALUOP|SNEF), "c,a,b" }, /* Set if not equal */ + { "slt", (ALUOP|SLTF), "c,a,b" }, /* Set if less */ + { "sgt", (ALUOP|SGTF), "c,a,b" }, /* Set if greater */ + { "sle", (ALUOP|SLEF), "c,a,b" }, /* Set if less or equal */ + { "sge", (ALUOP|SGEF), "c,a,b" }, /* Set if greater or equal */ + { "sequ", (ALUOP|SEQUF), "c,a,b" }, /* Set if equal unsigned */ + { "sneu", (ALUOP|SNEUF), "c,a,b" }, /* Set if not equal unsigned */ + { "sltu", (ALUOP|SLTUF), "c,a,b" }, /* Set if less unsigned */ + { "sgtu", (ALUOP|SGTUF), "c,a,b" }, /* Set if greater unsigned */ + { "sleu", (ALUOP|SLEUF), "c,a,b" }, /* Set if less or equal unsigned*/ + { "sgeu", (ALUOP|SGEUF), "c,a,b" }, /* Set if greater or equal */ + { "mvts", (ALUOP|MVTSF), "c,a" }, /* Move to special register */ + { "mvfs", (ALUOP|MVFSF), "c,a" }, /* Move from special register */ + { "bswap", (ALUOP|BSWAPF), "c,a,b" }, /* ??? Was not documented */ + { "lut", (ALUOP|LUTF), "c,a,b" }, /* ????? same as above */ + + /* Arithmetic and Logical Immediate I-TYPE instructions. */ + { "addi", ADDIOP, "b,a,I" }, /* Add Immediate */ + { "addui", ADDUIOP, "b,a,i" }, /* Add Usigned Immediate */ + { "subi", SUBIOP, "b,a,I" }, /* Sub Immediate */ + { "subui", SUBUIOP, "b,a,i" }, /* Sub Unsigned Immedated */ + { "andi", ANDIOP, "b,a,i" }, /* AND Immediate */ + { "ori", ORIOP, "b,a,i" }, /* OR Immediate */ + { "xori", XORIOP, "b,a,i" }, /* Exclusive OR Immediate */ + { "slli", SLLIOP, "b,a,i" }, /* SHIFT LEFT LOCICAL Immediate */ + { "srai", SRAIOP, "b,a,i" }, /* SHIFT RIGHT ARITH. Immediate */ + { "srli", SRLIOP, "b,a,i" }, /* SHIFT RIGHT LOGICAL Immediate*/ + { "seqi", SEQIOP, "b,a,i" }, /* Set if equal */ + { "snei", SNEIOP, "b,a,i" }, /* Set if not equal */ + { "slti", SLTIOP, "b,a,i" }, /* Set if less */ + { "sgti", SGTIOP, "b,a,i" }, /* Set if greater */ + { "slei", SLEIOP, "b,a,i" }, /* Set if less or equal */ + { "sgei", SGEIOP, "b,a,i" }, /* Set if greater or equal */ + { "sequi", SEQUIOP, "b,a,i" }, /* Set if equal */ + { "sneui", SNEUIOP, "b,a,i" }, /* Set if not equal */ + { "sltui", SLTUIOP, "b,a,i" }, /* Set if less */ + { "sgtui", SGTUIOP, "b,a,i" }, /* Set if greater */ + { "sleui", SLEUIOP, "b,a,i" }, /* Set if less or equal */ + { "sgeui", SGEUIOP, "b,a,i" }, /* Set if greater or equal */ + /* Macros for I type instructions. */ + { "mov", ADDIOP, "b,P" }, /* a move macro */ + { "movu", ADDUIOP, "b,P" }, /* a move macro, unsigned */ + +#if 0 + /* Move special. */ + { "mvts", MVTSOP, "b,a" }, /* Move From Integer to Special */ + { "mvfs", MVFSOP, "b,a" }, /* Move From Special to Integer */ +#endif + + /* Load high Immediate I-TYPE instruction. */ + { "lhi", LHIOP, "b,i" }, /* Load High Immediate */ + { "lui", LHIOP, "b,i" }, /* Load High Immediate */ + { "sethi", LHIOP, "b,i" }, /* Load High Immediate */ + + /* LOAD/STORE BYTE 8 bits I-TYPE. */ + { "lb", LBOP, "b,a,I" }, /* Load Byte */ + { "lbu", LBUOP, "b,a,I" }, /* Load Byte Unsigned */ + { "ldstbu", LSBUOP, "b,a,I" }, /* Load store Byte Unsigned */ + { "sb", SBOP, "b,a,I" }, /* Store Byte */ + + /* LOAD/STORE HALFWORD 16 bits. */ + { "lh", LHOP, "b,a,I" }, /* Load Halfword */ + { "lhu", LHUOP, "b,a,I" }, /* Load Halfword Unsigned */ + { "ldsthu", LSHUOP, "b,a,I" }, /* Load Store Halfword Unsigned */ + { "sh", SHOP, "b,a,I" }, /* Store Halfword */ + + /* LOAD/STORE WORD 32 bits. */ + { "lw", LWOP, "b,a,I" }, /* Load Word */ + { "sw", SWOP, "b,a,I" }, /* Store Word */ + { "ldstw", LSWOP, "b,a,I" }, /* Load Store Word */ + + /* Branch PC-relative, 16 bits offset. */ + { "beqz", BEQOP, "a,d" }, /* Branch if a == 0 */ + { "bnez", BNEOP, "a,d" }, /* Branch if a != 0 */ + { "beq", BEQOP, "a,d" }, /* Branch if a == 0 */ + { "bne", BNEOP, "a,d" }, /* Branch if a != 0 */ + + /* Jumps Trap and RFE J-TYPE. */ + { "j", JOP, "D" }, /* Jump, PC-relative 26 bits */ + { "jal", JALOP, "D" }, /* JAL, PC-relative 26 bits */ + { "break", BREAKOP, "D" }, /* break to OS */ + { "trap" , TRAPOP, "D" }, /* TRAP to OS */ + { "rfe", RFEOP, "N" }, /* Return From Exception */ + /* Macros. */ + { "call", JOP, "D" }, /* Jump, PC-relative 26 bits */ + + /* Jumps Trap and RFE I-TYPE. */ + { "jr", JROP, "a" }, /* Jump Register, Abs (32 bits) */ + { "jalr", JALROP, "a" }, /* JALR, Abs (32 bits) */ + /* Macros. */ + { "retr", JROP, "a" }, /* Jump Register, Abs (32 bits) */ + + { "", 0x0, "" } /* Dummy entry, not included in NUM_OPCODES. + This lets code examine entry i + 1 without + checking if we've run off the end of the table. */ + }; + +const unsigned int num_dlx_opcodes = (((sizeof dlx_opcodes) / (sizeof dlx_opcodes[0])) - 1); diff --git a/gnu/dist/toolchain/include/opcode/hppa.h b/gnu/dist/toolchain/include/opcode/hppa.h index f409ac94bb4..e9070914271 100644 --- a/gnu/dist/toolchain/include/opcode/hppa.h +++ b/gnu/dist/toolchain/include/opcode/hppa.h @@ -170,10 +170,16 @@ Also these: Completer operands all have 'c' as the prefix: cx indexed load completer. + cX indexed load completer. Like cx, but emits a space after + in disassembler. cm short load and store completer. + cM short load and store completer. Like cm, but emits a space + after in disassembler. cq long load and store completer (like cm, but inserted into a different location in the target instruction). cs store bytes short completer. + cA store bytes short completer. Like cs, but emits a space + after in disassembler. ce long load/store completer for LDW/STW with a different encoding than the others cc load cache control hint @@ -285,10 +291,6 @@ static const struct pa_opcode pa_opcodes[] = { "ldi", 0x34000000, 0xffe00000, "l,x", pa20w, 0},/* ldo val(r0),r */ { "ldi", 0x34000000, 0xffe0c000, "j,x", pa10, 0},/* ldo val(r0),r */ -{ "call", 0xe800f000, 0xfc1ffffd, "n(b)", pa20, FLAG_STRICT}, -{ "call", 0xe800a000, 0xffe0e000, "nW", pa10, FLAG_STRICT}, -{ "ret", 0xe840d000, 0xfffffffd, "n", pa20, FLAG_STRICT}, - { "cmpib", 0xec000000, 0xfc000000, "?Qn5,b,w", pa20, FLAG_STRICT}, { "cmpib", 0x84000000, 0xf4000000, "?nn5,b,w", pa10, FLAG_STRICT}, { "comib", 0x84000000, 0xfc000000, "?nn5,b,w", pa10, 0}, /* comib{tf}*/ @@ -301,12 +303,12 @@ static const struct pa_opcode pa_opcodes[] = /* This entry is for the disassembler only. It will never be used by assembler. */ { "comb", 0x88000000, 0xfc000000, "?nnx,b,w", pa10, 0}, /* comb{tf} */ -{ "addb", 0xa0000000, 0xf4000000, "?Wnx,b,w", pa20, FLAG_STRICT}, +{ "addb", 0xa0000000, 0xf4000000, "?Wnx,b,w", pa20w, FLAG_STRICT}, { "addb", 0xa0000000, 0xfc000000, "?@nx,b,w", pa10, 0}, /* addb{tf} */ /* This entry is for the disassembler only. It will never be used by assembler. */ { "addb", 0xa8000000, 0xfc000000, "?@nx,b,w", pa10, 0}, -{ "addib", 0xa4000000, 0xf4000000, "?Wn5,b,w", pa20, FLAG_STRICT}, +{ "addib", 0xa4000000, 0xf4000000, "?Wn5,b,w", pa20w, FLAG_STRICT}, { "addib", 0xa4000000, 0xfc000000, "?@n5,b,w", pa10, 0}, /* addib{tf}*/ /* This entry is for the disassembler only. It will never be used by assembler. */ @@ -327,10 +329,10 @@ static const struct pa_opcode pa_opcodes[] = { "ldd", 0x50000000, 0xfc000002, "cq#(b),x", pa20, FLAG_STRICT}, { "ldw", 0x0c000080, 0xfc0013c0, "cxccx(s,b),t", pa10, FLAG_STRICT}, { "ldw", 0x0c000080, 0xfc0013c0, "cxccx(b),t", pa10, FLAG_STRICT}, -{ "ldw", 0x0c0010a0, 0xfc1f33e0, "cocc@(s,b),t", pa20, FLAG_STRICT}, -{ "ldw", 0x0c0010a0, 0xfc1f33e0, "cocc@(b),t", pa20, FLAG_STRICT}, { "ldw", 0x0c001080, 0xfc0013c0, "cmcc5(s,b),t", pa10, FLAG_STRICT}, { "ldw", 0x0c001080, 0xfc0013c0, "cmcc5(b),t", pa10, FLAG_STRICT}, +{ "ldw", 0x0c0010a0, 0xfc1f33e0, "cocc@(s,b),t", pa20, FLAG_STRICT}, +{ "ldw", 0x0c0010a0, 0xfc1f33e0, "cocc@(b),t", pa20, FLAG_STRICT}, { "ldw", 0x4c000000, 0xfc000000, "ce<(b),x", pa20w, FLAG_STRICT}, { "ldw", 0x4c000000, 0xfc000000, "ceJ(s,b),x", pa10, FLAG_STRICT}, { "ldw", 0x4c000000, 0xfc000000, "ceJ(b),x", pa10, FLAG_STRICT}, @@ -342,19 +344,19 @@ static const struct pa_opcode pa_opcodes[] = { "ldw", 0x48000000, 0xfc000000, "j(b),x", pa10, 0}, { "ldh", 0x0c000040, 0xfc0013c0, "cxccx(s,b),t", pa10, FLAG_STRICT}, { "ldh", 0x0c000040, 0xfc0013c0, "cxccx(b),t", pa10, FLAG_STRICT}, -{ "ldh", 0x0c001060, 0xfc1f33e0, "cocc@(s,b),t", pa20, FLAG_STRICT}, -{ "ldh", 0x0c001060, 0xfc1f33e0, "cocc@(b),t", pa20, FLAG_STRICT}, { "ldh", 0x0c001040, 0xfc0013c0, "cmcc5(s,b),t", pa10, FLAG_STRICT}, { "ldh", 0x0c001040, 0xfc0013c0, "cmcc5(b),t", pa10, FLAG_STRICT}, +{ "ldh", 0x0c001060, 0xfc1f33e0, "cocc@(s,b),t", pa20, FLAG_STRICT}, +{ "ldh", 0x0c001060, 0xfc1f33e0, "cocc@(b),t", pa20, FLAG_STRICT}, { "ldh", 0x44000000, 0xfc000000, "l(b),x", pa20w, FLAG_STRICT}, { "ldh", 0x44000000, 0xfc000000, "j(s,b),x", pa10, 0}, { "ldh", 0x44000000, 0xfc000000, "j(b),x", pa10, 0}, { "ldb", 0x0c000000, 0xfc0013c0, "cxccx(s,b),t", pa10, FLAG_STRICT}, { "ldb", 0x0c000000, 0xfc0013c0, "cxccx(b),t", pa10, FLAG_STRICT}, -{ "ldb", 0x0c001020, 0xfc1f33e0, "cocc@(s,b),t", pa20, FLAG_STRICT}, -{ "ldb", 0x0c001020, 0xfc1f33e0, "cocc@(b),t", pa20, FLAG_STRICT}, { "ldb", 0x0c001000, 0xfc0013c0, "cmcc5(s,b),t", pa10, FLAG_STRICT}, { "ldb", 0x0c001000, 0xfc0013c0, "cmcc5(b),t", pa10, FLAG_STRICT}, +{ "ldb", 0x0c001020, 0xfc1f33e0, "cocc@(s,b),t", pa20, FLAG_STRICT}, +{ "ldb", 0x0c001020, 0xfc1f33e0, "cocc@(b),t", pa20, FLAG_STRICT}, { "ldb", 0x40000000, 0xfc000000, "l(b),x", pa20w, FLAG_STRICT}, { "ldb", 0x40000000, 0xfc000000, "j(s,b),x", pa10, 0}, { "ldb", 0x40000000, 0xfc000000, "j(b),x", pa10, 0}, @@ -364,10 +366,10 @@ static const struct pa_opcode pa_opcodes[] = { "std", 0x0c0012c0, 0xfc0013c0, "cmcCx,V(b)", pa20, FLAG_STRICT}, { "std", 0x70000000, 0xfc000002, "cqx,&(b)", pa20w, FLAG_STRICT}, { "std", 0x70000000, 0xfc000002, "cqx,#(b)", pa20, FLAG_STRICT}, -{ "stw", 0x0c0012a0, 0xfc0013ff, "cocCx,@(s,b)", pa20, FLAG_STRICT}, -{ "stw", 0x0c0012a0, 0xfc0013ff, "cocCx,@(b)", pa20, FLAG_STRICT}, { "stw", 0x0c001280, 0xfc0013c0, "cmcCx,V(s,b)", pa10, FLAG_STRICT}, { "stw", 0x0c001280, 0xfc0013c0, "cmcCx,V(b)", pa10, FLAG_STRICT}, +{ "stw", 0x0c0012a0, 0xfc0013ff, "cocCx,@(s,b)", pa20, FLAG_STRICT}, +{ "stw", 0x0c0012a0, 0xfc0013ff, "cocCx,@(b)", pa20, FLAG_STRICT}, { "stw", 0x6c000000, 0xfc000000, "cex,<(b)", pa20w, FLAG_STRICT}, { "stw", 0x6c000000, 0xfc000000, "cex,J(s,b)", pa10, FLAG_STRICT}, { "stw", 0x6c000000, 0xfc000000, "cex,J(b)", pa10, FLAG_STRICT}, @@ -377,17 +379,17 @@ static const struct pa_opcode pa_opcodes[] = { "stw", 0x68000000, 0xfc000000, "x,l(b)", pa20w, FLAG_STRICT}, { "stw", 0x68000000, 0xfc000000, "x,j(s,b)", pa10, 0}, { "stw", 0x68000000, 0xfc000000, "x,j(b)", pa10, 0}, -{ "sth", 0x0c001260, 0xfc0033ff, "cocCx,@(s,b)", pa20, FLAG_STRICT}, -{ "sth", 0x0c001260, 0xfc0033ff, "cocCx,@(b)", pa20, FLAG_STRICT}, { "sth", 0x0c001240, 0xfc0013c0, "cmcCx,V(s,b)", pa10, FLAG_STRICT}, { "sth", 0x0c001240, 0xfc0013c0, "cmcCx,V(b)", pa10, FLAG_STRICT}, +{ "sth", 0x0c001260, 0xfc0033ff, "cocCx,@(s,b)", pa20, FLAG_STRICT}, +{ "sth", 0x0c001260, 0xfc0033ff, "cocCx,@(b)", pa20, FLAG_STRICT}, { "sth", 0x64000000, 0xfc000000, "x,l(b)", pa20w, FLAG_STRICT}, { "sth", 0x64000000, 0xfc000000, "x,j(s,b)", pa10, 0}, { "sth", 0x64000000, 0xfc000000, "x,j(b)", pa10, 0}, -{ "stb", 0x0c001220, 0xfc0033ff, "cocCx,@(s,b)", pa20, FLAG_STRICT}, -{ "stb", 0x0c001220, 0xfc0033ff, "cocCx,@(b)", pa20, FLAG_STRICT}, { "stb", 0x0c001200, 0xfc0013c0, "cmcCx,V(s,b)", pa10, FLAG_STRICT}, { "stb", 0x0c001200, 0xfc0013c0, "cmcCx,V(b)", pa10, FLAG_STRICT}, +{ "stb", 0x0c001220, 0xfc0033ff, "cocCx,@(s,b)", pa20, FLAG_STRICT}, +{ "stb", 0x0c001220, 0xfc0033ff, "cocCx,@(b)", pa20, FLAG_STRICT}, { "stb", 0x60000000, 0xfc000000, "x,l(b)", pa20w, FLAG_STRICT}, { "stb", 0x60000000, 0xfc000000, "x,j(s,b)", pa10, 0}, { "stb", 0x60000000, 0xfc000000, "x,j(b)", pa10, 0}, @@ -395,20 +397,20 @@ static const struct pa_opcode pa_opcodes[] = { "ldwm", 0x4c000000, 0xfc000000, "j(b),x", pa10, 0}, { "stwm", 0x6c000000, 0xfc000000, "x,j(s,b)", pa10, 0}, { "stwm", 0x6c000000, 0xfc000000, "x,j(b)", pa10, 0}, -{ "ldwx", 0x0c000080, 0xfc001fc0, "cxx(s,b),t", pa10, 0}, -{ "ldwx", 0x0c000080, 0xfc001fc0, "cxx(b),t", pa10, 0}, -{ "ldhx", 0x0c000040, 0xfc001fc0, "cxx(s,b),t", pa10, 0}, -{ "ldhx", 0x0c000040, 0xfc001fc0, "cxx(b),t", pa10, 0}, -{ "ldbx", 0x0c000000, 0xfc001fc0, "cxx(s,b),t", pa10, 0}, -{ "ldbx", 0x0c000000, 0xfc001fc0, "cxx(b),t", pa10, 0}, +{ "ldwx", 0x0c000080, 0xfc001fc0, "cXx(s,b),t", pa10, 0}, +{ "ldwx", 0x0c000080, 0xfc001fc0, "cXx(b),t", pa10, 0}, +{ "ldhx", 0x0c000040, 0xfc001fc0, "cXx(s,b),t", pa10, 0}, +{ "ldhx", 0x0c000040, 0xfc001fc0, "cXx(b),t", pa10, 0}, +{ "ldbx", 0x0c000000, 0xfc001fc0, "cXx(s,b),t", pa10, 0}, +{ "ldbx", 0x0c000000, 0xfc001fc0, "cXx(b),t", pa10, 0}, { "ldwa", 0x0c000180, 0xfc00d3c0, "cxccx(b),t", pa10, FLAG_STRICT}, { "ldwa", 0x0c001180, 0xfc00d3c0, "cmcc5(b),t", pa10, FLAG_STRICT}, { "ldcw", 0x0c0001c0, 0xfc0013c0, "cxcdx(s,b),t", pa10, FLAG_STRICT}, { "ldcw", 0x0c0001c0, 0xfc0013c0, "cxcdx(b),t", pa10, FLAG_STRICT}, { "ldcw", 0x0c0011c0, 0xfc0013c0, "cmcd5(s,b),t", pa10, FLAG_STRICT}, { "ldcw", 0x0c0011c0, 0xfc0013c0, "cmcd5(b),t", pa10, FLAG_STRICT}, -{ "stwa", 0x0c0013a0, 0xfc00d3ff, "cocCx,@(b)", pa20, FLAG_STRICT}, { "stwa", 0x0c001380, 0xfc00d3c0, "cmcCx,V(b)", pa10, FLAG_STRICT}, +{ "stwa", 0x0c0013a0, 0xfc00d3ff, "cocCx,@(b)", pa20, FLAG_STRICT}, { "stby", 0x0c001300, 0xfc0013c0, "cscCx,V(s,b)", pa10, FLAG_STRICT}, { "stby", 0x0c001300, 0xfc0013c0, "cscCx,V(b)", pa10, FLAG_STRICT}, { "ldda", 0x0c000100, 0xfc00d3c0, "cxccx(b),t", pa20, FLAG_STRICT}, @@ -421,29 +423,29 @@ static const struct pa_opcode pa_opcodes[] = { "stda", 0x0c0013e0, 0xfc0033ff, "cocCx,@(b)", pa20, FLAG_STRICT}, { "stda", 0x0c0013c0, 0xfc0013c0, "cmcCx,V(s,b)", pa20, FLAG_STRICT}, { "stda", 0x0c0013c0, 0xfc0013c0, "cmcCx,V(b)", pa20, FLAG_STRICT}, -{ "ldwax", 0x0c000180, 0xfc00dfc0, "cxx(b),t", pa10, 0}, -{ "ldcwx", 0x0c0001c0, 0xfc001fc0, "cxx(s,b),t", pa10, 0}, -{ "ldcwx", 0x0c0001c0, 0xfc001fc0, "cxx(b),t", pa10, 0}, -{ "ldws", 0x0c001080, 0xfc001fc0, "cm5(s,b),t", pa10, 0}, -{ "ldws", 0x0c001080, 0xfc001fc0, "cm5(b),t", pa10, 0}, -{ "ldhs", 0x0c001040, 0xfc001fc0, "cm5(s,b),t", pa10, 0}, -{ "ldhs", 0x0c001040, 0xfc001fc0, "cm5(b),t", pa10, 0}, -{ "ldbs", 0x0c001000, 0xfc001fc0, "cm5(s,b),t", pa10, 0}, -{ "ldbs", 0x0c001000, 0xfc001fc0, "cm5(b),t", pa10, 0}, -{ "ldwas", 0x0c001180, 0xfc00dfc0, "cm5(b),t", pa10, 0}, -{ "ldcws", 0x0c0011c0, 0xfc001fc0, "cm5(s,b),t", pa10, 0}, -{ "ldcws", 0x0c0011c0, 0xfc001fc0, "cm5(b),t", pa10, 0}, -{ "stws", 0x0c001280, 0xfc001fc0, "cmx,V(s,b)", pa10, 0}, -{ "stws", 0x0c001280, 0xfc001fc0, "cmx,V(b)", pa10, 0}, -{ "sths", 0x0c001240, 0xfc001fc0, "cmx,V(s,b)", pa10, 0}, -{ "sths", 0x0c001240, 0xfc001fc0, "cmx,V(b)", pa10, 0}, -{ "stbs", 0x0c001200, 0xfc001fc0, "cmx,V(s,b)", pa10, 0}, -{ "stbs", 0x0c001200, 0xfc001fc0, "cmx,V(b)", pa10, 0}, -{ "stwas", 0x0c001380, 0xfc00dfc0, "cmx,V(b)", pa10, 0}, +{ "ldwax", 0x0c000180, 0xfc00dfc0, "cXx(b),t", pa10, 0}, +{ "ldcwx", 0x0c0001c0, 0xfc001fc0, "cXx(s,b),t", pa10, 0}, +{ "ldcwx", 0x0c0001c0, 0xfc001fc0, "cXx(b),t", pa10, 0}, +{ "ldws", 0x0c001080, 0xfc001fc0, "cM5(s,b),t", pa10, 0}, +{ "ldws", 0x0c001080, 0xfc001fc0, "cM5(b),t", pa10, 0}, +{ "ldhs", 0x0c001040, 0xfc001fc0, "cM5(s,b),t", pa10, 0}, +{ "ldhs", 0x0c001040, 0xfc001fc0, "cM5(b),t", pa10, 0}, +{ "ldbs", 0x0c001000, 0xfc001fc0, "cM5(s,b),t", pa10, 0}, +{ "ldbs", 0x0c001000, 0xfc001fc0, "cM5(b),t", pa10, 0}, +{ "ldwas", 0x0c001180, 0xfc00dfc0, "cM5(b),t", pa10, 0}, +{ "ldcws", 0x0c0011c0, 0xfc001fc0, "cM5(s,b),t", pa10, 0}, +{ "ldcws", 0x0c0011c0, 0xfc001fc0, "cM5(b),t", pa10, 0}, +{ "stws", 0x0c001280, 0xfc001fc0, "cMx,V(s,b)", pa10, 0}, +{ "stws", 0x0c001280, 0xfc001fc0, "cMx,V(b)", pa10, 0}, +{ "sths", 0x0c001240, 0xfc001fc0, "cMx,V(s,b)", pa10, 0}, +{ "sths", 0x0c001240, 0xfc001fc0, "cMx,V(b)", pa10, 0}, +{ "stbs", 0x0c001200, 0xfc001fc0, "cMx,V(s,b)", pa10, 0}, +{ "stbs", 0x0c001200, 0xfc001fc0, "cMx,V(b)", pa10, 0}, +{ "stwas", 0x0c001380, 0xfc00dfc0, "cMx,V(b)", pa10, 0}, { "stdby", 0x0c001340, 0xfc0013c0, "cscCx,V(s,b)", pa20, FLAG_STRICT}, { "stdby", 0x0c001340, 0xfc0013c0, "cscCx,V(b)", pa20, FLAG_STRICT}, -{ "stbys", 0x0c001300, 0xfc001fc0, "csx,V(s,b)", pa10, 0}, -{ "stbys", 0x0c001300, 0xfc001fc0, "csx,V(b)", pa10, 0}, +{ "stbys", 0x0c001300, 0xfc001fc0, "cAx,V(s,b)", pa10, 0}, +{ "stbys", 0x0c001300, 0xfc001fc0, "cAx,V(b)", pa10, 0}, /* Immediate instructions. */ { "ldo", 0x34000000, 0xfc000000, "l(b),x", pa20w, 0}, @@ -482,10 +484,10 @@ static const struct pa_opcode pa_opcodes[] = { "addbf", 0xa8000000, 0xfc000000, "?dnx,b,w", pa10, 0}, { "addibt", 0xa4000000, 0xfc000000, "?dn5,b,w", pa10, 0}, { "addibf", 0xac000000, 0xfc000000, "?dn5,b,w", pa10, 0}, -{ "bb", 0xc0006000, 0xffe06000, "?Bnx,!,w", pa20, FLAG_STRICT}, -{ "bb", 0xc4004000, 0xfc004000, "?Bnx,B,w", pa20, FLAG_STRICT}, { "bb", 0xc0004000, 0xffe06000, "?bnx,!,w", pa10, FLAG_STRICT}, { "bb", 0xc4004000, 0xfc004000, "?bnx,Q,w", pa10, 0}, +{ "bb", 0xc0006000, 0xffe06000, "?Bnx,!,w", pa20, FLAG_STRICT}, +{ "bb", 0xc4004000, 0xfc004000, "?Bnx,B,w", pa20, FLAG_STRICT}, { "bvb", 0xc0004000, 0xffe04000, "?bnx,w", pa10, 0}, { "clrbts", 0xe8004005, 0xffffffff, "", pa20, FLAG_STRICT}, { "popbts", 0xe8004005, 0xfffff007, "$", pa20, FLAG_STRICT}, @@ -701,46 +703,46 @@ static const struct pa_opcode pa_opcodes[] = /* Floating Point Coprocessor Instructions. */ -{ "fldw", 0x24001020, 0xfc1f33a0, "cocc@(s,b),fT", pa20, FLAG_STRICT}, -{ "fldw", 0x24001020, 0xfc1f33a0, "cocc@(b),fT", pa20, FLAG_STRICT}, { "fldw", 0x24000000, 0xfc001380, "cxccx(s,b),fT", pa10, FLAG_STRICT}, { "fldw", 0x24000000, 0xfc001380, "cxccx(b),fT", pa10, FLAG_STRICT}, { "fldw", 0x24001000, 0xfc001380, "cmcc5(s,b),fT", pa10, FLAG_STRICT}, { "fldw", 0x24001000, 0xfc001380, "cmcc5(b),fT", pa10, FLAG_STRICT}, +{ "fldw", 0x24001020, 0xfc1f33a0, "cocc@(s,b),fT", pa20, FLAG_STRICT}, +{ "fldw", 0x24001020, 0xfc1f33a0, "cocc@(b),fT", pa20, FLAG_STRICT}, { "fldw", 0x5c000000, 0xfc000004, "y(b),fe", pa20w, FLAG_STRICT}, { "fldw", 0x58000000, 0xfc000000, "cJy(b),fe", pa20w, FLAG_STRICT}, { "fldw", 0x5c000000, 0xfc000004, "d(b),fe", pa20, FLAG_STRICT}, { "fldw", 0x58000000, 0xfc000000, "cJd(b),fe", pa20, FLAG_STRICT}, -{ "fldd", 0x2c001020, 0xfc1f33e0, "cocc@(s,b),ft", pa20, FLAG_STRICT}, -{ "fldd", 0x2c001020, 0xfc1f33e0, "cocc@(b),ft", pa20, FLAG_STRICT}, { "fldd", 0x2c000000, 0xfc0013c0, "cxccx(s,b),ft", pa10, FLAG_STRICT}, { "fldd", 0x2c000000, 0xfc0013c0, "cxccx(b),ft", pa10, FLAG_STRICT}, { "fldd", 0x2c001000, 0xfc0013c0, "cmcc5(s,b),ft", pa10, FLAG_STRICT}, { "fldd", 0x2c001000, 0xfc0013c0, "cmcc5(b),ft", pa10, FLAG_STRICT}, +{ "fldd", 0x2c001020, 0xfc1f33e0, "cocc@(s,b),ft", pa20, FLAG_STRICT}, +{ "fldd", 0x2c001020, 0xfc1f33e0, "cocc@(b),ft", pa20, FLAG_STRICT}, { "fldd", 0x50000002, 0xfc000002, "cq&(b),fx", pa20w, FLAG_STRICT}, { "fldd", 0x50000002, 0xfc000002, "cq#(b),fx", pa20, FLAG_STRICT}, -{ "fstw", 0x24001220, 0xfc1f33a0, "cocCfT,@(s,b)", pa10, FLAG_STRICT}, -{ "fstw", 0x24001220, 0xfc1f33a0, "cocCfT,@(b)", pa10, FLAG_STRICT}, { "fstw", 0x24000200, 0xfc001380, "cxcCfT,x(s,b)", pa10, FLAG_STRICT}, { "fstw", 0x24000200, 0xfc001380, "cxcCfT,x(b)", pa10, FLAG_STRICT}, { "fstw", 0x24001200, 0xfc001380, "cmcCfT,5(s,b)", pa10, FLAG_STRICT}, { "fstw", 0x24001200, 0xfc001380, "cmcCfT,5(b)", pa10, FLAG_STRICT}, +{ "fstw", 0x24001220, 0xfc1f33a0, "cocCfT,@(s,b)", pa10, FLAG_STRICT}, +{ "fstw", 0x24001220, 0xfc1f33a0, "cocCfT,@(b)", pa10, FLAG_STRICT}, { "fstw", 0x7c000000, 0xfc000004, "fE,y(b)", pa20w, FLAG_STRICT}, { "fstw", 0x78000000, 0xfc000000, "cJfe,y(b)", pa20w, FLAG_STRICT}, { "fstw", 0x7c000000, 0xfc000004, "fe,d(b)", pa20, FLAG_STRICT}, { "fstw", 0x78000000, 0xfc000000, "cJfe,d(b)", pa20, FLAG_STRICT}, -{ "fstd", 0x2c001220, 0xfc1f33e0, "cocCft,@(s,b)", pa10, FLAG_STRICT}, -{ "fstd", 0x2c001220, 0xfc1f33e0, "cocCft,@(b)", pa10, FLAG_STRICT}, { "fstd", 0x2c000200, 0xfc0013c0, "cxcCft,x(s,b)", pa10, FLAG_STRICT}, { "fstd", 0x2c000200, 0xfc0013c0, "cxcCft,x(b)", pa10, FLAG_STRICT}, { "fstd", 0x2c001200, 0xfc0013c0, "cmcCft,5(s,b)", pa10, FLAG_STRICT}, { "fstd", 0x2c001200, 0xfc0013c0, "cmcCft,5(b)", pa10, FLAG_STRICT}, +{ "fstd", 0x2c001220, 0xfc1f33e0, "cocCft,@(s,b)", pa10, FLAG_STRICT}, +{ "fstd", 0x2c001220, 0xfc1f33e0, "cocCft,@(b)", pa10, FLAG_STRICT}, { "fstd", 0x70000002, 0xfc000002, "cqfx,&(b)", pa20w, FLAG_STRICT}, { "fstd", 0x70000002, 0xfc000002, "cqfx,#(b)", pa20, FLAG_STRICT}, -{ "fldwx", 0x24000000, 0xfc001f80, "cxx(s,b),fT", pa10, 0}, -{ "fldwx", 0x24000000, 0xfc001f80, "cxx(b),fT", pa10, 0}, -{ "flddx", 0x2c000000, 0xfc001fc0, "cxx(s,b),ft", pa10, 0}, -{ "flddx", 0x2c000000, 0xfc001fc0, "cxx(b),ft", pa10, 0}, +{ "fldwx", 0x24000000, 0xfc001f80, "cXx(s,b),fT", pa10, 0}, +{ "fldwx", 0x24000000, 0xfc001f80, "cXx(b),fT", pa10, 0}, +{ "flddx", 0x2c000000, 0xfc001fc0, "cXx(s,b),ft", pa10, 0}, +{ "flddx", 0x2c000000, 0xfc001fc0, "cXx(b),ft", pa10, 0}, { "fstwx", 0x24000200, 0xfc001f80, "cxfT,x(s,b)", pa10, 0}, { "fstwx", 0x24000200, 0xfc001f80, "cxfT,x(b)", pa10, 0}, { "fstdx", 0x2c000200, 0xfc001fc0, "cxft,x(s,b)", pa10, 0}, @@ -815,38 +817,44 @@ static const struct pa_opcode pa_opcodes[] = { "spop2", 0x10000400, 0xfc000600, "v,1Nb", pa10, 0}, { "spop3", 0x10000600, 0xfc000600, "v,0Nx,b", pa10, 0}, { "copr", 0x30000000, 0xfc000000, "u,2N", pa10, 0}, -{ "cldwx", 0x24000000, 0xfc001e00, "ucxx(s,b),t", pa10, 0}, -{ "cldwx", 0x24000000, 0xfc001e00, "ucxx(b),t", pa10, 0}, -{ "clddx", 0x2c000000, 0xfc001e00, "ucxx(s,b),t", pa10, 0}, -{ "clddx", 0x2c000000, 0xfc001e00, "ucxx(b),t", pa10, 0}, -{ "cstwx", 0x24000200, 0xfc001e00, "ucxt,x(s,b)", pa10, 0}, -{ "cstwx", 0x24000200, 0xfc001e00, "ucxt,x(b)", pa10, 0}, -{ "cstdx", 0x2c000200, 0xfc001e00, "ucxt,x(s,b)", pa10, 0}, -{ "cstdx", 0x2c000200, 0xfc001e00, "ucxt,x(b)", pa10, 0}, -{ "cldws", 0x24001000, 0xfc001e00, "ucm5(s,b),t", pa10, 0}, -{ "cldws", 0x24001000, 0xfc001e00, "ucm5(b),t", pa10, 0}, -{ "cldds", 0x2c001000, 0xfc001e00, "ucm5(s,b),t", pa10, 0}, -{ "cldds", 0x2c001000, 0xfc001e00, "ucm5(b),t", pa10, 0}, -{ "cstws", 0x24001200, 0xfc001e00, "ucmt,5(s,b)", pa10, 0}, -{ "cstws", 0x24001200, 0xfc001e00, "ucmt,5(b)", pa10, 0}, -{ "cstds", 0x2c001200, 0xfc001e00, "ucmt,5(s,b)", pa10, 0}, -{ "cstds", 0x2c001200, 0xfc001e00, "ucmt,5(b)", pa10, 0}, -{ "cldw", 0x24000000, 0xfc001e00, "ucxx(s,b),t", pa10, FLAG_STRICT}, -{ "cldw", 0x24000000, 0xfc001e00, "ucxx(b),t", pa10, FLAG_STRICT}, -{ "cldw", 0x24001000, 0xfc001e00, "ucm5(s,b),t", pa10, FLAG_STRICT}, -{ "cldw", 0x24001000, 0xfc001e00, "ucm5(b),t", pa10, FLAG_STRICT}, -{ "cldd", 0x2c000000, 0xfc001e00, "ucxx(s,b),t", pa10, FLAG_STRICT}, -{ "cldd", 0x2c000000, 0xfc001e00, "ucxx(b),t", pa10, FLAG_STRICT}, -{ "cldd", 0x2c001000, 0xfc001e00, "ucm5(s,b),t", pa10, FLAG_STRICT}, -{ "cldd", 0x2c001000, 0xfc001e00, "ucm5(b),t", pa20, FLAG_STRICT}, -{ "cstw", 0x24000200, 0xfc001e00, "ucxt,x(s,b)", pa10, FLAG_STRICT}, -{ "cstw", 0x24000200, 0xfc001e00, "ucxt,x(b)", pa10, FLAG_STRICT}, -{ "cstw", 0x24001200, 0xfc001e00, "ucmt,5(s,b)", pa10, FLAG_STRICT}, -{ "cstw", 0x24001200, 0xfc001e00, "ucmt,5(b)", pa10, FLAG_STRICT}, -{ "cstd", 0x2c000200, 0xfc001e00, "ucxt,x(s,b)", pa10, FLAG_STRICT}, -{ "cstd", 0x2c000200, 0xfc001e00, "ucxt,x(b)", pa10, FLAG_STRICT}, -{ "cstd", 0x2c001200, 0xfc001e00, "ucmt,5(s,b)", pa10, FLAG_STRICT}, -{ "cstd", 0x2c001200, 0xfc001e00, "ucmt,5(b)", pa10, FLAG_STRICT}, +{ "cldwx", 0x24000000, 0xfc001e00, "ucXx(s,b),t", pa10, 0}, +{ "cldwx", 0x24000000, 0xfc001e00, "ucXx(b),t", pa10, 0}, +{ "clddx", 0x2c000000, 0xfc001e00, "ucXx(s,b),t", pa10, 0}, +{ "clddx", 0x2c000000, 0xfc001e00, "ucXx(b),t", pa10, 0}, +{ "cstwx", 0x24000200, 0xfc001e00, "ucXt,x(s,b)", pa10, 0}, +{ "cstwx", 0x24000200, 0xfc001e00, "ucXt,x(b)", pa10, 0}, +{ "cstdx", 0x2c000200, 0xfc001e00, "ucXt,x(s,b)", pa10, 0}, +{ "cstdx", 0x2c000200, 0xfc001e00, "ucXt,x(b)", pa10, 0}, +{ "cldws", 0x24001000, 0xfc001e00, "ucM5(s,b),t", pa10, 0}, +{ "cldws", 0x24001000, 0xfc001e00, "ucM5(b),t", pa10, 0}, +{ "cldds", 0x2c001000, 0xfc001e00, "ucM5(s,b),t", pa10, 0}, +{ "cldds", 0x2c001000, 0xfc001e00, "ucM5(b),t", pa10, 0}, +{ "cstws", 0x24001200, 0xfc001e00, "ucMt,5(s,b)", pa10, 0}, +{ "cstws", 0x24001200, 0xfc001e00, "ucMt,5(b)", pa10, 0}, +{ "cstds", 0x2c001200, 0xfc001e00, "ucMt,5(s,b)", pa10, 0}, +{ "cstds", 0x2c001200, 0xfc001e00, "ucMt,5(b)", pa10, 0}, +{ "cldw", 0x24000000, 0xfc001e00, "ucXx(s,b),t", pa10, FLAG_STRICT}, +{ "cldw", 0x24000000, 0xfc001e00, "ucXx(b),t", pa10, FLAG_STRICT}, +{ "cldw", 0x24001000, 0xfc001e00, "ucM5(s,b),t", pa10, FLAG_STRICT}, +{ "cldw", 0x24001000, 0xfc001e00, "ucM5(b),t", pa10, FLAG_STRICT}, +{ "cldd", 0x2c000000, 0xfc001e00, "ucXx(s,b),t", pa10, FLAG_STRICT}, +{ "cldd", 0x2c000000, 0xfc001e00, "ucXx(b),t", pa10, FLAG_STRICT}, +{ "cldd", 0x2c001000, 0xfc001e00, "ucM5(s,b),t", pa10, FLAG_STRICT}, +{ "cldd", 0x2c001000, 0xfc001e00, "ucM5(b),t", pa20, FLAG_STRICT}, +{ "cstw", 0x24000200, 0xfc001e00, "ucXt,x(s,b)", pa10, FLAG_STRICT}, +{ "cstw", 0x24000200, 0xfc001e00, "ucXt,x(b)", pa10, FLAG_STRICT}, +{ "cstw", 0x24001200, 0xfc001e00, "ucMt,5(s,b)", pa10, FLAG_STRICT}, +{ "cstw", 0x24001200, 0xfc001e00, "ucMt,5(b)", pa10, FLAG_STRICT}, +{ "cstd", 0x2c000200, 0xfc001e00, "ucXt,x(s,b)", pa10, FLAG_STRICT}, +{ "cstd", 0x2c000200, 0xfc001e00, "ucXt,x(b)", pa10, FLAG_STRICT}, +{ "cstd", 0x2c001200, 0xfc001e00, "ucMt,5(s,b)", pa10, FLAG_STRICT}, +{ "cstd", 0x2c001200, 0xfc001e00, "ucMt,5(b)", pa10, FLAG_STRICT}, + +/* More pseudo instructions which must follow the main table. */ +{ "call", 0xe800f000, 0xfc1ffffd, "n(b)", pa20, FLAG_STRICT}, +{ "call", 0xe800a000, 0xffe0e000, "nW", pa10, FLAG_STRICT}, +{ "ret", 0xe840d000, 0xfffffffd, "n", pa20, FLAG_STRICT}, + }; #define NUMOPCODES ((sizeof pa_opcodes)/(sizeof pa_opcodes[0])) diff --git a/gnu/dist/toolchain/include/opcode/i386.h b/gnu/dist/toolchain/include/opcode/i386.h index 38de44aca0a..71c204c81f5 100644 --- a/gnu/dist/toolchain/include/opcode/i386.h +++ b/gnu/dist/toolchain/include/opcode/i386.h @@ -62,6 +62,7 @@ static const template i386_optab[] = { #define wl_Suf (No_bSuf|No_sSuf|No_xSuf|No_qSuf) #define wlq_Suf (No_bSuf|No_sSuf|No_xSuf) #define lq_Suf (No_bSuf|No_wSuf|No_sSuf|No_xSuf) +#define wq_Suf (No_bSuf|No_lSuf|No_sSuf|No_xSuf) #define sl_Suf (No_bSuf|No_wSuf|No_xSuf|No_qSuf) #define sldx_Suf (No_bSuf|No_wSuf|No_qSuf) #define bwl_Suf (No_sSuf|No_xSuf|No_qSuf) @@ -120,9 +121,9 @@ static const template i386_optab[] = { {"movslq", 2, 0x63, X, Cpu64, NoSuf|Modrm|Rex64, { Reg32|WordMem, Reg64, 0} }, /* Intel Syntax next 5 insns */ {"movsx", 2, 0x0fbe, X, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, WordReg, 0} }, -{"movsx", 2, 0x0fbf, X, Cpu386, w_Suf|Modrm|IgnoreSize, { Reg16|ShortMem, Reg32, 0} }, +{"movsx", 2, 0x0fbf, X, Cpu386, w_Suf|Modrm, { Reg16|ShortMem, Reg32, 0} }, {"movsx", 2, 0x0fbe, X, Cpu64, b_Suf|Modrm|Rex64, { Reg8|ByteMem, Reg64, 0} }, -{"movsx", 2, 0x0fbf, X, Cpu64, w_Suf|Modrm|IgnoreSize|Rex64, { Reg16|ShortMem, Reg64, 0} }, +{"movsx", 2, 0x0fbf, X, Cpu64, w_Suf|Modrm|Rex64, { Reg16|ShortMem, Reg64, 0} }, {"movsx", 2, 0x63, X, Cpu64, l_Suf|Modrm|Rex64, { Reg32|WordMem, Reg64, 0} }, /* Move with zero extend. */ @@ -134,11 +135,11 @@ static const template i386_optab[] = { {"movzwq", 2, 0x0fb7, X, Cpu64, NoSuf|Modrm|Rex64, { Reg16|ShortMem, Reg64, 0} }, /* Intel Syntax next 4 insns */ {"movzx", 2, 0x0fb6, X, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, WordReg, 0} }, -{"movzx", 2, 0x0fb7, X, Cpu386, w_Suf|Modrm|IgnoreSize, { Reg16|ShortMem, Reg32, 0} }, +{"movzx", 2, 0x0fb7, X, Cpu386, w_Suf|Modrm, { Reg16|ShortMem, Reg32, 0} }, /* These instructions are not particulary usefull, since the zero extend 32->64 is implicit, but we can encode them. */ {"movzx", 2, 0x0fb6, X, Cpu386, b_Suf|Modrm|Rex64, { Reg8|ByteMem, Reg64, 0} }, -{"movzx", 2, 0x0fb7, X, Cpu386, w_Suf|Modrm|IgnoreSize|Rex64, { Reg16|ShortMem, Reg64, 0} }, +{"movzx", 2, 0x0fb7, X, Cpu386, w_Suf|Modrm|Rex64, { Reg16|ShortMem, Reg64, 0} }, /* Push instructions. */ {"push", 1, 0x50, X, CpuNo64, wl_Suf|ShortForm|DefaultSize, { WordReg, 0, 0 } }, @@ -148,12 +149,12 @@ static const template i386_optab[] = { {"push", 1, 0x06, X, 0|CpuNo64, wl_Suf|Seg2ShortForm|DefaultSize, { SReg2, 0, 0 } }, {"push", 1, 0x0fa0, X, Cpu386|CpuNo64, wl_Suf|Seg3ShortForm|DefaultSize, { SReg3, 0, 0 } }, /* In 64bit mode, the operand size is implicitly 64bit. */ -{"push", 1, 0x50, X, Cpu64, q_Suf|ShortForm|DefaultSize|NoRex64, { Reg64, 0, 0 } }, -{"push", 1, 0xff, 6, Cpu64, q_Suf|Modrm|DefaultSize|NoRex64, { Reg64|WordMem, 0, 0 } }, -{"push", 1, 0x6a, X, Cpu186|Cpu64, q_Suf|DefaultSize|NoRex64, { Imm8S, 0, 0} }, -{"push", 1, 0x68, X, Cpu186|Cpu64, q_Suf|DefaultSize|NoRex64, { Imm32S, 0, 0} }, -{"push", 1, 0x06, X, Cpu64, q_Suf|Seg2ShortForm|DefaultSize|NoRex64, { SReg2, 0, 0 } }, -{"push", 1, 0x0fa0, X, Cpu386|Cpu64, q_Suf|Seg3ShortForm|DefaultSize|NoRex64, { SReg3, 0, 0 } }, +{"push", 1, 0x50, X, Cpu64, wq_Suf|ShortForm|DefaultSize|NoRex64, { WordReg, 0, 0 } }, +{"push", 1, 0xff, 6, Cpu64, wq_Suf|Modrm|DefaultSize|NoRex64, { WordReg|WordMem, 0, 0 } }, +{"push", 1, 0x6a, X, Cpu186|Cpu64, wq_Suf|DefaultSize|NoRex64, { Imm8S, 0, 0} }, +{"push", 1, 0x68, X, Cpu186|Cpu64, wq_Suf|DefaultSize|NoRex64, { Imm32S|Imm16, 0, 0} }, +{"push", 1, 0x06, X, Cpu64, wq_Suf|Seg2ShortForm|DefaultSize|NoRex64, { SReg2, 0, 0 } }, +{"push", 1, 0x0fa0, X, Cpu386|Cpu64, wq_Suf|Seg3ShortForm|DefaultSize|NoRex64, { SReg3, 0, 0 } }, {"pusha", 0, 0x60, X, Cpu186|CpuNo64, wl_Suf|DefaultSize, { 0, 0, 0 } }, @@ -164,10 +165,10 @@ static const template i386_optab[] = { {"pop", 1, 0x07, X, CpuNo64, wl_Suf|Seg2ShortForm|DefaultSize, { SReg2, 0, 0 } }, {"pop", 1, 0x0fa1, X, Cpu386|CpuNo64, wl_Suf|Seg3ShortForm|DefaultSize, { SReg3, 0, 0 } }, /* In 64bit mode, the operand size is implicitly 64bit. */ -{"pop", 1, 0x58, X, Cpu64, q_Suf|ShortForm|DefaultSize|NoRex64, { Reg64, 0, 0 } }, -{"pop", 1, 0x8f, 0, Cpu64, q_Suf|Modrm|DefaultSize|NoRex64, { Reg64|WordMem, 0, 0 } }, -{"pop", 1, 0x07, X, Cpu64, q_Suf|Seg2ShortForm|DefaultSize|NoRex64, { SReg2, 0, 0 } }, -{"pop", 1, 0x0fa1, X, Cpu64, q_Suf|Seg3ShortForm|DefaultSize|NoRex64, { SReg3, 0, 0 } }, +{"pop", 1, 0x58, X, Cpu64, wq_Suf|ShortForm|DefaultSize|NoRex64, { WordReg, 0, 0 } }, +{"pop", 1, 0x8f, 0, Cpu64, wq_Suf|Modrm|DefaultSize|NoRex64, { WordReg|WordMem, 0, 0 } }, +{"pop", 1, 0x07, X, Cpu64, wq_Suf|Seg2ShortForm|DefaultSize|NoRex64, { SReg2, 0, 0 } }, +{"pop", 1, 0x0fa1, X, Cpu64, wq_Suf|Seg3ShortForm|DefaultSize|NoRex64, { SReg3, 0, 0 } }, {"popa", 0, 0x61, X, Cpu186|CpuNo64, wl_Suf|DefaultSize, { 0, 0, 0 } }, @@ -176,20 +177,20 @@ static const template i386_optab[] = { In the 64bit code, xchg eax, eax is reused for new nop instruction. */ -{"xchg", 2, 0x90, X, CpuNo64, wl_Suf|ShortForm, { WordReg, Acc, 0 } }, -{"xchg", 2, 0x90, X, CpuNo64, wl_Suf|ShortForm, { Acc, WordReg, 0 } }, +{"xchg", 2, 0x90, X, 0, wlq_Suf|ShortForm, { WordReg, Acc, 0 } }, +{"xchg", 2, 0x90, X, 0, wlq_Suf|ShortForm, { Acc, WordReg, 0 } }, {"xchg", 2, 0x86, X, 0, bwlq_Suf|W|Modrm, { Reg, Reg|AnyMem, 0 } }, {"xchg", 2, 0x86, X, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, Reg, 0 } }, /* In/out from ports. */ -{"in", 2, 0xe4, X, 0, bwlq_Suf|W, { Imm8, Acc, 0 } }, -{"in", 2, 0xec, X, 0, bwlq_Suf|W, { InOutPortReg, Acc, 0 } }, -{"in", 1, 0xe4, X, 0, bwlq_Suf|W, { Imm8, 0, 0 } }, -{"in", 1, 0xec, X, 0, bwlq_Suf|W, { InOutPortReg, 0, 0 } }, -{"out", 2, 0xe6, X, 0, bwlq_Suf|W, { Acc, Imm8, 0 } }, -{"out", 2, 0xee, X, 0, bwlq_Suf|W, { Acc, InOutPortReg, 0 } }, -{"out", 1, 0xe6, X, 0, bwlq_Suf|W, { Imm8, 0, 0 } }, -{"out", 1, 0xee, X, 0, bwlq_Suf|W, { InOutPortReg, 0, 0 } }, +{"in", 2, 0xe4, X, 0, bwl_Suf|W, { Imm8, Acc, 0 } }, +{"in", 2, 0xec, X, 0, bwl_Suf|W, { InOutPortReg, Acc, 0 } }, +{"in", 1, 0xe4, X, 0, bwl_Suf|W, { Imm8, 0, 0 } }, +{"in", 1, 0xec, X, 0, bwl_Suf|W, { InOutPortReg, 0, 0 } }, +{"out", 2, 0xe6, X, 0, bwl_Suf|W, { Acc, Imm8, 0 } }, +{"out", 2, 0xee, X, 0, bwl_Suf|W, { Acc, InOutPortReg, 0 } }, +{"out", 1, 0xe6, X, 0, bwl_Suf|W, { Imm8, 0, 0 } }, +{"out", 1, 0xee, X, 0, bwl_Suf|W, { InOutPortReg, 0, 0 } }, /* Load effective address. */ {"lea", 2, 0x8d, X, 0, wlq_Suf|Modrm, { WordMem, WordReg, 0 } }, @@ -210,9 +211,9 @@ static const template i386_optab[] = { {"lahf", 0, 0x9f, X, CpuNo64,NoSuf, { 0, 0, 0} }, {"sahf", 0, 0x9e, X, CpuNo64,NoSuf, { 0, 0, 0} }, {"pushf", 0, 0x9c, X, CpuNo64,wlq_Suf|DefaultSize, { 0, 0, 0} }, -{"pushf", 0, 0x9c, X, Cpu64, q_Suf|DefaultSize|NoRex64,{ 0, 0, 0} }, +{"pushf", 0, 0x9c, X, Cpu64, wq_Suf|DefaultSize|NoRex64,{ 0, 0, 0} }, {"popf", 0, 0x9d, X, CpuNo64,wlq_Suf|DefaultSize, { 0, 0, 0} }, -{"popf", 0, 0x9d, X, Cpu64, q_Suf|DefaultSize|NoRex64,{ 0, 0, 0} }, +{"popf", 0, 0x9d, X, Cpu64, wq_Suf|DefaultSize|NoRex64,{ 0, 0, 0} }, {"stc", 0, 0xf9, X, 0, NoSuf, { 0, 0, 0} }, {"std", 0, 0xfd, X, 0, NoSuf, { 0, 0, 0} }, {"sti", 0, 0xfb, X, 0, NoSuf, { 0, 0, 0} }, @@ -370,7 +371,8 @@ static const template i386_optab[] = { /* Control transfer instructions. */ {"call", 1, 0xe8, X, 0, wlq_Suf|JumpDword|DefaultSize, { Disp16|Disp32, 0, 0} }, -{"call", 1, 0xff, 2, 0, wlq_Suf|Modrm|DefaultSize, { WordReg|WordMem|JumpAbsolute, 0, 0} }, +{"call", 1, 0xff, 2, CpuNo64, wl_Suf|Modrm|DefaultSize, { WordReg|WordMem|JumpAbsolute, 0, 0} }, +{"call", 1, 0xff, 2, Cpu64, wq_Suf|Modrm|DefaultSize|NoRex64,{ WordReg|WordMem|JumpAbsolute, 0, 0} }, /* Intel Syntax */ {"call", 2, 0x9a, X, CpuNo64,wlq_Suf|JumpInterSegment|DefaultSize, { Imm16, Imm16|Imm32, 0} }, /* Intel Syntax */ @@ -381,7 +383,8 @@ static const template i386_optab[] = { #define JUMP_PC_RELATIVE 0xeb {"jmp", 1, 0xeb, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"jmp", 1, 0xff, 4, 0, wlq_Suf|Modrm, { WordReg|WordMem|JumpAbsolute, 0, 0} }, +{"jmp", 1, 0xff, 4, CpuNo64, wl_Suf|Modrm, { WordReg|WordMem|JumpAbsolute, 0, 0} }, +{"jmp", 1, 0xff, 4, Cpu64, wq_Suf|Modrm|NoRex64, { WordReg|WordMem|JumpAbsolute, 0, 0} }, /* Intel Syntax */ {"jmp", 2, 0xea, X, CpuNo64,wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} }, /* Intel Syntax */ @@ -432,18 +435,25 @@ static const template i386_optab[] = { {"jg", 1, 0x7f, X, 0, NoSuf|Jump, { Disp, 0, 0} }, /* jcxz vs. jecxz is chosen on the basis of the address size prefix. */ -{"jcxz", 1, 0xe3, X, 0, NoSuf|JumpByte|Size16, { Disp, 0, 0} }, -{"jecxz", 1, 0xe3, X, 0, NoSuf|JumpByte|Size32, { Disp, 0, 0} }, +{"jcxz", 1, 0xe3, X, CpuNo64,NoSuf|JumpByte|Size16, { Disp, 0, 0} }, +{"jecxz", 1, 0xe3, X, CpuNo64,NoSuf|JumpByte|Size32, { Disp, 0, 0} }, +{"jecxz", 1, 0x67e3, X, Cpu64,NoSuf|JumpByte|Size32, { Disp, 0, 0} }, +{"jrcxz", 1, 0xe3, X, Cpu64, NoSuf|JumpByte|Size64|NoRex64, { Disp, 0, 0} }, /* The loop instructions also use the address size prefix to select %cx rather than %ecx for the loop count, so the `w' form of these instructions emit an address size prefix rather than a data size prefix. */ -{"loop", 1, 0xe2, X, 0, wlq_Suf|JumpByte, { Disp, 0, 0} }, -{"loopz", 1, 0xe1, X, 0, wlq_Suf|JumpByte, { Disp, 0, 0} }, -{"loope", 1, 0xe1, X, 0, wlq_Suf|JumpByte, { Disp, 0, 0} }, -{"loopnz", 1, 0xe0, X, 0, wlq_Suf|JumpByte, { Disp, 0, 0} }, -{"loopne", 1, 0xe0, X, 0, wlq_Suf|JumpByte, { Disp, 0, 0} }, +{"loop", 1, 0xe2, X, CpuNo64,wl_Suf|JumpByte,{ Disp, 0, 0} }, +{"loop", 1, 0xe2, X, Cpu64, lq_Suf|JumpByte|NoRex64,{ Disp, 0, 0} }, +{"loopz", 1, 0xe1, X, CpuNo64,wl_Suf|JumpByte,{ Disp, 0, 0} }, +{"loopz", 1, 0xe1, X, Cpu64, lq_Suf|JumpByte|NoRex64,{ Disp, 0, 0} }, +{"loope", 1, 0xe1, X, CpuNo64,wl_Suf|JumpByte,{ Disp, 0, 0} }, +{"loope", 1, 0xe1, X, Cpu64, lq_Suf|JumpByte|NoRex64,{ Disp, 0, 0} }, +{"loopnz", 1, 0xe0, X, CpuNo64,wl_Suf|JumpByte,{ Disp, 0, 0} }, +{"loopnz", 1, 0xe0, X, Cpu64, lq_Suf|JumpByte|NoRex64,{ Disp, 0, 0} }, +{"loopne", 1, 0xe0, X, CpuNo64,wl_Suf|JumpByte,{ Disp, 0, 0} }, +{"loopne", 1, 0xe0, X, Cpu64, lq_Suf|JumpByte|NoRex64,{ Disp, 0, 0} }, /* Set byte on flag instructions. */ {"seto", 1, 0x0f90, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, @@ -482,10 +492,10 @@ static const template i386_optab[] = { {"cmps", 2, 0xa6, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, AnyMem, 0} }, {"scmp", 0, 0xa6, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} }, {"scmp", 2, 0xa6, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, AnyMem, 0} }, -{"ins", 0, 0x6c, X, Cpu186, bwlq_Suf|W|IsString, { 0, 0, 0} }, -{"ins", 2, 0x6c, X, Cpu186, bwlq_Suf|W|IsString, { InOutPortReg, AnyMem|EsSeg, 0} }, -{"outs", 0, 0x6e, X, Cpu186, bwlq_Suf|W|IsString, { 0, 0, 0} }, -{"outs", 2, 0x6e, X, Cpu186, bwlq_Suf|W|IsString, { AnyMem, InOutPortReg, 0} }, +{"ins", 0, 0x6c, X, Cpu186, bwl_Suf|W|IsString, { 0, 0, 0} }, +{"ins", 2, 0x6c, X, Cpu186, bwl_Suf|W|IsString, { InOutPortReg, AnyMem|EsSeg, 0} }, +{"outs", 0, 0x6e, X, Cpu186, bwl_Suf|W|IsString, { 0, 0, 0} }, +{"outs", 2, 0x6e, X, Cpu186, bwl_Suf|W|IsString, { AnyMem, InOutPortReg, 0} }, {"lods", 0, 0xac, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} }, {"lods", 1, 0xac, X, 0, bwlq_Suf|W|IsString, { AnyMem, 0, 0} }, {"lods", 2, 0xac, X, 0, bwlq_Suf|W|IsString, { AnyMem, Acc, 0} }, @@ -553,9 +563,12 @@ static const template i386_optab[] = { {"sgdt", 1, 0x0f01, 0, Cpu286, wlq_Suf|Modrm, { WordMem, 0, 0} }, {"sidt", 1, 0x0f01, 1, Cpu286, wlq_Suf|Modrm, { WordMem, 0, 0} }, -{"sldt", 1, 0x0f00, 0, Cpu286, wlq_Suf|Modrm, { WordReg|WordMem, 0, 0} }, -{"smsw", 1, 0x0f01, 4, Cpu286, wlq_Suf|Modrm, { WordReg|WordMem, 0, 0} }, -{"str", 1, 0x0f00, 1, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, +{"sldt", 1, 0x0f00, 0, Cpu286, wlq_Suf|Modrm, { WordReg|InvMem, 0, 0} }, +{"sldt", 1, 0x0f00, 0, Cpu286, w_Suf|Modrm|IgnoreSize,{ ShortMem, 0, 0} }, +{"smsw", 1, 0x0f01, 4, Cpu286, wlq_Suf|Modrm, { WordReg|InvMem, 0, 0} }, +{"smsw", 1, 0x0f01, 4, Cpu286, w_Suf|Modrm|IgnoreSize,{ ShortMem, 0, 0} }, +{"str", 1, 0x0f00, 1, Cpu286, wlq_Suf|Modrm, { WordReg|InvMem, 0, 0} }, +{"str", 1, 0x0f00, 1, Cpu286, w_Suf|Modrm|IgnoreSize,{ ShortMem, 0, 0} }, {"verr", 1, 0x0f00, 4, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, {"verw", 1, 0x0f00, 5, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, @@ -968,12 +981,16 @@ static const template i386_optab[] = { {"movd", 2, 0x660f6e,X,CpuSSE2,FP|Modrm, { Reg32|LLongMem, RegXMM, 0 } }, {"movd", 2, 0x660f7e,X,CpuSSE2,FP|Modrm, { RegXMM, Reg32|LLongMem, 0 } }, /* Real MMX instructions. */ +{"movd", 2, 0x0f6e, X, CpuMMX, FP|Modrm, { Reg64|LLongMem, RegMMX, 0 } }, +{"movd", 2, 0x0f7e, X, CpuMMX, FP|Modrm, { RegMMX, Reg64|LLongMem, 0 } }, +{"movd", 2, 0x660f6e,X,CpuSSE2,FP|Modrm, { Reg64|LLongMem, RegXMM, 0 } }, +{"movd", 2, 0x660f7e,X,CpuSSE2,FP|Modrm, { RegXMM, Reg64|LLongMem, 0 } }, +/* In the 64bit mode the short form mov immediate is redefined to have + 64bit displacement value. */ {"movq", 2, 0x0f6f, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, {"movq", 2, 0x0f7f, X, CpuMMX, FP|Modrm, { RegMMX, RegMMX|LongMem, 0 } }, {"movq", 2, 0xf30f7e,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, {"movq", 2, 0x660fd6,X,CpuSSE2,FP|Modrm, { RegXMM, RegXMM|LLongMem, 0 } }, -/* In the 64bit mode the short form mov immediate is redefined to have - 64bit displacement value. */ {"movq", 2, 0x88, X, Cpu64, NoSuf|D|W|Modrm|Size64,{ Reg64, Reg64|AnyMem, 0 } }, {"movq", 2, 0xc6, 0, Cpu64, NoSuf|W|Modrm|Size64, { Imm32S, Reg64|WordMem, 0 } }, {"movq", 2, 0xb0, X, Cpu64, NoSuf|W|ShortForm|Size64,{ Imm64, Reg64, 0 } }, @@ -1137,7 +1154,7 @@ static const template i386_optab[] = { {"movlhps", 2, 0x0f16, X, CpuSSE, FP|Modrm, { RegXMM|InvMem, RegXMM, 0 } }, {"movlps", 2, 0x0f12, X, CpuSSE, FP|Modrm, { LLongMem, RegXMM, 0 } }, {"movlps", 2, 0x0f13, X, CpuSSE, FP|Modrm, { RegXMM, LLongMem, 0 } }, -{"movmskps", 2, 0x0f50, X, CpuSSE, FP|Modrm, { RegXMM|InvMem, Reg32, 0 } }, +{"movmskps", 2, 0x0f50, X, CpuSSE, lq_Suf|IgnoreSize|Modrm, { RegXMM|InvMem, Reg32|Reg64, 0 } }, {"movntps", 2, 0x0f2b, X, CpuSSE, FP|Modrm, { RegXMM, LLongMem, 0 } }, {"movntq", 2, 0x0fe7, X, CpuSSE, FP|Modrm, { RegMMX, LLongMem, 0 } }, {"movntdq", 2, 0x660fe7, X, CpuSSE2,FP|Modrm, { RegXMM, LLongMem, 0 } }, @@ -1152,10 +1169,10 @@ static const template i386_optab[] = { {"pavgb", 2, 0x660fe0, X, CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, {"pavgw", 2, 0x0fe3, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, {"pavgw", 2, 0x660fe3, X, CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pextrw", 3, 0x0fc5, X, CpuSSE, FP|Modrm, { Imm8, RegMMX|InvMem, Reg32 } }, -{"pextrw", 3, 0x660fc5, X, CpuSSE2,FP|Modrm, { Imm8, RegXMM|InvMem, Reg32 } }, -{"pinsrw", 3, 0x0fc4, X, CpuSSE, FP|Modrm, { Imm8, Reg32|ShortMem, RegMMX } }, -{"pinsrw", 3, 0x660fc4, X, CpuSSE2, FP|Modrm, { Imm8, Reg32|ShortMem, RegXMM } }, +{"pextrw", 3, 0x0fc5, X, CpuSSE, lq_Suf|IgnoreSize|Modrm, { Imm8, RegMMX|InvMem, Reg32|Reg64 } }, +{"pextrw", 3, 0x660fc5, X, CpuSSE2,lq_Suf|IgnoreSize|Modrm, { Imm8, RegXMM|InvMem, Reg32|Reg64 } }, +{"pinsrw", 3, 0x0fc4, X, CpuSSE, lq_Suf|IgnoreSize|Modrm, { Imm8, Reg32|Reg64|ShortMem, RegMMX } }, +{"pinsrw", 3, 0x660fc4, X, CpuSSE2, lq_Suf|IgnoreSize|Modrm, { Imm8, Reg32|Reg64|ShortMem, RegXMM } }, {"pmaxsw", 2, 0x0fee, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, {"pmaxsw", 2, 0x660fee, X, CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, {"pmaxub", 2, 0x0fde, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, @@ -1164,8 +1181,8 @@ static const template i386_optab[] = { {"pminsw", 2, 0x660fea, X, CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, {"pminub", 2, 0x0fda, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, {"pminub", 2, 0x660fda, X, CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pmovmskb", 2, 0x0fd7, X, CpuSSE, FP|Modrm, { RegMMX|InvMem, Reg32, 0 } }, -{"pmovmskb", 2, 0x660fd7, X, CpuSSE2,FP|Modrm, { RegXMM|InvMem, Reg32, 0 } }, +{"pmovmskb", 2, 0x0fd7, X, CpuSSE, lq_Suf|IgnoreSize|Modrm, { RegMMX|InvMem, Reg32|Reg64, 0 } }, +{"pmovmskb", 2, 0x660fd7, X, CpuSSE2,lq_Suf|IgnoreSize|Modrm, { RegXMM|InvMem, Reg32|Reg64, 0 } }, {"pmulhuw", 2, 0x0fe4, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, {"pmulhuw", 2, 0x660fe4, X, CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, {"prefetchnta", 1, 0x0f18, 0, CpuSSE, FP|Modrm, { LLongMem, 0, 0 } }, @@ -1214,6 +1231,9 @@ static const template i386_optab[] = { {"cmpunordpd",2, 0x660fc2, 3, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } }, {"cmpunordsd",2, 0xf20fc2, 3, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } }, {"cmppd", 3, 0x660fc2, X, CpuSSE2, FP|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, +/* Intel mode string compare. */ +{"cmpsd", 0, 0xa7, X, 0, NoSuf|Size32|IsString, { 0, 0, 0} }, +{"cmpsd", 2, 0xa7, X, 0, NoSuf|Size32|IsString, { AnyMem, AnyMem|EsSeg, 0} }, {"cmpsd", 3, 0xf20fc2, X, CpuSSE2, FP|Modrm, { Imm8, RegXMM|LongMem, RegXMM } }, {"comisd", 2, 0x660f2f, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, {"cvtpi2pd", 2, 0x660f2a, X, CpuSSE2, FP|Modrm, { RegMMX|LLongMem, RegXMM, 0 } }, @@ -1230,8 +1250,11 @@ static const template i386_optab[] = { {"movhpd", 2, 0x660f17, X, CpuSSE2, FP|Modrm, { RegXMM, LLongMem, 0 } }, {"movlpd", 2, 0x660f12, X, CpuSSE2, FP|Modrm, { LLongMem, RegXMM, 0 } }, {"movlpd", 2, 0x660f13, X, CpuSSE2, FP|Modrm, { RegXMM, LLongMem, 0 } }, -{"movmskpd", 2, 0x660f50, X, CpuSSE2, FP|Modrm, { RegXMM|InvMem, Reg32, 0 } }, +{"movmskpd", 2, 0x660f50, X, CpuSSE2, lq_Suf|IgnoreSize|Modrm, { RegXMM|InvMem, Reg32|Reg64, 0 } }, {"movntpd", 2, 0x660f2b, X, CpuSSE2, FP|Modrm, { RegXMM, LLongMem, 0 } }, +/* Intel mode string move. */ +{"movsd", 0, 0xa5, X, 0, NoSuf|Size32|IsString, { 0, 0, 0} }, +{"movsd", 2, 0xa5, X, 0, NoSuf|Size32|IsString, { AnyMem, AnyMem|EsSeg, 0} }, {"movsd", 2, 0xf20f10, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, {"movsd", 2, 0xf20f11, X, CpuSSE2, FP|Modrm, { RegXMM, RegXMM|LongMem, 0 } }, {"movupd", 2, 0x660f10, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, diff --git a/gnu/dist/toolchain/include/opcode/ia64.h b/gnu/dist/toolchain/include/opcode/ia64.h index 642330cc118..d4e6d108137 100644 --- a/gnu/dist/toolchain/include/opcode/ia64.h +++ b/gnu/dist/toolchain/include/opcode/ia64.h @@ -1,5 +1,5 @@ /* ia64.h -- Header file for ia64 opcode table - Copyright (C) 1998, 1999 David Mosberger-Tang <davidm@hpl.hp.com> + Copyright (C) 1998, 1999, 2002 David Mosberger-Tang <davidm@hpl.hp.com> See the file HP-COPYRIGHT for additional information. */ @@ -8,7 +8,7 @@ #include <sys/types.h> -#include <bfd.h> +#include "bfd.h" typedef BFD_HOST_U_64_BIT ia64_insn; diff --git a/gnu/dist/toolchain/include/opcode/m88k.h b/gnu/dist/toolchain/include/opcode/m88k.h index 9d403e1fc69..3dd5b733d84 100644 --- a/gnu/dist/toolchain/include/opcode/m88k.h +++ b/gnu/dist/toolchain/include/opcode/m88k.h @@ -1,5 +1,5 @@ -/* Table of opcodes for the motorola 88k family. - Copyright 1989, 1990, 1991, 1993 Free Software Foundation, Inc. +/* Table of opcodes for the Motorola M88k family. + Copyright 1989, 1990, 1991, 1993, 2001 Free Software Foundation, Inc. This file is part of GDB and GAS. @@ -34,22 +34,6 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ * pointer to the next instruction in the linked list. These pointers * are initialized by init_disasm(). * - * Structure Format - * - * struct INSTAB { - * UPINT opcode; - * char *mnemonic; - * struct OPSPEC op1,op2,op3; - * struct SIM_FLAGS flgs; - * struct INSTAB *next; - * } - * - * struct OPSPEC { - * UPINT offset:5; - * UPINT width:6; - * UPINT type:5; - * } - * * Revision History * * Revision 1.0 11/08/85 Creation date @@ -61,54 +45,52 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include <stdio.h> +/* Define the number of bits in the primary opcode field of the instruction, + the destination field, the source 1 and source 2 fields. */ -/* - * This file contains the structures and constants needed to build the M88000 - * simulator. It is the main include file, containing all the - * structures, macros and definitions except for the floating point - * instruction set. - */ - -/* - * The following flag informs the Simulator as to what type of byte ordering - * will be used. For instance, a BOFLAG = 1 indicates a DEC VAX and IBM type - * of ordering shall be used. -*/ +/* Size of opcode field. */ +#define OP 8 -/* # define BOFLAG 1 */ /* BYTE ORDERING FLAG */ +/* Size of destination. */ +#define DEST 6 -/* define the number of bits in the primary opcode field of the instruction, - * the destination field, the source 1 and source 2 fields. - */ -# define OP 8 /* size of opcode field */ -# define DEST 6 /* size of destination */ -# define SOURCE1 6 /* size of source1 */ -# define SOURCE2 6 /* size of source2 */ +/* Size of source1. */ +#define SOURCE1 6 -# define REGs 32 /* number of registers */ +/* Size of source2. */ +#define SOURCE2 6 -# define WORD long -# define FLAG unsigned -# define STATE short +/* Number of registers. */ +#define REGs 32 -# define TRUE 1 -# define FALSE 0 +/* Type definitions. */ -# define READ 0 -# define WRITE 1 +typedef unsigned int UINT; +#define WORD long +#define FLAG unsigned +#define STATE short /* The next four equates define the priorities that the various classes * of instructions have regarding writing results back into registers and - * signalling exceptions. - */ + * signalling exceptions. */ + /* PMEM is also defined in <sys/param.h> on Delta 88's. Sigh! */ #undef PMEM -# define PINT 0 /* Integer Priority */ -# define PFLT 1 /* Floating Point Priority */ -# define PMEM 2 /* Memory Priority */ -# define NA 3 /* Not Applicable, instruction doesnt write to regs */ -# define HIPRI 3 /* highest of these priorities */ +/* Integer priority. */ +#define PINT 0 + +/* Floating point priority. */ +#define PFLT 1 + +/* Memory priority. */ +#define PMEM 2 + +/* Not applicable, instruction doesn't write to regs. */ +#define NA 3 + +/* Highest of these priorities. */ +#define HIPRI 3 /* The instruction registers are an artificial mechanism to speed up * simulator execution. In the real processor, an instruction register @@ -122,231 +104,267 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ * Yes this wastes memory, but it executes much quicker. */ -struct IR_FIELDS { - unsigned op:OP, - dest: DEST, - src1: SOURCE1, - src2: SOURCE2; - int ltncy, - extime, - wb_pri; /* writeback priority */ - unsigned imm_flags:2,/* immediate size */ - rs1_used:1, /* register source 1 used */ - rs2_used:1, /* register source 2 used */ - rsd_used:1, /* register source/dest. used */ - c_flag:1, /* complement */ - u_flag:1, /* upper half word */ - n_flag:1, /* execute next */ - wb_flag:1, /* uses writeback slot */ - dest_64:1, /* dest size */ - s1_64:1, /* source 1 size */ - s2_64:1, /* source 2 size */ - scale_flag:1, /* scaled register */ - brk_flg:1; - }; - -struct mem_segs { - struct mem_wrd *seg; /* pointer (returned by calloc) to segment */ - unsigned long baseaddr; /* base load address from file headers */ - unsigned long endaddr; /* Ending address of segment */ - int flags; /* segment control flags (none defined 12/5/86) */ +struct IR_FIELDS +{ + unsigned op:OP, + dest: DEST, + src1: SOURCE1, + src2: SOURCE2; + int ltncy, + extime, + /* Writeback priority. */ + wb_pri; + /* Immediate size. */ + unsigned imm_flags:2, + /* Register source 1 used. */ + rs1_used:1, + /* Register source 2 used. */ + rs2_used:1, + /* Register source/dest. used. */ + rsd_used:1, + /* Complement. */ + c_flag:1, + /* Upper half word. */ + u_flag:1, + /* Execute next. */ + n_flag:1, + /* Uses writeback slot. */ + wb_flag:1, + /* Dest size. */ + dest_64:1, + /* Source 1 size. */ + s1_64:1, + /* Source 2 size. */ + s2_64:1, + scale_flag:1, + /* Scaled register. */ + brk_flg:1; +}; + +struct mem_segs +{ + /* Pointer (returned by calloc) to segment. */ + struct mem_wrd *seg; + + /* Base load address from file headers. */ + unsigned long baseaddr; + + /* Ending address of segment. */ + unsigned long endaddr; + + /* Segment control flags (none defined). */ + int flags; }; #define MAXSEGS (10) /* max number of segment allowed */ #define MEMSEGSIZE (sizeof(struct mem_segs))/* size of mem_segs structure */ - +#if 0 #define BRK_RD (0x01) /* break on memory read */ #define BRK_WR (0x02) /* break on memory write */ #define BRK_EXEC (0x04) /* break on execution */ #define BRK_CNT (0x08) /* break on terminal count */ +#endif +struct mem_wrd +{ + /* Simulator instruction break down. */ + struct IR_FIELDS opcode; + union { + /* Memory element break down. */ + unsigned long l; + unsigned short s[2]; + unsigned char c[4]; + } mem; +}; -struct mem_wrd { - struct IR_FIELDS opcode; /* simulator instruction break down */ - union { - unsigned long l; /* memory element break down */ - unsigned short s[2]; - unsigned char c[4]; - } mem; +/* Size of each 32 bit memory model. */ +#define MEMWRDSIZE (sizeof (struct mem_wrd)) + +extern struct mem_segs memory[]; +extern struct PROCESSOR m78000; + +struct PROCESSOR +{ + unsigned WORD + /* Execute instruction pointer. */ + ip, + /* Vector base register. */ + vbr, + /* Processor status register. */ + psr; + + /* Source 1. */ + WORD S1bus, + /* Source 2. */ + S2bus, + /* Destination. */ + Dbus, + /* Data address bus. */ + DAbus, + ALU, + /* Data registers. */ + Regs[REGs], + /* Max clocks before reg is available. */ + time_left[REGs], + /* Writeback priority of reg. */ + wb_pri[REGs], + /* Integer unit control regs. */ + SFU0_regs[REGs], + /* Floating point control regs. */ + SFU1_regs[REGs], + Scoreboard[REGs], + Vbr; + unsigned WORD scoreboard, + Psw, + Tpsw; + /* Waiting for a jump instruction. */ + FLAG jump_pending:1; }; -#define MEMWRDSIZE (sizeof(struct mem_wrd)) /* size of each 32 bit memory model */ - -/* External declarations */ - -extern struct mem_segs memory[]; -extern struct PROCESSOR m78000; - -struct PROCESSOR { - unsigned WORD - ip, /* execute instruction pointer */ - vbr, /* vector base register */ - psr; /* processor status register */ - - WORD S1bus, /* source 1 */ - S2bus, /* source 2 */ - Dbus, /* destination */ - DAbus, /* data address bus */ - ALU, - Regs[REGs], /* data registers */ - time_left[REGs], /* max clocks before reg is available */ - wb_pri[REGs], /* writeback priority of reg */ - SFU0_regs[REGs], /* integer unit control regs */ - SFU1_regs[REGs], /* floating point control regs */ - Scoreboard[REGs], - Vbr; - unsigned WORD scoreboard, - Psw, - Tpsw; - FLAG jump_pending:1; /* waiting for a jump instr. */ - }; - -# define i26bit 1 /* size of immediate field */ -# define i16bit 2 -# define i10bit 3 - -/* Definitions for fields in psr */ - -# define mode 31 -# define rbo 30 -# define ser 29 -# define carry 28 -# define sf7m 11 -# define sf6m 10 -# define sf5m 9 -# define sf4m 8 -# define sf3m 7 -# define sf2m 6 -# define sf1m 5 -# define mam 4 -# define inm 3 -# define exm 2 -# define trm 1 -# define ovfm 0 - -#define MODEMASK (1<<(mode-1)) -# define SILENT 0 /* simulate without output to crt */ -# define VERBOSE 1 /* simulate in verbose mode */ -# define PR_INSTR 2 /* only print instructions */ - -# define RESET 16 /* reset phase */ - -# define PHASE1 0 /* data path phases */ -# define PHASE2 1 - -/* the 1 clock operations */ - -# define ADDU 1 -# define ADDC 2 -# define ADDUC 3 -# define ADD 4 - -# define SUBU ADD+1 -# define SUBB ADD+2 -# define SUBUB ADD+3 -# define SUB ADD+4 - -# define AND_ ADD+5 -# define OR ADD+6 -# define XOR ADD+7 -# define CMP ADD+8 - -/* the LOADS */ - -# define LDAB CMP+1 -# define LDAH CMP+2 -# define LDA CMP+3 -# define LDAD CMP+4 - -# define LDB LDAD+1 -# define LDH LDAD+2 -# define LD LDAD+3 -# define LDD LDAD+4 -# define LDBU LDAD+5 -# define LDHU LDAD+6 - -/* the STORES */ - -# define STB LDHU+1 -# define STH LDHU+2 -# define ST LDHU+3 -# define STD LDHU+4 - -/* the exchange */ - -# define XMEMBU LDHU+5 -# define XMEM LDHU+6 - -/* the branches */ -# define JSR STD+1 -# define BSR STD+2 -# define BR STD+3 -# define JMP STD+4 -# define BB1 STD+5 -# define BB0 STD+6 -# define RTN STD+7 -# define BCND STD+8 - -/* the TRAPS */ -# define TB1 BCND+1 -# define TB0 BCND+2 -# define TCND BCND+3 -# define RTE BCND+4 -# define TBND BCND+5 - -/* the MISC instructions */ -# define MUL TBND + 1 -# define DIV MUL +2 -# define DIVU MUL +3 -# define MASK MUL +4 -# define FF0 MUL +5 -# define FF1 MUL +6 -# define CLR MUL +7 -# define SET MUL +8 -# define EXT MUL +9 -# define EXTU MUL +10 -# define MAK MUL +11 -# define ROT MUL +12 - -/* control register manipulations */ - -# define LDCR ROT +1 -# define STCR ROT +2 -# define XCR ROT +3 - -# define FLDCR ROT +4 -# define FSTCR ROT +5 -# define FXCR ROT +6 - - -# define NOP XCR +1 - -/* floating point instructions */ - -# define FADD NOP +1 -# define FSUB NOP +2 -# define FMUL NOP +3 -# define FDIV NOP +4 -# define FSQRT NOP +5 -# define FCMP NOP +6 -# define FIP NOP +7 -# define FLT NOP +8 -# define INT NOP +9 -# define NINT NOP +10 -# define TRNC NOP +11 -# define FLDC NOP +12 -# define FSTC NOP +13 -# define FXC NOP +14 - -# define UEXT(src,off,wid) ((((unsigned int)(src))>>(off)) & ((1<<(wid)) - 1)) -# define SEXT(src,off,wid) (((((int)(src))<<(32-((off)+(wid)))) >>(32-(wid))) ) -# define MAKE(src,off,wid) \ - ((((unsigned int)(src)) & ((1<<(wid)) - 1)) << (off)) - -# define opword(n) (unsigned long) (memaddr->mem.l) - -/* Constants and Masks */ +/* Size of immediate field. */ + +#define i26bit 1 +#define i16bit 2 +#define i10bit 3 + +/* Definitions for fields in psr. */ + +#define mode 31 +#define rbo 30 +#define ser 29 +#define carry 28 +#define sf7m 11 +#define sf6m 10 +#define sf5m 9 +#define sf4m 8 +#define sf3m 7 +#define sf2m 6 +#define sf1m 5 +#define mam 4 +#define inm 3 +#define exm 2 +#define trm 1 +#define ovfm 0 + +/* The 1 clock operations. */ + +#define ADDU 1 +#define ADDC 2 +#define ADDUC 3 +#define ADD 4 + +#define SUBU ADD+1 +#define SUBB ADD+2 +#define SUBUB ADD+3 +#define SUB ADD+4 + +#define AND_ ADD+5 +#define OR ADD+6 +#define XOR ADD+7 +#define CMP ADD+8 + +/* Loads. */ + +#define LDAB CMP+1 +#define LDAH CMP+2 +#define LDA CMP+3 +#define LDAD CMP+4 + +#define LDB LDAD+1 +#define LDH LDAD+2 +#define LD LDAD+3 +#define LDD LDAD+4 +#define LDBU LDAD+5 +#define LDHU LDAD+6 + +/* Stores. */ + +#define STB LDHU+1 +#define STH LDHU+2 +#define ST LDHU+3 +#define STD LDHU+4 + +/* Exchange. */ + +#define XMEMBU LDHU+5 +#define XMEM LDHU+6 + +/* Branches. */ + +#define JSR STD+1 +#define BSR STD+2 +#define BR STD+3 +#define JMP STD+4 +#define BB1 STD+5 +#define BB0 STD+6 +#define RTN STD+7 +#define BCND STD+8 + +/* Traps. */ + +#define TB1 BCND+1 +#define TB0 BCND+2 +#define TCND BCND+3 +#define RTE BCND+4 +#define TBND BCND+5 + +/* Misc. */ + +#define MUL TBND + 1 +#define DIV MUL +2 +#define DIVU MUL +3 +#define MASK MUL +4 +#define FF0 MUL +5 +#define FF1 MUL +6 +#define CLR MUL +7 +#define SET MUL +8 +#define EXT MUL +9 +#define EXTU MUL +10 +#define MAK MUL +11 +#define ROT MUL +12 + +/* Control register manipulations. */ + +#define LDCR ROT +1 +#define STCR ROT +2 +#define XCR ROT +3 + +#define FLDCR ROT +4 +#define FSTCR ROT +5 +#define FXCR ROT +6 + +#define NOP XCR +1 + +/* Floating point instructions. */ + +#define FADD NOP +1 +#define FSUB NOP +2 +#define FMUL NOP +3 +#define FDIV NOP +4 +#define FSQRT NOP +5 +#define FCMP NOP +6 +#define FIP NOP +7 +#define FLT NOP +8 +#define INT NOP +9 +#define NINT NOP +10 +#define TRNC NOP +11 +#define FLDC NOP +12 +#define FSTC NOP +13 +#define FXC NOP +14 + +#define UEXT(src,off,wid) \ + ((((unsigned int)(src)) >> (off)) & ((1 << (wid)) - 1)) + +#define SEXT(src,off,wid) \ + (((((int)(src))<<(32 - ((off) + (wid)))) >>(32 - (wid))) ) + +#define MAKE(src,off,wid) \ + ((((unsigned int)(src)) & ((1 << (wid)) - 1)) << (off)) + +#define opword(n) (unsigned long) (memaddr->mem.l) + +/* Constants and masks. */ #define SFU0 0x80000000 #define SFU1 0x84000000 @@ -360,72 +378,68 @@ struct PROCESSOR { #define CTRL 0x0000f000 #define CTRLMASK 0xfc00f800 -/* Operands types */ +/* Operands types. */ -enum operand_type { +enum operand_type +{ HEX = 1, REG = 2, CONT = 3, IND = 3, BF = 4, - REGSC = 5 /* scaled register */, - CRREG = 6 /* control register */, - FCRREG = 7 /* floating point control register */, + /* Scaled register. */ + REGSC = 5, + /* Control register. */ + CRREG = 6, + /* Floating point control register. */ + FCRREG = 7, PCREL = 8, CONDMASK = 9, - XREG = 10, /* extended register */ - DEC = 11, /* decimal */ + /* Extended register. */ + XREG = 10, + /* Decimal. */ + DEC = 11 }; -/* Hashing Specification */ +/* Hashing specification. */ #define HASHVAL 79 -/* Type definitions */ - -typedef unsigned int UINT; - -/* Structure templates */ - -#if never -typedef struct { - unsigned int offset:5; - unsigned int width:6; - unsigned int type:5; -} OPSPEC; -#endif +/* Structure templates. */ -typedef struct { - unsigned int offset; - unsigned int width; - enum operand_type type; +typedef struct +{ + unsigned int offset; + unsigned int width; + enum operand_type type; } OPSPEC; - struct SIM_FLAGS { - int ltncy, /* latency (max number of clocks needed to execute) */ - extime, /* execution time (min number of clocks needed to execute) */ - wb_pri; /* writeback slot priority */ - unsigned op:OP, /* simulator version of opcode */ - imm_flags:2, /* 10,16 or 26 bit immediate flags */ - rs1_used:1, /* register source 1 used */ - rs2_used:1, /* register source 2 used */ - rsd_used:1, /* register source/dest used */ - c_flag:1, /* complement */ - u_flag:1, /* upper half word */ - n_flag:1, /* execute next */ - wb_flag:1, /* uses writeback slot */ - dest_64:1, /* double precision dest */ - s1_64:1, /* double precision source 1 */ - s2_64:1, /* double precision source 2 */ - scale_flag:1; /* register is scaled */ +struct SIM_FLAGS +{ + int ltncy, /* latency (max number of clocks needed to execute). */ + extime, /* execution time (min number of clocks needed to execute). */ + wb_pri; /* writeback slot priority. */ + unsigned op:OP, /* simulator version of opcode. */ + imm_flags:2, /* 10,16 or 26 bit immediate flags. */ + rs1_used:1, /* register source 1 used. */ + rs2_used:1, /* register source 2 used. */ + rsd_used:1, /* register source/dest used. */ + c_flag:1, /* complement. */ + u_flag:1, /* upper half word. */ + n_flag:1, /* execute next. */ + wb_flag:1, /* uses writeback slot. */ + dest_64:1, /* double precision dest. */ + s1_64:1, /* double precision source 1. */ + s2_64:1, /* double precision source 2. */ + scale_flag:1; /* register is scaled. */ }; typedef struct INSTRUCTAB { - unsigned int opcode; - char *mnemonic; - OPSPEC op1,op2,op3; - struct SIM_FLAGS flgs; - struct INSTRUCTAB *next; + unsigned int opcode; + char *mnemonic; + OPSPEC op1,op2,op3; + struct SIM_FLAGS flgs; + struct INSTRUCTAB *next; } INSTAB; @@ -623,7 +637,7 @@ static INSTAB instructions[] = { {0x80008800,"fstcr ",{16,5,REG} ,{5,6,FCRREG} ,NO_OPERAND , {1,1,PFLT,FSTC ,0,0,1,1,0,0,0,1,0,0,0,0} ,NULL }, {0x8000c800,"fxcr ",{21,5,REG} ,{16,5,REG} ,{5,6,FCRREG} , {1,1,PFLT,FXC ,0,0,1,1,0,0,0,1,0,0,0,0} ,NULL }, -/* The following are new for the 88110. */ +/* The following are new for the 88110. */ {0x8400aaa0,"fadd.ddd ",{21,5,XREG} ,{16,5,XREG} ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL }, {0x8400aa80,"fadd.dds ",{21,5,XREG} ,{16,5,XREG} ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL }, diff --git a/gnu/dist/toolchain/include/opcode/mips.h b/gnu/dist/toolchain/include/opcode/mips.h index 7fd4703e53c..312a2ac1717 100644 --- a/gnu/dist/toolchain/include/opcode/mips.h +++ b/gnu/dist/toolchain/include/opcode/mips.h @@ -133,6 +133,16 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * #define OP_MASK_SEL 0x7 /* The sel field of mfcZ and mtcZ. */ #define OP_SH_CODE19 6 /* 19 bit wait code. */ #define OP_MASK_CODE19 0x7ffff +#define OP_SH_ALN 21 +#define OP_MASK_ALN 0x7 +#define OP_SH_VSEL 21 +#define OP_MASK_VSEL 0x1f + +/* Values in the 'VSEL' field. */ +#define MDMX_FMTSEL_IMM_QH 0x1d +#define MDMX_FMTSEL_IMM_OB 0x1e +#define MDMX_FMTSEL_VEC_QH 0x15 +#define MDMX_FMTSEL_VEC_OB 0x16 /* This structure holds information for a particular instruction. */ @@ -209,8 +219,8 @@ struct mips_opcode Coprocessor instructions: "E" 5 bit target register (OP_*_RT) "G" 5 bit destination register (OP_*_RD) + "H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL) "P" 5 bit performance-monitor register (OP_*_PERFREG) - "H" 3 bit sel field (OP_*_SEL) Macro instructions: "A" General 32 bit expression @@ -220,13 +230,21 @@ struct mips_opcode "f" 32 bit floating point constant "l" 32 bit floating point constant in .lit4 + MDMX instruction operands (note that while these use the FP register + fields, they accept both $fN and $vN names for the registers): + "O" MDMX alignment offset (OP_*_ALN) + "Q" MDMX vector/scalar/immediate source (OP_*_VSEL and OP_*_FT) + "X" MDMX destination register (OP_*_FD) + "Y" MDMX source register (OP_*_FS) + "Z" MDMX source register (OP_*_FT) + Other: "()" parens surrounding optional value "," separates operands Characters used so far, for quick reference when adding more: "<>()," - "ABCDEFGHIJLMNPRSTUVW" + "ABCDEFGHIJLMNOPQRSTUVWXYZ" "abcdfhijklopqrstuvwxz" */ @@ -297,6 +315,10 @@ struct mips_opcode #define INSN_MULT 0x40000000 /* Instruction synchronize shared memory. */ #define INSN_SYNC 0x80000000 +/* Instruction reads MDMX accumulator. XXX FIXME: No bits left! */ +#define INSN_READ_MDMX_ACC 0 +/* Instruction writes MDMX accumulator. XXX FIXME: No bits left! */ +#define INSN_WRITE_MDMX_ACC 0 /* Instruction is actually a macro. It should be ignored by the disassembler, and requires special treatment by the assembler. */ @@ -307,7 +329,7 @@ struct mips_opcode ORs of these bits, indicatingthat they support the instructions defined at the given level. */ -#define INSN_ISA_MASK 0x0000ffff +#define INSN_ISA_MASK 0x00000fff #define INSN_ISA1 0x00000010 #define INSN_ISA2 0x00000020 #define INSN_ISA3 0x00000040 @@ -316,6 +338,16 @@ struct mips_opcode #define INSN_ISA32 0x00000200 #define INSN_ISA64 0x00000400 +/* Masks used for MIPS-defined ASEs. */ +#define INSN_ASE_MASK 0x0000f000 + +/* MIPS 16 ASE */ +#define INSN_MIPS16 0x00002000 +/* MIPS-3D ASE */ +#define INSN_MIPS3D 0x00004000 +/* MDMX ASE */ +#define INSN_MDMX 0x00008000 + /* Chip specific instructions. These are bitmasks. */ /* MIPS R4650 instruction. */ @@ -326,8 +358,10 @@ struct mips_opcode #define INSN_4100 0x00040000 /* Toshiba R3900 instruction. */ #define INSN_3900 0x00080000 -/* 32-bit code running on a ISA3+ CPU. */ -#define INSN_GP32 0x00100000 +/* MIPS R10000 instruction. */ +#define INSN_10000 0x00100000 +/* Broadcom SB-1 instruction. */ +#define INSN_SB1 0x00200000 /* MIPS ISA defines, use instead of hardcoding ISA level. */ @@ -361,28 +395,26 @@ struct mips_opcode #define CPU_R12000 12000 #define CPU_MIPS16 16 #define CPU_MIPS32 32 -#define CPU_MIPS32_4K 3204113 /* 32, 04, octal 'K'. */ #define CPU_MIPS5 5 #define CPU_MIPS64 64 #define CPU_SB1 12310201 /* octal 'SB', 01. */ -/* Test for membership in an ISA including chip specific ISAs. - INSN is pointer to an element of the opcode table; ISA is the - specified ISA to test against; and CPU is the CPU specific ISA - to test, or zero if no CPU specific ISA test is desired. - The gp32 arg is set when you need to force 32-bit register usage on - a machine with 64-bit registers; see the documentation under -mgp32 - in the MIPS gas docs. */ - -#define OPCODE_IS_MEMBER(insn, isa, cpu, gp32) \ - ((((insn)->membership & isa) != 0 \ - && ((insn)->membership & INSN_GP32 ? gp32 : 1) \ - ) \ +/* Test for membership in an ISA including chip specific ISAs. INSN + is pointer to an element of the opcode table; ISA is the specified + ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to + test, or zero if no CPU specific ISA test is desired. */ + +#define OPCODE_IS_MEMBER(insn, isa, cpu) \ + (((insn)->membership & isa) != 0 \ || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0) \ || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) \ || ((cpu == CPU_VR4100 || cpu == CPU_R4111) \ && ((insn)->membership & INSN_4100) != 0) \ - || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0)) + || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0) \ + || ((cpu == CPU_R10000 || cpu == CPU_R12000) \ + && ((insn)->membership & INSN_10000) != 0) \ + || (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0) \ + || 0) /* Please keep this term for easier source merging. */ /* This is a list of macro expanded instructions. @@ -508,6 +540,7 @@ enum M_LWR_A, M_LWR_AB, M_LWU_AB, + M_MOVE, M_MUL, M_MUL_I, M_MULO, @@ -520,9 +553,13 @@ enum M_REM_3I, M_REMU_3, M_REMU_3I, + M_DROL, M_ROL, + M_DROL_I, M_ROL_I, + M_DROR, M_ROR, + M_DROR_I, M_ROR_I, M_S_DA, M_S_DOB, diff --git a/gnu/dist/toolchain/include/opcode/mmix.h b/gnu/dist/toolchain/include/opcode/mmix.h new file mode 100644 index 00000000000..825eb0e244b --- /dev/null +++ b/gnu/dist/toolchain/include/opcode/mmix.h @@ -0,0 +1,185 @@ +/* mmix.h -- Header file for MMIX opcode table + Copyright (C) 2001 Free Software Foundation, Inc. + Written by Hans-Peter Nilsson (hp@bitrange.com) + +This file is part of GDB, GAS, and the GNU binutils. + +GDB, GAS, and the GNU binutils are free software; you can redistribute +them and/or modify them under the terms of the GNU General Public +License as published by the Free Software Foundation; either version 2, +or (at your option) any later version. + +GDB, GAS, and the GNU binutils are distributed in the hope that they +will be useful, but WITHOUT ANY WARRANTY; without even the implied +warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See +the GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this file; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* We could have just a char*[] table indexed by the register number, but + that would not allow for synonyms. The table is terminated with an + entry with a NULL name. */ +struct mmix_spec_reg +{ + const char *name; + unsigned int number; +}; + +/* General indication of the type of instruction. */ +enum mmix_insn_type + { + mmix_type_pseudo, + mmix_type_normal, + mmix_type_branch, + mmix_type_condbranch, + mmix_type_memaccess_octa, + mmix_type_memaccess_tetra, + mmix_type_memaccess_wyde, + mmix_type_memaccess_byte, + mmix_type_memaccess_block, + mmix_type_jsr + }; + +/* Type of operands an instruction takes. Use when parsing assembly code + and disassembling. */ +enum mmix_operands_type + { + mmix_operands_none = 0, + + /* All operands are registers: "$X,$Y,$Z". */ + mmix_operands_regs, + + /* "$X,YZ", like SETH. */ + mmix_operands_reg_yz, + + /* The regular "$X,$Y,$Z|Z". + The Z is optional; if only "$X,$Y" is given, then "$X,$Y,0" is + assumed. */ + mmix_operands_regs_z_opt, + + /* The regular "$X,$Y,$Z|Z". */ + mmix_operands_regs_z, + + /* "Address"; only JMP. Zero operands allowed unless GNU syntax. */ + mmix_operands_jmp, + + /* "$X|X,$Y,$Z|Z": PUSHGO; like "3", but X can be expressed as an + integer. */ + mmix_operands_pushgo, + + /* Two registers or a register and a byte, like FLOT, possibly with + rounding: "$X,$Z|Z" or "$X,ROUND_MODE,$Z|Z". */ + mmix_operands_roundregs_z, + + /* "X,YZ", POP. Unless GNU syntax, zero or one operand is allowed. */ + mmix_operands_pop, + + /* Two registers, possibly with rounding: "$X,$Z" or + "$X,ROUND_MODE,$Z". */ + mmix_operands_roundregs, + + /* "XYZ", like SYNC. */ + mmix_operands_sync, + + /* "X,$Y,$Z|Z", like SYNCD. */ + mmix_operands_x_regs_z, + + /* "$X,Y,$Z|Z", like NEG and NEGU. The Y field is optional, default 0. */ + mmix_operands_neg, + + /* "$X,Address, like GETA or branches. */ + mmix_operands_regaddr, + + /* "$X|X,Address, like PUSHJ. */ + mmix_operands_pushj, + + /* "$X,spec_reg"; GET. */ + mmix_operands_get, + + /* "spec_reg,$Z|Z"; PUT. */ + mmix_operands_put, + + /* Two registers, "$X,$Y". */ + mmix_operands_set, + + /* "$X,0"; SAVE. */ + mmix_operands_save, + + /* "0,$Z"; UNSAVE. */ + mmix_operands_unsave, + + /* "X,Y,Z"; like SWYM or TRAP. Zero (or 1 if GNU syntax) to three + operands, interpreted as 0; XYZ; X, YZ and X, Y, Z. */ + mmix_operands_xyz_opt, + + /* Just "Z", like RESUME. Unless GNU syntax, the operand can be omitted + and will then be assumed zero. */ + mmix_operands_resume, + + /* These are specials to handle that pseudo-directives are specified + like ordinary insns when being mmixal-compatible. They signify the + specific pseudo-directive rather than the operands type. */ + + /* LOC. */ + mmix_operands_loc, + + /* PREFIX. */ + mmix_operands_prefix, + + /* BYTE. */ + mmix_operands_byte, + + /* WYDE. */ + mmix_operands_wyde, + + /* TETRA. */ + mmix_operands_tetra, + + /* OCTA. */ + mmix_operands_octa, + + /* LOCAL. */ + mmix_operands_local, + + /* BSPEC. */ + mmix_operands_bspec, + + /* ESPEC. */ + mmix_operands_espec, + }; + +struct mmix_opcode + { + const char *name; + unsigned long match; + unsigned long lose; + enum mmix_operands_type operands; + + /* This is used by the disassembly function. */ + enum mmix_insn_type type; + }; + +/* Declare the actual tables. */ +extern const struct mmix_opcode mmix_opcodes[]; + +/* This one is terminated with an entry with a NULL name. */ +extern const struct mmix_spec_reg mmix_spec_regs[]; + +/* Some insn values we use when padding and synthesizing address loads. */ +#define IMM_OFFSET_BIT 1 +#define COND_INV_BIT 0x8 +#define PRED_INV_BIT 0x10 + +#define PUSHGO_INSN_BYTE 0xbe +#define GO_INSN_BYTE 0x9e +#define SETL_INSN_BYTE 0xe3 +#define INCML_INSN_BYTE 0xe6 +#define INCMH_INSN_BYTE 0xe5 +#define INCH_INSN_BYTE 0xe4 +#define SWYM_INSN_BYTE 0xfd + +/* We can have 256 - 32 (local registers) - 1 ($255 is not allocatable) + global registers. */ +#define MAX_GREGS 223 diff --git a/gnu/dist/toolchain/include/opcode/or32.h b/gnu/dist/toolchain/include/opcode/or32.h new file mode 100644 index 00000000000..4609a48db56 --- /dev/null +++ b/gnu/dist/toolchain/include/opcode/or32.h @@ -0,0 +1,184 @@ +/* Table of opcodes for the OpenRISC 1000 ISA. + Copyright 2002 Free Software Foundation, Inc. + Contributed by Damjan Lampret (lampret@opencores.org). + + This file is part of or1k_gen_isa, or1ksim, GDB and GAS. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* We treat all letters the same in encode/decode routines so + we need to assign some characteristics to them like signess etc. */ + +#ifndef OR32_H_ISA +#define OR32_H_ISA + +#define NUM_UNSIGNED (0) +#define NUM_SIGNED (1) + +#ifndef PARAMS +#define PARAMS(x) x +#endif + +#define MAX_GPRS 32 +#define PAGE_SIZE 4096 +#undef __HALF_WORD_INSN__ + +#define OPERAND_DELIM (',') + +#define OR32_IF_DELAY (1) +#define OR32_W_FLAG (2) +#define OR32_R_FLAG (4) + +struct or32_letter +{ + char letter; + int sign; + /* int reloc; relocation per letter ?? */ +}; + +/* Main instruction specification array. */ +struct or32_opcode +{ + /* Name of the instruction. */ + char *name; + + /* A string of characters which describe the operands. + Valid characters are: + ,() Itself. Characters appears in the assembly code. + rA Register operand. + rB Register operand. + rD Register operand. + I An immediate operand, range -32768 to 32767. + J An immediate operand, range . (unused) + K An immediate operand, range 0 to 65535. + L An immediate operand, range 0 to 63. + M An immediate operand, range . (unused) + N An immediate operand, range -33554432 to 33554431. + O An immediate operand, range . (unused). */ + char *args; + + /* Opcode and operand encoding. */ + char *encoding; + void (*exec) PARAMS ((void)); + unsigned int flags; +}; + +#define OPTYPE_LAST (0x80000000) +#define OPTYPE_OP (0x40000000) +#define OPTYPE_REG (0x20000000) +#define OPTYPE_SIG (0x10000000) +#define OPTYPE_DIS (0x08000000) +#define OPTYPE_DST (0x04000000) +#define OPTYPE_SBIT (0x00001F00) +#define OPTYPE_SHR (0x0000001F) +#define OPTYPE_SBIT_SHR (8) + +/* MM: Data how to decode operands. */ +extern struct insn_op_struct +{ + unsigned long type; + unsigned long data; +} **op_start; + +#ifdef HAS_EXECUTION +extern void l_invalid PARAMS ((void)); +extern void l_sfne PARAMS ((void)); +extern void l_bf PARAMS ((void)); +extern void l_add PARAMS ((void)); +extern void l_sw PARAMS ((void)); +extern void l_sb PARAMS ((void)); +extern void l_sh PARAMS ((void)); +extern void l_lwz PARAMS ((void)); +extern void l_lbs PARAMS ((void)); +extern void l_lbz PARAMS ((void)); +extern void l_lhs PARAMS ((void)); +extern void l_lhz PARAMS ((void)); +extern void l_movhi PARAMS ((void)); +extern void l_and PARAMS ((void)); +extern void l_or PARAMS ((void)); +extern void l_xor PARAMS ((void)); +extern void l_sub PARAMS ((void)); +extern void l_mul PARAMS ((void)); +extern void l_div PARAMS ((void)); +extern void l_divu PARAMS ((void)); +extern void l_sll PARAMS ((void)); +extern void l_sra PARAMS ((void)); +extern void l_srl PARAMS ((void)); +extern void l_j PARAMS ((void)); +extern void l_jal PARAMS ((void)); +extern void l_jalr PARAMS ((void)); +extern void l_jr PARAMS ((void)); +extern void l_rfe PARAMS ((void)); +extern void l_nop PARAMS ((void)); +extern void l_bnf PARAMS ((void)); +extern void l_sfeq PARAMS ((void)); +extern void l_sfgts PARAMS ((void)); +extern void l_sfges PARAMS ((void)); +extern void l_sflts PARAMS ((void)); +extern void l_sfles PARAMS ((void)); +extern void l_sfgtu PARAMS ((void)); +extern void l_sfgeu PARAMS ((void)); +extern void l_sfltu PARAMS ((void)); +extern void l_sfleu PARAMS ((void)); +extern void l_mtspr PARAMS ((void)); +extern void l_mfspr PARAMS ((void)); +extern void l_sys PARAMS ((void)); +extern void l_trap PARAMS ((void)); /* CZ 21/06/01. */ +extern void l_macrc PARAMS ((void)); +extern void l_mac PARAMS ((void)); +extern void l_msb PARAMS ((void)); +extern void l_invalid PARAMS ((void)); +extern void l_cust1 PARAMS ((void)); +extern void l_cust2 PARAMS ((void)); +extern void l_cust3 PARAMS ((void)); +extern void l_cust4 PARAMS ((void)); +#endif +extern void l_none PARAMS ((void)); + +extern const struct or32_letter or32_letters[]; + +extern const struct or32_opcode or32_opcodes[]; + +extern const unsigned int or32_num_opcodes; + +/* Calculates instruction length in bytes. Always 4 for OR32. */ +extern int insn_len PARAMS ((int)); + +/* Is individual insn's operand signed or unsigned? */ +extern int letter_signed PARAMS ((char)); + +/* Number of letters in the individual lettered operand. */ +extern int letter_range PARAMS ((char)); + +/* MM: Returns index of given instruction name. */ +extern int insn_index PARAMS ((char *)); + +/* MM: Returns instruction name from index. */ +extern const char *insn_name PARAMS ((int)); + +/* MM: Constructs new FSM, based on or32_opcodes. */ +extern void build_automata PARAMS ((void)); + +/* MM: Destructs FSM. */ +extern void destruct_automata PARAMS ((void)); + +/* MM: Decodes instruction using FSM. Call build_automata first. */ +extern int insn_decode PARAMS ((unsigned int)); + +/* Disassemble one instruction from insn to disassemble. + Return the size of the instruction. */ +int disassemble_insn PARAMS ((unsigned long)); + +#endif diff --git a/gnu/dist/toolchain/include/opcode/pdp11.h b/gnu/dist/toolchain/include/opcode/pdp11.h new file mode 100644 index 00000000000..228c221fc1b --- /dev/null +++ b/gnu/dist/toolchain/include/opcode/pdp11.h @@ -0,0 +1,85 @@ +/* PDP-11 opcde list. + Copyright 2001, 2002 Free Software Foundation, Inc. + +This file is part of GDB and GAS. + +GDB and GAS are free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 1, or (at your option) +any later version. + +GDB and GAS are distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GDB or GAS; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* + * PDP-11 opcode types. + */ + +#define PDP11_OPCODE_NO_OPS 0 +#define PDP11_OPCODE_REG 1 /* register */ +#define PDP11_OPCODE_OP 2 /* generic operand */ +#define PDP11_OPCODE_REG_OP 3 /* register and generic operand */ +#define PDP11_OPCODE_REG_OP_REV 4 /* register and generic operand, + reversed syntax */ +#define PDP11_OPCODE_AC_FOP 5 /* fpu accumulator and generic float + operand */ +#define PDP11_OPCODE_OP_OP 6 /* two generic operands */ +#define PDP11_OPCODE_DISPL 7 /* pc-relative displacement */ +#define PDP11_OPCODE_REG_DISPL 8 /* redister and pc-relative + displacement */ +#define PDP11_OPCODE_IMM8 9 /* 8-bit immediate */ +#define PDP11_OPCODE_IMM6 10 /* 6-bit immediate */ +#define PDP11_OPCODE_IMM3 11 /* 3-bit immediate */ +#define PDP11_OPCODE_ILLEGAL 12 /* illegal instruction */ +#define PDP11_OPCODE_FOP_AC 13 /* generic float argument, then fpu + accumulator */ +#define PDP11_OPCODE_FOP 14 /* generic float operand */ +#define PDP11_OPCODE_AC_OP 15 /* fpu accumulator and generic int + operand */ +#define PDP11_OPCODE_OP_AC 16 /* generic int argument, then fpu + accumulator */ + +/* + * PDP-11 instruction set extensions. + * + * Please keep the numbers low, as they are used as indices into + * an array. + */ + +#define PDP11_NONE 0 /* not in instruction set */ +#define PDP11_BASIC 1 /* basic instruction set (11/20 etc) */ +#define PDP11_CSM 2 /* commercial instruction set */ +#define PDP11_CIS 3 /* commercial instruction set */ +#define PDP11_EIS 4 /* extended instruction set (11/45 etc) */ +#define PDP11_FIS 5 /* KEV11 floating-point instructions */ +#define PDP11_FPP 6 /* FP-11 floating-point instructions */ +#define PDP11_LEIS 7 /* limited extended instruction set + (11/40 etc) */ +#define PDP11_MFPT 8 /* move from processor type */ +#define PDP11_MPROC 9 /* multiprocessor instructions: tstset, + wrtlck */ +#define PDP11_MXPS 10 /* move from/to processor status */ +#define PDP11_SPL 11 /* set priority level */ +#define PDP11_UCODE 12 /* microcode instructions: ldub, med, xfc */ +#define PDP11_EXT_NUM 13 /* total number of extension types */ + +struct pdp11_opcode +{ + const char *name; + int opcode; + int mask; + int type; + int extension; +}; + +extern const struct pdp11_opcode pdp11_opcodes[]; +extern const struct pdp11_opcode pdp11_aliases[]; +extern const int pdp11_num_opcodes, pdp11_num_aliases; + +/* end of pdp11.h */ diff --git a/gnu/dist/toolchain/include/opcode/ppc.h b/gnu/dist/toolchain/include/opcode/ppc.h index d23e1c695e9..f7db66f63a8 100644 --- a/gnu/dist/toolchain/include/opcode/ppc.h +++ b/gnu/dist/toolchain/include/opcode/ppc.h @@ -1,5 +1,6 @@ /* ppc.h -- Header file for PowerPC opcode table - Copyright 1994, 1995, 1999, 2000 Free Software Foundation, Inc. + Copyright 1994, 1995, 1999, 2000, 2001, 2002 + Free Software Foundation, Inc. Written by Ian Lance Taylor, Cygnus Support This file is part of GDB, GAS, and the GNU binutils. @@ -89,7 +90,22 @@ extern const int powerpc_num_opcodes; #define PPC_OPCODE_64_BRIDGE (0400) /* Opcode is supported by Altivec Vector Unit */ -#define PPC_OPCODE_ALTIVEC (01000) +#define PPC_OPCODE_ALTIVEC (01000) + +/* Opcode is supported by PowerPC 403 processor. */ +#define PPC_OPCODE_403 (02000) + +/* Opcode is supported by PowerPC BookE processor. */ +#define PPC_OPCODE_BOOKE (04000) + +/* Opcode is only supported by 64-bit PowerPC BookE processor. */ +#define PPC_OPCODE_BOOKE64 (010000) + +/* Opcode is only supported by Power4 architecture. */ +#define PPC_OPCODE_POWER4 (020000) + +/* Opcode isn't supported by Power4 architecture. */ +#define PPC_OPCODE_NOPOWER4 (040000) /* A macro to extract the major opcode from an instruction. */ #define PPC_OP(i) (((i) >> 26) & 0x3f) @@ -121,6 +137,7 @@ struct powerpc_operand operand value is legal, *ERRMSG will be unchanged (most operands can accept any value). */ unsigned long (*insert) PARAMS ((unsigned long instruction, long op, + int dialect, const char **errmsg)); /* Extraction function. This is used by the disassembler. To @@ -140,7 +157,8 @@ struct powerpc_operand non-zero if this operand type can not actually be extracted from this operand (i.e., the instruction does not match). If the operand is valid, *INVALID will not be changed. */ - long (*extract) PARAMS ((unsigned long instruction, int *invalid)); + long (*extract) PARAMS ((unsigned long instruction, int dialect, + int *invalid)); /* One bit syntax flags. */ unsigned long flags; @@ -229,6 +247,8 @@ extern const struct powerpc_operand powerpc_operands[]; prints these with a leading 'v'. */ #define PPC_OPERAND_VR (010000) +/* This operand is for the DS field in a DS form instruction. */ +#define PPC_OPERAND_DS (020000) /* The POWER and PowerPC assemblers use a few macros. We keep them with the operands table for simplicity. The macro table is an diff --git a/gnu/dist/toolchain/include/opcode/s390.h b/gnu/dist/toolchain/include/opcode/s390.h new file mode 100644 index 00000000000..1a42be6603a --- /dev/null +++ b/gnu/dist/toolchain/include/opcode/s390.h @@ -0,0 +1,130 @@ +/* s390.h -- Header file for S390 opcode table + Copyright 2000, 2001 Free Software Foundation, Inc. + Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com). + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ + +#ifndef S390_H +#define S390_H + +/* List of instruction sets variations. */ + +enum s390_opcode_arch_val + { + S390_OPCODE_ESA = 0, + S390_OPCODE_ESAME + }; + +/* The opcode table is an array of struct s390_opcode. */ + +struct s390_opcode + { + /* The opcode name. */ + const char * name; + + /* The opcode itself. Those bits which will be filled in with + operands are zeroes. */ + unsigned char opcode[6]; + + /* The opcode mask. This is used by the disassembler. This is a + mask containing ones indicating those bits which must match the + opcode field, and zeroes indicating those bits which need not + match (and are presumably filled in by operands). */ + unsigned char mask[6]; + + /* The opcode length in bytes. */ + int oplen; + + /* An array of operand codes. Each code is an index into the + operand table. They appear in the order which the operands must + appear in assembly code, and are terminated by a zero. */ + unsigned char operands[6]; + + /* Bitmask of architectures this opcode is available for. */ + unsigned int architecture; + }; + +/* The table itself is sorted by major opcode number, and is otherwise + in the order in which the disassembler should consider + instructions. */ +extern const struct s390_opcode s390_opcodes[]; +extern const int s390_num_opcodes; + +/* A opcode format table for the .insn pseudo mnemonic. */ +extern const struct s390_opcode s390_opformats[]; +extern const int s390_num_opformats; + +/* Values defined for the flags field of a struct powerpc_opcode. */ + +/* The operands table is an array of struct s390_operand. */ + +struct s390_operand + { + /* The number of bits in the operand. */ + int bits; + + /* How far the operand is left shifted in the instruction. */ + int shift; + + /* One bit syntax flags. */ + unsigned long flags; + }; + +/* Elements in the table are retrieved by indexing with values from + the operands field of the powerpc_opcodes table. */ + +extern const struct s390_operand s390_operands[]; + +/* Values defined for the flags field of a struct s390_operand. */ + +/* This operand names a register. The disassembler uses this to print + register names with a leading 'r'. */ +#define S390_OPERAND_GPR 0x1 + +/* This operand names a floating point register. The disassembler + prints these with a leading 'f'. */ +#define S390_OPERAND_FPR 0x2 + +/* This operand names an access register. The disassembler + prints these with a leading 'a'. */ +#define S390_OPERAND_AR 0x4 + +/* This operand names a control register. The disassembler + prints these with a leading 'c'. */ +#define S390_OPERAND_CR 0x8 + +/* This operand is a displacement. */ +#define S390_OPERAND_DISP 0x10 + +/* This operand names a base register. */ +#define S390_OPERAND_BASE 0x20 + +/* This operand names an index register, it can be skipped. */ +#define S390_OPERAND_INDEX 0x40 + +/* This operand is a relative branch displacement. The disassembler + prints these symbolically if possible. */ +#define S390_OPERAND_PCREL 0x80 + +/* This operand takes signed values. */ +#define S390_OPERAND_SIGNED 0x100 + +/* This operand is a length. */ +#define S390_OPERAND_LENGTH 0x200 + +#endif /* S390_H */ diff --git a/gnu/dist/toolchain/include/opcode/sparc.h b/gnu/dist/toolchain/include/opcode/sparc.h index 5b6b5d14932..c41292364b1 100644 --- a/gnu/dist/toolchain/include/opcode/sparc.h +++ b/gnu/dist/toolchain/include/opcode/sparc.h @@ -1,5 +1,5 @@ /* Definitions for opcode table for the sparc. - Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 2000 + Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 2000, 2002 Free Software Foundation, Inc. This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and @@ -20,7 +20,7 @@ along with GAS or GDB; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ -#include <ansidecl.h> +#include "ansidecl.h" /* The SPARC opcode table (and other related data) is defined in the opcodes library in sparc-opc.c. If you change anything here, make diff --git a/gnu/dist/toolchain/include/opcode/tic54x.h b/gnu/dist/toolchain/include/opcode/tic54x.h index 09ee8c90370..ae657225d61 100644 --- a/gnu/dist/toolchain/include/opcode/tic54x.h +++ b/gnu/dist/toolchain/include/opcode/tic54x.h @@ -19,8 +19,8 @@ along with this file; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ -#ifndef _TIC54X_H_ -#define _TIC54X_H_ +#ifndef _opcode_tic54x_h_ +#define _opcode_tic54x_h_ typedef struct _symbol { @@ -86,7 +86,6 @@ typedef struct _template { /* The opcode mnemonic */ const char *name; - unsigned int words; /* insn size in words */ int minops, maxops; /* min/max operand count */ /* The significant bits in the opcode. Other bits are zero. @@ -141,27 +140,24 @@ typedef struct _template #define FL_NR 0x100 /* no repeat allowed */ #define FL_SMR 0x200 /* Smem read (for flagging write-only *+ARx */ - unsigned short opcode2, mask2; /* some insns have an extended opcode */ +#define FL_PAR 0x400 /* Parallel instruction. */ -} template; + unsigned short opcode2, mask2; /* some insns have an extended opcode */ -typedef struct _partemplate { - char *name; - char *parname; - unsigned int words; /* length in words */ - int minops, maxops; /* min/max operand count for 2nd part of insn */ - unsigned short opcode; - unsigned short mask; - enum optype operand_types[MAX_OPERANDS]; + const char* parname; enum optype paroperand_types[MAX_OPERANDS]; -} partemplate; + +} template; extern const template tic54x_unknown_opcode; extern const template tic54x_optab[]; -extern const partemplate tic54x_paroptab[]; +extern const template tic54x_paroptab[]; extern const symbol mmregs[], regs[]; extern const symbol condition_codes[], cc2_codes[], status_bits[]; extern const symbol cc3_codes[]; extern const char *misc_symbols[]; +struct disassemble_info; +extern const template* tic54x_get_insn (struct disassemble_info *, + bfd_vma, unsigned short, int *); -#endif /* TIC54X_H */ +#endif /* _opcode_tic54x_h_ */ diff --git a/gnu/dist/toolchain/include/opcode/v850.h b/gnu/dist/toolchain/include/opcode/v850.h index 737faf88d0d..2183bc8586b 100644 --- a/gnu/dist/toolchain/include/opcode/v850.h +++ b/gnu/dist/toolchain/include/opcode/v850.h @@ -1,5 +1,5 @@ /* v850.h -- Header file for NEC V850 opcode table - Copyright 1996, 1997 Free Software Foundation, Inc. + Copyright 1996, 1997, 2001 Free Software Foundation, Inc. Written by J.T. Conklin, Cygnus Support This file is part of GDB, GAS, and the GNU binutils. @@ -153,7 +153,6 @@ extern const struct v850_operand v850_operands[]; /* The register specified must not be r0 */ #define V850_NOT_R0 0x80 -/* CYGNUS LOCAL v850e */ /* push/pop type instruction, V850E specific. */ #define V850E_PUSH_POP 0x100 |
