diff options
| author | matt <matt@NetBSD.org> | 2009-12-14 00:40:04 +0000 |
|---|---|---|
| committer | matt <matt@NetBSD.org> | 2009-12-14 00:40:04 +0000 |
| commit | 36c802e628aa9c3eb5f60d0d47aefae4160f6776 (patch) | |
| tree | 797cfc0a2f57c0b747ac7b4621ee7e9c8ba6b591 /gnu | |
| parent | 2e067db09835f866dde3e889fbb83df187488ce8 (diff) | |
Merge gcc mips64 support from matt-nb5-mips64.
Diffstat (limited to 'gnu')
| -rw-r--r-- | gnu/dist/gcc4/gcc/config.gcc | 7 | ||||
| -rw-r--r-- | gnu/dist/gcc4/gcc/config/mips/mips.c | 1 | ||||
| -rw-r--r-- | gnu/dist/gcc4/gcc/config/mips/mips.h | 72 | ||||
| -rw-r--r-- | gnu/dist/gcc4/gcc/config/mips/netbsd.h | 21 | ||||
| -rw-r--r-- | gnu/dist/gcc4/gcc/config/mips/netbsd64.h | 58 | ||||
| -rw-r--r-- | gnu/dist/gcc4/gcc/config/mips/t-netbsd64 | 9 |
6 files changed, 141 insertions, 27 deletions
diff --git a/gnu/dist/gcc4/gcc/config.gcc b/gnu/dist/gcc4/gcc/config.gcc index 4859a5755de..f55ade0c7d3 100644 --- a/gnu/dist/gcc4/gcc/config.gcc +++ b/gnu/dist/gcc4/gcc/config.gcc @@ -1496,10 +1496,13 @@ mips-sgi-irix[56]*) ;; mips64*-*-netbsd*) # NetBSD/mips64, either endian. target_cpu_default="MASK_ABICALLS|MASK_64BIT|MASK_FLOAT64" - tm_file="elfos.h ${tm_file} mips/elf.h netbsd.h netbsd-elf.h mips/netbsd.h" + tm_file="elfos.h ${tm_file} mips/elf.h netbsd.h netbsd-elf.h mips/netbsd.h mips/netbsd64.h" + tmake_file="${tmake_file} mips/t-netbsd64" # tm_defines="${tm_defines} MIPS_ISA_DEFAULT=64" - tm_defines="${tm_defines} MIPS_ABI_DEFAULT=ABI_64" + tm_defines="${tm_defines} MIPS_ABI_DEFAULT=ABI_N32" # tm_defines="${tm_defines} MIPS_CPU_STRING_DEFAULT=\\\"mips64\\\"" + gnu_ld=yes + gas=yes ;; mips*-*-netbsd*) # NetBSD/mips, either endian. target_cpu_default="MASK_ABICALLS" diff --git a/gnu/dist/gcc4/gcc/config/mips/mips.c b/gnu/dist/gcc4/gcc/config/mips/mips.c index 683bc5c4557..fe52c598978 100644 --- a/gnu/dist/gcc4/gcc/config/mips/mips.c +++ b/gnu/dist/gcc4/gcc/config/mips/mips.c @@ -713,6 +713,7 @@ const struct mips_cpu_info mips_cpu_info_table[] = { { "mips32", PROCESSOR_4KC, 32 }, { "mips32r2", PROCESSOR_M4K, 33 }, { "mips64", PROCESSOR_5KC, 64 }, + { "mips64r2", PROCESSOR_5KC, 65 }, /* MIPS I */ { "r3000", PROCESSOR_R3000, 1 }, diff --git a/gnu/dist/gcc4/gcc/config/mips/mips.h b/gnu/dist/gcc4/gcc/config/mips/mips.h index 6dca88967d8..0696001a993 100644 --- a/gnu/dist/gcc4/gcc/config/mips/mips.h +++ b/gnu/dist/gcc4/gcc/config/mips/mips.h @@ -171,7 +171,7 @@ extern const struct mips_rtx_cost_data *mips_cost; /* Generate mips16 code */ #define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0) -/* Generate mips16e code. Default 16bit ASE for mips32/mips32r2/mips64 */ +/* Generate mips16e code. Default 16bit ASE for mips32/mips32r2/mips64/mips64r2 */ #define GENERATE_MIPS16E (TARGET_MIPS16 && mips_isa >= 32) /* Generic ISA defines. */ @@ -182,6 +182,7 @@ extern const struct mips_rtx_cost_data *mips_cost; #define ISA_MIPS32 (mips_isa == 32) #define ISA_MIPS32R2 (mips_isa == 33) #define ISA_MIPS64 (mips_isa == 64) +#define ISA_MIPS64R2 (mips_isa == 65) /* Architecture target defines. */ #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900) @@ -361,6 +362,12 @@ extern const struct mips_rtx_cost_data *mips_cost; builtin_define ("__mips_isa_rev=1"); \ builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \ } \ + else if (ISA_MIPS64R2) \ + { \ + builtin_define ("__mips=64"); \ + builtin_define ("__mips_isa_rev=2"); \ + builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \ + } \ \ if (TARGET_HARD_FLOAT) \ builtin_define ("__mips_hard_float"); \ @@ -480,7 +487,11 @@ extern const struct mips_rtx_cost_data *mips_cost; # if MIPS_ISA_DEFAULT == 64 # define MULTILIB_ISA_DEFAULT "mips64" # else -# define MULTILIB_ISA_DEFAULT "mips1" +# if MIPS_ISA_DEFAULT == 65 +# define MULTILIB_ISA_DEFAULT "mips64r2" +# else +# define MULTILIB_ISA_DEFAULT "mips1" +# endif # endif # endif # endif @@ -541,8 +552,9 @@ extern const struct mips_rtx_cost_data *mips_cost; || TARGET_MAD \ || ISA_MIPS32 \ || ISA_MIPS32R2 \ - || ISA_MIPS64) \ - && !TARGET_MIPS16) + || ISA_MIPS64 \ + || ISA_MIPS64R2 \ + ) && !TARGET_MIPS16) /* Generate three-operand multiply instructions for DImode. */ #define GENERATE_MULT3_DI ((TARGET_MIPS3900) \ @@ -563,7 +575,8 @@ extern const struct mips_rtx_cost_data *mips_cost; /* ISA has instructions for managing 64 bit fp and gp regs (e.g. mips3). */ #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \ || ISA_MIPS4 \ - || ISA_MIPS64) + || ISA_MIPS64 \ + || ISA_MIPS64R2) /* ISA has branch likely instructions (e.g. mips2). */ /* Disable branchlikely for tx39 until compare rewrite. They haven't @@ -574,8 +587,9 @@ extern const struct mips_rtx_cost_data *mips_cost; #define ISA_HAS_CONDMOVE ((ISA_MIPS4 \ || ISA_MIPS32 \ || ISA_MIPS32R2 \ - || ISA_MIPS64) \ - && !TARGET_MIPS5500 \ + || ISA_MIPS64 \ + || ISA_MIPS64R2 \ + ) && !TARGET_MIPS5500 \ && !TARGET_MIPS16) /* ISA has the mips4 FP condition code instructions: FP-compare to CC, @@ -583,14 +597,16 @@ extern const struct mips_rtx_cost_data *mips_cost; #define ISA_HAS_8CC (ISA_MIPS4 \ || ISA_MIPS32 \ || ISA_MIPS32R2 \ - || ISA_MIPS64) + || ISA_MIPS64 \ + || ISA_MIPS64R2) /* This is a catch all for other mips4 instructions: indexed load, the FP madd and msub instructions, and the FP recip and recip sqrt instructions. */ #define ISA_HAS_FP4 ((ISA_MIPS4 \ - || ISA_MIPS64) \ - && !TARGET_MIPS16) + || ISA_MIPS64 \ + || ISA_MIPS64R2 \ + ) && !TARGET_MIPS16) /* ISA has conditional trap instructions. */ #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \ @@ -600,24 +616,28 @@ extern const struct mips_rtx_cost_data *mips_cost; #define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \ || ISA_MIPS32R2 \ || ISA_MIPS64 \ + || ISA_MIPS64R2 \ ) && !TARGET_MIPS16) /* ISA has floating-point nmadd and nmsub instructions. */ #define ISA_HAS_NMADD_NMSUB ((ISA_MIPS4 \ - || ISA_MIPS64) \ - && (!TARGET_MIPS5400 || TARGET_MAD) \ + || ISA_MIPS64 \ + || ISA_MIPS64R2 \ + ) && (!TARGET_MIPS5400 || TARGET_MAD) \ && ! TARGET_MIPS16) /* ISA has count leading zeroes/ones instruction (not implemented). */ #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \ || ISA_MIPS32R2 \ || ISA_MIPS64 \ - ) && !TARGET_MIPS16) + || ISA_MIPS64R2 \ + ) && !TARGET_MIPS16) /* ISA has double-word count leading zeroes/ones instruction (not implemented). */ -#define ISA_HAS_DCLZ_DCLO (ISA_MIPS64 \ - && !TARGET_MIPS16) +#define ISA_HAS_DCLZ_DCLO ((ISA_MIPS64 \ + || ISA_MIPS64R2 \ + ) && !TARGET_MIPS16) /* ISA has three operand multiply instructions that put the high part in an accumulator: mulhi or mulhiu. */ @@ -656,6 +676,7 @@ extern const struct mips_rtx_cost_data *mips_cost; /* ISA has 32-bit rotate right instruction. */ #define ISA_HAS_ROTR_SI (!TARGET_MIPS16 \ && (ISA_MIPS32R2 \ + || ISA_MIPS64R2 \ || TARGET_MIPS5400 \ || TARGET_MIPS5500 \ || TARGET_SR71K \ @@ -667,36 +688,41 @@ extern const struct mips_rtx_cost_data *mips_cost; && (TARGET_MIPS5400 \ || TARGET_MIPS5500 \ || TARGET_SR71K \ + || ISA_MIPS64R2 \ )) /* ISA has data prefetch instructions. This controls use of 'pref'. */ #define ISA_HAS_PREFETCH ((ISA_MIPS4 \ || ISA_MIPS32 \ || ISA_MIPS32R2 \ - || ISA_MIPS64) \ - && !TARGET_MIPS16) + || ISA_MIPS64 \ + || ISA_MIPS64R2 \ + ) && !TARGET_MIPS16) /* ISA has data indexed prefetch instructions. This controls use of 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT. (prefx is a cop1x instruction, so can only be used if FP is enabled.) */ #define ISA_HAS_PREFETCHX ((ISA_MIPS4 \ - || ISA_MIPS64) \ - && !TARGET_MIPS16) + || ISA_MIPS64 \ + || ISA_MIPS64R2 \ + ) && !TARGET_MIPS16) /* True if trunc.w.s and trunc.w.d are real (not synthetic) instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d also requires TARGET_DOUBLE_FLOAT. */ #define ISA_HAS_TRUNC_W (!ISA_MIPS1) -/* ISA includes the MIPS32r2 seb and seh instructions. */ +/* ISA includes the MIPS32/64 rev2 seb and seh instructions. */ #define ISA_HAS_SEB_SEH (!TARGET_MIPS16 \ && (ISA_MIPS32R2 \ + || ISA_MIPS64R2 \ )) /* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */ #define ISA_HAS_EXT_INS (!TARGET_MIPS16 \ && (ISA_MIPS32R2 \ + || ISA_MIPS64R2 \ )) /* True if the result of a load is not available to the next instruction. @@ -727,6 +753,7 @@ extern const struct mips_rtx_cost_data *mips_cost; #define ISA_HAS_HILO_INTERLOCKS (ISA_MIPS32 \ || ISA_MIPS32R2 \ || ISA_MIPS64 \ + || ISA_MIPS64R2 \ || TARGET_MIPS5500) /* Add -G xx support. */ @@ -808,7 +835,7 @@ extern const struct mips_rtx_cost_data *mips_cost; #undef ASM_SPEC #define ASM_SPEC "\ %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \ -%{mips32} %{mips32r2} %{mips64} \ +%{mips32} %{mips32r2} %{mips64} %{mips64r2} \ %{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \ %{mips3d:-mips3d} \ %{mdsp} \ @@ -828,7 +855,8 @@ extern const struct mips_rtx_cost_data *mips_cost; #ifndef LINK_SPEC #define LINK_SPEC "\ %(endian_spec) \ -%{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips32r2} %{mips64} \ +%{G*} %{mips1} %{mips2} %{mips3} %{mips4} \ +%{mips32} %{mips32r2} %{mips64} %{mips64r2} \ %{bestGnum} %{shared} %{non_shared}" #endif /* LINK_SPEC defined */ diff --git a/gnu/dist/gcc4/gcc/config/mips/netbsd.h b/gnu/dist/gcc4/gcc/config/mips/netbsd.h index 04c2d4d054f..8bd1fce5ed9 100644 --- a/gnu/dist/gcc4/gcc/config/mips/netbsd.h +++ b/gnu/dist/gcc4/gcc/config/mips/netbsd.h @@ -85,6 +85,7 @@ Boston, MA 02110-1301, USA. */ } \ else \ { \ + builtin_define ("__mips_o32"); \ builtin_define ("_ABIO32=1"); \ builtin_define ("_MIPS_SIM=_ABIO32"); \ builtin_define ("_MIPS_SZLONG=32"); \ @@ -152,6 +153,11 @@ Boston, MA 02110-1301, USA. */ builtin_define ("__mips=64"); \ builtin_define ("__mips_isa_rev=1"); \ } \ + else if (ISA_MIPS64R2) \ + { \ + builtin_define ("__mips=64"); \ + builtin_define ("__mips_isa_rev=2"); \ + } \ \ if (TARGET_HARD_FLOAT) \ builtin_define ("__mips_hard_float"); \ @@ -195,10 +201,11 @@ Boston, MA 02110-1301, USA. */ #undef LINK_SPEC #define LINK_SPEC \ - "%{EL:-m elf32lmip} \ - %{EB:-m elf32bmip} \ + "%{EL:-m elf32ltsmip} \ + %{EB:-m elf32btsmip} \ %(endian_spec) \ - %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips32r2} %{mips64} \ + %{G*} %{mips1} %{mips2} %{mips3} %{mips4} \ + %{mips32} %{mips32r2} %{mips64} %{mips64r2} \ %{bestGnum} %{call_shared} %{no_archive} %{exact_version} \ %(netbsd_link_spec)" @@ -239,6 +246,14 @@ Boston, MA 02110-1301, USA. */ /* Make gcc agree with <machine/ansi.h> */ +#undef SIZE_TYPE +#define SIZE_TYPE ((POINTER_SIZE == 64 || TARGET_NEWABI) \ + ? "long unsigned int" : "unsigned int") + +#undef PTRDIFF_TYPE +#define PTRDIFF_TYPE ((POINTER_SIZE == 64 || TARGET_NEWABI) \ + ? "long int" : "int") + #undef WCHAR_TYPE #define WCHAR_TYPE "int" diff --git a/gnu/dist/gcc4/gcc/config/mips/netbsd64.h b/gnu/dist/gcc4/gcc/config/mips/netbsd64.h new file mode 100644 index 00000000000..28278fe288e --- /dev/null +++ b/gnu/dist/gcc4/gcc/config/mips/netbsd64.h @@ -0,0 +1,58 @@ +/* Definitions of target machine for GNU compiler, for MIPS NetBSD systems. + Copyright (C) 1993, 1995, 1996, 1997, 1999, 2000, 2001, 2002, 2003, 2004 + Free Software Foundation, Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GCC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GCC; see the file COPYING. If not, write to +the Free Software Foundation, 51 Franklin Street, Fifth Floor, +Boston, MA 02110-1301, USA. */ + +/* Force the default endianness and ABI flags onto the command line + in order to make the other specs easier to write. */ + +#define DRIVER_SELF_SPECS \ +"%{!EB:%{!EL:%(endian_spec)}}", \ +"%{!mabi=*: -mabi=n32}" + +/* Define default target values. */ + +#undef MACHINE_TYPE +#if TARGET_ENDIAN_DEFAULT != 0 +#define MACHINE_TYPE "NetBSD/mips64eb ELF" +#else +#define MACHINE_TYPE "NetBSD/mips64el ELF" +#endif + +/* Provide a LINK_SPEC appropriate for a NetBSD/mips target. + This is a copy of LINK_SPEC from <netbsd-elf.h> tweaked for + the MIPS target. */ + +#undef LINK_SPEC +#define LINK_SPEC \ + "%{mabi=64:-m elf64%{EB:b}%{EL:l}tsmip} \ + %{mabi=32:-m elf32%{EB:b}%{EL:l}tsmip} \ + %{mabi=o64:-m elf64%{EB:b}%{EL:l}tsmip} \ + %{mabi=n32:-m elf32%{EB:b}%{EL:l}tsmipn32} \ + %(endian_spec) \ + %{G*} %{mips1} %{mips2} %{mips3} %{mips4} \ + %{mips32} %{mips32r2} %{mips64} %{mips64r2} \ + %{bestGnum} %{call_shared} %{no_archive} %{exact_version} \ + %(netbsd_link_spec)" + +#undef LONG_DOUBLE_TYPE_SIZE +#define LONG_DOUBLE_TYPE_SIZE 64 + +#undef LIBGCC2_LONG_DOUBLE_TYPE_SIZE +#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64 diff --git a/gnu/dist/gcc4/gcc/config/mips/t-netbsd64 b/gnu/dist/gcc4/gcc/config/mips/t-netbsd64 new file mode 100644 index 00000000000..dca7cc4762c --- /dev/null +++ b/gnu/dist/gcc4/gcc/config/mips/t-netbsd64 @@ -0,0 +1,9 @@ +# NetBSD has (will have) "non-native" libraries in /usr/lib/<arch>. +# For NetBSD/mips64 we thus have /usr/lib (n32), /usr/lib/o32 and /usr/lib/64. + +MULTILIB_OPTIONS = mabi=n32/mabi=64/mabi=32 +MULTILIB_DIRNAMES = n32 n64 o32 +MULTILIB_OSDIRNAMES = . ../lib/64 ../lib/o32 + +LIBGCC = stmp-multilib +INSTALL_LIBGCC = install-multilib |
