diff options
| author | rafal <rafal@NetBSD.org> | 2001-12-05 05:31:44 +0000 |
|---|---|---|
| committer | rafal <rafal@NetBSD.org> | 2001-12-05 05:31:44 +0000 |
| commit | 49df24a94219827aa0cf44b23893ebbfff27adc1 (patch) | |
| tree | 2491d56eaced46fed527616273c66e8b9026ebba /gnu | |
| parent | 5e5ab178087b4aae3f5ea1c9eb361ac0090afb5d (diff) | |
Add MIPS (both target and host) support to the NEW_TOOLCHAIN GDB, based on
the 4.17 NetBSD support from our tree. Original port by Chris Sekiya, with
minimal tweaks and cleanups by me (mainly: build bi-endian by default, add
NetBSD kcore support back).
Diffstat (limited to 'gnu')
| -rw-r--r-- | gnu/dist/toolchain/gdb/config/mips/nbsd.mh | 7 | ||||
| -rw-r--r-- | gnu/dist/toolchain/gdb/config/mips/nbsdeb.mt | 3 | ||||
| -rw-r--r-- | gnu/dist/toolchain/gdb/config/mips/nbsdel.mt | 3 | ||||
| -rw-r--r-- | gnu/dist/toolchain/gdb/config/mips/nm-nbsd.h | 42 | ||||
| -rw-r--r-- | gnu/dist/toolchain/gdb/config/mips/tm-nbsd.h | 48 | ||||
| -rw-r--r-- | gnu/dist/toolchain/gdb/config/mips/tm-nbsdeb.h | 23 | ||||
| -rw-r--r-- | gnu/dist/toolchain/gdb/config/mips/tm-nbsdel.h | 23 | ||||
| -rw-r--r-- | gnu/dist/toolchain/gdb/config/mips/xm-nbsd.h | 21 | ||||
| -rw-r--r-- | gnu/dist/toolchain/gdb/configure.host | 2 | ||||
| -rw-r--r-- | gnu/dist/toolchain/gdb/configure.tgt | 3 | ||||
| -rw-r--r-- | gnu/dist/toolchain/gdb/mipsnbsd-nat.c | 408 | ||||
| -rw-r--r-- | gnu/dist/toolchain/gdb/solib.c | 2 |
12 files changed, 583 insertions, 2 deletions
diff --git a/gnu/dist/toolchain/gdb/config/mips/nbsd.mh b/gnu/dist/toolchain/gdb/config/mips/nbsd.mh new file mode 100644 index 00000000000..d4e710be93a --- /dev/null +++ b/gnu/dist/toolchain/gdb/config/mips/nbsd.mh @@ -0,0 +1,7 @@ +# Host: Mips (either-endian) running NetBSD +XDEPFILES= ser-tcp.o +XM_FILE= xm-nbsd.h +XM_CLIBS=-lkvm +NAT_FILE= nm-nbsd.h +NATDEPFILES= infptrace.o inftarg.o fork-child.o corelow.o mipsnbsd-nat.o \ + kcore-nbsd.o diff --git a/gnu/dist/toolchain/gdb/config/mips/nbsdeb.mt b/gnu/dist/toolchain/gdb/config/mips/nbsdeb.mt new file mode 100644 index 00000000000..0b7fdd2f3d5 --- /dev/null +++ b/gnu/dist/toolchain/gdb/config/mips/nbsdeb.mt @@ -0,0 +1,3 @@ +# Target: Mips (BE) running NetBSD +TDEPFILES= mips-tdep.o solib.o +TM_FILE= tm-nbsdeb.h diff --git a/gnu/dist/toolchain/gdb/config/mips/nbsdel.mt b/gnu/dist/toolchain/gdb/config/mips/nbsdel.mt new file mode 100644 index 00000000000..b42b8bea81c --- /dev/null +++ b/gnu/dist/toolchain/gdb/config/mips/nbsdel.mt @@ -0,0 +1,3 @@ +# Target: Mips (LE) running NetBSD +TDEPFILES= mips-tdep.o solib.o +TM_FILE= tm-nbsdel.h diff --git a/gnu/dist/toolchain/gdb/config/mips/nm-nbsd.h b/gnu/dist/toolchain/gdb/config/mips/nm-nbsd.h new file mode 100644 index 00000000000..9877c5159c4 --- /dev/null +++ b/gnu/dist/toolchain/gdb/config/mips/nm-nbsd.h @@ -0,0 +1,42 @@ +/* Native-dependent definitions for Mips running NetBSD, for GDB. + Copyright (C) 1986, 1987, 1989, 1992, 1995, 1996 + Free Software Foundation, Inc. + +This file is part of GDB. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef NM_NBSD_H +#define NM_NBSD_H + +/* Need to define this before including the common nm-nbsd.h. */ +#ifndef SVR4_SHARED_LIBS +#define SVR4_SHARED_LIBS +#endif + +/* Get generic NetBSD native definitions. */ +#include <nm-nbsd.h> + +/* Figure out where the longjmp will land. We expect that we have just entered + longjmp and haven't yet setup the stack frame, so the args are still in the + argument regs. A0_REGNUM points at the jmp_buf structure from which we + extract the pc (JB_PC) that we will land at. The pc is copied into ADDR. + This routine returns true on success */ + +#define GET_LONGJMP_TARGET(ADDR) get_longjmp_target(ADDR) +extern int +get_longjmp_target PARAMS ((CORE_ADDR *)); + +#endif diff --git a/gnu/dist/toolchain/gdb/config/mips/tm-nbsd.h b/gnu/dist/toolchain/gdb/config/mips/tm-nbsd.h new file mode 100644 index 00000000000..13ba24745bb --- /dev/null +++ b/gnu/dist/toolchain/gdb/config/mips/tm-nbsd.h @@ -0,0 +1,48 @@ +/* Macro definitions for Mips running under NetBSD. + Copyright 1994 Free Software Foundation, Inc. + +This file is part of GDB. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef TM_NBSD_H +#define TM_NBSD_H + +/* Saved Pc. Get it from sigcontext if within sigtramp. */ +#define SIGCONTEXT_PC_OFFSET 8 + +/* + * This is a generic template for both BE and LE mips targets. + * The default endianness should be set up before this is included. + */ +#if !defined(TARGET_BYTE_ORDER_DEFAULT) +#error Must define TARGET_BYTE_ORDER_DEFAULT before including tm-nbsd.h +#endif + +/* Generic definitions. */ +#include "mips/tm-mips.h" + +#undef TARGET_BYTE_ORDER_SELECTABLE_P +#define TARGET_BYTE_ORDER_SELECTABLE_P 1 + +#undef SOFTWARE_SINGLE_STEP_P +#define SOFTWARE_SINGLE_STEP_P 1 +#define SOFTWARE_SINGLE_STEP(sig, bp_p) netbsd_mips_software_single_step (sig, bp_p) + +void netbsd_mips_software_single_step (unsigned int, int); + +#include <tm-nbsd.h> + +#endif /* TM_NBSD_H */ diff --git a/gnu/dist/toolchain/gdb/config/mips/tm-nbsdeb.h b/gnu/dist/toolchain/gdb/config/mips/tm-nbsdeb.h new file mode 100644 index 00000000000..761928bc64d --- /dev/null +++ b/gnu/dist/toolchain/gdb/config/mips/tm-nbsdeb.h @@ -0,0 +1,23 @@ +/* Macro definitions for Mips running under NetBSD. +/* Copyright (C) 1990 Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#define TARGET_BYTE_ORDER_DEFAULT BIG_ENDIAN + +#include "mips/tm-nbsd.h" diff --git a/gnu/dist/toolchain/gdb/config/mips/tm-nbsdel.h b/gnu/dist/toolchain/gdb/config/mips/tm-nbsdel.h new file mode 100644 index 00000000000..275a95b0bac --- /dev/null +++ b/gnu/dist/toolchain/gdb/config/mips/tm-nbsdel.h @@ -0,0 +1,23 @@ +/* Macro definitions for Mips running under NetBSD. +/* Copyright (C) 1990 Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#define TARGET_BYTE_ORDER_DEFAULT LITTLE_ENDIAN + +#include "mips/tm-nbsd.h" diff --git a/gnu/dist/toolchain/gdb/config/mips/xm-nbsd.h b/gnu/dist/toolchain/gdb/config/mips/xm-nbsd.h new file mode 100644 index 00000000000..621ee34da08 --- /dev/null +++ b/gnu/dist/toolchain/gdb/config/mips/xm-nbsd.h @@ -0,0 +1,21 @@ +/* Parameters for execution on a Mips running NetBSD, for GDB. + Copyright 1996 Free Software Foundation, Inc. + +This file is part of GDB. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* Get generic NetBSD host definitions. */ +#include <xm-nbsd.h> diff --git a/gnu/dist/toolchain/gdb/configure.host b/gnu/dist/toolchain/gdb/configure.host index 3e9985b0cb9..ce33bb6399e 100644 --- a/gnu/dist/toolchain/gdb/configure.host +++ b/gnu/dist/toolchain/gdb/configure.host @@ -17,6 +17,7 @@ hppa*) gdb_host_cpu=pa ;; i[3456]86*) gdb_host_cpu=i386 ;; m68*) gdb_host_cpu=m68k ;; m88*) gdb_host_cpu=m88k ;; +mipseb*) gdb_host_cpu=mips ;; # OBSOLETE pyramid) gdb_host_cpu=pyr ;; powerpc*) gdb_host_cpu=powerpc ;; sparc64) gdb_host_cpu=sparc ;; @@ -125,6 +126,7 @@ mips-*-mach3*) gdb_host=mipsm3 ;; mips-*-sysv4*) gdb_host=mipsv4 ;; mips-*-sysv*) gdb_host=riscos ;; mips-*-riscos*) gdb_host=riscos ;; +mips*-*-netbsd*) gdb_host=nbsd ;; none-*-*) gdb_host=none ;; diff --git a/gnu/dist/toolchain/gdb/configure.tgt b/gnu/dist/toolchain/gdb/configure.tgt index 958cf3eb300..933f07f60c0 100644 --- a/gnu/dist/toolchain/gdb/configure.tgt +++ b/gnu/dist/toolchain/gdb/configure.tgt @@ -172,7 +172,8 @@ m88*-*-*) gdb_target=m88k ;; mcore*-*-*) gdb_target=mcore ;; -mips*-*-netbsd*) gdb_target=nbsd ;; +mipseb-*-netbsd*) gdb_target=nbsdeb ;; +mipsel-*-netbsd*) gdb_target=nbsdel ;; mips64*-big-*) gdb_target=bigmips64 ;; mips*-big-*) gdb_target=bigmips ;; mips*-dec-mach3*) gdb_target=mach3 ;; diff --git a/gnu/dist/toolchain/gdb/mipsnbsd-nat.c b/gnu/dist/toolchain/gdb/mipsnbsd-nat.c new file mode 100644 index 00000000000..0c4e4ca44c6 --- /dev/null +++ b/gnu/dist/toolchain/gdb/mipsnbsd-nat.c @@ -0,0 +1,408 @@ +/* Functions specific to running gdb native on a mips running NetBSD + Copyright 1997 Free Software Foundation, Inc. + Contributed by Jonathan Stone(jonathan@dsg.stanford.edu) at Stanford + +This file is part of GDB. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include <sys/types.h> +#include <sys/ptrace.h> +#include <machine/reg.h> +#include <machine/pcb.h> +#include <setjmp.h> + +#include "defs.h" +#include "inferior.h" +#include "target.h" +#include "gdbcore.h" + +#define JB_ELEMENT_SIZE 4 + +void +fetch_inferior_registers (regno) + int regno; +{ + struct reg inferior_registers; + struct fpreg inferior_fp_registers; + + bzero(&inferior_registers, sizeof(inferior_registers)); + ptrace (PT_GETREGS, inferior_pid, + (PTRACE_ARG3_TYPE) &inferior_registers, 0); + + memcpy (®isters[REGISTER_BYTE (0)], + &inferior_registers, sizeof(inferior_registers)); + + bzero(&inferior_fp_registers, sizeof(inferior_fp_registers)); + ptrace (PT_GETFPREGS, inferior_pid, + (PTRACE_ARG3_TYPE) &inferior_fp_registers, 0); + + memcpy (®isters[REGISTER_BYTE (FP0_REGNUM)], + &inferior_fp_registers, sizeof(struct fpreg)); + + registers_fetched (); +} + +void +store_inferior_registers (regno) + int regno; +{ + struct reg inferior_registers; + struct fpreg inferior_fp_registers; + + memcpy (&inferior_registers, ®isters[REGISTER_BYTE (0)], + sizeof(inferior_registers)); + + ptrace (PT_SETREGS, inferior_pid, + (PTRACE_ARG3_TYPE) &inferior_registers, 0); + + memcpy (&inferior_fp_registers, ®isters[REGISTER_BYTE (FP0_REGNUM)], + sizeof(inferior_fp_registers)); + + ptrace (PT_SETFPREGS, inferior_pid, + (PTRACE_ARG3_TYPE) &inferior_fp_registers, 0); + + registers_fetched (); +} + + +/* Figure out where the longjmp will land. + We expect the first arg to be a pointer to the jmp_buf structure from which + we extract the pc (JB_PC) that we will land at. The pc is copied into PC. + This routine returns true on success. */ + +int +get_longjmp_target(pc) + CORE_ADDR *pc; +{ + CORE_ADDR jb_addr; + char buf[TARGET_PTR_BIT / TARGET_CHAR_BIT]; + + jb_addr = read_register (A0_REGNUM); + + if (target_read_memory (jb_addr + JB_PC * JB_ELEMENT_SIZE, buf, + TARGET_PTR_BIT / TARGET_CHAR_BIT)) + return 0; + + *pc = extract_address (buf, TARGET_PTR_BIT / TARGET_CHAR_BIT); + + return 1; +} + + +/* XXX - Add this to machine/regs.h instead? */ +struct md_core { + struct reg intreg; + struct fpreg freg; +}; + + +/* Extract the register values out of the core file and store + them where `read_register' will find them. + + CORE_REG_SECT points to the register values themselves, read into memory. + CORE_REG_SIZE is the size of that area. + WHICH says which set of registers we are handling (0 = int, 2 = float + on machines where they are discontiguous). + REG_ADDR is the offset from u.u_ar0 to the register values relative to + core_reg_sect. This is used with old-fashioned core files to + locate the registers in a large upage-plus-stack ".reg" section. + Original upage address X is at location core_reg_sect+x+reg_addr. + */ +void +fetch_core_registers (core_reg_sect, core_reg_size, which, ignore) + char *core_reg_sect; + unsigned core_reg_size; + int which; + unsigned int ignore; /* reg addr, unused in this version */ +{ + struct md_core *core_reg; + + core_reg = (struct md_core *)core_reg_sect; + + /* We get everything from the .reg section. */ + if (which != 0) + return; + + /* Integer registers */ + memcpy(®isters[REGISTER_BYTE (0)], + &core_reg->intreg, sizeof(struct reg)); + + /* Floating point registers */ + memcpy(®isters[REGISTER_BYTE (FP0_REGNUM)], + &core_reg->freg, sizeof(struct fpreg)); + + registers_fetched (); +} + +#ifdef FETCH_KCORE_REGISTERS +/* Get registers from a kernel crash dump. + */ +void +fetch_kcore_registers(pcb) +struct pcb *pcb; +{ + /* First clear out any garbage. */ + memset(registers, '\0', REGISTER_BYTES); + + supply_register(16, (char *)&pcb->pcb_context[0x0]); /* s0 */ + supply_register(17, (char *)&pcb->pcb_context[0x1]); /* s1 */ + supply_register(18, (char *)&pcb->pcb_context[0x2]); /* s2 */ + supply_register(19, (char *)&pcb->pcb_context[0x3]); /* s3 */ + supply_register(20, (char *)&pcb->pcb_context[0x4]); /* s4 */ + supply_register(21, (char *)&pcb->pcb_context[0x5]); /* s5 */ + supply_register(22, (char *)&pcb->pcb_context[0x6]); /* s6 */ + supply_register(23, (char *)&pcb->pcb_context[0x7]); /* s7 */ + supply_register(30, (char *)&pcb->pcb_context[0x9]); /* s8 */ + + supply_register(SP_REGNUM, (char *)&pcb->pcb_context[0x8]); /* sp */ + supply_register(RA_REGNUM, (char *)&pcb->pcb_context[0xa]); /* ra */ + supply_register(PC_REGNUM, (char *)&pcb->pcb_context[0xa]); /* ra is pc */ + supply_register(PS_REGNUM, (char *)&pcb->pcb_context[0xb]); /* sr */ + + /* The kernel does not use the FPU, so ignore it. */ + registers_fetched (); +} +#endif /* FETCH_KCORE_REGISTERS */ + + +/* Register that we are able to handle core file formats. + FIXME: is this really bfd_target_unknown_flavour? */ + +static struct core_fns netbsd_core_fns = +{ + bfd_target_unknown_flavour, /* core_flavour */ + default_check_format, /* check_format */ + default_core_sniffer, /* core_sniffer */ + fetch_core_registers, /* core_read_registers */ + NULL /* next */ +}; + +void +_initialize_mipsbsd_nat () +{ + add_core_fns (&netbsd_core_fns); +} + +int one_stepped; +CORE_ADDR target_addr; +CORE_ADDR step_addr; +long step_cache [3]; + +void netbsd_mips_software_single_step (unsigned int sig, int bp_p) +{ + CORE_ADDR pc; + CORE_ADDR epc; + CORE_ADDR next; + unsigned long cause; + unsigned long delay_instruction; + + if (!one_stepped) + { + epc = read_register (PC_REGNUM); + cause = read_register (CAUSE_REGNUM); + pc = epc; +#define CAUSE_BD 0x80000000UL + if (cause & CAUSE_BD) + pc += 4; + next = pc + 4; + target_addr = 0; + step_addr = next; + + if (cause & CAUSE_BD) + { + delay_instruction = + read_memory_integer (epc, sizeof(delay_instruction)); + +/* Main instruction opcode mask - top six bits... */ +#define MI_IMASK 0xfc000000UL +/* Opcode for ``special'' instructions.... */ +#define MI_SPECIAL 0x0 +/* Opcode for ``regimm'' instructions... */ +#define MI_REGIMM 0x04000000 +/* Mask for special instruction opcodes... */ +#if 0 +# define MS_IMASK 0x37 /* XXX Mellon's original, broken? */ +#else +# define MS_IMASK 0x3f /* XXX jrs attempt at fix */ +#endif + +/* JALR and JR are special instructions... */ +#define MS_JALR 9 +#define MS_JR 8 +/* Target register for jump... */ +#define MS_JR_REG(x) (((x) & 0x03e00000) >> 21) +/* J and JAL are regular instructions... */ +#define MI_J 0x08000000 +#define MI_JAL 0x0c000000 +/* All the bits following the opcode are used in J and JAL instructions... */ +#define MI_JMASK (~MI_IMASK) +#define MI_JSIGN 0x20000000 +/* Coprocessor instructions use the bottom two bits of the opcode as a + coprocessor id, so we only test the top four bits to see if this is a + COPz instruction... */ +#define MC_MASK 0xf0000000UL +#define MC_COPz 0x40000000 +/* The coprocessor subopcode is in the five bits following the regular + instruction opcode... */ +#define MCB_MASK 0x03e00000 +/* All coprocessor branches have the following subopcode... */ +#define MCB_BC 0x01000000 +/* Offsets for coprocessor branches are contained in the bottom 16 bis. */ +#define MCB_OFFSET 0xffff +/* The following are all the branch instructions with regular opcodes: */ +#define MI_BEQ 0x10000000 +#define MI_BEQL 0x50000000 +#define MI_BGTZ 0x1c000000 +#define MI_BGTZL 0x5c000000 +#define MI_BLEZ 0x18000000 +#define MI_BLEZL 0x58000000 +#define MI_BNE 0x14000000 +#define MI_BNEL 0x54000000 +/* They also use the lower sixteen bits for their target offset... */ +#define BRANCH_OFFSET 0xffff +/* REGIMM instructions have a second opcode in bits 20 through 16... */ +#define REGIMM_MASK 0x001f0000 +/* The following are all the ``regimm'' branch instructions: */ +#define MRI_BGEZ 0x00010000 +#define MRI_BGEZAL 0x00110000 +#define MRI_BGEZALL 0x00130000 +#define MRI_BGEZL 0x00030000 +#define MRI_BLTZ 0x00000000 +#define MRI_BLTZAL 0x00100000 +#define MRI_BLTZALL 0x00120000 +#define MRI_BLTZL 0x00020000 + + /* Decode the instruction sufficiently to determine + the branch target... */ + switch (delay_instruction & MI_IMASK) + { + case MI_J: + case MI_JAL: + target_addr = delay_instruction & MI_JMASK; + /* Sign extend... */ + if (target_addr & MI_JSIGN) + target_addr |= ~(CORE_ADDR)MI_JMASK; + target_addr += (pc >> 2) & ~MI_JMASK; + target_addr <<= 2; + step_addr = 0; + break; + case MI_SPECIAL: + switch (delay_instruction & MS_IMASK) + { + case MS_JALR: + case MS_JR: + target_addr += + read_register (MS_JR_REG (delay_instruction)); + step_addr = 0; + break; + default: + bad_delay: + error ("In delay slot of non-branch instruction: %x\n", + delay_instruction); + break; + } + break; + case MI_REGIMM: + switch (delay_instruction & REGIMM_MASK) + { + case MRI_BGEZ: + case MRI_BGEZAL: + case MRI_BGEZALL: + case MRI_BGEZL: + case MRI_BLTZ: + case MRI_BLTZAL: + case MRI_BLTZALL: + case MRI_BLTZL: + /* Compiler should sign extend this... */ + target_addr = (short)delay_instruction; + target_addr <<= 2; + target_addr += pc; + break; + default: + error ("In delay slot, register-immediate insn: %x\n", + delay_instruction); + goto bad_delay; + } + break; + case MI_BEQ: + case MI_BEQL: + case MI_BGTZ: + case MI_BGTZL: + case MI_BLEZ: + case MI_BLEZL: + case MI_BNE: + case MI_BNEL: + target_addr = (short)delay_instruction; + target_addr <<= 2; + target_addr += pc; + break; + default: + error ("In delay slot, unrecognised instruction: %x\n", + delay_instruction); + goto bad_delay; + } + } + + /* Don't try to put down two breakpoints in the same spot... */ + if (step_addr == target_addr) + target_addr = 0; + + if (step_addr) + { + target_insert_breakpoint (step_addr, (char *)&step_cache [0]); + if (step_addr + 4 != target_addr) + target_insert_breakpoint (step_addr + 4, (char *)&step_cache [1]); + } + if (target_addr) + { + target_insert_breakpoint (target_addr, (char *)&step_cache [2]); + } + + /* If the breakpoint occurred in a branch instruction, + re-run the branch (the breakpoint instruction should + be gone by now)... */ + if (epc != pc) + { + write_register (PC_REGNUM, epc); + } + one_stepped = 1; + return; + } + else + { + epc = read_register (PC_REGNUM); + cause = read_register (CAUSE_REGNUM); + pc = epc; +#define CAUSE_BD 0x80000000UL + if (cause & CAUSE_BD) + pc += 4; + /* Remove step breakpoints */ + if (step_addr) + { + target_remove_breakpoint (step_addr, (char *)&step_cache [0]); + if (step_addr + 4 != target_addr) + target_remove_breakpoint (step_addr + 4, (char *)&step_cache [1]); + } + + if (target_addr) + { + target_remove_breakpoint (target_addr, (char *)&step_cache [2]); + target_addr = 0; + } + + one_stepped = 0; + } +} diff --git a/gnu/dist/toolchain/gdb/solib.c b/gnu/dist/toolchain/gdb/solib.c index f0584fcc856..8dea61214b8 100644 --- a/gnu/dist/toolchain/gdb/solib.c +++ b/gnu/dist/toolchain/gdb/solib.c @@ -139,7 +139,7 @@ static CORE_ADDR flag_addr; #define LM_NEXT(so) (SOLIB_EXTRACT_ADDRESS ((so) -> lm.l_next)) #define LM_NAME(so) (SOLIB_EXTRACT_ADDRESS ((so) -> lm.l_name)) #ifdef __mips__ -#define LM_OFFS(so) ((so) -> lm.l_offs) +#define LM_OFFS(so) (u_int32_t)((so) -> lm.l_offs) #endif /* Test for first link map entry; first entry is the exec-file. */ #define IGNORE_FIRST_LINK_MAP_ENTRY(so) \ |
