diff options
| author | paul <paul@NetBSD.org> | 1993-07-16 00:27:07 +0000 |
|---|---|---|
| committer | paul <paul@NetBSD.org> | 1993-07-16 00:27:07 +0000 |
| commit | e969d9dd00de0adce800fc57b2631020dbe455e8 (patch) | |
| tree | bbb70b57a978e3c7b0f0585d238ee447e436f47a /gnu | |
| parent | a2b68b3bae7d9a171941c684ad2759ca802a50cb (diff) | |
Configured gcc2 for multiple architectures.
Diffstat (limited to 'gnu')
22 files changed, 20436 insertions, 1 deletions
diff --git a/gnu/usr.bin/gcc2/i386/aux-output.c b/gnu/usr.bin/gcc2/i386/aux-output.c new file mode 100644 index 00000000000..d0b11961b7b --- /dev/null +++ b/gnu/usr.bin/gcc2/i386/aux-output.c @@ -0,0 +1,1921 @@ +/* Subroutines for insn-output.c for Intel 80386. + Copyright (C) 1988, 1992 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + +#include <stdio.h> +#include <setjmp.h> +#include "config.h" +#include "rtl.h" +#include "regs.h" +#include "hard-reg-set.h" +#include "real.h" +#include "insn-config.h" +#include "conditions.h" +#include "insn-flags.h" +#include "output.h" +#include "insn-attr.h" +#include "tree.h" +#include "flags.h" + +#ifdef EXTRA_CONSTRAINT +/* If EXTRA_CONSTRAINT is defined, then the 'S' + constraint in REG_CLASS_FROM_LETTER will no longer work, and various + asm statements that need 'S' for class SIREG will break. */ + error EXTRA_CONSTRAINT conflicts with S constraint letter +/* The previous line used to be #error, but some compilers barf + even if the conditional was untrue. */ +#endif + +#define AT_BP(mode) (gen_rtx (MEM, (mode), frame_pointer_rtx)) + +extern FILE *asm_out_file; +extern char *strcat (); + +char *singlemove_string (); +char *output_move_const_single (); +char *output_fp_cc0_set (); + +char *hi_reg_name[] = HI_REGISTER_NAMES; +char *qi_reg_name[] = QI_REGISTER_NAMES; +char *qi_high_reg_name[] = QI_HIGH_REGISTER_NAMES; + +/* Array of the smallest class containing reg number REGNO, indexed by + REGNO. Used by REGNO_REG_CLASS in i386.h. */ + +enum reg_class regclass_map[FIRST_PSEUDO_REGISTER] = +{ + /* ax, dx, cx, bx */ + AREG, DREG, CREG, BREG, + /* si, di, bp, sp */ + SIREG, DIREG, INDEX_REGS, GENERAL_REGS, + /* FP registers */ + FP_TOP_REG, FP_SECOND_REG, FLOAT_REGS, FLOAT_REGS, + FLOAT_REGS, FLOAT_REGS, FLOAT_REGS, FLOAT_REGS, + /* arg pointer */ + INDEX_REGS +}; + +/* Test and compare insns in i386.md store the information needed to + generate branch and scc insns here. */ + +struct rtx_def *i386_compare_op0, *i386_compare_op1; +struct rtx_def *(*i386_compare_gen)(), *(*i386_compare_gen_eq)(); + +/* Output an insn whose source is a 386 integer register. SRC is the + rtx for the register, and TEMPLATE is the op-code template. SRC may + be either SImode or DImode. + + The template will be output with operands[0] as SRC, and operands[1] + as a pointer to the top of the 386 stack. So a call from floatsidf2 + would look like this: + + output_op_from_reg (operands[1], AS1 (fild%z0,%1)); + + where %z0 corresponds to the caller's operands[1], and is used to + emit the proper size suffix. + + ??? Extend this to handle HImode - a 387 can load and store HImode + values directly. */ + +void +output_op_from_reg (src, template) + rtx src; + char *template; +{ + rtx xops[4]; + + xops[0] = src; + xops[1] = AT_SP (Pmode); + xops[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (src))); + xops[3] = stack_pointer_rtx; + + if (GET_MODE_SIZE (GET_MODE (src)) > UNITS_PER_WORD) + { + rtx high = gen_rtx (REG, SImode, REGNO (src) + 1); + output_asm_insn (AS1 (push%L0,%0), &high); + } + output_asm_insn (AS1 (push%L0,%0), &src); + + output_asm_insn (template, xops); + + output_asm_insn (AS2 (add%L3,%2,%3), xops); +} + +/* Output an insn to pop an value from the 387 top-of-stack to 386 + register DEST. The 387 register stack is popped if DIES is true. If + the mode of DEST is an integer mode, a `fist' integer store is done, + otherwise a `fst' float store is done. */ + +void +output_to_reg (dest, dies) + rtx dest; + int dies; +{ + rtx xops[4]; + + xops[0] = AT_SP (Pmode); + xops[1] = stack_pointer_rtx; + xops[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (dest))); + xops[3] = dest; + + output_asm_insn (AS2 (sub%L1,%2,%1), xops); + + if (GET_MODE_CLASS (GET_MODE (dest)) == MODE_INT) + { + if (dies) + output_asm_insn (AS1 (fistp%z3,%y0), xops); + else + output_asm_insn (AS1 (fist%z3,%y0), xops); + } + else if (GET_MODE_CLASS (GET_MODE (dest)) == MODE_FLOAT) + { + if (dies) + output_asm_insn (AS1 (fstp%z3,%y0), xops); + else + output_asm_insn (AS1 (fst%z3,%y0), xops); + } + else + abort (); + + output_asm_insn (AS1 (pop%L0,%0), &dest); + + if (GET_MODE_SIZE (GET_MODE (dest)) > UNITS_PER_WORD) + { + dest = gen_rtx (REG, SImode, REGNO (dest) + 1); + output_asm_insn (AS1 (pop%L0,%0), &dest); + } +} + +char * +singlemove_string (operands) + rtx *operands; +{ + rtx x; + if (GET_CODE (operands[0]) == MEM + && GET_CODE (x = XEXP (operands[0], 0)) == PRE_DEC) + { + if (XEXP (x, 0) != stack_pointer_rtx) + abort (); + return "push%L1 %1"; + } + else if (GET_CODE (operands[1]) == CONST_DOUBLE) + { + return output_move_const_single (operands); + } + else if (GET_CODE (operands[0]) == REG || GET_CODE (operands[1]) == REG) + return AS2 (mov%L0,%1,%0); + else if (CONSTANT_P (operands[1])) + return AS2 (mov%L0,%1,%0); + else + { + output_asm_insn ("push%L1 %1", operands); + return "pop%L0 %0"; + } +} + +/* Return a REG that occurs in ADDR with coefficient 1. + ADDR can be effectively incremented by incrementing REG. */ + +static rtx +find_addr_reg (addr) + rtx addr; +{ + while (GET_CODE (addr) == PLUS) + { + if (GET_CODE (XEXP (addr, 0)) == REG) + addr = XEXP (addr, 0); + else if (GET_CODE (XEXP (addr, 1)) == REG) + addr = XEXP (addr, 1); + else if (CONSTANT_P (XEXP (addr, 0))) + addr = XEXP (addr, 1); + else if (CONSTANT_P (XEXP (addr, 1))) + addr = XEXP (addr, 0); + else + abort (); + } + if (GET_CODE (addr) == REG) + return addr; + abort (); +} + +/* Output an insn to add the constant N to the register X. */ + +static void +asm_add (n, x) + int n; + rtx x; +{ + rtx xops[2]; + xops[1] = x; + if (n < 0) + { + xops[0] = GEN_INT (-n); + output_asm_insn (AS2 (sub%L0,%0,%1), xops); + } + else if (n > 0) + { + xops[0] = GEN_INT (n); + output_asm_insn (AS2 (add%L0,%0,%1), xops); + } +} + +/* Output assembler code to perform a doubleword move insn + with operands OPERANDS. */ + +char * +output_move_double (operands) + rtx *operands; +{ + enum {REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP } optype0, optype1; + rtx latehalf[2]; + rtx addreg0 = 0, addreg1 = 0; + int dest_overlapped_low = 0; + + /* First classify both operands. */ + + if (REG_P (operands[0])) + optype0 = REGOP; + else if (offsettable_memref_p (operands[0])) + optype0 = OFFSOP; + else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC) + optype0 = POPOP; + else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC) + optype0 = PUSHOP; + else if (GET_CODE (operands[0]) == MEM) + optype0 = MEMOP; + else + optype0 = RNDOP; + + if (REG_P (operands[1])) + optype1 = REGOP; + else if (CONSTANT_P (operands[1])) + optype1 = CNSTOP; + else if (offsettable_memref_p (operands[1])) + optype1 = OFFSOP; + else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC) + optype1 = POPOP; + else if (GET_CODE (XEXP (operands[1], 0)) == PRE_DEC) + optype1 = PUSHOP; + else if (GET_CODE (operands[1]) == MEM) + optype1 = MEMOP; + else + optype1 = RNDOP; + + /* Check for the cases that the operand constraints are not + supposed to allow to happen. Abort if we get one, + because generating code for these cases is painful. */ + + if (optype0 == RNDOP || optype1 == RNDOP) + abort (); + + /* If one operand is decrementing and one is incrementing + decrement the former register explicitly + and change that operand into ordinary indexing. */ + + if (optype0 == PUSHOP && optype1 == POPOP) + { + operands[0] = XEXP (XEXP (operands[0], 0), 0); + asm_add (-8, operands[0]); + operands[0] = gen_rtx (MEM, DImode, operands[0]); + optype0 = OFFSOP; + } + if (optype0 == POPOP && optype1 == PUSHOP) + { + operands[1] = XEXP (XEXP (operands[1], 0), 0); + asm_add (-8, operands[1]); + operands[1] = gen_rtx (MEM, DImode, operands[1]); + optype1 = OFFSOP; + } + + /* If an operand is an unoffsettable memory ref, find a register + we can increment temporarily to make it refer to the second word. */ + + if (optype0 == MEMOP) + addreg0 = find_addr_reg (XEXP (operands[0], 0)); + + if (optype1 == MEMOP) + addreg1 = find_addr_reg (XEXP (operands[1], 0)); + + /* Ok, we can do one word at a time. + Normally we do the low-numbered word first, + but if either operand is autodecrementing then we + do the high-numbered word first. + + In either case, set up in LATEHALF the operands to use + for the high-numbered word and in some cases alter the + operands in OPERANDS to be suitable for the low-numbered word. */ + + if (optype0 == REGOP) + latehalf[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); + else if (optype0 == OFFSOP) + latehalf[0] = adj_offsettable_operand (operands[0], 4); + else + latehalf[0] = operands[0]; + + if (optype1 == REGOP) + latehalf[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); + else if (optype1 == OFFSOP) + latehalf[1] = adj_offsettable_operand (operands[1], 4); + else if (optype1 == CNSTOP) + { + if (GET_CODE (operands[1]) == CONST_DOUBLE) + split_double (operands[1], &operands[1], &latehalf[1]); + else if (CONSTANT_P (operands[1])) + { + if (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) < 0) + latehalf[1] = constm1_rtx; + else + latehalf[1] = const0_rtx; + } + } + else + latehalf[1] = operands[1]; + + /* If insn is effectively movd N (sp),-(sp) then we will do the + high word first. We should use the adjusted operand 1 (which is N+4 (sp)) + for the low word as well, to compensate for the first decrement of sp. */ + if (optype0 == PUSHOP + && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM + && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1])) + operands[1] = latehalf[1]; + + /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)), + if the upper part of reg N does not appear in the MEM, arrange to + emit the move late-half first. Otherwise, compute the MEM address + into the upper part of N and use that as a pointer to the memory + operand. */ + if (optype0 == REGOP + && (optype1 == OFFSOP || optype1 == MEMOP)) + { + if (reg_mentioned_p (operands[0], XEXP (operands[1], 0)) + && reg_mentioned_p (latehalf[0], XEXP (operands[1], 0))) + { + /* If both halves of dest are used in the src memory address, + compute the address into latehalf of dest. */ + rtx xops[2]; + xops[0] = latehalf[0]; + xops[1] = XEXP (operands[1], 0); + output_asm_insn (AS2 (lea%L0,%a1,%0), xops); + operands[1] = gen_rtx (MEM, DImode, latehalf[0]); + latehalf[1] = adj_offsettable_operand (operands[1], 4); + } + else if (reg_mentioned_p (operands[0], XEXP (operands[1], 0))) + /* If the low half of dest is mentioned in the source memory + address, the arrange to emit the move late half first. */ + dest_overlapped_low = 1; + } + + /* If one or both operands autodecrementing, + do the two words, high-numbered first. */ + + /* Likewise, the first move would clobber the source of the second one, + do them in the other order. This happens only for registers; + such overlap can't happen in memory unless the user explicitly + sets it up, and that is an undefined circumstance. */ + + if (optype0 == PUSHOP || optype1 == PUSHOP + || (optype0 == REGOP && optype1 == REGOP + && REGNO (operands[0]) == REGNO (latehalf[1])) + || dest_overlapped_low) + { + /* Make any unoffsettable addresses point at high-numbered word. */ + if (addreg0) + asm_add (4, addreg0); + if (addreg1) + asm_add (4, addreg1); + + /* Do that word. */ + output_asm_insn (singlemove_string (latehalf), latehalf); + + /* Undo the adds we just did. */ + if (addreg0) + asm_add (-4, addreg0); + if (addreg1) + asm_add (-4, addreg1); + + /* Do low-numbered word. */ + return singlemove_string (operands); + } + + /* Normal case: do the two words, low-numbered first. */ + + output_asm_insn (singlemove_string (operands), operands); + + /* Make any unoffsettable addresses point at high-numbered word. */ + if (addreg0) + asm_add (4, addreg0); + if (addreg1) + asm_add (4, addreg1); + + /* Do that word. */ + output_asm_insn (singlemove_string (latehalf), latehalf); + + /* Undo the adds we just did. */ + if (addreg0) + asm_add (-4, addreg0); + if (addreg1) + asm_add (-4, addreg1); + + return ""; +} + +int +standard_80387_constant_p (x) + rtx x; +{ +#if ! defined (REAL_IS_NOT_DOUBLE) || defined (REAL_ARITHMETIC) + REAL_VALUE_TYPE d; + jmp_buf handler; + int is0, is1; + + if (setjmp (handler)) + return 0; + + set_float_handler (handler); + REAL_VALUE_FROM_CONST_DOUBLE (d, x); + is0 = REAL_VALUES_EQUAL (d, dconst0); + is1 = REAL_VALUES_EQUAL (d, dconst1); + set_float_handler (NULL_PTR); + + if (is0) + return 1; + + if (is1) + return 2; + + /* Note that on the 80387, other constants, such as pi, + are much slower to load as standard constants + than to load from doubles in memory! */ +#endif + + return 0; +} + +char * +output_move_const_single (operands) + rtx *operands; +{ + if (FP_REG_P (operands[0])) + { + int conval = standard_80387_constant_p (operands[1]); + + if (conval == 1) + return "fldz"; + + if (conval == 2) + return "fld1"; + } + if (GET_CODE (operands[1]) == CONST_DOUBLE) + { + union { int i[2]; double d;} u1; + union { int i; float f;} u2; + u1.i[0] = CONST_DOUBLE_LOW (operands[1]); + u1.i[1] = CONST_DOUBLE_HIGH (operands[1]); + u2.f = u1.d; + operands[1] = GEN_INT (u2.i); + } + return singlemove_string (operands); +} + +/* Returns 1 if OP is either a symbol reference or a sum of a symbol + reference and a constant. */ + +int +symbolic_operand (op, mode) + register rtx op; + enum machine_mode mode; +{ + switch (GET_CODE (op)) + { + case SYMBOL_REF: + case LABEL_REF: + return 1; + case CONST: + op = XEXP (op, 0); + return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF + || GET_CODE (XEXP (op, 0)) == LABEL_REF) + && GET_CODE (XEXP (op, 1)) == CONST_INT); + default: + return 0; + } +} + +/* Test for a valid operand for a call instruction. + Don't allow the arg pointer register or virtual regs + since they may change into reg + const, which the patterns + can't handle yet. */ + +int +call_insn_operand (op, mode) + rtx op; + enum machine_mode mode; +{ + if (GET_CODE (op) == MEM + && ((CONSTANT_ADDRESS_P (XEXP (op, 0)) + /* This makes a difference for PIC. */ + && general_operand (XEXP (op, 0), Pmode)) + || (GET_CODE (XEXP (op, 0)) == REG + && XEXP (op, 0) != arg_pointer_rtx + && !(REGNO (XEXP (op, 0)) >= FIRST_PSEUDO_REGISTER + && REGNO (XEXP (op, 0)) <= LAST_VIRTUAL_REGISTER)))) + return 1; + return 0; +} + +/* Like call_insn_operand but allow (mem (symbol_ref ...)) + even if pic. */ + +int +expander_call_insn_operand (op, mode) + rtx op; + enum machine_mode mode; +{ + if (GET_CODE (op) == MEM + && (CONSTANT_ADDRESS_P (XEXP (op, 0)) + || (GET_CODE (XEXP (op, 0)) == REG + && XEXP (op, 0) != arg_pointer_rtx + && !(REGNO (XEXP (op, 0)) >= FIRST_PSEUDO_REGISTER + && REGNO (XEXP (op, 0)) <= LAST_VIRTUAL_REGISTER)))) + return 1; + return 0; +} + +/* Returns 1 if OP contains a symbol reference */ + +int +symbolic_reference_mentioned_p (op) + rtx op; +{ + register char *fmt; + register int i; + + if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF) + return 1; + + fmt = GET_RTX_FORMAT (GET_CODE (op)); + for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--) + { + if (fmt[i] == 'E') + { + register int j; + + for (j = XVECLEN (op, i) - 1; j >= 0; j--) + if (symbolic_reference_mentioned_p (XVECEXP (op, i, j))) + return 1; + } + else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i))) + return 1; + } + + return 0; +} + +/* Return a legitimate reference for ORIG (an address) using the + register REG. If REG is 0, a new pseudo is generated. + + There are three types of references that must be handled: + + 1. Global data references must load the address from the GOT, via + the PIC reg. An insn is emitted to do this load, and the reg is + returned. + + 2. Static data references must compute the address as an offset + from the GOT, whose base is in the PIC reg. An insn is emitted to + compute the address into a reg, and the reg is returned. Static + data objects have SYMBOL_REF_FLAG set to differentiate them from + global data objects. + + 3. Constant pool addresses must be handled special. They are + considered legitimate addresses, but only if not used with regs. + When printed, the output routines know to print the reference with the + PIC reg, even though the PIC reg doesn't appear in the RTL. + + GO_IF_LEGITIMATE_ADDRESS rejects symbolic references unless the PIC + reg also appears in the address (except for constant pool references, + noted above). + + "switch" statements also require special handling when generating + PIC code. See comments by the `casesi' insn in i386.md for details. */ + +rtx +legitimize_pic_address (orig, reg) + rtx orig; + rtx reg; +{ + rtx addr = orig; + rtx new = orig; + + if (GET_CODE (addr) == SYMBOL_REF || GET_CODE (addr) == LABEL_REF) + { + if (GET_CODE (addr) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (addr)) + reg = new = orig; + else + { + if (reg == 0) + reg = gen_reg_rtx (Pmode); + + if (GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_FLAG (addr)) + new = gen_rtx (PLUS, Pmode, pic_offset_table_rtx, orig); + else + new = gen_rtx (MEM, Pmode, + gen_rtx (PLUS, Pmode, + pic_offset_table_rtx, orig)); + + emit_move_insn (reg, new); + } + current_function_uses_pic_offset_table = 1; + return reg; + } + else if (GET_CODE (addr) == CONST || GET_CODE (addr) == PLUS) + { + rtx base; + + if (GET_CODE (addr) == CONST) + { + addr = XEXP (addr, 0); + if (GET_CODE (addr) != PLUS) + abort (); + } + + if (XEXP (addr, 0) == pic_offset_table_rtx) + return orig; + + if (reg == 0) + reg = gen_reg_rtx (Pmode); + + base = legitimize_pic_address (XEXP (addr, 0), reg); + addr = legitimize_pic_address (XEXP (addr, 1), + base == reg ? NULL_RTX : reg); + + if (GET_CODE (addr) == CONST_INT) + return plus_constant (base, INTVAL (addr)); + + if (GET_CODE (addr) == PLUS && CONSTANT_P (XEXP (addr, 1))) + { + base = gen_rtx (PLUS, Pmode, base, XEXP (addr, 0)); + addr = XEXP (addr, 1); + } + return gen_rtx (PLUS, Pmode, base, addr); + } + return new; +} + +/* Emit insns to move operands[1] into operands[0]. */ + +void +emit_pic_move (operands, mode) + rtx *operands; + enum machine_mode mode; +{ + rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode); + + if (GET_CODE (operands[0]) == MEM && SYMBOLIC_CONST (operands[1])) + operands[1] = (rtx) force_reg (SImode, operands[1]); + else + operands[1] = legitimize_pic_address (operands[1], temp); +} + +/* This function generates the assembly code for function entry. + FILE is an stdio stream to output the code to. + SIZE is an int: how many units of temporary storage to allocate. */ + +void +function_prologue (file, size) + FILE *file; + int size; +{ + register int regno; + int limit; + rtx xops[4]; + int pic_reg_used = flag_pic && (current_function_uses_pic_offset_table + || current_function_uses_const_pool); + + xops[0] = stack_pointer_rtx; + xops[1] = frame_pointer_rtx; + xops[2] = GEN_INT (size); + if (frame_pointer_needed) + { + output_asm_insn ("push%L1 %1", xops); + output_asm_insn (AS2 (mov%L0,%0,%1), xops); + } + + if (size) + output_asm_insn (AS2 (sub%L0,%2,%0), xops); + + /* Note If use enter it is NOT reversed args. + This one is not reversed from intel!! + I think enter is slower. Also sdb doesn't like it. + But if you want it the code is: + { + xops[3] = const0_rtx; + output_asm_insn ("enter %2,%3", xops); + } + */ + limit = (frame_pointer_needed ? FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM); + for (regno = limit - 1; regno >= 0; regno--) + if ((regs_ever_live[regno] && ! call_used_regs[regno]) + || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used)) + { + xops[0] = gen_rtx (REG, SImode, regno); + output_asm_insn ("push%L0 %0", xops); + } + + if (pic_reg_used) + { + xops[0] = pic_offset_table_rtx; + xops[1] = (rtx) gen_label_rtx (); + + output_asm_insn (AS1 (call,%P1), xops); + ASM_OUTPUT_INTERNAL_LABEL (file, "L", CODE_LABEL_NUMBER (xops[1])); + output_asm_insn (AS1 (pop%L0,%0), xops); + output_asm_insn ("addl $_GLOBAL_OFFSET_TABLE_+[.-%P1],%0", xops); + } +} + +/* Return 1 if it is appropriate to emit `ret' instructions in the + body of a function. Do this only if the epilogue is simple, needing a + couple of insns. Prior to reloading, we can't tell how many registers + must be saved, so return 0 then. + + If NON_SAVING_SETJMP is defined and true, then it is not possible + for the epilogue to be simple, so return 0. This is a special case + since NON_SAVING_SETJMP will not cause regs_ever_live to change until + final, but jump_optimize may need to know sooner if a `return' is OK. */ + +int +simple_386_epilogue () +{ + int regno; + int nregs = 0; + int reglimit = (frame_pointer_needed + ? FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM); + int pic_reg_used = flag_pic && (current_function_uses_pic_offset_table + || current_function_uses_const_pool); + +#ifdef NON_SAVING_SETJMP + if (NON_SAVING_SETJMP && current_function_calls_setjmp) + return 0; +#endif + + if (! reload_completed) + return 0; + + for (regno = reglimit - 1; regno >= 0; regno--) + if ((regs_ever_live[regno] && ! call_used_regs[regno]) + || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used)) + nregs++; + + return nregs == 0 || ! frame_pointer_needed; +} + +/* This function generates the assembly code for function exit. + FILE is an stdio stream to output the code to. + SIZE is an int: how many units of temporary storage to deallocate. */ + +void +function_epilogue (file, size) + FILE *file; + int size; +{ + register int regno; + register int nregs, limit; + int offset; + rtx xops[3]; + int pic_reg_used = flag_pic && (current_function_uses_pic_offset_table + || current_function_uses_const_pool); + + /* Compute the number of registers to pop */ + + limit = (frame_pointer_needed + ? FRAME_POINTER_REGNUM + : STACK_POINTER_REGNUM); + + nregs = 0; + + for (regno = limit - 1; regno >= 0; regno--) + if ((regs_ever_live[regno] && ! call_used_regs[regno]) + || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used)) + nregs++; + + /* sp is often unreliable so we must go off the frame pointer, + */ + + /* In reality, we may not care if sp is unreliable, because we can + restore the register relative to the frame pointer. In theory, + since each move is the same speed as a pop, and we don't need the + leal, this is faster. For now restore multiple registers the old + way. */ + + offset = -size - (nregs * UNITS_PER_WORD); + + xops[2] = stack_pointer_rtx; + + if (nregs > 1 || ! frame_pointer_needed) + { + if (frame_pointer_needed) + { + xops[0] = adj_offsettable_operand (AT_BP (Pmode), offset); + output_asm_insn (AS2 (lea%L2,%0,%2), xops); + } + + for (regno = 0; regno < limit; regno++) + if ((regs_ever_live[regno] && ! call_used_regs[regno]) + || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used)) + { + xops[0] = gen_rtx (REG, SImode, regno); + output_asm_insn ("pop%L0 %0", xops); + } + } + else + for (regno = 0; regno < limit; regno++) + if ((regs_ever_live[regno] && ! call_used_regs[regno]) + || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used)) + { + xops[0] = gen_rtx (REG, SImode, regno); + xops[1] = adj_offsettable_operand (AT_BP (Pmode), offset); + output_asm_insn (AS2 (mov%L0,%1,%0), xops); + offset += 4; + } + + if (frame_pointer_needed) + { + /* On i486, mov & pop is faster than "leave". */ + + if (TARGET_486) + { + xops[0] = frame_pointer_rtx; + output_asm_insn (AS2 (mov%L2,%0,%2), xops); + output_asm_insn ("pop%L0 %0", xops); + } + else + output_asm_insn ("leave", xops); + } + else if (size) + { + /* If there is no frame pointer, we must still release the frame. */ + + xops[0] = GEN_INT (size); + output_asm_insn (AS2 (add%L2,%0,%2), xops); + } + + if (current_function_pops_args && current_function_args_size) + { + xops[1] = GEN_INT (current_function_pops_args); + + /* i386 can only pop 32K bytes (maybe 64K? Is it signed?). If + asked to pop more, pop return address, do explicit add, and jump + indirectly to the caller. */ + + if (current_function_pops_args >= 32768) + { + /* ??? Which register to use here? */ + xops[0] = gen_rtx (REG, SImode, 2); + output_asm_insn ("pop%L0 %0", xops); + output_asm_insn (AS2 (add%L2,%1,%2), xops); + output_asm_insn ("jmp %*%0", xops); + } + else + output_asm_insn ("ret %1", xops); + } + else + output_asm_insn ("ret", xops); +} + +/* Print an integer constant expression in assembler syntax. Addition + and subtraction are the only arithmetic that may appear in these + expressions. FILE is the stdio stream to write to, X is the rtx, and + CODE is the operand print code from the output string. */ + +static void +output_pic_addr_const (file, x, code) + FILE *file; + rtx x; + int code; +{ + char buf[256]; + + switch (GET_CODE (x)) + { + case PC: + if (flag_pic) + putc ('.', file); + else + abort (); + break; + + case SYMBOL_REF: + case LABEL_REF: + if (GET_CODE (x) == SYMBOL_REF) + assemble_name (file, XSTR (x, 0)); + else + { + ASM_GENERATE_INTERNAL_LABEL (buf, "L", + CODE_LABEL_NUMBER (XEXP (x, 0))); + assemble_name (asm_out_file, buf); + } + + if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x)) + fprintf (file, "@GOTOFF(%%ebx)"); + else if (code == 'P') + fprintf (file, "@PLT"); + else if (GET_CODE (x) == LABEL_REF || ! SYMBOL_REF_FLAG (x)) + fprintf (file, "@GOT"); + else + fprintf (file, "@GOTOFF"); + + break; + + case CODE_LABEL: + ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (x)); + assemble_name (asm_out_file, buf); + break; + + case CONST_INT: + fprintf (file, "%d", INTVAL (x)); + break; + + case CONST: + /* This used to output parentheses around the expression, + but that does not work on the 386 (either ATT or BSD assembler). */ + output_pic_addr_const (file, XEXP (x, 0), code); + break; + + case CONST_DOUBLE: + if (GET_MODE (x) == VOIDmode) + { + /* We can use %d if the number is <32 bits and positive. */ + if (CONST_DOUBLE_HIGH (x) || CONST_DOUBLE_LOW (x) < 0) + fprintf (file, "0x%x%08x", + CONST_DOUBLE_HIGH (x), CONST_DOUBLE_LOW (x)); + else + fprintf (file, "%d", CONST_DOUBLE_LOW (x)); + } + else + /* We can't handle floating point constants; + PRINT_OPERAND must handle them. */ + output_operand_lossage ("floating constant misused"); + break; + + case PLUS: + /* Some assemblers need integer constants to appear last (eg masm). */ + if (GET_CODE (XEXP (x, 0)) == CONST_INT) + { + output_pic_addr_const (file, XEXP (x, 1), code); + if (INTVAL (XEXP (x, 0)) >= 0) + fprintf (file, "+"); + output_pic_addr_const (file, XEXP (x, 0), code); + } + else + { + output_pic_addr_const (file, XEXP (x, 0), code); + if (INTVAL (XEXP (x, 1)) >= 0) + fprintf (file, "+"); + output_pic_addr_const (file, XEXP (x, 1), code); + } + break; + + case MINUS: + output_pic_addr_const (file, XEXP (x, 0), code); + fprintf (file, "-"); + output_pic_addr_const (file, XEXP (x, 1), code); + break; + + default: + output_operand_lossage ("invalid expression as operand"); + } +} + +/* Meaning of CODE: + f -- float insn (print a CONST_DOUBLE as a float rather than in hex). + D,L,W,B,Q,S -- print the opcode suffix for specified size of operand. + R -- print the prefix for register names. + z -- print the opcode suffix for the size of the current operand. + * -- print a star (in certain assembler syntax) + w -- print the operand as if it's a "word" (HImode) even if it isn't. + c -- don't print special prefixes before constant operands. +*/ + +void +print_operand (file, x, code) + FILE *file; + rtx x; + int code; +{ + if (code) + { + switch (code) + { + case '*': + if (USE_STAR) + putc ('*', file); + return; + + case 'L': + PUT_OP_SIZE (code, 'l', file); + return; + + case 'W': + PUT_OP_SIZE (code, 'w', file); + return; + + case 'B': + PUT_OP_SIZE (code, 'b', file); + return; + + case 'Q': + PUT_OP_SIZE (code, 'l', file); + return; + + case 'S': + PUT_OP_SIZE (code, 's', file); + return; + + case 'z': + /* 387 opcodes don't get size suffixes if the operands are + registers. */ + + if (STACK_REG_P (x)) + return; + + /* this is the size of op from size of operand */ + switch (GET_MODE_SIZE (GET_MODE (x))) + { + case 1: + PUT_OP_SIZE ('B', 'b', file); + return; + + case 2: + PUT_OP_SIZE ('W', 'w', file); + return; + + case 4: + if (GET_MODE (x) == SFmode) + { + PUT_OP_SIZE ('S', 's', file); + return; + } + else + PUT_OP_SIZE ('L', 'l', file); + return; + + case 8: + if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT) + { +#ifdef GAS_MNEMONICS + PUT_OP_SIZE ('Q', 'q', file); + return; +#else + PUT_OP_SIZE ('Q', 'l', file); /* Fall through */ +#endif + } + + PUT_OP_SIZE ('Q', 'l', file); + return; + } + + case 'b': + case 'w': + case 'k': + case 'h': + case 'y': + case 'P': + break; + + default: + { + char str[50]; + + sprintf (str, "invalid operand code `%c'", code); + output_operand_lossage (str); + } + } + } + if (GET_CODE (x) == REG) + { + PRINT_REG (x, code, file); + } + else if (GET_CODE (x) == MEM) + { + PRINT_PTR (x, file); + if (CONSTANT_ADDRESS_P (XEXP (x, 0))) + { + if (flag_pic) + output_pic_addr_const (file, XEXP (x, 0), code); + else + output_addr_const (file, XEXP (x, 0)); + } + else + output_address (XEXP (x, 0)); + } + else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode) + { + union { double d; int i[2]; } u; + union { float f; int i; } u1; + u.i[0] = CONST_DOUBLE_LOW (x); + u.i[1] = CONST_DOUBLE_HIGH (x); + u1.f = u.d; + PRINT_IMMED_PREFIX (file); + fprintf (file, "0x%x", u1.i); + } + else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode) + { + union { double d; int i[2]; } u; + u.i[0] = CONST_DOUBLE_LOW (x); + u.i[1] = CONST_DOUBLE_HIGH (x); + fprintf (file, "%.22e", u.d); + } + else + { + if (code != 'P') + { + if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE) + PRINT_IMMED_PREFIX (file); + else if (GET_CODE (x) == CONST || GET_CODE (x) == SYMBOL_REF + || GET_CODE (x) == LABEL_REF) + PRINT_OFFSET_PREFIX (file); + } + if (flag_pic) + output_pic_addr_const (file, x, code); + else + output_addr_const (file, x); + } +} + +/* Print a memory operand whose address is ADDR. */ + +void +print_operand_address (file, addr) + FILE *file; + register rtx addr; +{ + register rtx reg1, reg2, breg, ireg; + rtx offset; + + switch (GET_CODE (addr)) + { + case REG: + ADDR_BEG (file); + fprintf (file, "%se", RP); + fputs (hi_reg_name[REGNO (addr)], file); + ADDR_END (file); + break; + + case PLUS: + reg1 = 0; + reg2 = 0; + ireg = 0; + breg = 0; + offset = 0; + if (CONSTANT_ADDRESS_P (XEXP (addr, 0))) + { + offset = XEXP (addr, 0); + addr = XEXP (addr, 1); + } + else if (CONSTANT_ADDRESS_P (XEXP (addr, 1))) + { + offset = XEXP (addr, 1); + addr = XEXP (addr, 0); + } + if (GET_CODE (addr) != PLUS) ; + else if (GET_CODE (XEXP (addr, 0)) == MULT) + { + reg1 = XEXP (addr, 0); + addr = XEXP (addr, 1); + } + else if (GET_CODE (XEXP (addr, 1)) == MULT) + { + reg1 = XEXP (addr, 1); + addr = XEXP (addr, 0); + } + else if (GET_CODE (XEXP (addr, 0)) == REG) + { + reg1 = XEXP (addr, 0); + addr = XEXP (addr, 1); + } + else if (GET_CODE (XEXP (addr, 1)) == REG) + { + reg1 = XEXP (addr, 1); + addr = XEXP (addr, 0); + } + if (GET_CODE (addr) == REG || GET_CODE (addr) == MULT) + { + if (reg1 == 0) reg1 = addr; + else reg2 = addr; + addr = 0; + } + if (offset != 0) + { + if (addr != 0) abort (); + addr = offset; + } + if ((reg1 && GET_CODE (reg1) == MULT) + || (reg2 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2)))) + { + breg = reg2; + ireg = reg1; + } + else if (reg1 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1))) + { + breg = reg1; + ireg = reg2; + } + + if (ireg != 0 || breg != 0) + { + int scale = 1; + + if (addr != 0) + { + if (GET_CODE (addr) == LABEL_REF) + output_asm_label (addr); + else + { + if (flag_pic) + output_pic_addr_const (file, addr, 0); + else + output_addr_const (file, addr); + } + } + + if (ireg != 0 && GET_CODE (ireg) == MULT) + { + scale = INTVAL (XEXP (ireg, 1)); + ireg = XEXP (ireg, 0); + } + + /* The stack pointer can only appear as a base register, + never an index register, so exchange the regs if it is wrong. */ + + if (scale == 1 && ireg && REGNO (ireg) == STACK_POINTER_REGNUM) + { + rtx tmp; + + tmp = breg; + breg = ireg; + ireg = tmp; + } + + /* output breg+ireg*scale */ + PRINT_B_I_S (breg, ireg, scale, file); + break; + } + + case MULT: + { + int scale; + if (GET_CODE (XEXP (addr, 0)) == CONST_INT) + { + scale = INTVAL (XEXP (addr, 0)); + ireg = XEXP (addr, 1); + } + else + { + scale = INTVAL (XEXP (addr, 1)); + ireg = XEXP (addr, 0); + } + output_addr_const (file, const0_rtx); + PRINT_B_I_S ((rtx) 0, ireg, scale, file); + } + break; + + default: + if (GET_CODE (addr) == CONST_INT + && INTVAL (addr) < 0x8000 + && INTVAL (addr) >= -0x8000) + fprintf (file, "%d", INTVAL (addr)); + else + { + if (flag_pic) + output_pic_addr_const (file, addr, 0); + else + output_addr_const (file, addr); + } + } +} + +/* Set the cc_status for the results of an insn whose pattern is EXP. + On the 80386, we assume that only test and compare insns, as well + as SI, HI, & DI mode ADD, SUB, NEG, AND, IOR, XOR, ASHIFT, LSHIFT, + ASHIFTRT, and LSHIFTRT instructions set the condition codes usefully. + Also, we assume that jumps, moves and sCOND don't affect the condition + codes. All else clobbers the condition codes, by assumption. + + We assume that ALL integer add, minus, etc. instructions effect the + condition codes. This MUST be consistent with i386.md. + + We don't record any float test or compare - the redundant test & + compare check in final.c does not handle stack-like regs correctly. */ + +void +notice_update_cc (exp) + rtx exp; +{ + if (GET_CODE (exp) == SET) + { + /* Jumps do not alter the cc's. */ + if (SET_DEST (exp) == pc_rtx) + return; + /* Moving register or memory into a register: + it doesn't alter the cc's, but it might invalidate + the RTX's which we remember the cc's came from. + (Note that moving a constant 0 or 1 MAY set the cc's). */ + if (REG_P (SET_DEST (exp)) + && (REG_P (SET_SRC (exp)) || GET_CODE (SET_SRC (exp)) == MEM + || GET_RTX_CLASS (GET_CODE (SET_SRC (exp))) == '<')) + { + if (cc_status.value1 + && reg_overlap_mentioned_p (SET_DEST (exp), cc_status.value1)) + cc_status.value1 = 0; + if (cc_status.value2 + && reg_overlap_mentioned_p (SET_DEST (exp), cc_status.value2)) + cc_status.value2 = 0; + return; + } + /* Moving register into memory doesn't alter the cc's. + It may invalidate the RTX's which we remember the cc's came from. */ + if (GET_CODE (SET_DEST (exp)) == MEM + && (REG_P (SET_SRC (exp)) + || GET_RTX_CLASS (GET_CODE (SET_SRC (exp))) == '<')) + { + if (cc_status.value1 && GET_CODE (cc_status.value1) == MEM) + cc_status.value1 = 0; + if (cc_status.value2 && GET_CODE (cc_status.value2) == MEM) + cc_status.value2 = 0; + return; + } + /* Function calls clobber the cc's. */ + else if (GET_CODE (SET_SRC (exp)) == CALL) + { + CC_STATUS_INIT; + return; + } + /* Tests and compares set the cc's in predictable ways. */ + else if (SET_DEST (exp) == cc0_rtx) + { + CC_STATUS_INIT; + cc_status.value1 = SET_SRC (exp); + return; + } + /* Certain instructions effect the condition codes. */ + else if (GET_MODE (SET_SRC (exp)) == SImode + || GET_MODE (SET_SRC (exp)) == HImode + || GET_MODE (SET_SRC (exp)) == QImode) + switch (GET_CODE (SET_SRC (exp))) + { + case ASHIFTRT: case LSHIFTRT: + case ASHIFT: case LSHIFT: + /* Shifts on the 386 don't set the condition codes if the + shift count is zero. */ + if (GET_CODE (XEXP (SET_SRC (exp), 1)) != CONST_INT) + { + CC_STATUS_INIT; + break; + } + /* We assume that the CONST_INT is non-zero (this rtx would + have been deleted if it were zero. */ + + case PLUS: case MINUS: case NEG: + case AND: case IOR: case XOR: + cc_status.flags = CC_NO_OVERFLOW; + cc_status.value1 = SET_SRC (exp); + cc_status.value2 = SET_DEST (exp); + break; + + default: + CC_STATUS_INIT; + } + else + { + CC_STATUS_INIT; + } + } + else if (GET_CODE (exp) == PARALLEL + && GET_CODE (XVECEXP (exp, 0, 0)) == SET) + { + if (SET_DEST (XVECEXP (exp, 0, 0)) == pc_rtx) + return; + if (SET_DEST (XVECEXP (exp, 0, 0)) == cc0_rtx) + { + CC_STATUS_INIT; + if (stack_regs_mentioned_p (SET_SRC (XVECEXP (exp, 0, 0)))) + cc_status.flags |= CC_IN_80387; + else + cc_status.value1 = SET_SRC (XVECEXP (exp, 0, 0)); + return; + } + CC_STATUS_INIT; + } + else + { + CC_STATUS_INIT; + } +} + +/* Split one or more DImode RTL references into pairs of SImode + references. The RTL can be REG, offsettable MEM, integer constant, or + CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to + split and "num" is its length. lo_half and hi_half are output arrays + that parallel "operands". */ + +void +split_di (operands, num, lo_half, hi_half) + rtx operands[]; + int num; + rtx lo_half[], hi_half[]; +{ + while (num--) + { + if (GET_CODE (operands[num]) == REG) + { + lo_half[num] = gen_rtx (REG, SImode, REGNO (operands[num])); + hi_half[num] = gen_rtx (REG, SImode, REGNO (operands[num]) + 1); + } + else if (CONSTANT_P (operands[num])) + { + split_double (operands[num], &lo_half[num], &hi_half[num]); + } + else if (offsettable_memref_p (operands[num])) + { + lo_half[num] = operands[num]; + hi_half[num] = adj_offsettable_operand (operands[num], 4); + } + else + abort(); + } +} + +/* Return 1 if this is a valid binary operation on a 387. + OP is the expression matched, and MODE is its mode. */ + +int +binary_387_op (op, mode) + register rtx op; + enum machine_mode mode; +{ + if (mode != VOIDmode && mode != GET_MODE (op)) + return 0; + + switch (GET_CODE (op)) + { + case PLUS: + case MINUS: + case MULT: + case DIV: + return GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT; + + default: + return 0; + } +} + +/* Return 1 if this is a valid conversion operation on a 387. + OP is the expression matched, and MODE is its mode. */ + +int +convert_387_op (op, mode) + register rtx op; + enum machine_mode mode; +{ + if (mode != VOIDmode && mode != GET_MODE (op)) + return 0; + + switch (GET_CODE (op)) + { + case FLOAT: + return GET_MODE (XEXP (op, 0)) == SImode; + + case FLOAT_EXTEND: + return mode == DFmode && GET_MODE (XEXP (op, 0)) == SFmode; + + default: + return 0; + } +} + +/* Return 1 if this is a valid shift or rotate operation on a 386. + OP is the expression matched, and MODE is its mode. */ + +int +shift_op (op, mode) + register rtx op; + enum machine_mode mode; +{ + rtx operand = XEXP (op, 0); + + if (mode != VOIDmode && mode != GET_MODE (op)) + return 0; + + if (GET_MODE (operand) != GET_MODE (op) + || GET_MODE_CLASS (GET_MODE (op)) != MODE_INT) + return 0; + + return (GET_CODE (op) == ASHIFT + || GET_CODE (op) == ASHIFTRT + || GET_CODE (op) == LSHIFTRT + || GET_CODE (op) == ROTATE + || GET_CODE (op) == ROTATERT); +} + +/* Return 1 if OP is COMPARE rtx with mode VOIDmode. + MODE is not used. */ + +int +VOIDmode_compare_op (op, mode) + register rtx op; + enum machine_mode mode; +{ + return GET_CODE (op) == COMPARE && GET_MODE (op) == VOIDmode; +} + +/* Output code to perform a 387 binary operation in INSN, one of PLUS, + MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3] + is the expression of the binary operation. The output may either be + emitted here, or returned to the caller, like all output_* functions. + + There is no guarantee that the operands are the same mode, as they + might be within FLOAT or FLOAT_EXTEND expressions. */ + +char * +output_387_binary_op (insn, operands) + rtx insn; + rtx *operands; +{ + rtx temp; + char *base_op; + static char buf[100]; + + switch (GET_CODE (operands[3])) + { + case PLUS: + if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT + || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT) + base_op = "fiadd"; + else + base_op = "fadd"; + break; + + case MINUS: + if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT + || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT) + base_op = "fisub"; + else + base_op = "fsub"; + break; + + case MULT: + if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT + || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT) + base_op = "fimul"; + else + base_op = "fmul"; + break; + + case DIV: + if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT + || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT) + base_op = "fidiv"; + else + base_op = "fdiv"; + break; + + default: + abort (); + } + + strcpy (buf, base_op); + + switch (GET_CODE (operands[3])) + { + case MULT: + case PLUS: + if (REG_P (operands[2]) && REGNO (operands[0]) == REGNO (operands[2])) + { + temp = operands[2]; + operands[2] = operands[1]; + operands[1] = temp; + } + + if (GET_CODE (operands[2]) == MEM) + return strcat (buf, AS1 (%z2,%2)); + + if (NON_STACK_REG_P (operands[1])) + { + output_op_from_reg (operands[1], strcat (buf, AS1 (%z0,%1))); + RET; + } + else if (NON_STACK_REG_P (operands[2])) + { + output_op_from_reg (operands[2], strcat (buf, AS1 (%z0,%1))); + RET; + } + + if (find_regno_note (insn, REG_DEAD, REGNO (operands[2]))) + return strcat (buf, AS2 (p,%2,%0)); + + if (STACK_TOP_P (operands[0])) + return strcat (buf, AS2 (,%y2,%0)); + else + return strcat (buf, AS2 (,%2,%0)); + + case MINUS: + case DIV: + if (GET_CODE (operands[1]) == MEM) + return strcat (buf, AS1 (r%z1,%1)); + + if (GET_CODE (operands[2]) == MEM) + return strcat (buf, AS1 (%z2,%2)); + + if (NON_STACK_REG_P (operands[1])) + { + output_op_from_reg (operands[1], strcat (buf, AS1 (r%z0,%1))); + RET; + } + else if (NON_STACK_REG_P (operands[2])) + { + output_op_from_reg (operands[2], strcat (buf, AS1 (%z0,%1))); + RET; + } + + if (! STACK_REG_P (operands[1]) || ! STACK_REG_P (operands[2])) + abort (); + + if (find_regno_note (insn, REG_DEAD, REGNO (operands[2]))) + return strcat (buf, AS2 (rp,%2,%0)); + + if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) + return strcat (buf, AS2 (p,%1,%0)); + + if (STACK_TOP_P (operands[0])) + { + if (STACK_TOP_P (operands[1])) + return strcat (buf, AS2 (,%y2,%0)); + else + return strcat (buf, AS2 (r,%y1,%0)); + } + else if (STACK_TOP_P (operands[1])) + return strcat (buf, AS2 (,%1,%0)); + else + return strcat (buf, AS2 (r,%2,%0)); + + default: + abort (); + } +} + +/* Output code for INSN to convert a float to a signed int. OPERANDS + are the insn operands. The output may be SFmode or DFmode and the + input operand may be SImode or DImode. As a special case, make sure + that the 387 stack top dies if the output mode is DImode, because the + hardware requires this. */ + +char * +output_fix_trunc (insn, operands) + rtx insn; + rtx *operands; +{ + int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0; + rtx xops[2]; + + if (! STACK_TOP_P (operands[1]) || + (GET_MODE (operands[0]) == DImode && ! stack_top_dies)) + abort (); + + xops[0] = GEN_INT (12); + xops[1] = operands[4]; + + output_asm_insn (AS1 (fnstc%W2,%2), operands); + output_asm_insn (AS2 (mov%L2,%2,%4), operands); + output_asm_insn (AS2 (mov%B1,%0,%h1), xops); + output_asm_insn (AS2 (mov%L4,%4,%3), operands); + output_asm_insn (AS1 (fldc%W3,%3), operands); + + if (NON_STACK_REG_P (operands[0])) + output_to_reg (operands[0], stack_top_dies); + else if (GET_CODE (operands[0]) == MEM) + { + if (stack_top_dies) + output_asm_insn (AS1 (fistp%z0,%0), operands); + else + output_asm_insn (AS1 (fist%z0,%0), operands); + } + else + abort (); + + return AS1 (fldc%W2,%2); +} + +/* Output code for INSN to compare OPERANDS. The two operands might + not have the same mode: one might be within a FLOAT or FLOAT_EXTEND + expression. If the compare is in mode CCFPEQmode, use an opcode that + will not fault if a qNaN is present. */ + +char * +output_float_compare (insn, operands) + rtx insn; + rtx *operands; +{ + int stack_top_dies; + rtx body = XVECEXP (PATTERN (insn), 0, 0); + int unordered_compare = GET_MODE (SET_SRC (body)) == CCFPEQmode; + + if (! STACK_TOP_P (operands[0])) + abort (); + + stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0; + + if (STACK_REG_P (operands[1]) + && stack_top_dies + && find_regno_note (insn, REG_DEAD, REGNO (operands[1])) + && REGNO (operands[1]) != FIRST_STACK_REG) + { + /* If both the top of the 387 stack dies, and the other operand + is also a stack register that dies, then this must be a + `fcompp' float compare */ + + if (unordered_compare) + output_asm_insn ("fucompp", operands); + else + output_asm_insn ("fcompp", operands); + } + else + { + static char buf[100]; + + /* Decide if this is the integer or float compare opcode, or the + unordered float compare. */ + + if (unordered_compare) + strcpy (buf, "fucom"); + else if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_FLOAT) + strcpy (buf, "fcom"); + else + strcpy (buf, "ficom"); + + /* Modify the opcode if the 387 stack is to be popped. */ + + if (stack_top_dies) + strcat (buf, "p"); + + if (NON_STACK_REG_P (operands[1])) + output_op_from_reg (operands[1], strcat (buf, AS1 (%z0,%1))); + else + output_asm_insn (strcat (buf, AS1 (%z1,%y1)), operands); + } + + /* Now retrieve the condition code. */ + + return output_fp_cc0_set (insn); +} + +/* Output opcodes to transfer the results of FP compare or test INSN + from the FPU to the CPU flags. If TARGET_IEEE_FP, ensure that if the + result of the compare or test is unordered, no comparison operator + succeeds except NE. Return an output template, if any. */ + +char * +output_fp_cc0_set (insn) + rtx insn; +{ + rtx xops[3]; + rtx unordered_label; + rtx next; + enum rtx_code code; + + xops[0] = gen_rtx (REG, HImode, 0); + output_asm_insn (AS1 (fnsts%W0,%0), xops); + + if (! TARGET_IEEE_FP) + return "sahf"; + + next = next_cc0_user (insn); + if (next == NULL_RTX) + abort (); + + if (GET_CODE (next) == JUMP_INSN + && GET_CODE (PATTERN (next)) == SET + && SET_DEST (PATTERN (next)) == pc_rtx + && GET_CODE (SET_SRC (PATTERN (next))) == IF_THEN_ELSE) + { + code = GET_CODE (XEXP (SET_SRC (PATTERN (next)), 0)); + } + else if (GET_CODE (PATTERN (next)) == SET) + { + code = GET_CODE (SET_SRC (PATTERN (next))); + } + else + abort (); + + xops[0] = gen_rtx (REG, QImode, 0); + + switch (code) + { + case GT: + xops[1] = GEN_INT (0x45); + output_asm_insn (AS2 (and%B0,%1,%h0), xops); + /* je label */ + break; + + case LT: + xops[1] = GEN_INT (0x45); + xops[2] = GEN_INT (0x01); + output_asm_insn (AS2 (and%B0,%1,%h0), xops); + output_asm_insn (AS2 (cmp%B0,%2,%h0), xops); + /* je label */ + break; + + case GE: + xops[1] = GEN_INT (0x05); + output_asm_insn (AS2 (and%B0,%1,%h0), xops); + /* je label */ + break; + + case LE: + xops[1] = GEN_INT (0x45); + xops[2] = GEN_INT (0x40); + output_asm_insn (AS2 (and%B0,%1,%h0), xops); + output_asm_insn (AS1 (dec%B0,%h0), xops); + output_asm_insn (AS2 (cmp%B0,%2,%h0), xops); + /* jb label */ + break; + + case EQ: + xops[1] = GEN_INT (0x45); + xops[2] = GEN_INT (0x40); + output_asm_insn (AS2 (and%B0,%1,%h0), xops); + output_asm_insn (AS2 (cmp%B0,%2,%h0), xops); + /* je label */ + break; + + case NE: + xops[1] = GEN_INT (0x44); + xops[2] = GEN_INT (0x40); + output_asm_insn (AS2 (and%B0,%1,%h0), xops); + output_asm_insn (AS2 (xor%B0,%2,%h0), xops); + /* jne label */ + break; + + case GTU: + case LTU: + case GEU: + case LEU: + default: + abort (); + } + RET; +} + +#define MAX_386_STACK_LOCALS 2 + +static rtx i386_stack_locals[(int) MAX_MACHINE_MODE][MAX_386_STACK_LOCALS]; + +/* Clear stack slot assignments remembered from previous functions. + This is called from INIT_EXPANDERS once before RTL is emitted for each + function. */ + +void +clear_386_stack_locals () +{ + enum machine_mode mode; + int n; + + for (mode = VOIDmode; (int) mode < (int) MAX_MACHINE_MODE; + mode = (enum machine_mode) ((int) mode + 1)) + for (n = 0; n < MAX_386_STACK_LOCALS; n++) + i386_stack_locals[(int) mode][n] = NULL_RTX; +} + +/* Return a MEM corresponding to a stack slot with mode MODE. + Allocate a new slot if necessary. + + The RTL for a function can have several slots available: N is + which slot to use. */ + +rtx +assign_386_stack_local (mode, n) + enum machine_mode mode; + int n; +{ + if (n < 0 || n >= MAX_386_STACK_LOCALS) + abort (); + + if (i386_stack_locals[(int) mode][n] == NULL_RTX) + i386_stack_locals[(int) mode][n] + = assign_stack_local (mode, GET_MODE_SIZE (mode), 0); + + return i386_stack_locals[(int) mode][n]; +} diff --git a/gnu/usr.bin/gcc2/i386/bsd.h b/gnu/usr.bin/gcc2/i386/bsd.h new file mode 100644 index 00000000000..ad7a04448fa --- /dev/null +++ b/gnu/usr.bin/gcc2/i386/bsd.h @@ -0,0 +1,135 @@ +/* Definitions for BSD assembler syntax for Intel 386 + (actually AT&T syntax for insns and operands, + adapted to BSD conventions for symbol names and debugging.) + Copyright (C) 1988 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + +/* Include common aspects of all 386 Unix assemblers. */ +#include "i386/unix.h" + +/* Enable #pragma pack for building NetBSD and 386BSD kernels. */ +#define HANDLE_SYSV_PRAGMA + +/* Use the Sequent Symmetry assembler syntax. */ + +#define TARGET_VERSION fprintf (stderr, " (80386, BSD syntax)"); + +/* Define the syntax of pseudo-ops, labels and comments. */ + +/* Prefix for internally generated assembler labels. If we aren't using + underscores, we are using prefix `.'s to identify labels that should + be ignored, as in `i386/gas.h' --karl@cs.umb.edu */ +#ifdef NO_UNDERSCORES +#define LPREFIX ".L" +#else +#define LPREFIX "L" +#endif /* not NO_UNDERSCORES */ + +/* Assembler pseudos to introduce constants of various size. */ + +#define ASM_BYTE_OP "\t.byte" +#define ASM_SHORT "\t.word" +#define ASM_LONG "\t.long" +#define ASM_DOUBLE "\t.double" + +/* Output at beginning of assembler file. + ??? I am skeptical of this -- RMS. */ + +#define ASM_FILE_START(FILE) \ + fprintf (FILE, "\t.file\t\"%s\"\n", dump_base_name); + +/* This was suggested, but it shouldn't be right for DBX output. -- RMS + #define ASM_OUTPUT_SOURCE_FILENAME(FILE, NAME) */ + + +/* Define the syntax of labels and symbol definitions/declarations. */ + +/* This is how to output an assembler line + that says to advance the location counter by SIZE bytes. */ + +#define ASM_OUTPUT_SKIP(FILE,SIZE) \ + fprintf (FILE, "\t.space %u\n", (SIZE)) + +/* Define the syntax of labels and symbol definitions/declarations. */ + +/* This says how to output an assembler line + to define a global common symbol. */ + +#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ +( fputs (".comm ", (FILE)), \ + assemble_name ((FILE), (NAME)), \ + fprintf ((FILE), ",%u\n", (ROUNDED))) + +/* This says how to output an assembler line + to define a local common symbol. */ + +#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ +( fputs (".lcomm ", (FILE)), \ + assemble_name ((FILE), (NAME)), \ + fprintf ((FILE), ",%u\n", (ROUNDED))) + +/* This is how to output an assembler line + that says to advance the location counter + to a multiple of 2**LOG bytes. */ + +#define ASM_OUTPUT_ALIGN(FILE,LOG) \ + if ((LOG)!=0) fprintf ((FILE), "\t.align %d\n", (LOG)) + +/* This is how to store into the string BUF + the symbol_ref name of an internal numbered label where + PREFIX is the class of label and NUM is the number within the class. + This is suitable for output with `assemble_name'. */ + +#ifdef NO_UNDERSCORES +#define ASM_GENERATE_INTERNAL_LABEL(BUF,PREFIX,NUMBER) \ + sprintf ((BUF), "*.%s%d", (PREFIX), (NUMBER)) +#else +#define ASM_GENERATE_INTERNAL_LABEL(BUF,PREFIX,NUMBER) \ + sprintf ((BUF), "*%s%d", (PREFIX), (NUMBER)) +#endif + +/* This is how to output an internal numbered label where + PREFIX is the class of label and NUM is the number within the class. */ + +#ifdef NO_UNDERSCORES +#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \ + fprintf (FILE, ".%s%d:\n", PREFIX, NUM) +#else +#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \ + fprintf (FILE, "%s%d:\n", PREFIX, NUM) +#endif + +/* This is how to output a reference to a user-level label named NAME. */ + +#ifdef NO_UNDERSCORES +#define ASM_OUTPUT_LABELREF(FILE,NAME) fprintf (FILE, "%s", NAME) +#else +#define ASM_OUTPUT_LABELREF(FILE,NAME) fprintf (FILE, "_%s", NAME) +#endif /* not NO_UNDERSCORES */ + +/* Sequent has some changes in the format of DBX symbols. */ +#define DBX_NO_XREFS 1 + +/* Don't split DBX symbols into continuations. */ +#define DBX_CONTIN_LENGTH 0 + +/* This is how to output an assembler line defining a `double' constant. */ + +#undef ASM_OUTPUT_DOUBLE +#define ASM_OUTPUT_DOUBLE(FILE,VALUE) \ + fprintf (FILE, "\t.double 0d%.20e\n", (VALUE)) diff --git a/gnu/usr.bin/gcc2/i386/config.h b/gnu/usr.bin/gcc2/i386/config.h new file mode 100644 index 00000000000..eb90681006f --- /dev/null +++ b/gnu/usr.bin/gcc2/i386/config.h @@ -0,0 +1,48 @@ +/* Configuration for GNU C-compiler for Intel 80386. + Copyright (C) 1988 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + +#ifndef i386 +#define i386 +#endif + +/* #defines that need visibility everywhere. */ +#define FALSE 0 +#define TRUE 1 + +/* This describes the machine the compiler is hosted on. */ +#define HOST_BITS_PER_CHAR 8 +#define HOST_BITS_PER_SHORT 16 +#define HOST_BITS_PER_INT 32 +#define HOST_BITS_PER_LONG 32 +#define HOST_BITS_PER_LONGLONG 64 + +/* Arguments to use with `exit'. */ +#define SUCCESS_EXIT_CODE 0 +#define FATAL_EXIT_CODE 33 + +/* If compiled with GNU C, use the built-in alloca */ +#ifdef __GNUC__ +#undef alloca +#define alloca __builtin_alloca +#endif + +/* target machine dependencies. + tm.h is a symbolic link to the actual target specific file. */ + +#include "tm.h" diff --git a/gnu/usr.bin/gcc2/i386/gas.h b/gnu/usr.bin/gcc2/i386/gas.h new file mode 100644 index 00000000000..4821a895c5d --- /dev/null +++ b/gnu/usr.bin/gcc2/i386/gas.h @@ -0,0 +1,158 @@ +/* Definitions for Intel 386 running system V with gnu tools + Copyright (C) 1988 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + +/* Note that i386/seq-gas.h is a GAS configuration that does not use this + file. */ + +#include "i386/i386.h" + +#ifndef YES_UNDERSCORES +/* Define this now, because i386/bsd.h tests it. */ +#define NO_UNDERSCORES +#endif + +/* Use the bsd assembler syntax. */ +/* we need to do this because gas is really a bsd style assembler, + * and so doesn't work well this these att-isms: + * + * ASM_OUTPUT_SKIP is .set .,.+N, which isn't implemented in gas + * ASM_OUTPUT_LOCAL is done with .set .,.+N, but that can't be + * used to define bss static space + * + * Next is the question of whether to uses underscores. RMS didn't + * like this idea at first, but since it is now obvious that we + * need this separate tm file for use with gas, at least to get + * dbx debugging info, I think we should also switch to underscores. + * We can keep i386v for real att style output, and the few + * people who want both form will have to compile twice. + */ + +#include "i386/bsd.h" + +/* these come from i386/bsd.h, but are specific to sequent */ +#undef DBX_NO_XREFS +#undef DBX_CONTIN_LENGTH + +/* Ask for COFF symbols. */ + +#define SDB_DEBUGGING_INFO + +/* Specify predefined symbols in preprocessor. */ + +#define CPP_PREDEFINES "-Dunix -Di386" +#define CPP_SPEC "%{posix:-D_POSIX_SOURCE}" + +/* Allow #sccs in preprocessor. */ + +#define SCCS_DIRECTIVE + +/* Output #ident as a .ident. */ + +#define ASM_OUTPUT_IDENT(FILE, NAME) fprintf (FILE, "\t.ident \"%s\"\n", NAME); + +/* Implicit library calls should use memcpy, not bcopy, etc. */ + +#define TARGET_MEM_FUNCTIONS + +#if 0 /* People say gas uses the log as the arg to .align. */ +/* When using gas, .align N aligns to an N-byte boundary. */ + +#undef ASM_OUTPUT_ALIGN +#define ASM_OUTPUT_ALIGN(FILE,LOG) \ + if ((LOG)!=0) fprintf ((FILE), "\t.align %d\n", 1<<(LOG)) +#endif + +/* Align labels, etc. at 4-byte boundaries. + For the 486, align to 16-byte boundary for sake of cache. */ + +#undef ASM_OUTPUT_ALIGN_CODE +#define ASM_OUTPUT_ALIGN_CODE(FILE) \ + fprintf ((FILE), "\t.align %d,0x90\n", \ + TARGET_486 ? 4 : 2); /* Use log of 16 or log of 4 as arg. */ + +/* Align start of loop at 4-byte boundary. */ + +#undef ASM_OUTPUT_LOOP_ALIGN +#define ASM_OUTPUT_LOOP_ALIGN(FILE) \ + fprintf ((FILE), "\t.align 2,0x90\n"); /* Use log of 4 as arg. */ + +#undef ASM_FILE_START +#define ASM_FILE_START(FILE) \ + fprintf (FILE, "\t.file\t\"%s\"\n", dump_base_name); + +/* A C statement or statements which output an assembler instruction + opcode to the stdio stream STREAM. The macro-operand PTR is a + variable of type `char *' which points to the opcode name in its + "internal" form--the form that is written in the machine description. + + GAS version 1.38.1 doesn't understand the `repz' opcode mnemonic. + So use `repe' instead. */ + +#define ASM_OUTPUT_OPCODE(STREAM, PTR) \ +{ \ + if ((PTR)[0] == 'r' \ + && (PTR)[1] == 'e' \ + && (PTR)[2] == 'p') \ + { \ + if ((PTR)[3] == 'z') \ + { \ + fprintf (STREAM, "repe"); \ + (PTR) += 4; \ + } \ + else if ((PTR)[3] == 'n' && (PTR)[4] == 'z') \ + { \ + fprintf (STREAM, "repne"); \ + (PTR) += 5; \ + } \ + } \ +} + +/* Define macro used to output shift-double opcodes when the shift + count is in %cl. Some assemblers require %cl as an argument; + some don't. + + GAS requires the %cl argument, so override i386/unix.h. */ + +#undef AS3_SHIFT_DOUBLE +#define AS3_SHIFT_DOUBLE(a,b,c,d) AS3 (a,b,c,d) + +/* Print opcodes the way that GAS expects them. */ +#define GAS_MNEMONICS 1 + +#ifdef NO_UNDERSCORES /* If user-symbols don't have underscores, + then it must take more than `L' to identify + a label that should be ignored. */ + +/* This is how to store into the string BUF + the symbol_ref name of an internal numbered label where + PREFIX is the class of label and NUM is the number within the class. + This is suitable for output with `assemble_name'. */ + +#undef ASM_GENERATE_INTERNAL_LABEL +#define ASM_GENERATE_INTERNAL_LABEL(BUF,PREFIX,NUMBER) \ + sprintf ((BUF), ".%s%d", (PREFIX), (NUMBER)) + +/* This is how to output an internal numbered label where + PREFIX is the class of label and NUM is the number within the class. */ + +#undef ASM_OUTPUT_INTERNAL_LABEL +#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \ + fprintf (FILE, ".%s%d:\n", PREFIX, NUM) + +#endif /* NO_UNDERSCORES */ diff --git a/gnu/usr.bin/gcc2/i386/gstabs.h b/gnu/usr.bin/gcc2/i386/gstabs.h new file mode 100644 index 00000000000..5f0ae348f15 --- /dev/null +++ b/gnu/usr.bin/gcc2/i386/gstabs.h @@ -0,0 +1,9 @@ +#include "i386/gas.h" + +/* We do not want to output SDB debugging information. */ + +#undef SDB_DEBUGGING_INFO + +/* We want to output DBX debugging information. */ + +#define DBX_DEBUGGING_INFO diff --git a/gnu/usr.bin/gcc2/i386/i386.h b/gnu/usr.bin/gcc2/i386/i386.h new file mode 100644 index 00000000000..fa8f0b5b26b --- /dev/null +++ b/gnu/usr.bin/gcc2/i386/i386.h @@ -0,0 +1,1591 @@ +/* Definitions of target machine for GNU compiler for Intel 80386. + Copyright (C) 1988, 1992 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + + +/* The purpose of this file is to define the characteristics of the i386, + independent of assembler syntax or operating system. + + Three other files build on this one to describe a specific assembler syntax: + bsd386.h, att386.h, and sun386.h. + + The actual tm.h file for a particular system should include + this file, and then the file for the appropriate assembler syntax. + + Many macros that specify assembler syntax are omitted entirely from + this file because they really belong in the files for particular + assemblers. These include AS1, AS2, AS3, RP, IP, LPREFIX, L_SIZE, + PUT_OP_SIZE, USE_STAR, ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, + PRINT_B_I_S, and many that start with ASM_ or end in ASM_OP. */ + +/* Names to predefine in the preprocessor for this target machine. */ + +#define I386 1 + +/* Stubs for half-pic support if not OSF/1 reference platform. */ + +#ifndef HALF_PIC_P +#define HALF_PIC_P() 0 +#define HALF_PIC_NUMBER_PTRS 0 +#define HALF_PIC_NUMBER_REFS 0 +#define HALF_PIC_ENCODE(DECL) +#define HALF_PIC_DECLARE(NAME) +#define HALF_PIC_INIT() error ("half-pic init called on systems that don't support it.") +#define HALF_PIC_ADDRESS_P(X) 0 +#define HALF_PIC_PTR(X) X +#define HALF_PIC_FINISH(STREAM) +#endif + +/* Run-time compilation parameters selecting different hardware subsets. */ + +extern int target_flags; + +/* Macros used in the machine description to test the flags. */ + +/* configure can arrage to make this 2, to force a 486. */ +#ifndef TARGET_CPU_DEFAULT +#define TARGET_CPU_DEFAULT 0 +#endif + +/* Compile 80387 insns for floating point (not library calls). */ +#define TARGET_80387 (target_flags & 1) +/* Compile code for an i486. */ +#define TARGET_486 (target_flags & 2) +/* Compile using ret insn that pops args. + This will not work unless you use prototypes at least + for all functions that can take varying numbers of args. */ +#define TARGET_RTD (target_flags & 8) +/* Compile passing first two args in regs 0 and 1. + This exists only to test compiler features that will + be needed for RISC chips. It is not usable + and is not intended to be usable on this cpu. */ +#define TARGET_REGPARM (target_flags & 020) + +/* Put uninitialized locals into bss, not data. + Meaningful only on svr3. */ +#define TARGET_SVR3_SHLIB (target_flags & 040) + +/* Use IEEE floating point comparisons. These handle correctly the cases + where the result of a comparison is unordered. Normally SIGFPE is + generated in such cases, in which case this isn't needed. */ +#define TARGET_IEEE_FP (target_flags & 0100) + +/* Functions that return a floating point value may return that value + in the 387 FPU or in 386 integer registers. If set, this flag causes + the 387 to be used, which is compatible with most calling conventions. */ +#define TARGET_FLOAT_RETURNS_IN_80387 (target_flags & 0200) + +/* Macro to define tables used to set the flags. + This is a list in braces of pairs in braces, + each pair being { "NAME", VALUE } + where VALUE is the bits to set or minus the bits to clear. + An empty string NAME is used to identify the default VALUE. */ + +#define TARGET_SWITCHES \ + { { "80387", 1}, \ + { "no-80387", -1}, \ + { "soft-float", -1}, \ + { "no-soft-float", 1}, \ + { "486", 2}, \ + { "no-486", -2}, \ + { "386", -2}, \ + { "rtd", 8}, \ + { "no-rtd", -8}, \ + { "regparm", 020}, \ + { "no-regparm", -020}, \ + { "svr3-shlib", 040}, \ + { "no-svr3-shlib", -040}, \ + { "ieee-fp", 0100}, \ + { "no-ieee-fp", -0100}, \ + { "fp-ret-in-387", 0200}, \ + { "no-fp-ret-in-387", -0200}, \ + SUBTARGET_SWITCHES \ + { "", TARGET_DEFAULT | TARGET_CPU_DEFAULT}} + +/* This is meant to be redefined in the host dependent files */ +#define SUBTARGET_SWITCHES + + +/* target machine storage layout */ + +/* Define this if most significant byte of a word is the lowest numbered. */ +/* That is true on the 80386. */ + +#define BITS_BIG_ENDIAN 0 + +/* Define this if most significant byte of a word is the lowest numbered. */ +/* That is not true on the 80386. */ +#define BYTES_BIG_ENDIAN 0 + +/* Define this if most significant word of a multiword number is the lowest + numbered. */ +/* Not true for 80386 */ +#define WORDS_BIG_ENDIAN 0 + +/* number of bits in an addressable storage unit */ +#define BITS_PER_UNIT 8 + +/* Width in bits of a "word", which is the contents of a machine register. + Note that this is not necessarily the width of data type `int'; + if using 16-bit ints on a 80386, this would still be 32. + But on a machine with 16-bit registers, this would be 16. */ +#define BITS_PER_WORD 32 + +/* Width of a word, in units (bytes). */ +#define UNITS_PER_WORD 4 + +/* Width in bits of a pointer. + See also the macro `Pmode' defined below. */ +#define POINTER_SIZE 32 + +/* Allocation boundary (in *bits*) for storing arguments in argument list. */ +#define PARM_BOUNDARY 32 + +/* Boundary (in *bits*) on which stack pointer should be aligned. */ +#define STACK_BOUNDARY 32 + +/* Allocation boundary (in *bits*) for the code of a function. + For i486, we get better performance by aligning to a cache + line (i.e. 16 byte) boundary. */ +#define FUNCTION_BOUNDARY (TARGET_486 ? 128 : 32) + +/* Alignment of field after `int : 0' in a structure. */ + +#define EMPTY_FIELD_BOUNDARY 32 + +/* Minimum size in bits of the largest boundary to which any + and all fundamental data types supported by the hardware + might need to be aligned. No data type wants to be aligned + rounder than this. The i386 supports 64-bit floating point + quantities, but these can be aligned on any 32-bit boundary. */ +#define BIGGEST_ALIGNMENT 32 + +/* Set this non-zero if move instructions will actually fail to work + when given unaligned data. */ +#define STRICT_ALIGNMENT 0 + +/* If bit field type is int, don't let it cross an int, + and give entire struct the alignment of an int. */ +/* Required on the 386 since it doesn't have bitfield insns. */ +#define PCC_BITFIELD_TYPE_MATTERS 1 + +/* Align loop starts for optimal branching. */ +#define ASM_OUTPUT_LOOP_ALIGN(FILE) \ + ASM_OUTPUT_ALIGN (FILE, 2) + +/* This is how to align an instruction for optimal branching. + On i486 we'll get better performance by aligning on a + cache line (i.e. 16 byte) boundary. */ +#define ASM_OUTPUT_ALIGN_CODE(FILE) \ + ASM_OUTPUT_ALIGN ((FILE), (TARGET_486 ? 4 : 2)) + +/* Standard register usage. */ + +/* This processor has special stack-like registers. See reg-stack.c + for details. */ + +#define STACK_REGS + +/* Number of actual hardware registers. + The hardware registers are assigned numbers for the compiler + from 0 to just below FIRST_PSEUDO_REGISTER. + All registers that the compiler knows about must be given numbers, + even those that are not normally considered general registers. + + In the 80386 we give the 8 general purpose registers the numbers 0-7. + We number the floating point registers 8-15. + Note that registers 0-7 can be accessed as a short or int, + while only 0-3 may be used with byte `mov' instructions. + + Reg 16 does not correspond to any hardware register, but instead + appears in the RTL as an argument pointer prior to reload, and is + eliminated during reloading in favor of either the stack or frame + pointer. */ + +#define FIRST_PSEUDO_REGISTER 17 + +/* 1 for registers that have pervasive standard uses + and are not available for the register allocator. + On the 80386, the stack pointer is such, as is the arg pointer. */ +#define FIXED_REGISTERS \ +/*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7,arg*/ \ +{ 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1 } + +/* 1 for registers not available across function calls. + These must include the FIXED_REGISTERS and also any + registers that can be used without being saved. + The latter must include the registers where values are returned + and the register where structure-value addresses are passed. + Aside from that, you can include as many other registers as you like. */ + +#define CALL_USED_REGISTERS \ +/*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7,arg*/ \ +{ 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 } + +/* Macro to conditionally modify fixed_regs/call_used_regs. */ +#define CONDITIONAL_REGISTER_USAGE \ + { \ + if (flag_pic) \ + { \ + fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ + call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ + } \ + if (! TARGET_80387 && ! TARGET_FLOAT_RETURNS_IN_80387) \ + { \ + int i; \ + HARD_REG_SET x; \ + COPY_HARD_REG_SET (x, reg_class_contents[(int)FLOAT_REGS]); \ + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ ) \ + if (TEST_HARD_REG_BIT (x, i)) \ + fixed_regs[i] = call_used_regs[i] = 1; \ + } \ + } + +/* Return number of consecutive hard regs needed starting at reg REGNO + to hold something of mode MODE. + This is ordinarily the length in words of a value of mode MODE + but can be less for certain modes in special long registers. + + Actually there are no two word move instructions for consecutive + registers. And only registers 0-3 may have mov byte instructions + applied to them. + */ + +#define HARD_REGNO_NREGS(REGNO, MODE) \ + (FP_REGNO_P (REGNO) ? 1 \ + : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) + +/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. + On the 80386, the first 4 cpu registers can hold any mode + while the floating point registers may hold only floating point. + Make it clear that the fp regs could not hold a 16-byte float. */ + +/* The casts to int placate a compiler on a microvax, + for cross-compiler testing. */ + +#define HARD_REGNO_MODE_OK(REGNO, MODE) \ + ((REGNO) < 2 ? 1 \ + : (REGNO) < 4 ? 1 \ + : FP_REGNO_P ((REGNO)) \ + ? (((int) GET_MODE_CLASS (MODE) == (int) MODE_FLOAT \ + || (int) GET_MODE_CLASS (MODE) == (int) MODE_COMPLEX_FLOAT) \ + && GET_MODE_UNIT_SIZE (MODE) <= 12) \ + : (int) (MODE) != (int) QImode) + +/* Value is 1 if it is a good idea to tie two pseudo registers + when one has mode MODE1 and one has mode MODE2. + If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, + for any hard reg, then this must be 0 for correct output. */ + +#define MODES_TIEABLE_P(MODE1, MODE2) ((MODE1) == (MODE2)) + +/* A C expression returning the cost of moving data from a register of class + CLASS1 to one of CLASS2. + + On the i386, copying between floating-point and fixed-point + registers is expensive. */ + +#define REGISTER_MOVE_COST(CLASS1, CLASS2) \ + (((FLOAT_CLASS_P (CLASS1) && ! FLOAT_CLASS_P (CLASS2)) \ + || (! FLOAT_CLASS_P (CLASS1) && FLOAT_CLASS_P (CLASS2))) ? 10 \ + : 2) + +/* Specify the registers used for certain standard purposes. + The values of these macros are register numbers. */ + +/* on the 386 the pc register is %eip, and is not usable as a general + register. The ordinary mov instructions won't work */ +/* #define PC_REGNUM */ + +/* Register to use for pushing function arguments. */ +#define STACK_POINTER_REGNUM 7 + +/* Base register for access to local variables of the function. */ +#define FRAME_POINTER_REGNUM 6 + +/* First floating point reg */ +#define FIRST_FLOAT_REG 8 + +/* First & last stack-like regs */ +#define FIRST_STACK_REG FIRST_FLOAT_REG +#define LAST_STACK_REG (FIRST_FLOAT_REG + 7) + +/* Value should be nonzero if functions must have frame pointers. + Zero means the frame pointer need not be set up (and parms + may be accessed via the stack pointer) in functions that seem suitable. + This is computed in `reload', in reload1.c. */ +#define FRAME_POINTER_REQUIRED 0 + +/* Base register for access to arguments of the function. */ +#define ARG_POINTER_REGNUM 16 + +/* Register in which static-chain is passed to a function. */ +#define STATIC_CHAIN_REGNUM 2 + +/* Register to hold the addressing base for position independent + code access to data items. */ +#define PIC_OFFSET_TABLE_REGNUM 3 + +/* Register in which address to store a structure value + arrives in the function. On the 386, the prologue + copies this from the stack to register %eax. */ +#define STRUCT_VALUE_INCOMING 0 + +/* Place in which caller passes the structure value address. + 0 means push the value on the stack like an argument. */ +#define STRUCT_VALUE 0 + +/* Define the classes of registers for register constraints in the + machine description. Also define ranges of constants. + + One of the classes must always be named ALL_REGS and include all hard regs. + If there is more than one class, another class must be named NO_REGS + and contain no registers. + + The name GENERAL_REGS must be the name of a class (or an alias for + another name such as ALL_REGS). This is the class of registers + that is allowed by "g" or "r" in a register constraint. + Also, registers outside this class are allocated only when + instructions express preferences for them. + + The classes must be numbered in nondecreasing order; that is, + a larger-numbered class must never be contained completely + in a smaller-numbered class. + + For any two classes, it is very desirable that there be another + class that represents their union. + + It might seem that class BREG is unnecessary, since no useful 386 + opcode needs reg %ebx. But some systems pass args to the OS in ebx, + and the "b" register constraint is useful in asms for syscalls. */ + +enum reg_class +{ + NO_REGS, + AREG, DREG, CREG, BREG, + Q_REGS, /* %eax %ebx %ecx %edx */ + SIREG, DIREG, + INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */ + GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */ + FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */ + FLOAT_REGS, + ALL_REGS, LIM_REG_CLASSES +}; + +#define N_REG_CLASSES (int) LIM_REG_CLASSES + +#define FLOAT_CLASS_P(CLASS) (reg_class_subset_p (CLASS, FLOAT_REGS)) + +/* Give names of register classes as strings for dump file. */ + +#define REG_CLASS_NAMES \ +{ "NO_REGS", \ + "AREG", "DREG", "CREG", "BREG", \ + "Q_REGS", \ + "SIREG", "DIREG", \ + "INDEX_REGS", \ + "GENERAL_REGS", \ + "FP_TOP_REG", "FP_SECOND_REG", \ + "FLOAT_REGS", \ + "ALL_REGS" } + +/* Define which registers fit in which classes. + This is an initializer for a vector of HARD_REG_SET + of length N_REG_CLASSES. */ + +#define REG_CLASS_CONTENTS \ +{ 0, \ + 0x1, 0x2, 0x4, 0x8, /* AREG, DREG, CREG, BREG */ \ + 0xf, /* Q_REGS */ \ + 0x10, 0x20, /* SIREG, DIREG */ \ + 0x1007f, /* INDEX_REGS */ \ + 0x100ff, /* GENERAL_REGS */ \ + 0x0100, 0x0200, /* FP_TOP_REG, FP_SECOND_REG */ \ + 0xff00, /* FLOAT_REGS */ \ + 0x1ffff } + +/* The same information, inverted: + Return the class number of the smallest class containing + reg number REGNO. This could be a conditional expression + or could index an array. */ + +extern enum reg_class regclass_map[FIRST_PSEUDO_REGISTER]; +#define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO]) + +/* When defined, the compiler allows registers explicitly used in the + rtl to be used as spill registers but prevents the compiler from + extending the lifetime of these registers. */ + +#define SMALL_REGISTER_CLASSES + +#define QI_REG_P(X) \ + (REG_P (X) && REGNO (X) < 4) +#define NON_QI_REG_P(X) \ + (REG_P (X) && REGNO (X) >= 4 && REGNO (X) < FIRST_PSEUDO_REGISTER) + +#define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X))) +#define FP_REGNO_P(n) ((n) >= FIRST_STACK_REG && (n) <= LAST_STACK_REG) + +#define STACK_REG_P(xop) (REG_P (xop) && \ + REGNO (xop) >= FIRST_STACK_REG && \ + REGNO (xop) <= LAST_STACK_REG) + +#define NON_STACK_REG_P(xop) (REG_P (xop) && ! STACK_REG_P (xop)) + +#define STACK_TOP_P(xop) (REG_P (xop) && REGNO (xop) == FIRST_STACK_REG) + +/* Try to maintain the accuracy of the death notes for regs satisfying the + following. Important for stack like regs, to know when to pop. */ + +/* #define PRESERVE_DEATH_INFO_REGNO_P(x) FP_REGNO_P(x) */ + +/* 1 if register REGNO can magically overlap other regs. + Note that nonzero values work only in very special circumstances. */ + +/* #define OVERLAPPING_REGNO_P(REGNO) FP_REGNO_P (REGNO) */ + +/* The class value for index registers, and the one for base regs. */ + +#define INDEX_REG_CLASS INDEX_REGS +#define BASE_REG_CLASS GENERAL_REGS + +/* Get reg_class from a letter such as appears in the machine description. */ + +#define REG_CLASS_FROM_LETTER(C) \ + ((C) == 'r' ? GENERAL_REGS : \ + (C) == 'q' ? Q_REGS : \ + (C) == 'f' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \ + ? FLOAT_REGS \ + : NO_REGS) : \ + (C) == 't' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \ + ? FP_TOP_REG \ + : NO_REGS) : \ + (C) == 'u' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \ + ? FP_SECOND_REG \ + : NO_REGS) : \ + (C) == 'a' ? AREG : \ + (C) == 'b' ? BREG : \ + (C) == 'c' ? CREG : \ + (C) == 'd' ? DREG : \ + (C) == 'D' ? DIREG : \ + (C) == 'S' ? SIREG : NO_REGS) + +/* The letters I, J, K, L and M in a register constraint string + can be used to stand for particular ranges of immediate operands. + This macro defines what the ranges are. + C is the letter, and VALUE is a constant value. + Return 1 if VALUE is in the range specified by C. + + I is for non-DImode shifts. + J is for DImode shifts. + K and L are for an `andsi' optimization. + M is for shifts that can be executed by the "lea" opcode. + */ + +#define CONST_OK_FOR_LETTER_P(VALUE, C) \ + ((C) == 'I' ? (VALUE) >= 0 && (VALUE) <= 31 : \ + (C) == 'J' ? (VALUE) >= 0 && (VALUE) <= 63 : \ + (C) == 'K' ? (VALUE) == 0xff : \ + (C) == 'L' ? (VALUE) == 0xffff : \ + (C) == 'M' ? (VALUE) >= 0 && (VALUE) <= 3 : \ + 0) + +/* Similar, but for floating constants, and defining letters G and H. + Here VALUE is the CONST_DOUBLE rtx itself. We allow constants even if + TARGET_387 isn't set, because the stack register converter may need to + load 0.0 into the function value register. */ + +#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ + ((C) == 'G' ? standard_80387_constant_p (VALUE) : 0) + +/* Place additional restrictions on the register class to use when it + is necessary to be able to hold a value of mode MODE in a reload + register for which class CLASS would ordinarily be used. */ + +#define LIMIT_RELOAD_CLASS(MODE, CLASS) \ + ((MODE) == QImode && ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS) \ + ? Q_REGS : (CLASS)) + +/* Given an rtx X being reloaded into a reg required to be + in class CLASS, return the class of reg to actually use. + In general this is just CLASS; but on some machines + in some cases it is preferable to use a more restrictive class. + On the 80386 series, we prevent floating constants from being + reloaded into floating registers (since no move-insn can do that) + and we ensure that QImodes aren't reloaded into the esi or edi reg. */ + +/* Put float CONST_DOUBLE in the constant pool instead of fp regs. + QImode must go into class Q_REGS. + Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and + movdf to do mem-to-mem moves through integer regs. */ + +#define PREFERRED_RELOAD_CLASS(X,CLASS) \ + (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) != VOIDmode ? NO_REGS \ + : GET_MODE (X) == QImode && ! reg_class_subset_p (CLASS, Q_REGS) ? Q_REGS \ + : ((CLASS) == ALL_REGS \ + && GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT) ? GENERAL_REGS \ + : (CLASS)) + +/* If we are copying between general and FP registers, we need a memory + location. */ + +#define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \ + ((FLOAT_CLASS_P (CLASS1) && ! FLOAT_CLASS_P (CLASS2)) \ + || (! FLOAT_CLASS_P (CLASS1) && FLOAT_CLASS_P (CLASS2))) + +/* Return the maximum number of consecutive registers + needed to represent mode MODE in a register of class CLASS. */ +/* On the 80386, this is the size of MODE in words, + except in the FP regs, where a single reg is always enough. */ +#define CLASS_MAX_NREGS(CLASS, MODE) \ + (FLOAT_CLASS_P (CLASS) ? 1 : \ + ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) + +/* Stack layout; function entry, exit and calling. */ + +/* Define this if pushing a word on the stack + makes the stack pointer a smaller address. */ +#define STACK_GROWS_DOWNWARD + +/* Define this if the nominal address of the stack frame + is at the high-address end of the local variables; + that is, each additional local variable allocated + goes at a more negative offset in the frame. */ +#define FRAME_GROWS_DOWNWARD + +/* Offset within stack frame to start allocating local variables at. + If FRAME_GROWS_DOWNWARD, this is the offset to the END of the + first local allocated. Otherwise, it is the offset to the BEGINNING + of the first local allocated. */ +#define STARTING_FRAME_OFFSET 0 + +/* If we generate an insn to push BYTES bytes, + this says how many the stack pointer really advances by. + On 386 pushw decrements by exactly 2 no matter what the position was. + On the 386 there is no pushb; we use pushw instead, and this + has the effect of rounding up to 2. */ + +#define PUSH_ROUNDING(BYTES) (((BYTES) + 1) & (-2)) + +/* Offset of first parameter from the argument pointer register value. */ +#define FIRST_PARM_OFFSET(FNDECL) 0 + +/* Value is the number of bytes of arguments automatically + popped when returning from a subroutine call. + FUNTYPE is the data type of the function (as a tree), + or for a library call it is an identifier node for the subroutine name. + SIZE is the number of bytes of arguments passed on the stack. + + On the 80386, the RTD insn may be used to pop them if the number + of args is fixed, but if the number is variable then the caller + must pop them all. RTD can't be used for library calls now + because the library is compiled with the Unix compiler. + Use of RTD is a selectable option, since it is incompatible with + standard Unix calling sequences. If the option is not selected, + the caller must always pop the args. */ + +#define RETURN_POPS_ARGS(FUNTYPE,SIZE) \ + (TREE_CODE (FUNTYPE) == IDENTIFIER_NODE ? 0 \ + : (TARGET_RTD \ + && (TYPE_ARG_TYPES (FUNTYPE) == 0 \ + || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (FUNTYPE))) \ + == void_type_node))) ? (SIZE) \ + : (aggregate_value_p (FUNTYPE)) ? GET_MODE_SIZE (Pmode) : 0) + +/* Define how to find the value returned by a function. + VALTYPE is the data type of the value (as a tree). + If the precise function being called is known, FUNC is its FUNCTION_DECL; + otherwise, FUNC is 0. */ +#define FUNCTION_VALUE(VALTYPE, FUNC) \ + gen_rtx (REG, TYPE_MODE (VALTYPE), \ + VALUE_REGNO (TYPE_MODE (VALTYPE))) + +/* Define how to find the value returned by a library function + assuming the value has mode MODE. */ + +#define LIBCALL_VALUE(MODE) \ + gen_rtx (REG, MODE, VALUE_REGNO (MODE)) + +/* Define the size of the result block used for communication between + untyped_call and untyped_return. The block contains a DImode value + followed by the block used by fnsave and frstor. */ + +#define APPLY_RESULT_SIZE (8+108) + +/* 1 if N is a possible register number for function argument passing. + On the 80386, no registers are used in this way. + *NOTE* -mregparm does not work. + It exists only to test register calling conventions. */ + +#define FUNCTION_ARG_REGNO_P(N) 0 + +/* Define a data type for recording info about an argument list + during the scan of that argument list. This data type should + hold all necessary information about the function itself + and about the args processed so far, enough to enable macros + such as FUNCTION_ARG to determine where the next arg should go. + + On the 80386, this is a single integer, which is a number of bytes + of arguments scanned so far. */ + +#define CUMULATIVE_ARGS int + +/* Initialize a variable CUM of type CUMULATIVE_ARGS + for a call to a function whose data type is FNTYPE. + For a library call, FNTYPE is 0. + + On the 80386, the offset starts at 0. */ + +#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME) \ + ((CUM) = 0) + +/* Update the data in CUM to advance over an argument + of mode MODE and data type TYPE. + (TYPE is null for libcalls where that information may not be available.) */ + +#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ + ((CUM) += ((MODE) != BLKmode \ + ? (GET_MODE_SIZE (MODE) + 3) & ~3 \ + : (int_size_in_bytes (TYPE) + 3) & ~3)) + +/* Define where to put the arguments to a function. + Value is zero to push the argument on the stack, + or a hard register in which to store the argument. + + MODE is the argument's machine mode. + TYPE is the data type of the argument (as a tree). + This is null for libcalls where that information may + not be available. + CUM is a variable of type CUMULATIVE_ARGS which gives info about + the preceding args and about the function being called. + NAMED is nonzero if this argument is a named parameter + (otherwise it is an extra parameter matching an ellipsis). */ + + +/* On the 80386 all args are pushed, except if -mregparm is specified + then the first two words of arguments are passed in EAX, EDX. + *NOTE* -mregparm does not work. + It exists only to test register calling conventions. */ + +#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ +((TARGET_REGPARM && (CUM) < 8) ? gen_rtx (REG, (MODE), (CUM) / 4) : 0) + +/* For an arg passed partly in registers and partly in memory, + this is the number of registers used. + For args passed entirely in registers or entirely in memory, zero. */ + + +#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \ +((TARGET_REGPARM && (CUM) < 8 \ + && 8 < ((CUM) + ((MODE) == BLKmode \ + ? int_size_in_bytes (TYPE) \ + : GET_MODE_SIZE (MODE)))) \ + ? 2 - (CUM) / 4 : 0) + +/* This macro generates the assembly code for function entry. + FILE is a stdio stream to output the code to. + SIZE is an int: how many units of temporary storage to allocate. + Refer to the array `regs_ever_live' to determine which registers + to save; `regs_ever_live[I]' is nonzero if register number I + is ever used in the function. This macro is responsible for + knowing which registers should not be saved even if used. */ + +#define FUNCTION_PROLOGUE(FILE, SIZE) \ + function_prologue (FILE, SIZE) + +/* Output assembler code to FILE to increment profiler label # LABELNO + for profiling a function entry. */ + +#define FUNCTION_PROFILER(FILE, LABELNO) \ +{ \ + if (flag_pic) \ + { \ + fprintf (FILE, "\tleal %sP%d@GOTOFF(%%ebx),%%edx\n", \ + LPREFIX, (LABELNO)); \ + fprintf (FILE, "\tcall *_mcount@GOT(%%ebx)\n"); \ + } \ + else \ + { \ + fprintf (FILE, "\tmovl $%sP%d,%%edx\n", LPREFIX, (LABELNO)); \ + fprintf (FILE, "\tcall _mcount\n"); \ + } \ +} + +/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, + the stack pointer does not matter. The value is tested only in + functions that have frame pointers. + No definition is equivalent to always zero. */ +/* Note on the 386 it might be more efficient not to define this since + we have to restore it ourselves from the frame pointer, in order to + use pop */ + +#define EXIT_IGNORE_STACK 1 + +/* This macro generates the assembly code for function exit, + on machines that need it. If FUNCTION_EPILOGUE is not defined + then individual return instructions are generated for each + return statement. Args are same as for FUNCTION_PROLOGUE. + + The function epilogue should not depend on the current stack pointer! + It should use the frame pointer only. This is mandatory because + of alloca; we also take advantage of it to omit stack adjustments + before returning. + + If the last non-note insn in the function is a BARRIER, then there + is no need to emit a function prologue, because control does not fall + off the end. This happens if the function ends in an "exit" call, or + if a `return' insn is emitted directly into the function. */ + +#define FUNCTION_EPILOGUE(FILE, SIZE) \ +do { \ + rtx last = get_last_insn (); \ + if (last && GET_CODE (last) == NOTE) \ + last = prev_nonnote_insn (last); \ + if (! last || GET_CODE (last) != BARRIER) \ + function_epilogue (FILE, SIZE); \ +} while (0) + +/* Output assembler code for a block containing the constant parts + of a trampoline, leaving space for the variable parts. */ + +/* On the 386, the trampoline contains three instructions: + mov #STATIC,ecx + mov #FUNCTION,eax + jmp @eax */ +#define TRAMPOLINE_TEMPLATE(FILE) \ +{ \ + ASM_OUTPUT_CHAR (FILE, GEN_INT (0xb9)); \ + ASM_OUTPUT_SHORT (FILE, const0_rtx); \ + ASM_OUTPUT_SHORT (FILE, const0_rtx); \ + ASM_OUTPUT_CHAR (FILE, GEN_INT (0xb8)); \ + ASM_OUTPUT_SHORT (FILE, const0_rtx); \ + ASM_OUTPUT_SHORT (FILE, const0_rtx); \ + ASM_OUTPUT_CHAR (FILE, GEN_INT (0xff)); \ + ASM_OUTPUT_CHAR (FILE, GEN_INT (0xe0)); \ +} + +/* Length in units of the trampoline for entering a nested function. */ + +#define TRAMPOLINE_SIZE 12 + +/* Emit RTL insns to initialize the variable parts of a trampoline. + FNADDR is an RTX for the address of the function's pure code. + CXT is an RTX for the static chain value for the function. */ + +#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ +{ \ + emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 1)), CXT); \ + emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 6)), FNADDR); \ +} + +/* Definitions for register eliminations. + + This is an array of structures. Each structure initializes one pair + of eliminable registers. The "from" register number is given first, + followed by "to". Eliminations of the same "from" register are listed + in order of preference. + + We have two registers that can be eliminated on the i386. First, the + frame pointer register can often be eliminated in favor of the stack + pointer register. Secondly, the argument pointer register can always be + eliminated; it is replaced with either the stack or frame pointer. */ + +#define ELIMINABLE_REGS \ +{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ + { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \ + { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}} + +/* Given FROM and TO register numbers, say whether this elimination is allowed. + Frame pointer elimination is automatically handled. + + For the i386, if frame pointer elimination is being done, we would like to + convert ap into sp, not fp. + + All other eliminations are valid. */ + +#define CAN_ELIMINATE(FROM, TO) \ + ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM \ + ? ! frame_pointer_needed \ + : 1) + +/* Define the offset between two registers, one to be eliminated, and the other + its replacement, at the start of a routine. */ + +#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ +{ \ + if ((FROM) == ARG_POINTER_REGNUM && (TO) == FRAME_POINTER_REGNUM) \ + (OFFSET) = 8; /* Skip saved PC and previous frame pointer */ \ + else \ + { \ + int regno; \ + int offset = 0; \ + \ + for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) \ + if ((regs_ever_live[regno] && ! call_used_regs[regno]) \ + || (current_function_uses_pic_offset_table \ + && regno == PIC_OFFSET_TABLE_REGNUM)) \ + offset += 4; \ + \ + (OFFSET) = offset + get_frame_size (); \ + \ + if ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \ + (OFFSET) += 4; /* Skip saved PC */ \ + } \ +} + +/* Addressing modes, and classification of registers for them. */ + +/* #define HAVE_POST_INCREMENT */ +/* #define HAVE_POST_DECREMENT */ + +/* #define HAVE_PRE_DECREMENT */ +/* #define HAVE_PRE_INCREMENT */ + +/* Macros to check register numbers against specific register classes. */ + +/* These assume that REGNO is a hard or pseudo reg number. + They give nonzero only if REGNO is a hard reg of the suitable class + or a pseudo reg currently allocated to a suitable hard reg. + Since they use reg_renumber, they are safe only once reg_renumber + has been allocated, which happens in local-alloc.c. */ + +#define REGNO_OK_FOR_INDEX_P(REGNO) \ + ((REGNO) < STACK_POINTER_REGNUM \ + || (unsigned) reg_renumber[REGNO] < STACK_POINTER_REGNUM) + +#define REGNO_OK_FOR_BASE_P(REGNO) \ + ((REGNO) <= STACK_POINTER_REGNUM \ + || (REGNO) == ARG_POINTER_REGNUM \ + || (unsigned) reg_renumber[REGNO] <= STACK_POINTER_REGNUM) + +#define REGNO_OK_FOR_SIREG_P(REGNO) ((REGNO) == 4 || reg_renumber[REGNO] == 4) +#define REGNO_OK_FOR_DIREG_P(REGNO) ((REGNO) == 5 || reg_renumber[REGNO] == 5) + +/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx + and check its validity for a certain class. + We have two alternate definitions for each of them. + The usual definition accepts all pseudo regs; the other rejects + them unless they have been allocated suitable hard regs. + The symbol REG_OK_STRICT causes the latter definition to be used. + + Most source files want to accept pseudo regs in the hope that + they will get allocated to the class that the insn wants them to be in. + Source files for reload pass need to be strict. + After reload, it makes no difference, since pseudo regs have + been eliminated by then. */ + +#ifndef REG_OK_STRICT + +/* Nonzero if X is a hard reg that can be used as an index or if + it is a pseudo reg. */ + +#define REG_OK_FOR_INDEX_P(X) \ + (REGNO (X) < STACK_POINTER_REGNUM \ + || REGNO (X) >= FIRST_PSEUDO_REGISTER) + +/* Nonzero if X is a hard reg that can be used as a base reg + of if it is a pseudo reg. */ + /* ?wfs */ + +#define REG_OK_FOR_BASE_P(X) \ + (REGNO (X) <= STACK_POINTER_REGNUM \ + || REGNO (X) == ARG_POINTER_REGNUM \ + || REGNO(X) >= FIRST_PSEUDO_REGISTER) + +#define REG_OK_FOR_STRREG_P(X) \ + (REGNO (X) == 4 || REGNO (X) == 5 || REGNO (X) >= FIRST_PSEUDO_REGISTER) + +#else + +/* Nonzero if X is a hard reg that can be used as an index. */ +#define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) +/* Nonzero if X is a hard reg that can be used as a base reg. */ +#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) +#define REG_OK_FOR_STRREG_P(X) \ + (REGNO_OK_FOR_DIREG_P (REGNO (X)) || REGNO_OK_FOR_SIREG_P (REGNO (X))) + +#endif + +/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression + that is a valid memory address for an instruction. + The MODE argument is the machine mode for the MEM expression + that wants to use this address. + + The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS, + except for CONSTANT_ADDRESS_P which is usually machine-independent. + + See legitimize_pic_address in i386.c for details as to what + constitutes a legitimate address when -fpic is used. */ + +#define MAX_REGS_PER_ADDRESS 2 + +#define CONSTANT_ADDRESS_P(X) \ + (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ + || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \ + || GET_CODE (X) == HIGH) + +/* Nonzero if the constant value X is a legitimate general operand. + It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ + +#define LEGITIMATE_CONSTANT_P(X) 1 + +#define GO_IF_INDEXABLE_BASE(X, ADDR) \ + if (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) goto ADDR + +#define LEGITIMATE_INDEX_REG_P(X) \ + (GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) + +/* Return 1 if X is an index or an index times a scale. */ + +#define LEGITIMATE_INDEX_P(X) \ + (LEGITIMATE_INDEX_REG_P (X) \ + || (GET_CODE (X) == MULT \ + && LEGITIMATE_INDEX_REG_P (XEXP (X, 0)) \ + && GET_CODE (XEXP (X, 1)) == CONST_INT \ + && (INTVAL (XEXP (X, 1)) == 2 \ + || INTVAL (XEXP (X, 1)) == 4 \ + || INTVAL (XEXP (X, 1)) == 8))) + +/* Go to ADDR if X is an index term, a base reg, or a sum of those. */ + +#define GO_IF_INDEXING(X, ADDR) \ +{ if (LEGITIMATE_INDEX_P (X)) goto ADDR; \ + GO_IF_INDEXABLE_BASE (X, ADDR); \ + if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 0))) \ + { GO_IF_INDEXABLE_BASE (XEXP (X, 1), ADDR); } \ + if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 1))) \ + { GO_IF_INDEXABLE_BASE (XEXP (X, 0), ADDR); } } + +/* We used to allow this, but it isn't ever used. + || ((GET_CODE (X) == POST_DEC || GET_CODE (X) == POST_INC) \ + && REG_P (XEXP (X, 0)) \ + && REG_OK_FOR_STRREG_P (XEXP (X, 0))) \ +*/ + +#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ +{ \ + if (CONSTANT_ADDRESS_P (X) \ + && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (X))) \ + goto ADDR; \ + GO_IF_INDEXING (X, ADDR); \ + if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 1))) \ + { \ + rtx x0 = XEXP (X, 0); \ + if (! flag_pic || ! SYMBOLIC_CONST (XEXP (X, 1))) \ + { GO_IF_INDEXING (x0, ADDR); } \ + else if (x0 == pic_offset_table_rtx) \ + goto ADDR; \ + else if (GET_CODE (x0) == PLUS) \ + { \ + if (XEXP (x0, 0) == pic_offset_table_rtx) \ + { GO_IF_INDEXABLE_BASE (XEXP (x0, 1), ADDR); } \ + if (XEXP (x0, 1) == pic_offset_table_rtx) \ + { GO_IF_INDEXABLE_BASE (XEXP (x0, 0), ADDR); } \ + } \ + } \ +} + +/* Try machine-dependent ways of modifying an illegitimate address + to be legitimate. If we find one, return the new, valid address. + This macro is used in only one place: `memory_address' in explow.c. + + OLDX is the address as it was before break_out_memory_refs was called. + In some cases it is useful to look at this to decide what needs to be done. + + MODE and WIN are passed so that this macro can use + GO_IF_LEGITIMATE_ADDRESS. + + It is always safe for this macro to do nothing. It exists to recognize + opportunities to optimize the output. + + For the 80386, we handle X+REG by loading X into a register R and + using R+REG. R will go in a general reg and indexing will be used. + However, if REG is a broken-out memory address or multiplication, + nothing needs to be done because REG can certainly go in a general reg. + + When -fpic is used, special handling is needed for symbolic references. + See comments by legitimize_pic_address in i386.c for details. */ + +#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \ +{ extern rtx legitimize_pic_address (); \ + int ch = (X) != (OLDX); \ + if (flag_pic && SYMBOLIC_CONST (X)) \ + { \ + (X) = legitimize_pic_address (X, 0); \ + if (memory_address_p (MODE, X)) \ + goto WIN; \ + } \ + if (GET_CODE (X) == PLUS) \ + { if (GET_CODE (XEXP (X, 0)) == MULT) \ + ch = 1, XEXP (X, 0) = force_operand (XEXP (X, 0), 0); \ + if (GET_CODE (XEXP (X, 1)) == MULT) \ + ch = 1, XEXP (X, 1) = force_operand (XEXP (X, 1), 0); \ + if (ch && GET_CODE (XEXP (X, 1)) == REG \ + && GET_CODE (XEXP (X, 0)) == REG) \ + goto WIN; \ + if (flag_pic && SYMBOLIC_CONST (XEXP (X, 1))) \ + ch = 1, (X) = legitimize_pic_address (X, 0); \ + if (ch) { GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN); } \ + if (GET_CODE (XEXP (X, 0)) == REG) \ + { register rtx temp = gen_reg_rtx (Pmode); \ + register rtx val = force_operand (XEXP (X, 1), temp); \ + if (val != temp) emit_move_insn (temp, val); \ + XEXP (X, 1) = temp; \ + goto WIN; } \ + else if (GET_CODE (XEXP (X, 1)) == REG) \ + { register rtx temp = gen_reg_rtx (Pmode); \ + register rtx val = force_operand (XEXP (X, 0), temp); \ + if (val != temp) emit_move_insn (temp, val); \ + XEXP (X, 0) = temp; \ + goto WIN; }}} + +/* Nonzero if the constant value X is a legitimate general operand + when generating PIC code. It is given that flag_pic is on and + that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ + +#define LEGITIMATE_PIC_OPERAND_P(X) \ + (! SYMBOLIC_CONST (X) \ + || (GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X))) + +#define SYMBOLIC_CONST(X) \ +(GET_CODE (X) == SYMBOL_REF \ + || GET_CODE (X) == LABEL_REF \ + || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X))) + +/* Go to LABEL if ADDR (a legitimate address expression) + has an effect that depends on the machine mode it is used for. + On the 80386, only postdecrement and postincrement address depend thus + (the amount of decrement or increment being the length of the operand). */ +#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \ + if (GET_CODE (ADDR) == POST_INC || GET_CODE (ADDR) == POST_DEC) goto LABEL + +/* Define this macro if references to a symbol must be treated + differently depending on something about the variable or + function named by the symbol (such as what section it is in). + + On i386, if using PIC, mark a SYMBOL_REF for a non-global symbol + so that we may access it directly in the GOT. */ + +#define ENCODE_SECTION_INFO(DECL) \ +do \ + { \ + if (flag_pic) \ + { \ + rtx rtl = (TREE_CODE_CLASS (TREE_CODE (DECL)) != 'd' \ + ? TREE_CST_RTL (DECL) : DECL_RTL (DECL)); \ + SYMBOL_REF_FLAG (XEXP (rtl, 0)) \ + = (TREE_CODE_CLASS (TREE_CODE (DECL)) != 'd' \ + || ! TREE_PUBLIC (DECL)); \ + } \ + } \ +while (0) + +/* Initialize data used by insn expanders. This is called from + init_emit, once for each function, before code is generated. + For 386, clear stack slot assignments remembered from previous + functions. */ + +#define INIT_EXPANDERS clear_386_stack_locals () + +/* Specify the machine mode that this machine uses + for the index in the tablejump instruction. */ +#define CASE_VECTOR_MODE Pmode + +/* Define this if the tablejump instruction expects the table + to contain offsets from the address of the table. + Do not define this if the table should contain absolute addresses. */ +/* #define CASE_VECTOR_PC_RELATIVE */ + +/* Specify the tree operation to be used to convert reals to integers. + This should be changed to take advantage of fist --wfs ?? + */ +#define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR + +/* This is the kind of divide that is easiest to do in the general case. */ +#define EASY_DIV_EXPR TRUNC_DIV_EXPR + +/* Define this as 1 if `char' should by default be signed; else as 0. */ +#define DEFAULT_SIGNED_CHAR 1 + +/* Max number of bytes we can move from memory to memory + in one reasonably fast instruction. */ +#define MOVE_MAX 4 + +/* MOVE_RATIO is the number of move instructions that is better than a + block move. Make this large on i386, since the block move is very + inefficient with small blocks, and the hard register needs of the + block move require much reload work. */ +#define MOVE_RATIO 5 + +/* Define this if zero-extension is slow (more than one real instruction). */ +/* #define SLOW_ZERO_EXTEND */ + +/* Nonzero if access to memory by bytes is slow and undesirable. */ +#define SLOW_BYTE_ACCESS 0 + +/* Define if shifts truncate the shift count + which implies one can omit a sign-extension or zero-extension + of a shift count. */ +/* One i386, shifts do truncate the count. But bit opcodes don't. */ + +/* #define SHIFT_COUNT_TRUNCATED */ + +/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits + is done just by pretending it is already truncated. */ +#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 + +/* We assume that the store-condition-codes instructions store 0 for false + and some other value for true. This is the value stored for true. */ + +#define STORE_FLAG_VALUE 1 + +/* When a prototype says `char' or `short', really pass an `int'. + (The 386 can't easily push less than an int.) */ + +#define PROMOTE_PROTOTYPES + +/* Specify the machine mode that pointers have. + After generation of rtl, the compiler makes no further distinction + between pointers and any other objects of this machine mode. */ +#define Pmode SImode + +/* A function address in a call instruction + is a byte address (for indexing purposes) + so give the MEM rtx a byte's mode. */ +#define FUNCTION_MODE QImode + +/* Define this if addresses of constant functions + shouldn't be put through pseudo regs where they can be cse'd. + Desirable on the 386 because a CALL with a constant address is + not much slower than one with a register address. */ +#define NO_FUNCTION_CSE + +/* Provide the costs of a rtl expression. This is in the body of a + switch on CODE. */ + +#define RTX_COSTS(X,CODE,OUTER_CODE) \ + case MULT: \ + return COSTS_N_INSNS (10); \ + case DIV: \ + case UDIV: \ + case MOD: \ + case UMOD: \ + return COSTS_N_INSNS (40); \ + case PLUS: \ + if (GET_CODE (XEXP (X, 0)) == REG \ + && GET_CODE (XEXP (X, 1)) == CONST_INT) \ + return 1; \ + break; + + +/* Compute the cost of computing a constant rtl expression RTX + whose rtx-code is CODE. The body of this macro is a portion + of a switch statement. If the code is computed here, + return it with a return statement. Otherwise, break from the switch. */ + +#define CONST_COSTS(RTX,CODE,OUTER_CODE) \ + case CONST_INT: \ + case CONST: \ + case LABEL_REF: \ + case SYMBOL_REF: \ + return flag_pic && SYMBOLIC_CONST (RTX) ? 2 : 0; \ + case CONST_DOUBLE: \ + { \ + int code; \ + if (GET_MODE (RTX) == VOIDmode) \ + return 2; \ + code = standard_80387_constant_p (RTX); \ + return code == 1 ? 0 : \ + code == 2 ? 1 : \ + 2; \ + } + +/* Compute the cost of an address. This is meant to approximate the size + and/or execution delay of an insn using that address. If the cost is + approximated by the RTL complexity, including CONST_COSTS above, as + is usually the case for CISC machines, this macro should not be defined. + For aggressively RISCy machines, only one insn format is allowed, so + this macro should be a constant. The value of this macro only matters + for valid addresses. + + For i386, it is better to use a complex address than let gcc copy + the address into a reg and make a new pseudo. But not if the address + requires to two regs - that would mean more pseudos with longer + lifetimes. */ + +#define ADDRESS_COST(RTX) \ + ((CONSTANT_P (RTX) \ + || (GET_CODE (RTX) == PLUS && CONSTANT_P (XEXP (RTX, 1)) \ + && REG_P (XEXP (RTX, 0)))) ? 0 \ + : REG_P (RTX) ? 1 \ + : 2) + +/* Add any extra modes needed to represent the condition code. + + For the i386, we need separate modes when floating-point equality + comparisons are being done. */ + +#define EXTRA_CC_MODES CCFPEQmode + +/* Define the names for the modes specified above. */ +#define EXTRA_CC_NAMES "CCFPEQ" + +/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, + return the mode to be used for the comparison. + + For floating-point equality comparisons, CCFPEQmode should be used. + VOIDmode should be used in all other cases. */ + +#define SELECT_CC_MODE(OP,X,Y) \ + (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \ + && ((OP) == EQ || (OP) == NE) ? CCFPEQmode : VOIDmode) + +/* Define the information needed to generate branch and scc insns. This is + stored from the compare operation. Note that we can't use "rtx" here + since it hasn't been defined! */ + +extern struct rtx_def *i386_compare_op0, *i386_compare_op1; +extern struct rtx_def *(*i386_compare_gen)(), *(*i386_compare_gen_eq)(); + +/* Tell final.c how to eliminate redundant test instructions. */ + +/* Here we define machine-dependent flags and fields in cc_status + (see `conditions.h'). */ + +/* Set if the cc value is actually in the 80387, so a floating point + conditional branch must be output. */ +#define CC_IN_80387 04000 + +/* Set if the CC value was stored in a nonstandard way, so that + the state of equality is indicated by zero in the carry bit. */ +#define CC_Z_IN_NOT_C 010000 + +/* Store in cc_status the expressions + that the condition codes will describe + after execution of an instruction whose pattern is EXP. + Do not alter them if the instruction would not alter the cc's. */ + +#define NOTICE_UPDATE_CC(EXP, INSN) \ + notice_update_cc((EXP)) + +/* Output a signed jump insn. Use template NORMAL ordinarily, or + FLOAT following a floating point comparison. + Use NO_OV following an arithmetic insn that set the cc's + before a test insn that was deleted. + NO_OV may be zero, meaning final should reinsert the test insn + because the jump cannot be handled properly without it. */ + +#define OUTPUT_JUMP(NORMAL, FLOAT, NO_OV) \ +{ \ + if (cc_prev_status.flags & CC_IN_80387) \ + return FLOAT; \ + if (cc_prev_status.flags & CC_NO_OVERFLOW) \ + return NO_OV; \ + return NORMAL; \ +} + +/* Control the assembler format that we output, to the extent + this does not vary between assemblers. */ + +/* How to refer to registers in assembler output. + This sequence is indexed by compiler's hard-register-number (see above). */ + +/* In order to refer to the first 8 regs as 32 bit regs prefix an "e" + For non floating point regs, the following are the HImode names. + + For float regs, the stack top is sometimes referred to as "%st(0)" + instead of just "%st". PRINT_REG handles this with the "y" code. */ + +#define HI_REGISTER_NAMES \ +{"ax","dx","cx","bx","si","di","bp","sp", \ + "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)","" } + +#define REGISTER_NAMES HI_REGISTER_NAMES + +/* Table of additional register names to use in user input. */ + +#define ADDITIONAL_REGISTER_NAMES \ +{ "eax", 0, "edx", 1, "ecx", 2, "ebx", 3, \ + "esi", 4, "edi", 5, "ebp", 6, "esp", 7, \ + "al", 0, "dl", 1, "cl", 2, "bl", 3, \ + "ah", 0, "dh", 1, "ch", 2, "bh", 3 } + +/* Note we are omitting these since currently I don't know how +to get gcc to use these, since they want the same but different +number as al, and ax. +*/ + +/* note the last four are not really qi_registers, but + the md will have to never output movb into one of them + only a movw . There is no movb into the last four regs */ + +#define QI_REGISTER_NAMES \ +{"al", "dl", "cl", "bl", "si", "di", "bp", "sp",} + +/* These parallel the array above, and can be used to access bits 8:15 + of regs 0 through 3. */ + +#define QI_HIGH_REGISTER_NAMES \ +{"ah", "dh", "ch", "bh", } + +/* How to renumber registers for dbx and gdb. */ + +/* {0,2,1,3,6,7,4,5,12,13,14,15,16,17} */ +#define DBX_REGISTER_NUMBER(n) \ +((n) == 0 ? 0 : \ + (n) == 1 ? 2 : \ + (n) == 2 ? 1 : \ + (n) == 3 ? 3 : \ + (n) == 4 ? 6 : \ + (n) == 5 ? 7 : \ + (n) == 6 ? 4 : \ + (n) == 7 ? 5 : \ + (n) + 4) + +/* This is how to output the definition of a user-level label named NAME, + such as the label on a static function or variable NAME. */ + +#define ASM_OUTPUT_LABEL(FILE,NAME) \ + (assemble_name (FILE, NAME), fputs (":\n", FILE)) + +/* This is how to output an assembler line defining a `double' constant. */ + +#define ASM_OUTPUT_DOUBLE(FILE,VALUE) \ + fprintf (FILE, "%s %.22e\n", ASM_DOUBLE, (VALUE)) + + +/* This is how to output an assembler line defining a `float' constant. */ + +#define ASM_OUTPUT_FLOAT(FILE,VALUE) \ +do { union { float f; long l;} tem; \ + tem.f = (VALUE); \ + fprintf((FILE), "%s 0x%x\n", ASM_LONG, tem.l); \ + } while (0) + + +/* Store in OUTPUT a string (made with alloca) containing + an assembler-name for a local static variable named NAME. + LABELNO is an integer which is different for each call. */ + +#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ +( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \ + sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO))) + + + +/* This is how to output an assembler line defining an `int' constant. */ + +#define ASM_OUTPUT_INT(FILE,VALUE) \ +( fprintf (FILE, "%s ", ASM_LONG), \ + output_addr_const (FILE,(VALUE)), \ + putc('\n',FILE)) + +/* Likewise for `char' and `short' constants. */ +/* is this supposed to do align too?? */ + +#define ASM_OUTPUT_SHORT(FILE,VALUE) \ +( fprintf (FILE, "%s ", ASM_SHORT), \ + output_addr_const (FILE,(VALUE)), \ + putc('\n',FILE)) + +/* +#define ASM_OUTPUT_SHORT(FILE,VALUE) \ +( fprintf (FILE, "%s ", ASM_BYTE_OP), \ + output_addr_const (FILE,(VALUE)), \ + fputs (",", FILE), \ + output_addr_const (FILE,(VALUE)), \ + fputs (" >> 8\n",FILE)) +*/ + + +#define ASM_OUTPUT_CHAR(FILE,VALUE) \ +( fprintf (FILE, "%s ", ASM_BYTE_OP), \ + output_addr_const (FILE, (VALUE)), \ + putc ('\n', FILE)) + +/* This is how to output an assembler line for a numeric constant byte. */ + +#define ASM_OUTPUT_BYTE(FILE,VALUE) \ + fprintf ((FILE), "%s 0x%x\n", ASM_BYTE_OP, (VALUE)) + +/* This is how to output an insn to push a register on the stack. + It need not be very fast code. */ + +#define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \ + fprintf (FILE, "\tpushl e%s\n", reg_names[REGNO]) + +/* This is how to output an insn to pop a register from the stack. + It need not be very fast code. */ + +#define ASM_OUTPUT_REG_POP(FILE,REGNO) \ + fprintf (FILE, "\tpopl e%s\n", reg_names[REGNO]) + +/* This is how to output an element of a case-vector that is absolute. + */ + +#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ + fprintf (FILE, "%s %s%d\n", ASM_LONG, LPREFIX, VALUE) + +/* This is how to output an element of a case-vector that is relative. + We don't use these on the 386 yet, because the ATT assembler can't do + forward reference the differences. + */ + +#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \ + fprintf (FILE, "\t.word %s%d-%s%d\n",LPREFIX, VALUE,LPREFIX, REL) + +/* Define the parentheses used to group arithmetic operations + in assembler code. */ + +#define ASM_OPEN_PAREN "" +#define ASM_CLOSE_PAREN "" + +/* Define results of standard character escape sequences. */ +#define TARGET_BELL 007 +#define TARGET_BS 010 +#define TARGET_TAB 011 +#define TARGET_NEWLINE 012 +#define TARGET_VT 013 +#define TARGET_FF 014 +#define TARGET_CR 015 + +/* Print operand X (an rtx) in assembler syntax to file FILE. + CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. + The CODE z takes the size of operand from the following digit, and + outputs b,w,or l respectively. + + On the 80386, we use several such letters: + f -- float insn (print a CONST_DOUBLE as a float rather than in hex). + L,W,B,Q,S -- print the opcode suffix for specified size of operand. + R -- print the prefix for register names. + z -- print the opcode suffix for the size of the current operand. + * -- print a star (in certain assembler syntax) + w -- print the operand as if it's a "word" (HImode) even if it isn't. + b -- print the operand as if it's a byte (QImode) even if it isn't. + c -- don't print special prefixes before constant operands. */ + +#define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ + ((CODE) == '*') + +/* Print the name of a register based on its machine mode and number. + If CODE is 'w', pretend the mode is HImode. + If CODE is 'b', pretend the mode is QImode. + If CODE is 'k', pretend the mode is SImode. + If CODE is 'h', pretend the reg is the `high' byte register. + If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op. */ + +extern char *hi_reg_name[]; +extern char *qi_reg_name[]; +extern char *qi_high_reg_name[]; + +#define PRINT_REG(X, CODE, FILE) \ + do { if (REGNO (X) == ARG_POINTER_REGNUM) \ + abort (); \ + fprintf (FILE, "%s", RP); \ + switch ((CODE == 'w' ? 2 \ + : CODE == 'b' ? 1 \ + : CODE == 'k' ? 4 \ + : CODE == 'y' ? 3 \ + : CODE == 'h' ? 0 \ + : GET_MODE_SIZE (GET_MODE (X)))) \ + { \ + case 3: \ + if (STACK_TOP_P (X)) \ + { \ + fputs ("st(0)", FILE); \ + break; \ + } \ + case 4: \ + case 8: \ + if (! FP_REG_P (X)) fputs ("e", FILE); \ + case 2: \ + fputs (hi_reg_name[REGNO (X)], FILE); \ + break; \ + case 1: \ + fputs (qi_reg_name[REGNO (X)], FILE); \ + break; \ + case 0: \ + fputs (qi_high_reg_name[REGNO (X)], FILE); \ + break; \ + } \ + } while (0) + +#define PRINT_OPERAND(FILE, X, CODE) \ + print_operand (FILE, X, CODE) + +#define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ + print_operand_address (FILE, ADDR) + +/* Print the name of a register for based on its machine mode and number. + This macro is used to print debugging output. + This macro is different from PRINT_REG in that it may be used in + programs that are not linked with aux-output.o. */ + +#define DEBUG_PRINT_REG(X, CODE, FILE) \ + do { static char *hi_name[] = HI_REGISTER_NAMES; \ + static char *qi_name[] = QI_REGISTER_NAMES; \ + fprintf (FILE, "%d %s", REGNO (X), RP); \ + if (REGNO (X) == ARG_POINTER_REGNUM) \ + { fputs ("argp", FILE); break; } \ + if (STACK_TOP_P (X)) \ + { fputs ("st(0)", FILE); break; } \ + switch (GET_MODE_SIZE (GET_MODE (X))) \ + { \ + case 8: \ + case 4: \ + if (! FP_REG_P (X)) fputs ("e", FILE); \ + case 2: \ + fputs (hi_name[REGNO (X)], FILE); \ + break; \ + case 1: \ + fputs (qi_name[REGNO (X)], FILE); \ + break; \ + } \ + } while (0) + +/* Output the prefix for an immediate operand, or for an offset operand. */ +#define PRINT_IMMED_PREFIX(FILE) fputs (IP, (FILE)) +#define PRINT_OFFSET_PREFIX(FILE) fputs (IP, (FILE)) + +/* Routines in libgcc that return floats must return them in an fp reg, + just as other functions do which return such values. + These macros make that happen. */ + +#define FLOAT_VALUE_TYPE float +#define INTIFY(FLOATVAL) FLOATVAL + +/* Nonzero if INSN magically clobbers register REGNO. */ + +/* #define INSN_CLOBBERS_REGNO_P(INSN, REGNO) \ + (FP_REGNO_P (REGNO) \ + && (GET_CODE (INSN) == JUMP_INSN || GET_CODE (INSN) == BARRIER)) +*/ + +/* a letter which is not needed by the normal asm syntax, which + we can use for operand syntax in the extended asm */ + +#define ASM_OPERAND_LETTER '#' + +#define RET return "" +#define AT_SP(mode) (gen_rtx (MEM, (mode), stack_pointer_rtx)) + +/* +Local variables: +version-control: t +End: +*/ diff --git a/gnu/usr.bin/gcc2/i386/insn-attr.h b/gnu/usr.bin/gcc2/i386/insn-attr.h new file mode 100644 index 00000000000..5fe9a2f8001 --- /dev/null +++ b/gnu/usr.bin/gcc2/i386/insn-attr.h @@ -0,0 +1,19 @@ +/* Generated automatically by the program `genattr' +from the machine description file `md'. */ + +#ifndef PROTO +#if defined (USE_PROTOTYPES) ? USE_PROTOTYPES : defined (__STDC__) +#define PROTO(ARGS) ARGS +#else +#define PROTO(ARGS) () +#endif +#endif +#define HAVE_ATTR_alternative +#define get_attr_alternative(insn) which_alternative + +#define ATTR_FLAG_forward 0x1 +#define ATTR_FLAG_backward 0x2 +#define ATTR_FLAG_likely 0x4 +#define ATTR_FLAG_very_likely 0x8 +#define ATTR_FLAG_unlikely 0x10 +#define ATTR_FLAG_very_unlikely 0x20 diff --git a/gnu/usr.bin/gcc2/i386/insn-attrtab.c b/gnu/usr.bin/gcc2/i386/insn-attrtab.c new file mode 100644 index 00000000000..0e86d1f4c35 --- /dev/null +++ b/gnu/usr.bin/gcc2/i386/insn-attrtab.c @@ -0,0 +1,14 @@ +/* Generated automatically by the program `genattrtab' +from the machine description file `md'. */ + +#include "config.h" +#include "rtl.h" +#include "insn-config.h" +#include "recog.h" +#include "regs.h" +#include "real.h" +#include "output.h" +#include "insn-attr.h" + +#define operands recog_operand + diff --git a/gnu/usr.bin/gcc2/i386/insn-codes.h b/gnu/usr.bin/gcc2/i386/insn-codes.h new file mode 100644 index 00000000000..59b4e98d519 --- /dev/null +++ b/gnu/usr.bin/gcc2/i386/insn-codes.h @@ -0,0 +1,174 @@ +/* Generated automatically by the program `gencodes' +from the machine description file `md'. */ + +#ifndef MAX_INSN_CODE + +enum insn_code { + CODE_FOR_tstsi_1 = 0, + CODE_FOR_tstsi = 1, + CODE_FOR_tsthi_1 = 2, + CODE_FOR_tsthi = 3, + CODE_FOR_tstqi_1 = 4, + CODE_FOR_tstqi = 5, + CODE_FOR_tstsf_cc = 6, + CODE_FOR_tstsf = 7, + CODE_FOR_tstdf_cc = 8, + CODE_FOR_tstdf = 9, + CODE_FOR_cmpsi_1 = 10, + CODE_FOR_cmpsi = 11, + CODE_FOR_cmphi_1 = 12, + CODE_FOR_cmphi = 13, + CODE_FOR_cmpqi_1 = 14, + CODE_FOR_cmpqi = 15, + CODE_FOR_cmpsf_cc_1 = 22, + CODE_FOR_cmpdf = 26, + CODE_FOR_cmpsf = 27, + CODE_FOR_cmpdf_cc = 28, + CODE_FOR_cmpdf_ccfpeq = 29, + CODE_FOR_cmpsf_cc = 30, + CODE_FOR_cmpsf_ccfpeq = 31, + CODE_FOR_movsi = 37, + CODE_FOR_movhi = 40, + CODE_FOR_movstricthi = 41, + CODE_FOR_movqi = 43, + CODE_FOR_movstrictqi = 44, + CODE_FOR_movsf = 46, + CODE_FOR_swapdf = 48, + CODE_FOR_movdf = 49, + CODE_FOR_movdi = 51, + CODE_FOR_zero_extendhisi2 = 52, + CODE_FOR_zero_extendqihi2 = 53, + CODE_FOR_zero_extendqisi2 = 54, + CODE_FOR_zero_extendsidi2 = 55, + CODE_FOR_extendsidi2 = 56, + CODE_FOR_extendhisi2 = 57, + CODE_FOR_extendqihi2 = 58, + CODE_FOR_extendqisi2 = 59, + CODE_FOR_extendsfdf2 = 60, + CODE_FOR_truncdfsf2 = 61, + CODE_FOR_fixuns_truncdfsi2 = 63, + CODE_FOR_fixuns_truncsfsi2 = 64, + CODE_FOR_fix_truncdfdi2 = 65, + CODE_FOR_fix_truncsfdi2 = 66, + CODE_FOR_fix_truncdfsi2 = 69, + CODE_FOR_fix_truncsfsi2 = 70, + CODE_FOR_floatsisf2 = 73, + CODE_FOR_floatdisf2 = 74, + CODE_FOR_floatsidf2 = 75, + CODE_FOR_floatdidf2 = 76, + CODE_FOR_adddi3 = 81, + CODE_FOR_addsi3 = 82, + CODE_FOR_addhi3 = 83, + CODE_FOR_addqi3 = 84, + CODE_FOR_adddf3 = 86, + CODE_FOR_addsf3 = 87, + CODE_FOR_subdi3 = 88, + CODE_FOR_subsi3 = 89, + CODE_FOR_subhi3 = 90, + CODE_FOR_subqi3 = 91, + CODE_FOR_subdf3 = 92, + CODE_FOR_subsf3 = 93, + CODE_FOR_mulhi3 = 95, + CODE_FOR_mulsi3 = 97, + CODE_FOR_muldf3 = 99, + CODE_FOR_mulsf3 = 100, + CODE_FOR_divqi3 = 101, + CODE_FOR_udivqi3 = 102, + CODE_FOR_divdf3 = 103, + CODE_FOR_divsf3 = 104, + CODE_FOR_divmodsi4 = 105, + CODE_FOR_divmodhi4 = 106, + CODE_FOR_udivmodsi4 = 107, + CODE_FOR_udivmodhi4 = 108, + CODE_FOR_andsi3 = 109, + CODE_FOR_andhi3 = 110, + CODE_FOR_andqi3 = 111, + CODE_FOR_iorsi3 = 112, + CODE_FOR_iorhi3 = 113, + CODE_FOR_iorqi3 = 114, + CODE_FOR_xorsi3 = 115, + CODE_FOR_xorhi3 = 116, + CODE_FOR_xorqi3 = 117, + CODE_FOR_negdi2 = 118, + CODE_FOR_negsi2 = 119, + CODE_FOR_neghi2 = 120, + CODE_FOR_negqi2 = 121, + CODE_FOR_negsf2 = 122, + CODE_FOR_negdf2 = 123, + CODE_FOR_abssf2 = 125, + CODE_FOR_absdf2 = 126, + CODE_FOR_sqrtsf2 = 128, + CODE_FOR_sqrtdf2 = 129, + CODE_FOR_sindf2 = 131, + CODE_FOR_sinsf2 = 132, + CODE_FOR_cosdf2 = 134, + CODE_FOR_cossf2 = 135, + CODE_FOR_one_cmplsi2 = 137, + CODE_FOR_one_cmplhi2 = 138, + CODE_FOR_one_cmplqi2 = 139, + CODE_FOR_ashldi3 = 140, + CODE_FOR_ashldi3_const_int = 141, + CODE_FOR_ashldi3_non_const_int = 142, + CODE_FOR_ashlsi3 = 143, + CODE_FOR_ashlhi3 = 144, + CODE_FOR_ashlqi3 = 145, + CODE_FOR_ashrdi3 = 146, + CODE_FOR_ashrdi3_const_int = 147, + CODE_FOR_ashrdi3_non_const_int = 148, + CODE_FOR_ashrsi3 = 149, + CODE_FOR_ashrhi3 = 150, + CODE_FOR_ashrqi3 = 151, + CODE_FOR_lshrdi3 = 152, + CODE_FOR_lshrdi3_const_int = 153, + CODE_FOR_lshrdi3_non_const_int = 154, + CODE_FOR_lshrsi3 = 155, + CODE_FOR_lshrhi3 = 156, + CODE_FOR_lshrqi3 = 157, + CODE_FOR_rotlsi3 = 158, + CODE_FOR_rotlhi3 = 159, + CODE_FOR_rotlqi3 = 160, + CODE_FOR_rotrsi3 = 161, + CODE_FOR_rotrhi3 = 162, + CODE_FOR_rotrqi3 = 163, + CODE_FOR_seq = 170, + CODE_FOR_sne = 172, + CODE_FOR_sgt = 174, + CODE_FOR_sgtu = 176, + CODE_FOR_slt = 178, + CODE_FOR_sltu = 180, + CODE_FOR_sge = 182, + CODE_FOR_sgeu = 184, + CODE_FOR_sle = 186, + CODE_FOR_sleu = 188, + CODE_FOR_beq = 190, + CODE_FOR_bne = 192, + CODE_FOR_bgt = 194, + CODE_FOR_bgtu = 196, + CODE_FOR_blt = 198, + CODE_FOR_bltu = 200, + CODE_FOR_bge = 202, + CODE_FOR_bgeu = 204, + CODE_FOR_ble = 206, + CODE_FOR_bleu = 208, + CODE_FOR_jump = 220, + CODE_FOR_indirect_jump = 221, + CODE_FOR_casesi = 222, + CODE_FOR_tablejump = 224, + CODE_FOR_call_pop = 225, + CODE_FOR_call = 228, + CODE_FOR_call_value_pop = 231, + CODE_FOR_call_value = 234, + CODE_FOR_untyped_call = 237, + CODE_FOR_untyped_return = 240, + CODE_FOR_update_return = 241, + CODE_FOR_return = 242, + CODE_FOR_nop = 243, + CODE_FOR_movstrsi = 244, + CODE_FOR_cmpstrsi = 246, + CODE_FOR_ffssi2 = 249, + CODE_FOR_ffshi2 = 251, + CODE_FOR_strlensi = 261, + CODE_FOR_nothing }; + +#define MAX_INSN_CODE ((int) CODE_FOR_nothing) +#endif /* MAX_INSN_CODE */ diff --git a/gnu/usr.bin/gcc2/i386/insn-config.h b/gnu/usr.bin/gcc2/i386/insn-config.h new file mode 100644 index 00000000000..7dba8866f62 --- /dev/null +++ b/gnu/usr.bin/gcc2/i386/insn-config.h @@ -0,0 +1,12 @@ +/* Generated automatically by the program `genconfig' +from the machine description file `md'. */ + + +#define MAX_RECOG_OPERANDS 10 + +#define MAX_DUP_OPERANDS 3 +#ifndef MAX_INSNS_PER_SPLIT +#define MAX_INSNS_PER_SPLIT 1 +#endif +#define REGISTER_CONSTRAINTS +#define HAVE_cc0 diff --git a/gnu/usr.bin/gcc2/i386/insn-emit.c b/gnu/usr.bin/gcc2/i386/insn-emit.c new file mode 100644 index 00000000000..8a8d9bd4f80 --- /dev/null +++ b/gnu/usr.bin/gcc2/i386/insn-emit.c @@ -0,0 +1,2708 @@ +/* Generated automatically by the program `genemit' +from the machine description file `md'. */ + +#include "config.h" +#include "rtl.h" +#include "expr.h" +#include "real.h" +#include "output.h" +#include "insn-config.h" + +#include "insn-flags.h" + +#include "insn-codes.h" + +extern char *insn_operand_constraint[][MAX_RECOG_OPERANDS]; + +extern rtx recog_operand[]; +#define operands emit_operand + +#define FAIL goto _fail + +#define DONE goto _done + +rtx +gen_tstsi_1 (operand0) + rtx operand0; +{ + return gen_rtx (SET, VOIDmode, cc0_rtx, operand0); +} + +rtx +gen_tstsi (operand0) + rtx operand0; +{ + rtx operands[1]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + +{ + i386_compare_gen = gen_tstsi_1; + i386_compare_op0 = operands[0]; + DONE; +} + operand0 = operands[0]; + emit_insn (gen_rtx (SET, VOIDmode, cc0_rtx, operand0)); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_tsthi_1 (operand0) + rtx operand0; +{ + return gen_rtx (SET, VOIDmode, cc0_rtx, operand0); +} + +rtx +gen_tsthi (operand0) + rtx operand0; +{ + rtx operands[1]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + +{ + i386_compare_gen = gen_tsthi_1; + i386_compare_op0 = operands[0]; + DONE; +} + operand0 = operands[0]; + emit_insn (gen_rtx (SET, VOIDmode, cc0_rtx, operand0)); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_tstqi_1 (operand0) + rtx operand0; +{ + return gen_rtx (SET, VOIDmode, cc0_rtx, operand0); +} + +rtx +gen_tstqi (operand0) + rtx operand0; +{ + rtx operands[1]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + +{ + i386_compare_gen = gen_tstqi_1; + i386_compare_op0 = operands[0]; + DONE; +} + operand0 = operands[0]; + emit_insn (gen_rtx (SET, VOIDmode, cc0_rtx, operand0)); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_tstsf_cc (operand0) + rtx operand0; +{ + return gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2, + gen_rtx (SET, VOIDmode, cc0_rtx, operand0), + gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, HImode, 0)))); +} + +rtx +gen_tstsf (operand0) + rtx operand0; +{ + rtx operands[1]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + +{ + i386_compare_gen = gen_tstsf_cc; + i386_compare_op0 = operands[0]; + DONE; +} + operand0 = operands[0]; + emit (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2, + gen_rtx (SET, VOIDmode, cc0_rtx, operand0), + gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, HImode, 0))))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_tstdf_cc (operand0) + rtx operand0; +{ + return gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2, + gen_rtx (SET, VOIDmode, cc0_rtx, operand0), + gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, HImode, 0)))); +} + +rtx +gen_tstdf (operand0) + rtx operand0; +{ + rtx operands[1]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + +{ + i386_compare_gen = gen_tstdf_cc; + i386_compare_op0 = operands[0]; + DONE; +} + operand0 = operands[0]; + emit (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2, + gen_rtx (SET, VOIDmode, cc0_rtx, operand0), + gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, HImode, 0))))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_cmpsi_1 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, cc0_rtx, gen_rtx (COMPARE, VOIDmode, operand0, operand1)); +} + +rtx +gen_cmpsi (operand0, operand1) + rtx operand0; + rtx operand1; +{ + rtx operands[2]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; + +{ + if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) + operands[0] = force_reg (SImode, operands[0]); + + i386_compare_gen = gen_cmpsi_1; + i386_compare_op0 = operands[0]; + i386_compare_op1 = operands[1]; + DONE; +} + operand0 = operands[0]; + operand1 = operands[1]; + emit_insn (gen_rtx (SET, VOIDmode, cc0_rtx, gen_rtx (COMPARE, VOIDmode, operand0, operand1))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_cmphi_1 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, cc0_rtx, gen_rtx (COMPARE, VOIDmode, operand0, operand1)); +} + +rtx +gen_cmphi (operand0, operand1) + rtx operand0; + rtx operand1; +{ + rtx operands[2]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; + +{ + if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) + operands[0] = force_reg (HImode, operands[0]); + + i386_compare_gen = gen_cmphi_1; + i386_compare_op0 = operands[0]; + i386_compare_op1 = operands[1]; + DONE; +} + operand0 = operands[0]; + operand1 = operands[1]; + emit_insn (gen_rtx (SET, VOIDmode, cc0_rtx, gen_rtx (COMPARE, VOIDmode, operand0, operand1))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_cmpqi_1 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, cc0_rtx, gen_rtx (COMPARE, VOIDmode, operand0, operand1)); +} + +rtx +gen_cmpqi (operand0, operand1) + rtx operand0; + rtx operand1; +{ + rtx operands[2]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; + +{ + if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) + operands[0] = force_reg (QImode, operands[0]); + + i386_compare_gen = gen_cmpqi_1; + i386_compare_op0 = operands[0]; + i386_compare_op1 = operands[1]; + DONE; +} + operand0 = operands[0]; + operand1 = operands[1]; + emit_insn (gen_rtx (SET, VOIDmode, cc0_rtx, gen_rtx (COMPARE, VOIDmode, operand0, operand1))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_cmpsf_cc_1 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2, + gen_rtx (SET, VOIDmode, cc0_rtx, gen_rtx (GET_CODE (operand2), VOIDmode, + operand0, + operand1)), + gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, HImode, 0)))); +} + +rtx +gen_cmpdf (operand0, operand1) + rtx operand0; + rtx operand1; +{ + rtx operands[2]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; + +{ + i386_compare_gen = gen_cmpdf_cc; + i386_compare_gen_eq = gen_cmpdf_ccfpeq; + i386_compare_op0 = operands[0]; + i386_compare_op1 = operands[1]; + DONE; +} + operand0 = operands[0]; + operand1 = operands[1]; + emit_insn (gen_rtx (SET, VOIDmode, cc0_rtx, gen_rtx (COMPARE, VOIDmode, operand0, operand1))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_cmpsf (operand0, operand1) + rtx operand0; + rtx operand1; +{ + rtx operands[2]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; + +{ + i386_compare_gen = gen_cmpsf_cc; + i386_compare_gen_eq = gen_cmpsf_ccfpeq; + i386_compare_op0 = operands[0]; + i386_compare_op1 = operands[1]; + DONE; +} + operand0 = operands[0]; + operand1 = operands[1]; + emit_insn (gen_rtx (SET, VOIDmode, cc0_rtx, gen_rtx (COMPARE, VOIDmode, operand0, operand1))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_cmpdf_cc (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2, + gen_rtx (SET, VOIDmode, cc0_rtx, gen_rtx (COMPARE, VOIDmode, operand0, operand1)), + gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, HImode, 0)))); +} + +rtx +gen_cmpdf_ccfpeq (operand0, operand1) + rtx operand0; + rtx operand1; +{ + rtx operands[2]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; + +{ + if (! register_operand (operands[1], DFmode)) + operands[1] = copy_to_mode_reg (DFmode, operands[1]); +} + operand0 = operands[0]; + operand1 = operands[1]; + emit (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2, + gen_rtx (SET, VOIDmode, cc0_rtx, gen_rtx (COMPARE, CCFPEQmode, operand0, operand1)), + gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, HImode, 0))))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_cmpsf_cc (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2, + gen_rtx (SET, VOIDmode, cc0_rtx, gen_rtx (COMPARE, VOIDmode, operand0, operand1)), + gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, HImode, 0)))); +} + +rtx +gen_cmpsf_ccfpeq (operand0, operand1) + rtx operand0; + rtx operand1; +{ + rtx operands[2]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; + +{ + if (! register_operand (operands[1], SFmode)) + operands[1] = copy_to_mode_reg (SFmode, operands[1]); +} + operand0 = operands[0]; + operand1 = operands[1]; + emit (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2, + gen_rtx (SET, VOIDmode, cc0_rtx, gen_rtx (COMPARE, CCFPEQmode, operand0, operand1)), + gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, HImode, 0))))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_movsi (operand0, operand1) + rtx operand0; + rtx operand1; +{ + rtx operands[2]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; + +{ + extern int flag_pic; + + if (flag_pic && SYMBOLIC_CONST (operands[1])) + emit_pic_move (operands, SImode); +} + operand0 = operands[0]; + operand1 = operands[1]; + emit_insn (gen_rtx (SET, VOIDmode, operand0, operand1)); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_movhi (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, operand1); +} + +rtx +gen_movstricthi (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, gen_rtx (STRICT_LOW_PART, VOIDmode, operand0), operand1); +} + +rtx +gen_movqi (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, operand1); +} + +rtx +gen_movstrictqi (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, gen_rtx (STRICT_LOW_PART, VOIDmode, operand0), operand1); +} + +rtx +gen_movsf (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, operand1); +} + +rtx +gen_swapdf (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2, + gen_rtx (SET, VOIDmode, operand0, operand1), + gen_rtx (SET, VOIDmode, operand1, operand0))); +} + +rtx +gen_movdf (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, operand1); +} + +rtx +gen_movdi (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, operand1); +} + +rtx +gen_zero_extendhisi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (ZERO_EXTEND, SImode, operand1)); +} + +rtx +gen_zero_extendqihi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (ZERO_EXTEND, HImode, operand1)); +} + +rtx +gen_zero_extendqisi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (ZERO_EXTEND, SImode, operand1)); +} + +rtx +gen_zero_extendsidi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (ZERO_EXTEND, DImode, operand1)); +} + +rtx +gen_extendsidi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (SIGN_EXTEND, DImode, operand1)); +} + +rtx +gen_extendhisi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (SIGN_EXTEND, SImode, operand1)); +} + +rtx +gen_extendqihi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (SIGN_EXTEND, HImode, operand1)); +} + +rtx +gen_extendqisi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (SIGN_EXTEND, SImode, operand1)); +} + +rtx +gen_extendsfdf2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (FLOAT_EXTEND, DFmode, operand1)); +} + +rtx +gen_truncdfsf2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + rtx operand2; + rtx operands[3]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; + +{ + operands[2] = (rtx) assign_386_stack_local (SFmode, 0); +} + operand0 = operands[0]; + operand1 = operands[1]; + operand2 = operands[2]; + emit (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2, + gen_rtx (SET, VOIDmode, operand0, gen_rtx (FLOAT_TRUNCATE, SFmode, operand1)), + gen_rtx (CLOBBER, VOIDmode, operand2)))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_fixuns_truncdfsi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + rtx operand2; + rtx operand3; + rtx operand4; + rtx operand5; + rtx operand6; + rtx operands[7]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; + +{ + operands[2] = gen_reg_rtx (DImode); + operands[3] = gen_lowpart (SImode, operands[2]); + operands[4] = gen_reg_rtx (DFmode); + operands[5] = (rtx) assign_386_stack_local (SImode, 0); + operands[6] = (rtx) assign_386_stack_local (SImode, 1); +} + operand0 = operands[0]; + operand1 = operands[1]; + operand2 = operands[2]; + operand3 = operands[3]; + operand4 = operands[4]; + operand5 = operands[5]; + operand6 = operands[6]; + emit_insn (gen_rtx (SET, VOIDmode, operand4, operand1)); + emit (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (5, + gen_rtx (SET, VOIDmode, operand2, gen_rtx (FIX, DImode, gen_rtx (FIX, DFmode, operand4))), + gen_rtx (CLOBBER, VOIDmode, operand4), + gen_rtx (CLOBBER, VOIDmode, operand5), + gen_rtx (CLOBBER, VOIDmode, operand6), + gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, SImode, 0))))); + emit_insn (gen_rtx (SET, VOIDmode, operand0, operand3)); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_fixuns_truncsfsi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + rtx operand2; + rtx operand3; + rtx operand4; + rtx operand5; + rtx operand6; + rtx operands[7]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; + +{ + operands[2] = gen_reg_rtx (DImode); + operands[3] = gen_lowpart (SImode, operands[2]); + operands[4] = gen_reg_rtx (SFmode); + operands[5] = (rtx) assign_386_stack_local (SImode, 0); + operands[6] = (rtx) assign_386_stack_local (SImode, 1); +} + operand0 = operands[0]; + operand1 = operands[1]; + operand2 = operands[2]; + operand3 = operands[3]; + operand4 = operands[4]; + operand5 = operands[5]; + operand6 = operands[6]; + emit_insn (gen_rtx (SET, VOIDmode, operand4, operand1)); + emit (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (5, + gen_rtx (SET, VOIDmode, operand2, gen_rtx (FIX, DImode, gen_rtx (FIX, SFmode, operand4))), + gen_rtx (CLOBBER, VOIDmode, operand4), + gen_rtx (CLOBBER, VOIDmode, operand5), + gen_rtx (CLOBBER, VOIDmode, operand6), + gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, SImode, 0))))); + emit_insn (gen_rtx (SET, VOIDmode, operand0, operand3)); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_fix_truncdfdi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + rtx operand2; + rtx operand3; + rtx operand4; + rtx operands[5]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; + +{ + operands[1] = copy_to_mode_reg (DFmode, operands[1]); + operands[2] = gen_reg_rtx (DFmode); + operands[3] = (rtx) assign_386_stack_local (SImode, 0); + operands[4] = (rtx) assign_386_stack_local (SImode, 1); +} + operand0 = operands[0]; + operand1 = operands[1]; + operand2 = operands[2]; + operand3 = operands[3]; + operand4 = operands[4]; + emit_insn (gen_rtx (SET, VOIDmode, operand2, operand1)); + emit (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (5, + gen_rtx (SET, VOIDmode, operand0, gen_rtx (FIX, DImode, gen_rtx (FIX, DFmode, operand2))), + gen_rtx (CLOBBER, VOIDmode, operand2), + gen_rtx (CLOBBER, VOIDmode, operand3), + gen_rtx (CLOBBER, VOIDmode, operand4), + gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, SImode, 0))))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_fix_truncsfdi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + rtx operand2; + rtx operand3; + rtx operand4; + rtx operands[5]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; + +{ + operands[1] = copy_to_mode_reg (SFmode, operands[1]); + operands[2] = gen_reg_rtx (SFmode); + operands[3] = (rtx) assign_386_stack_local (SImode, 0); + operands[4] = (rtx) assign_386_stack_local (SImode, 1); +} + operand0 = operands[0]; + operand1 = operands[1]; + operand2 = operands[2]; + operand3 = operands[3]; + operand4 = operands[4]; + emit_insn (gen_rtx (SET, VOIDmode, operand2, operand1)); + emit (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (5, + gen_rtx (SET, VOIDmode, operand0, gen_rtx (FIX, DImode, gen_rtx (FIX, SFmode, operand2))), + gen_rtx (CLOBBER, VOIDmode, operand2), + gen_rtx (CLOBBER, VOIDmode, operand3), + gen_rtx (CLOBBER, VOIDmode, operand4), + gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, SImode, 0))))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_fix_truncdfsi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + rtx operand2; + rtx operand3; + rtx operands[4]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; + +{ + operands[2] = (rtx) assign_386_stack_local (SImode, 0); + operands[3] = (rtx) assign_386_stack_local (SImode, 1); +} + operand0 = operands[0]; + operand1 = operands[1]; + operand2 = operands[2]; + operand3 = operands[3]; + emit (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (4, + gen_rtx (SET, VOIDmode, operand0, gen_rtx (FIX, SImode, gen_rtx (FIX, DFmode, operand1))), + gen_rtx (CLOBBER, VOIDmode, operand2), + gen_rtx (CLOBBER, VOIDmode, operand3), + gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, SImode, 0))))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_fix_truncsfsi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + rtx operand2; + rtx operand3; + rtx operands[4]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; + +{ + operands[2] = (rtx) assign_386_stack_local (SImode, 0); + operands[3] = (rtx) assign_386_stack_local (SImode, 1); +} + operand0 = operands[0]; + operand1 = operands[1]; + operand2 = operands[2]; + operand3 = operands[3]; + emit (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (4, + gen_rtx (SET, VOIDmode, operand0, gen_rtx (FIX, SImode, gen_rtx (FIX, SFmode, operand1))), + gen_rtx (CLOBBER, VOIDmode, operand2), + gen_rtx (CLOBBER, VOIDmode, operand3), + gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, SImode, 0))))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_floatsisf2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (FLOAT, SFmode, operand1)); +} + +rtx +gen_floatdisf2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (FLOAT, SFmode, operand1)); +} + +rtx +gen_floatsidf2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (FLOAT, DFmode, operand1)); +} + +rtx +gen_floatdidf2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (FLOAT, DFmode, operand1)); +} + +rtx +gen_adddi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (PLUS, DImode, operand1, operand2)); +} + +rtx +gen_addsi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (PLUS, SImode, operand1, operand2)); +} + +rtx +gen_addhi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (PLUS, HImode, operand1, operand2)); +} + +rtx +gen_addqi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (PLUS, QImode, operand1, operand2)); +} + +rtx +gen_adddf3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (PLUS, DFmode, operand1, operand2)); +} + +rtx +gen_addsf3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (PLUS, SFmode, operand1, operand2)); +} + +rtx +gen_subdi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (MINUS, DImode, operand1, operand2)); +} + +rtx +gen_subsi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (MINUS, SImode, operand1, operand2)); +} + +rtx +gen_subhi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (MINUS, HImode, operand1, operand2)); +} + +rtx +gen_subqi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (MINUS, QImode, operand1, operand2)); +} + +rtx +gen_subdf3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (MINUS, DFmode, operand1, operand2)); +} + +rtx +gen_subsf3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (MINUS, SFmode, operand1, operand2)); +} + +rtx +gen_mulhi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (MULT, SImode, operand1, operand2)); +} + +rtx +gen_mulsi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (MULT, SImode, operand1, operand2)); +} + +rtx +gen_muldf3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (MULT, DFmode, operand1, operand2)); +} + +rtx +gen_mulsf3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (MULT, SFmode, operand1, operand2)); +} + +rtx +gen_divqi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (DIV, QImode, operand1, operand2)); +} + +rtx +gen_udivqi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (UDIV, QImode, operand1, operand2)); +} + +rtx +gen_divdf3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (DIV, DFmode, operand1, operand2)); +} + +rtx +gen_divsf3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (DIV, SFmode, operand1, operand2)); +} + +rtx +gen_divmodsi4 (operand0, operand1, operand2, operand3) + rtx operand0; + rtx operand1; + rtx operand2; + rtx operand3; +{ + return gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2, + gen_rtx (SET, VOIDmode, operand0, gen_rtx (DIV, SImode, operand1, operand2)), + gen_rtx (SET, VOIDmode, operand3, gen_rtx (MOD, SImode, operand1, operand2)))); +} + +rtx +gen_divmodhi4 (operand0, operand1, operand2, operand3) + rtx operand0; + rtx operand1; + rtx operand2; + rtx operand3; +{ + return gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2, + gen_rtx (SET, VOIDmode, operand0, gen_rtx (DIV, HImode, operand1, operand2)), + gen_rtx (SET, VOIDmode, operand3, gen_rtx (MOD, HImode, operand1, operand2)))); +} + +rtx +gen_udivmodsi4 (operand0, operand1, operand2, operand3) + rtx operand0; + rtx operand1; + rtx operand2; + rtx operand3; +{ + return gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2, + gen_rtx (SET, VOIDmode, operand0, gen_rtx (UDIV, SImode, operand1, operand2)), + gen_rtx (SET, VOIDmode, operand3, gen_rtx (UMOD, SImode, operand1, operand2)))); +} + +rtx +gen_udivmodhi4 (operand0, operand1, operand2, operand3) + rtx operand0; + rtx operand1; + rtx operand2; + rtx operand3; +{ + return gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2, + gen_rtx (SET, VOIDmode, operand0, gen_rtx (UDIV, HImode, operand1, operand2)), + gen_rtx (SET, VOIDmode, operand3, gen_rtx (UMOD, HImode, operand1, operand2)))); +} + +rtx +gen_andsi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (AND, SImode, operand1, operand2)); +} + +rtx +gen_andhi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (AND, HImode, operand1, operand2)); +} + +rtx +gen_andqi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (AND, QImode, operand1, operand2)); +} + +rtx +gen_iorsi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (IOR, SImode, operand1, operand2)); +} + +rtx +gen_iorhi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (IOR, HImode, operand1, operand2)); +} + +rtx +gen_iorqi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (IOR, QImode, operand1, operand2)); +} + +rtx +gen_xorsi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (XOR, SImode, operand1, operand2)); +} + +rtx +gen_xorhi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (XOR, HImode, operand1, operand2)); +} + +rtx +gen_xorqi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (XOR, QImode, operand1, operand2)); +} + +rtx +gen_negdi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (NEG, DImode, operand1)); +} + +rtx +gen_negsi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (NEG, SImode, operand1)); +} + +rtx +gen_neghi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (NEG, HImode, operand1)); +} + +rtx +gen_negqi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (NEG, QImode, operand1)); +} + +rtx +gen_negsf2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (NEG, SFmode, operand1)); +} + +rtx +gen_negdf2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (NEG, DFmode, operand1)); +} + +rtx +gen_abssf2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (ABS, SFmode, operand1)); +} + +rtx +gen_absdf2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (ABS, DFmode, operand1)); +} + +rtx +gen_sqrtsf2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (SQRT, SFmode, operand1)); +} + +rtx +gen_sqrtdf2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (SQRT, DFmode, operand1)); +} + +rtx +gen_sindf2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (UNSPEC, DFmode, gen_rtvec (1, + operand1), 1)); +} + +rtx +gen_sinsf2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (UNSPEC, SFmode, gen_rtvec (1, + operand1), 1)); +} + +rtx +gen_cosdf2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (UNSPEC, DFmode, gen_rtvec (1, + operand1), 2)); +} + +rtx +gen_cossf2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (UNSPEC, SFmode, gen_rtvec (1, + operand1), 2)); +} + +rtx +gen_one_cmplsi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (NOT, SImode, operand1)); +} + +rtx +gen_one_cmplhi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (NOT, HImode, operand1)); +} + +rtx +gen_one_cmplqi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (NOT, QImode, operand1)); +} + +rtx +gen_ashldi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + rtx operands[3]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; + operands[2] = operand2; + +{ + if (GET_CODE (operands[2]) != CONST_INT + || ! CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')) + { + operands[2] = copy_to_mode_reg (QImode, operands[2]); + emit_insn (gen_ashldi3_non_const_int (operands[0], operands[1], + operands[2])); + } + else + emit_insn (gen_ashldi3_const_int (operands[0], operands[1], operands[2])); + + DONE; +} + operand0 = operands[0]; + operand1 = operands[1]; + operand2 = operands[2]; + emit_insn (gen_rtx (SET, VOIDmode, operand0, gen_rtx (ASHIFT, DImode, operand1, operand2))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_ashldi3_const_int (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (ASHIFT, DImode, operand1, operand2)); +} + +rtx +gen_ashldi3_non_const_int (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2, + gen_rtx (SET, VOIDmode, operand0, gen_rtx (ASHIFT, DImode, operand1, operand2)), + gen_rtx (CLOBBER, VOIDmode, operand2))); +} + +rtx +gen_ashlsi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (ASHIFT, SImode, operand1, operand2)); +} + +rtx +gen_ashlhi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (ASHIFT, HImode, operand1, operand2)); +} + +rtx +gen_ashlqi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (ASHIFT, QImode, operand1, operand2)); +} + +rtx +gen_ashrdi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + rtx operands[3]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; + operands[2] = operand2; + +{ + if (GET_CODE (operands[2]) != CONST_INT + || ! CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')) + { + operands[2] = copy_to_mode_reg (QImode, operands[2]); + emit_insn (gen_ashrdi3_non_const_int (operands[0], operands[1], + operands[2])); + } + else + emit_insn (gen_ashrdi3_const_int (operands[0], operands[1], operands[2])); + + DONE; +} + operand0 = operands[0]; + operand1 = operands[1]; + operand2 = operands[2]; + emit_insn (gen_rtx (SET, VOIDmode, operand0, gen_rtx (ASHIFTRT, DImode, operand1, operand2))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_ashrdi3_const_int (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (ASHIFTRT, DImode, operand1, operand2)); +} + +rtx +gen_ashrdi3_non_const_int (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2, + gen_rtx (SET, VOIDmode, operand0, gen_rtx (ASHIFTRT, DImode, operand1, operand2)), + gen_rtx (CLOBBER, VOIDmode, operand2))); +} + +rtx +gen_ashrsi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (ASHIFTRT, SImode, operand1, operand2)); +} + +rtx +gen_ashrhi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (ASHIFTRT, HImode, operand1, operand2)); +} + +rtx +gen_ashrqi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (ASHIFTRT, QImode, operand1, operand2)); +} + +rtx +gen_lshrdi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + rtx operands[3]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; + operands[2] = operand2; + +{ + if (GET_CODE (operands[2]) != CONST_INT + || ! CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')) + { + operands[2] = copy_to_mode_reg (QImode, operands[2]); + emit_insn (gen_lshrdi3_non_const_int (operands[0], operands[1], + operands[2])); + } + else + emit_insn (gen_lshrdi3_const_int (operands[0], operands[1], operands[2])); + + DONE; +} + operand0 = operands[0]; + operand1 = operands[1]; + operand2 = operands[2]; + emit_insn (gen_rtx (SET, VOIDmode, operand0, gen_rtx (LSHIFTRT, DImode, operand1, operand2))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_lshrdi3_const_int (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (LSHIFTRT, DImode, operand1, operand2)); +} + +rtx +gen_lshrdi3_non_const_int (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2, + gen_rtx (SET, VOIDmode, operand0, gen_rtx (LSHIFTRT, DImode, operand1, operand2)), + gen_rtx (CLOBBER, VOIDmode, operand2))); +} + +rtx +gen_lshrsi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (LSHIFTRT, SImode, operand1, operand2)); +} + +rtx +gen_lshrhi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (LSHIFTRT, HImode, operand1, operand2)); +} + +rtx +gen_lshrqi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (LSHIFTRT, QImode, operand1, operand2)); +} + +rtx +gen_rotlsi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (ROTATE, SImode, operand1, operand2)); +} + +rtx +gen_rotlhi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (ROTATE, HImode, operand1, operand2)); +} + +rtx +gen_rotlqi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (ROTATE, QImode, operand1, operand2)); +} + +rtx +gen_rotrsi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (ROTATERT, SImode, operand1, operand2)); +} + +rtx +gen_rotrhi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (ROTATERT, HImode, operand1, operand2)); +} + +rtx +gen_rotrqi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (ROTATERT, QImode, operand1, operand2)); +} + +rtx +gen_seq (operand0) + rtx operand0; +{ + rtx operand1; + rtx operands[2]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + +{ + if (TARGET_IEEE_FP + && GET_MODE_CLASS (GET_MODE (i386_compare_op0)) == MODE_FLOAT) + operands[1] = (*i386_compare_gen_eq)(i386_compare_op0, i386_compare_op1); + else + operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1); +} + operand0 = operands[0]; + operand1 = operands[1]; + emit (operand1); + emit_insn (gen_rtx (SET, VOIDmode, operand0, gen_rtx (EQ, QImode, cc0_rtx, const0_rtx))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_sne (operand0) + rtx operand0; +{ + rtx operand1; + rtx operands[2]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + +{ + if (TARGET_IEEE_FP + && GET_MODE_CLASS (GET_MODE (i386_compare_op0)) == MODE_FLOAT) + operands[1] = (*i386_compare_gen_eq)(i386_compare_op0, i386_compare_op1); + else + operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1); +} + operand0 = operands[0]; + operand1 = operands[1]; + emit (operand1); + emit_insn (gen_rtx (SET, VOIDmode, operand0, gen_rtx (NE, QImode, cc0_rtx, const0_rtx))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_sgt (operand0) + rtx operand0; +{ + rtx operand1; + rtx operands[2]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; +operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1); + operand0 = operands[0]; + operand1 = operands[1]; + emit (operand1); + emit_insn (gen_rtx (SET, VOIDmode, operand0, gen_rtx (GT, QImode, cc0_rtx, const0_rtx))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_sgtu (operand0) + rtx operand0; +{ + rtx operand1; + rtx operands[2]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; +operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1); + operand0 = operands[0]; + operand1 = operands[1]; + emit (operand1); + emit_insn (gen_rtx (SET, VOIDmode, operand0, gen_rtx (GTU, QImode, cc0_rtx, const0_rtx))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_slt (operand0) + rtx operand0; +{ + rtx operand1; + rtx operands[2]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; +operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1); + operand0 = operands[0]; + operand1 = operands[1]; + emit (operand1); + emit_insn (gen_rtx (SET, VOIDmode, operand0, gen_rtx (LT, QImode, cc0_rtx, const0_rtx))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_sltu (operand0) + rtx operand0; +{ + rtx operand1; + rtx operands[2]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; +operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1); + operand0 = operands[0]; + operand1 = operands[1]; + emit (operand1); + emit_insn (gen_rtx (SET, VOIDmode, operand0, gen_rtx (LTU, QImode, cc0_rtx, const0_rtx))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_sge (operand0) + rtx operand0; +{ + rtx operand1; + rtx operands[2]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; +operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1); + operand0 = operands[0]; + operand1 = operands[1]; + emit (operand1); + emit_insn (gen_rtx (SET, VOIDmode, operand0, gen_rtx (GE, QImode, cc0_rtx, const0_rtx))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_sgeu (operand0) + rtx operand0; +{ + rtx operand1; + rtx operands[2]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; +operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1); + operand0 = operands[0]; + operand1 = operands[1]; + emit (operand1); + emit_insn (gen_rtx (SET, VOIDmode, operand0, gen_rtx (GEU, QImode, cc0_rtx, const0_rtx))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_sle (operand0) + rtx operand0; +{ + rtx operand1; + rtx operands[2]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; +operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1); + operand0 = operands[0]; + operand1 = operands[1]; + emit (operand1); + emit_insn (gen_rtx (SET, VOIDmode, operand0, gen_rtx (LE, QImode, cc0_rtx, const0_rtx))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_sleu (operand0) + rtx operand0; +{ + rtx operand1; + rtx operands[2]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; +operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1); + operand0 = operands[0]; + operand1 = operands[1]; + emit (operand1); + emit_insn (gen_rtx (SET, VOIDmode, operand0, gen_rtx (LEU, QImode, cc0_rtx, const0_rtx))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_beq (operand0) + rtx operand0; +{ + rtx operand1; + rtx operands[2]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + +{ + if (TARGET_IEEE_FP + && GET_MODE_CLASS (GET_MODE (i386_compare_op0)) == MODE_FLOAT) + operands[1] = (*i386_compare_gen_eq)(i386_compare_op0, i386_compare_op1); + else + operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1); +} + operand0 = operands[0]; + operand1 = operands[1]; + emit (operand1); + emit_jump_insn (gen_rtx (SET, VOIDmode, pc_rtx, gen_rtx (IF_THEN_ELSE, VOIDmode, gen_rtx (EQ, VOIDmode, cc0_rtx, const0_rtx), gen_rtx (LABEL_REF, VOIDmode, operand0), pc_rtx))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_bne (operand0) + rtx operand0; +{ + rtx operand1; + rtx operands[2]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + +{ + if (TARGET_IEEE_FP + && GET_MODE_CLASS (GET_MODE (i386_compare_op0)) == MODE_FLOAT) + operands[1] = (*i386_compare_gen_eq)(i386_compare_op0, i386_compare_op1); + else + operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1); +} + operand0 = operands[0]; + operand1 = operands[1]; + emit (operand1); + emit_jump_insn (gen_rtx (SET, VOIDmode, pc_rtx, gen_rtx (IF_THEN_ELSE, VOIDmode, gen_rtx (NE, VOIDmode, cc0_rtx, const0_rtx), gen_rtx (LABEL_REF, VOIDmode, operand0), pc_rtx))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_bgt (operand0) + rtx operand0; +{ + rtx operand1; + rtx operands[2]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; +operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1); + operand0 = operands[0]; + operand1 = operands[1]; + emit (operand1); + emit_jump_insn (gen_rtx (SET, VOIDmode, pc_rtx, gen_rtx (IF_THEN_ELSE, VOIDmode, gen_rtx (GT, VOIDmode, cc0_rtx, const0_rtx), gen_rtx (LABEL_REF, VOIDmode, operand0), pc_rtx))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_bgtu (operand0) + rtx operand0; +{ + rtx operand1; + rtx operands[2]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; +operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1); + operand0 = operands[0]; + operand1 = operands[1]; + emit (operand1); + emit_jump_insn (gen_rtx (SET, VOIDmode, pc_rtx, gen_rtx (IF_THEN_ELSE, VOIDmode, gen_rtx (GTU, VOIDmode, cc0_rtx, const0_rtx), gen_rtx (LABEL_REF, VOIDmode, operand0), pc_rtx))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_blt (operand0) + rtx operand0; +{ + rtx operand1; + rtx operands[2]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; +operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1); + operand0 = operands[0]; + operand1 = operands[1]; + emit (operand1); + emit_jump_insn (gen_rtx (SET, VOIDmode, pc_rtx, gen_rtx (IF_THEN_ELSE, VOIDmode, gen_rtx (LT, VOIDmode, cc0_rtx, const0_rtx), gen_rtx (LABEL_REF, VOIDmode, operand0), pc_rtx))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_bltu (operand0) + rtx operand0; +{ + rtx operand1; + rtx operands[2]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; +operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1); + operand0 = operands[0]; + operand1 = operands[1]; + emit (operand1); + emit_jump_insn (gen_rtx (SET, VOIDmode, pc_rtx, gen_rtx (IF_THEN_ELSE, VOIDmode, gen_rtx (LTU, VOIDmode, cc0_rtx, const0_rtx), gen_rtx (LABEL_REF, VOIDmode, operand0), pc_rtx))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_bge (operand0) + rtx operand0; +{ + rtx operand1; + rtx operands[2]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; +operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1); + operand0 = operands[0]; + operand1 = operands[1]; + emit (operand1); + emit_jump_insn (gen_rtx (SET, VOIDmode, pc_rtx, gen_rtx (IF_THEN_ELSE, VOIDmode, gen_rtx (GE, VOIDmode, cc0_rtx, const0_rtx), gen_rtx (LABEL_REF, VOIDmode, operand0), pc_rtx))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_bgeu (operand0) + rtx operand0; +{ + rtx operand1; + rtx operands[2]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; +operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1); + operand0 = operands[0]; + operand1 = operands[1]; + emit (operand1); + emit_jump_insn (gen_rtx (SET, VOIDmode, pc_rtx, gen_rtx (IF_THEN_ELSE, VOIDmode, gen_rtx (GEU, VOIDmode, cc0_rtx, const0_rtx), gen_rtx (LABEL_REF, VOIDmode, operand0), pc_rtx))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_ble (operand0) + rtx operand0; +{ + rtx operand1; + rtx operands[2]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; +operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1); + operand0 = operands[0]; + operand1 = operands[1]; + emit (operand1); + emit_jump_insn (gen_rtx (SET, VOIDmode, pc_rtx, gen_rtx (IF_THEN_ELSE, VOIDmode, gen_rtx (LE, VOIDmode, cc0_rtx, const0_rtx), gen_rtx (LABEL_REF, VOIDmode, operand0), pc_rtx))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_bleu (operand0) + rtx operand0; +{ + rtx operand1; + rtx operands[2]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; +operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1); + operand0 = operands[0]; + operand1 = operands[1]; + emit (operand1); + emit_jump_insn (gen_rtx (SET, VOIDmode, pc_rtx, gen_rtx (IF_THEN_ELSE, VOIDmode, gen_rtx (LEU, VOIDmode, cc0_rtx, const0_rtx), gen_rtx (LABEL_REF, VOIDmode, operand0), pc_rtx))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_jump (operand0) + rtx operand0; +{ + return gen_rtx (SET, VOIDmode, pc_rtx, gen_rtx (LABEL_REF, VOIDmode, operand0)); +} + +rtx +gen_indirect_jump (operand0) + rtx operand0; +{ + return gen_rtx (SET, VOIDmode, pc_rtx, operand0); +} + +rtx +gen_casesi (operand0, operand1, operand2, operand3, operand4) + rtx operand0; + rtx operand1; + rtx operand2; + rtx operand3; + rtx operand4; +{ + rtx operand5; + rtx operands[6]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; + operands[2] = operand2; + operands[3] = operand3; + operands[4] = operand4; + +{ + operands[5] = gen_reg_rtx (SImode); + current_function_uses_pic_offset_table = 1; +} + operand0 = operands[0]; + operand1 = operands[1]; + operand2 = operands[2]; + operand3 = operands[3]; + operand4 = operands[4]; + operand5 = operands[5]; + emit_insn (gen_rtx (SET, VOIDmode, operand5, gen_rtx (MINUS, SImode, operand0, operand1))); + emit_insn (gen_rtx (SET, VOIDmode, cc0_rtx, gen_rtx (COMPARE, CCmode, operand5, operand2))); + emit_jump_insn (gen_rtx (SET, VOIDmode, pc_rtx, gen_rtx (IF_THEN_ELSE, VOIDmode, gen_rtx (GTU, VOIDmode, cc0_rtx, const0_rtx), gen_rtx (LABEL_REF, VOIDmode, operand4), pc_rtx))); + emit_jump_insn (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2, + gen_rtx (SET, VOIDmode, pc_rtx, gen_rtx (MINUS, SImode, gen_rtx (REG, SImode, 3), gen_rtx (MEM, SImode, gen_rtx (PLUS, SImode, gen_rtx (MULT, SImode, operand5, GEN_INT (4)), gen_rtx (LABEL_REF, VOIDmode, operand3))))), + gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, SImode, 0))))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_tablejump (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2, + gen_rtx (SET, VOIDmode, pc_rtx, operand0), + gen_rtx (USE, VOIDmode, gen_rtx (LABEL_REF, VOIDmode, operand1)))); +} + +rtx +gen_call_pop (operand0, operand1, operand2, operand3) + rtx operand0; + rtx operand1; + rtx operand2; + rtx operand3; +{ + rtx operands[4]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; + operands[2] = operand2; + operands[3] = operand3; + +{ + rtx addr; + + if (flag_pic) + current_function_uses_pic_offset_table = 1; + + /* With half-pic, force the address into a register. */ + addr = XEXP (operands[0], 0); + if (GET_CODE (addr) != REG && HALF_PIC_P () && !CONSTANT_ADDRESS_P (addr)) + XEXP (operands[0], 0) = force_reg (Pmode, addr); + + if (! expander_call_insn_operand (operands[0], QImode)) + operands[0] + = change_address (operands[0], VOIDmode, + copy_to_mode_reg (Pmode, XEXP (operands[0], 0))); +} + operand0 = operands[0]; + operand1 = operands[1]; + operand2 = operands[2]; + operand3 = operands[3]; + emit_call_insn (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2, + gen_rtx (CALL, VOIDmode, operand0, operand1), + gen_rtx (SET, VOIDmode, gen_rtx (REG, SImode, 7), gen_rtx (PLUS, SImode, gen_rtx (REG, SImode, 7), operand3))))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_call (operand0, operand1) + rtx operand0; + rtx operand1; +{ + rtx operands[2]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; + +{ + rtx addr; + + if (flag_pic) + current_function_uses_pic_offset_table = 1; + + /* With half-pic, force the address into a register. */ + addr = XEXP (operands[0], 0); + if (GET_CODE (addr) != REG && HALF_PIC_P () && !CONSTANT_ADDRESS_P (addr)) + XEXP (operands[0], 0) = force_reg (Pmode, addr); + + if (! expander_call_insn_operand (operands[0], QImode)) + operands[0] + = change_address (operands[0], VOIDmode, + copy_to_mode_reg (Pmode, XEXP (operands[0], 0))); +} + operand0 = operands[0]; + operand1 = operands[1]; + emit_call_insn (gen_rtx (CALL, VOIDmode, operand0, operand1)); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_call_value_pop (operand0, operand1, operand2, operand3, operand4) + rtx operand0; + rtx operand1; + rtx operand2; + rtx operand3; + rtx operand4; +{ + rtx operands[5]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; + operands[2] = operand2; + operands[3] = operand3; + operands[4] = operand4; + +{ + rtx addr; + + if (flag_pic) + current_function_uses_pic_offset_table = 1; + + /* With half-pic, force the address into a register. */ + addr = XEXP (operands[1], 0); + if (GET_CODE (addr) != REG && HALF_PIC_P () && !CONSTANT_ADDRESS_P (addr)) + XEXP (operands[1], 0) = force_reg (Pmode, addr); + + if (! expander_call_insn_operand (operands[1], QImode)) + operands[1] + = change_address (operands[1], VOIDmode, + copy_to_mode_reg (Pmode, XEXP (operands[1], 0))); +} + operand0 = operands[0]; + operand1 = operands[1]; + operand2 = operands[2]; + operand3 = operands[3]; + operand4 = operands[4]; + emit_call_insn (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2, + gen_rtx (SET, VOIDmode, operand0, gen_rtx (CALL, VOIDmode, operand1, operand2)), + gen_rtx (SET, VOIDmode, gen_rtx (REG, SImode, 7), gen_rtx (PLUS, SImode, gen_rtx (REG, SImode, 7), operand4))))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_call_value (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + rtx operands[3]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; + operands[2] = operand2; + +{ + rtx addr; + + if (flag_pic) + current_function_uses_pic_offset_table = 1; + + /* With half-pic, force the address into a register. */ + addr = XEXP (operands[1], 0); + if (GET_CODE (addr) != REG && HALF_PIC_P () && !CONSTANT_ADDRESS_P (addr)) + XEXP (operands[1], 0) = force_reg (Pmode, addr); + + if (! expander_call_insn_operand (operands[1], QImode)) + operands[1] + = change_address (operands[1], VOIDmode, + copy_to_mode_reg (Pmode, XEXP (operands[1], 0))); +} + operand0 = operands[0]; + operand1 = operands[1]; + operand2 = operands[2]; + emit_call_insn (gen_rtx (SET, VOIDmode, operand0, gen_rtx (CALL, VOIDmode, operand1, operand2))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_untyped_call (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + rtx operands[3]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; + operands[2] = operand2; + +{ + rtx addr; + + if (flag_pic) + current_function_uses_pic_offset_table = 1; + + /* With half-pic, force the address into a register. */ + addr = XEXP (operands[0], 0); + if (GET_CODE (addr) != REG && HALF_PIC_P () && !CONSTANT_ADDRESS_P (addr)) + XEXP (operands[0], 0) = force_reg (Pmode, addr); + + operands[1] = change_address (operands[1], DImode, XEXP (operands[1], 0)); + if (! expander_call_insn_operand (operands[1], QImode)) + operands[1] + = change_address (operands[1], VOIDmode, + copy_to_mode_reg (Pmode, XEXP (operands[1], 0))); +} + operand0 = operands[0]; + operand1 = operands[1]; + operand2 = operands[2]; + emit_call_insn (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (3, + gen_rtx (CALL, VOIDmode, operand0, const0_rtx), + operand1, + operand2))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_untyped_return (operand0, operand1) + rtx operand0; + rtx operand1; +{ + rtx operands[2]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; + +{ + rtx valreg1 = gen_rtx (REG, SImode, 0); + rtx valreg2 = gen_rtx (REG, SImode, 1); + rtx result = operands[0]; + + /* Restore the FPU state. */ + emit_insn (gen_update_return (change_address (result, SImode, + plus_constant (XEXP (result, 0), + 8)))); + + /* Reload the function value registers. */ + emit_move_insn (valreg1, change_address (result, SImode, XEXP (result, 0))); + emit_move_insn (valreg2, + change_address (result, SImode, + plus_constant (XEXP (result, 0), 4))); + + /* Put USE insns before the return. */ + emit_insn (gen_rtx (USE, VOIDmode, valreg1)); + emit_insn (gen_rtx (USE, VOIDmode, valreg2)); + + /* Construct the return. */ + expand_null_return (); + + DONE; +} + operand0 = operands[0]; + operand1 = operands[1]; + emit (operand0); + emit (operand1); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_update_return (operand0) + rtx operand0; +{ + return gen_rtx (UNSPEC, SImode, gen_rtvec (1, + operand0), 0); +} + +rtx +gen_return () +{ + return gen_rtx (RETURN, VOIDmode); +} + +rtx +gen_nop () +{ + return const0_rtx; +} + +rtx +gen_movstrsi (operand0, operand1, operand2, operand3) + rtx operand0; + rtx operand1; + rtx operand2; + rtx operand3; +{ + rtx operand4; + rtx operand5; + rtx operand6; + rtx operands[7]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; + operands[2] = operand2; + operands[3] = operand3; + +{ + rtx addr0, addr1; + + if (GET_CODE (operands[2]) != CONST_INT) + FAIL; + + addr0 = copy_to_mode_reg (Pmode, XEXP (operands[0], 0)); + addr1 = copy_to_mode_reg (Pmode, XEXP (operands[1], 0)); + + operands[5] = addr0; + operands[6] = addr1; + + operands[0] = gen_rtx (MEM, BLKmode, addr0); + operands[1] = gen_rtx (MEM, BLKmode, addr1); +} + operand0 = operands[0]; + operand1 = operands[1]; + operand2 = operands[2]; + operand3 = operands[3]; + operand4 = operands[4]; + operand5 = operands[5]; + operand6 = operands[6]; + emit (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (6, + gen_rtx (SET, VOIDmode, operand0, operand1), + gen_rtx (USE, VOIDmode, operand2), + gen_rtx (USE, VOIDmode, operand3), + gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, SImode, 0)), + gen_rtx (CLOBBER, VOIDmode, operand5), + gen_rtx (CLOBBER, VOIDmode, operand6)))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_cmpstrsi (operand0, operand1, operand2, operand3, operand4) + rtx operand0; + rtx operand1; + rtx operand2; + rtx operand3; + rtx operand4; +{ + rtx operand5; + rtx operand6; + rtx operands[7]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; + operands[2] = operand2; + operands[3] = operand3; + operands[4] = operand4; + +{ + rtx addr1, addr2; + + addr1 = copy_to_mode_reg (Pmode, XEXP (operands[1], 0)); + addr2 = copy_to_mode_reg (Pmode, XEXP (operands[2], 0)); + operands[3] = copy_to_mode_reg (SImode, operands[3]); + + operands[5] = addr1; + operands[6] = addr2; + + operands[1] = gen_rtx (MEM, BLKmode, addr1); + operands[2] = gen_rtx (MEM, BLKmode, addr2); + +} + operand0 = operands[0]; + operand1 = operands[1]; + operand2 = operands[2]; + operand3 = operands[3]; + operand4 = operands[4]; + operand5 = operands[5]; + operand6 = operands[6]; + emit (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (6, + gen_rtx (SET, VOIDmode, operand0, gen_rtx (COMPARE, SImode, operand1, operand2)), + gen_rtx (USE, VOIDmode, operand3), + gen_rtx (USE, VOIDmode, operand4), + gen_rtx (CLOBBER, VOIDmode, operand5), + gen_rtx (CLOBBER, VOIDmode, operand6), + gen_rtx (CLOBBER, VOIDmode, operand3)))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_ffssi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + rtx operand2; + rtx operand3; + rtx operands[4]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; +operands[3] = gen_reg_rtx (SImode); + operand0 = operands[0]; + operand1 = operands[1]; + operand2 = operands[2]; + operand3 = operands[3]; + emit (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2, + gen_rtx (SET, VOIDmode, operand3, gen_rtx (PLUS, SImode, gen_rtx (FFS, SImode, operand1), constm1_rtx)), + gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, SImode, 0))))); + emit_insn (gen_rtx (SET, VOIDmode, operand0, gen_rtx (PLUS, SImode, operand3, const1_rtx))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_ffshi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + rtx operand2; + rtx operand3; + rtx operands[4]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; +operands[3] = gen_reg_rtx (HImode); + operand0 = operands[0]; + operand1 = operands[1]; + operand2 = operands[2]; + operand3 = operands[3]; + emit (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2, + gen_rtx (SET, VOIDmode, operand3, gen_rtx (PLUS, HImode, gen_rtx (FFS, HImode, operand1), constm1_rtx)), + gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, HImode, 0))))); + emit_insn (gen_rtx (SET, VOIDmode, operand0, gen_rtx (PLUS, HImode, operand3, const1_rtx))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_strlensi (operand0, operand1, operand2, operand3) + rtx operand0; + rtx operand1; + rtx operand2; + rtx operand3; +{ + rtx operand4; + rtx operand5; + rtx operands[6]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; + operands[2] = operand2; + operands[3] = operand3; + +{ + operands[1] = copy_to_mode_reg (SImode, XEXP (operands[1], 0)); + operands[4] = gen_reg_rtx (SImode); + operands[5] = gen_reg_rtx (SImode); +} + operand0 = operands[0]; + operand1 = operands[1]; + operand2 = operands[2]; + operand3 = operands[3]; + operand4 = operands[4]; + operand5 = operands[5]; + emit (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2, + gen_rtx (SET, VOIDmode, operand4, gen_rtx (UNSPEC, SImode, gen_rtvec (3, + gen_rtx (MEM, BLKmode, operand1), + operand2, + operand3), 0)), + gen_rtx (CLOBBER, VOIDmode, operand1)))); + emit_insn (gen_rtx (SET, VOIDmode, operand5, gen_rtx (NOT, SImode, operand4))); + emit_insn (gen_rtx (SET, VOIDmode, operand0, gen_rtx (MINUS, SImode, operand5, const1_rtx))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + + + +void +add_clobbers (pattern, insn_code_number) + rtx pattern; + int insn_code_number; +{ + int i; + + switch (insn_code_number) + { + case 250: + case 223: + XVECEXP (pattern, 0, 1) = gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, SImode, 0)); + break; + + case 72: + case 71: + XVECEXP (pattern, 0, 3) = gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, SImode, 0)); + break; + + case 68: + case 67: + XVECEXP (pattern, 0, 4) = gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, SImode, 0)); + break; + + case 252: + case 25: + case 24: + case 23: + case 22: + case 21: + case 20: + case 19: + case 18: + case 17: + case 16: + case 8: + case 6: + XVECEXP (pattern, 0, 1) = gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, HImode, 0)); + break; + + default: + abort (); + } +} + +void +init_mov_optab () +{ +#ifdef HAVE_movccfpeq + if (HAVE_movccfpeq) + mov_optab->handlers[(int) CCFPEQmode].insn_code = CODE_FOR_movccfpeq; +#endif +} diff --git a/gnu/usr.bin/gcc2/i386/insn-extract.c b/gnu/usr.bin/gcc2/i386/insn-extract.c new file mode 100644 index 00000000000..f645b830af8 --- /dev/null +++ b/gnu/usr.bin/gcc2/i386/insn-extract.c @@ -0,0 +1,505 @@ +/* Generated automatically by the program `genextract' +from the machine description file `md'. */ + +#include "config.h" +#include "rtl.h" + +static rtx junk; +extern rtx recog_operand[]; +extern rtx *recog_operand_loc[]; +extern rtx *recog_dup_loc[]; +extern char recog_dup_num[]; +extern +#ifdef __GNUC__ +__volatile__ +#endif +void fatal_insn_not_found (); + +void +insn_extract (insn) + rtx insn; +{ + register rtx *ro = recog_operand; + register rtx **ro_loc = recog_operand_loc; + rtx pat = PATTERN (insn); + switch (INSN_CODE (insn)) + { + case -1: + fatal_insn_not_found (insn); + + case 262: + ro[0] = *(ro_loc[0] = &XEXP (XVECEXP (pat, 0, 0), 0)); + ro[1] = *(ro_loc[1] = &XEXP (XVECEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0, 0), 0)); + ro[2] = *(ro_loc[2] = &XVECEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0, 1)); + ro[3] = *(ro_loc[3] = &XVECEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0, 2)); + recog_dup_loc[0] = &XEXP (XVECEXP (pat, 0, 1), 0); + recog_dup_num[0] = 1; + break; + + case 260: + case 257: + case 256: + ro[0] = *(ro_loc[0] = &XEXP (pat, 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (pat, 1), 0)); + ro[2] = *(ro_loc[2] = &XEXP (XEXP (XEXP (pat, 1), 1), 0)); + ro[3] = *(ro_loc[3] = &XEXP (pat, 1)); + break; + + case 259: + case 255: + case 254: + ro[0] = *(ro_loc[0] = &XEXP (pat, 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (XEXP (pat, 1), 0), 0)); + ro[2] = *(ro_loc[2] = &XEXP (XEXP (pat, 1), 1)); + ro[3] = *(ro_loc[3] = &XEXP (pat, 1)); + break; + + case 258: + case 253: + ro[0] = *(ro_loc[0] = &XEXP (pat, 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (pat, 1), 0)); + ro[2] = *(ro_loc[2] = &XEXP (XEXP (pat, 1), 1)); + ro[3] = *(ro_loc[3] = &XEXP (pat, 1)); + break; + + case 252: + case 250: + ro[0] = *(ro_loc[0] = &XEXP (XVECEXP (pat, 0, 0), 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0), 0)); + ro[2] = *(ro_loc[2] = &XEXP (XVECEXP (pat, 0, 1), 0)); + break; + + case 248: + ro[0] = *(ro_loc[0] = &XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0), 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 1), 0)); + ro[2] = *(ro_loc[2] = &XEXP (XVECEXP (pat, 0, 1), 0)); + ro[3] = *(ro_loc[3] = &XEXP (XVECEXP (pat, 0, 2), 0)); + recog_dup_loc[0] = &XEXP (XVECEXP (pat, 0, 5), 0); + recog_dup_num[0] = 2; + recog_dup_loc[1] = &XEXP (XVECEXP (pat, 0, 4), 0); + recog_dup_num[1] = 1; + recog_dup_loc[2] = &XEXP (XVECEXP (pat, 0, 3), 0); + recog_dup_num[2] = 0; + break; + + case 247: + ro[0] = *(ro_loc[0] = &XEXP (XVECEXP (pat, 0, 0), 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0), 0)); + ro[2] = *(ro_loc[2] = &XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 1), 0)); + ro[3] = *(ro_loc[3] = &XEXP (XVECEXP (pat, 0, 1), 0)); + ro[4] = *(ro_loc[4] = &XEXP (XVECEXP (pat, 0, 2), 0)); + recog_dup_loc[0] = &XEXP (XVECEXP (pat, 0, 5), 0); + recog_dup_num[0] = 3; + recog_dup_loc[1] = &XEXP (XVECEXP (pat, 0, 4), 0); + recog_dup_num[1] = 2; + recog_dup_loc[2] = &XEXP (XVECEXP (pat, 0, 3), 0); + recog_dup_num[2] = 1; + break; + + case 245: + ro[0] = *(ro_loc[0] = &XEXP (XEXP (XVECEXP (pat, 0, 0), 0), 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0)); + ro[2] = *(ro_loc[2] = &XEXP (XVECEXP (pat, 0, 1), 0)); + ro[3] = *(ro_loc[3] = &XEXP (XVECEXP (pat, 0, 2), 0)); + ro[4] = *(ro_loc[4] = &XEXP (XVECEXP (pat, 0, 3), 0)); + recog_dup_loc[0] = &XEXP (XVECEXP (pat, 0, 5), 0); + recog_dup_num[0] = 1; + recog_dup_loc[1] = &XEXP (XVECEXP (pat, 0, 4), 0); + recog_dup_num[1] = 0; + break; + + case 243: + case 242: + break; + + case 241: + ro[0] = *(ro_loc[0] = &XVECEXP (pat, 0, 0)); + break; + + case 239: + ro[0] = *(ro_loc[0] = &XEXP (XEXP (XVECEXP (pat, 0, 0), 0), 0)); + ro[1] = *(ro_loc[1] = &XVECEXP (pat, 0, 1)); + ro[2] = *(ro_loc[2] = &XVECEXP (pat, 0, 2)); + break; + + case 238: + ro[0] = *(ro_loc[0] = &XEXP (XVECEXP (pat, 0, 0), 0)); + ro[1] = *(ro_loc[1] = &XVECEXP (pat, 0, 1)); + ro[2] = *(ro_loc[2] = &XVECEXP (pat, 0, 2)); + break; + + case 236: + ro[0] = *(ro_loc[0] = &XEXP (pat, 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (XEXP (pat, 1), 0), 0)); + ro[2] = *(ro_loc[2] = &XEXP (XEXP (pat, 1), 1)); + break; + + case 233: + ro[0] = *(ro_loc[0] = &XEXP (XVECEXP (pat, 0, 0), 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0), 0)); + ro[2] = *(ro_loc[2] = &XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 1)); + ro[3] = const0_rtx; + ro_loc[3] = &junk; + ro[4] = *(ro_loc[4] = &XEXP (XEXP (XVECEXP (pat, 0, 1), 1), 1)); + break; + + case 232: + ro[0] = *(ro_loc[0] = &XEXP (XVECEXP (pat, 0, 0), 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0)); + ro[2] = *(ro_loc[2] = &XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 1)); + ro[3] = const0_rtx; + ro_loc[3] = &junk; + ro[4] = *(ro_loc[4] = &XEXP (XEXP (XVECEXP (pat, 0, 1), 1), 1)); + break; + + case 227: + ro[0] = *(ro_loc[0] = &XEXP (XEXP (XVECEXP (pat, 0, 0), 0), 0)); + ro[1] = *(ro_loc[1] = &XEXP (XVECEXP (pat, 0, 0), 1)); + ro[2] = const0_rtx; + ro_loc[2] = &junk; + ro[3] = *(ro_loc[3] = &XEXP (XEXP (XVECEXP (pat, 0, 1), 1), 1)); + break; + + case 226: + ro[0] = *(ro_loc[0] = &XEXP (XVECEXP (pat, 0, 0), 0)); + ro[1] = *(ro_loc[1] = &XEXP (XVECEXP (pat, 0, 0), 1)); + ro[2] = const0_rtx; + ro_loc[2] = &junk; + ro[3] = *(ro_loc[3] = &XEXP (XEXP (XVECEXP (pat, 0, 1), 1), 1)); + break; + + case 224: + ro[0] = *(ro_loc[0] = &XEXP (XVECEXP (pat, 0, 0), 1)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (XVECEXP (pat, 0, 1), 0), 0)); + break; + + case 223: + ro[0] = *(ro_loc[0] = &XEXP (XEXP (XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 1), 0), 0), 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 1), 0), 1), 0)); + ro[2] = *(ro_loc[2] = &XEXP (XVECEXP (pat, 0, 1), 0)); + break; + + case 220: + ro[0] = *(ro_loc[0] = &XEXP (XEXP (pat, 1), 0)); + break; + + case 219: + case 218: + case 217: + case 216: + case 215: + case 214: + case 213: + case 212: + case 211: + case 210: + ro[0] = *(ro_loc[0] = &XEXP (XEXP (XEXP (pat, 1), 2), 0)); + break; + + case 209: + case 207: + case 205: + case 203: + case 201: + case 199: + case 197: + case 195: + case 193: + case 191: + ro[0] = *(ro_loc[0] = &XEXP (XEXP (XEXP (pat, 1), 1), 0)); + break; + + case 189: + case 187: + case 185: + case 183: + case 181: + case 179: + case 177: + case 175: + case 173: + case 171: + ro[0] = *(ro_loc[0] = &XEXP (pat, 0)); + break; + + case 169: + case 168: + ro[0] = *(ro_loc[0] = &XEXP (XEXP (pat, 1), 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (pat, 1), 1)); + ro[2] = *(ro_loc[2] = &XEXP (XEXP (pat, 1), 2)); + break; + + case 167: + ro[0] = *(ro_loc[0] = &XEXP (XEXP (pat, 1), 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (pat, 1), 2)); + break; + + case 166: + ro[0] = *(ro_loc[0] = &XEXP (pat, 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (pat, 1), 0)); + ro[2] = *(ro_loc[2] = &XEXP (XEXP (XEXP (pat, 1), 1), 1)); + break; + + case 165: + ro[0] = *(ro_loc[0] = &XEXP (pat, 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (XEXP (pat, 1), 0), 1)); + ro[2] = *(ro_loc[2] = &XEXP (XEXP (pat, 1), 1)); + break; + + case 164: + ro[0] = *(ro_loc[0] = &XEXP (XEXP (pat, 0), 0)); + ro[1] = const0_rtx; + ro_loc[1] = &junk; + ro[2] = *(ro_loc[2] = &XEXP (XEXP (pat, 0), 2)); + ro[3] = *(ro_loc[3] = &XEXP (pat, 1)); + break; + + case 154: + case 148: + case 142: + ro[0] = *(ro_loc[0] = &XEXP (XVECEXP (pat, 0, 0), 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0)); + ro[2] = *(ro_loc[2] = &XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 1)); + recog_dup_loc[0] = &XEXP (XVECEXP (pat, 0, 1), 0); + recog_dup_num[0] = 2; + break; + + case 136: + case 133: + ro[0] = *(ro_loc[0] = &XEXP (pat, 0)); + ro[1] = *(ro_loc[1] = &XEXP (XVECEXP (XEXP (pat, 1), 0, 0), 0)); + break; + + case 135: + case 134: + case 132: + case 131: + ro[0] = *(ro_loc[0] = &XEXP (pat, 0)); + ro[1] = *(ro_loc[1] = &XVECEXP (XEXP (pat, 1), 0, 0)); + break; + + case 130: + case 127: + case 124: + ro[0] = *(ro_loc[0] = &XEXP (pat, 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (XEXP (pat, 1), 0), 0)); + break; + + case 108: + case 107: + case 106: + case 105: + ro[0] = *(ro_loc[0] = &XEXP (XVECEXP (pat, 0, 0), 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0)); + ro[2] = *(ro_loc[2] = &XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 1)); + ro[3] = *(ro_loc[3] = &XEXP (XVECEXP (pat, 0, 1), 0)); + recog_dup_loc[0] = &XEXP (XEXP (XVECEXP (pat, 0, 1), 1), 0); + recog_dup_num[0] = 1; + recog_dup_loc[1] = &XEXP (XEXP (XVECEXP (pat, 0, 1), 1), 1); + recog_dup_num[1] = 2; + break; + + case 98: + ro[0] = *(ro_loc[0] = &XEXP (pat, 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (XEXP (pat, 1), 0), 0)); + ro[2] = *(ro_loc[2] = &XEXP (XEXP (XEXP (pat, 1), 1), 0)); + break; + + case 235: + case 163: + case 162: + case 161: + case 160: + case 159: + case 158: + case 157: + case 156: + case 155: + case 153: + case 151: + case 150: + case 149: + case 147: + case 145: + case 144: + case 143: + case 141: + case 117: + case 116: + case 115: + case 114: + case 113: + case 112: + case 111: + case 110: + case 109: + case 102: + case 101: + case 97: + case 96: + case 95: + case 94: + case 91: + case 90: + case 89: + case 88: + case 84: + case 83: + case 82: + case 81: + ro[0] = *(ro_loc[0] = &XEXP (pat, 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (pat, 1), 0)); + ro[2] = *(ro_loc[2] = &XEXP (XEXP (pat, 1), 1)); + break; + + case 72: + case 71: + ro[0] = *(ro_loc[0] = &XEXP (XVECEXP (pat, 0, 0), 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0), 0)); + ro[2] = *(ro_loc[2] = &XEXP (XVECEXP (pat, 0, 1), 0)); + ro[3] = *(ro_loc[3] = &XEXP (XVECEXP (pat, 0, 2), 0)); + ro[4] = *(ro_loc[4] = &XEXP (XVECEXP (pat, 0, 3), 0)); + break; + + case 68: + case 67: + ro[0] = *(ro_loc[0] = &XEXP (XVECEXP (pat, 0, 0), 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0), 0)); + ro[2] = *(ro_loc[2] = &XEXP (XVECEXP (pat, 0, 2), 0)); + ro[3] = *(ro_loc[3] = &XEXP (XVECEXP (pat, 0, 3), 0)); + ro[4] = *(ro_loc[4] = &XEXP (XVECEXP (pat, 0, 4), 0)); + recog_dup_loc[0] = &XEXP (XVECEXP (pat, 0, 1), 0); + recog_dup_num[0] = 1; + break; + + case 62: + ro[0] = *(ro_loc[0] = &XEXP (XVECEXP (pat, 0, 0), 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0)); + ro[2] = *(ro_loc[2] = &XEXP (XVECEXP (pat, 0, 1), 0)); + break; + + case 139: + case 138: + case 137: + case 129: + case 128: + case 126: + case 125: + case 123: + case 122: + case 121: + case 120: + case 119: + case 118: + case 80: + case 79: + case 78: + case 77: + case 60: + case 59: + case 58: + case 57: + case 56: + case 55: + case 54: + case 53: + case 52: + ro[0] = *(ro_loc[0] = &XEXP (pat, 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (pat, 1), 0)); + break; + + case 48: + ro[0] = *(ro_loc[0] = &XEXP (XVECEXP (pat, 0, 0), 0)); + ro[1] = *(ro_loc[1] = &XEXP (XVECEXP (pat, 0, 0), 1)); + recog_dup_loc[0] = &XEXP (XVECEXP (pat, 0, 1), 0); + recog_dup_num[0] = 1; + recog_dup_loc[1] = &XEXP (XVECEXP (pat, 0, 1), 1); + recog_dup_num[1] = 0; + break; + + case 230: + case 44: + case 41: + ro[0] = *(ro_loc[0] = &XEXP (XEXP (pat, 0), 0)); + ro[1] = *(ro_loc[1] = &XEXP (pat, 1)); + break; + + case 229: + case 85: + case 51: + case 50: + case 49: + case 47: + case 46: + case 45: + case 43: + case 42: + case 40: + case 39: + case 38: + case 36: + case 35: + ro[0] = *(ro_loc[0] = &XEXP (pat, 0)); + ro[1] = *(ro_loc[1] = &XEXP (pat, 1)); + break; + + case 25: + case 21: + ro[0] = *(ro_loc[0] = &XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 1)); + ro[2] = *(ro_loc[2] = &XEXP (XVECEXP (pat, 0, 1), 0)); + break; + + case 24: + case 20: + case 18: + ro[0] = *(ro_loc[0] = &XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0), 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 1)); + ro[2] = *(ro_loc[2] = &XEXP (XVECEXP (pat, 0, 0), 1)); + ro[3] = *(ro_loc[3] = &XEXP (XVECEXP (pat, 0, 1), 0)); + break; + + case 23: + case 19: + case 17: + ro[0] = *(ro_loc[0] = &XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 1), 0)); + ro[2] = *(ro_loc[2] = &XEXP (XVECEXP (pat, 0, 0), 1)); + ro[3] = *(ro_loc[3] = &XEXP (XVECEXP (pat, 0, 1), 0)); + break; + + case 22: + case 16: + ro[0] = *(ro_loc[0] = &XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 1)); + ro[2] = *(ro_loc[2] = &XEXP (XVECEXP (pat, 0, 0), 1)); + ro[3] = *(ro_loc[3] = &XEXP (XVECEXP (pat, 0, 1), 0)); + break; + + case 34: + case 33: + case 32: + case 14: + case 12: + case 10: + ro[0] = *(ro_loc[0] = &XEXP (XEXP (pat, 1), 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (pat, 1), 1)); + break; + + case 8: + case 6: + ro[0] = *(ro_loc[0] = &XEXP (XVECEXP (pat, 0, 0), 1)); + ro[1] = *(ro_loc[1] = &XEXP (XVECEXP (pat, 0, 1), 0)); + break; + + case 221: + case 4: + case 2: + case 0: + ro[0] = *(ro_loc[0] = &XEXP (pat, 1)); + break; + + default: + abort (); + } +} diff --git a/gnu/usr.bin/gcc2/i386/insn-flags.h b/gnu/usr.bin/gcc2/i386/insn-flags.h new file mode 100644 index 00000000000..9070b93d11e --- /dev/null +++ b/gnu/usr.bin/gcc2/i386/insn-flags.h @@ -0,0 +1,510 @@ +/* Generated automatically by the program `genflags' +from the machine description file `md'. */ + +#define HAVE_tstsi_1 1 +#define HAVE_tstsi 1 +#define HAVE_tsthi_1 1 +#define HAVE_tsthi 1 +#define HAVE_tstqi_1 1 +#define HAVE_tstqi 1 +#define HAVE_tstsf_cc (TARGET_80387 && ! TARGET_IEEE_FP) +#define HAVE_tstsf (TARGET_80387 && ! TARGET_IEEE_FP) +#define HAVE_tstdf_cc (TARGET_80387 && ! TARGET_IEEE_FP) +#define HAVE_tstdf (TARGET_80387 && ! TARGET_IEEE_FP) +#define HAVE_cmpsi_1 (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM) +#define HAVE_cmpsi 1 +#define HAVE_cmphi_1 (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM) +#define HAVE_cmphi 1 +#define HAVE_cmpqi_1 (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM) +#define HAVE_cmpqi 1 +#define HAVE_cmpsf_cc_1 (TARGET_80387 \ + && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)) +#define HAVE_cmpdf (TARGET_80387) +#define HAVE_cmpsf (TARGET_80387) +#define HAVE_cmpdf_cc (TARGET_80387) +#define HAVE_cmpdf_ccfpeq (TARGET_80387) +#define HAVE_cmpsf_cc (TARGET_80387) +#define HAVE_cmpsf_ccfpeq (TARGET_80387) +#define HAVE_movsi 1 +#define HAVE_movhi 1 +#define HAVE_movstricthi 1 +#define HAVE_movqi 1 +#define HAVE_movstrictqi 1 +#define HAVE_movsf 1 +#define HAVE_swapdf 1 +#define HAVE_movdf 1 +#define HAVE_movdi 1 +#define HAVE_zero_extendhisi2 1 +#define HAVE_zero_extendqihi2 1 +#define HAVE_zero_extendqisi2 1 +#define HAVE_zero_extendsidi2 1 +#define HAVE_extendsidi2 1 +#define HAVE_extendhisi2 1 +#define HAVE_extendqihi2 1 +#define HAVE_extendqisi2 1 +#define HAVE_extendsfdf2 (TARGET_80387) +#define HAVE_truncdfsf2 (TARGET_80387) +#define HAVE_fixuns_truncdfsi2 (TARGET_80387) +#define HAVE_fixuns_truncsfsi2 (TARGET_80387) +#define HAVE_fix_truncdfdi2 (TARGET_80387) +#define HAVE_fix_truncsfdi2 (TARGET_80387) +#define HAVE_fix_truncdfsi2 (TARGET_80387) +#define HAVE_fix_truncsfsi2 (TARGET_80387) +#define HAVE_floatsisf2 (TARGET_80387) +#define HAVE_floatdisf2 (TARGET_80387) +#define HAVE_floatsidf2 (TARGET_80387) +#define HAVE_floatdidf2 (TARGET_80387) +#define HAVE_adddi3 1 +#define HAVE_addsi3 1 +#define HAVE_addhi3 1 +#define HAVE_addqi3 1 +#define HAVE_adddf3 (TARGET_80387) +#define HAVE_addsf3 (TARGET_80387) +#define HAVE_subdi3 1 +#define HAVE_subsi3 1 +#define HAVE_subhi3 1 +#define HAVE_subqi3 1 +#define HAVE_subdf3 (TARGET_80387) +#define HAVE_subsf3 (TARGET_80387) +#define HAVE_mulhi3 1 +#define HAVE_mulsi3 1 +#define HAVE_muldf3 (TARGET_80387) +#define HAVE_mulsf3 (TARGET_80387) +#define HAVE_divqi3 1 +#define HAVE_udivqi3 1 +#define HAVE_divdf3 (TARGET_80387) +#define HAVE_divsf3 (TARGET_80387) +#define HAVE_divmodsi4 1 +#define HAVE_divmodhi4 1 +#define HAVE_udivmodsi4 1 +#define HAVE_udivmodhi4 1 +#define HAVE_andsi3 1 +#define HAVE_andhi3 1 +#define HAVE_andqi3 1 +#define HAVE_iorsi3 1 +#define HAVE_iorhi3 1 +#define HAVE_iorqi3 1 +#define HAVE_xorsi3 1 +#define HAVE_xorhi3 1 +#define HAVE_xorqi3 1 +#define HAVE_negdi2 1 +#define HAVE_negsi2 1 +#define HAVE_neghi2 1 +#define HAVE_negqi2 1 +#define HAVE_negsf2 (TARGET_80387) +#define HAVE_negdf2 (TARGET_80387) +#define HAVE_abssf2 (TARGET_80387) +#define HAVE_absdf2 (TARGET_80387) +#define HAVE_sqrtsf2 (TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)) +#define HAVE_sqrtdf2 (TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)) +#define HAVE_sindf2 (TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)) +#define HAVE_sinsf2 (TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)) +#define HAVE_cosdf2 (TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)) +#define HAVE_cossf2 (TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)) +#define HAVE_one_cmplsi2 1 +#define HAVE_one_cmplhi2 1 +#define HAVE_one_cmplqi2 1 +#define HAVE_ashldi3 1 +#define HAVE_ashldi3_const_int 1 +#define HAVE_ashldi3_non_const_int 1 +#define HAVE_ashlsi3 1 +#define HAVE_ashlhi3 1 +#define HAVE_ashlqi3 1 +#define HAVE_ashrdi3 1 +#define HAVE_ashrdi3_const_int 1 +#define HAVE_ashrdi3_non_const_int 1 +#define HAVE_ashrsi3 1 +#define HAVE_ashrhi3 1 +#define HAVE_ashrqi3 1 +#define HAVE_lshrdi3 1 +#define HAVE_lshrdi3_const_int 1 +#define HAVE_lshrdi3_non_const_int 1 +#define HAVE_lshrsi3 1 +#define HAVE_lshrhi3 1 +#define HAVE_lshrqi3 1 +#define HAVE_rotlsi3 1 +#define HAVE_rotlhi3 1 +#define HAVE_rotlqi3 1 +#define HAVE_rotrsi3 1 +#define HAVE_rotrhi3 1 +#define HAVE_rotrqi3 1 +#define HAVE_seq 1 +#define HAVE_sne 1 +#define HAVE_sgt 1 +#define HAVE_sgtu 1 +#define HAVE_slt 1 +#define HAVE_sltu 1 +#define HAVE_sge 1 +#define HAVE_sgeu 1 +#define HAVE_sle 1 +#define HAVE_sleu 1 +#define HAVE_beq 1 +#define HAVE_bne 1 +#define HAVE_bgt 1 +#define HAVE_bgtu 1 +#define HAVE_blt 1 +#define HAVE_bltu 1 +#define HAVE_bge 1 +#define HAVE_bgeu 1 +#define HAVE_ble 1 +#define HAVE_bleu 1 +#define HAVE_jump 1 +#define HAVE_indirect_jump 1 +#define HAVE_casesi (flag_pic) +#define HAVE_tablejump 1 +#define HAVE_call_pop 1 +#define HAVE_call 1 +#define HAVE_call_value_pop 1 +#define HAVE_call_value 1 +#define HAVE_untyped_call 1 +#define HAVE_untyped_return 1 +#define HAVE_update_return 1 +#define HAVE_return (simple_386_epilogue ()) +#define HAVE_nop 1 +#define HAVE_movstrsi 1 +#define HAVE_cmpstrsi 1 +#define HAVE_ffssi2 1 +#define HAVE_ffshi2 1 +#define HAVE_strlensi 1 + +#ifndef NO_MD_PROTOTYPES +extern rtx gen_tstsi_1 PROTO((rtx)); +extern rtx gen_tstsi PROTO((rtx)); +extern rtx gen_tsthi_1 PROTO((rtx)); +extern rtx gen_tsthi PROTO((rtx)); +extern rtx gen_tstqi_1 PROTO((rtx)); +extern rtx gen_tstqi PROTO((rtx)); +extern rtx gen_tstsf_cc PROTO((rtx)); +extern rtx gen_tstsf PROTO((rtx)); +extern rtx gen_tstdf_cc PROTO((rtx)); +extern rtx gen_tstdf PROTO((rtx)); +extern rtx gen_cmpsi_1 PROTO((rtx, rtx)); +extern rtx gen_cmpsi PROTO((rtx, rtx)); +extern rtx gen_cmphi_1 PROTO((rtx, rtx)); +extern rtx gen_cmphi PROTO((rtx, rtx)); +extern rtx gen_cmpqi_1 PROTO((rtx, rtx)); +extern rtx gen_cmpqi PROTO((rtx, rtx)); +extern rtx gen_cmpsf_cc_1 PROTO((rtx, rtx, rtx)); +extern rtx gen_cmpdf PROTO((rtx, rtx)); +extern rtx gen_cmpsf PROTO((rtx, rtx)); +extern rtx gen_cmpdf_cc PROTO((rtx, rtx)); +extern rtx gen_cmpdf_ccfpeq PROTO((rtx, rtx)); +extern rtx gen_cmpsf_cc PROTO((rtx, rtx)); +extern rtx gen_cmpsf_ccfpeq PROTO((rtx, rtx)); +extern rtx gen_movsi PROTO((rtx, rtx)); +extern rtx gen_movhi PROTO((rtx, rtx)); +extern rtx gen_movstricthi PROTO((rtx, rtx)); +extern rtx gen_movqi PROTO((rtx, rtx)); +extern rtx gen_movstrictqi PROTO((rtx, rtx)); +extern rtx gen_movsf PROTO((rtx, rtx)); +extern rtx gen_swapdf PROTO((rtx, rtx)); +extern rtx gen_movdf PROTO((rtx, rtx)); +extern rtx gen_movdi PROTO((rtx, rtx)); +extern rtx gen_zero_extendhisi2 PROTO((rtx, rtx)); +extern rtx gen_zero_extendqihi2 PROTO((rtx, rtx)); +extern rtx gen_zero_extendqisi2 PROTO((rtx, rtx)); +extern rtx gen_zero_extendsidi2 PROTO((rtx, rtx)); +extern rtx gen_extendsidi2 PROTO((rtx, rtx)); +extern rtx gen_extendhisi2 PROTO((rtx, rtx)); +extern rtx gen_extendqihi2 PROTO((rtx, rtx)); +extern rtx gen_extendqisi2 PROTO((rtx, rtx)); +extern rtx gen_extendsfdf2 PROTO((rtx, rtx)); +extern rtx gen_truncdfsf2 PROTO((rtx, rtx)); +extern rtx gen_fixuns_truncdfsi2 PROTO((rtx, rtx)); +extern rtx gen_fixuns_truncsfsi2 PROTO((rtx, rtx)); +extern rtx gen_fix_truncdfdi2 PROTO((rtx, rtx)); +extern rtx gen_fix_truncsfdi2 PROTO((rtx, rtx)); +extern rtx gen_fix_truncdfsi2 PROTO((rtx, rtx)); +extern rtx gen_fix_truncsfsi2 PROTO((rtx, rtx)); +extern rtx gen_floatsisf2 PROTO((rtx, rtx)); +extern rtx gen_floatdisf2 PROTO((rtx, rtx)); +extern rtx gen_floatsidf2 PROTO((rtx, rtx)); +extern rtx gen_floatdidf2 PROTO((rtx, rtx)); +extern rtx gen_adddi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_addsi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_addhi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_addqi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_adddf3 PROTO((rtx, rtx, rtx)); +extern rtx gen_addsf3 PROTO((rtx, rtx, rtx)); +extern rtx gen_subdi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_subsi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_subhi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_subqi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_subdf3 PROTO((rtx, rtx, rtx)); +extern rtx gen_subsf3 PROTO((rtx, rtx, rtx)); +extern rtx gen_mulhi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_mulsi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_muldf3 PROTO((rtx, rtx, rtx)); +extern rtx gen_mulsf3 PROTO((rtx, rtx, rtx)); +extern rtx gen_divqi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_udivqi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_divdf3 PROTO((rtx, rtx, rtx)); +extern rtx gen_divsf3 PROTO((rtx, rtx, rtx)); +extern rtx gen_divmodsi4 PROTO((rtx, rtx, rtx, rtx)); +extern rtx gen_divmodhi4 PROTO((rtx, rtx, rtx, rtx)); +extern rtx gen_udivmodsi4 PROTO((rtx, rtx, rtx, rtx)); +extern rtx gen_udivmodhi4 PROTO((rtx, rtx, rtx, rtx)); +extern rtx gen_andsi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_andhi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_andqi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_iorsi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_iorhi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_iorqi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_xorsi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_xorhi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_xorqi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_negdi2 PROTO((rtx, rtx)); +extern rtx gen_negsi2 PROTO((rtx, rtx)); +extern rtx gen_neghi2 PROTO((rtx, rtx)); +extern rtx gen_negqi2 PROTO((rtx, rtx)); +extern rtx gen_negsf2 PROTO((rtx, rtx)); +extern rtx gen_negdf2 PROTO((rtx, rtx)); +extern rtx gen_abssf2 PROTO((rtx, rtx)); +extern rtx gen_absdf2 PROTO((rtx, rtx)); +extern rtx gen_sqrtsf2 PROTO((rtx, rtx)); +extern rtx gen_sqrtdf2 PROTO((rtx, rtx)); +extern rtx gen_sindf2 PROTO((rtx, rtx)); +extern rtx gen_sinsf2 PROTO((rtx, rtx)); +extern rtx gen_cosdf2 PROTO((rtx, rtx)); +extern rtx gen_cossf2 PROTO((rtx, rtx)); +extern rtx gen_one_cmplsi2 PROTO((rtx, rtx)); +extern rtx gen_one_cmplhi2 PROTO((rtx, rtx)); +extern rtx gen_one_cmplqi2 PROTO((rtx, rtx)); +extern rtx gen_ashldi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_ashldi3_const_int PROTO((rtx, rtx, rtx)); +extern rtx gen_ashldi3_non_const_int PROTO((rtx, rtx, rtx)); +extern rtx gen_ashlsi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_ashlhi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_ashlqi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_ashrdi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_ashrdi3_const_int PROTO((rtx, rtx, rtx)); +extern rtx gen_ashrdi3_non_const_int PROTO((rtx, rtx, rtx)); +extern rtx gen_ashrsi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_ashrhi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_ashrqi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_lshrdi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_lshrdi3_const_int PROTO((rtx, rtx, rtx)); +extern rtx gen_lshrdi3_non_const_int PROTO((rtx, rtx, rtx)); +extern rtx gen_lshrsi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_lshrhi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_lshrqi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_rotlsi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_rotlhi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_rotlqi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_rotrsi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_rotrhi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_rotrqi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_seq PROTO((rtx)); +extern rtx gen_sne PROTO((rtx)); +extern rtx gen_sgt PROTO((rtx)); +extern rtx gen_sgtu PROTO((rtx)); +extern rtx gen_slt PROTO((rtx)); +extern rtx gen_sltu PROTO((rtx)); +extern rtx gen_sge PROTO((rtx)); +extern rtx gen_sgeu PROTO((rtx)); +extern rtx gen_sle PROTO((rtx)); +extern rtx gen_sleu PROTO((rtx)); +extern rtx gen_beq PROTO((rtx)); +extern rtx gen_bne PROTO((rtx)); +extern rtx gen_bgt PROTO((rtx)); +extern rtx gen_bgtu PROTO((rtx)); +extern rtx gen_blt PROTO((rtx)); +extern rtx gen_bltu PROTO((rtx)); +extern rtx gen_bge PROTO((rtx)); +extern rtx gen_bgeu PROTO((rtx)); +extern rtx gen_ble PROTO((rtx)); +extern rtx gen_bleu PROTO((rtx)); +extern rtx gen_jump PROTO((rtx)); +extern rtx gen_indirect_jump PROTO((rtx)); +extern rtx gen_casesi PROTO((rtx, rtx, rtx, rtx, rtx)); +extern rtx gen_tablejump PROTO((rtx, rtx)); +extern rtx gen_untyped_call PROTO((rtx, rtx, rtx)); +extern rtx gen_untyped_return PROTO((rtx, rtx)); +extern rtx gen_update_return PROTO((rtx)); +extern rtx gen_return PROTO((void)); +extern rtx gen_nop PROTO((void)); +extern rtx gen_movstrsi PROTO((rtx, rtx, rtx, rtx)); +extern rtx gen_cmpstrsi PROTO((rtx, rtx, rtx, rtx, rtx)); +extern rtx gen_ffssi2 PROTO((rtx, rtx)); +extern rtx gen_ffshi2 PROTO((rtx, rtx)); +extern rtx gen_strlensi PROTO((rtx, rtx, rtx, rtx)); + +#ifdef MD_CALL_PROTOTYPES +extern rtx gen_call_pop PROTO((rtx, rtx, rtx)); +extern rtx gen_call PROTO((rtx, rtx)); +extern rtx gen_call_value_pop PROTO((rtx, rtx, rtx, rtx)); +extern rtx gen_call_value PROTO((rtx, rtx, rtx)); + +#else /* !MD_CALL_PROTOTYPES */ +extern rtx gen_call_pop (); +extern rtx gen_call (); +extern rtx gen_call_value_pop (); +extern rtx gen_call_value (); +#endif /* !MD_CALL_PROTOTYPES */ + +#else /* NO_MD_PROTOTYPES */ +extern rtx gen_tstsi_1 (); +extern rtx gen_tstsi (); +extern rtx gen_tsthi_1 (); +extern rtx gen_tsthi (); +extern rtx gen_tstqi_1 (); +extern rtx gen_tstqi (); +extern rtx gen_tstsf_cc (); +extern rtx gen_tstsf (); +extern rtx gen_tstdf_cc (); +extern rtx gen_tstdf (); +extern rtx gen_cmpsi_1 (); +extern rtx gen_cmpsi (); +extern rtx gen_cmphi_1 (); +extern rtx gen_cmphi (); +extern rtx gen_cmpqi_1 (); +extern rtx gen_cmpqi (); +extern rtx gen_cmpsf_cc_1 (); +extern rtx gen_cmpdf (); +extern rtx gen_cmpsf (); +extern rtx gen_cmpdf_cc (); +extern rtx gen_cmpdf_ccfpeq (); +extern rtx gen_cmpsf_cc (); +extern rtx gen_cmpsf_ccfpeq (); +extern rtx gen_movsi (); +extern rtx gen_movhi (); +extern rtx gen_movstricthi (); +extern rtx gen_movqi (); +extern rtx gen_movstrictqi (); +extern rtx gen_movsf (); +extern rtx gen_swapdf (); +extern rtx gen_movdf (); +extern rtx gen_movdi (); +extern rtx gen_zero_extendhisi2 (); +extern rtx gen_zero_extendqihi2 (); +extern rtx gen_zero_extendqisi2 (); +extern rtx gen_zero_extendsidi2 (); +extern rtx gen_extendsidi2 (); +extern rtx gen_extendhisi2 (); +extern rtx gen_extendqihi2 (); +extern rtx gen_extendqisi2 (); +extern rtx gen_extendsfdf2 (); +extern rtx gen_truncdfsf2 (); +extern rtx gen_fixuns_truncdfsi2 (); +extern rtx gen_fixuns_truncsfsi2 (); +extern rtx gen_fix_truncdfdi2 (); +extern rtx gen_fix_truncsfdi2 (); +extern rtx gen_fix_truncdfsi2 (); +extern rtx gen_fix_truncsfsi2 (); +extern rtx gen_floatsisf2 (); +extern rtx gen_floatdisf2 (); +extern rtx gen_floatsidf2 (); +extern rtx gen_floatdidf2 (); +extern rtx gen_adddi3 (); +extern rtx gen_addsi3 (); +extern rtx gen_addhi3 (); +extern rtx gen_addqi3 (); +extern rtx gen_adddf3 (); +extern rtx gen_addsf3 (); +extern rtx gen_subdi3 (); +extern rtx gen_subsi3 (); +extern rtx gen_subhi3 (); +extern rtx gen_subqi3 (); +extern rtx gen_subdf3 (); +extern rtx gen_subsf3 (); +extern rtx gen_mulhi3 (); +extern rtx gen_mulsi3 (); +extern rtx gen_muldf3 (); +extern rtx gen_mulsf3 (); +extern rtx gen_divqi3 (); +extern rtx gen_udivqi3 (); +extern rtx gen_divdf3 (); +extern rtx gen_divsf3 (); +extern rtx gen_divmodsi4 (); +extern rtx gen_divmodhi4 (); +extern rtx gen_udivmodsi4 (); +extern rtx gen_udivmodhi4 (); +extern rtx gen_andsi3 (); +extern rtx gen_andhi3 (); +extern rtx gen_andqi3 (); +extern rtx gen_iorsi3 (); +extern rtx gen_iorhi3 (); +extern rtx gen_iorqi3 (); +extern rtx gen_xorsi3 (); +extern rtx gen_xorhi3 (); +extern rtx gen_xorqi3 (); +extern rtx gen_negdi2 (); +extern rtx gen_negsi2 (); +extern rtx gen_neghi2 (); +extern rtx gen_negqi2 (); +extern rtx gen_negsf2 (); +extern rtx gen_negdf2 (); +extern rtx gen_abssf2 (); +extern rtx gen_absdf2 (); +extern rtx gen_sqrtsf2 (); +extern rtx gen_sqrtdf2 (); +extern rtx gen_sindf2 (); +extern rtx gen_sinsf2 (); +extern rtx gen_cosdf2 (); +extern rtx gen_cossf2 (); +extern rtx gen_one_cmplsi2 (); +extern rtx gen_one_cmplhi2 (); +extern rtx gen_one_cmplqi2 (); +extern rtx gen_ashldi3 (); +extern rtx gen_ashldi3_const_int (); +extern rtx gen_ashldi3_non_const_int (); +extern rtx gen_ashlsi3 (); +extern rtx gen_ashlhi3 (); +extern rtx gen_ashlqi3 (); +extern rtx gen_ashrdi3 (); +extern rtx gen_ashrdi3_const_int (); +extern rtx gen_ashrdi3_non_const_int (); +extern rtx gen_ashrsi3 (); +extern rtx gen_ashrhi3 (); +extern rtx gen_ashrqi3 (); +extern rtx gen_lshrdi3 (); +extern rtx gen_lshrdi3_const_int (); +extern rtx gen_lshrdi3_non_const_int (); +extern rtx gen_lshrsi3 (); +extern rtx gen_lshrhi3 (); +extern rtx gen_lshrqi3 (); +extern rtx gen_rotlsi3 (); +extern rtx gen_rotlhi3 (); +extern rtx gen_rotlqi3 (); +extern rtx gen_rotrsi3 (); +extern rtx gen_rotrhi3 (); +extern rtx gen_rotrqi3 (); +extern rtx gen_seq (); +extern rtx gen_sne (); +extern rtx gen_sgt (); +extern rtx gen_sgtu (); +extern rtx gen_slt (); +extern rtx gen_sltu (); +extern rtx gen_sge (); +extern rtx gen_sgeu (); +extern rtx gen_sle (); +extern rtx gen_sleu (); +extern rtx gen_beq (); +extern rtx gen_bne (); +extern rtx gen_bgt (); +extern rtx gen_bgtu (); +extern rtx gen_blt (); +extern rtx gen_bltu (); +extern rtx gen_bge (); +extern rtx gen_bgeu (); +extern rtx gen_ble (); +extern rtx gen_bleu (); +extern rtx gen_jump (); +extern rtx gen_indirect_jump (); +extern rtx gen_casesi (); +extern rtx gen_tablejump (); +extern rtx gen_untyped_call (); +extern rtx gen_untyped_return (); +extern rtx gen_update_return (); +extern rtx gen_return (); +extern rtx gen_nop (); +extern rtx gen_movstrsi (); +extern rtx gen_cmpstrsi (); +extern rtx gen_ffssi2 (); +extern rtx gen_ffshi2 (); +extern rtx gen_strlensi (); +extern rtx gen_call_pop (); +extern rtx gen_call (); +extern rtx gen_call_value_pop (); +extern rtx gen_call_value (); +#endif /* NO_MD_PROTOTYPES */ diff --git a/gnu/usr.bin/gcc2/i386/insn-opinit.c b/gnu/usr.bin/gcc2/i386/insn-opinit.c new file mode 100644 index 00000000000..7959ae5fb1c --- /dev/null +++ b/gnu/usr.bin/gcc2/i386/insn-opinit.c @@ -0,0 +1,179 @@ +/* Generated automatically by the program `genopinit' +from the machine description file `md'. */ + +#include "config.h" +#include "rtl.h" +#include "flags.h" +#include "insn-flags.h" +#include "insn-codes.h" +#include "insn-config.h" +#include "recog.h" +#include "expr.h" +#include "reload.h" + +void +init_all_optabs () +{ + tst_optab->handlers[(int) SImode].insn_code = CODE_FOR_tstsi; + tst_optab->handlers[(int) HImode].insn_code = CODE_FOR_tsthi; + tst_optab->handlers[(int) QImode].insn_code = CODE_FOR_tstqi; + if (HAVE_tstsf) + tst_optab->handlers[(int) SFmode].insn_code = CODE_FOR_tstsf; + if (HAVE_tstdf) + tst_optab->handlers[(int) DFmode].insn_code = CODE_FOR_tstdf; + cmp_optab->handlers[(int) SImode].insn_code = CODE_FOR_cmpsi; + cmp_optab->handlers[(int) HImode].insn_code = CODE_FOR_cmphi; + cmp_optab->handlers[(int) QImode].insn_code = CODE_FOR_cmpqi; + if (HAVE_cmpdf) + cmp_optab->handlers[(int) DFmode].insn_code = CODE_FOR_cmpdf; + if (HAVE_cmpsf) + cmp_optab->handlers[(int) SFmode].insn_code = CODE_FOR_cmpsf; + mov_optab->handlers[(int) SImode].insn_code = CODE_FOR_movsi; + mov_optab->handlers[(int) HImode].insn_code = CODE_FOR_movhi; + movstrict_optab->handlers[(int) HImode].insn_code = CODE_FOR_movstricthi; + mov_optab->handlers[(int) QImode].insn_code = CODE_FOR_movqi; + movstrict_optab->handlers[(int) QImode].insn_code = CODE_FOR_movstrictqi; + mov_optab->handlers[(int) SFmode].insn_code = CODE_FOR_movsf; + mov_optab->handlers[(int) DFmode].insn_code = CODE_FOR_movdf; + mov_optab->handlers[(int) DImode].insn_code = CODE_FOR_movdi; + extendtab[(int) SImode][(int) HImode][1] = CODE_FOR_zero_extendhisi2; + extendtab[(int) HImode][(int) QImode][1] = CODE_FOR_zero_extendqihi2; + extendtab[(int) SImode][(int) QImode][1] = CODE_FOR_zero_extendqisi2; + extendtab[(int) DImode][(int) SImode][1] = CODE_FOR_zero_extendsidi2; + extendtab[(int) DImode][(int) SImode][0] = CODE_FOR_extendsidi2; + extendtab[(int) SImode][(int) HImode][0] = CODE_FOR_extendhisi2; + extendtab[(int) HImode][(int) QImode][0] = CODE_FOR_extendqihi2; + extendtab[(int) SImode][(int) QImode][0] = CODE_FOR_extendqisi2; + if (HAVE_extendsfdf2) + extendtab[(int) DFmode][(int) SFmode][0] = CODE_FOR_extendsfdf2; + if (HAVE_fixuns_truncdfsi2) + fixtrunctab[(int) DFmode][(int) SImode][1] = CODE_FOR_fixuns_truncdfsi2; + if (HAVE_fixuns_truncsfsi2) + fixtrunctab[(int) SFmode][(int) SImode][1] = CODE_FOR_fixuns_truncsfsi2; + if (HAVE_fix_truncdfdi2) + fixtrunctab[(int) DFmode][(int) DImode][0] = CODE_FOR_fix_truncdfdi2; + if (HAVE_fix_truncsfdi2) + fixtrunctab[(int) SFmode][(int) DImode][0] = CODE_FOR_fix_truncsfdi2; + if (HAVE_fix_truncdfsi2) + fixtrunctab[(int) DFmode][(int) SImode][0] = CODE_FOR_fix_truncdfsi2; + if (HAVE_fix_truncsfsi2) + fixtrunctab[(int) SFmode][(int) SImode][0] = CODE_FOR_fix_truncsfsi2; + if (HAVE_floatsisf2) + floattab[(int) SFmode][(int) SImode][0] = CODE_FOR_floatsisf2; + if (HAVE_floatdisf2) + floattab[(int) SFmode][(int) DImode][0] = CODE_FOR_floatdisf2; + if (HAVE_floatsidf2) + floattab[(int) DFmode][(int) SImode][0] = CODE_FOR_floatsidf2; + if (HAVE_floatdidf2) + floattab[(int) DFmode][(int) DImode][0] = CODE_FOR_floatdidf2; + add_optab->handlers[(int) DImode].insn_code = CODE_FOR_adddi3; + add_optab->handlers[(int) SImode].insn_code = CODE_FOR_addsi3; + add_optab->handlers[(int) HImode].insn_code = CODE_FOR_addhi3; + add_optab->handlers[(int) QImode].insn_code = CODE_FOR_addqi3; + if (HAVE_adddf3) + add_optab->handlers[(int) DFmode].insn_code = CODE_FOR_adddf3; + if (HAVE_addsf3) + add_optab->handlers[(int) SFmode].insn_code = CODE_FOR_addsf3; + sub_optab->handlers[(int) DImode].insn_code = CODE_FOR_subdi3; + sub_optab->handlers[(int) SImode].insn_code = CODE_FOR_subsi3; + sub_optab->handlers[(int) HImode].insn_code = CODE_FOR_subhi3; + sub_optab->handlers[(int) QImode].insn_code = CODE_FOR_subqi3; + if (HAVE_subdf3) + sub_optab->handlers[(int) DFmode].insn_code = CODE_FOR_subdf3; + if (HAVE_subsf3) + sub_optab->handlers[(int) SFmode].insn_code = CODE_FOR_subsf3; + smul_optab->handlers[(int) HImode].insn_code = CODE_FOR_mulhi3; + smul_optab->handlers[(int) SImode].insn_code = CODE_FOR_mulsi3; + if (HAVE_muldf3) + smul_optab->handlers[(int) DFmode].insn_code = CODE_FOR_muldf3; + if (HAVE_mulsf3) + smul_optab->handlers[(int) SFmode].insn_code = CODE_FOR_mulsf3; + sdiv_optab->handlers[(int) QImode].insn_code = CODE_FOR_divqi3; + udiv_optab->handlers[(int) QImode].insn_code = CODE_FOR_udivqi3; + if (HAVE_divdf3) + flodiv_optab->handlers[(int) DFmode].insn_code = CODE_FOR_divdf3; + if (HAVE_divsf3) + flodiv_optab->handlers[(int) SFmode].insn_code = CODE_FOR_divsf3; + sdivmod_optab->handlers[(int) SImode].insn_code = CODE_FOR_divmodsi4; + sdivmod_optab->handlers[(int) HImode].insn_code = CODE_FOR_divmodhi4; + udivmod_optab->handlers[(int) SImode].insn_code = CODE_FOR_udivmodsi4; + udivmod_optab->handlers[(int) HImode].insn_code = CODE_FOR_udivmodhi4; + and_optab->handlers[(int) SImode].insn_code = CODE_FOR_andsi3; + and_optab->handlers[(int) HImode].insn_code = CODE_FOR_andhi3; + and_optab->handlers[(int) QImode].insn_code = CODE_FOR_andqi3; + ior_optab->handlers[(int) SImode].insn_code = CODE_FOR_iorsi3; + ior_optab->handlers[(int) HImode].insn_code = CODE_FOR_iorhi3; + ior_optab->handlers[(int) QImode].insn_code = CODE_FOR_iorqi3; + xor_optab->handlers[(int) SImode].insn_code = CODE_FOR_xorsi3; + xor_optab->handlers[(int) HImode].insn_code = CODE_FOR_xorhi3; + xor_optab->handlers[(int) QImode].insn_code = CODE_FOR_xorqi3; + neg_optab->handlers[(int) DImode].insn_code = CODE_FOR_negdi2; + neg_optab->handlers[(int) SImode].insn_code = CODE_FOR_negsi2; + neg_optab->handlers[(int) HImode].insn_code = CODE_FOR_neghi2; + neg_optab->handlers[(int) QImode].insn_code = CODE_FOR_negqi2; + if (HAVE_negsf2) + neg_optab->handlers[(int) SFmode].insn_code = CODE_FOR_negsf2; + if (HAVE_negdf2) + neg_optab->handlers[(int) DFmode].insn_code = CODE_FOR_negdf2; + if (HAVE_abssf2) + abs_optab->handlers[(int) SFmode].insn_code = CODE_FOR_abssf2; + if (HAVE_absdf2) + abs_optab->handlers[(int) DFmode].insn_code = CODE_FOR_absdf2; + if (HAVE_sqrtsf2) + sqrt_optab->handlers[(int) SFmode].insn_code = CODE_FOR_sqrtsf2; + if (HAVE_sqrtdf2) + sqrt_optab->handlers[(int) DFmode].insn_code = CODE_FOR_sqrtdf2; + if (HAVE_sindf2) + sin_optab->handlers[(int) DFmode].insn_code = CODE_FOR_sindf2; + if (HAVE_sinsf2) + sin_optab->handlers[(int) SFmode].insn_code = CODE_FOR_sinsf2; + if (HAVE_cosdf2) + cos_optab->handlers[(int) DFmode].insn_code = CODE_FOR_cosdf2; + if (HAVE_cossf2) + cos_optab->handlers[(int) SFmode].insn_code = CODE_FOR_cossf2; + one_cmpl_optab->handlers[(int) SImode].insn_code = CODE_FOR_one_cmplsi2; + one_cmpl_optab->handlers[(int) HImode].insn_code = CODE_FOR_one_cmplhi2; + one_cmpl_optab->handlers[(int) QImode].insn_code = CODE_FOR_one_cmplqi2; + ashl_optab->handlers[(int) DImode].insn_code = CODE_FOR_ashldi3; + ashl_optab->handlers[(int) SImode].insn_code = CODE_FOR_ashlsi3; + ashl_optab->handlers[(int) HImode].insn_code = CODE_FOR_ashlhi3; + ashl_optab->handlers[(int) QImode].insn_code = CODE_FOR_ashlqi3; + ashr_optab->handlers[(int) DImode].insn_code = CODE_FOR_ashrdi3; + ashr_optab->handlers[(int) SImode].insn_code = CODE_FOR_ashrsi3; + ashr_optab->handlers[(int) HImode].insn_code = CODE_FOR_ashrhi3; + ashr_optab->handlers[(int) QImode].insn_code = CODE_FOR_ashrqi3; + lshr_optab->handlers[(int) DImode].insn_code = CODE_FOR_lshrdi3; + lshr_optab->handlers[(int) SImode].insn_code = CODE_FOR_lshrsi3; + lshr_optab->handlers[(int) HImode].insn_code = CODE_FOR_lshrhi3; + lshr_optab->handlers[(int) QImode].insn_code = CODE_FOR_lshrqi3; + rotl_optab->handlers[(int) SImode].insn_code = CODE_FOR_rotlsi3; + rotl_optab->handlers[(int) HImode].insn_code = CODE_FOR_rotlhi3; + rotl_optab->handlers[(int) QImode].insn_code = CODE_FOR_rotlqi3; + rotr_optab->handlers[(int) SImode].insn_code = CODE_FOR_rotrsi3; + rotr_optab->handlers[(int) HImode].insn_code = CODE_FOR_rotrhi3; + rotr_optab->handlers[(int) QImode].insn_code = CODE_FOR_rotrqi3; + setcc_gen_code[(int) EQ] = CODE_FOR_seq; + setcc_gen_code[(int) NE] = CODE_FOR_sne; + setcc_gen_code[(int) GT] = CODE_FOR_sgt; + setcc_gen_code[(int) GTU] = CODE_FOR_sgtu; + setcc_gen_code[(int) LT] = CODE_FOR_slt; + setcc_gen_code[(int) LTU] = CODE_FOR_sltu; + setcc_gen_code[(int) GE] = CODE_FOR_sge; + setcc_gen_code[(int) GEU] = CODE_FOR_sgeu; + setcc_gen_code[(int) LE] = CODE_FOR_sle; + setcc_gen_code[(int) LEU] = CODE_FOR_sleu; + bcc_gen_fctn[(int) EQ] = gen_beq; + bcc_gen_fctn[(int) NE] = gen_bne; + bcc_gen_fctn[(int) GT] = gen_bgt; + bcc_gen_fctn[(int) GTU] = gen_bgtu; + bcc_gen_fctn[(int) LT] = gen_blt; + bcc_gen_fctn[(int) LTU] = gen_bltu; + bcc_gen_fctn[(int) GE] = gen_bge; + bcc_gen_fctn[(int) GEU] = gen_bgeu; + bcc_gen_fctn[(int) LE] = gen_ble; + bcc_gen_fctn[(int) LEU] = gen_bleu; + movstr_optab[(int) SImode] = CODE_FOR_movstrsi; + ffs_optab->handlers[(int) SImode].insn_code = CODE_FOR_ffssi2; + ffs_optab->handlers[(int) HImode].insn_code = CODE_FOR_ffshi2; + strlen_optab->handlers[(int) SImode].insn_code = CODE_FOR_strlensi; +} diff --git a/gnu/usr.bin/gcc2/i386/insn-output.c b/gnu/usr.bin/gcc2/i386/insn-output.c new file mode 100644 index 00000000000..c39c4ffcc10 --- /dev/null +++ b/gnu/usr.bin/gcc2/i386/insn-output.c @@ -0,0 +1,5899 @@ +/* Generated automatically by the program `genoutput' +from the machine description file `md'. */ + +#include "config.h" +#include "rtl.h" +#include "regs.h" +#include "hard-reg-set.h" +#include "real.h" +#include "insn-config.h" + +#include "conditions.h" +#include "insn-flags.h" +#include "insn-attr.h" + +#include "insn-codes.h" + +#include "recog.h" + +#include <stdio.h> +#include "output.h" + +static char * +output_0 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (REG_P (operands[0])) + return AS2 (test%L0,%0,%0); + + operands[1] = const0_rtx; + return AS2 (cmp%L0,%1,%0); +} +} + +static char * +output_2 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (REG_P (operands[0])) + return AS2 (test%W0,%0,%0); + + operands[1] = const0_rtx; + return AS2 (cmp%W0,%1,%0); +} +} + +static char * +output_4 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (REG_P (operands[0])) + return AS2 (test%B0,%0,%0); + + operands[1] = const0_rtx; + return AS2 (cmp%B0,%1,%0); +} +} + +static char * +output_6 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (! STACK_TOP_P (operands[0])) + abort (); + + output_asm_insn ("ftst", operands); + + if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG)) + output_asm_insn (AS1 (fstp,%y0), operands); + + return (char *) output_fp_cc0_set (insn); +} +} + +static char * +output_8 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (! STACK_TOP_P (operands[0])) + abort (); + + output_asm_insn ("ftst", operands); + + if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG)) + output_asm_insn (AS1 (fstp,%y0), operands); + + return (char *) output_fp_cc0_set (insn); +} +} + +static char * +output_10 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (CONSTANT_P (operands[0]) || GET_CODE (operands[1]) == MEM) + { + cc_status.flags |= CC_REVERSED; + return AS2 (cmp%L0,%0,%1); + } + return AS2 (cmp%L0,%1,%0); +} +} + +static char * +output_12 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (CONSTANT_P (operands[0]) || GET_CODE (operands[1]) == MEM) + { + cc_status.flags |= CC_REVERSED; + return AS2 (cmp%W0,%0,%1); + } + return AS2 (cmp%W0,%1,%0); +} +} + +static char * +output_14 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (CONSTANT_P (operands[0]) || GET_CODE (operands[1]) == MEM) + { + cc_status.flags |= CC_REVERSED; + return AS2 (cmp%B0,%0,%1); + } + return AS2 (cmp%B0,%1,%0); +} +} + +static char * +output_16 (operands, insn) + rtx *operands; + rtx insn; +{ + return (char *) output_float_compare (insn, operands); +} + +static char * +output_17 (operands, insn) + rtx *operands; + rtx insn; +{ + return (char *) output_float_compare (insn, operands); +} + +static char * +output_18 (operands, insn) + rtx *operands; + rtx insn; +{ + return (char *) output_float_compare (insn, operands); +} + +static char * +output_19 (operands, insn) + rtx *operands; + rtx insn; +{ + return (char *) output_float_compare (insn, operands); +} + +static char * +output_20 (operands, insn) + rtx *operands; + rtx insn; +{ + return (char *) output_float_compare (insn, operands); +} + +static char * +output_21 (operands, insn) + rtx *operands; + rtx insn; +{ + return (char *) output_float_compare (insn, operands); +} + +static char * +output_22 (operands, insn) + rtx *operands; + rtx insn; +{ + return (char *) output_float_compare (insn, operands); +} + +static char * +output_23 (operands, insn) + rtx *operands; + rtx insn; +{ + return (char *) output_float_compare (insn, operands); +} + +static char * +output_24 (operands, insn) + rtx *operands; + rtx insn; +{ + return (char *) output_float_compare (insn, operands); +} + +static char * +output_25 (operands, insn) + rtx *operands; + rtx insn; +{ + return (char *) output_float_compare (insn, operands); +} + +static char * +output_32 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + /* For small integers, we may actually use testb. */ + if (GET_CODE (operands[1]) == CONST_INT + && ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])) + && (! REG_P (operands[0]) || QI_REG_P (operands[0]))) + { + /* We may set the sign bit spuriously. */ + + if ((INTVAL (operands[1]) & ~0xff) == 0) + { + cc_status.flags |= CC_NOT_NEGATIVE; + return AS2 (test%B0,%1,%b0); + } + + if ((INTVAL (operands[1]) & ~0xff00) == 0) + { + cc_status.flags |= CC_NOT_NEGATIVE; + operands[1] = GEN_INT (INTVAL (operands[1]) >> 8); + + if (QI_REG_P (operands[0])) + return AS2 (test%B0,%1,%h0); + else + { + operands[0] = adj_offsettable_operand (operands[0], 1); + return AS2 (test%B0,%1,%b0); + } + } + + if (GET_CODE (operands[0]) == MEM + && (INTVAL (operands[1]) & ~0xff0000) == 0) + { + cc_status.flags |= CC_NOT_NEGATIVE; + operands[1] = GEN_INT (INTVAL (operands[1]) >> 16); + operands[0] = adj_offsettable_operand (operands[0], 2); + return AS2 (test%B0,%1,%b0); + } + + if (GET_CODE (operands[0]) == MEM + && (INTVAL (operands[1]) & ~0xff000000) == 0) + { + operands[1] = GEN_INT ((INTVAL (operands[1]) >> 24) & 0xff); + operands[0] = adj_offsettable_operand (operands[0], 3); + return AS2 (test%B0,%1,%b0); + } + } + + if (CONSTANT_P (operands[1]) || GET_CODE (operands[0]) == MEM) + return AS2 (test%L0,%1,%0); + + return AS2 (test%L1,%0,%1); +} +} + +static char * +output_33 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (GET_CODE (operands[1]) == CONST_INT + && ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])) + && (! REG_P (operands[0]) || QI_REG_P (operands[0]))) + { + if ((INTVAL (operands[1]) & 0xff00) == 0) + { + /* ??? This might not be necessary. */ + if (INTVAL (operands[1]) & 0xffff0000) + operands[1] = GEN_INT (INTVAL (operands[1]) & 0xff); + + /* We may set the sign bit spuriously. */ + cc_status.flags |= CC_NOT_NEGATIVE; + return AS2 (test%B0,%1,%b0); + } + + if ((INTVAL (operands[1]) & 0xff) == 0) + { + operands[1] = GEN_INT ((INTVAL (operands[1]) >> 8) & 0xff); + + if (QI_REG_P (operands[0])) + return AS2 (test%B0,%1,%h0); + else + { + operands[0] = adj_offsettable_operand (operands[0], 1); + return AS2 (test%B0,%1,%b0); + } + } + } + + if (CONSTANT_P (operands[1]) || GET_CODE (operands[0]) == MEM) + return AS2 (test%W0,%1,%0); + + return AS2 (test%W1,%0,%1); +} +} + +static char * +output_34 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (CONSTANT_P (operands[1]) || GET_CODE (operands[0]) == MEM) + return AS2 (test%B0,%1,%0); + + return AS2 (test%B1,%0,%1); +} +} + +static char * +output_38 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + rtx link; + if (operands[1] == const0_rtx && REG_P (operands[0])) + return AS2 (xor%L0,%0,%0); + + if (operands[1] == const1_rtx + && (link = find_reg_note (insn, REG_WAS_0, 0)) + /* Make sure the insn that stored the 0 is still present. */ + && ! INSN_DELETED_P (XEXP (link, 0)) + && GET_CODE (XEXP (link, 0)) != NOTE + /* Make sure cross jumping didn't happen here. */ + && no_labels_between_p (XEXP (link, 0), insn) + /* Make sure the reg hasn't been clobbered. */ + && ! reg_set_between_p (operands[0], XEXP (link, 0), insn)) + /* Fastest way to change a 0 to a 1. */ + return AS1 (inc%L0,%0); + + return AS2 (mov%L0,%1,%0); +} +} + +static char * +output_40 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + rtx link; + if (REG_P (operands[0]) && operands[1] == const0_rtx) + return AS2 (xor%L0,%k0,%k0); + + if (REG_P (operands[0]) && operands[1] == const1_rtx + && (link = find_reg_note (insn, REG_WAS_0, 0)) + /* Make sure the insn that stored the 0 is still present. */ + && ! INSN_DELETED_P (XEXP (link, 0)) + && GET_CODE (XEXP (link, 0)) != NOTE + /* Make sure cross jumping didn't happen here. */ + && no_labels_between_p (XEXP (link, 0), insn) + /* Make sure the reg hasn't been clobbered. */ + && ! reg_set_between_p (operands[0], XEXP (link, 0), insn)) + /* Fastest way to change a 0 to a 1. */ + return AS1 (inc%L0,%k0); + + if (REG_P (operands[0])) + { + if (REG_P (operands[1])) + return AS2 (mov%L0,%k1,%k0); + else if (CONSTANT_P (operands[1])) + return AS2 (mov%L0,%1,%k0); + } + + return AS2 (mov%W0,%1,%0); +} +} + +static char * +output_41 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + rtx link; + if (operands[1] == const0_rtx && REG_P (operands[0])) + return AS2 (xor%W0,%0,%0); + + if (operands[1] == const1_rtx + && (link = find_reg_note (insn, REG_WAS_0, 0)) + /* Make sure the insn that stored the 0 is still present. */ + && ! INSN_DELETED_P (XEXP (link, 0)) + && GET_CODE (XEXP (link, 0)) != NOTE + /* Make sure cross jumping didn't happen here. */ + && no_labels_between_p (XEXP (link, 0), insn) + /* Make sure the reg hasn't been clobbered. */ + && ! reg_set_between_p (operands[0], XEXP (link, 0), insn)) + /* Fastest way to change a 0 to a 1. */ + return AS1 (inc%W0,%0); + + return AS2 (mov%W0,%1,%0); +} +} + +static char * +output_42 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + operands[1] = gen_rtx (REG, HImode, REGNO (operands[1])); + return AS1 (push%W0,%1); +} +} + +static char * +output_43 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + rtx link; + if (operands[1] == const0_rtx && REG_P (operands[0])) + return AS2 (xor%B0,%0,%0); + + if (operands[1] == const1_rtx + && (link = find_reg_note (insn, REG_WAS_0, 0)) + /* Make sure the insn that stored the 0 is still present. */ + && ! INSN_DELETED_P (XEXP (link, 0)) + && GET_CODE (XEXP (link, 0)) != NOTE + /* Make sure cross jumping didn't happen here. */ + && no_labels_between_p (XEXP (link, 0), insn) + /* Make sure the reg hasn't been clobbered. */ + && ! reg_set_between_p (operands[0], XEXP (link, 0), insn)) + /* Fastest way to change a 0 to a 1. */ + return AS1 (inc%B0,%0); + + /* If mov%B0 isn't allowed for one of these regs, use mov%L0. */ + if (NON_QI_REG_P (operands[0]) || NON_QI_REG_P (operands[1])) + return (AS2 (mov%L0,%k1,%k0)); + + return (AS2 (mov%B0,%1,%0)); +} +} + +static char * +output_44 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + rtx link; + if (operands[1] == const0_rtx && REG_P (operands[0])) + return AS2 (xor%B0,%0,%0); + + if (operands[1] == const1_rtx + && (link = find_reg_note (insn, REG_WAS_0, 0)) + /* Make sure the insn that stored the 0 is still present. */ + && ! INSN_DELETED_P (XEXP (link, 0)) + && GET_CODE (XEXP (link, 0)) != NOTE + /* Make sure cross jumping didn't happen here. */ + && no_labels_between_p (XEXP (link, 0), insn) + /* Make sure the reg hasn't been clobbered. */ + && ! reg_set_between_p (operands[0], XEXP (link, 0), insn)) + /* Fastest way to change a 0 to a 1. */ + return AS1 (inc%B0,%0); + + /* If mov%B0 isn't allowed for one of these regs, use mov%W0. */ + if (NON_QI_REG_P (operands[0]) || NON_QI_REG_P (operands[1])) + { + abort (); + return (AS2 (mov%L0,%k1,%k0)); + } + + return AS2 (mov%B0,%1,%0); +} +} + +static char * +output_45 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (STACK_REG_P (operands[1])) + { + rtx xops[3]; + + if (! STACK_TOP_P (operands[1])) + abort (); + + xops[0] = AT_SP (SFmode); + xops[1] = GEN_INT (4); + xops[2] = stack_pointer_rtx; + + output_asm_insn (AS2 (sub%L2,%1,%2), xops); + + if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG)) + output_asm_insn (AS1 (fstp%S0,%0), xops); + else + output_asm_insn (AS1 (fst%S0,%0), xops); + RET; + } + return AS1 (push%L1,%1); +} +} + +static char * +output_46 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0; + + /* First handle a `pop' insn or a `fld %st(0)' */ + + if (STACK_TOP_P (operands[0]) && STACK_TOP_P (operands[1])) + { + if (stack_top_dies) + return AS1 (fstp,%y0); + else + return AS1 (fld,%y0); + } + + /* Handle a transfer between the 387 and a 386 register */ + + if (STACK_TOP_P (operands[0]) && NON_STACK_REG_P (operands[1])) + { + output_op_from_reg (operands[1], AS1 (fld%z0,%y1)); + RET; + } + + if (STACK_TOP_P (operands[1]) && NON_STACK_REG_P (operands[0])) + { + output_to_reg (operands[0], stack_top_dies); + RET; + } + + /* Handle other kinds of writes from the 387 */ + + if (STACK_TOP_P (operands[1])) + { + if (stack_top_dies) + return AS1 (fstp%z0,%y0); + else + return AS1 (fst%z0,%y0); + } + + /* Handle other kinds of reads to the 387 */ + + if (STACK_TOP_P (operands[0]) && GET_CODE (operands[1]) == CONST_DOUBLE) + return (char *) output_move_const_single (operands); + + if (STACK_TOP_P (operands[0])) + return AS1 (fld%z1,%y1); + + /* Handle all SFmode moves not involving the 387 */ + + return (char *) singlemove_string (operands); +} +} + +static char * +output_47 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (STACK_REG_P (operands[1])) + { + rtx xops[3]; + + xops[0] = AT_SP (SFmode); + xops[1] = GEN_INT (8); + xops[2] = stack_pointer_rtx; + + output_asm_insn (AS2 (sub%L2,%1,%2), xops); + + if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG)) + output_asm_insn (AS1 (fstp%Q0,%0), xops); + else + output_asm_insn (AS1 (fst%Q0,%0), xops); + + RET; + } + else + return (char *) output_move_double (operands); +} +} + +static char * +output_48 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (STACK_TOP_P (operands[0])) + return AS1 (fxch,%1); + else + return AS1 (fxch,%0); +} +} + +static char * +output_49 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0; + + /* First handle a `pop' insn or a `fld %st(0)' */ + + if (STACK_TOP_P (operands[0]) && STACK_TOP_P (operands[1])) + { + if (stack_top_dies) + return AS1 (fstp,%y0); + else + return AS1 (fld,%y0); + } + + /* Handle a transfer between the 387 and a 386 register */ + + if (STACK_TOP_P (operands[0]) && NON_STACK_REG_P (operands[1])) + { + output_op_from_reg (operands[1], AS1 (fld%z0,%y1)); + RET; + } + + if (STACK_TOP_P (operands[1]) && NON_STACK_REG_P (operands[0])) + { + output_to_reg (operands[0], stack_top_dies); + RET; + } + + /* Handle other kinds of writes from the 387 */ + + if (STACK_TOP_P (operands[1])) + { + if (stack_top_dies) + return AS1 (fstp%z0,%y0); + else + return AS1 (fst%z0,%y0); + } + + /* Handle other kinds of reads to the 387 */ + + if (STACK_TOP_P (operands[0]) && GET_CODE (operands[1]) == CONST_DOUBLE) + return (char *) output_move_const_single (operands); + + if (STACK_TOP_P (operands[0])) + return AS1 (fld%z1,%y1); + + /* Handle all DFmode moves not involving the 387 */ + + return (char *) output_move_double (operands); +} +} + +static char * +output_50 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + return (char *) output_move_double (operands); +} +} + +static char * +output_51 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + return (char *) output_move_double (operands); +} +} + +static char * +output_52 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if ((TARGET_486 || REGNO (operands[0]) == 0) + && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])) + { + rtx xops[2]; + xops[0] = operands[0]; + xops[1] = GEN_INT (0xffff); + output_asm_insn (AS2 (and%L0,%1,%k0), xops); + RET; + } + +#ifdef INTEL_SYNTAX + return AS2 (movzx,%1,%0); +#else + return AS2 (movz%W0%L0,%1,%0); +#endif +} +} + +static char * +output_53 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if ((TARGET_486 || REGNO (operands[0]) == 0) + && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])) + { + rtx xops[2]; + xops[0] = operands[0]; + xops[1] = GEN_INT (0xff); + output_asm_insn (AS2 (and%L0,%1,%k0), xops); + RET; + } + +#ifdef INTEL_SYNTAX + return AS2 (movzx,%1,%0); +#else + return AS2 (movz%B0%W0,%1,%0); +#endif +} +} + +static char * +output_54 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if ((TARGET_486 || REGNO (operands[0]) == 0) + && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])) + { + rtx xops[2]; + xops[0] = operands[0]; + xops[1] = GEN_INT (0xff); + output_asm_insn (AS2 (and%L0,%1,%k0), xops); + RET; + } + +#ifdef INTEL_SYNTAX + return AS2 (movzx,%1,%0); +#else + return AS2 (movz%B0%L0,%1,%0); +#endif +} +} + +static char * +output_55 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); + return AS2 (xor%L0,%0,%0); +} +} + +static char * +output_56 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (REGNO (operands[0]) == 0) + { + /* This used to be cwtl, but that extends HI to SI somehow. */ +#ifdef INTEL_SYNTAX + return "cdq"; +#else + return "cltd"; +#endif + } + + operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); + output_asm_insn (AS2 (mov%L0,%0,%1), operands); + + operands[0] = GEN_INT (31); + return AS2 (sar%L1,%0,%1); +} +} + +static char * +output_57 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (REGNO (operands[0]) == 0 + && REG_P (operands[1]) && REGNO (operands[1]) == 0) +#ifdef INTEL_SYNTAX + return "cwde"; +#else + return "cwtl"; +#endif + +#ifdef INTEL_SYNTAX + return AS2 (movsx,%1,%0); +#else + return AS2 (movs%W0%L0,%1,%0); +#endif +} +} + +static char * +output_58 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (REGNO (operands[0]) == 0 + && REG_P (operands[1]) && REGNO (operands[1]) == 0) + return "cbtw"; + +#ifdef INTEL_SYNTAX + return AS2 (movsx,%1,%0); +#else + return AS2 (movs%B0%W0,%1,%0); +#endif +} +} + +static char * +output_59 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ +#ifdef INTEL_SYNTAX + return AS2 (movsx,%1,%0); +#else + return AS2 (movs%B0%L0,%1,%0); +#endif +} +} + +static char * +output_60 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0; + + if (NON_STACK_REG_P (operands[1])) + { + output_op_from_reg (operands[1], AS1 (fld%z0,%y1)); + RET; + } + + if (NON_STACK_REG_P (operands[0])) + { + output_to_reg (operands[0], stack_top_dies); + RET; + } + + if (STACK_TOP_P (operands[0])) + return AS1 (fld%z1,%y1); + + if (GET_CODE (operands[0]) == MEM) + { + if (stack_top_dies) + return AS1 (fstp%z0,%y0); + else + return AS1 (fst%z0,%y0); + } + + abort (); +} +} + +static char * +output_62 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0; + + if (GET_CODE (operands[0]) == MEM) + { + if (stack_top_dies) + return AS1 (fstp%z0,%0); + else + return AS1 (fst%z0,%0); + } + else if (STACK_TOP_P (operands[0])) + { + output_asm_insn (AS1 (fstp%z2,%y2), operands); + return AS1 (fld%z2,%y2); + } + else + abort (); +} +} + +static char * +output_67 (operands, insn) + rtx *operands; + rtx insn; +{ + return (char *) output_fix_trunc (insn, operands); +} + +static char * +output_68 (operands, insn) + rtx *operands; + rtx insn; +{ + return (char *) output_fix_trunc (insn, operands); +} + +static char * +output_71 (operands, insn) + rtx *operands; + rtx insn; +{ + return (char *) output_fix_trunc (insn, operands); +} + +static char * +output_72 (operands, insn) + rtx *operands; + rtx insn; +{ + return (char *) output_fix_trunc (insn, operands); +} + +static char * +output_77 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (NON_STACK_REG_P (operands[1])) + { + output_op_from_reg (operands[1], AS1 (fild%z0,%1)); + RET; + } + else if (GET_CODE (operands[1]) == MEM) + return AS1 (fild%z1,%1); + else + abort (); +} +} + +static char * +output_78 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (NON_STACK_REG_P (operands[1])) + { + output_op_from_reg (operands[1], AS1 (fild%z0,%1)); + RET; + } + else if (GET_CODE (operands[1]) == MEM) + return AS1 (fild%z1,%1); + else + abort (); +} +} + +static char * +output_79 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (NON_STACK_REG_P (operands[1])) + { + output_op_from_reg (operands[1], AS1 (fild%z0,%1)); + RET; + } + else if (GET_CODE (operands[1]) == MEM) + return AS1 (fild%z1,%1); + else + abort (); +} +} + +static char * +output_80 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (NON_STACK_REG_P (operands[1])) + { + output_op_from_reg (operands[1], AS1 (fild%z0,%1)); + RET; + } + else if (GET_CODE (operands[1]) == MEM) + return AS1 (fild%z1,%1); + else + abort (); +} +} + +static char * +output_81 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + rtx low[3], high[3]; + + CC_STATUS_INIT; + + split_di (operands, 3, low, high); + + if (GET_CODE (low[2]) != CONST_INT || INTVAL (low[2]) != 0) + { + output_asm_insn (AS2 (add%L0,%2,%0), low); + output_asm_insn (AS2 (adc%L0,%2,%0), high); + } + else + output_asm_insn (AS2 (add%L0,%2,%0), high); + RET; +} +} + +static char * +output_82 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (REG_P (operands[0]) && REGNO (operands[0]) != REGNO (operands[1])) + { + if (REG_P (operands[2]) && REGNO (operands[0]) == REGNO (operands[2])) + return AS2 (add%L0,%1,%0); + + if (! TARGET_486 || ! REG_P (operands[2])) + { + CC_STATUS_INIT; + + if (operands[2] == stack_pointer_rtx) + { + rtx temp; + + temp = operands[1]; + operands[1] = operands[2]; + operands[2] = temp; + } + if (operands[2] != stack_pointer_rtx) + { + operands[1] = SET_SRC (PATTERN (insn)); + return AS2 (lea%L0,%a1,%0); + } + } + + output_asm_insn (AS2 (mov%L0,%1,%0), operands); + } + + if (operands[2] == const1_rtx) + return AS1 (inc%L0,%0); + + if (operands[2] == constm1_rtx) + return AS1 (dec%L0,%0); + + return AS2 (add%L0,%2,%0); +} +} + +static char * +output_83 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (operands[2] == const1_rtx) + return AS1 (inc%W0,%0); + + if (operands[2] == constm1_rtx) + return AS1 (dec%W0,%0); + + return AS2 (add%W0,%2,%0); +} +} + +static char * +output_84 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (operands[2] == const1_rtx) + return AS1 (inc%B0,%0); + + if (operands[2] == constm1_rtx) + return AS1 (dec%B0,%0); + + return AS2 (add%B0,%2,%0); +} +} + +static char * +output_85 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + CC_STATUS_INIT; + /* Adding a constant to a register is faster with an add. */ + /* ??? can this ever happen? */ + if (GET_CODE (operands[1]) == PLUS + && GET_CODE (XEXP (operands[1], 1)) == CONST_INT + && rtx_equal_p (operands[0], XEXP (operands[1], 0))) + { + operands[1] = XEXP (operands[1], 1); + + if (operands[1] == const1_rtx) + return AS1 (inc%L0,%0); + + if (operands[1] == constm1_rtx) + return AS1 (dec%L0,%0); + + return AS2 (add%L0,%1,%0); + } + return AS2 (lea%L0,%a1,%0); +} +} + +static char * +output_88 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + rtx low[3], high[3]; + + CC_STATUS_INIT; + + split_di (operands, 3, low, high); + + if (GET_CODE (low[2]) != CONST_INT || INTVAL (low[2]) != 0) + { + output_asm_insn (AS2 (sub%L0,%2,%0), low); + output_asm_insn (AS2 (sbb%L0,%2,%0), high); + } + else + output_asm_insn (AS2 (sub%L0,%2,%0), high); + + RET; +} +} + +static char * +output_89 (operands, insn) + rtx *operands; + rtx insn; +{ + return AS2 (sub%L0,%2,%0); +} + +static char * +output_90 (operands, insn) + rtx *operands; + rtx insn; +{ + return AS2 (sub%W0,%2,%0); +} + +static char * +output_91 (operands, insn) + rtx *operands; + rtx insn; +{ + return AS2 (sub%B0,%2,%0); +} + +static char * +output_94 (operands, insn) + rtx *operands; + rtx insn; +{ + return AS2 (imul%W0,%2,%0); +} + +static char * +output_95 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (GET_CODE (operands[1]) == REG + && REGNO (operands[1]) == REGNO (operands[0]) + && (GET_CODE (operands[2]) == MEM || GET_CODE (operands[2]) == REG)) + /* Assembler has weird restrictions. */ + return AS2 (imul%W0,%2,%0); + return AS3 (imul%W0,%2,%1,%0); +} +} + +static char * +output_96 (operands, insn) + rtx *operands; + rtx insn; +{ + return AS2 (imul%L0,%2,%0); +} + +static char * +output_97 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (GET_CODE (operands[1]) == REG + && REGNO (operands[1]) == REGNO (operands[0]) + && (GET_CODE (operands[2]) == MEM || GET_CODE (operands[2]) == REG)) + /* Assembler has weird restrictions. */ + return AS2 (imul%L0,%2,%0); + return AS3 (imul%L0,%2,%1,%0); +} +} + +static char * +output_105 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ +#ifdef INTEL_SYNTAX + output_asm_insn ("cdq", operands); +#else + output_asm_insn ("cltd", operands); +#endif + return AS1 (idiv%L0,%2); +} +} + +static char * +output_107 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + output_asm_insn (AS2 (xor%L3,%3,%3), operands); + return AS1 (div%L0,%2); +} +} + +static char * +output_108 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + output_asm_insn (AS2 (xor%W0,%3,%3), operands); + return AS1 (div%W0,%2); +} +} + +static char * +output_109 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (GET_CODE (operands[2]) == CONST_INT + && ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))) + { + if (INTVAL (operands[2]) == 0xffff && REG_P (operands[0]) + && (! REG_P (operands[1]) + || REGNO (operands[0]) != 0 || REGNO (operands[1]) != 0) + && (! TARGET_486 || ! rtx_equal_p (operands[0], operands[1]))) + { + /* ??? tege: Should forget CC_STATUS only if we clobber a + remembered operand. Fix that later. */ + CC_STATUS_INIT; +#ifdef INTEL_SYNTAX + return AS2 (movzx,%w1,%0); +#else + return AS2 (movz%W0%L0,%w1,%0); +#endif + } + + if (INTVAL (operands[2]) == 0xff && REG_P (operands[0]) + && !(REG_P (operands[1]) && NON_QI_REG_P (operands[1])) + && (! REG_P (operands[1]) + || REGNO (operands[0]) != 0 || REGNO (operands[1]) != 0) + && (! TARGET_486 || ! rtx_equal_p (operands[0], operands[1]))) + { + /* ??? tege: Should forget CC_STATUS only if we clobber a + remembered operand. Fix that later. */ + CC_STATUS_INIT; +#ifdef INTEL_SYNTAX + return AS2 (movzx,%b1,%0); +#else + return AS2 (movz%B0%L0,%b1,%0); +#endif + } + + if (QI_REG_P (operands[0]) && ~(INTVAL (operands[2]) | 0xff) == 0) + { + CC_STATUS_INIT; + + if (INTVAL (operands[2]) == 0xffffff00) + { + operands[2] = const0_rtx; + return AS2 (mov%B0,%2,%b0); + } + + operands[2] = GEN_INT (INTVAL (operands[2]) & 0xff); + return AS2 (and%B0,%2,%b0); + } + + if (QI_REG_P (operands[0]) && ~(INTVAL (operands[2]) | 0xff00) == 0) + { + CC_STATUS_INIT; + + if (INTVAL (operands[2]) == 0xffff00ff) + { + operands[2] = const0_rtx; + return AS2 (mov%B0,%2,%h0); + } + + operands[2] = GEN_INT ((INTVAL (operands[2]) >> 8) & 0xff); + return AS2 (and%B0,%2,%h0); + } + + if (GET_CODE (operands[0]) == MEM && INTVAL (operands[2]) == 0xffff0000) + { + operands[2] = const0_rtx; + return AS2 (mov%W0,%2,%w0); + } + } + + return AS2 (and%L0,%2,%0); +} +} + +static char * +output_110 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (GET_CODE (operands[2]) == CONST_INT + && ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))) + { + /* Can we ignore the upper byte? */ + if ((! REG_P (operands[0]) || QI_REG_P (operands[0])) + && (INTVAL (operands[2]) & 0xff00) == 0xff00) + { + CC_STATUS_INIT; + + if ((INTVAL (operands[2]) & 0xff) == 0) + { + operands[2] = const0_rtx; + return AS2 (mov%B0,%2,%b0); + } + + operands[2] = GEN_INT (INTVAL (operands[2]) & 0xff); + return AS2 (and%B0,%2,%b0); + } + + /* Can we ignore the lower byte? */ + /* ??? what about offsettable memory references? */ + if (QI_REG_P (operands[0]) && (INTVAL (operands[2]) & 0xff) == 0xff) + { + CC_STATUS_INIT; + + if ((INTVAL (operands[2]) & 0xff00) == 0) + { + operands[2] = const0_rtx; + return AS2 (mov%B0,%2,%h0); + } + + operands[2] = GEN_INT ((INTVAL (operands[2]) >> 8) & 0xff); + return AS2 (and%B0,%2,%h0); + } + } + + return AS2 (and%W0,%2,%0); +} +} + +static char * +output_111 (operands, insn) + rtx *operands; + rtx insn; +{ + return AS2 (and%B0,%2,%0); +} + +static char * +output_112 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (GET_CODE (operands[2]) == CONST_INT + && ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))) + { + if ((! REG_P (operands[0]) || QI_REG_P (operands[0])) + && (INTVAL (operands[2]) & ~0xff) == 0) + { + CC_STATUS_INIT; + + if (INTVAL (operands[2]) == 0xff) + return AS2 (mov%B0,%2,%b0); + + return AS2 (or%B0,%2,%b0); + } + + if (QI_REG_P (operands[0]) && (INTVAL (operands[2]) & ~0xff00) == 0) + { + CC_STATUS_INIT; + operands[2] = GEN_INT (INTVAL (operands[2]) >> 8); + + if (INTVAL (operands[2]) == 0xff) + return AS2 (mov%B0,%2,%h0); + + return AS2 (or%B0,%2,%h0); + } + } + + return AS2 (or%L0,%2,%0); +} +} + +static char * +output_113 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (GET_CODE (operands[2]) == CONST_INT + && ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))) + { + /* Can we ignore the upper byte? */ + if ((! REG_P (operands[0]) || QI_REG_P (operands[0])) + && (INTVAL (operands[2]) & 0xff00) == 0) + { + CC_STATUS_INIT; + if (INTVAL (operands[2]) & 0xffff0000) + operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffff); + + if (INTVAL (operands[2]) == 0xff) + return AS2 (mov%B0,%2,%b0); + + return AS2 (or%B0,%2,%b0); + } + + /* Can we ignore the lower byte? */ + /* ??? what about offsettable memory references? */ + if (QI_REG_P (operands[0]) + && (INTVAL (operands[2]) & 0xff) == 0) + { + CC_STATUS_INIT; + operands[2] = GEN_INT ((INTVAL (operands[2]) >> 8) & 0xff); + + if (INTVAL (operands[2]) == 0xff) + return AS2 (mov%B0,%2,%h0); + + return AS2 (or%B0,%2,%h0); + } + } + + return AS2 (or%W0,%2,%0); +} +} + +static char * +output_114 (operands, insn) + rtx *operands; + rtx insn; +{ + return AS2 (or%B0,%2,%0); +} + +static char * +output_115 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (GET_CODE (operands[2]) == CONST_INT + && ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))) + { + if ((! REG_P (operands[0]) || QI_REG_P (operands[0])) + && (INTVAL (operands[2]) & ~0xff) == 0) + { + CC_STATUS_INIT; + + if (INTVAL (operands[2]) == 0xff) + return AS1 (not%B0,%b0); + + return AS2 (xor%B0,%2,%b0); + } + + if (QI_REG_P (operands[0]) && (INTVAL (operands[2]) & ~0xff00) == 0) + { + CC_STATUS_INIT; + operands[2] = GEN_INT (INTVAL (operands[2]) >> 8); + + if (INTVAL (operands[2]) == 0xff) + return AS1 (not%B0,%h0); + + return AS2 (xor%B0,%2,%h0); + } + } + + return AS2 (xor%L0,%2,%0); +} +} + +static char * +output_116 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (GET_CODE (operands[2]) == CONST_INT + && ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))) + { + /* Can we ignore the upper byte? */ + if ((! REG_P (operands[0]) || QI_REG_P (operands[0])) + && (INTVAL (operands[2]) & 0xff00) == 0) + { + CC_STATUS_INIT; + if (INTVAL (operands[2]) & 0xffff0000) + operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffff); + + if (INTVAL (operands[2]) == 0xff) + return AS1 (not%B0,%b0); + + return AS2 (xor%B0,%2,%b0); + } + + /* Can we ignore the lower byte? */ + /* ??? what about offsettable memory references? */ + if (QI_REG_P (operands[0]) + && (INTVAL (operands[2]) & 0xff) == 0) + { + CC_STATUS_INIT; + operands[2] = GEN_INT ((INTVAL (operands[2]) >> 8) & 0xff); + + if (INTVAL (operands[2]) == 0xff) + return AS1 (not%B0,%h0); + + return AS2 (xor%B0,%2,%h0); + } + } + + return AS2 (xor%W0,%2,%0); +} +} + +static char * +output_117 (operands, insn) + rtx *operands; + rtx insn; +{ + return AS2 (xor%B0,%2,%0); +} + +static char * +output_118 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + rtx xops[2], low[1], high[1]; + + CC_STATUS_INIT; + + split_di (operands, 1, low, high); + xops[0] = const0_rtx; + xops[1] = high[0]; + + output_asm_insn (AS1 (neg%L0,%0), low); + output_asm_insn (AS2 (adc%L1,%0,%1), xops); + output_asm_insn (AS1 (neg%L0,%0), high); + RET; +} +} + +static char * +output_141 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + rtx xops[4], low[1], high[1]; + + CC_STATUS_INIT; + + split_di (operands, 1, low, high); + xops[0] = operands[2]; + xops[1] = const1_rtx; + xops[2] = low[0]; + xops[3] = high[0]; + + if (INTVAL (xops[0]) > 31) + { + output_asm_insn (AS2 (mov%L3,%2,%3), xops); /* Fast shift by 32 */ + output_asm_insn (AS2 (xor%L2,%2,%2), xops); + + if (INTVAL (xops[0]) > 32) + { + xops[0] = GEN_INT (INTVAL (xops[0]) - 32); + output_asm_insn (AS2 (sal%L3,%0,%3), xops); /* Remaining shift */ + } + } + else + { + output_asm_insn (AS3 (shld%L3,%0,%2,%3), xops); + output_asm_insn (AS2 (sal%L2,%0,%2), xops); + } + RET; +} +} + +static char * +output_142 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + rtx xops[4], low[1], high[1]; + + CC_STATUS_INIT; + + split_di (operands, 1, low, high); + xops[0] = operands[2]; + xops[1] = const1_rtx; + xops[2] = low[0]; + xops[3] = high[0]; + + output_asm_insn (AS2 (ror%B0,%1,%0), xops); /* shift count / 2 */ + + output_asm_insn (AS3_SHIFT_DOUBLE (shld%L3,%0,%2,%3), xops); + output_asm_insn (AS2 (sal%L2,%0,%2), xops); + output_asm_insn (AS3_SHIFT_DOUBLE (shld%L3,%0,%2,%3), xops); + output_asm_insn (AS2 (sal%L2,%0,%2), xops); + + xops[1] = GEN_INT (7); /* shift count & 1 */ + + output_asm_insn (AS2 (shr%B0,%1,%0), xops); + + output_asm_insn (AS3_SHIFT_DOUBLE (shld%L3,%0,%2,%3), xops); + output_asm_insn (AS2 (sal%L2,%0,%2), xops); + + RET; +} +} + +static char * +output_143 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (REG_P (operands[0]) && REGNO (operands[0]) != REGNO (operands[1])) + { + if (TARGET_486 && INTVAL (operands[2]) == 1) + { + output_asm_insn (AS2 (mov%L0,%1,%0), operands); + return AS2 (add%L0,%1,%0); + } + else + { + CC_STATUS_INIT; + + if (operands[1] == stack_pointer_rtx) + { + output_asm_insn (AS2 (mov%L0,%1,%0), operands); + operands[1] = operands[0]; + } + operands[1] = gen_rtx (MULT, SImode, operands[1], + GEN_INT (1 << INTVAL (operands[2]))); + return AS2 (lea%L0,%a1,%0); + } + } + + if (REG_P (operands[2])) + return AS2 (sal%L0,%b2,%0); + + if (REG_P (operands[0]) && operands[2] == const1_rtx) + return AS2 (add%L0,%0,%0); + + return AS2 (sal%L0,%2,%0); +} +} + +static char * +output_144 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (REG_P (operands[2])) + return AS2 (sal%W0,%b2,%0); + + if (REG_P (operands[0]) && operands[2] == const1_rtx) + return AS2 (add%W0,%0,%0); + + return AS2 (sal%W0,%2,%0); +} +} + +static char * +output_145 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (REG_P (operands[2])) + return AS2 (sal%B0,%b2,%0); + + if (REG_P (operands[0]) && operands[2] == const1_rtx) + return AS2 (add%B0,%0,%0); + + return AS2 (sal%B0,%2,%0); +} +} + +static char * +output_147 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + rtx xops[4], low[1], high[1]; + + CC_STATUS_INIT; + + split_di (operands, 1, low, high); + xops[0] = operands[2]; + xops[1] = const1_rtx; + xops[2] = low[0]; + xops[3] = high[0]; + + if (INTVAL (xops[0]) > 31) + { + xops[1] = GEN_INT (31); + output_asm_insn (AS2 (mov%L2,%3,%2), xops); + output_asm_insn (AS2 (sar%L3,%1,%3), xops); /* shift by 32 */ + + if (INTVAL (xops[0]) > 32) + { + xops[0] = GEN_INT (INTVAL (xops[0]) - 32); + output_asm_insn (AS2 (sar%L2,%0,%2), xops); /* Remaining shift */ + } + } + else + { + output_asm_insn (AS3 (shrd%L2,%0,%3,%2), xops); + output_asm_insn (AS2 (sar%L3,%0,%3), xops); + } + + RET; +} +} + +static char * +output_148 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + rtx xops[4], low[1], high[1]; + + CC_STATUS_INIT; + + split_di (operands, 1, low, high); + xops[0] = operands[2]; + xops[1] = const1_rtx; + xops[2] = low[0]; + xops[3] = high[0]; + + output_asm_insn (AS2 (ror%B0,%1,%0), xops); /* shift count / 2 */ + + output_asm_insn (AS3_SHIFT_DOUBLE (shrd%L2,%0,%3,%2), xops); + output_asm_insn (AS2 (sar%L3,%0,%3), xops); + output_asm_insn (AS3_SHIFT_DOUBLE (shrd%L2,%0,%3,%2), xops); + output_asm_insn (AS2 (sar%L3,%0,%3), xops); + + xops[1] = GEN_INT (7); /* shift count & 1 */ + + output_asm_insn (AS2 (shr%B0,%1,%0), xops); + + output_asm_insn (AS3_SHIFT_DOUBLE (shrd%L2,%0,%3,%2), xops); + output_asm_insn (AS2 (sar%L3,%0,%3), xops); + + RET; +} +} + +static char * +output_149 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (REG_P (operands[2])) + return AS2 (sar%L0,%b2,%0); + else + return AS2 (sar%L0,%2,%0); +} +} + +static char * +output_150 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (REG_P (operands[2])) + return AS2 (sar%W0,%b2,%0); + else + return AS2 (sar%W0,%2,%0); +} +} + +static char * +output_151 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (REG_P (operands[2])) + return AS2 (sar%B0,%b2,%0); + else + return AS2 (sar%B0,%2,%0); +} +} + +static char * +output_153 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + rtx xops[4], low[1], high[1]; + + CC_STATUS_INIT; + + split_di (operands, 1, low, high); + xops[0] = operands[2]; + xops[1] = const1_rtx; + xops[2] = low[0]; + xops[3] = high[0]; + + if (INTVAL (xops[0]) > 31) + { + output_asm_insn (AS2 (mov%L2,%3,%2), xops); /* Fast shift by 32 */ + output_asm_insn (AS2 (xor%L3,%3,%3), xops); + + if (INTVAL (xops[0]) > 32) + { + xops[0] = GEN_INT (INTVAL (xops[0]) - 32); + output_asm_insn (AS2 (shr%L2,%0,%2), xops); /* Remaining shift */ + } + } + else + { + output_asm_insn (AS3 (shrd%L2,%0,%3,%2), xops); + output_asm_insn (AS2 (shr%L3,%0,%3), xops); + } + + RET; +} +} + +static char * +output_154 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + rtx xops[4], low[1], high[1]; + + CC_STATUS_INIT; + + split_di (operands, 1, low, high); + xops[0] = operands[2]; + xops[1] = const1_rtx; + xops[2] = low[0]; + xops[3] = high[0]; + + output_asm_insn (AS2 (ror%B0,%1,%0), xops); /* shift count / 2 */ + + output_asm_insn (AS3_SHIFT_DOUBLE (shrd%L2,%0,%3,%2), xops); + output_asm_insn (AS2 (shr%L3,%0,%3), xops); + output_asm_insn (AS3_SHIFT_DOUBLE (shrd%L2,%0,%3,%2), xops); + output_asm_insn (AS2 (shr%L3,%0,%3), xops); + + xops[1] = GEN_INT (7); /* shift count & 1 */ + + output_asm_insn (AS2 (shr%B0,%1,%0), xops); + + output_asm_insn (AS3_SHIFT_DOUBLE (shrd%L2,%0,%3,%2), xops); + output_asm_insn (AS2 (shr%L3,%0,%3), xops); + + RET; +} +} + +static char * +output_155 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (REG_P (operands[2])) + return AS2 (shr%L0,%b2,%0); + else + return AS2 (shr%L0,%2,%1); +} +} + +static char * +output_156 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (REG_P (operands[2])) + return AS2 (shr%W0,%b2,%0); + else + return AS2 (shr%W0,%2,%0); +} +} + +static char * +output_157 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (REG_P (operands[2])) + return AS2 (shr%B0,%b2,%0); + else + return AS2 (shr%B0,%2,%0); +} +} + +static char * +output_158 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (REG_P (operands[2])) + return AS2 (rol%L0,%b2,%0); + else + return AS2 (rol%L0,%2,%0); +} +} + +static char * +output_159 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (REG_P (operands[2])) + return AS2 (rol%W0,%b2,%0); + else + return AS2 (rol%W0,%2,%0); +} +} + +static char * +output_160 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (REG_P (operands[2])) + return AS2 (rol%B0,%b2,%0); + else + return AS2 (rol%B0,%2,%0); +} +} + +static char * +output_161 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (REG_P (operands[2])) + return AS2 (ror%L0,%b2,%0); + else + return AS2 (ror%L0,%2,%0); +} +} + +static char * +output_162 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (REG_P (operands[2])) + return AS2 (ror%W0,%b2,%0); + else + return AS2 (ror%W0,%2,%0); +} +} + +static char * +output_163 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (REG_P (operands[2])) + return AS2 (ror%B0,%b2,%0); + else + return AS2 (ror%B0,%2,%0); +} +} + +static char * +output_164 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + CC_STATUS_INIT; + + if (INTVAL (operands[3]) == 1) + return AS2 (bts%L0,%2,%0); + else + return AS2 (btr%L0,%2,%0); +} +} + +static char * +output_165 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + CC_STATUS_INIT; + + return AS2 (btc%L0,%1,%0); +} +} + +static char * +output_166 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + CC_STATUS_INIT; + + return AS2 (btc%L0,%2,%0); +} +} + +static char * +output_167 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + cc_status.flags |= CC_Z_IN_NOT_C; + return AS2 (bt%L0,%1,%0); +} +} + +static char * +output_168 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + unsigned int mask; + + mask = ((1 << INTVAL (operands[1])) - 1) << INTVAL (operands[2]); + operands[1] = GEN_INT (mask); + + if (QI_REG_P (operands[0])) + { + if ((mask & ~0xff) == 0) + { + cc_status.flags |= CC_NOT_NEGATIVE; + return AS2 (test%B0,%1,%b0); + } + + if ((mask & ~0xff00) == 0) + { + cc_status.flags |= CC_NOT_NEGATIVE; + operands[1] = GEN_INT (mask >> 8); + return AS2 (test%B0,%1,%h0); + } + } + + return AS2 (test%L0,%1,%0); +} +} + +static char * +output_169 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + unsigned int mask; + + mask = ((1 << INTVAL (operands[1])) - 1) << INTVAL (operands[2]); + operands[1] = GEN_INT (mask); + + if (! REG_P (operands[0]) || QI_REG_P (operands[0])) + { + if ((mask & ~0xff) == 0) + { + cc_status.flags |= CC_NOT_NEGATIVE; + return AS2 (test%B0,%1,%b0); + } + + if ((mask & ~0xff00) == 0) + { + cc_status.flags |= CC_NOT_NEGATIVE; + operands[1] = GEN_INT (mask >> 8); + + if (QI_REG_P (operands[0])) + return AS2 (test%B0,%1,%h0); + else + { + operands[0] = adj_offsettable_operand (operands[0], 1); + return AS2 (test%B0,%1,%b0); + } + } + + if (GET_CODE (operands[0]) == MEM && (mask & ~0xff0000) == 0) + { + cc_status.flags |= CC_NOT_NEGATIVE; + operands[1] = GEN_INT (mask >> 16); + operands[0] = adj_offsettable_operand (operands[0], 2); + return AS2 (test%B0,%1,%b0); + } + + if (GET_CODE (operands[0]) == MEM && (mask & ~0xff000000) == 0) + { + cc_status.flags |= CC_NOT_NEGATIVE; + operands[1] = GEN_INT (mask >> 24); + operands[0] = adj_offsettable_operand (operands[0], 3); + return AS2 (test%B0,%1,%b0); + } + } + + if (CONSTANT_P (operands[1]) || GET_CODE (operands[0]) == MEM) + return AS2 (test%L0,%1,%0); + + return AS2 (test%L1,%0,%1); +} +} + +static char * +output_171 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (cc_prev_status.flags & CC_Z_IN_NOT_C) + return AS1 (setnb,%0); + else + return AS1 (sete,%0); +} +} + +static char * +output_173 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (cc_prev_status.flags & CC_Z_IN_NOT_C) + return AS1 (setb,%0); + else + return AS1 (setne,%0); +} + +} + +static char * +output_175 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)) + return AS1 (sete,%0); + + OUTPUT_JUMP ("setg %0", "seta %0", NULL_PTR); +} +} + +static char * +output_177 (operands, insn) + rtx *operands; + rtx insn; +{ + return "seta %0"; +} + +static char * +output_179 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)) + return AS1 (sete,%0); + + OUTPUT_JUMP ("setl %0", "setb %0", "sets %0"); +} +} + +static char * +output_181 (operands, insn) + rtx *operands; + rtx insn; +{ + return "setb %0"; +} + +static char * +output_183 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)) + return AS1 (sete,%0); + + OUTPUT_JUMP ("setge %0", "setae %0", "setns %0"); +} +} + +static char * +output_185 (operands, insn) + rtx *operands; + rtx insn; +{ + return "setae %0"; +} + +static char * +output_187 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)) + return AS1 (setb,%0); + + OUTPUT_JUMP ("setle %0", "setbe %0", NULL_PTR); +} +} + +static char * +output_189 (operands, insn) + rtx *operands; + rtx insn; +{ + return "setbe %0"; +} + +static char * +output_191 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (cc_prev_status.flags & CC_Z_IN_NOT_C) + return "jnc %l0"; + else + return "je %l0"; +} +} + +static char * +output_193 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (cc_prev_status.flags & CC_Z_IN_NOT_C) + return "jc %l0"; + else + return "jne %l0"; +} +} + +static char * +output_195 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)) + return AS1 (je,%l0); + + OUTPUT_JUMP ("jg %l0", "ja %l0", NULL_PTR); +} +} + +static char * +output_199 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)) + return AS1 (je,%l0); + + OUTPUT_JUMP ("jl %l0", "jb %l0", "js %l0"); +} +} + +static char * +output_203 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)) + return AS1 (je,%l0); + + OUTPUT_JUMP ("jge %l0", "jae %l0", "jns %l0"); +} +} + +static char * +output_207 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)) + return AS1 (jb,%l0); + + OUTPUT_JUMP ("jle %l0", "jbe %l0", NULL_PTR); +} +} + +static char * +output_210 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (cc_prev_status.flags & CC_Z_IN_NOT_C) + return "jc %l0"; + else + return "jne %l0"; +} +} + +static char * +output_211 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (cc_prev_status.flags & CC_Z_IN_NOT_C) + return "jnc %l0"; + else + return "je %l0"; +} +} + +static char * +output_212 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)) + return AS1 (jne,%l0); + + OUTPUT_JUMP ("jle %l0", "jbe %l0", NULL_PTR); +} +} + +static char * +output_214 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)) + return AS1 (jne,%l0); + + OUTPUT_JUMP ("jge %l0", "jae %l0", "jns %l0"); +} +} + +static char * +output_216 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)) + return AS1 (jne,%l0); + + OUTPUT_JUMP ("jl %l0", "jb %l0", "js %l0"); +} +} + +static char * +output_218 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)) + return AS1 (jae,%l0); + + OUTPUT_JUMP ("jg %l0", "ja %l0", NULL_PTR); +} +} + +static char * +output_221 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + CC_STATUS_INIT; + + return AS1 (jmp,%*%0); +} +} + +static char * +output_223 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + rtx xops[4]; + + xops[0] = operands[0]; + xops[1] = operands[1]; + xops[2] = operands[2]; + xops[3] = pic_offset_table_rtx; + + output_asm_insn (AS2 (mov%L2,%3,%2), xops); + output_asm_insn ("sub%L2 %l1@GOTOFF(%3,%0,4),%2", xops); + output_asm_insn (AS1 (jmp,%*%2), xops); + ASM_OUTPUT_ALIGN_CODE (asm_out_file); + RET; +} +} + +static char * +output_224 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + CC_STATUS_INIT; + + return AS1 (jmp,%*%0); +} +} + +static char * +output_226 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (GET_CODE (operands[0]) == MEM + && ! CONSTANT_ADDRESS_P (XEXP (operands[0], 0))) + { + operands[0] = XEXP (operands[0], 0); + return AS1 (call,%*%0); + } + else + return AS1 (call,%P0); +} +} + +static char * +output_229 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (GET_CODE (operands[0]) == MEM + && ! CONSTANT_ADDRESS_P (XEXP (operands[0], 0))) + { + operands[0] = XEXP (operands[0], 0); + return AS1 (call,%*%0); + } + else + return AS1 (call,%P0); +} +} + +static char * +output_232 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (GET_CODE (operands[1]) == MEM + && ! CONSTANT_ADDRESS_P (XEXP (operands[1], 0))) + { + operands[1] = XEXP (operands[1], 0); + output_asm_insn (AS1 (call,%*%1), operands); + } + else + output_asm_insn (AS1 (call,%P1), operands); + + RET; +} +} + +static char * +output_235 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (GET_CODE (operands[1]) == MEM + && ! CONSTANT_ADDRESS_P (XEXP (operands[1], 0))) + { + operands[1] = XEXP (operands[1], 0); + output_asm_insn (AS1 (call,%*%1), operands); + } + else + output_asm_insn (AS1 (call,%P1), operands); + + RET; +} +} + +static char * +output_238 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + rtx addr = operands[1]; + + if (GET_CODE (operands[0]) == MEM + && ! CONSTANT_ADDRESS_P (XEXP (operands[0], 0))) + { + operands[0] = XEXP (operands[0], 0); + output_asm_insn (AS1 (call,%*%0), operands); + } + else + output_asm_insn (AS1 (call,%P0), operands); + + operands[2] = gen_rtx (REG, SImode, 0); + output_asm_insn (AS2 (mov%L2,%2,%1), operands); + + operands[2] = gen_rtx (REG, SImode, 1); + operands[1] = adj_offsettable_operand (addr, 4); + output_asm_insn (AS2 (mov%L2,%2,%1), operands); + + operands[1] = adj_offsettable_operand (addr, 8); + return AS1 (fnsave,%1); +} +} + +static char * +output_239 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + rtx addr = operands[1]; + + output_asm_insn (AS1 (call,%P0), operands); + + operands[2] = gen_rtx (REG, SImode, 0); + output_asm_insn (AS2 (mov%L2,%2,%1), operands); + + operands[2] = gen_rtx (REG, SImode, 1); + operands[1] = adj_offsettable_operand (addr, 4); + output_asm_insn (AS2 (mov%L2,%2,%1), operands); + + operands[1] = adj_offsettable_operand (addr, 8); + return AS1 (fnsave,%1); +} +} + +static char * +output_242 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + function_epilogue (asm_out_file, get_frame_size ()); + RET; +} +} + +static char * +output_245 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + rtx xops[2]; + + output_asm_insn ("cld", operands); + if (GET_CODE (operands[2]) == CONST_INT) + { + if (INTVAL (operands[2]) & ~0x03) + { + xops[0] = GEN_INT ((INTVAL (operands[2]) >> 2) & 0x3fffffff); + xops[1] = operands[4]; + + output_asm_insn (AS2 (mov%L1,%0,%1), xops); +#ifdef INTEL_SYNTAX + output_asm_insn ("rep movsd", xops); +#else + output_asm_insn ("rep\n\tmovsl", xops); +#endif + } + if (INTVAL (operands[2]) & 0x02) + output_asm_insn ("movsw", operands); + if (INTVAL (operands[2]) & 0x01) + output_asm_insn ("movsb", operands); + } + else + abort (); + RET; +} +} + +static char * +output_247 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + rtx xops[4], label; + + label = gen_label_rtx (); + + output_asm_insn ("cld", operands); + output_asm_insn (AS2 (xor%L0,%0,%0), operands); + output_asm_insn ("repz\n\tcmps%B2", operands); + output_asm_insn ("je %l0", &label); + + xops[0] = operands[0]; + xops[1] = gen_rtx (MEM, QImode, + gen_rtx (PLUS, SImode, operands[1], constm1_rtx)); + xops[2] = gen_rtx (MEM, QImode, + gen_rtx (PLUS, SImode, operands[2], constm1_rtx)); + xops[3] = operands[3]; + + output_asm_insn (AS2 (movz%B1%L0,%1,%0), xops); + output_asm_insn (AS2 (movz%B2%L3,%2,%3), xops); + + output_asm_insn (AS2 (sub%L0,%3,%0), xops); + ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (label)); + RET; +} +} + +static char * +output_248 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + rtx xops[2]; + + cc_status.flags |= CC_NOT_SIGNED; + + xops[0] = gen_rtx (REG, QImode, 0); + xops[1] = CONST0_RTX (QImode); + + output_asm_insn ("cld", operands); + output_asm_insn (AS2 (test%B0,%1,%0), xops); + return "repz\n\tcmps%B2"; +} +} + +static char * +output_250 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + rtx xops[2]; + + xops[0] = const1_rtx; + xops[1] = operands[1]; + output_asm_insn (AS2 (bsf%L1,%1,%0), operands); + output_asm_insn (AS2 (cmp%L1,%0,%1), xops); + output_asm_insn (AS2 (sbb%L0,%2,%2), operands); + output_asm_insn (AS2 (or%L0,%2,%0), operands); + return ""; +} +} + +static char * +output_252 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + rtx xops[2]; + + xops[0] = const1_rtx; + xops[1] = operands[1]; + output_asm_insn (AS2 (bsf%W1,%1,%0), operands); + output_asm_insn (AS2 (cmp%W1,%0,%1), xops); + output_asm_insn (AS2 (sbb%W0,%2,%2), operands); + output_asm_insn (AS2 (or%W0,%2,%0), operands); + return ""; +} +} + +static char * +output_253 (operands, insn) + rtx *operands; + rtx insn; +{ + return (char *) output_387_binary_op (insn, operands); +} + +static char * +output_254 (operands, insn) + rtx *operands; + rtx insn; +{ + return (char *) output_387_binary_op (insn, operands); +} + +static char * +output_255 (operands, insn) + rtx *operands; + rtx insn; +{ + return (char *) output_387_binary_op (insn, operands); +} + +static char * +output_256 (operands, insn) + rtx *operands; + rtx insn; +{ + return (char *) output_387_binary_op (insn, operands); +} + +static char * +output_257 (operands, insn) + rtx *operands; + rtx insn; +{ + return (char *) output_387_binary_op (insn, operands); +} + +static char * +output_258 (operands, insn) + rtx *operands; + rtx insn; +{ + return (char *) output_387_binary_op (insn, operands); +} + +static char * +output_259 (operands, insn) + rtx *operands; + rtx insn; +{ + return (char *) output_387_binary_op (insn, operands); +} + +static char * +output_260 (operands, insn) + rtx *operands; + rtx insn; +{ + return (char *) output_387_binary_op (insn, operands); +} + +static char * +output_262 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + rtx xops[2]; + + xops[0] = operands[0]; + xops[1] = constm1_rtx; + output_asm_insn ("cld", operands); + output_asm_insn (AS2 (mov%L0,%1,%0), xops); + return "repnz\n\tscas%B2"; +} +} + +char * const insn_template[] = + { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + "push%L0 %1", + "push%L0 %1", + 0, + 0, + "push%W0 %1", + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + "mul%B0 %2", + 0, + 0, + "idiv%B0 %2", + "div%B0 %2", + 0, + 0, + 0, + "cwtd\n\tidiv%W0 %2", + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + "neg%L0 %0", + "neg%W0 %0", + "neg%B0 %0", + "fchs", + "fchs", + "fchs", + "fabs", + "fabs", + "fabs", + "fsqrt", + "fsqrt", + "fsqrt", + "fsin", + "fsin", + "fsin", + "fcos", + "fcos", + "fcos", + "not%L0 %0", + "not%W0 %0", + "not%B0 %0", + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + "ja %l0", + 0, + 0, + 0, + "jb %l0", + 0, + 0, + 0, + "jae %l0", + 0, + 0, + 0, + "jbe %l0", + 0, + 0, + 0, + "jbe %l0", + 0, + "jae %l0", + 0, + "jb %l0", + 0, + "ja %l0", + "jmp %l0", + 0, + 0, + 0, + 0, + 0, + 0, + "call %P0", + 0, + 0, + "call %P0", + 0, + 0, + "call %P1", + 0, + 0, + "call %P1", + 0, + 0, + 0, + 0, + "frstor %0", + 0, + "nop", + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + }; + +char *(*const insn_outfun[])() = + { + output_0, + 0, + output_2, + 0, + output_4, + 0, + output_6, + 0, + output_8, + 0, + output_10, + 0, + output_12, + 0, + output_14, + 0, + output_16, + output_17, + output_18, + output_19, + output_20, + output_21, + output_22, + output_23, + output_24, + output_25, + 0, + 0, + 0, + 0, + 0, + 0, + output_32, + output_33, + output_34, + 0, + 0, + 0, + output_38, + 0, + output_40, + output_41, + output_42, + output_43, + output_44, + output_45, + output_46, + output_47, + output_48, + output_49, + output_50, + output_51, + output_52, + output_53, + output_54, + output_55, + output_56, + output_57, + output_58, + output_59, + output_60, + 0, + output_62, + 0, + 0, + 0, + 0, + output_67, + output_68, + 0, + 0, + output_71, + output_72, + 0, + 0, + 0, + 0, + output_77, + output_78, + output_79, + output_80, + output_81, + output_82, + output_83, + output_84, + output_85, + 0, + 0, + output_88, + output_89, + output_90, + output_91, + 0, + 0, + output_94, + output_95, + output_96, + output_97, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + output_105, + 0, + output_107, + output_108, + output_109, + output_110, + output_111, + output_112, + output_113, + output_114, + output_115, + output_116, + output_117, + output_118, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + output_141, + output_142, + output_143, + output_144, + output_145, + 0, + output_147, + output_148, + output_149, + output_150, + output_151, + 0, + output_153, + output_154, + output_155, + output_156, + output_157, + output_158, + output_159, + output_160, + output_161, + output_162, + output_163, + output_164, + output_165, + output_166, + output_167, + output_168, + output_169, + 0, + output_171, + 0, + output_173, + 0, + output_175, + 0, + output_177, + 0, + output_179, + 0, + output_181, + 0, + output_183, + 0, + output_185, + 0, + output_187, + 0, + output_189, + 0, + output_191, + 0, + output_193, + 0, + output_195, + 0, + 0, + 0, + output_199, + 0, + 0, + 0, + output_203, + 0, + 0, + 0, + output_207, + 0, + 0, + output_210, + output_211, + output_212, + 0, + output_214, + 0, + output_216, + 0, + output_218, + 0, + 0, + output_221, + 0, + output_223, + output_224, + 0, + output_226, + 0, + 0, + output_229, + 0, + 0, + output_232, + 0, + 0, + output_235, + 0, + 0, + output_238, + output_239, + 0, + 0, + output_242, + 0, + 0, + output_245, + 0, + output_247, + output_248, + 0, + output_250, + 0, + output_252, + output_253, + output_254, + output_255, + output_256, + output_257, + output_258, + output_259, + output_260, + 0, + output_262, + }; + +rtx (*const insn_gen_function[]) () = + { + gen_tstsi_1, + gen_tstsi, + gen_tsthi_1, + gen_tsthi, + gen_tstqi_1, + gen_tstqi, + gen_tstsf_cc, + gen_tstsf, + gen_tstdf_cc, + gen_tstdf, + gen_cmpsi_1, + gen_cmpsi, + gen_cmphi_1, + gen_cmphi, + gen_cmpqi_1, + gen_cmpqi, + 0, + 0, + 0, + 0, + 0, + 0, + gen_cmpsf_cc_1, + 0, + 0, + 0, + gen_cmpdf, + gen_cmpsf, + gen_cmpdf_cc, + gen_cmpdf_ccfpeq, + gen_cmpsf_cc, + gen_cmpsf_ccfpeq, + 0, + 0, + 0, + 0, + 0, + gen_movsi, + 0, + 0, + gen_movhi, + gen_movstricthi, + 0, + gen_movqi, + gen_movstrictqi, + 0, + gen_movsf, + 0, + gen_swapdf, + gen_movdf, + 0, + gen_movdi, + gen_zero_extendhisi2, + gen_zero_extendqihi2, + gen_zero_extendqisi2, + gen_zero_extendsidi2, + gen_extendsidi2, + gen_extendhisi2, + gen_extendqihi2, + gen_extendqisi2, + gen_extendsfdf2, + gen_truncdfsf2, + 0, + gen_fixuns_truncdfsi2, + gen_fixuns_truncsfsi2, + gen_fix_truncdfdi2, + gen_fix_truncsfdi2, + 0, + 0, + gen_fix_truncdfsi2, + gen_fix_truncsfsi2, + 0, + 0, + gen_floatsisf2, + gen_floatdisf2, + gen_floatsidf2, + gen_floatdidf2, + 0, + 0, + 0, + 0, + gen_adddi3, + gen_addsi3, + gen_addhi3, + gen_addqi3, + 0, + gen_adddf3, + gen_addsf3, + gen_subdi3, + gen_subsi3, + gen_subhi3, + gen_subqi3, + gen_subdf3, + gen_subsf3, + 0, + gen_mulhi3, + 0, + gen_mulsi3, + 0, + gen_muldf3, + gen_mulsf3, + gen_divqi3, + gen_udivqi3, + gen_divdf3, + gen_divsf3, + gen_divmodsi4, + gen_divmodhi4, + gen_udivmodsi4, + gen_udivmodhi4, + gen_andsi3, + gen_andhi3, + gen_andqi3, + gen_iorsi3, + gen_iorhi3, + gen_iorqi3, + gen_xorsi3, + gen_xorhi3, + gen_xorqi3, + gen_negdi2, + gen_negsi2, + gen_neghi2, + gen_negqi2, + gen_negsf2, + gen_negdf2, + 0, + gen_abssf2, + gen_absdf2, + 0, + gen_sqrtsf2, + gen_sqrtdf2, + 0, + gen_sindf2, + gen_sinsf2, + 0, + gen_cosdf2, + gen_cossf2, + 0, + gen_one_cmplsi2, + gen_one_cmplhi2, + gen_one_cmplqi2, + gen_ashldi3, + gen_ashldi3_const_int, + gen_ashldi3_non_const_int, + gen_ashlsi3, + gen_ashlhi3, + gen_ashlqi3, + gen_ashrdi3, + gen_ashrdi3_const_int, + gen_ashrdi3_non_const_int, + gen_ashrsi3, + gen_ashrhi3, + gen_ashrqi3, + gen_lshrdi3, + gen_lshrdi3_const_int, + gen_lshrdi3_non_const_int, + gen_lshrsi3, + gen_lshrhi3, + gen_lshrqi3, + gen_rotlsi3, + gen_rotlhi3, + gen_rotlqi3, + gen_rotrsi3, + gen_rotrhi3, + gen_rotrqi3, + 0, + 0, + 0, + 0, + 0, + 0, + gen_seq, + 0, + gen_sne, + 0, + gen_sgt, + 0, + gen_sgtu, + 0, + gen_slt, + 0, + gen_sltu, + 0, + gen_sge, + 0, + gen_sgeu, + 0, + gen_sle, + 0, + gen_sleu, + 0, + gen_beq, + 0, + gen_bne, + 0, + gen_bgt, + 0, + gen_bgtu, + 0, + gen_blt, + 0, + gen_bltu, + 0, + gen_bge, + 0, + gen_bgeu, + 0, + gen_ble, + 0, + gen_bleu, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + gen_jump, + gen_indirect_jump, + gen_casesi, + 0, + gen_tablejump, + gen_call_pop, + 0, + 0, + gen_call, + 0, + 0, + gen_call_value_pop, + 0, + 0, + gen_call_value, + 0, + 0, + gen_untyped_call, + 0, + 0, + gen_untyped_return, + gen_update_return, + gen_return, + gen_nop, + gen_movstrsi, + 0, + gen_cmpstrsi, + 0, + 0, + gen_ffssi2, + 0, + gen_ffshi2, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + gen_strlensi, + 0, + }; + +char *insn_name[] = + { + "tstsi_1", + "tstsi", + "tsthi_1", + "tsthi", + "tstqi_1", + "tstqi", + "tstsf_cc", + "tstsf", + "tstdf_cc", + "tstdf", + "cmpsi_1", + "cmpsi", + "cmphi_1", + "cmphi", + "cmpqi_1", + "cmpqi", + "cmpqi+1", + "cmpqi+2", + "cmpqi+3", + "cmpsf_cc_1-3", + "cmpsf_cc_1-2", + "cmpsf_cc_1-1", + "cmpsf_cc_1", + "cmpsf_cc_1+1", + "cmpsf_cc_1+2", + "cmpdf-1", + "cmpdf", + "cmpsf", + "cmpdf_cc", + "cmpdf_ccfpeq", + "cmpsf_cc", + "cmpsf_ccfpeq", + "cmpsf_ccfpeq+1", + "cmpsf_ccfpeq+2", + "cmpsf_ccfpeq+3", + "movsi-2", + "movsi-1", + "movsi", + "movsi+1", + "movhi-1", + "movhi", + "movstricthi", + "movstricthi+1", + "movqi", + "movstrictqi", + "movstrictqi+1", + "movsf", + "movsf+1", + "swapdf", + "movdf", + "movdf+1", + "movdi", + "zero_extendhisi2", + "zero_extendqihi2", + "zero_extendqisi2", + "zero_extendsidi2", + "extendsidi2", + "extendhisi2", + "extendqihi2", + "extendqisi2", + "extendsfdf2", + "truncdfsf2", + "truncdfsf2+1", + "fixuns_truncdfsi2", + "fixuns_truncsfsi2", + "fix_truncdfdi2", + "fix_truncsfdi2", + "fix_truncsfdi2+1", + "fix_truncdfsi2-1", + "fix_truncdfsi2", + "fix_truncsfsi2", + "fix_truncsfsi2+1", + "floatsisf2-1", + "floatsisf2", + "floatdisf2", + "floatsidf2", + "floatdidf2", + "floatdidf2+1", + "floatdidf2+2", + "adddi3-2", + "adddi3-1", + "adddi3", + "addsi3", + "addhi3", + "addqi3", + "addqi3+1", + "adddf3", + "addsf3", + "subdi3", + "subsi3", + "subhi3", + "subqi3", + "subdf3", + "subsf3", + "subsf3+1", + "mulhi3", + "mulhi3+1", + "mulsi3", + "mulsi3+1", + "muldf3", + "mulsf3", + "divqi3", + "udivqi3", + "divdf3", + "divsf3", + "divmodsi4", + "divmodhi4", + "udivmodsi4", + "udivmodhi4", + "andsi3", + "andhi3", + "andqi3", + "iorsi3", + "iorhi3", + "iorqi3", + "xorsi3", + "xorhi3", + "xorqi3", + "negdi2", + "negsi2", + "neghi2", + "negqi2", + "negsf2", + "negdf2", + "negdf2+1", + "abssf2", + "absdf2", + "absdf2+1", + "sqrtsf2", + "sqrtdf2", + "sqrtdf2+1", + "sindf2", + "sinsf2", + "sinsf2+1", + "cosdf2", + "cossf2", + "cossf2+1", + "one_cmplsi2", + "one_cmplhi2", + "one_cmplqi2", + "ashldi3", + "ashldi3_const_int", + "ashldi3_non_const_int", + "ashlsi3", + "ashlhi3", + "ashlqi3", + "ashrdi3", + "ashrdi3_const_int", + "ashrdi3_non_const_int", + "ashrsi3", + "ashrhi3", + "ashrqi3", + "lshrdi3", + "lshrdi3_const_int", + "lshrdi3_non_const_int", + "lshrsi3", + "lshrhi3", + "lshrqi3", + "rotlsi3", + "rotlhi3", + "rotlqi3", + "rotrsi3", + "rotrhi3", + "rotrqi3", + "rotrqi3+1", + "rotrqi3+2", + "rotrqi3+3", + "seq-3", + "seq-2", + "seq-1", + "seq", + "seq+1", + "sne", + "sne+1", + "sgt", + "sgt+1", + "sgtu", + "sgtu+1", + "slt", + "slt+1", + "sltu", + "sltu+1", + "sge", + "sge+1", + "sgeu", + "sgeu+1", + "sle", + "sle+1", + "sleu", + "sleu+1", + "beq", + "beq+1", + "bne", + "bne+1", + "bgt", + "bgt+1", + "bgtu", + "bgtu+1", + "blt", + "blt+1", + "bltu", + "bltu+1", + "bge", + "bge+1", + "bgeu", + "bgeu+1", + "ble", + "ble+1", + "bleu", + "bleu+1", + "bleu+2", + "bleu+3", + "bleu+4", + "bleu+5", + "bleu+6", + "jump-5", + "jump-4", + "jump-3", + "jump-2", + "jump-1", + "jump", + "indirect_jump", + "casesi", + "casesi+1", + "tablejump", + "call_pop", + "call_pop+1", + "call-1", + "call", + "call+1", + "call_value_pop-1", + "call_value_pop", + "call_value_pop+1", + "call_value-1", + "call_value", + "call_value+1", + "untyped_call-1", + "untyped_call", + "untyped_call+1", + "untyped_return-1", + "untyped_return", + "update_return", + "return", + "nop", + "movstrsi", + "movstrsi+1", + "cmpstrsi", + "cmpstrsi+1", + "ffssi2-1", + "ffssi2", + "ffssi2+1", + "ffshi2", + "ffshi2+1", + "ffshi2+2", + "ffshi2+3", + "ffshi2+4", + "ffshi2+5", + "strlensi-4", + "strlensi-3", + "strlensi-2", + "strlensi-1", + "strlensi", + "strlensi+1", + }; +char **insn_name_ptr = insn_name; + +const int insn_n_operands[] = + { + 1, + 1, + 1, + 1, + 1, + 1, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 4, + 4, + 4, + 4, + 4, + 3, + 4, + 4, + 4, + 3, + 2, + 2, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 3, + 8, + 8, + 6, + 6, + 5, + 5, + 5, + 5, + 5, + 5, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 3, + 3, + 3, + 3, + 2, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 4, + 4, + 4, + 4, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 4, + 3, + 3, + 2, + 3, + 3, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 7, + 3, + 1, + 4, + 4, + 4, + 2, + 2, + 2, + 5, + 5, + 5, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 1, + 0, + 0, + 5, + 5, + 5, + 5, + 4, + 3, + 3, + 3, + 3, + 4, + 4, + 4, + 4, + 4, + 4, + 4, + 4, + 4, + 4, + }; + +const int insn_n_dups[] = + { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 2, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 7, + 7, + 5, + 5, + 1, + 1, + 2, + 2, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 2, + 2, + 2, + 2, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 3, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 2, + 2, + 3, + 3, + 3, + 2, + 0, + 2, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 5, + 1, + }; + +char *const insn_operand_constraint[][MAX_RECOG_OPERANDS] = + { + { "rm", }, + { "", }, + { "rm", }, + { "", }, + { "qm", }, + { "", }, + { "f", "=a", }, + { "", "", }, + { "f", "=a", }, + { "", "", }, + { "mr,r", "ri,mr", }, + { "", "", }, + { "mr,r", "ri,mr", }, + { "", "", }, + { "q,mq", "qm,nq", }, + { "", "", }, + { "f,fm", "fm,f", "", "=a,a", }, + { "f", "rm", "", "=a", }, + { "rm", "f", "", "=a", }, + { "f", "fm", "", "=a", }, + { "fm", "f", "", "=a", }, + { "f", "f", "=a", }, + { "f,fm", "fm,f", "", "=a,a", }, + { "f", "rm", "", "=a", }, + { "rm", "f", "", "=a", }, + { "f", "f", "=a", }, + { "", "", }, + { "", "", }, + { "", "", "", }, + { "", "", "", }, + { "", "", "", }, + { "", "", "", }, + { "%ro", "ri", }, + { "%ro", "ri", }, + { "%qm", "qi", }, + { "=<", "g", }, + { "=<", "ri", }, + { "", "", }, + { "=g,r", "ri,m", }, + { "=<", "g", }, + { "=g,r", "ri,m", }, + { "+g,r", "ri,m", }, + { "=<", "q", }, + { "=q,*r,qm", "*g,q,qn", }, + { "+q,qm", "*g,qn", }, + { "=<,<", "gF,f", }, + { "=*rfm,*rf,f,!*rm", "*rf,*rfm,fG,fF", }, + { "=<,<", "gF,f", }, + { "f", "f", }, + { "=*rfm,*rf,f,!*rm", "*rf,*rfm,fG,fF", }, + { "=<", "roiF", }, + { "=r,rm", "m,riF", }, + { "=r", "rm", }, + { "=r", "qm", }, + { "=r", "qm", }, + { "=r", "0", }, + { "=r", "0", }, + { "=r", "rm", }, + { "=r", "qm", }, + { "=r", "qm", }, + { "=fm,f", "f,fm", }, + { "", "", }, + { "=f,m", "0,f", "m,m", }, + { "", "", "", "", "", "", "", "", }, + { "", "", "", "", "", "", "", "", }, + { "", "", "", "", "", "", }, + { "", "", "", "", "", "", }, + { "=rm", "f", "m", "m", "=&q", }, + { "=rm", "f", "m", "m", "=&q", }, + { "", "", "", "", "", }, + { "", "", "", "", "", }, + { "=rm", "f", "m", "m", "=&q", }, + { "=rm", "f", "m", "m", "=&q", }, + { "", "", }, + { "", "", }, + { "", "", }, + { "", "", }, + { "=f", "rm", }, + { "=f", "rm", }, + { "=f", "rm", }, + { "=f", "rm", }, + { "=&r,ro", "%0,0", "o,riF", }, + { "=?r,rm,r", "%r,0,0", "ri,ri,rm", }, + { "=rm,r", "%0,0", "ri,rm", }, + { "=qm,q", "%0,0", "qn,qmn", }, + { "=r", "p", }, + { "", "", "", }, + { "", "", "", }, + { "=&r,ro", "0,0", "o,riF", }, + { "=rm,r", "0,0", "ri,rm", }, + { "=rm,r", "0,0", "ri,rm", }, + { "=qm,q", "0,0", "qn,qmn", }, + { "", "", "", }, + { "", "", "", }, + { "=r", "%0", "r", }, + { "=r,r", "%0,rm", "g,i", }, + { "=r", "%0", "r", }, + { "=r,r", "%0,rm", "g,i", }, + { "=a", "%0", "qm", }, + { "", "", "", }, + { "", "", "", }, + { "=a", "0", "qm", }, + { "=a", "0", "qm", }, + { "", "", "", }, + { "", "", "", }, + { "=a", "0", "rm", "=&d", }, + { "=a", "0", "rm", "=&d", }, + { "=a", "0", "rm", "=&d", }, + { "=a", "0", "rm", "=&d", }, + { "=r,r,rm,r", "%rm,qm,0,0", "L,K,ri,rm", }, + { "=rm,r", "%0,0", "ri,rm", }, + { "=qm,q", "%0,0", "qn,qmn", }, + { "=rm,r", "%0,0", "ri,rm", }, + { "=rm,r", "%0,0", "ri,rm", }, + { "=qm,q", "%0,0", "qn,qmn", }, + { "=rm,r", "%0,0", "ri,rm", }, + { "=rm,r", "%0,0", "ri,rm", }, + { "=qm,q", "%0,0", "qn,qm", }, + { "=&ro", "0", }, + { "=rm", "0", }, + { "=rm", "0", }, + { "=qm", "0", }, + { "=f", "0", }, + { "=f", "0", }, + { "=f", "0", }, + { "=f", "0", }, + { "=f", "0", }, + { "=f", "0", }, + { "=f", "0", }, + { "=f", "0", }, + { "=f", "0", }, + { "=f", "0", }, + { "=f", "0", }, + { "=f", "0", }, + { "=f", "0", }, + { "=f", "0", }, + { "=f", "0", }, + { "=rm", "0", }, + { "=rm", "0", }, + { "=qm", "0", }, + { "", "", "", }, + { "=&r", "0", "J", }, + { "=&r", "0", "c", }, + { "=r,rm", "r,0", "M,cI", }, + { "=rm", "0", "cI", }, + { "=qm", "0", "cI", }, + { "", "", "", }, + { "=&r", "0", "J", }, + { "=&r", "0", "c", }, + { "=rm", "0", "cI", }, + { "=rm", "0", "cI", }, + { "=qm", "0", "cI", }, + { "", "", "", }, + { "=&r", "0", "J", }, + { "=&r", "0", "c", }, + { "=rm", "0", "cI", }, + { "=rm", "0", "cI", }, + { "=qm", "0", "cI", }, + { "=rm", "0", "cI", }, + { "=rm", "0", "cI", }, + { "=qm", "0", "cI", }, + { "=rm", "0", "cI", }, + { "=rm", "0", "cI", }, + { "=qm", "0", "cI", }, + { "+rm", "", "r", "n", }, + { "=rm", "r", "0", }, + { "=rm", "0", "r", }, + { "r", "r", }, + { "r", "n", "n", }, + { "rm", "n", "n", }, + { "", }, + { "=q", }, + { "", }, + { "=q", }, + { "", }, + { "=q", }, + { "", }, + { "=q", }, + { "", }, + { "=q", }, + { "", }, + { "=q", }, + { "", }, + { "=q", }, + { "", }, + { "=q", }, + { "", }, + { "=q", }, + { "", }, + { "=q", }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { "rm", }, + { "", "", "", "", "", "", "", }, + { "r", "", "=&r", }, + { "rm", }, + { "", "", "", "", }, + { "m", "g", "", "i", }, + { "", "g", "", "i", }, + { "", "", }, + { "m", "g", }, + { "", "g", }, + { "", "", "", "", "", }, + { "=rf", "m", "g", "", "i", }, + { "=rf", "", "g", "", "i", }, + { "", "", "", }, + { "=rf", "m", "g", }, + { "=rf", "", "g", }, + { "", "", "", }, + { "m", "o", "", }, + { "", "o", "", }, + { "", "", }, + { "m", }, + { 0 }, + { 0 }, + { "", "", "", "", "", }, + { "D", "S", "n", "i", "=&c", }, + { "", "", "", "", "", }, + { "=&r", "S", "D", "c", "i", }, + { "S", "D", "c", "i", }, + { "", "", "", }, + { "=&r", "rm", "=r", }, + { "", "", "", }, + { "=&r", "rm", "=r", }, + { "=f,f", "0,fm", "fm,0", "", }, + { "=f", "rm", "0", "", }, + { "=f,f", "fm,0", "0,f", "", }, + { "=f", "0", "rm", "", }, + { "=f,f", "0,f", "fm,0", "", }, + { "=f,f", "0,fm", "fm,0", "", }, + { "=f", "rm", "0", "", }, + { "=f", "0", "rm", "", }, + { "", "", "", "", }, + { "=&c", "D", "a", "i", }, + }; + +const enum machine_mode insn_operand_mode[][MAX_RECOG_OPERANDS] = + { + { SImode, }, + { SImode, }, + { HImode, }, + { HImode, }, + { QImode, }, + { QImode, }, + { SFmode, HImode, }, + { SFmode, HImode, }, + { DFmode, HImode, }, + { DFmode, HImode, }, + { SImode, SImode, }, + { SImode, SImode, }, + { HImode, HImode, }, + { HImode, HImode, }, + { QImode, QImode, }, + { QImode, QImode, }, + { DFmode, DFmode, VOIDmode, HImode, }, + { DFmode, SImode, VOIDmode, HImode, }, + { SImode, DFmode, VOIDmode, HImode, }, + { DFmode, SFmode, VOIDmode, HImode, }, + { SFmode, DFmode, VOIDmode, HImode, }, + { DFmode, DFmode, HImode, }, + { SFmode, SFmode, VOIDmode, HImode, }, + { SFmode, SImode, VOIDmode, HImode, }, + { SImode, SFmode, VOIDmode, HImode, }, + { SFmode, SFmode, HImode, }, + { DFmode, DFmode, }, + { SFmode, SFmode, }, + { DFmode, DFmode, HImode, }, + { DFmode, DFmode, HImode, }, + { SFmode, SFmode, HImode, }, + { SFmode, SFmode, HImode, }, + { SImode, SImode, }, + { HImode, HImode, }, + { QImode, QImode, }, + { SImode, SImode, }, + { SImode, SImode, }, + { SImode, SImode, }, + { SImode, SImode, }, + { HImode, HImode, }, + { HImode, HImode, }, + { HImode, HImode, }, + { QImode, QImode, }, + { QImode, QImode, }, + { QImode, QImode, }, + { SFmode, SFmode, }, + { SFmode, SFmode, }, + { DFmode, DFmode, }, + { DFmode, DFmode, }, + { DFmode, DFmode, }, + { DImode, DImode, }, + { DImode, DImode, }, + { SImode, HImode, }, + { HImode, QImode, }, + { SImode, QImode, }, + { DImode, SImode, }, + { DImode, SImode, }, + { SImode, HImode, }, + { HImode, QImode, }, + { SImode, QImode, }, + { DFmode, SFmode, }, + { SFmode, DFmode, }, + { SFmode, DFmode, SFmode, }, + { SImode, DFmode, VOIDmode, VOIDmode, VOIDmode, VOIDmode, VOIDmode, SImode, }, + { SImode, SFmode, VOIDmode, VOIDmode, VOIDmode, VOIDmode, VOIDmode, SImode, }, + { DImode, DFmode, VOIDmode, VOIDmode, VOIDmode, SImode, }, + { DImode, SFmode, VOIDmode, VOIDmode, VOIDmode, SImode, }, + { DImode, DFmode, SImode, SImode, SImode, }, + { DImode, SFmode, SImode, SImode, SImode, }, + { SImode, DFmode, VOIDmode, VOIDmode, SImode, }, + { SImode, SFmode, VOIDmode, VOIDmode, SImode, }, + { SImode, DFmode, SImode, SImode, SImode, }, + { SImode, SFmode, SImode, SImode, SImode, }, + { SFmode, SImode, }, + { SFmode, DImode, }, + { DFmode, SImode, }, + { DFmode, DImode, }, + { DFmode, DImode, }, + { SFmode, DImode, }, + { DFmode, SImode, }, + { SFmode, SImode, }, + { DImode, DImode, DImode, }, + { SImode, SImode, SImode, }, + { HImode, HImode, HImode, }, + { QImode, QImode, QImode, }, + { SImode, QImode, }, + { DFmode, DFmode, DFmode, }, + { SFmode, SFmode, SFmode, }, + { DImode, DImode, DImode, }, + { SImode, SImode, SImode, }, + { HImode, HImode, HImode, }, + { QImode, QImode, QImode, }, + { DFmode, DFmode, DFmode, }, + { SFmode, SFmode, SFmode, }, + { HImode, HImode, HImode, }, + { HImode, HImode, HImode, }, + { SImode, SImode, SImode, }, + { SImode, SImode, SImode, }, + { HImode, QImode, QImode, }, + { DFmode, DFmode, DFmode, }, + { SFmode, SFmode, SFmode, }, + { QImode, HImode, QImode, }, + { QImode, HImode, QImode, }, + { DFmode, DFmode, DFmode, }, + { SFmode, SFmode, SFmode, }, + { SImode, SImode, SImode, SImode, }, + { HImode, HImode, HImode, HImode, }, + { SImode, SImode, SImode, SImode, }, + { HImode, HImode, HImode, HImode, }, + { SImode, SImode, SImode, }, + { HImode, HImode, HImode, }, + { QImode, QImode, QImode, }, + { SImode, SImode, SImode, }, + { HImode, HImode, HImode, }, + { QImode, QImode, QImode, }, + { SImode, SImode, SImode, }, + { HImode, HImode, HImode, }, + { QImode, QImode, QImode, }, + { DImode, DImode, }, + { SImode, SImode, }, + { HImode, HImode, }, + { QImode, QImode, }, + { SFmode, SFmode, }, + { DFmode, DFmode, }, + { DFmode, SFmode, }, + { SFmode, SFmode, }, + { DFmode, DFmode, }, + { DFmode, SFmode, }, + { SFmode, SFmode, }, + { DFmode, DFmode, }, + { DFmode, SFmode, }, + { DFmode, DFmode, }, + { SFmode, SFmode, }, + { DFmode, SFmode, }, + { DFmode, DFmode, }, + { SFmode, SFmode, }, + { DFmode, SFmode, }, + { SImode, SImode, }, + { HImode, HImode, }, + { QImode, QImode, }, + { DImode, DImode, QImode, }, + { DImode, DImode, QImode, }, + { DImode, DImode, QImode, }, + { SImode, SImode, SImode, }, + { HImode, HImode, HImode, }, + { QImode, QImode, QImode, }, + { DImode, DImode, QImode, }, + { DImode, DImode, QImode, }, + { DImode, DImode, QImode, }, + { SImode, SImode, SImode, }, + { HImode, HImode, HImode, }, + { QImode, QImode, QImode, }, + { DImode, DImode, QImode, }, + { DImode, DImode, QImode, }, + { DImode, DImode, QImode, }, + { SImode, SImode, SImode, }, + { HImode, HImode, HImode, }, + { QImode, QImode, QImode, }, + { SImode, SImode, SImode, }, + { HImode, HImode, HImode, }, + { QImode, QImode, QImode, }, + { SImode, SImode, SImode, }, + { HImode, HImode, HImode, }, + { QImode, QImode, QImode, }, + { SImode, VOIDmode, SImode, SImode, }, + { SImode, SImode, SImode, }, + { SImode, SImode, SImode, }, + { SImode, SImode, }, + { SImode, SImode, SImode, }, + { QImode, SImode, SImode, }, + { QImode, }, + { QImode, }, + { QImode, }, + { QImode, }, + { QImode, }, + { QImode, }, + { QImode, }, + { QImode, }, + { QImode, }, + { QImode, }, + { QImode, }, + { QImode, }, + { QImode, }, + { QImode, }, + { QImode, }, + { QImode, }, + { QImode, }, + { QImode, }, + { QImode, }, + { QImode, }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { SImode, }, + { SImode, SImode, SImode, VOIDmode, VOIDmode, VOIDmode, SImode, }, + { SImode, VOIDmode, SImode, }, + { SImode, }, + { QImode, SImode, VOIDmode, SImode, }, + { QImode, SImode, VOIDmode, SImode, }, + { SImode, SImode, VOIDmode, SImode, }, + { QImode, SImode, }, + { QImode, SImode, }, + { SImode, SImode, }, + { VOIDmode, QImode, SImode, VOIDmode, SImode, }, + { VOIDmode, QImode, SImode, VOIDmode, SImode, }, + { VOIDmode, SImode, SImode, VOIDmode, SImode, }, + { VOIDmode, QImode, SImode, }, + { VOIDmode, QImode, SImode, }, + { VOIDmode, SImode, SImode, }, + { QImode, BLKmode, VOIDmode, }, + { QImode, DImode, VOIDmode, }, + { SImode, DImode, VOIDmode, }, + { BLKmode, VOIDmode, }, + { SImode, }, + { VOIDmode }, + { VOIDmode }, + { BLKmode, BLKmode, SImode, SImode, SImode, }, + { SImode, SImode, SImode, SImode, SImode, }, + { SImode, BLKmode, BLKmode, SImode, SImode, }, + { SImode, SImode, SImode, SImode, SImode, }, + { SImode, SImode, SImode, SImode, }, + { SImode, SImode, SImode, }, + { SImode, SImode, SImode, }, + { HImode, HImode, HImode, }, + { HImode, HImode, HImode, }, + { DFmode, DFmode, DFmode, DFmode, }, + { DFmode, SImode, DFmode, DFmode, }, + { DFmode, SFmode, DFmode, DFmode, }, + { DFmode, DFmode, SImode, DFmode, }, + { DFmode, DFmode, SFmode, DFmode, }, + { SFmode, SFmode, SFmode, SFmode, }, + { SFmode, SImode, SFmode, SFmode, }, + { SFmode, SFmode, SImode, SFmode, }, + { SImode, BLKmode, QImode, SImode, }, + { SImode, SImode, QImode, SImode, }, + }; + +const char insn_operand_strict_low[][MAX_RECOG_OPERANDS] = + { + { 0, }, + { 0, }, + { 0, }, + { 0, }, + { 0, }, + { 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 1, 0, }, + { 0, 0, }, + { 0, 0, }, + { 1, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, 0, 0, 0, 0, 0, }, + { 0, 0, 0, 0, 0, 0, 0, 0, }, + { 0, 0, 0, 0, 0, 0, }, + { 0, 0, 0, 0, 0, 0, }, + { 0, 0, 0, 0, 0, }, + { 0, 0, 0, 0, 0, }, + { 0, 0, 0, 0, 0, }, + { 0, 0, 0, 0, 0, }, + { 0, 0, 0, 0, 0, }, + { 0, 0, 0, 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, }, + { 0, }, + { 0, }, + { 0, }, + { 0, }, + { 0, }, + { 0, }, + { 0, }, + { 0, }, + { 0, }, + { 0, }, + { 0, }, + { 0, }, + { 0, }, + { 0, }, + { 0, }, + { 0, }, + { 0, }, + { 0, }, + { 0, }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0, }, + { 0, 0, 0, 0, 0, 0, 0, }, + { 0, 0, 0, }, + { 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, 0, 0, 0, }, + { 0, 0, 0, 0, 0, }, + { 0, 0, 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, }, + { 0, }, + { 0 }, + { 0 }, + { 0, 0, 0, 0, 0, }, + { 0, 0, 0, 0, 0, }, + { 0, 0, 0, 0, 0, }, + { 0, 0, 0, 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, 0, }, + }; + +extern int nonimmediate_operand (); +extern int register_operand (); +extern int scratch_operand (); +extern int general_operand (); +extern int VOIDmode_compare_op (); +extern int push_operand (); +extern int memory_operand (); +extern int address_operand (); +extern int nonmemory_operand (); +extern int const_int_operand (); +extern int indirect_operand (); +extern int immediate_operand (); +extern int call_insn_operand (); +extern int symbolic_operand (); +extern int binary_387_op (); + +int (*const insn_operand_predicate[][MAX_RECOG_OPERANDS])() = + { + { nonimmediate_operand, }, + { nonimmediate_operand, }, + { nonimmediate_operand, }, + { nonimmediate_operand, }, + { nonimmediate_operand, }, + { nonimmediate_operand, }, + { register_operand, scratch_operand, }, + { register_operand, scratch_operand, }, + { register_operand, scratch_operand, }, + { register_operand, scratch_operand, }, + { nonimmediate_operand, general_operand, }, + { nonimmediate_operand, general_operand, }, + { nonimmediate_operand, general_operand, }, + { nonimmediate_operand, general_operand, }, + { nonimmediate_operand, general_operand, }, + { nonimmediate_operand, general_operand, }, + { nonimmediate_operand, nonimmediate_operand, VOIDmode_compare_op, scratch_operand, }, + { register_operand, nonimmediate_operand, VOIDmode_compare_op, scratch_operand, }, + { nonimmediate_operand, register_operand, VOIDmode_compare_op, scratch_operand, }, + { register_operand, nonimmediate_operand, VOIDmode_compare_op, scratch_operand, }, + { nonimmediate_operand, register_operand, VOIDmode_compare_op, scratch_operand, }, + { register_operand, register_operand, scratch_operand, }, + { nonimmediate_operand, nonimmediate_operand, VOIDmode_compare_op, scratch_operand, }, + { register_operand, nonimmediate_operand, VOIDmode_compare_op, scratch_operand, }, + { nonimmediate_operand, register_operand, VOIDmode_compare_op, scratch_operand, }, + { register_operand, register_operand, scratch_operand, }, + { register_operand, nonimmediate_operand, }, + { register_operand, nonimmediate_operand, }, + { register_operand, register_operand, scratch_operand, }, + { register_operand, register_operand, scratch_operand, }, + { register_operand, register_operand, scratch_operand, }, + { register_operand, register_operand, scratch_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { push_operand, general_operand, }, + { push_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { push_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { push_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { push_operand, general_operand, }, + { general_operand, general_operand, }, + { push_operand, general_operand, }, + { register_operand, register_operand, }, + { general_operand, general_operand, }, + { push_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, nonimmediate_operand, }, + { general_operand, nonimmediate_operand, }, + { general_operand, nonimmediate_operand, }, + { register_operand, register_operand, }, + { register_operand, register_operand, }, + { general_operand, nonimmediate_operand, }, + { general_operand, nonimmediate_operand, }, + { general_operand, nonimmediate_operand, }, + { general_operand, general_operand, }, + { nonimmediate_operand, register_operand, }, + { nonimmediate_operand, register_operand, memory_operand, }, + { general_operand, register_operand, 0, 0, 0, 0, 0, scratch_operand, }, + { general_operand, register_operand, 0, 0, 0, 0, 0, scratch_operand, }, + { general_operand, register_operand, 0, 0, 0, scratch_operand, }, + { general_operand, register_operand, 0, 0, 0, scratch_operand, }, + { general_operand, register_operand, memory_operand, memory_operand, scratch_operand, }, + { general_operand, register_operand, memory_operand, memory_operand, scratch_operand, }, + { general_operand, register_operand, 0, 0, scratch_operand, }, + { general_operand, register_operand, 0, 0, scratch_operand, }, + { general_operand, register_operand, memory_operand, memory_operand, scratch_operand, }, + { general_operand, register_operand, memory_operand, memory_operand, scratch_operand, }, + { register_operand, nonimmediate_operand, }, + { register_operand, nonimmediate_operand, }, + { register_operand, nonimmediate_operand, }, + { register_operand, nonimmediate_operand, }, + { register_operand, nonimmediate_operand, }, + { register_operand, nonimmediate_operand, }, + { register_operand, nonimmediate_operand, }, + { register_operand, nonimmediate_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { register_operand, address_operand, }, + { register_operand, nonimmediate_operand, nonimmediate_operand, }, + { register_operand, nonimmediate_operand, nonimmediate_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { register_operand, nonimmediate_operand, nonimmediate_operand, }, + { register_operand, nonimmediate_operand, nonimmediate_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, nonimmediate_operand, nonimmediate_operand, }, + { register_operand, nonimmediate_operand, nonimmediate_operand, }, + { register_operand, nonimmediate_operand, nonimmediate_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { register_operand, nonimmediate_operand, nonimmediate_operand, }, + { register_operand, nonimmediate_operand, nonimmediate_operand, }, + { register_operand, register_operand, general_operand, register_operand, }, + { register_operand, register_operand, general_operand, register_operand, }, + { register_operand, register_operand, general_operand, register_operand, }, + { register_operand, register_operand, general_operand, register_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { register_operand, general_operand, }, + { register_operand, general_operand, }, + { register_operand, general_operand, }, + { register_operand, general_operand, }, + { register_operand, general_operand, }, + { register_operand, general_operand, }, + { register_operand, general_operand, }, + { register_operand, general_operand, }, + { register_operand, general_operand, }, + { register_operand, register_operand, }, + { register_operand, register_operand, }, + { register_operand, register_operand, }, + { register_operand, register_operand, }, + { register_operand, register_operand, }, + { register_operand, register_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { register_operand, register_operand, nonmemory_operand, }, + { register_operand, register_operand, const_int_operand, }, + { register_operand, register_operand, register_operand, }, + { general_operand, general_operand, nonmemory_operand, }, + { general_operand, general_operand, nonmemory_operand, }, + { general_operand, general_operand, nonmemory_operand, }, + { register_operand, register_operand, nonmemory_operand, }, + { register_operand, register_operand, const_int_operand, }, + { register_operand, register_operand, register_operand, }, + { general_operand, general_operand, nonmemory_operand, }, + { general_operand, general_operand, nonmemory_operand, }, + { general_operand, general_operand, nonmemory_operand, }, + { register_operand, register_operand, nonmemory_operand, }, + { register_operand, register_operand, const_int_operand, }, + { register_operand, register_operand, register_operand, }, + { general_operand, general_operand, nonmemory_operand, }, + { general_operand, general_operand, nonmemory_operand, }, + { general_operand, general_operand, nonmemory_operand, }, + { general_operand, general_operand, nonmemory_operand, }, + { general_operand, general_operand, nonmemory_operand, }, + { general_operand, general_operand, nonmemory_operand, }, + { general_operand, general_operand, nonmemory_operand, }, + { general_operand, general_operand, nonmemory_operand, }, + { general_operand, general_operand, nonmemory_operand, }, + { general_operand, 0, general_operand, const_int_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { register_operand, general_operand, }, + { register_operand, const_int_operand, const_int_operand, }, + { general_operand, const_int_operand, const_int_operand, }, + { register_operand, }, + { register_operand, }, + { register_operand, }, + { register_operand, }, + { register_operand, }, + { register_operand, }, + { register_operand, }, + { register_operand, }, + { register_operand, }, + { register_operand, }, + { register_operand, }, + { register_operand, }, + { register_operand, }, + { register_operand, }, + { register_operand, }, + { register_operand, }, + { register_operand, }, + { register_operand, }, + { register_operand, }, + { register_operand, }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { general_operand, }, + { general_operand, general_operand, general_operand, 0, 0, 0, scratch_operand, }, + { register_operand, 0, scratch_operand, }, + { general_operand, }, + { indirect_operand, general_operand, 0, immediate_operand, }, + { call_insn_operand, general_operand, 0, immediate_operand, }, + { symbolic_operand, general_operand, 0, immediate_operand, }, + { indirect_operand, general_operand, }, + { call_insn_operand, general_operand, }, + { symbolic_operand, general_operand, }, + { 0, indirect_operand, general_operand, 0, immediate_operand, }, + { 0, call_insn_operand, general_operand, 0, immediate_operand, }, + { 0, symbolic_operand, general_operand, 0, immediate_operand, }, + { 0, indirect_operand, general_operand, }, + { 0, call_insn_operand, general_operand, }, + { 0, symbolic_operand, general_operand, }, + { indirect_operand, memory_operand, 0, }, + { call_insn_operand, memory_operand, 0, }, + { symbolic_operand, memory_operand, 0, }, + { memory_operand, 0, }, + { memory_operand, }, + { 0 }, + { 0 }, + { memory_operand, memory_operand, const_int_operand, const_int_operand, scratch_operand, }, + { address_operand, address_operand, const_int_operand, immediate_operand, scratch_operand, }, + { general_operand, general_operand, general_operand, general_operand, immediate_operand, }, + { general_operand, address_operand, address_operand, register_operand, immediate_operand, }, + { address_operand, address_operand, register_operand, immediate_operand, }, + { general_operand, general_operand, scratch_operand, }, + { register_operand, general_operand, scratch_operand, }, + { general_operand, general_operand, scratch_operand, }, + { register_operand, general_operand, scratch_operand, }, + { register_operand, nonimmediate_operand, nonimmediate_operand, binary_387_op, }, + { register_operand, general_operand, general_operand, binary_387_op, }, + { register_operand, general_operand, general_operand, binary_387_op, }, + { register_operand, general_operand, general_operand, binary_387_op, }, + { register_operand, general_operand, general_operand, binary_387_op, }, + { register_operand, nonimmediate_operand, nonimmediate_operand, binary_387_op, }, + { register_operand, general_operand, general_operand, binary_387_op, }, + { register_operand, general_operand, general_operand, binary_387_op, }, + { register_operand, general_operand, register_operand, immediate_operand, }, + { register_operand, address_operand, register_operand, immediate_operand, }, + }; + +const int insn_n_alternatives[] = + { + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 2, + 0, + 2, + 0, + 2, + 0, + 2, + 1, + 1, + 1, + 1, + 1, + 2, + 1, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 1, + 1, + 1, + 0, + 2, + 1, + 2, + 2, + 1, + 3, + 2, + 2, + 4, + 2, + 1, + 4, + 1, + 2, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 2, + 0, + 2, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 0, + 1, + 1, + 0, + 0, + 0, + 0, + 1, + 1, + 1, + 1, + 2, + 3, + 2, + 2, + 1, + 0, + 0, + 2, + 2, + 2, + 2, + 0, + 0, + 1, + 2, + 1, + 2, + 1, + 0, + 0, + 1, + 1, + 0, + 0, + 1, + 1, + 1, + 1, + 4, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 0, + 1, + 1, + 2, + 1, + 1, + 0, + 1, + 1, + 1, + 1, + 1, + 0, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 1, + 1, + 0, + 1, + 1, + 0, + 1, + 1, + 0, + 1, + 1, + 0, + 1, + 1, + 0, + 1, + 1, + 0, + 1, + 0, + 0, + 0, + 1, + 0, + 1, + 1, + 0, + 1, + 0, + 1, + 2, + 1, + 2, + 1, + 2, + 2, + 1, + 1, + 0, + 1, + }; diff --git a/gnu/usr.bin/gcc2/i386/insn-peep.c b/gnu/usr.bin/gcc2/i386/insn-peep.c new file mode 100644 index 00000000000..37136c4333d --- /dev/null +++ b/gnu/usr.bin/gcc2/i386/insn-peep.c @@ -0,0 +1,28 @@ +/* Generated automatically by the program `genpeep' +from the machine description file `md'. */ + +#include "config.h" +#include "rtl.h" +#include "regs.h" +#include "output.h" +#include "real.h" + +extern rtx peep_operand[]; + +#define operands peep_operand + +rtx +peephole (ins1) + rtx ins1; +{ + rtx insn, x, pat; + int i; + + if (NEXT_INSN (ins1) + && GET_CODE (NEXT_INSN (ins1)) == BARRIER) + return 0; + + return 0; +} + +rtx peep_operand[2]; diff --git a/gnu/usr.bin/gcc2/i386/insn-recog.c b/gnu/usr.bin/gcc2/i386/insn-recog.c new file mode 100644 index 00000000000..bca21b305fe --- /dev/null +++ b/gnu/usr.bin/gcc2/i386/insn-recog.c @@ -0,0 +1,6158 @@ +/* Generated automatically by the program `genrecog' +from the machine description file `md'. */ + +#include "config.h" +#include "rtl.h" +#include "insn-config.h" +#include "recog.h" +#include "real.h" +#include "output.h" +#include "flags.h" + + +/* `recog' contains a decision tree + that recognizes whether the rtx X0 is a valid instruction. + + recog returns -1 if the rtx is not valid. + If the rtx is valid, recog returns a nonnegative number + which is the insn code number for the pattern that matched. + This is the same as the order in the machine description of + the entry that matched. This number can be used as an index into + entry that matched. This number can be used as an index into various + insn_* tables, such as insn_templates, insn_outfun, and insn_n_operands + (found in insn-output.c). + + The third argument to recog is an optional pointer to an int. + If present, recog will accept a pattern if it matches except for + missing CLOBBER expressions at the end. In that case, the value + pointed to by the optional pointer will be set to the number of + CLOBBERs that need to be added (it should be initialized to zero by + the caller). If it is set nonzero, the caller should allocate a + PARALLEL of the appropriate size, copy the initial entries, and call + add_clobbers (found in insn-emit.c) to fill in the CLOBBERs.*/ + +rtx recog_operand[MAX_RECOG_OPERANDS]; + +rtx *recog_operand_loc[MAX_RECOG_OPERANDS]; + +rtx *recog_dup_loc[MAX_DUP_OPERANDS]; + +char recog_dup_num[MAX_DUP_OPERANDS]; + +#define operands recog_operand + +int +recog_1 (x0, insn, pnum_clobbers) + register rtx x0; + rtx insn; + int *pnum_clobbers; +{ + register rtx *ro = &recog_operand[0]; + register rtx x1, x2, x3, x4, x5, x6; + int tem; + + x1 = XEXP (x0, 1); + switch (GET_MODE (x1)) + { + case SImode: + if (nonimmediate_operand (x1, SImode)) + { + ro[0] = x1; + return 0; + } + break; + case HImode: + if (nonimmediate_operand (x1, HImode)) + { + ro[0] = x1; + return 2; + } + break; + case QImode: + if (nonimmediate_operand (x1, QImode)) + { + ro[0] = x1; + return 4; + } + break; + case SFmode: + if (pnum_clobbers != 0 && register_operand (x1, SFmode)) + { + ro[0] = x1; + if (TARGET_80387 && ! TARGET_IEEE_FP) + { + *pnum_clobbers = 1; + return 6; + } + } + break; + case DFmode: + if (pnum_clobbers != 0 && register_operand (x1, DFmode)) + { + ro[0] = x1; + if (TARGET_80387 && ! TARGET_IEEE_FP) + { + *pnum_clobbers = 1; + return 8; + } + } + } + switch (GET_CODE (x1)) + { + case COMPARE: + goto L30; + case ZERO_EXTRACT: + goto L813; + } + L52: + if (VOIDmode_compare_op (x1, VOIDmode)) + { + ro[2] = x1; + goto L82; + } + L125: + switch (GET_MODE (x1)) + { + case CCFPEQmode: + switch (GET_CODE (x1)) + { + case COMPARE: + goto L126; + } + break; + case SImode: + switch (GET_CODE (x1)) + { + case AND: + goto L187; + } + break; + case HImode: + switch (GET_CODE (x1)) + { + case AND: + goto L192; + } + break; + case QImode: + if (GET_CODE (x1) == AND && 1) + goto L197; + } + goto ret0; + + L30: + x2 = XEXP (x1, 0); + switch (GET_MODE (x2)) + { + case SImode: + if (nonimmediate_operand (x2, SImode)) + { + ro[0] = x2; + goto L31; + } + break; + case HImode: + if (nonimmediate_operand (x2, HImode)) + { + ro[0] = x2; + goto L36; + } + break; + case QImode: + if (nonimmediate_operand (x2, QImode)) + { + ro[0] = x2; + goto L41; + } + } + goto L52; + + L31: + x2 = XEXP (x1, 1); + if (general_operand (x2, SImode)) + { + ro[1] = x2; + if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM) + return 10; + } + goto L52; + + L36: + x2 = XEXP (x1, 1); + if (general_operand (x2, HImode)) + { + ro[1] = x2; + if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM) + return 12; + } + goto L52; + + L41: + x2 = XEXP (x1, 1); + if (general_operand (x2, QImode)) + { + ro[1] = x2; + if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM) + return 14; + } + goto L52; + + L813: + x2 = XEXP (x1, 0); + switch (GET_MODE (x2)) + { + case SImode: + if (register_operand (x2, SImode)) + { + ro[0] = x2; + goto L814; + } + break; + case QImode: + if (general_operand (x2, QImode)) + { + ro[0] = x2; + goto L826; + } + } + goto L52; + + L814: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) != CONST_INT) + { + goto L52; + } + if (XWINT (x2, 0) == 1 && 1) + goto L815; + L820: + ro[1] = x2; + goto L821; + + L815: + x2 = XEXP (x1, 2); + if (general_operand (x2, SImode)) + { + ro[1] = x2; + if (GET_CODE (operands[1]) != CONST_INT) + return 167; + } + x2 = XEXP (x1, 1); + goto L820; + + L821: + x2 = XEXP (x1, 2); + if (GET_CODE (x2) == CONST_INT && 1) + { + ro[2] = x2; + return 168; + } + goto L52; + + L826: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && 1) + { + ro[1] = x2; + goto L827; + } + goto L52; + + L827: + x2 = XEXP (x1, 2); + if (GET_CODE (x2) == CONST_INT && 1) + { + ro[2] = x2; + if (GET_CODE (operands[0]) != MEM || ! MEM_VOLATILE_P (operands[0])) + return 169; + } + goto L52; + + L82: + x2 = XEXP (x1, 0); + switch (GET_MODE (x2)) + { + case DFmode: + switch (GET_CODE (x2)) + { + case FLOAT: + goto L83; + case FLOAT_EXTEND: + goto L113; + case SUBREG: + case REG: + case MEM: + if (nonimmediate_operand (x2, DFmode)) + { + ro[0] = x2; + goto L54; + } + } + L67: + if (register_operand (x2, DFmode)) + { + ro[0] = x2; + goto L68; + } + break; + case SFmode: + if (GET_CODE (x2) == FLOAT && 1) + goto L169; + if (nonimmediate_operand (x2, SFmode)) + { + ro[0] = x2; + goto L140; + } + L153: + if (register_operand (x2, SFmode)) + { + ro[0] = x2; + goto L154; + } + } + goto L125; + + L83: + x3 = XEXP (x2, 0); + if (nonimmediate_operand (x3, SImode)) + { + ro[0] = x3; + goto L84; + } + goto L125; + + L84: + x2 = XEXP (x1, 1); + if (pnum_clobbers != 0 && register_operand (x2, DFmode)) + { + ro[1] = x2; + if (TARGET_80387) + { + *pnum_clobbers = 1; + return 18; + } + } + goto L125; + + L113: + x3 = XEXP (x2, 0); + if (nonimmediate_operand (x3, SFmode)) + { + ro[0] = x3; + goto L114; + } + goto L125; + + L114: + x2 = XEXP (x1, 1); + if (pnum_clobbers != 0 && register_operand (x2, DFmode)) + { + ro[1] = x2; + if (TARGET_80387) + { + *pnum_clobbers = 1; + return 20; + } + } + goto L125; + + L54: + x2 = XEXP (x1, 1); + if (pnum_clobbers != 0 && nonimmediate_operand (x2, DFmode)) + { + ro[1] = x2; + if (TARGET_80387 + && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)) + { + *pnum_clobbers = 1; + return 16; + } + } + x2 = XEXP (x1, 0); + goto L67; + + L68: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) != DFmode) + { + goto L125; + } + switch (GET_CODE (x2)) + { + case FLOAT: + goto L69; + case FLOAT_EXTEND: + goto L99; + } + goto L125; + + L69: + x3 = XEXP (x2, 0); + if (pnum_clobbers != 0 && nonimmediate_operand (x3, SImode)) + { + ro[1] = x3; + if (TARGET_80387) + { + *pnum_clobbers = 1; + return 17; + } + } + goto L125; + + L99: + x3 = XEXP (x2, 0); + if (pnum_clobbers != 0 && nonimmediate_operand (x3, SFmode)) + { + ro[1] = x3; + if (TARGET_80387) + { + *pnum_clobbers = 1; + return 19; + } + } + goto L125; + + L169: + x3 = XEXP (x2, 0); + if (nonimmediate_operand (x3, SImode)) + { + ro[0] = x3; + goto L170; + } + goto L125; + + L170: + x2 = XEXP (x1, 1); + if (pnum_clobbers != 0 && register_operand (x2, SFmode)) + { + ro[1] = x2; + if (TARGET_80387) + { + *pnum_clobbers = 1; + return 24; + } + } + goto L125; + + L140: + x2 = XEXP (x1, 1); + if (pnum_clobbers != 0 && nonimmediate_operand (x2, SFmode)) + { + ro[1] = x2; + if (TARGET_80387 + && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)) + { + *pnum_clobbers = 1; + return 22; + } + } + x2 = XEXP (x1, 0); + goto L153; + + L154: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) == SFmode && GET_CODE (x2) == FLOAT && 1) + goto L155; + goto L125; + + L155: + x3 = XEXP (x2, 0); + if (pnum_clobbers != 0 && nonimmediate_operand (x3, SImode)) + { + ro[1] = x3; + if (TARGET_80387) + { + *pnum_clobbers = 1; + return 23; + } + } + goto L125; + + L126: + x2 = XEXP (x1, 0); + switch (GET_MODE (x2)) + { + case DFmode: + if (register_operand (x2, DFmode)) + { + ro[0] = x2; + goto L127; + } + break; + case SFmode: + if (register_operand (x2, SFmode)) + { + ro[0] = x2; + goto L183; + } + } + goto ret0; + + L127: + x2 = XEXP (x1, 1); + if (pnum_clobbers != 0 && register_operand (x2, DFmode)) + { + ro[1] = x2; + if (TARGET_80387) + { + *pnum_clobbers = 1; + return 21; + } + } + goto ret0; + + L183: + x2 = XEXP (x1, 1); + if (pnum_clobbers != 0 && register_operand (x2, SFmode)) + { + ro[1] = x2; + if (TARGET_80387) + { + *pnum_clobbers = 1; + return 25; + } + } + goto ret0; + + L187: + x2 = XEXP (x1, 0); + if (general_operand (x2, SImode)) + { + ro[0] = x2; + goto L188; + } + goto ret0; + + L188: + x2 = XEXP (x1, 1); + if (general_operand (x2, SImode)) + { + ro[1] = x2; + return 32; + } + goto ret0; + + L192: + x2 = XEXP (x1, 0); + if (general_operand (x2, HImode)) + { + ro[0] = x2; + goto L193; + } + goto ret0; + + L193: + x2 = XEXP (x1, 1); + if (general_operand (x2, HImode)) + { + ro[1] = x2; + return 33; + } + goto ret0; + + L197: + x2 = XEXP (x1, 0); + if (general_operand (x2, QImode)) + { + ro[0] = x2; + goto L198; + } + goto ret0; + + L198: + x2 = XEXP (x1, 1); + if (general_operand (x2, QImode)) + { + ro[1] = x2; + return 34; + } + goto ret0; + ret0: return -1; +} + +int +recog_2 (x0, insn, pnum_clobbers) + register rtx x0; + rtx insn; + int *pnum_clobbers; +{ + register rtx *ro = &recog_operand[0]; + register rtx x1, x2, x3, x4, x5, x6; + int tem; + + x1 = XEXP (x0, 1); + x2 = XEXP (x1, 0); + switch (GET_CODE (x2)) + { + case EQ: + goto L882; + case NE: + goto L891; + case GT: + goto L900; + case GTU: + goto L909; + case LT: + goto L918; + case LTU: + goto L927; + case GE: + goto L936; + case GEU: + goto L945; + case LE: + goto L954; + case LEU: + goto L963; + } + goto ret0; + + L882: + x3 = XEXP (x2, 0); + if (GET_CODE (x3) == CC0 && 1) + goto L883; + goto ret0; + + L883: + x3 = XEXP (x2, 1); + if (GET_CODE (x3) == CONST_INT && XWINT (x3, 0) == 0 && 1) + goto L884; + goto ret0; + + L884: + x2 = XEXP (x1, 1); + switch (GET_CODE (x2)) + { + case LABEL_REF: + goto L885; + case PC: + goto L975; + } + goto ret0; + + L885: + x3 = XEXP (x2, 0); + ro[0] = x3; + goto L886; + + L886: + x2 = XEXP (x1, 2); + if (GET_CODE (x2) == PC && 1) + return 191; + goto ret0; + + L975: + x2 = XEXP (x1, 2); + if (GET_CODE (x2) == LABEL_REF && 1) + goto L976; + goto ret0; + + L976: + x3 = XEXP (x2, 0); + ro[0] = x3; + return 210; + + L891: + x3 = XEXP (x2, 0); + if (GET_CODE (x3) == CC0 && 1) + goto L892; + goto ret0; + + L892: + x3 = XEXP (x2, 1); + if (GET_CODE (x3) == CONST_INT && XWINT (x3, 0) == 0 && 1) + goto L893; + goto ret0; + + L893: + x2 = XEXP (x1, 1); + switch (GET_CODE (x2)) + { + case LABEL_REF: + goto L894; + case PC: + goto L984; + } + goto ret0; + + L894: + x3 = XEXP (x2, 0); + ro[0] = x3; + goto L895; + + L895: + x2 = XEXP (x1, 2); + if (GET_CODE (x2) == PC && 1) + return 193; + goto ret0; + + L984: + x2 = XEXP (x1, 2); + if (GET_CODE (x2) == LABEL_REF && 1) + goto L985; + goto ret0; + + L985: + x3 = XEXP (x2, 0); + ro[0] = x3; + return 211; + + L900: + x3 = XEXP (x2, 0); + if (GET_CODE (x3) == CC0 && 1) + goto L901; + goto ret0; + + L901: + x3 = XEXP (x2, 1); + if (GET_CODE (x3) == CONST_INT && XWINT (x3, 0) == 0 && 1) + goto L902; + goto ret0; + + L902: + x2 = XEXP (x1, 1); + switch (GET_CODE (x2)) + { + case LABEL_REF: + goto L903; + case PC: + goto L993; + } + goto ret0; + + L903: + x3 = XEXP (x2, 0); + ro[0] = x3; + goto L904; + + L904: + x2 = XEXP (x1, 2); + if (GET_CODE (x2) == PC && 1) + return 195; + goto ret0; + + L993: + x2 = XEXP (x1, 2); + if (GET_CODE (x2) == LABEL_REF && 1) + goto L994; + goto ret0; + + L994: + x3 = XEXP (x2, 0); + ro[0] = x3; + return 212; + + L909: + x3 = XEXP (x2, 0); + if (GET_CODE (x3) == CC0 && 1) + goto L910; + goto ret0; + + L910: + x3 = XEXP (x2, 1); + if (GET_CODE (x3) == CONST_INT && XWINT (x3, 0) == 0 && 1) + goto L911; + goto ret0; + + L911: + x2 = XEXP (x1, 1); + switch (GET_CODE (x2)) + { + case LABEL_REF: + goto L912; + case PC: + goto L1002; + } + goto ret0; + + L912: + x3 = XEXP (x2, 0); + ro[0] = x3; + goto L913; + + L913: + x2 = XEXP (x1, 2); + if (GET_CODE (x2) == PC && 1) + return 197; + goto ret0; + + L1002: + x2 = XEXP (x1, 2); + if (GET_CODE (x2) == LABEL_REF && 1) + goto L1003; + goto ret0; + + L1003: + x3 = XEXP (x2, 0); + ro[0] = x3; + return 213; + + L918: + x3 = XEXP (x2, 0); + if (GET_CODE (x3) == CC0 && 1) + goto L919; + goto ret0; + + L919: + x3 = XEXP (x2, 1); + if (GET_CODE (x3) == CONST_INT && XWINT (x3, 0) == 0 && 1) + goto L920; + goto ret0; + + L920: + x2 = XEXP (x1, 1); + switch (GET_CODE (x2)) + { + case LABEL_REF: + goto L921; + case PC: + goto L1011; + } + goto ret0; + + L921: + x3 = XEXP (x2, 0); + ro[0] = x3; + goto L922; + + L922: + x2 = XEXP (x1, 2); + if (GET_CODE (x2) == PC && 1) + return 199; + goto ret0; + + L1011: + x2 = XEXP (x1, 2); + if (GET_CODE (x2) == LABEL_REF && 1) + goto L1012; + goto ret0; + + L1012: + x3 = XEXP (x2, 0); + ro[0] = x3; + return 214; + + L927: + x3 = XEXP (x2, 0); + if (GET_CODE (x3) == CC0 && 1) + goto L928; + goto ret0; + + L928: + x3 = XEXP (x2, 1); + if (GET_CODE (x3) == CONST_INT && XWINT (x3, 0) == 0 && 1) + goto L929; + goto ret0; + + L929: + x2 = XEXP (x1, 1); + switch (GET_CODE (x2)) + { + case LABEL_REF: + goto L930; + case PC: + goto L1020; + } + goto ret0; + + L930: + x3 = XEXP (x2, 0); + ro[0] = x3; + goto L931; + + L931: + x2 = XEXP (x1, 2); + if (GET_CODE (x2) == PC && 1) + return 201; + goto ret0; + + L1020: + x2 = XEXP (x1, 2); + if (GET_CODE (x2) == LABEL_REF && 1) + goto L1021; + goto ret0; + + L1021: + x3 = XEXP (x2, 0); + ro[0] = x3; + return 215; + + L936: + x3 = XEXP (x2, 0); + if (GET_CODE (x3) == CC0 && 1) + goto L937; + goto ret0; + + L937: + x3 = XEXP (x2, 1); + if (GET_CODE (x3) == CONST_INT && XWINT (x3, 0) == 0 && 1) + goto L938; + goto ret0; + + L938: + x2 = XEXP (x1, 1); + switch (GET_CODE (x2)) + { + case LABEL_REF: + goto L939; + case PC: + goto L1029; + } + goto ret0; + + L939: + x3 = XEXP (x2, 0); + ro[0] = x3; + goto L940; + + L940: + x2 = XEXP (x1, 2); + if (GET_CODE (x2) == PC && 1) + return 203; + goto ret0; + + L1029: + x2 = XEXP (x1, 2); + if (GET_CODE (x2) == LABEL_REF && 1) + goto L1030; + goto ret0; + + L1030: + x3 = XEXP (x2, 0); + ro[0] = x3; + return 216; + + L945: + x3 = XEXP (x2, 0); + if (GET_CODE (x3) == CC0 && 1) + goto L946; + goto ret0; + + L946: + x3 = XEXP (x2, 1); + if (GET_CODE (x3) == CONST_INT && XWINT (x3, 0) == 0 && 1) + goto L947; + goto ret0; + + L947: + x2 = XEXP (x1, 1); + switch (GET_CODE (x2)) + { + case LABEL_REF: + goto L948; + case PC: + goto L1038; + } + goto ret0; + + L948: + x3 = XEXP (x2, 0); + ro[0] = x3; + goto L949; + + L949: + x2 = XEXP (x1, 2); + if (GET_CODE (x2) == PC && 1) + return 205; + goto ret0; + + L1038: + x2 = XEXP (x1, 2); + if (GET_CODE (x2) == LABEL_REF && 1) + goto L1039; + goto ret0; + + L1039: + x3 = XEXP (x2, 0); + ro[0] = x3; + return 217; + + L954: + x3 = XEXP (x2, 0); + if (GET_CODE (x3) == CC0 && 1) + goto L955; + goto ret0; + + L955: + x3 = XEXP (x2, 1); + if (GET_CODE (x3) == CONST_INT && XWINT (x3, 0) == 0 && 1) + goto L956; + goto ret0; + + L956: + x2 = XEXP (x1, 1); + switch (GET_CODE (x2)) + { + case LABEL_REF: + goto L957; + case PC: + goto L1047; + } + goto ret0; + + L957: + x3 = XEXP (x2, 0); + ro[0] = x3; + goto L958; + + L958: + x2 = XEXP (x1, 2); + if (GET_CODE (x2) == PC && 1) + return 207; + goto ret0; + + L1047: + x2 = XEXP (x1, 2); + if (GET_CODE (x2) == LABEL_REF && 1) + goto L1048; + goto ret0; + + L1048: + x3 = XEXP (x2, 0); + ro[0] = x3; + return 218; + + L963: + x3 = XEXP (x2, 0); + if (GET_CODE (x3) == CC0 && 1) + goto L964; + goto ret0; + + L964: + x3 = XEXP (x2, 1); + if (GET_CODE (x3) == CONST_INT && XWINT (x3, 0) == 0 && 1) + goto L965; + goto ret0; + + L965: + x2 = XEXP (x1, 1); + switch (GET_CODE (x2)) + { + case LABEL_REF: + goto L966; + case PC: + goto L1056; + } + goto ret0; + + L966: + x3 = XEXP (x2, 0); + ro[0] = x3; + goto L967; + + L967: + x2 = XEXP (x1, 2); + if (GET_CODE (x2) == PC && 1) + return 209; + goto ret0; + + L1056: + x2 = XEXP (x1, 2); + if (GET_CODE (x2) == LABEL_REF && 1) + goto L1057; + goto ret0; + + L1057: + x3 = XEXP (x2, 0); + ro[0] = x3; + return 219; + ret0: return -1; +} + +int +recog_3 (x0, insn, pnum_clobbers) + register rtx x0; + rtx insn; + int *pnum_clobbers; +{ + register rtx *ro = &recog_operand[0]; + register rtx x1, x2, x3, x4, x5, x6; + int tem; + + x1 = XEXP (x0, 0); + switch (GET_MODE (x1)) + { + case SImode: + switch (GET_CODE (x1)) + { + case MEM: + if (push_operand (x1, SImode)) + { + ro[0] = x1; + goto L201; + } + break; + case ZERO_EXTRACT: + goto L792; + } + L208: + if (general_operand (x1, SImode)) + { + ro[0] = x1; + goto L257; + } + L431: + if (register_operand (x1, SImode)) + { + ro[0] = x1; + goto L432; + } + L439: + if (general_operand (x1, SImode)) + { + ro[0] = x1; + goto L440; + } + break; + case HImode: + if (GET_CODE (x1) == MEM && push_operand (x1, HImode)) + { + ro[0] = x1; + goto L212; + } + L214: + if (general_operand (x1, HImode)) + { + ro[0] = x1; + goto L261; + } + break; + case QImode: + if (GET_CODE (x1) == MEM && push_operand (x1, QImode)) + { + ro[0] = x1; + goto L222; + } + L224: + if (general_operand (x1, QImode)) + { + ro[0] = x1; + goto L427; + } + L829: + if (register_operand (x1, QImode)) + { + ro[0] = x1; + goto L830; + } + break; + case SFmode: + if (GET_CODE (x1) == MEM && push_operand (x1, SFmode)) + { + ro[0] = x1; + goto L232; + } + L234: + if (general_operand (x1, SFmode)) + { + ro[0] = x1; + goto L235; + } + L399: + if (register_operand (x1, SFmode)) + { + ro[0] = x1; + goto L400; + } + break; + case DFmode: + if (GET_CODE (x1) == MEM && push_operand (x1, DFmode)) + { + ro[0] = x1; + goto L238; + } + L247: + if (general_operand (x1, DFmode)) + { + ro[0] = x1; + goto L289; + } + L395: + if (register_operand (x1, DFmode)) + { + ro[0] = x1; + goto L396; + } + break; + case DImode: + if (GET_CODE (x1) == MEM && push_operand (x1, DImode)) + { + ro[0] = x1; + goto L251; + } + L253: + if (general_operand (x1, DImode)) + { + ro[0] = x1; + goto L412; + } + L268: + if (register_operand (x1, DImode)) + { + ro[0] = x1; + goto L269; + } + } + switch (GET_CODE (x1)) + { + case CC0: + goto L2; + case STRICT_LOW_PART: + goto L218; + case PC: + goto L1081; + } + L1147: + ro[0] = x1; + goto L1148; + L1236: + switch (GET_MODE (x1)) + { + case SImode: + if (register_operand (x1, SImode)) + { + ro[0] = x1; + goto L1237; + } + break; + case HImode: + if (register_operand (x1, HImode)) + { + ro[0] = x1; + goto L1252; + } + break; + case DFmode: + if (register_operand (x1, DFmode)) + { + ro[0] = x1; + goto L1258; + } + break; + case SFmode: + if (register_operand (x1, SFmode)) + { + ro[0] = x1; + goto L1287; + } + } + goto ret0; + + L201: + x1 = XEXP (x0, 1); + if (general_operand (x1, SImode)) + goto L205; + x1 = XEXP (x0, 0); + goto L208; + + L205: + ro[1] = x1; + if (! TARGET_486) + return 35; + L206: + ro[1] = x1; + if (TARGET_486) + return 36; + x1 = XEXP (x0, 0); + goto L208; + + L792: + x2 = XEXP (x1, 0); + if (GET_MODE (x2) == SImode && general_operand (x2, SImode)) + { + ro[0] = x2; + goto L793; + } + goto L1147; + + L793: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && XWINT (x2, 0) == 1 && 1) + goto L794; + goto L1147; + + L794: + x2 = XEXP (x1, 2); + if (general_operand (x2, SImode)) + { + ro[2] = x2; + goto L795; + } + goto L1147; + + L795: + x1 = XEXP (x0, 1); + if (GET_CODE (x1) == CONST_INT && 1) + { + ro[3] = x1; + if (! TARGET_486 && GET_CODE (operands[2]) != CONST_INT) + return 164; + } + x1 = XEXP (x0, 0); + goto L1147; + + L257: + x1 = XEXP (x0, 1); + switch (GET_MODE (x1)) + { + case SImode: + switch (GET_CODE (x1)) + { + case ZERO_EXTEND: + goto L258; + case SIGN_EXTEND: + goto L278; + case PLUS: + goto L418; + } + } + if (general_operand (x1, SImode)) + { + ro[1] = x1; + return 38; + } + x1 = XEXP (x0, 0); + goto L431; + + L258: + x2 = XEXP (x1, 0); + switch (GET_MODE (x2)) + { + case HImode: + if (nonimmediate_operand (x2, HImode)) + { + ro[1] = x2; + return 52; + } + break; + case QImode: + if (nonimmediate_operand (x2, QImode)) + { + ro[1] = x2; + return 54; + } + } + x1 = XEXP (x0, 0); + goto L431; + + L278: + x2 = XEXP (x1, 0); + switch (GET_MODE (x2)) + { + case HImode: + if (nonimmediate_operand (x2, HImode)) + { + ro[1] = x2; + return 57; + } + break; + case QImode: + if (nonimmediate_operand (x2, QImode)) + { + ro[1] = x2; + return 59; + } + } + x1 = XEXP (x0, 0); + goto L431; + + L418: + x2 = XEXP (x1, 0); + if (general_operand (x2, SImode)) + { + ro[1] = x2; + goto L419; + } + x1 = XEXP (x0, 0); + goto L431; + + L419: + x2 = XEXP (x1, 1); + if (general_operand (x2, SImode)) + { + ro[2] = x2; + return 82; + } + x1 = XEXP (x0, 0); + goto L431; + + L432: + x1 = XEXP (x0, 1); + if (address_operand (x1, QImode)) + { + ro[1] = x1; + return 85; + } + x1 = XEXP (x0, 0); + goto L439; + + L440: + x1 = XEXP (x0, 1); + if (GET_MODE (x1) != SImode) + { + x1 = XEXP (x0, 0); + goto L1147; + } + switch (GET_CODE (x1)) + { + case MINUS: + goto L441; + case MULT: + goto L468; + case AND: + goto L541; + case IOR: + goto L556; + case XOR: + goto L799; + case NEG: + goto L590; + case NOT: + goto L667; + case ASHIFT: + goto L692; + case ASHIFTRT: + goto L720; + case LSHIFTRT: + goto L748; + case ROTATE: + goto L763; + case ROTATERT: + goto L778; + } + x1 = XEXP (x0, 0); + goto L1147; + + L441: + x2 = XEXP (x1, 0); + if (general_operand (x2, SImode)) + { + ro[1] = x2; + goto L442; + } + x1 = XEXP (x0, 0); + goto L1147; + + L442: + x2 = XEXP (x1, 1); + if (general_operand (x2, SImode)) + { + ro[2] = x2; + return 89; + } + x1 = XEXP (x0, 0); + goto L1147; + + L468: + x2 = XEXP (x1, 0); + if (general_operand (x2, SImode)) + { + ro[1] = x2; + goto L469; + } + x1 = XEXP (x0, 0); + goto L1147; + + L469: + x2 = XEXP (x1, 1); + if (general_operand (x2, SImode)) + goto L475; + x1 = XEXP (x0, 0); + goto L1147; + + L475: + ro[2] = x2; + if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0x80) + return 96; + L476: + ro[2] = x2; + return 97; + + L541: + x2 = XEXP (x1, 0); + if (general_operand (x2, SImode)) + { + ro[1] = x2; + goto L542; + } + x1 = XEXP (x0, 0); + goto L1147; + + L542: + x2 = XEXP (x1, 1); + if (general_operand (x2, SImode)) + { + ro[2] = x2; + return 109; + } + x1 = XEXP (x0, 0); + goto L1147; + + L556: + x2 = XEXP (x1, 0); + if (general_operand (x2, SImode)) + { + ro[1] = x2; + goto L557; + } + x1 = XEXP (x0, 0); + goto L1147; + + L557: + x2 = XEXP (x1, 1); + if (general_operand (x2, SImode)) + { + ro[2] = x2; + return 112; + } + x1 = XEXP (x0, 0); + goto L1147; + + L799: + x2 = XEXP (x1, 0); + if (GET_MODE (x2) == SImode && GET_CODE (x2) == ASHIFT && 1) + goto L800; + if (general_operand (x2, SImode)) + { + ro[1] = x2; + goto L807; + } + x1 = XEXP (x0, 0); + goto L1147; + + L800: + x3 = XEXP (x2, 0); + if (GET_CODE (x3) == CONST_INT && XWINT (x3, 0) == 1 && 1) + goto L801; + x1 = XEXP (x0, 0); + goto L1147; + + L801: + x3 = XEXP (x2, 1); + if (general_operand (x3, SImode)) + { + ro[1] = x3; + goto L802; + } + x1 = XEXP (x0, 0); + goto L1147; + + L802: + x2 = XEXP (x1, 1); + if (general_operand (x2, SImode)) + { + ro[2] = x2; + if (! TARGET_486 && GET_CODE (operands[1]) != CONST_INT) + return 165; + } + x1 = XEXP (x0, 0); + goto L1147; + + L807: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) == SImode && GET_CODE (x2) == ASHIFT && 1) + goto L808; + if (general_operand (x2, SImode)) + { + ro[2] = x2; + return 115; + } + x1 = XEXP (x0, 0); + goto L1147; + + L808: + x3 = XEXP (x2, 0); + if (GET_CODE (x3) == CONST_INT && XWINT (x3, 0) == 1 && 1) + goto L809; + x1 = XEXP (x0, 0); + goto L1147; + + L809: + x3 = XEXP (x2, 1); + if (general_operand (x3, SImode)) + { + ro[2] = x3; + if (! TARGET_486 && GET_CODE (operands[2]) != CONST_INT) + return 166; + } + x1 = XEXP (x0, 0); + goto L1147; + + L590: + x2 = XEXP (x1, 0); + if (general_operand (x2, SImode)) + { + ro[1] = x2; + return 119; + } + x1 = XEXP (x0, 0); + goto L1147; + + L667: + x2 = XEXP (x1, 0); + if (general_operand (x2, SImode)) + { + ro[1] = x2; + return 137; + } + x1 = XEXP (x0, 0); + goto L1147; + + L692: + x2 = XEXP (x1, 0); + if (general_operand (x2, SImode)) + { + ro[1] = x2; + goto L693; + } + x1 = XEXP (x0, 0); + goto L1147; + + L693: + x2 = XEXP (x1, 1); + if (nonmemory_operand (x2, SImode)) + { + ro[2] = x2; + return 143; + } + x1 = XEXP (x0, 0); + goto L1147; + + L720: + x2 = XEXP (x1, 0); + if (general_operand (x2, SImode)) + { + ro[1] = x2; + goto L721; + } + x1 = XEXP (x0, 0); + goto L1147; + + L721: + x2 = XEXP (x1, 1); + if (nonmemory_operand (x2, SImode)) + { + ro[2] = x2; + return 149; + } + x1 = XEXP (x0, 0); + goto L1147; + + L748: + x2 = XEXP (x1, 0); + if (general_operand (x2, SImode)) + { + ro[1] = x2; + goto L749; + } + x1 = XEXP (x0, 0); + goto L1147; + + L749: + x2 = XEXP (x1, 1); + if (nonmemory_operand (x2, SImode)) + { + ro[2] = x2; + return 155; + } + x1 = XEXP (x0, 0); + goto L1147; + + L763: + x2 = XEXP (x1, 0); + if (general_operand (x2, SImode)) + { + ro[1] = x2; + goto L764; + } + x1 = XEXP (x0, 0); + goto L1147; + + L764: + x2 = XEXP (x1, 1); + if (nonmemory_operand (x2, SImode)) + { + ro[2] = x2; + return 158; + } + x1 = XEXP (x0, 0); + goto L1147; + + L778: + x2 = XEXP (x1, 0); + if (general_operand (x2, SImode)) + { + ro[1] = x2; + goto L779; + } + x1 = XEXP (x0, 0); + goto L1147; + + L779: + x2 = XEXP (x1, 1); + if (nonmemory_operand (x2, SImode)) + { + ro[2] = x2; + return 161; + } + x1 = XEXP (x0, 0); + goto L1147; + + L212: + x1 = XEXP (x0, 1); + if (general_operand (x1, HImode)) + { + ro[1] = x1; + return 39; + } + x1 = XEXP (x0, 0); + goto L214; + + L261: + x1 = XEXP (x0, 1); + switch (GET_MODE (x1)) + { + case HImode: + switch (GET_CODE (x1)) + { + case ZERO_EXTEND: + goto L262; + case SIGN_EXTEND: + goto L282; + case PLUS: + goto L423; + case MINUS: + goto L446; + case AND: + goto L546; + case IOR: + goto L561; + case XOR: + goto L576; + case NEG: + goto L594; + case NOT: + goto L671; + case ASHIFT: + goto L697; + case ASHIFTRT: + goto L725; + case LSHIFTRT: + goto L753; + case ROTATE: + goto L768; + case ROTATERT: + goto L783; + } + break; + case SImode: + if (GET_CODE (x1) == MULT && 1) + goto L480; + } + if (general_operand (x1, HImode)) + { + ro[1] = x1; + return 40; + } + x1 = XEXP (x0, 0); + goto L1147; + + L262: + x2 = XEXP (x1, 0); + if (nonimmediate_operand (x2, QImode)) + { + ro[1] = x2; + return 53; + } + x1 = XEXP (x0, 0); + goto L1147; + + L282: + x2 = XEXP (x1, 0); + if (nonimmediate_operand (x2, QImode)) + { + ro[1] = x2; + return 58; + } + x1 = XEXP (x0, 0); + goto L1147; + + L423: + x2 = XEXP (x1, 0); + if (general_operand (x2, HImode)) + { + ro[1] = x2; + goto L424; + } + x1 = XEXP (x0, 0); + goto L1147; + + L424: + x2 = XEXP (x1, 1); + if (general_operand (x2, HImode)) + { + ro[2] = x2; + return 83; + } + x1 = XEXP (x0, 0); + goto L1147; + + L446: + x2 = XEXP (x1, 0); + if (general_operand (x2, HImode)) + { + ro[1] = x2; + goto L447; + } + x1 = XEXP (x0, 0); + goto L1147; + + L447: + x2 = XEXP (x1, 1); + if (general_operand (x2, HImode)) + { + ro[2] = x2; + return 90; + } + x1 = XEXP (x0, 0); + goto L1147; + + L546: + x2 = XEXP (x1, 0); + if (general_operand (x2, HImode)) + { + ro[1] = x2; + goto L547; + } + x1 = XEXP (x0, 0); + goto L1147; + + L547: + x2 = XEXP (x1, 1); + if (general_operand (x2, HImode)) + { + ro[2] = x2; + return 110; + } + x1 = XEXP (x0, 0); + goto L1147; + + L561: + x2 = XEXP (x1, 0); + if (general_operand (x2, HImode)) + { + ro[1] = x2; + goto L562; + } + x1 = XEXP (x0, 0); + goto L1147; + + L562: + x2 = XEXP (x1, 1); + if (general_operand (x2, HImode)) + { + ro[2] = x2; + return 113; + } + x1 = XEXP (x0, 0); + goto L1147; + + L576: + x2 = XEXP (x1, 0); + if (general_operand (x2, HImode)) + { + ro[1] = x2; + goto L577; + } + x1 = XEXP (x0, 0); + goto L1147; + + L577: + x2 = XEXP (x1, 1); + if (general_operand (x2, HImode)) + { + ro[2] = x2; + return 116; + } + x1 = XEXP (x0, 0); + goto L1147; + + L594: + x2 = XEXP (x1, 0); + if (general_operand (x2, HImode)) + { + ro[1] = x2; + return 120; + } + x1 = XEXP (x0, 0); + goto L1147; + + L671: + x2 = XEXP (x1, 0); + if (general_operand (x2, HImode)) + { + ro[1] = x2; + return 138; + } + x1 = XEXP (x0, 0); + goto L1147; + + L697: + x2 = XEXP (x1, 0); + if (general_operand (x2, HImode)) + { + ro[1] = x2; + goto L698; + } + x1 = XEXP (x0, 0); + goto L1147; + + L698: + x2 = XEXP (x1, 1); + if (nonmemory_operand (x2, HImode)) + { + ro[2] = x2; + return 144; + } + x1 = XEXP (x0, 0); + goto L1147; + + L725: + x2 = XEXP (x1, 0); + if (general_operand (x2, HImode)) + { + ro[1] = x2; + goto L726; + } + x1 = XEXP (x0, 0); + goto L1147; + + L726: + x2 = XEXP (x1, 1); + if (nonmemory_operand (x2, HImode)) + { + ro[2] = x2; + return 150; + } + x1 = XEXP (x0, 0); + goto L1147; + + L753: + x2 = XEXP (x1, 0); + if (general_operand (x2, HImode)) + { + ro[1] = x2; + goto L754; + } + x1 = XEXP (x0, 0); + goto L1147; + + L754: + x2 = XEXP (x1, 1); + if (nonmemory_operand (x2, HImode)) + { + ro[2] = x2; + return 156; + } + x1 = XEXP (x0, 0); + goto L1147; + + L768: + x2 = XEXP (x1, 0); + if (general_operand (x2, HImode)) + { + ro[1] = x2; + goto L769; + } + x1 = XEXP (x0, 0); + goto L1147; + + L769: + x2 = XEXP (x1, 1); + if (nonmemory_operand (x2, HImode)) + { + ro[2] = x2; + return 159; + } + x1 = XEXP (x0, 0); + goto L1147; + + L783: + x2 = XEXP (x1, 0); + if (general_operand (x2, HImode)) + { + ro[1] = x2; + goto L784; + } + x1 = XEXP (x0, 0); + goto L1147; + + L784: + x2 = XEXP (x1, 1); + if (nonmemory_operand (x2, HImode)) + { + ro[2] = x2; + return 162; + } + x1 = XEXP (x0, 0); + goto L1147; + + L480: + x2 = XEXP (x1, 0); + if (GET_MODE (x2) == HImode && GET_CODE (x2) == ZERO_EXTEND && 1) + goto L481; + if (general_operand (x2, HImode)) + { + ro[1] = x2; + goto L457; + } + x1 = XEXP (x0, 0); + goto L1147; + + L481: + x3 = XEXP (x2, 0); + if (nonimmediate_operand (x3, QImode)) + { + ro[1] = x3; + goto L482; + } + x1 = XEXP (x0, 0); + goto L1147; + + L482: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) == HImode && GET_CODE (x2) == ZERO_EXTEND && 1) + goto L483; + x1 = XEXP (x0, 0); + goto L1147; + + L483: + x3 = XEXP (x2, 0); + if (nonimmediate_operand (x3, QImode)) + { + ro[2] = x3; + return 98; + } + x1 = XEXP (x0, 0); + goto L1147; + + L457: + x2 = XEXP (x1, 1); + if (general_operand (x2, HImode)) + goto L463; + x1 = XEXP (x0, 0); + goto L1147; + + L463: + ro[2] = x2; + if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0x80) + return 94; + L464: + ro[2] = x2; + return 95; + + L222: + x1 = XEXP (x0, 1); + if (general_operand (x1, QImode)) + { + ro[1] = x1; + return 42; + } + x1 = XEXP (x0, 0); + goto L224; + + L427: + x1 = XEXP (x0, 1); + switch (GET_MODE (x1)) + { + case QImode: + switch (GET_CODE (x1)) + { + case PLUS: + goto L428; + case MINUS: + goto L451; + case DIV: + goto L487; + case UDIV: + goto L492; + case AND: + goto L551; + case IOR: + goto L566; + case XOR: + goto L581; + case NEG: + goto L598; + case NOT: + goto L675; + case ASHIFT: + goto L702; + case ASHIFTRT: + goto L730; + case LSHIFTRT: + goto L758; + case ROTATE: + goto L773; + case ROTATERT: + goto L788; + } + } + if (general_operand (x1, QImode)) + { + ro[1] = x1; + return 43; + } + x1 = XEXP (x0, 0); + goto L829; + + L428: + x2 = XEXP (x1, 0); + if (general_operand (x2, QImode)) + { + ro[1] = x2; + goto L429; + } + x1 = XEXP (x0, 0); + goto L829; + + L429: + x2 = XEXP (x1, 1); + if (general_operand (x2, QImode)) + { + ro[2] = x2; + return 84; + } + x1 = XEXP (x0, 0); + goto L829; + + L451: + x2 = XEXP (x1, 0); + if (general_operand (x2, QImode)) + { + ro[1] = x2; + goto L452; + } + x1 = XEXP (x0, 0); + goto L829; + + L452: + x2 = XEXP (x1, 1); + if (general_operand (x2, QImode)) + { + ro[2] = x2; + return 91; + } + x1 = XEXP (x0, 0); + goto L829; + + L487: + x2 = XEXP (x1, 0); + if (general_operand (x2, HImode)) + { + ro[1] = x2; + goto L488; + } + x1 = XEXP (x0, 0); + goto L829; + + L488: + x2 = XEXP (x1, 1); + if (general_operand (x2, QImode)) + { + ro[2] = x2; + return 101; + } + x1 = XEXP (x0, 0); + goto L829; + + L492: + x2 = XEXP (x1, 0); + if (general_operand (x2, HImode)) + { + ro[1] = x2; + goto L493; + } + x1 = XEXP (x0, 0); + goto L829; + + L493: + x2 = XEXP (x1, 1); + if (general_operand (x2, QImode)) + { + ro[2] = x2; + return 102; + } + x1 = XEXP (x0, 0); + goto L829; + + L551: + x2 = XEXP (x1, 0); + if (general_operand (x2, QImode)) + { + ro[1] = x2; + goto L552; + } + x1 = XEXP (x0, 0); + goto L829; + + L552: + x2 = XEXP (x1, 1); + if (general_operand (x2, QImode)) + { + ro[2] = x2; + return 111; + } + x1 = XEXP (x0, 0); + goto L829; + + L566: + x2 = XEXP (x1, 0); + if (general_operand (x2, QImode)) + { + ro[1] = x2; + goto L567; + } + x1 = XEXP (x0, 0); + goto L829; + + L567: + x2 = XEXP (x1, 1); + if (general_operand (x2, QImode)) + { + ro[2] = x2; + return 114; + } + x1 = XEXP (x0, 0); + goto L829; + + L581: + x2 = XEXP (x1, 0); + if (general_operand (x2, QImode)) + { + ro[1] = x2; + goto L582; + } + x1 = XEXP (x0, 0); + goto L829; + + L582: + x2 = XEXP (x1, 1); + if (general_operand (x2, QImode)) + { + ro[2] = x2; + return 117; + } + x1 = XEXP (x0, 0); + goto L829; + + L598: + x2 = XEXP (x1, 0); + if (general_operand (x2, QImode)) + { + ro[1] = x2; + return 121; + } + x1 = XEXP (x0, 0); + goto L829; + + L675: + x2 = XEXP (x1, 0); + if (general_operand (x2, QImode)) + { + ro[1] = x2; + return 139; + } + x1 = XEXP (x0, 0); + goto L829; + + L702: + x2 = XEXP (x1, 0); + if (general_operand (x2, QImode)) + { + ro[1] = x2; + goto L703; + } + x1 = XEXP (x0, 0); + goto L829; + + L703: + x2 = XEXP (x1, 1); + if (nonmemory_operand (x2, QImode)) + { + ro[2] = x2; + return 145; + } + x1 = XEXP (x0, 0); + goto L829; + + L730: + x2 = XEXP (x1, 0); + if (general_operand (x2, QImode)) + { + ro[1] = x2; + goto L731; + } + x1 = XEXP (x0, 0); + goto L829; + + L731: + x2 = XEXP (x1, 1); + if (nonmemory_operand (x2, QImode)) + { + ro[2] = x2; + return 151; + } + x1 = XEXP (x0, 0); + goto L829; + + L758: + x2 = XEXP (x1, 0); + if (general_operand (x2, QImode)) + { + ro[1] = x2; + goto L759; + } + x1 = XEXP (x0, 0); + goto L829; + + L759: + x2 = XEXP (x1, 1); + if (nonmemory_operand (x2, QImode)) + { + ro[2] = x2; + return 157; + } + x1 = XEXP (x0, 0); + goto L829; + + L773: + x2 = XEXP (x1, 0); + if (general_operand (x2, QImode)) + { + ro[1] = x2; + goto L774; + } + x1 = XEXP (x0, 0); + goto L829; + + L774: + x2 = XEXP (x1, 1); + if (nonmemory_operand (x2, QImode)) + { + ro[2] = x2; + return 160; + } + x1 = XEXP (x0, 0); + goto L829; + + L788: + x2 = XEXP (x1, 0); + if (general_operand (x2, QImode)) + { + ro[1] = x2; + goto L789; + } + x1 = XEXP (x0, 0); + goto L829; + + L789: + x2 = XEXP (x1, 1); + if (nonmemory_operand (x2, QImode)) + { + ro[2] = x2; + return 163; + } + x1 = XEXP (x0, 0); + goto L829; + + L830: + x1 = XEXP (x0, 1); + if (GET_MODE (x1) != QImode) + { + x1 = XEXP (x0, 0); + goto L1147; + } + switch (GET_CODE (x1)) + { + case EQ: + goto L831; + case NE: + goto L836; + case GT: + goto L841; + case GTU: + goto L846; + case LT: + goto L851; + case LTU: + goto L856; + case GE: + goto L861; + case GEU: + goto L866; + case LE: + goto L871; + case LEU: + goto L876; + } + x1 = XEXP (x0, 0); + goto L1147; + + L831: + x2 = XEXP (x1, 0); + if (GET_CODE (x2) == CC0 && 1) + goto L832; + x1 = XEXP (x0, 0); + goto L1147; + + L832: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && XWINT (x2, 0) == 0 && 1) + return 171; + x1 = XEXP (x0, 0); + goto L1147; + + L836: + x2 = XEXP (x1, 0); + if (GET_CODE (x2) == CC0 && 1) + goto L837; + x1 = XEXP (x0, 0); + goto L1147; + + L837: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && XWINT (x2, 0) == 0 && 1) + return 173; + x1 = XEXP (x0, 0); + goto L1147; + + L841: + x2 = XEXP (x1, 0); + if (GET_CODE (x2) == CC0 && 1) + goto L842; + x1 = XEXP (x0, 0); + goto L1147; + + L842: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && XWINT (x2, 0) == 0 && 1) + return 175; + x1 = XEXP (x0, 0); + goto L1147; + + L846: + x2 = XEXP (x1, 0); + if (GET_CODE (x2) == CC0 && 1) + goto L847; + x1 = XEXP (x0, 0); + goto L1147; + + L847: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && XWINT (x2, 0) == 0 && 1) + return 177; + x1 = XEXP (x0, 0); + goto L1147; + + L851: + x2 = XEXP (x1, 0); + if (GET_CODE (x2) == CC0 && 1) + goto L852; + x1 = XEXP (x0, 0); + goto L1147; + + L852: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && XWINT (x2, 0) == 0 && 1) + return 179; + x1 = XEXP (x0, 0); + goto L1147; + + L856: + x2 = XEXP (x1, 0); + if (GET_CODE (x2) == CC0 && 1) + goto L857; + x1 = XEXP (x0, 0); + goto L1147; + + L857: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && XWINT (x2, 0) == 0 && 1) + return 181; + x1 = XEXP (x0, 0); + goto L1147; + + L861: + x2 = XEXP (x1, 0); + if (GET_CODE (x2) == CC0 && 1) + goto L862; + x1 = XEXP (x0, 0); + goto L1147; + + L862: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && XWINT (x2, 0) == 0 && 1) + return 183; + x1 = XEXP (x0, 0); + goto L1147; + + L866: + x2 = XEXP (x1, 0); + if (GET_CODE (x2) == CC0 && 1) + goto L867; + x1 = XEXP (x0, 0); + goto L1147; + + L867: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && XWINT (x2, 0) == 0 && 1) + return 185; + x1 = XEXP (x0, 0); + goto L1147; + + L871: + x2 = XEXP (x1, 0); + if (GET_CODE (x2) == CC0 && 1) + goto L872; + x1 = XEXP (x0, 0); + goto L1147; + + L872: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && XWINT (x2, 0) == 0 && 1) + return 187; + x1 = XEXP (x0, 0); + goto L1147; + + L876: + x2 = XEXP (x1, 0); + if (GET_CODE (x2) == CC0 && 1) + goto L877; + x1 = XEXP (x0, 0); + goto L1147; + + L877: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && XWINT (x2, 0) == 0 && 1) + return 189; + x1 = XEXP (x0, 0); + goto L1147; + + L232: + x1 = XEXP (x0, 1); + if (general_operand (x1, SFmode)) + { + ro[1] = x1; + return 45; + } + x1 = XEXP (x0, 0); + goto L234; + + L235: + x1 = XEXP (x0, 1); + if (general_operand (x1, SFmode)) + { + ro[1] = x1; + return 46; + } + x1 = XEXP (x0, 0); + goto L399; + + L400: + x1 = XEXP (x0, 1); + if (GET_MODE (x1) != SFmode) + { + x1 = XEXP (x0, 0); + goto L1147; + } + switch (GET_CODE (x1)) + { + case FLOAT: + goto L401; + case NEG: + goto L602; + case ABS: + goto L615; + case SQRT: + goto L628; + case UNSPEC: + if (XINT (x1, 1) == 1 && XVECLEN (x1, 0) == 1 && 1) + goto L645; + if (XINT (x1, 1) == 2 && XVECLEN (x1, 0) == 1 && 1) + goto L658; + } + x1 = XEXP (x0, 0); + goto L1147; + + L401: + x2 = XEXP (x1, 0); + switch (GET_MODE (x2)) + { + case DImode: + if (nonimmediate_operand (x2, DImode)) + { + ro[1] = x2; + if (TARGET_80387) + return 78; + } + break; + case SImode: + if (nonimmediate_operand (x2, SImode)) + { + ro[1] = x2; + if (TARGET_80387) + return 80; + } + } + x1 = XEXP (x0, 0); + goto L1147; + + L602: + x2 = XEXP (x1, 0); + if (general_operand (x2, SFmode)) + { + ro[1] = x2; + if (TARGET_80387) + return 122; + } + x1 = XEXP (x0, 0); + goto L1147; + + L615: + x2 = XEXP (x1, 0); + if (general_operand (x2, SFmode)) + { + ro[1] = x2; + if (TARGET_80387) + return 125; + } + x1 = XEXP (x0, 0); + goto L1147; + + L628: + x2 = XEXP (x1, 0); + if (general_operand (x2, SFmode)) + { + ro[1] = x2; + if (TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)) + return 128; + } + x1 = XEXP (x0, 0); + goto L1147; + + L645: + x2 = XVECEXP (x1, 0, 0); + if (register_operand (x2, SFmode)) + { + ro[1] = x2; + if (TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)) + return 132; + } + x1 = XEXP (x0, 0); + goto L1147; + + L658: + x2 = XVECEXP (x1, 0, 0); + if (register_operand (x2, SFmode)) + { + ro[1] = x2; + if (TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)) + return 135; + } + x1 = XEXP (x0, 0); + goto L1147; + + L238: + x1 = XEXP (x0, 1); + if (general_operand (x1, DFmode)) + { + ro[1] = x1; + return 47; + } + x1 = XEXP (x0, 0); + goto L247; + + L289: + x1 = XEXP (x0, 1); + if (GET_MODE (x1) == DFmode && GET_CODE (x1) == FLOAT_EXTEND && 1) + goto L290; + if (general_operand (x1, DFmode)) + { + ro[1] = x1; + return 49; + } + x1 = XEXP (x0, 0); + goto L395; + + L290: + x2 = XEXP (x1, 0); + if (general_operand (x2, SFmode)) + { + ro[1] = x2; + if (TARGET_80387) + return 60; + } + x1 = XEXP (x0, 0); + goto L395; + + L396: + x1 = XEXP (x0, 1); + if (GET_MODE (x1) != DFmode) + { + x1 = XEXP (x0, 0); + goto L1147; + } + switch (GET_CODE (x1)) + { + case FLOAT: + goto L397; + case NEG: + goto L610; + case ABS: + goto L623; + case SQRT: + goto L636; + case UNSPEC: + if (XINT (x1, 1) == 1 && XVECLEN (x1, 0) == 1 && 1) + goto L649; + if (XINT (x1, 1) == 2 && XVECLEN (x1, 0) == 1 && 1) + goto L662; + } + x1 = XEXP (x0, 0); + goto L1147; + + L397: + x2 = XEXP (x1, 0); + switch (GET_MODE (x2)) + { + case DImode: + if (nonimmediate_operand (x2, DImode)) + { + ro[1] = x2; + if (TARGET_80387) + return 77; + } + break; + case SImode: + if (nonimmediate_operand (x2, SImode)) + { + ro[1] = x2; + if (TARGET_80387) + return 79; + } + } + x1 = XEXP (x0, 0); + goto L1147; + + L610: + x2 = XEXP (x1, 0); + if (GET_MODE (x2) == DFmode && GET_CODE (x2) == FLOAT_EXTEND && 1) + goto L611; + if (general_operand (x2, DFmode)) + { + ro[1] = x2; + if (TARGET_80387) + return 123; + } + x1 = XEXP (x0, 0); + goto L1147; + + L611: + x3 = XEXP (x2, 0); + if (general_operand (x3, SFmode)) + { + ro[1] = x3; + if (TARGET_80387) + return 124; + } + x1 = XEXP (x0, 0); + goto L1147; + + L623: + x2 = XEXP (x1, 0); + if (GET_MODE (x2) == DFmode && GET_CODE (x2) == FLOAT_EXTEND && 1) + goto L624; + if (general_operand (x2, DFmode)) + { + ro[1] = x2; + if (TARGET_80387) + return 126; + } + x1 = XEXP (x0, 0); + goto L1147; + + L624: + x3 = XEXP (x2, 0); + if (general_operand (x3, SFmode)) + { + ro[1] = x3; + if (TARGET_80387) + return 127; + } + x1 = XEXP (x0, 0); + goto L1147; + + L636: + x2 = XEXP (x1, 0); + if (GET_MODE (x2) == DFmode && GET_CODE (x2) == FLOAT_EXTEND && 1) + goto L637; + if (general_operand (x2, DFmode)) + { + ro[1] = x2; + if (TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)) + return 129; + } + x1 = XEXP (x0, 0); + goto L1147; + + L637: + x3 = XEXP (x2, 0); + if (general_operand (x3, SFmode)) + { + ro[1] = x3; + if (TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)) + return 130; + } + x1 = XEXP (x0, 0); + goto L1147; + + L649: + x2 = XVECEXP (x1, 0, 0); + if (GET_MODE (x2) != DFmode) + { + x1 = XEXP (x0, 0); + goto L1147; + } + if (GET_CODE (x2) == FLOAT_EXTEND && 1) + goto L650; + if (register_operand (x2, DFmode)) + { + ro[1] = x2; + if (TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)) + return 131; + } + x1 = XEXP (x0, 0); + goto L1147; + + L650: + x3 = XEXP (x2, 0); + if (register_operand (x3, SFmode)) + { + ro[1] = x3; + if (TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)) + return 133; + } + x1 = XEXP (x0, 0); + goto L1147; + + L662: + x2 = XVECEXP (x1, 0, 0); + if (GET_MODE (x2) != DFmode) + { + x1 = XEXP (x0, 0); + goto L1147; + } + if (GET_CODE (x2) == FLOAT_EXTEND && 1) + goto L663; + if (register_operand (x2, DFmode)) + { + ro[1] = x2; + if (TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)) + return 134; + } + x1 = XEXP (x0, 0); + goto L1147; + + L663: + x3 = XEXP (x2, 0); + if (register_operand (x3, SFmode)) + { + ro[1] = x3; + if (TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)) + return 136; + } + x1 = XEXP (x0, 0); + goto L1147; + + L251: + x1 = XEXP (x0, 1); + if (general_operand (x1, DImode)) + { + ro[1] = x1; + return 50; + } + x1 = XEXP (x0, 0); + goto L253; + + L412: + x1 = XEXP (x0, 1); + switch (GET_MODE (x1)) + { + case DImode: + switch (GET_CODE (x1)) + { + case PLUS: + goto L413; + case MINUS: + goto L436; + case NEG: + goto L586; + } + } + if (general_operand (x1, DImode)) + { + ro[1] = x1; + return 51; + } + x1 = XEXP (x0, 0); + goto L268; + + L413: + x2 = XEXP (x1, 0); + if (general_operand (x2, DImode)) + { + ro[1] = x2; + goto L414; + } + x1 = XEXP (x0, 0); + goto L268; + + L414: + x2 = XEXP (x1, 1); + if (general_operand (x2, DImode)) + { + ro[2] = x2; + return 81; + } + x1 = XEXP (x0, 0); + goto L268; + + L436: + x2 = XEXP (x1, 0); + if (general_operand (x2, DImode)) + { + ro[1] = x2; + goto L437; + } + x1 = XEXP (x0, 0); + goto L268; + + L437: + x2 = XEXP (x1, 1); + if (general_operand (x2, DImode)) + { + ro[2] = x2; + return 88; + } + x1 = XEXP (x0, 0); + goto L268; + + L586: + x2 = XEXP (x1, 0); + if (general_operand (x2, DImode)) + { + ro[1] = x2; + return 118; + } + x1 = XEXP (x0, 0); + goto L268; + + L269: + x1 = XEXP (x0, 1); + if (GET_MODE (x1) != DImode) + { + x1 = XEXP (x0, 0); + goto L1147; + } + switch (GET_CODE (x1)) + { + case ZERO_EXTEND: + goto L270; + case SIGN_EXTEND: + goto L274; + case ASHIFT: + goto L679; + case ASHIFTRT: + goto L707; + case LSHIFTRT: + goto L735; + } + x1 = XEXP (x0, 0); + goto L1147; + + L270: + x2 = XEXP (x1, 0); + if (register_operand (x2, SImode)) + { + ro[1] = x2; + return 55; + } + x1 = XEXP (x0, 0); + goto L1147; + + L274: + x2 = XEXP (x1, 0); + if (register_operand (x2, SImode)) + { + ro[1] = x2; + return 56; + } + x1 = XEXP (x0, 0); + goto L1147; + + L679: + x2 = XEXP (x1, 0); + if (register_operand (x2, DImode)) + { + ro[1] = x2; + goto L680; + } + x1 = XEXP (x0, 0); + goto L1147; + + L680: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && 1) + { + ro[2] = x2; + return 141; + } + x1 = XEXP (x0, 0); + goto L1147; + + L707: + x2 = XEXP (x1, 0); + if (register_operand (x2, DImode)) + { + ro[1] = x2; + goto L708; + } + x1 = XEXP (x0, 0); + goto L1147; + + L708: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && 1) + { + ro[2] = x2; + return 147; + } + x1 = XEXP (x0, 0); + goto L1147; + + L735: + x2 = XEXP (x1, 0); + if (register_operand (x2, DImode)) + { + ro[1] = x2; + goto L736; + } + x1 = XEXP (x0, 0); + goto L1147; + + L736: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && 1) + { + ro[2] = x2; + return 153; + } + x1 = XEXP (x0, 0); + goto L1147; + L2: + tem = recog_1 (x0, insn, pnum_clobbers); + if (tem >= 0) return tem; + x1 = XEXP (x0, 0); + goto L1147; + + L218: + x2 = XEXP (x1, 0); + switch (GET_MODE (x2)) + { + case HImode: + if (general_operand (x2, HImode)) + { + ro[0] = x2; + goto L219; + } + break; + case QImode: + if (general_operand (x2, QImode)) + { + ro[0] = x2; + goto L229; + } + } + goto L1147; + + L219: + x1 = XEXP (x0, 1); + if (general_operand (x1, HImode)) + { + ro[1] = x1; + return 41; + } + x1 = XEXP (x0, 0); + goto L1147; + + L229: + x1 = XEXP (x0, 1); + if (general_operand (x1, QImode)) + { + ro[1] = x1; + return 44; + } + x1 = XEXP (x0, 0); + goto L1147; + + L1081: + x1 = XEXP (x0, 1); + switch (GET_CODE (x1)) + { + case MINUS: + if (GET_MODE (x1) == SImode && 1) + goto L1082; + break; + case IF_THEN_ELSE: + goto L881; + case LABEL_REF: + goto L1061; + } + L1064: + if (general_operand (x1, SImode)) + { + ro[0] = x1; + return 221; + } + x1 = XEXP (x0, 0); + goto L1147; + + L1082: + x2 = XEXP (x1, 0); + if (GET_MODE (x2) == SImode && GET_CODE (x2) == REG && XINT (x2, 0) == 3 && 1) + goto L1083; + x1 = XEXP (x0, 0); + goto L1147; + + L1083: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) == SImode && GET_CODE (x2) == MEM && 1) + goto L1084; + x1 = XEXP (x0, 0); + goto L1147; + + L1084: + x3 = XEXP (x2, 0); + if (GET_MODE (x3) == SImode && GET_CODE (x3) == PLUS && 1) + goto L1085; + x1 = XEXP (x0, 0); + goto L1147; + + L1085: + x4 = XEXP (x3, 0); + if (GET_MODE (x4) == SImode && GET_CODE (x4) == MULT && 1) + goto L1086; + x1 = XEXP (x0, 0); + goto L1147; + + L1086: + x5 = XEXP (x4, 0); + if (register_operand (x5, SImode)) + { + ro[0] = x5; + goto L1087; + } + x1 = XEXP (x0, 0); + goto L1147; + + L1087: + x5 = XEXP (x4, 1); + if (GET_CODE (x5) == CONST_INT && XWINT (x5, 0) == 4 && 1) + goto L1088; + x1 = XEXP (x0, 0); + goto L1147; + + L1088: + x4 = XEXP (x3, 1); + if (GET_CODE (x4) == LABEL_REF && 1) + goto L1089; + x1 = XEXP (x0, 0); + goto L1147; + + L1089: + x5 = XEXP (x4, 0); + if (pnum_clobbers != 0 && 1) + { + ro[1] = x5; + *pnum_clobbers = 1; + return 223; + } + x1 = XEXP (x0, 0); + goto L1147; + L881: + tem = recog_2 (x0, insn, pnum_clobbers); + if (tem >= 0) return tem; + x1 = XEXP (x0, 0); + goto L1147; + + L1061: + x2 = XEXP (x1, 0); + ro[0] = x2; + return 220; + + L1148: + x1 = XEXP (x0, 1); + if (GET_CODE (x1) == CALL && 1) + goto L1149; + x1 = XEXP (x0, 0); + goto L1236; + + L1149: + x2 = XEXP (x1, 0); + if (call_insn_operand (x2, QImode)) + { + ro[1] = x2; + goto L1150; + } + L1154: + if (GET_MODE (x2) == QImode && GET_CODE (x2) == MEM && 1) + goto L1155; + x1 = XEXP (x0, 0); + goto L1236; + + L1150: + x2 = XEXP (x1, 1); + if (general_operand (x2, SImode)) + { + ro[2] = x2; + return 235; + } + x2 = XEXP (x1, 0); + goto L1154; + + L1155: + x3 = XEXP (x2, 0); + if (symbolic_operand (x3, SImode)) + { + ro[1] = x3; + goto L1156; + } + x1 = XEXP (x0, 0); + goto L1236; + + L1156: + x2 = XEXP (x1, 1); + if (general_operand (x2, SImode)) + { + ro[2] = x2; + if (!HALF_PIC_P ()) + return 236; + } + x1 = XEXP (x0, 0); + goto L1236; + + L1237: + x1 = XEXP (x0, 1); + if (GET_MODE (x1) == SImode && GET_CODE (x1) == PLUS && 1) + goto L1238; + goto ret0; + + L1238: + x2 = XEXP (x1, 0); + if (GET_MODE (x2) == SImode && GET_CODE (x2) == FFS && 1) + goto L1239; + goto ret0; + + L1239: + x3 = XEXP (x2, 0); + if (general_operand (x3, SImode)) + { + ro[1] = x3; + goto L1240; + } + goto ret0; + + L1240: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && XWINT (x2, 0) == -1 && pnum_clobbers != 0 && 1) + { + *pnum_clobbers = 1; + return 250; + } + goto ret0; + + L1252: + x1 = XEXP (x0, 1); + if (GET_MODE (x1) == HImode && GET_CODE (x1) == PLUS && 1) + goto L1253; + goto ret0; + + L1253: + x2 = XEXP (x1, 0); + if (GET_MODE (x2) == HImode && GET_CODE (x2) == FFS && 1) + goto L1254; + goto ret0; + + L1254: + x3 = XEXP (x2, 0); + if (general_operand (x3, HImode)) + { + ro[1] = x3; + goto L1255; + } + goto ret0; + + L1255: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && XWINT (x2, 0) == -1 && pnum_clobbers != 0 && 1) + { + *pnum_clobbers = 1; + return 252; + } + goto ret0; + + L1258: + x1 = XEXP (x0, 1); + if (binary_387_op (x1, DFmode)) + { + ro[3] = x1; + goto L1264; + } + goto ret0; + + L1264: + x2 = XEXP (x1, 0); + switch (GET_MODE (x2)) + { + case DFmode: + switch (GET_CODE (x2)) + { + case FLOAT: + goto L1265; + case FLOAT_EXTEND: + goto L1271; + case SUBREG: + case REG: + case MEM: + if (nonimmediate_operand (x2, DFmode)) + { + ro[1] = x2; + goto L1260; + } + } + } + L1276: + if (general_operand (x2, DFmode)) + { + ro[1] = x2; + goto L1277; + } + goto ret0; + + L1265: + x3 = XEXP (x2, 0); + if (general_operand (x3, SImode)) + { + ro[1] = x3; + goto L1266; + } + goto ret0; + + L1266: + x2 = XEXP (x1, 1); + if (general_operand (x2, DFmode)) + { + ro[2] = x2; + if (TARGET_80387) + return 254; + } + goto ret0; + + L1271: + x3 = XEXP (x2, 0); + if (general_operand (x3, SFmode)) + { + ro[1] = x3; + goto L1272; + } + goto ret0; + + L1272: + x2 = XEXP (x1, 1); + if (general_operand (x2, DFmode)) + { + ro[2] = x2; + if (TARGET_80387) + return 255; + } + goto ret0; + + L1260: + x2 = XEXP (x1, 1); + if (nonimmediate_operand (x2, DFmode)) + { + ro[2] = x2; + if (TARGET_80387) + return 253; + } + x2 = XEXP (x1, 0); + goto L1276; + + L1277: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) != DFmode) + goto ret0; + switch (GET_CODE (x2)) + { + case FLOAT: + goto L1278; + case FLOAT_EXTEND: + goto L1284; + } + goto ret0; + + L1278: + x3 = XEXP (x2, 0); + if (general_operand (x3, SImode)) + { + ro[2] = x3; + if (TARGET_80387) + return 256; + } + goto ret0; + + L1284: + x3 = XEXP (x2, 0); + if (general_operand (x3, SFmode)) + { + ro[2] = x3; + if (TARGET_80387) + return 257; + } + goto ret0; + + L1287: + x1 = XEXP (x0, 1); + if (binary_387_op (x1, SFmode)) + { + ro[3] = x1; + goto L1293; + } + goto ret0; + + L1293: + x2 = XEXP (x1, 0); + switch (GET_MODE (x2)) + { + case SFmode: + if (GET_CODE (x2) == FLOAT && 1) + goto L1294; + if (nonimmediate_operand (x2, SFmode)) + { + ro[1] = x2; + goto L1289; + } + } + L1299: + if (general_operand (x2, SFmode)) + { + ro[1] = x2; + goto L1300; + } + goto ret0; + + L1294: + x3 = XEXP (x2, 0); + if (general_operand (x3, SImode)) + { + ro[1] = x3; + goto L1295; + } + goto ret0; + + L1295: + x2 = XEXP (x1, 1); + if (general_operand (x2, SFmode)) + { + ro[2] = x2; + if (TARGET_80387) + return 259; + } + goto ret0; + + L1289: + x2 = XEXP (x1, 1); + if (nonimmediate_operand (x2, SFmode)) + { + ro[2] = x2; + if (TARGET_80387) + return 258; + } + x2 = XEXP (x1, 0); + goto L1299; + + L1300: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) == SFmode && GET_CODE (x2) == FLOAT && 1) + goto L1301; + goto ret0; + + L1301: + x3 = XEXP (x2, 0); + if (general_operand (x3, SImode)) + { + ro[2] = x3; + if (TARGET_80387) + return 260; + } + goto ret0; + ret0: return -1; +} + +int +recog_4 (x0, insn, pnum_clobbers) + register rtx x0; + rtx insn; + int *pnum_clobbers; +{ + register rtx *ro = &recog_operand[0]; + register rtx x1, x2, x3, x4, x5, x6; + int tem; + + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 1); + switch (GET_MODE (x2)) + { + case SFmode: + if (register_operand (x2, SFmode)) + { + ro[0] = x2; + goto L13; + } + break; + case DFmode: + if (register_operand (x2, DFmode)) + { + ro[0] = x2; + goto L22; + } + } + L45: + if (VOIDmode_compare_op (x2, VOIDmode)) + { + ro[2] = x2; + goto L74; + } + L118: + if (GET_MODE (x2) == CCFPEQmode && GET_CODE (x2) == COMPARE && 1) + goto L119; + goto ret0; + + L13: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == CLOBBER && 1) + goto L14; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 1); + goto L45; + + L14: + x2 = XEXP (x1, 0); + if (scratch_operand (x2, HImode)) + { + ro[1] = x2; + if (TARGET_80387 && ! TARGET_IEEE_FP) + return 6; + } + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 1); + goto L45; + + L22: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == CLOBBER && 1) + goto L23; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 1); + goto L45; + + L23: + x2 = XEXP (x1, 0); + if (scratch_operand (x2, HImode)) + { + ro[1] = x2; + if (TARGET_80387 && ! TARGET_IEEE_FP) + return 8; + } + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 1); + goto L45; + + L74: + x3 = XEXP (x2, 0); + switch (GET_MODE (x3)) + { + case DFmode: + switch (GET_CODE (x3)) + { + case FLOAT: + goto L75; + case FLOAT_EXTEND: + goto L105; + case SUBREG: + case REG: + case MEM: + if (nonimmediate_operand (x3, DFmode)) + { + ro[0] = x3; + goto L47; + } + } + L59: + if (register_operand (x3, DFmode)) + { + ro[0] = x3; + goto L60; + } + break; + case SFmode: + if (GET_CODE (x3) == FLOAT && 1) + goto L161; + if (nonimmediate_operand (x3, SFmode)) + { + ro[0] = x3; + goto L133; + } + L145: + if (register_operand (x3, SFmode)) + { + ro[0] = x3; + goto L146; + } + } + goto L118; + + L75: + x4 = XEXP (x3, 0); + if (nonimmediate_operand (x4, SImode)) + { + ro[0] = x4; + goto L76; + } + goto L118; + + L76: + x3 = XEXP (x2, 1); + if (register_operand (x3, DFmode)) + { + ro[1] = x3; + goto L77; + } + goto L118; + + L77: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == CLOBBER && 1) + goto L78; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 1); + goto L118; + + L78: + x2 = XEXP (x1, 0); + if (scratch_operand (x2, HImode)) + { + ro[3] = x2; + if (TARGET_80387) + return 18; + } + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 1); + goto L118; + + L105: + x4 = XEXP (x3, 0); + if (nonimmediate_operand (x4, SFmode)) + { + ro[0] = x4; + goto L106; + } + goto L118; + + L106: + x3 = XEXP (x2, 1); + if (register_operand (x3, DFmode)) + { + ro[1] = x3; + goto L107; + } + goto L118; + + L107: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == CLOBBER && 1) + goto L108; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 1); + goto L118; + + L108: + x2 = XEXP (x1, 0); + if (scratch_operand (x2, HImode)) + { + ro[3] = x2; + if (TARGET_80387) + return 20; + } + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 1); + goto L118; + + L47: + x3 = XEXP (x2, 1); + if (nonimmediate_operand (x3, DFmode)) + { + ro[1] = x3; + goto L48; + } + x3 = XEXP (x2, 0); + goto L59; + + L48: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == CLOBBER && 1) + goto L49; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 1); + x3 = XEXP (x2, 0); + goto L59; + + L49: + x2 = XEXP (x1, 0); + if (scratch_operand (x2, HImode)) + { + ro[3] = x2; + if (TARGET_80387 + && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)) + return 16; + } + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 1); + x3 = XEXP (x2, 0); + goto L59; + + L60: + x3 = XEXP (x2, 1); + if (GET_MODE (x3) != DFmode) + { + goto L118; + } + switch (GET_CODE (x3)) + { + case FLOAT: + goto L61; + case FLOAT_EXTEND: + goto L91; + } + goto L118; + + L61: + x4 = XEXP (x3, 0); + if (nonimmediate_operand (x4, SImode)) + { + ro[1] = x4; + goto L62; + } + goto L118; + + L62: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == CLOBBER && 1) + goto L63; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 1); + goto L118; + + L63: + x2 = XEXP (x1, 0); + if (scratch_operand (x2, HImode)) + { + ro[3] = x2; + if (TARGET_80387) + return 17; + } + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 1); + goto L118; + + L91: + x4 = XEXP (x3, 0); + if (nonimmediate_operand (x4, SFmode)) + { + ro[1] = x4; + goto L92; + } + goto L118; + + L92: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == CLOBBER && 1) + goto L93; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 1); + goto L118; + + L93: + x2 = XEXP (x1, 0); + if (scratch_operand (x2, HImode)) + { + ro[3] = x2; + if (TARGET_80387) + return 19; + } + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 1); + goto L118; + + L161: + x4 = XEXP (x3, 0); + if (nonimmediate_operand (x4, SImode)) + { + ro[0] = x4; + goto L162; + } + goto L118; + + L162: + x3 = XEXP (x2, 1); + if (register_operand (x3, SFmode)) + { + ro[1] = x3; + goto L163; + } + goto L118; + + L163: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == CLOBBER && 1) + goto L164; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 1); + goto L118; + + L164: + x2 = XEXP (x1, 0); + if (scratch_operand (x2, HImode)) + { + ro[3] = x2; + if (TARGET_80387) + return 24; + } + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 1); + goto L118; + + L133: + x3 = XEXP (x2, 1); + if (nonimmediate_operand (x3, SFmode)) + { + ro[1] = x3; + goto L134; + } + x3 = XEXP (x2, 0); + goto L145; + + L134: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == CLOBBER && 1) + goto L135; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 1); + x3 = XEXP (x2, 0); + goto L145; + + L135: + x2 = XEXP (x1, 0); + if (scratch_operand (x2, HImode)) + { + ro[3] = x2; + if (TARGET_80387 + && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)) + return 22; + } + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 1); + x3 = XEXP (x2, 0); + goto L145; + + L146: + x3 = XEXP (x2, 1); + if (GET_MODE (x3) == SFmode && GET_CODE (x3) == FLOAT && 1) + goto L147; + goto L118; + + L147: + x4 = XEXP (x3, 0); + if (nonimmediate_operand (x4, SImode)) + { + ro[1] = x4; + goto L148; + } + goto L118; + + L148: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == CLOBBER && 1) + goto L149; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 1); + goto L118; + + L149: + x2 = XEXP (x1, 0); + if (scratch_operand (x2, HImode)) + { + ro[3] = x2; + if (TARGET_80387) + return 23; + } + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 1); + goto L118; + + L119: + x3 = XEXP (x2, 0); + switch (GET_MODE (x3)) + { + case DFmode: + if (register_operand (x3, DFmode)) + { + ro[0] = x3; + goto L120; + } + break; + case SFmode: + if (register_operand (x3, SFmode)) + { + ro[0] = x3; + goto L176; + } + } + goto ret0; + + L120: + x3 = XEXP (x2, 1); + if (register_operand (x3, DFmode)) + { + ro[1] = x3; + goto L121; + } + goto ret0; + + L121: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == CLOBBER && 1) + goto L122; + goto ret0; + + L122: + x2 = XEXP (x1, 0); + if (scratch_operand (x2, HImode)) + { + ro[2] = x2; + if (TARGET_80387) + return 21; + } + goto ret0; + + L176: + x3 = XEXP (x2, 1); + if (register_operand (x3, SFmode)) + { + ro[1] = x3; + goto L177; + } + goto ret0; + + L177: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == CLOBBER && 1) + goto L178; + goto ret0; + + L178: + x2 = XEXP (x1, 0); + if (scratch_operand (x2, HImode)) + { + ro[2] = x2; + if (TARGET_80387) + return 25; + } + goto ret0; + ret0: return -1; +} + +int +recog_5 (x0, insn, pnum_clobbers) + register rtx x0; + rtx insn; + int *pnum_clobbers; +{ + register rtx *ro = &recog_operand[0]; + register rtx x1, x2, x3, x4, x5, x6; + int tem; + + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + switch (GET_MODE (x2)) + { + case DFmode: + if (register_operand (x2, DFmode)) + { + ro[0] = x2; + goto L242; + } + break; + case SFmode: + if (nonimmediate_operand (x2, SFmode)) + { + ro[0] = x2; + goto L294; + } + break; + case SImode: + if (register_operand (x2, SImode)) + { + ro[0] = x2; + goto L497; + } + break; + case HImode: + if (register_operand (x2, HImode)) + { + ro[0] = x2; + goto L508; + } + break; + case DImode: + if (register_operand (x2, DImode)) + { + ro[0] = x2; + goto L684; + } + } + switch (GET_CODE (x2)) + { + case CC0: + goto L12; + case PC: + goto L1068; + } + L1125: + ro[0] = x2; + goto L1126; + L1228: + switch (GET_MODE (x2)) + { + case SImode: + if (register_operand (x2, SImode)) + { + ro[0] = x2; + goto L1229; + } + break; + case HImode: + if (register_operand (x2, HImode)) + { + ro[0] = x2; + goto L1244; + } + } + goto ret0; + + L242: + x2 = XEXP (x1, 1); + if (register_operand (x2, DFmode)) + { + ro[1] = x2; + goto L243; + } + x2 = XEXP (x1, 0); + goto L1125; + + L243: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == SET && 1) + goto L244; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1125; + + L244: + x2 = XEXP (x1, 0); + if (rtx_equal_p (x2, ro[1]) && 1) + goto L245; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1125; + + L245: + x2 = XEXP (x1, 1); + if (rtx_equal_p (x2, ro[0]) && 1) + return 48; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1125; + + L294: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) == SFmode && GET_CODE (x2) == FLOAT_TRUNCATE && 1) + goto L295; + x2 = XEXP (x1, 0); + goto L1125; + + L295: + x3 = XEXP (x2, 0); + if (register_operand (x3, DFmode)) + { + ro[1] = x3; + goto L296; + } + x2 = XEXP (x1, 0); + goto L1125; + + L296: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == CLOBBER && 1) + goto L297; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1125; + + L297: + x2 = XEXP (x1, 0); + if (memory_operand (x2, SFmode)) + { + ro[2] = x2; + if (TARGET_80387) + return 62; + } + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1125; + + L497: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) != SImode) + { + x2 = XEXP (x1, 0); + goto L1125; + } + switch (GET_CODE (x2)) + { + case DIV: + goto L498; + case UDIV: + goto L520; + } + x2 = XEXP (x1, 0); + goto L1125; + + L498: + x3 = XEXP (x2, 0); + if (register_operand (x3, SImode)) + { + ro[1] = x3; + goto L499; + } + x2 = XEXP (x1, 0); + goto L1125; + + L499: + x3 = XEXP (x2, 1); + if (general_operand (x3, SImode)) + { + ro[2] = x3; + goto L500; + } + x2 = XEXP (x1, 0); + goto L1125; + + L500: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == SET && 1) + goto L501; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1125; + + L501: + x2 = XEXP (x1, 0); + if (register_operand (x2, SImode)) + { + ro[3] = x2; + goto L502; + } + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1125; + + L502: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) == SImode && GET_CODE (x2) == MOD && 1) + goto L503; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1125; + + L503: + x3 = XEXP (x2, 0); + if (rtx_equal_p (x3, ro[1]) && 1) + goto L504; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1125; + + L504: + x3 = XEXP (x2, 1); + if (rtx_equal_p (x3, ro[2]) && 1) + return 105; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1125; + + L520: + x3 = XEXP (x2, 0); + if (register_operand (x3, SImode)) + { + ro[1] = x3; + goto L521; + } + x2 = XEXP (x1, 0); + goto L1125; + + L521: + x3 = XEXP (x2, 1); + if (general_operand (x3, SImode)) + { + ro[2] = x3; + goto L522; + } + x2 = XEXP (x1, 0); + goto L1125; + + L522: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == SET && 1) + goto L523; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1125; + + L523: + x2 = XEXP (x1, 0); + if (register_operand (x2, SImode)) + { + ro[3] = x2; + goto L524; + } + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1125; + + L524: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) == SImode && GET_CODE (x2) == UMOD && 1) + goto L525; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1125; + + L525: + x3 = XEXP (x2, 0); + if (rtx_equal_p (x3, ro[1]) && 1) + goto L526; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1125; + + L526: + x3 = XEXP (x2, 1); + if (rtx_equal_p (x3, ro[2]) && 1) + return 107; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1125; + + L508: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) != HImode) + { + x2 = XEXP (x1, 0); + goto L1125; + } + switch (GET_CODE (x2)) + { + case DIV: + goto L509; + case UDIV: + goto L531; + } + x2 = XEXP (x1, 0); + goto L1125; + + L509: + x3 = XEXP (x2, 0); + if (register_operand (x3, HImode)) + { + ro[1] = x3; + goto L510; + } + x2 = XEXP (x1, 0); + goto L1125; + + L510: + x3 = XEXP (x2, 1); + if (general_operand (x3, HImode)) + { + ro[2] = x3; + goto L511; + } + x2 = XEXP (x1, 0); + goto L1125; + + L511: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == SET && 1) + goto L512; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1125; + + L512: + x2 = XEXP (x1, 0); + if (register_operand (x2, HImode)) + { + ro[3] = x2; + goto L513; + } + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1125; + + L513: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) == HImode && GET_CODE (x2) == MOD && 1) + goto L514; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1125; + + L514: + x3 = XEXP (x2, 0); + if (rtx_equal_p (x3, ro[1]) && 1) + goto L515; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1125; + + L515: + x3 = XEXP (x2, 1); + if (rtx_equal_p (x3, ro[2]) && 1) + return 106; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1125; + + L531: + x3 = XEXP (x2, 0); + if (register_operand (x3, HImode)) + { + ro[1] = x3; + goto L532; + } + x2 = XEXP (x1, 0); + goto L1125; + + L532: + x3 = XEXP (x2, 1); + if (general_operand (x3, HImode)) + { + ro[2] = x3; + goto L533; + } + x2 = XEXP (x1, 0); + goto L1125; + + L533: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == SET && 1) + goto L534; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1125; + + L534: + x2 = XEXP (x1, 0); + if (register_operand (x2, HImode)) + { + ro[3] = x2; + goto L535; + } + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1125; + + L535: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) == HImode && GET_CODE (x2) == UMOD && 1) + goto L536; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1125; + + L536: + x3 = XEXP (x2, 0); + if (rtx_equal_p (x3, ro[1]) && 1) + goto L537; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1125; + + L537: + x3 = XEXP (x2, 1); + if (rtx_equal_p (x3, ro[2]) && 1) + return 108; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1125; + + L684: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) != DImode) + { + x2 = XEXP (x1, 0); + goto L1125; + } + switch (GET_CODE (x2)) + { + case ASHIFT: + goto L685; + case ASHIFTRT: + goto L713; + case LSHIFTRT: + goto L741; + } + x2 = XEXP (x1, 0); + goto L1125; + + L685: + x3 = XEXP (x2, 0); + if (register_operand (x3, DImode)) + { + ro[1] = x3; + goto L686; + } + x2 = XEXP (x1, 0); + goto L1125; + + L686: + x3 = XEXP (x2, 1); + if (register_operand (x3, QImode)) + { + ro[2] = x3; + goto L687; + } + x2 = XEXP (x1, 0); + goto L1125; + + L687: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == CLOBBER && 1) + goto L688; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1125; + + L688: + x2 = XEXP (x1, 0); + if (rtx_equal_p (x2, ro[2]) && 1) + return 142; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1125; + + L713: + x3 = XEXP (x2, 0); + if (register_operand (x3, DImode)) + { + ro[1] = x3; + goto L714; + } + x2 = XEXP (x1, 0); + goto L1125; + + L714: + x3 = XEXP (x2, 1); + if (register_operand (x3, QImode)) + { + ro[2] = x3; + goto L715; + } + x2 = XEXP (x1, 0); + goto L1125; + + L715: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == CLOBBER && 1) + goto L716; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1125; + + L716: + x2 = XEXP (x1, 0); + if (rtx_equal_p (x2, ro[2]) && 1) + return 148; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1125; + + L741: + x3 = XEXP (x2, 0); + if (register_operand (x3, DImode)) + { + ro[1] = x3; + goto L742; + } + x2 = XEXP (x1, 0); + goto L1125; + + L742: + x3 = XEXP (x2, 1); + if (register_operand (x3, QImode)) + { + ro[2] = x3; + goto L743; + } + x2 = XEXP (x1, 0); + goto L1125; + + L743: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == CLOBBER && 1) + goto L744; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1125; + + L744: + x2 = XEXP (x1, 0); + if (rtx_equal_p (x2, ro[2]) && 1) + return 154; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1125; + L12: + tem = recog_4 (x0, insn, pnum_clobbers); + if (tem >= 0) return tem; + x2 = XEXP (x1, 0); + goto L1125; + + L1068: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) == SImode && GET_CODE (x2) == MINUS && 1) + goto L1069; + if (general_operand (x2, SImode)) + { + ro[0] = x2; + goto L1094; + } + x2 = XEXP (x1, 0); + goto L1125; + + L1069: + x3 = XEXP (x2, 0); + if (GET_MODE (x3) == SImode && GET_CODE (x3) == REG && XINT (x3, 0) == 3 && 1) + goto L1070; + x2 = XEXP (x1, 0); + goto L1125; + + L1070: + x3 = XEXP (x2, 1); + if (GET_MODE (x3) == SImode && GET_CODE (x3) == MEM && 1) + goto L1071; + x2 = XEXP (x1, 0); + goto L1125; + + L1071: + x4 = XEXP (x3, 0); + if (GET_MODE (x4) == SImode && GET_CODE (x4) == PLUS && 1) + goto L1072; + x2 = XEXP (x1, 0); + goto L1125; + + L1072: + x5 = XEXP (x4, 0); + if (GET_MODE (x5) == SImode && GET_CODE (x5) == MULT && 1) + goto L1073; + x2 = XEXP (x1, 0); + goto L1125; + + L1073: + x6 = XEXP (x5, 0); + if (register_operand (x6, SImode)) + { + ro[0] = x6; + goto L1074; + } + x2 = XEXP (x1, 0); + goto L1125; + + L1074: + x6 = XEXP (x5, 1); + if (GET_CODE (x6) == CONST_INT && XWINT (x6, 0) == 4 && 1) + goto L1075; + x2 = XEXP (x1, 0); + goto L1125; + + L1075: + x5 = XEXP (x4, 1); + if (GET_CODE (x5) == LABEL_REF && 1) + goto L1076; + x2 = XEXP (x1, 0); + goto L1125; + + L1076: + x6 = XEXP (x5, 0); + ro[1] = x6; + goto L1077; + + L1077: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == CLOBBER && 1) + goto L1078; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1125; + + L1078: + x2 = XEXP (x1, 0); + if (scratch_operand (x2, SImode)) + { + ro[2] = x2; + return 223; + } + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1125; + + L1094: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == USE && 1) + goto L1095; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1125; + + L1095: + x2 = XEXP (x1, 0); + if (GET_CODE (x2) == LABEL_REF && 1) + goto L1096; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1125; + + L1096: + x3 = XEXP (x2, 0); + ro[1] = x3; + return 224; + + L1126: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CALL && 1) + goto L1138; + x2 = XEXP (x1, 0); + goto L1228; + + L1138: + x3 = XEXP (x2, 0); + if (GET_MODE (x3) == QImode && GET_CODE (x3) == MEM && 1) + goto L1139; + L1127: + if (call_insn_operand (x3, QImode)) + { + ro[1] = x3; + goto L1128; + } + x2 = XEXP (x1, 0); + goto L1228; + + L1139: + x4 = XEXP (x3, 0); + if (symbolic_operand (x4, SImode)) + { + ro[1] = x4; + goto L1140; + } + goto L1127; + + L1140: + x3 = XEXP (x2, 1); + if (general_operand (x3, SImode)) + { + ro[2] = x3; + goto L1141; + } + x3 = XEXP (x2, 0); + goto L1127; + + L1141: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == SET && 1) + goto L1142; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 1); + x3 = XEXP (x2, 0); + goto L1127; + + L1142: + x2 = XEXP (x1, 0); + if (GET_MODE (x2) == SImode && GET_CODE (x2) == REG && XINT (x2, 0) == 7 && 1) + goto L1143; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 1); + x3 = XEXP (x2, 0); + goto L1127; + + L1143: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) == SImode && GET_CODE (x2) == PLUS && 1) + goto L1144; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 1); + x3 = XEXP (x2, 0); + goto L1127; + + L1144: + x3 = XEXP (x2, 0); + if (GET_MODE (x3) == SImode && GET_CODE (x3) == REG && XINT (x3, 0) == 7 && 1) + goto L1145; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 1); + x3 = XEXP (x2, 0); + goto L1127; + + L1145: + x3 = XEXP (x2, 1); + if (immediate_operand (x3, SImode)) + { + ro[4] = x3; + if (!HALF_PIC_P ()) + return 233; + } + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 1); + x3 = XEXP (x2, 0); + goto L1127; + + L1128: + x3 = XEXP (x2, 1); + if (general_operand (x3, SImode)) + { + ro[2] = x3; + goto L1129; + } + x2 = XEXP (x1, 0); + goto L1228; + + L1129: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == SET && 1) + goto L1130; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1228; + + L1130: + x2 = XEXP (x1, 0); + if (GET_MODE (x2) == SImode && GET_CODE (x2) == REG && XINT (x2, 0) == 7 && 1) + goto L1131; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1228; + + L1131: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) == SImode && GET_CODE (x2) == PLUS && 1) + goto L1132; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1228; + + L1132: + x3 = XEXP (x2, 0); + if (GET_MODE (x3) == SImode && GET_CODE (x3) == REG && XINT (x3, 0) == 7 && 1) + goto L1133; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1228; + + L1133: + x3 = XEXP (x2, 1); + if (immediate_operand (x3, SImode)) + { + ro[4] = x3; + return 232; + } + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1228; + + L1229: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) != SImode) + goto ret0; + switch (GET_CODE (x2)) + { + case PLUS: + goto L1230; + case UNSPEC: + if (XINT (x2, 1) == 0 && XVECLEN (x2, 0) == 3 && 1) + goto L1306; + } + goto ret0; + + L1230: + x3 = XEXP (x2, 0); + if (GET_MODE (x3) == SImode && GET_CODE (x3) == FFS && 1) + goto L1231; + goto ret0; + + L1231: + x4 = XEXP (x3, 0); + if (general_operand (x4, SImode)) + { + ro[1] = x4; + goto L1232; + } + goto ret0; + + L1232: + x3 = XEXP (x2, 1); + if (GET_CODE (x3) == CONST_INT && XWINT (x3, 0) == -1 && 1) + goto L1233; + goto ret0; + + L1233: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == CLOBBER && 1) + goto L1234; + goto ret0; + + L1234: + x2 = XEXP (x1, 0); + if (scratch_operand (x2, SImode)) + { + ro[2] = x2; + return 250; + } + goto ret0; + + L1306: + x3 = XVECEXP (x2, 0, 0); + if (GET_MODE (x3) == BLKmode && GET_CODE (x3) == MEM && 1) + goto L1307; + goto ret0; + + L1307: + x4 = XEXP (x3, 0); + if (address_operand (x4, SImode)) + { + ro[1] = x4; + goto L1308; + } + goto ret0; + + L1308: + x3 = XVECEXP (x2, 0, 1); + if (register_operand (x3, QImode)) + { + ro[2] = x3; + goto L1309; + } + goto ret0; + + L1309: + x3 = XVECEXP (x2, 0, 2); + if (immediate_operand (x3, SImode)) + { + ro[3] = x3; + goto L1310; + } + goto ret0; + + L1310: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == CLOBBER && 1) + goto L1311; + goto ret0; + + L1311: + x2 = XEXP (x1, 0); + if (rtx_equal_p (x2, ro[1]) && 1) + return 262; + goto ret0; + + L1244: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) == HImode && GET_CODE (x2) == PLUS && 1) + goto L1245; + goto ret0; + + L1245: + x3 = XEXP (x2, 0); + if (GET_MODE (x3) == HImode && GET_CODE (x3) == FFS && 1) + goto L1246; + goto ret0; + + L1246: + x4 = XEXP (x3, 0); + if (general_operand (x4, HImode)) + { + ro[1] = x4; + goto L1247; + } + goto ret0; + + L1247: + x3 = XEXP (x2, 1); + if (GET_CODE (x3) == CONST_INT && XWINT (x3, 0) == -1 && 1) + goto L1248; + goto ret0; + + L1248: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == CLOBBER && 1) + goto L1249; + goto ret0; + + L1249: + x2 = XEXP (x1, 0); + if (scratch_operand (x2, HImode)) + { + ro[2] = x2; + return 252; + } + goto ret0; + ret0: return -1; +} + +int +recog (x0, insn, pnum_clobbers) + register rtx x0; + rtx insn; + int *pnum_clobbers; +{ + register rtx *ro = &recog_operand[0]; + register rtx x1, x2, x3, x4, x5, x6; + int tem; + + L1170: + switch (GET_CODE (x0)) + { + case UNSPEC: + if (GET_MODE (x0) == SImode && XINT (x0, 1) == 0 && XVECLEN (x0, 0) == 1 && 1) + goto L1171; + break; + case SET: + goto L200; + case PARALLEL: + if (XVECLEN (x0, 0) == 2 && 1) + goto L10; + if (XVECLEN (x0, 0) == 5 && 1) + goto L299; + if (XVECLEN (x0, 0) == 4 && 1) + goto L313; + if (XVECLEN (x0, 0) == 3 && 1) + goto L363; + if (XVECLEN (x0, 0) == 6 && 1) + goto L1175; + break; + case CALL: + goto L1117; + case RETURN: + if (simple_386_epilogue ()) + return 242; + break; + case CONST_INT: + if (XWINT (x0, 0) == 0 && 1) + return 243; + } + goto ret0; + + L1171: + x1 = XVECEXP (x0, 0, 0); + if (memory_operand (x1, SImode)) + { + ro[0] = x1; + return 241; + } + goto ret0; + L200: + return recog_3 (x0, insn, pnum_clobbers); + + L10: + x1 = XVECEXP (x0, 0, 0); + switch (GET_CODE (x1)) + { + case SET: + goto L241; + case CALL: + goto L1108; + } + goto ret0; + L241: + return recog_5 (x0, insn, pnum_clobbers); + + L1108: + x2 = XEXP (x1, 0); + if (GET_MODE (x2) == QImode && GET_CODE (x2) == MEM && 1) + goto L1109; + L1099: + if (call_insn_operand (x2, QImode)) + { + ro[0] = x2; + goto L1100; + } + goto ret0; + + L1109: + x3 = XEXP (x2, 0); + if (symbolic_operand (x3, SImode)) + { + ro[0] = x3; + goto L1110; + } + goto L1099; + + L1110: + x2 = XEXP (x1, 1); + if (general_operand (x2, SImode)) + { + ro[1] = x2; + goto L1111; + } + x2 = XEXP (x1, 0); + goto L1099; + + L1111: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == SET && 1) + goto L1112; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1099; + + L1112: + x2 = XEXP (x1, 0); + if (GET_MODE (x2) == SImode && GET_CODE (x2) == REG && XINT (x2, 0) == 7 && 1) + goto L1113; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1099; + + L1113: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) == SImode && GET_CODE (x2) == PLUS && 1) + goto L1114; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1099; + + L1114: + x3 = XEXP (x2, 0); + if (GET_MODE (x3) == SImode && GET_CODE (x3) == REG && XINT (x3, 0) == 7 && 1) + goto L1115; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1099; + + L1115: + x3 = XEXP (x2, 1); + if (immediate_operand (x3, SImode)) + { + ro[3] = x3; + if (!HALF_PIC_P ()) + return 227; + } + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1099; + + L1100: + x2 = XEXP (x1, 1); + if (general_operand (x2, SImode)) + { + ro[1] = x2; + goto L1101; + } + goto ret0; + + L1101: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == SET && 1) + goto L1102; + goto ret0; + + L1102: + x2 = XEXP (x1, 0); + if (GET_MODE (x2) == SImode && GET_CODE (x2) == REG && XINT (x2, 0) == 7 && 1) + goto L1103; + goto ret0; + + L1103: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) == SImode && GET_CODE (x2) == PLUS && 1) + goto L1104; + goto ret0; + + L1104: + x3 = XEXP (x2, 0); + if (GET_MODE (x3) == SImode && GET_CODE (x3) == REG && XINT (x3, 0) == 7 && 1) + goto L1105; + goto ret0; + + L1105: + x3 = XEXP (x2, 1); + if (immediate_operand (x3, SImode)) + { + ro[3] = x3; + return 226; + } + goto ret0; + + L299: + x1 = XVECEXP (x0, 0, 0); + if (GET_CODE (x1) == SET && 1) + goto L300; + goto ret0; + + L300: + x2 = XEXP (x1, 0); + if (GET_MODE (x2) == DImode && general_operand (x2, DImode)) + { + ro[0] = x2; + goto L301; + } + goto ret0; + + L301: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) == DImode && GET_CODE (x2) == FIX && 1) + goto L302; + goto ret0; + + L302: + x3 = XEXP (x2, 0); + if (GET_CODE (x3) != FIX) + goto ret0; + switch (GET_MODE (x3)) + { + case DFmode: + goto L303; + case SFmode: + goto L329; + } + goto ret0; + + L303: + x4 = XEXP (x3, 0); + if (register_operand (x4, DFmode)) + { + ro[1] = x4; + goto L304; + } + goto ret0; + + L304: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == CLOBBER && 1) + goto L305; + goto ret0; + + L305: + x2 = XEXP (x1, 0); + if (rtx_equal_p (x2, ro[1]) && 1) + goto L306; + goto ret0; + + L306: + x1 = XVECEXP (x0, 0, 2); + if (GET_CODE (x1) == CLOBBER && 1) + goto L307; + goto ret0; + + L307: + x2 = XEXP (x1, 0); + if (memory_operand (x2, SImode)) + { + ro[2] = x2; + goto L308; + } + goto ret0; + + L308: + x1 = XVECEXP (x0, 0, 3); + if (GET_CODE (x1) == CLOBBER && 1) + goto L309; + goto ret0; + + L309: + x2 = XEXP (x1, 0); + if (memory_operand (x2, SImode)) + { + ro[3] = x2; + goto L310; + } + goto ret0; + + L310: + x1 = XVECEXP (x0, 0, 4); + if (GET_CODE (x1) == CLOBBER && 1) + goto L311; + goto ret0; + + L311: + x2 = XEXP (x1, 0); + if (scratch_operand (x2, SImode)) + { + ro[4] = x2; + if (TARGET_80387) + return 67; + } + goto ret0; + + L329: + x4 = XEXP (x3, 0); + if (register_operand (x4, SFmode)) + { + ro[1] = x4; + goto L330; + } + goto ret0; + + L330: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == CLOBBER && 1) + goto L331; + goto ret0; + + L331: + x2 = XEXP (x1, 0); + if (rtx_equal_p (x2, ro[1]) && 1) + goto L332; + goto ret0; + + L332: + x1 = XVECEXP (x0, 0, 2); + if (GET_CODE (x1) == CLOBBER && 1) + goto L333; + goto ret0; + + L333: + x2 = XEXP (x1, 0); + if (memory_operand (x2, SImode)) + { + ro[2] = x2; + goto L334; + } + goto ret0; + + L334: + x1 = XVECEXP (x0, 0, 3); + if (GET_CODE (x1) == CLOBBER && 1) + goto L335; + goto ret0; + + L335: + x2 = XEXP (x1, 0); + if (memory_operand (x2, SImode)) + { + ro[3] = x2; + goto L336; + } + goto ret0; + + L336: + x1 = XVECEXP (x0, 0, 4); + if (GET_CODE (x1) == CLOBBER && 1) + goto L337; + goto ret0; + + L337: + x2 = XEXP (x1, 0); + if (scratch_operand (x2, SImode)) + { + ro[4] = x2; + if (TARGET_80387) + return 68; + } + goto ret0; + + L313: + x1 = XVECEXP (x0, 0, 0); + if (GET_CODE (x1) == SET && 1) + goto L314; + goto ret0; + + L314: + x2 = XEXP (x1, 0); + switch (GET_MODE (x2)) + { + case DImode: + if (general_operand (x2, DImode)) + { + ro[0] = x2; + goto L315; + } + break; + case SImode: + if (general_operand (x2, SImode)) + { + ro[0] = x2; + goto L353; + } + } + goto ret0; + + L315: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) == DImode && GET_CODE (x2) == FIX && 1) + goto L316; + goto ret0; + + L316: + x3 = XEXP (x2, 0); + if (GET_CODE (x3) != FIX) + goto ret0; + switch (GET_MODE (x3)) + { + case DFmode: + goto L317; + case SFmode: + goto L343; + } + goto ret0; + + L317: + x4 = XEXP (x3, 0); + if (register_operand (x4, DFmode)) + { + ro[1] = x4; + goto L318; + } + goto ret0; + + L318: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == CLOBBER && 1) + goto L319; + goto ret0; + + L319: + x2 = XEXP (x1, 0); + if (rtx_equal_p (x2, ro[1]) && 1) + goto L320; + goto ret0; + + L320: + x1 = XVECEXP (x0, 0, 2); + if (GET_CODE (x1) == CLOBBER && 1) + goto L321; + goto ret0; + + L321: + x2 = XEXP (x1, 0); + if (memory_operand (x2, SImode)) + { + ro[2] = x2; + goto L322; + } + goto ret0; + + L322: + x1 = XVECEXP (x0, 0, 3); + if (GET_CODE (x1) == CLOBBER && 1) + goto L323; + goto ret0; + + L323: + x2 = XEXP (x1, 0); + if (pnum_clobbers != 0 && memory_operand (x2, SImode)) + { + ro[3] = x2; + if (TARGET_80387) + { + *pnum_clobbers = 1; + return 67; + } + } + goto ret0; + + L343: + x4 = XEXP (x3, 0); + if (register_operand (x4, SFmode)) + { + ro[1] = x4; + goto L344; + } + goto ret0; + + L344: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == CLOBBER && 1) + goto L345; + goto ret0; + + L345: + x2 = XEXP (x1, 0); + if (rtx_equal_p (x2, ro[1]) && 1) + goto L346; + goto ret0; + + L346: + x1 = XVECEXP (x0, 0, 2); + if (GET_CODE (x1) == CLOBBER && 1) + goto L347; + goto ret0; + + L347: + x2 = XEXP (x1, 0); + if (memory_operand (x2, SImode)) + { + ro[2] = x2; + goto L348; + } + goto ret0; + + L348: + x1 = XVECEXP (x0, 0, 3); + if (GET_CODE (x1) == CLOBBER && 1) + goto L349; + goto ret0; + + L349: + x2 = XEXP (x1, 0); + if (pnum_clobbers != 0 && memory_operand (x2, SImode)) + { + ro[3] = x2; + if (TARGET_80387) + { + *pnum_clobbers = 1; + return 68; + } + } + goto ret0; + + L353: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) == SImode && GET_CODE (x2) == FIX && 1) + goto L354; + goto ret0; + + L354: + x3 = XEXP (x2, 0); + if (GET_CODE (x3) != FIX) + goto ret0; + switch (GET_MODE (x3)) + { + case DFmode: + goto L355; + case SFmode: + goto L377; + } + goto ret0; + + L355: + x4 = XEXP (x3, 0); + if (register_operand (x4, DFmode)) + { + ro[1] = x4; + goto L356; + } + goto ret0; + + L356: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == CLOBBER && 1) + goto L357; + goto ret0; + + L357: + x2 = XEXP (x1, 0); + if (memory_operand (x2, SImode)) + { + ro[2] = x2; + goto L358; + } + goto ret0; + + L358: + x1 = XVECEXP (x0, 0, 2); + if (GET_CODE (x1) == CLOBBER && 1) + goto L359; + goto ret0; + + L359: + x2 = XEXP (x1, 0); + if (memory_operand (x2, SImode)) + { + ro[3] = x2; + goto L360; + } + goto ret0; + + L360: + x1 = XVECEXP (x0, 0, 3); + if (GET_CODE (x1) == CLOBBER && 1) + goto L361; + goto ret0; + + L361: + x2 = XEXP (x1, 0); + if (scratch_operand (x2, SImode)) + { + ro[4] = x2; + if (TARGET_80387) + return 71; + } + goto ret0; + + L377: + x4 = XEXP (x3, 0); + if (register_operand (x4, SFmode)) + { + ro[1] = x4; + goto L378; + } + goto ret0; + + L378: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == CLOBBER && 1) + goto L379; + goto ret0; + + L379: + x2 = XEXP (x1, 0); + if (memory_operand (x2, SImode)) + { + ro[2] = x2; + goto L380; + } + goto ret0; + + L380: + x1 = XVECEXP (x0, 0, 2); + if (GET_CODE (x1) == CLOBBER && 1) + goto L381; + goto ret0; + + L381: + x2 = XEXP (x1, 0); + if (memory_operand (x2, SImode)) + { + ro[3] = x2; + goto L382; + } + goto ret0; + + L382: + x1 = XVECEXP (x0, 0, 3); + if (GET_CODE (x1) == CLOBBER && 1) + goto L383; + goto ret0; + + L383: + x2 = XEXP (x1, 0); + if (scratch_operand (x2, SImode)) + { + ro[4] = x2; + if (TARGET_80387) + return 72; + } + goto ret0; + + L363: + x1 = XVECEXP (x0, 0, 0); + switch (GET_CODE (x1)) + { + case SET: + goto L364; + case CALL: + goto L1165; + } + goto ret0; + + L364: + x2 = XEXP (x1, 0); + if (GET_MODE (x2) == SImode && general_operand (x2, SImode)) + { + ro[0] = x2; + goto L365; + } + goto ret0; + + L365: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) == SImode && GET_CODE (x2) == FIX && 1) + goto L366; + goto ret0; + + L366: + x3 = XEXP (x2, 0); + if (GET_CODE (x3) != FIX) + goto ret0; + switch (GET_MODE (x3)) + { + case DFmode: + goto L367; + case SFmode: + goto L389; + } + goto ret0; + + L367: + x4 = XEXP (x3, 0); + if (register_operand (x4, DFmode)) + { + ro[1] = x4; + goto L368; + } + goto ret0; + + L368: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == CLOBBER && 1) + goto L369; + goto ret0; + + L369: + x2 = XEXP (x1, 0); + if (memory_operand (x2, SImode)) + { + ro[2] = x2; + goto L370; + } + goto ret0; + + L370: + x1 = XVECEXP (x0, 0, 2); + if (GET_CODE (x1) == CLOBBER && 1) + goto L371; + goto ret0; + + L371: + x2 = XEXP (x1, 0); + if (pnum_clobbers != 0 && memory_operand (x2, SImode)) + { + ro[3] = x2; + if (TARGET_80387) + { + *pnum_clobbers = 1; + return 71; + } + } + goto ret0; + + L389: + x4 = XEXP (x3, 0); + if (register_operand (x4, SFmode)) + { + ro[1] = x4; + goto L390; + } + goto ret0; + + L390: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == CLOBBER && 1) + goto L391; + goto ret0; + + L391: + x2 = XEXP (x1, 0); + if (memory_operand (x2, SImode)) + { + ro[2] = x2; + goto L392; + } + goto ret0; + + L392: + x1 = XVECEXP (x0, 0, 2); + if (GET_CODE (x1) == CLOBBER && 1) + goto L393; + goto ret0; + + L393: + x2 = XEXP (x1, 0); + if (pnum_clobbers != 0 && memory_operand (x2, SImode)) + { + ro[3] = x2; + if (TARGET_80387) + { + *pnum_clobbers = 1; + return 72; + } + } + goto ret0; + + L1165: + x2 = XEXP (x1, 0); + if (GET_MODE (x2) == QImode && GET_CODE (x2) == MEM && 1) + goto L1166; + L1159: + if (call_insn_operand (x2, QImode)) + { + ro[0] = x2; + goto L1160; + } + goto ret0; + + L1166: + x3 = XEXP (x2, 0); + if (symbolic_operand (x3, SImode)) + { + ro[0] = x3; + goto L1167; + } + goto L1159; + + L1167: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && XWINT (x2, 0) == 0 && 1) + goto L1168; + x2 = XEXP (x1, 0); + goto L1159; + + L1168: + x1 = XVECEXP (x0, 0, 1); + if (memory_operand (x1, DImode)) + { + ro[1] = x1; + goto L1169; + } + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1159; + + L1169: + x1 = XVECEXP (x0, 0, 2); + ro[2] = x1; + if (!HALF_PIC_P ()) + return 239; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L1159; + + L1160: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && XWINT (x2, 0) == 0 && 1) + goto L1161; + goto ret0; + + L1161: + x1 = XVECEXP (x0, 0, 1); + if (memory_operand (x1, DImode)) + { + ro[1] = x1; + goto L1162; + } + goto ret0; + + L1162: + x1 = XVECEXP (x0, 0, 2); + ro[2] = x1; + return 238; + + L1175: + x1 = XVECEXP (x0, 0, 0); + if (GET_CODE (x1) == SET && 1) + goto L1176; + goto ret0; + + L1176: + x2 = XEXP (x1, 0); + switch (GET_MODE (x2)) + { + case BLKmode: + if (GET_CODE (x2) == MEM && 1) + goto L1177; + break; + case SImode: + if (general_operand (x2, SImode)) + { + ro[0] = x2; + goto L1193; + } + } + if (GET_CODE (x2) == CC0 && 1) + goto L1211; + goto ret0; + + L1177: + x3 = XEXP (x2, 0); + if (address_operand (x3, SImode)) + { + ro[0] = x3; + goto L1178; + } + goto ret0; + + L1178: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) == BLKmode && GET_CODE (x2) == MEM && 1) + goto L1179; + goto ret0; + + L1179: + x3 = XEXP (x2, 0); + if (address_operand (x3, SImode)) + { + ro[1] = x3; + goto L1180; + } + goto ret0; + + L1180: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == USE && 1) + goto L1181; + goto ret0; + + L1181: + x2 = XEXP (x1, 0); + if (GET_CODE (x2) == CONST_INT && 1) + { + ro[2] = x2; + goto L1182; + } + goto ret0; + + L1182: + x1 = XVECEXP (x0, 0, 2); + if (GET_CODE (x1) == USE && 1) + goto L1183; + goto ret0; + + L1183: + x2 = XEXP (x1, 0); + if (immediate_operand (x2, SImode)) + { + ro[3] = x2; + goto L1184; + } + goto ret0; + + L1184: + x1 = XVECEXP (x0, 0, 3); + if (GET_CODE (x1) == CLOBBER && 1) + goto L1185; + goto ret0; + + L1185: + x2 = XEXP (x1, 0); + if (scratch_operand (x2, SImode)) + { + ro[4] = x2; + goto L1186; + } + goto ret0; + + L1186: + x1 = XVECEXP (x0, 0, 4); + if (GET_CODE (x1) == CLOBBER && 1) + goto L1187; + goto ret0; + + L1187: + x2 = XEXP (x1, 0); + if (rtx_equal_p (x2, ro[0]) && 1) + goto L1188; + goto ret0; + + L1188: + x1 = XVECEXP (x0, 0, 5); + if (GET_CODE (x1) == CLOBBER && 1) + goto L1189; + goto ret0; + + L1189: + x2 = XEXP (x1, 0); + if (rtx_equal_p (x2, ro[1]) && 1) + return 245; + goto ret0; + + L1193: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) == SImode && GET_CODE (x2) == COMPARE && 1) + goto L1194; + goto ret0; + + L1194: + x3 = XEXP (x2, 0); + if (GET_MODE (x3) == BLKmode && GET_CODE (x3) == MEM && 1) + goto L1195; + goto ret0; + + L1195: + x4 = XEXP (x3, 0); + if (address_operand (x4, SImode)) + { + ro[1] = x4; + goto L1196; + } + goto ret0; + + L1196: + x3 = XEXP (x2, 1); + if (GET_MODE (x3) == BLKmode && GET_CODE (x3) == MEM && 1) + goto L1197; + goto ret0; + + L1197: + x4 = XEXP (x3, 0); + if (address_operand (x4, SImode)) + { + ro[2] = x4; + goto L1198; + } + goto ret0; + + L1198: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == USE && 1) + goto L1199; + goto ret0; + + L1199: + x2 = XEXP (x1, 0); + if (register_operand (x2, SImode)) + { + ro[3] = x2; + goto L1200; + } + goto ret0; + + L1200: + x1 = XVECEXP (x0, 0, 2); + if (GET_CODE (x1) == USE && 1) + goto L1201; + goto ret0; + + L1201: + x2 = XEXP (x1, 0); + if (immediate_operand (x2, SImode)) + { + ro[4] = x2; + goto L1202; + } + goto ret0; + + L1202: + x1 = XVECEXP (x0, 0, 3); + if (GET_CODE (x1) == CLOBBER && 1) + goto L1203; + goto ret0; + + L1203: + x2 = XEXP (x1, 0); + if (rtx_equal_p (x2, ro[1]) && 1) + goto L1204; + goto ret0; + + L1204: + x1 = XVECEXP (x0, 0, 4); + if (GET_CODE (x1) == CLOBBER && 1) + goto L1205; + goto ret0; + + L1205: + x2 = XEXP (x1, 0); + if (rtx_equal_p (x2, ro[2]) && 1) + goto L1206; + goto ret0; + + L1206: + x1 = XVECEXP (x0, 0, 5); + if (GET_CODE (x1) == CLOBBER && 1) + goto L1207; + goto ret0; + + L1207: + x2 = XEXP (x1, 0); + if (rtx_equal_p (x2, ro[3]) && 1) + return 247; + goto ret0; + + L1211: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) == SImode && GET_CODE (x2) == COMPARE && 1) + goto L1212; + goto ret0; + + L1212: + x3 = XEXP (x2, 0); + if (GET_MODE (x3) == BLKmode && GET_CODE (x3) == MEM && 1) + goto L1213; + goto ret0; + + L1213: + x4 = XEXP (x3, 0); + if (address_operand (x4, SImode)) + { + ro[0] = x4; + goto L1214; + } + goto ret0; + + L1214: + x3 = XEXP (x2, 1); + if (GET_MODE (x3) == BLKmode && GET_CODE (x3) == MEM && 1) + goto L1215; + goto ret0; + + L1215: + x4 = XEXP (x3, 0); + if (address_operand (x4, SImode)) + { + ro[1] = x4; + goto L1216; + } + goto ret0; + + L1216: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == USE && 1) + goto L1217; + goto ret0; + + L1217: + x2 = XEXP (x1, 0); + if (register_operand (x2, SImode)) + { + ro[2] = x2; + goto L1218; + } + goto ret0; + + L1218: + x1 = XVECEXP (x0, 0, 2); + if (GET_CODE (x1) == USE && 1) + goto L1219; + goto ret0; + + L1219: + x2 = XEXP (x1, 0); + if (immediate_operand (x2, SImode)) + { + ro[3] = x2; + goto L1220; + } + goto ret0; + + L1220: + x1 = XVECEXP (x0, 0, 3); + if (GET_CODE (x1) == CLOBBER && 1) + goto L1221; + goto ret0; + + L1221: + x2 = XEXP (x1, 0); + if (rtx_equal_p (x2, ro[0]) && 1) + goto L1222; + goto ret0; + + L1222: + x1 = XVECEXP (x0, 0, 4); + if (GET_CODE (x1) == CLOBBER && 1) + goto L1223; + goto ret0; + + L1223: + x2 = XEXP (x1, 0); + if (rtx_equal_p (x2, ro[1]) && 1) + goto L1224; + goto ret0; + + L1224: + x1 = XVECEXP (x0, 0, 5); + if (GET_CODE (x1) == CLOBBER && 1) + goto L1225; + goto ret0; + + L1225: + x2 = XEXP (x1, 0); + if (rtx_equal_p (x2, ro[2]) && 1) + return 248; + goto ret0; + + L1117: + x1 = XEXP (x0, 0); + if (call_insn_operand (x1, QImode)) + { + ro[0] = x1; + goto L1118; + } + L1120: + if (GET_MODE (x1) == QImode && GET_CODE (x1) == MEM && 1) + goto L1121; + goto ret0; + + L1118: + x1 = XEXP (x0, 1); + if (general_operand (x1, SImode)) + { + ro[1] = x1; + return 229; + } + x1 = XEXP (x0, 0); + goto L1120; + + L1121: + x2 = XEXP (x1, 0); + if (symbolic_operand (x2, SImode)) + { + ro[0] = x2; + goto L1122; + } + goto ret0; + + L1122: + x1 = XEXP (x0, 1); + if (general_operand (x1, SImode)) + { + ro[1] = x1; + if (!HALF_PIC_P ()) + return 230; + } + goto ret0; + ret0: return -1; +} + +rtx +split_insns (x0, insn) + register rtx x0; + rtx insn; +{ + register rtx *ro = &recog_operand[0]; + register rtx x1, x2, x3, x4, x5, x6; + rtx tem; + + goto ret0; + ret0: return 0; +} + diff --git a/gnu/usr.bin/gcc2/i386/perform.h b/gnu/usr.bin/gcc2/i386/perform.h new file mode 100644 index 00000000000..c1a417071ca --- /dev/null +++ b/gnu/usr.bin/gcc2/i386/perform.h @@ -0,0 +1,93 @@ +/* Definitions for AT&T assembler syntax for the Intel 80386. + Copyright (C) 1988 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + +/* Defines to be able to build libgcc.a with GCC. */ + +/* It might seem that these are not important, since gcc 2 will never + call libgcc for these functions. But programs might be linked with + code compiled by gcc 1, and then these will be used. */ + +/* The arg names used to be a and b, but `a' appears inside strings + and that confuses non-ANSI cpp. */ + +#define perform_udivsi3(arg0,arg1) \ +{ \ + register int dx asm("dx"); \ + register int ax asm("ax"); \ + \ + dx = 0; \ + ax = arg0; \ + asm ("divl %3" : "=a" (ax), "=d" (dx) : "a" (ax), "g" (arg1), "d" (dx)); \ + return ax; \ +} + +#define perform_divsi3(arg0,arg1) \ +{ \ + register int dx asm("dx"); \ + register int ax asm("ax"); \ + \ + ax = arg0; \ + asm ("cltd\n\tidivl %3" : "=a" (ax), "=d" (dx) : "a" (ax), "g" (arg1)); \ + return ax; \ +} + +#define perform_umodsi3(arg0,arg1) \ +{ \ + register int dx asm("dx"); \ + register int ax asm("ax"); \ + \ + dx = 0; \ + ax = arg0; \ + asm ("divl %3" : "=a" (ax), "=d" (dx) : "a" (ax), "g" (arg1), "d" (dx)); \ + return dx; \ +} + +#define perform_modsi3(arg0,arg1) \ +{ \ + register int dx asm("dx"); \ + register int ax asm("ax"); \ + \ + ax = arg0; \ + asm ("cltd\n\tidivl %3" : "=a" (ax), "=d" (dx) : "a" (ax), "g" (arg1)); \ + return dx; \ +} + +#define perform_fixdfsi(arg0) \ +{ \ + auto unsigned short ostatus; \ + auto unsigned short nstatus; \ + auto int ret; \ + auto double tmp; \ + \ + &ostatus; /* guarantee these land in memory */ \ + &nstatus; \ + &ret; \ + &tmp; \ + \ + asm volatile ("fnstcw %0" : "=m" (ostatus)); \ + nstatus = ostatus | 0x0c00; \ + asm volatile ("fldcw %0" : /* no outputs */ : "m" (nstatus)); \ + tmp = arg0; \ + asm volatile ("fldl %0" : /* no outputs */ : "m" (tmp)); \ + asm volatile ("fistpl %0" : "=m" (ret)); \ + asm volatile ("fldcw %0" : /* no outputs */ : "m" (ostatus)); \ + \ + return ret; \ +} + diff --git a/gnu/usr.bin/gcc2/i386/tconfig.h b/gnu/usr.bin/gcc2/i386/tconfig.h new file mode 100644 index 00000000000..eb90681006f --- /dev/null +++ b/gnu/usr.bin/gcc2/i386/tconfig.h @@ -0,0 +1,48 @@ +/* Configuration for GNU C-compiler for Intel 80386. + Copyright (C) 1988 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + +#ifndef i386 +#define i386 +#endif + +/* #defines that need visibility everywhere. */ +#define FALSE 0 +#define TRUE 1 + +/* This describes the machine the compiler is hosted on. */ +#define HOST_BITS_PER_CHAR 8 +#define HOST_BITS_PER_SHORT 16 +#define HOST_BITS_PER_INT 32 +#define HOST_BITS_PER_LONG 32 +#define HOST_BITS_PER_LONGLONG 64 + +/* Arguments to use with `exit'. */ +#define SUCCESS_EXIT_CODE 0 +#define FATAL_EXIT_CODE 33 + +/* If compiled with GNU C, use the built-in alloca */ +#ifdef __GNUC__ +#undef alloca +#define alloca __builtin_alloca +#endif + +/* target machine dependencies. + tm.h is a symbolic link to the actual target specific file. */ + +#include "tm.h" diff --git a/gnu/usr.bin/gcc2/i386/tm.h b/gnu/usr.bin/gcc2/i386/tm.h new file mode 100644 index 00000000000..f7fbac12425 --- /dev/null +++ b/gnu/usr.bin/gcc2/i386/tm.h @@ -0,0 +1,81 @@ +/* Configuration for an i386 running 386BSD as the target machine. */ + +/* This is tested by i386gas.h. */ +#define YES_UNDERSCORES + +#include "i386/gstabs.h" + +/* Get perform_* macros to build libgcc.a. */ +#include "i386/perform.h" + +#undef CPP_PREDEFINES +#define CPP_PREDEFINES "-Dunix -Di386 -D____386BSD____ -D__386BSD__ -DBSD_NET2" + +/* Like the default, except no -lg. */ +#define LIB_SPEC "%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p}" + +#undef SIZE_TYPE +#define SIZE_TYPE "unsigned int" + +#undef PTRDIFF_TYPE +#define PTRDIFF_TYPE "int" + +#undef WCHAR_TYPE +#define WCHAR_TYPE "short unsigned int" + +#define WCHAR_UNSIGNED 1 + +#undef WCHAR_TYPE_SIZE +#define WCHAR_TYPE_SIZE 16 + +/* 386BSD does have atexit. */ + +#define HAVE_ATEXIT + +/* Redefine this to use %eax instead of %edx. */ +#undef FUNCTION_PROFILER +#define FUNCTION_PROFILER(FILE, LABELNO) \ +{ \ + if (flag_pic) \ + { \ + fprintf (FILE, "\tleal %sP%d@GOTOFF(%%ebx),%%eax\n", \ + LPREFIX, (LABELNO)); \ + fprintf (FILE, "\tcall *mcount@GOT(%%ebx)\n"); \ + } \ + else \ + { \ + fprintf (FILE, "\tmovl $%sP%d,%%eax\n", LPREFIX, (LABELNO)); \ + fprintf (FILE, "\tcall mcount\n"); \ + } \ +} + +/* There are conflicting reports about whether this system uses + a different assembler syntax. wilson@cygnus.com says # is right. */ +#undef COMMENT_BEGIN +#define COMMENT_BEGIN "#" + +#undef ASM_APP_ON +#define ASM_APP_ON "#APP\n" + +#undef ASM_APP_OFF +#define ASM_APP_OFF "#NO_APP\n" + +/* The following macros are stolen from i386v4.h */ +/* These have to be defined to get PIC code correct */ + +/* This is how to output an element of a case-vector that is relative. + This is only used for PIC code. See comments by the `casesi' insn in + i386.md for an explanation of the expression this outputs. */ + +#undef ASM_OUTPUT_ADDR_DIFF_ELT +#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \ + fprintf (FILE, "\t.long _GLOBAL_OFFSET_TABLE_+[.-%s%d]\n", LPREFIX, VALUE) + +/* Indicate that jump tables go in the text section. This is + necessary when compiling PIC code. */ + +#define JUMP_TABLES_IN_TEXT_SECTION + +/* Don't default to pcc-struct-return, because gcc is the only compiler, and + we want to retain compatibility with older gcc versions. */ +#define DEFAULT_PCC_STRUCT_RETURN 0 diff --git a/gnu/usr.bin/gcc2/i386/unix.h b/gnu/usr.bin/gcc2/i386/unix.h new file mode 100644 index 00000000000..7209176d191 --- /dev/null +++ b/gnu/usr.bin/gcc2/i386/unix.h @@ -0,0 +1,145 @@ +/* Definitions for Unix assembler syntax for the Intel 80386. + Copyright (C) 1988 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + +/* This file defines the aspects of assembler syntax + that are the same for all the i386 Unix systems + (though they may differ in non-Unix systems). */ + +/* Define some concatenation macros to concatenate an opcode + and one, two or three operands. In other assembler syntaxes + they may alter the order of ther operands. */ + +/* Note that the other files fail to use these + in some of the places where they should. */ + +#ifdef __STDC__ +#define AS2(a,b,c) #a " " #b "," #c +#define AS3(a,b,c,d) #a " " #b "," #c "," #d +#define AS1(a,b) #a " " #b +#else +#define AS1(a,b) "a b" +#define AS2(a,b,c) "a b,c" +#define AS3(a,b,c,d) "a b,c,d" +#endif + +/* Define macro used to output shift-double opcodes when the shift + count is in %cl. Some assemblers require %cl as an argument; + some don't. This macro controls what to do: by default, don't + print %cl. */ +#define AS3_SHIFT_DOUBLE(a,b,c,d) AS2 (a,c,d) + +/* Output the size-letter for an opcode. + CODE is the letter used in an operand spec (L, B, W, S or Q). + CH is the corresponding lower case letter + (except if CODE is `Q' then CH is `l', unless GAS_MNEMONICS). */ +#define PUT_OP_SIZE(CODE,CH,FILE) putc (CH,(FILE)) + +/* Opcode suffix for fullword insn. */ +#define L_SIZE "l" + +/* Prefix for register names in this syntax. */ +#define RP "%" + +/* Prefix for immediate operands in this syntax. */ +#define IP "$" + +/* Indirect call instructions should use `*'. */ +#define USE_STAR 1 + +/* Prefix for a memory-operand X. */ +#define PRINT_PTR(X, FILE) + +/* Delimiters that surround base reg and index reg. */ +#define ADDR_BEG(FILE) putc('(', (FILE)) +#define ADDR_END(FILE) putc(')', (FILE)) + +/* Print an index register (whose rtx is IREG). */ +#define PRINT_IREG(FILE,IREG) \ + do \ + { fputs (",", (FILE)); PRINT_REG ((IREG), 0, (FILE)); } \ + while (0) + +/* Print an index scale factor SCALE. */ +#define PRINT_SCALE(FILE,SCALE) \ + if ((SCALE) != 1) fprintf ((FILE), ",%d", (SCALE)) + +/* Print a base/index combination. + BREG is the base reg rtx, IREG is the index reg rtx, + and SCALE is the index scale factor (an integer). */ + +#define PRINT_B_I_S(BREG,IREG,SCALE,FILE) \ + { ADDR_BEG (FILE); \ + if (BREG) PRINT_REG ((BREG), 0, (FILE)); \ + if ((IREG) != 0) \ + { PRINT_IREG ((FILE), (IREG)); \ + PRINT_SCALE ((FILE), (SCALE)); } \ + ADDR_END (FILE); } + +/* Define the syntax of pseudo-ops, labels and comments. */ + +/* String containing the assembler's comment-starter. */ + +#define ASM_COMMENT_START "/" +#define COMMENT_BEGIN "/" + +/* Output to assembler file text saying following lines + may contain character constants, extra white space, comments, etc. */ + +#define ASM_APP_ON "/APP\n" + +/* Output to assembler file text saying following lines + no longer contain unusual constructs. */ + +#define ASM_APP_OFF "/NO_APP\n" + +/* Output before read-only data. */ + +#define TEXT_SECTION_ASM_OP ".text" + +/* Output before writable (initialized) data. */ + +#define DATA_SECTION_ASM_OP ".data" + +/* Output before writable (uninitialized) data. */ + +#define BSS_SECTION_ASM_OP ".bss" + +/* This is how to output a command to make the user-level label named NAME + defined for reference from other files. */ + +#define ASM_GLOBALIZE_LABEL(FILE,NAME) \ + (fputs (".globl ", FILE), assemble_name (FILE, NAME), fputs ("\n", FILE)) + +/* By default, target has a 80387, uses IEEE compatible arithmetic, + and returns float values in the 387, ie, + (TARGET_80387 | TARGET_IEEE_FP | TARGET_FLOAT_RETURNS_IN_80387) */ + +#define TARGET_DEFAULT 0301 + +/* Floating-point return values come in the FP register. */ + +#define VALUE_REGNO(MODE) \ + (GET_MODE_CLASS (MODE) == MODE_FLOAT \ + && TARGET_FLOAT_RETURNS_IN_80387 ? FIRST_FLOAT_REG : 0) + +/* 1 if N is a possible register number for a function value. */ + +#define FUNCTION_VALUE_REGNO_P(N) \ + ((N) == 0 || ((N)== FIRST_FLOAT_REG && TARGET_FLOAT_RETURNS_IN_80387)) + diff --git a/gnu/usr.bin/gcc2/libgcc/Makefile b/gnu/usr.bin/gcc2/libgcc/Makefile index 95e3f8897ba..a20b464b7d9 100644 --- a/gnu/usr.bin/gcc2/libgcc/Makefile +++ b/gnu/usr.bin/gcc2/libgcc/Makefile @@ -1,6 +1,6 @@ LIB= gcc CC= cc -CFLAGS= -I../common +CFLAGS= -I../common -I$(.CURDIR)/../$(MACHINE) SRCS= _mulsi3.c _udivsi3.c _divsi3.c _umodsi3.c _modsi3.c \ _lshrsi3.c _lshlsi3.c _ashrsi3.c _ashlsi3.c \ |
