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authorandvar <andvar@NetBSD.org>2021-11-01 21:28:01 +0000
committerandvar <andvar@NetBSD.org>2021-11-01 21:28:01 +0000
commitee4bc26f46b1caa589a3a282912d1aae8e5d9ba2 (patch)
tree6f0ca47652bd45f362b4318ae773a6f3ad7e57eb /sys/arch/mips/include
parent662a6dfd6a3188acbdbc98437a016c62962dbb73 (diff)
fix typos, mainly in words minimum and maximum, but also few others.
Diffstat (limited to 'sys/arch/mips/include')
-rw-r--r--sys/arch/mips/include/cpuregs.h8
1 files changed, 4 insertions, 4 deletions
diff --git a/sys/arch/mips/include/cpuregs.h b/sys/arch/mips/include/cpuregs.h
index 0344cae9034..294be82742e 100644
--- a/sys/arch/mips/include/cpuregs.h
+++ b/sys/arch/mips/include/cpuregs.h
@@ -1,4 +1,4 @@
-/* $NetBSD: cpuregs.h,v 1.112 2021/08/09 21:13:05 andvar Exp $ */
+/* $NetBSD: cpuregs.h,v 1.113 2021/11/01 21:28:02 andvar Exp $ */
/*
* Copyright (c) 2009 Miodrag Vallat.
@@ -695,7 +695,7 @@
(MIPS_BREAK_SOVER_VAL << MIPS_BREAK_VAL_SHIFT))
/*
- * Mininum and maximum cache sizes.
+ * Minimum and maximum cache sizes.
*/
#define MIPS_MIN_CACHE_SIZE (16 * 1024)
#define MIPS_MAX_CACHE_SIZE (256 * 1024)
@@ -712,7 +712,7 @@
*/
#define MIPS_FCSR_RM __BITS(1,0)
#define MIPS_FCSR_RM_RN 0 /* round to nearest */
-#define MIPS_FCSR_RM_RZ 1 /* round toward zerO */
+#define MIPS_FCSR_RM_RZ 1 /* round towards zero */
#define MIPS_FCSR_RM_RP 2 /* round towards +infinity */
#define MIPS_FCSR_RM_RM 3 /* round towards -infinity */
#define MIPS_FCSR_FLAGS __BITS(6,2)
@@ -1034,7 +1034,7 @@
#define MIPS_BCM3302 0x90 /* MIPS 4KEc_R2-like? ISA 32 Rel 2 */
/*
- * Alchemy (company ID 3) use the processor ID field to donote the CPU core
+ * Alchemy (company ID 3) use the processor ID field to denote the CPU core
* revision and the company options field do donate the SOC chip type.
*/
/* CPU processor revision IDs */