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authortsutsui <tsutsui@NetBSD.org>2008-01-08 16:15:04 +0000
committertsutsui <tsutsui@NetBSD.org>2008-01-08 16:15:04 +0000
commit03b0d74e1eccf62edffcd497ee26484dd74151d2 (patch)
treef056e049aef6954274496c25a513e6aba74d1cbc /sys/arch
parent808b08ff6f46f1490fceb4a8899c36504f12f2dc (diff)
Set proper mask values for ipl_sr_bits[] and
use C99 initializer to avoid confusion. Tested on gxemul.
Diffstat (limited to 'sys/arch')
-rw-r--r--sys/arch/evbmips/malta/malta_intr.c35
1 files changed, 18 insertions, 17 deletions
diff --git a/sys/arch/evbmips/malta/malta_intr.c b/sys/arch/evbmips/malta/malta_intr.c
index 2ebcd484b1c..f67bd1f3955 100644
--- a/sys/arch/evbmips/malta/malta_intr.c
+++ b/sys/arch/evbmips/malta/malta_intr.c
@@ -1,4 +1,4 @@
-/* $NetBSD: malta_intr.c,v 1.16 2008/01/08 14:28:35 dogcow Exp $ */
+/* $NetBSD: malta_intr.c,v 1.17 2008/01/08 16:15:04 tsutsui Exp $ */
/*
* Copyright 2001, 2002 Wasabi Systems, Inc.
@@ -40,7 +40,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: malta_intr.c,v 1.16 2008/01/08 14:28:35 dogcow Exp $");
+__KERNEL_RCSID(0, "$NetBSD: malta_intr.c,v 1.17 2008/01/08 16:15:04 tsutsui Exp $");
#include <sys/param.h>
#include <sys/device.h>
@@ -64,21 +64,22 @@ __KERNEL_RCSID(0, "$NetBSD: malta_intr.c,v 1.16 2008/01/08 14:28:35 dogcow Exp $
* given hardware interrupt priority level.
*/
const uint32_t ipl_sr_bits[_IPL_N] = {
- 0, /* 0: IPL_NONE */
-
- MIPS_SOFT_INT_MASK_0, /* 1: IPL_VM */
-
- MIPS_SOFT_INT_MASK_0|
- MIPS_SOFT_INT_MASK_1, /* 3: IPL_SCHED */
-
- MIPS_SOFT_INT_MASK_0|
- MIPS_SOFT_INT_MASK_1|
- MIPS_INT_MASK_0|
- MIPS_INT_MASK_1|
- MIPS_INT_MASK_2|
- MIPS_INT_MASK_3|
- MIPS_INT_MASK_4|
- MIPS_INT_MASK_5, /* 8: IPL_HIGH */
+ [IPL_NONE] = 0,
+ [IPL_SOFTCLOCK] =
+ MIPS_SOFT_INT_MASK_0,
+ [IPL_SOFTNET] =
+ MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1,
+ [IPL_VM] =
+ MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1 |
+ MIPS_INT_MASK_0,
+ [IPL_SCHED] =
+ MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1 |
+ MIPS_INT_MASK_0 |
+ MIPS_INT_MASK_1 |
+ MIPS_INT_MASK_2 |
+ MIPS_INT_MASK_3 |
+ MIPS_INT_MASK_4 |
+ MIPS_INT_MASK_5,
};
/*