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authorrearnsha <rearnsha@NetBSD.org>2001-10-18 17:06:14 +0000
committerrearnsha <rearnsha@NetBSD.org>2001-10-18 17:06:14 +0000
commitb5a8c6922adbbc531832c8f06638cf7079707e89 (patch)
treed9ad87652d5c68fcaabb996b245357132797387e /sys/dev/DEVNAMES
parent7de86d9ccd38f18cc4e11ec19d7e80104181a999 (diff)
On processors that support both write-through and write-back cacheing
(eg ARM920), the mode in which the processor operates is governed by the use of both the PT_C and PT_B bits: PT_C=1,PT_B=1 -> Write-back PT_C=1,PT_B=0 -> Write-through To support this define pte_cache_mode (initialized to PT_C|PT_B) and use that when enabling cacheing for a page.
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