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authordrochner <drochner@NetBSD.org>1999-09-19 14:45:47 +0000
committerdrochner <drochner@NetBSD.org>1999-09-19 14:45:47 +0000
commitfa13e8eb92b56e71ae483f930387b69028a32691 (patch)
tree5922df71be6e747e6b47673ddbdfd1d3696e51b1 /sys/dev/dec
parentf9d2e41bb7e0297e8bdcc99bd137183d35100dbb (diff)
set odd parity for the serial line
(done by directly setting zilog chip control bits -- there should be a zs_set_frame() or so in z8530sc.c) fixes PR port-alpha/8423 by Konrad Schroder <perseant@hhhh.org>
Diffstat (limited to 'sys/dev/dec')
-rw-r--r--sys/dev/dec/zsms.c9
1 files changed, 7 insertions, 2 deletions
diff --git a/sys/dev/dec/zsms.c b/sys/dev/dec/zsms.c
index 3a11a8f402c..79eed90bc42 100644
--- a/sys/dev/dec/zsms.c
+++ b/sys/dev/dec/zsms.c
@@ -1,4 +1,4 @@
-/* $NetBSD: zsms.c,v 1.3 1999/02/03 20:22:28 mycroft Exp $ */
+/* $NetBSD: zsms.c,v 1.4 1999/09/19 14:45:47 drochner Exp $ */
/*
* Copyright (c) 1992, 1993
@@ -165,10 +165,15 @@ zsms_attach(parent, self, aux)
s = splzs();
/* May need reset... */
zs_write_reg(cs, 9, ZSWR9_A_RESET);
- /* These are OK as set by zscc: WR3, WR4, WR5 */
+ /* These are OK as set by zscc: WR3, WR5 */
/* We don't care about status or tx interrupts. */
cs->cs_preg[1] = ZSWR1_RIE;
(void) zs_set_speed(cs, ZSMS_BPS);
+
+ /* mouse wants odd parity */
+ cs->cs_preg[4] |= ZSWR4_PARENB;
+ /* cs->cs_preg[4] &= ~ZSWR4_EVENP; (no-op) */
+
zs_loadchannelregs(cs);
splx(s);