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authorskrll <skrll@NetBSD.org>2019-12-30 15:54:55 +0000
committerskrll <skrll@NetBSD.org>2019-12-30 15:54:55 +0000
commitf81e72a96656aec23e6f0a14555221f549ee74cf (patch)
tree3e0783d1b4e73bee8f05e8880850b05d8abd95ef /sys/dev/dm/dm_dev.c
parentd04aafb62dd66134baf28adb5d8e424f6c20bdcd (diff)
Flush the cache and disable TTBR0 translations once we're done with
them in cpu_kernel_vm_init The Cortex A72s in RPI4 need the cache flush for some reason.
Diffstat (limited to 'sys/dev/dm/dm_dev.c')
0 files changed, 0 insertions, 0 deletions