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authorthorpej <thorpej@NetBSD.org>1999-12-12 17:46:36 +0000
committerthorpej <thorpej@NetBSD.org>1999-12-12 17:46:36 +0000
commit014cd3fcc1dcb4d46481eec995dd932c3f587727 (patch)
tree05d6a9f7825c4ae8348a4cd800baefd12ac187d5 /sys/dev/ic
parent78a5012f77c3b7788756f6e6a069cdd3e70e5241 (diff)
Take a stab at making this work on big-endian systems.
Diffstat (limited to 'sys/dev/ic')
-rw-r--r--sys/dev/ic/i82557.c75
-rw-r--r--sys/dev/ic/i82557reg.h91
-rw-r--r--sys/dev/ic/i82557var.h16
3 files changed, 99 insertions, 83 deletions
diff --git a/sys/dev/ic/i82557.c b/sys/dev/ic/i82557.c
index ccfddb8e194..6f10c3ea174 100644
--- a/sys/dev/ic/i82557.c
+++ b/sys/dev/ic/i82557.c
@@ -1,4 +1,4 @@
-/* $NetBSD: i82557.c,v 1.14 1999/12/04 02:02:30 sommerfeld Exp $ */
+/* $NetBSD: i82557.c,v 1.15 1999/12/12 17:46:36 thorpej Exp $ */
/*-
* Copyright (c) 1997, 1998, 1999 The NetBSD Foundation, Inc.
@@ -86,6 +86,8 @@
#include <sys/errno.h>
#include <sys/device.h>
+#include <machine/endian.h>
+
#include <vm/vm.h> /* for PAGE_SIZE */
#if NRND > 0
@@ -757,9 +759,9 @@ fxp_start(ifp)
/* Initialize the fraglist. */
for (seg = 0; seg < dmamap->dm_nsegs; seg++) {
tbd->tbd_d[seg].tb_addr =
- dmamap->dm_segs[seg].ds_addr;
+ htole32(dmamap->dm_segs[seg].ds_addr);
tbd->tbd_d[seg].tb_size =
- dmamap->dm_segs[seg].ds_len;
+ htole32(dmamap->dm_segs[seg].ds_len);
}
FXP_CDTBDSYNC(sc, nexttx, BUS_DMASYNC_PREWRITE);
@@ -776,9 +778,10 @@ fxp_start(ifp)
/*
* Initialize the transmit descriptor.
*/
+ /* BIG_ENDIAN: no need to swap to store 0 */
txd->cb_status = 0;
txd->cb_command =
- FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF;
+ htole16(FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF);
txd->tx_threshold = tx_threshold;
txd->tbd_number = dmamap->dm_nsegs;
@@ -817,7 +820,7 @@ fxp_start(ifp)
* has been transmitted.
*/
FXP_CDTX(sc, sc->sc_txlast)->cb_command |=
- FXP_CB_COMMAND_I | FXP_CB_COMMAND_S;
+ htole16(FXP_CB_COMMAND_I | FXP_CB_COMMAND_S);
FXP_CDTXSYNC(sc, sc->sc_txlast,
BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
@@ -827,7 +830,7 @@ fxp_start(ifp)
*/
FXP_CDTXSYNC(sc, lasttx,
BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
- FXP_CDTX(sc, lasttx)->cb_command &= ~FXP_CB_COMMAND_S;
+ FXP_CDTX(sc, lasttx)->cb_command &= htole16(~FXP_CB_COMMAND_S);
FXP_CDTXSYNC(sc, lasttx,
BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
@@ -858,7 +861,7 @@ fxp_intr(arg)
struct fxp_rfa *rfa;
struct ether_header *eh;
int i, claimed = 0;
- u_int16_t len;
+ u_int16_t len, rxstat, txstat;
u_int8_t statack;
/*
@@ -896,7 +899,9 @@ fxp_intr(arg)
FXP_RFASYNC(sc, m,
BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
- if ((rfa->rfa_status & FXP_RFA_STATUS_C) == 0) {
+ rxstat = le16toh(rfa->rfa_status);
+
+ if ((rxstat & FXP_RFA_STATUS_C) == 0) {
/*
* We have processed all of the
* receive buffers.
@@ -908,7 +913,8 @@ fxp_intr(arg)
FXP_RXBUFSYNC(sc, m, BUS_DMASYNC_POSTREAD);
- len = rfa->actual_size & (m->m_ext.ext_size - 1);
+ len = le16toh(rfa->actual_size) &
+ (m->m_ext.ext_size - 1);
if (len < sizeof(struct ether_header)) {
/*
@@ -959,8 +965,7 @@ fxp_intr(arg)
bpf_mtap(ifp->if_bpf, m);
if ((ifp->if_flags & IFF_PROMISC) != 0 &&
- (rfa->rfa_status &
- FXP_RFA_STATUS_IAMATCH) != 0 &&
+ (rxstat & FXP_RFA_STATUS_IAMATCH) != 0 &&
(eh->ether_dhost[0] & 1) == 0) {
m_freem(m);
goto rcvloop;
@@ -997,7 +1002,9 @@ fxp_intr(arg)
FXP_CDTXSYNC(sc, i,
BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
- if ((txd->cb_status & FXP_CB_STATUS_C) == 0)
+ txstat = le16toh(txd->cb_status);
+
+ if ((txstat & FXP_CB_STATUS_C) == 0)
break;
FXP_CDTBDSYNC(sc, i, BUS_DMASYNC_POSTWRITE);
@@ -1063,25 +1070,25 @@ fxp_tick(arg)
s = splnet();
- ifp->if_opackets += sp->tx_good;
- ifp->if_collisions += sp->tx_total_collisions;
+ ifp->if_opackets += le32toh(sp->tx_good);
+ ifp->if_collisions += le32toh(sp->tx_total_collisions);
if (sp->rx_good) {
- ifp->if_ipackets += sp->rx_good;
+ ifp->if_ipackets += le32toh(sp->rx_good);
sc->sc_rxidle = 0;
} else {
sc->sc_rxidle++;
}
ifp->if_ierrors +=
- sp->rx_crc_errors +
- sp->rx_alignment_errors +
- sp->rx_rnr_errors +
- sp->rx_overrun_errors;
+ le32toh(sp->rx_crc_errors) +
+ le32toh(sp->rx_alignment_errors) +
+ le32toh(sp->rx_rnr_errors) +
+ le32toh(sp->rx_overrun_errors);
/*
* If any transmit underruns occured, bump up the transmit
* threshold by another 512 bytes (64 * 8).
*/
if (sp->tx_underruns) {
- ifp->if_oerrors += sp->tx_underruns;
+ ifp->if_oerrors += le32toh(sp->tx_underruns);
if (tx_threshold < 192)
tx_threshold += 64;
}
@@ -1118,6 +1125,7 @@ fxp_tick(arg)
* Just zero our copy of the stats and wait for the
* next timer event to update them.
*/
+ /* BIG_ENDIAN: no swap required to store 0 */
sp->tx_good = 0;
sp->tx_underruns = 0;
sp->tx_total_collisions = 0;
@@ -1297,9 +1305,12 @@ fxp_init(sc)
*/
memcpy(cbp, fxp_cb_config_template, sizeof(fxp_cb_config_template));
+ /* BIG_ENDIAN: no need to swap to store 0 */
cbp->cb_status = 0;
- cbp->cb_command = FXP_CB_COMMAND_CONFIG | FXP_CB_COMMAND_EL;
- cbp->link_addr = -1; /* (no) next command */
+ cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG |
+ FXP_CB_COMMAND_EL);
+ /* BIG_ENDIAN: no need to swap to store 0xffffffff */
+ cbp->link_addr = 0xffffffff; /* (no) next command */
cbp->byte_count = 22; /* (22) bytes to config */
cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */
cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */
@@ -1349,9 +1360,11 @@ fxp_init(sc)
* Initialize the station address.
*/
cb_ias = &sc->sc_control_data->fcd_iascb;
+ /* BIG_ENDIAN: no need to swap to store 0 */
cb_ias->cb_status = 0;
- cb_ias->cb_command = FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL;
- cb_ias->link_addr = -1;
+ cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL);
+ /* BIG_ENDIAN: no need to swap to store 0xffffffff */
+ cb_ias->link_addr = 0xffffffff;
memcpy((void *)cb_ias->macaddr, LLADDR(ifp->if_sadl), ETHER_ADDR_LEN);
FXP_CDIASSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
@@ -1376,9 +1389,10 @@ fxp_init(sc)
for (i = 0; i < FXP_NTXCB; i++) {
txd = FXP_CDTX(sc, i);
memset(txd, 0, sizeof(struct fxp_cb_tx));
- txd->cb_command = FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S;
- txd->tbd_array_addr = FXP_CDTBDADDR(sc, i);
- txd->link_addr = FXP_CDTXADDR(sc, FXP_NEXTTX(i));
+ txd->cb_command =
+ htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S);
+ txd->tbd_array_addr = htole32(FXP_CDTBDADDR(sc, i));
+ txd->link_addr = htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(i)));
FXP_CDTXSYNC(sc, i, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
}
sc->sc_txpending = 0;
@@ -1788,10 +1802,11 @@ fxp_mc_setup(sc)
ETHER_NEXT_MULTI(step, enm);
}
+ /* BIG_ENDIAN: no need to swap to store 0 */
mcsp->cb_status = 0;
- mcsp->cb_command = FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL;
- mcsp->link_addr = FXP_CDTXADDR(sc, FXP_NEXTTX(sc->sc_txlast));
- mcsp->mc_cnt = nmcasts * ETHER_ADDR_LEN;
+ mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL);
+ mcsp->link_addr = htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(sc->sc_txlast)));
+ mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN);
FXP_CDMCSSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
diff --git a/sys/dev/ic/i82557reg.h b/sys/dev/ic/i82557reg.h
index 35ac28e886f..b0e2690b902 100644
--- a/sys/dev/ic/i82557reg.h
+++ b/sys/dev/ic/i82557reg.h
@@ -1,4 +1,4 @@
-/* $NetBSD: i82557reg.h,v 1.2 1999/08/03 22:43:28 thorpej Exp $ */
+/* $NetBSD: i82557reg.h,v 1.3 1999/12/12 17:46:36 thorpej Exp $ */
/*-
* Copyright (c) 1998, 1999 The NetBSD Foundation, Inc.
@@ -156,6 +156,18 @@ struct fxp_cb_ias {
volatile u_int8_t macaddr[6];
};
+#if BYTE_ORDER == LITTLE_ENDIAN
+#define __FXP_BITFIELD2(a, b) a, b
+#define __FXP_BITFIELD3(a, b, c) a, b, c
+#define __FXP_BITFIELD4(a, b, c, d) a, b, c, d
+#define __FXP_BITFIELD6(a, b, c, d, e, f) a, b, c, d, e, f
+#else
+#define __FXP_BITFIELD2(a, b) b, a
+#define __FXP_BITFIELD3(a, b, c) c, b, a
+#define __FXP_BITFIELD4(a, b, c, d) d, c, b, a
+#define __FXP_BITFIELD6(a, b, c, d, e, f) f, e, d, c, b, a
+#endif
+
/*
* Configure command.
*/
@@ -163,59 +175,44 @@ struct fxp_cb_config {
volatile u_int16_t cb_status;
volatile u_int16_t cb_command;
volatile u_int32_t link_addr;
- volatile u_int8_t byte_count:6,
- :2;
- volatile u_int8_t rx_fifo_limit:4,
- tx_fifo_limit:3,
- :1;
+ volatile u_int8_t __FXP_BITFIELD2(byte_count:6, :2);
+ volatile u_int8_t __FXP_BITFIELD3(rx_fifo_limit:4,
+ tx_fifo_limit:3,
+ :1);
volatile u_int8_t adaptive_ifs;
volatile u_int8_t :8;
- volatile u_int8_t rx_dma_bytecount:7,
- :1;
- volatile u_int8_t tx_dma_bytecount:7,
- dma_bce:1;
- volatile u_int8_t late_scb:1,
- :1,
- tno_int:1,
- ci_int:1,
- :3,
- save_bf:1;
- volatile u_int8_t disc_short_rx:1,
- underrun_retry:2,
- :5;
- volatile u_int8_t mediatype:1,
- :7;
+ volatile u_int8_t __FXP_BITFIELD2(rx_dma_bytecount:7, :1);
+ volatile u_int8_t __FXP_BITFIELD2(tx_dma_bytecount:7,
+ dma_bce:1);
+ volatile u_int8_t __FXP_BITFIELD6(late_scb:1, :1,
+ tno_int:1,
+ ci_int:1, :3,
+ save_bf:1);
+ volatile u_int8_t __FXP_BITFIELD3(disc_short_rx:1,
+ underrun_retry:2, :5);
+ volatile u_int8_t __FXP_BITFIELD2(mediatype:1, :7);
volatile u_int8_t :8;
- volatile u_int8_t :3,
- nsai:1,
- preamble_length:2,
- loopback:2;
- volatile u_int8_t linear_priority:3,
- :5;
- volatile u_int8_t linear_pri_mode:1,
- :3,
- interfrm_spacing:4;
+ volatile u_int8_t __FXP_BITFIELD4(:3,
+ nsai:1,
+ preamble_length:2,
+ loopback:2);
+ volatile u_int8_t __FXP_BITFIELD2(linear_priority:3, :5);
+ volatile u_int8_t __FXP_BITFIELD3(linear_pri_mode:1, :3,
+ interfrm_spacing:4);
volatile u_int8_t :8;
volatile u_int8_t :8;
- volatile u_int8_t promiscuous:1,
- bcast_disable:1,
- :5,
- crscdt:1;
+ volatile u_int8_t __FXP_BITFIELD4(promiscuous:1,
+ bcast_disable:1, :5,
+ crscdt:1);
volatile u_int8_t :8;
volatile u_int8_t :8;
- volatile u_int8_t stripping:1,
- padding:1,
- rcv_crc_xfer:1,
- :5;
- volatile u_int8_t :6,
- force_fdx:1,
- fdx_pin_en:1;
- volatile u_int8_t :6,
- multi_ia:1,
- :1;
- volatile u_int8_t :3,
- mc_all:1,
- :4;
+ volatile u_int8_t __FXP_BITFIELD4(stripping:1,
+ padding:1,
+ rcv_crc_xfer:1, :5);
+ volatile u_int8_t __FXP_BITFIELD3(:6, force_fdx:1,
+ fdx_pin_en:1);
+ volatile u_int8_t __FXP_BITFIELD3(:6, multi_ia:1, :1);
+ volatile u_int8_t __FXP_BITFIELD3(:3, mc_all:1, :4);
};
/*
diff --git a/sys/dev/ic/i82557var.h b/sys/dev/ic/i82557var.h
index 3bcd83c7df1..5f0f40ec24a 100644
--- a/sys/dev/ic/i82557var.h
+++ b/sys/dev/ic/i82557var.h
@@ -1,4 +1,4 @@
-/* $NetBSD: i82557var.h,v 1.8 1999/10/30 16:07:58 sommerfeld Exp $ */
+/* $NetBSD: i82557var.h,v 1.9 1999/12/12 17:46:36 thorpej Exp $ */
/*-
* Copyright (c) 1997, 1998, 1999 The NetBSD Foundation, Inc.
@@ -269,13 +269,16 @@ do { \
RFA_ALIGNMENT_FUDGE; \
\
__rfa = FXP_MTORFA((m)); \
- __rfa->size = FXP_RXBUFSIZE((m)); \
+ __rfa->size = htole16(FXP_RXBUFSIZE((m))); \
+ /* BIG_ENDIAN: no need to swap to store 0 */ \
__rfa->rfa_status = 0; \
- __rfa->rfa_control = FXP_RFA_CONTROL_EL; \
+ __rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL); \
+ /* BIG_ENDIAN: no need to swap to store 0 */ \
__rfa->actual_size = 0; \
\
/* NOTE: the RFA is misaligned, so we must copy. */ \
- __v = -1; \
+ /* BIG_ENDIAN: no need to swap to store 0xffffffff */ \
+ __v = 0xffffffff; \
memcpy((void *)&__rfa->link_addr, &__v, sizeof(__v)); \
memcpy((void *)&__rfa->rbd_addr, &__v, sizeof(__v)); \
\
@@ -286,12 +289,13 @@ do { \
\
if ((__p_m = (sc)->sc_rxq.ifq_tail) != NULL) { \
__p_rfa = FXP_MTORFA(__p_m); \
- __v = __rxmap->dm_segs[0].ds_addr + RFA_ALIGNMENT_FUDGE;\
+ __v = htole32(__rxmap->dm_segs[0].ds_addr + \
+ RFA_ALIGNMENT_FUDGE); \
FXP_RFASYNC((sc), __p_m, \
BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); \
memcpy((void *)&__p_rfa->link_addr, &__v, \
sizeof(__v)); \
- __p_rfa->rfa_control &= ~FXP_RFA_CONTROL_EL; \
+ __p_rfa->rfa_control &= htole16(~FXP_RFA_CONTROL_EL); \
FXP_RFASYNC((sc), __p_m, \
BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \
} \