diff options
| author | heas <heas@NetBSD.org> | 2005-02-18 01:39:18 +0000 |
|---|---|---|
| committer | heas <heas@NetBSD.org> | 2005-02-18 01:39:18 +0000 |
| commit | 981782a1d91dc2bef5200c64fba698eab054eac3 (patch) | |
| tree | 3b88886dd14683ecdce17afe88f3d4867fe61e41 /sys/dev/ic | |
| parent | f5a6c8bf2f8444a08b4dc7ff4b771b2e9e64aa3f (diff) | |
Adjust/add a few comments, add a few bitmask_snprintf formats, and add
register definitions for hardware checksums and the PCS (the fiber interface
version of a MII).
Diffstat (limited to 'sys/dev/ic')
| -rw-r--r-- | sys/dev/ic/gemreg.h | 71 |
1 files changed, 58 insertions, 13 deletions
diff --git a/sys/dev/ic/gemreg.h b/sys/dev/ic/gemreg.h index f7f6777281b..da5663a201a 100644 --- a/sys/dev/ic/gemreg.h +++ b/sys/dev/ic/gemreg.h @@ -1,4 +1,4 @@ -/* $NetBSD: gemreg.h,v 1.6 2004/10/17 21:49:08 heas Exp $ */ +/* $NetBSD: gemreg.h,v 1.7 2005/02/18 01:39:18 heas Exp $ */ /* * @@ -87,8 +87,8 @@ #define GEM_INTR_BITS "\177\020" \ "b\0INTME\0b\1TXEMPTY\0b\2TXDONE\0" \ "b\4RXDONE\0b\5RXNOBUF\0b\6RX_TAG_ERR\0" \ - "b\15PCS\0b\16TXMAC\0b\17RXMAC\0" \ - "b\20MAC_CONTROL\0b\21MIF\0b\22BERR\0\0" \ + "b\xdPCS\0b\xeTXMAC\0b\xfRXMAC\0" \ + "b\x10MAC_CONTROL\0b\x11MIF\0b\x12IBERR\0\0" @@ -96,6 +96,7 @@ #define GEM_ERROR_STAT_BADACK 0x000000001 /* No ACK64# */ #define GEM_ERROR_STAT_DTRTO 0x000000002 /* Delayed xaction timeout */ #define GEM_ERROR_STAT_OTHERS 0x000000004 +#define GEM_ERROR_BITS "\177\020b\0ACKBAD\0b\1DTRTO\0b\2OTHER\0\0" /* GEM_BIF_CONFIG register bits */ @@ -103,6 +104,8 @@ #define GEM_BIF_CONFIG_HOST_64 0x000000002 /* 64-bit host */ #define GEM_BIF_CONFIG_B64D_DIS 0x000000004 /* no 64-bit data cycle */ #define GEM_BIF_CONFIG_M66EN 0x000000008 +#define GEM_BIF_CONFIG_BITS "\177\020b\0SLOWCLK\0b\1HOST64\0" \ + "b\2B64DIS\0b\3M66EN\0\0" /* GEM_RESET register bits -- TX and RX self clear when complete. */ @@ -190,7 +193,7 @@ #define GEM_RX_CONFIG_RXRING_SZ 0x0000001e /* RX ring size */ #define GEM_RX_CONFIG_BATCH_DIS 0x00000020 /* desc batching disable */ #define GEM_RX_CONFIG_FBOFF 0x00001c00 /* first byte offset */ -#define GEM_RX_CONFIG_CXM_START 0x000fe000 /* checksum start offset */ +#define GEM_RX_CONFIG_CXM_START 0x000fe000 /* cksum start offset bytes */ #define GEM_RX_CONFIG_FIFO_THRS 0x07000000 /* fifo threshold size */ #define GEM_THRSH_64 0 @@ -234,7 +237,7 @@ #define GEM_MAC_IPG0 0x6040 /* inter packet gap 0 */ #define GEM_MAC_IPG1 0x6044 /* inter packet gap 1 */ #define GEM_MAC_IPG2 0x6048 /* inter packet gap 2 */ -#define GEM_MAC_SLOT_TIME 0x604c +#define GEM_MAC_SLOT_TIME 0x604c /* slot time, bits 0-7 */ #define GEM_MAC_MAC_MIN_FRAME 0x6050 #define GEM_MAC_MAC_MAX_FRAME 0x6054 #define GEM_MAC_PREAMBLE_LEN 0x6058 @@ -322,6 +325,7 @@ #define GEM_MAC_PAUSE 0x00000002 /* enter pause state */ #define GEM_MAC_RESUME 0x00000004 /* exit pause state */ #define GEM_MAC_PAUSE_TIME 0xffff0000 +#define GEM_MAC_STATUS_BITS "\177\020b\0PAUSED\0b\1PAUSE\0b\2RESUME\0\0" /* GEM_MAC_XIF_CONFIG register bits */ #define GEM_MAC_XIF_TX_MII_ENA 0x00000001 /* Enable XIF output drivers */ @@ -331,6 +335,14 @@ #define GEM_MAC_XIF_MII_BUF_ENA 0x00000010 /* Enable MII recv buffers */ #define GEM_MAC_XIF_LINK_LED 0x00000020 /* force link LED active */ #define GEM_MAC_XIF_FDPLX_LED 0x00000040 /* force FDPLX LED active */ +#define GEM_MAC_XIF_BITS "\177\020b\0TXMIIENA\0b\1MIILOOP\0b\2NOECHO" \ + "\0b\3GMII\0b\4MIIBUFENA\0b\5LINKLED\0" \ + "b\6FDLED\0\0" + +/* GEM_MAC_SLOT_TIME register bits */ +#define GEM_MAC_SLOT_INT 0x40 +#define GEM_MAC_SLOT_EXT 0x200 /* external phy */ +#define GEM_MAC_SLOT_BITS "\177\020b\6INTSLOT\0b\x9SLOTEXT\0\0" /* GEM_MAC_TX_CONFIG register bits */ #define GEM_MAC_TX_ENABLE 0x00000001 /* TX enable */ @@ -344,6 +356,11 @@ #define GEM_MAC_TX_NO_FCS 0x00000100 /* no FCS will be generated */ #define GEM_MAC_TX_CARR_EXTEND 0x00000200 /* Ena TX Carrier Extension */ /* Carrier Extension is required for half duplex Gbps operation */ +#define GEM_MAC_TX_CONFIG_BITS "\177\020" \ + "b\0TXENA\0b\1IGNCAR\0b\2IGNCOLLIS\0" \ + "b\3IPG0ENA\0b\4TXNGU\0b\5TXNGULIM\0" \ + "b\6NOBKOFF\0b\7SLOWDN\0b\x8NOFCS\0" \ + "b\x9TXCARREXT\0\0" /* GEM_MAC_RX_CONFIG register bits */ @@ -360,12 +377,17 @@ * Carrier Extension enables reception of packet bursts generated by * senders with carrier extension enabled. */ +#define GEM_MAC_RX_CONFIG_BITS "\177\020" \ + "b\0RXENA\0b\1STRPAD\0b\2STRCRC\0" \ + "b\3PROMIS\0b\4PROMISCGRP\0b\5HASHFLTR\0" \ + "b\6ADDRFLTR\0b\7ERRCHKDIS\0b\x9TXCARREXT\0\0" /* GEM_MAC_CONTROL_CONFIG bits */ #define GEM_MAC_CC_TX_PAUSE 0x00000001 /* send pause enabled */ #define GEM_MAC_CC_RX_PAUSE 0x00000002 /* receive pause enabled */ #define GEM_MAC_CC_PASS_PAUSE 0x00000004 /* pass pause up */ +#define GEM_MAC_CC_BITS "\177\020b\0TXPAUSE\0b\1RXPAUSE\0b\2NOPAUSE\0\0" /* GEM MIF registers */ @@ -397,7 +419,7 @@ /* GEM_MIF_CONFIG register bits */ -#define GEM_MIF_CONFIG_PHY_SEL 0x00000001 /* PHY select */ +#define GEM_MIF_CONFIG_PHY_SEL 0x00000001 /* PHY select, 0=MDIO0 */ #define GEM_MIF_CONFIG_POLL_ENA 0x00000002 /* poll enable */ #define GEM_MIF_CONFIG_BB_ENA 0x00000004 /* bit bang enable */ #define GEM_MIF_CONFIG_REG_ADR 0x000000f8 /* poll register address */ @@ -405,6 +427,8 @@ #define GEM_MIF_CONFIG_MDI1 0x00000200 /* MDIO_1 Data/MDIO_1 atached */ #define GEM_MIF_CONFIG_PHY_ADR 0x00007c00 /* poll PHY address */ /* MDI0 is onboard transceiver MID1 is external, PHYAD for both is 0 */ +#define GEM_MIF_CONFIG_BITS "\177\020b\0PHYSEL\0b\1POLL\0b\2BBENA\0" \ + "b\x8MDIO0\0b\x9MDIO1\0\0" /* GEM_MIF_BASIC_STATUS and GEM_MIF_INTERRUPT_MASK bits */ @@ -418,15 +442,15 @@ */ -/* The GEM PCS/Serial link register. */ +/* The GEM PCS/Serial link registers. */ /* DO NOT TOUCH THESE REGISTERS ON ERI -- IT HARD HANGS. */ #define GEM_MII_CONTROL 0x9000 #define GEM_MII_STATUS 0x9004 #define GEM_MII_ANAR 0x9008 /* MII advertisement reg */ -#define GEM_MII_ANLPAR 0x900c /* LP ability reg */ +#define GEM_MII_ANLPAR 0x900c /* Link Partner Ability Reg */ #define GEM_MII_CONFIG 0x9010 #define GEM_MII_STATE_MACHINE 0x9014 -#define GEM_MII_INTERRUP_STATUS 0x9018 +#define GEM_MII_INTERRUP_STATUS 0x9018 /* PCS interrupt state */ #define GEM_MII_DATAPATH_MODE 0x9050 #define GEM_MII_SLINK_CONTROL 0x9054 /* Serial link control */ #define GEM_MII_OUTPUT_SELECT 0x9058 @@ -443,20 +467,27 @@ #define GEM_MII_CONTROL_RAN 0x00000200 /* restart auto negotiation */ #define GEM_MII_CONTROL_FDUPLEX 0x00000100 /* full duplex, always 0 */ #define GEM_MII_CONTROL_COL_TST 0x00000080 /* collision test */ +#define GEM_MII_CONTROL_BITS "\177\020b\7COLTST\0b\x8_FD\0b\x9RAN\0" \ + "b\xaISOLATE\0b\xbPWRDWN\0b\xc_ANEG\0" \ + "b\xdGIGE\0b\xeLOOP\0b\xfRESET\0\0" /* GEM_MII_STATUS reg - PCS "BMSR" (Basic Mode Status Reg) */ #define GEM_MII_STATUS_GB_FDX 0x00000400 /* can perform GBit FDX */ #define GEM_MII_STATUS_GB_HDX 0x00000200 /* can perform GBit HDX */ +#define GEM_MII_STATUS_UNK 0x00000100 #define GEM_MII_STATUS_ANEG_CPT 0x00000020 /* auto negotiate compete */ #define GEM_MII_STATUS_REM_FLT 0x00000010 /* remote fault detected */ #define GEM_MII_STATUS_ACFG 0x00000008 /* can auto negotiate */ #define GEM_MII_STATUS_LINK_STS 0x00000004 /* link status */ #define GEM_MII_STATUS_JABBER 0x00000002 /* jabber condition detected */ #define GEM_MII_STATUS_EXTCAP 0x00000001 /* extended register capability */ +#define GEM_MII_STATUS_BITS "\177\020b\0EXTCAP\0b\1JABBER\0b\2LINKSTS\0" \ + "b\3ACFG\0b\4REMFLT\0b\5ANEGCPT\0b\x9GBHDX\0" \ + "b\xaGBFDX\0\0" -/* GEM_MII_ANAR and GEM_MII_ANLAR reg bits */ +/* GEM_MII_ANAR and GEM_MII_ANLPAR reg bits */ #define GEM_MII_ANEG_NP 0x00008000 /* next page bit */ #define GEM_MII_ANEG_ACK 0x00004000 /* ack reception of */ /* Link Partner Capability */ @@ -465,11 +496,20 @@ #define GEM_MII_ANEG_SYM_PAUSE 0x00000080 /* symmetric pause */ #define GEM_MII_ANEG_HLF_DUPLX 0x00000040 #define GEM_MII_ANEG_FUL_DUPLX 0x00000020 +#define GEM_MII_ANEG_BITS "\177\020b\5FDX\0b\6HDX\0b\7SYMPAUSE\0" \ + "\b\x8_ASYMPAUSE\0\b\xdREMFLT\0\b\xeLPACK\0" \ + "\b\xfNPBIT\0\0" /* GEM_MII_CONFIG reg */ -#define GEM_MII_CONFIG_TIMER 0x0000001c /* link monitor timer values */ +#define GEM_MII_CONFIG_TIMER 0x0000000e /* link monitor timer values */ +#define GEM_MII_CONFIG_ANTO 0x00000020 /* 10ms ANEG timer override */ +#define GEM_MII_CONFIG_JS 0x00000018 /* Jitter Study, 0 normal + * 1 high freq, 2 low freq */ +#define GEM_MII_CONFIG_SDL 0x00000004 /* Signal Detect active low */ +#define GEM_MII_CONFIG_SDO 0x00000002 /* Signal Detect Override */ #define GEM_MII_CONFIG_ENABLE 0x00000001 /* Enable PCS */ +#define GEM_MII_CONFIG_BITS "\177\020b\0PCSENA\0\0" /* @@ -492,7 +532,7 @@ /* GEM_MII_DATAPATH_MODE reg */ #define GEM_MII_DATAPATH_SERIAL 0x00000001 /* Serial link */ #define GEM_MII_DATAPATH_SERDES 0x00000002 /* Use PCS via 10bit interfac */ -#define GEM_MII_DATAPATH_MII 0x00000004 /* Use MII, not PCS */ +#define GEM_MII_DATAPATH_MII 0x00000004 /* Use {G}MII, not PCS */ #define GEM_MII_DATAPATH_MIIOUT 0x00000008 /* enable serial output on GMII */ #define GEM_MII_DATAPATH_BITS "\177\020" \ "b\0SERIAL\0b\1SERDES\0b\2MII\0b\3MIIOUT\0\0" @@ -506,6 +546,9 @@ #define GEM_MII_SLINK_EMPHASIS 0x00000008 /* enable emphasis */ #define GEM_MII_SLINK_SELFTEST 0x000001c0 #define GEM_MII_SLINK_POWER_OFF 0x00000200 /* Power down serial link */ +#define GEM_MII_SLINK_CONTROL_BITS \ + "\177\020b\0LOOP\0b\1ENASYNC\0b\2LOCKREF" \ + "\0b\3EMPHASIS\0b\x9PWRDWN\0\0" /* GEM_MII_SLINK_STATUS reg */ @@ -530,7 +573,9 @@ struct gem_desc { /* Transmit flags */ #define GEM_TD_BUFSIZE 0x0000000000007fffLL #define GEM_TD_CXSUM_START 0x00000000001f8000LL /* Cxsum start offset */ +#define GEM_TD_CXSUM_STARTSHFT 15 #define GEM_TD_CXSUM_STUFF 0x000000001fe00000LL /* Cxsum stuff offset */ +#define GEM_TD_CXSUM_STUFFSHFT 21 #define GEM_TD_CXSUM_ENABLE 0x0000000020000000LL /* Cxsum generation enable */ #define GEM_TD_END_OF_PACKET 0x0000000040000000LL #define GEM_TD_START_OF_PACKET 0x0000000080000000LL @@ -542,7 +587,7 @@ struct gem_desc { */ /* Receive flags */ -#define GEM_RD_CHECKSUM 0x000000000000ffffLL +#define GEM_RD_CHECKSUM 0x000000000000ffffLL /* is the complement */ #define GEM_RD_BUFSIZE 0x000000007fff0000LL #define GEM_RD_OWN 0x0000000080000000LL /* 1 - owned by h/w */ #define GEM_RD_HASHVAL 0x0ffff00000000000LL |
