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authorichiro <ichiro@NetBSD.org>2001-10-13 15:00:23 +0000
committerichiro <ichiro@NetBSD.org>2001-10-13 15:00:23 +0000
commitcbcfff63ec7b3663616433f2db8810e84d741055 (patch)
tree715f9e1a6178faa93d341191bc6284355ae879f5 /sys/dev/ic
parent9202040b703bb7277d88328ff97f8f1046a9859d (diff)
Add Intersil Prism2.5 Mini-PCI wavelan.
Diffstat (limited to 'sys/dev/ic')
-rw-r--r--sys/dev/ic/wi.c20
-rw-r--r--sys/dev/ic/wireg.h59
-rw-r--r--sys/dev/ic/wivar.h4
3 files changed, 67 insertions, 16 deletions
diff --git a/sys/dev/ic/wi.c b/sys/dev/ic/wi.c
index 9e3c13bacf4..aab90fa0049 100644
--- a/sys/dev/ic/wi.c
+++ b/sys/dev/ic/wi.c
@@ -1,4 +1,4 @@
-/* $NetBSD: wi.c,v 1.25 2001/09/22 17:22:25 explorer Exp $ */
+/* $NetBSD: wi.c,v 1.26 2001/10/13 15:00:23 ichiro Exp $ */
/*
* Copyright (c) 1997, 1998, 1999
@@ -707,6 +707,20 @@ wi_reset(sc)
return;
}
+void
+wi_pci_reset(sc)
+ struct wi_softc *sc;
+{
+
+ bus_space_write_2(sc->sc_iot, sc->sc_ioh, WI_PCI_COR, 0x80);
+ DELAY(100*1000); /* 100 m sec */
+
+ bus_space_write_2(sc->sc_iot, sc->sc_ioh, WI_PCI_COR, 0x0);
+ DELAY(100*1000); /* 100 m sec */
+
+ return;
+}
+
/*
* Read an LTV record from the NIC.
*/
@@ -1891,6 +1905,10 @@ wi_get_id(sc)
printf("RF:PRISM2.5 MAC:ISL3873");
sc->sc_prism2 = 1;
break;
+ case WI_NIC_3874A:
+ printf("RF:PRISM2.5 MAC:ISL3874A(PCI)");
+ sc->sc_prism2 = 1;
+ break;
default:
printf("Lucent chip or unknown chip\n");
sc->sc_prism2 = 0;
diff --git a/sys/dev/ic/wireg.h b/sys/dev/ic/wireg.h
index 2ff423be58e..f1a1eb214e5 100644
--- a/sys/dev/ic/wireg.h
+++ b/sys/dev/ic/wireg.h
@@ -1,4 +1,4 @@
-/* $NetBSD: wireg.h,v 1.10 2001/09/22 17:22:25 explorer Exp $ */
+/* $NetBSD: wireg.h,v 1.11 2001/10/13 15:00:23 ichiro Exp $ */
/*
* Copyright (c) 1997, 1998, 1999
@@ -96,18 +96,24 @@
* register space access macros
*/
#define CSR_WRITE_4(sc, reg, val) \
- bus_space_write_4(sc->sc_iot, sc->sc_ioh, reg, val)
+ bus_space_write_4(sc->sc_iot, sc->sc_ioh, \
+ (sc->sc_pci? reg * 2: reg) , val)
#define CSR_WRITE_2(sc, reg, val) \
- bus_space_write_2(sc->sc_iot, sc->sc_ioh, reg, val)
+ bus_space_write_2(sc->sc_iot, sc->sc_ioh, \
+ (sc->sc_pci? reg * 2: reg), val)
#define CSR_WRITE_1(sc, reg, val) \
- bus_space_write_1(sc->sc_iot, sc->sc_ioh, reg, val)
+ bus_space_write_1(sc->sc_iot, sc->sc_ioh, \
+ (sc->sc_pci? reg * 2: reg), val)
#define CSR_READ_4(sc, reg) \
- bus_space_read_4(sc->sc_iot, sc->sc_ioh, reg)
+ bus_space_read_4(sc->sc_iot, sc->sc_ioh, \
+ (sc->sc_pci? reg * 2: reg))
#define CSR_READ_2(sc, reg) \
- bus_space_read_2(sc->sc_iot, sc->sc_ioh, reg)
+ bus_space_read_2(sc->sc_iot, sc->sc_ioh, \
+ (sc->sc_pci? reg * 2: reg))
#define CSR_READ_1(sc, reg) \
- bus_space_read_1(sc->sc_iot, sc->sc_ioh, reg)
+ bus_space_read_1(sc->sc_iot, sc->sc_ioh, \
+ (sc->sc_pci? reg * 2: reg))
#ifndef __BUS_SPACE_HAS_STREAM_METHODS
#define bus_space_write_stream_2 bus_space_write_2
@@ -117,13 +123,17 @@
#endif
#define CSR_WRITE_STREAM_2(sc, reg, val) \
- bus_space_write_stream_2(sc->sc_iot, sc->sc_ioh, reg, val)
+ bus_space_write_stream_2(sc->sc_iot, sc->sc_ioh, \
+ (sc->sc_pci? reg * 2: reg), val)
#define CSR_WRITE_MULTI_STREAM_2(sc, reg, val, count) \
- bus_space_write_multi_stream_2(sc->sc_iot, sc->sc_ioh, reg, val, count)
+ bus_space_write_multi_stream_2(sc->sc_iot, sc->sc_ioh, \
+ (sc->sc_pci? reg * 2: reg), val, count)
#define CSR_READ_STREAM_2(sc, reg) \
- bus_space_read_stream_2(sc->sc_iot, sc->sc_ioh, reg)
+ bus_space_read_stream_2(sc->sc_iot, sc->sc_ioh, \
+ (sc->sc_pci? reg * 2: reg))
#define CSR_READ_MULTI_STREAM_2(sc, reg, buf, count) \
- bus_space_read_multi_stream_2(sc->sc_iot, sc->sc_ioh, reg, buf, count)
+ bus_space_read_multi_stream_2(sc->sc_iot, sc->sc_ioh, \
+ (sc->sc_pci? reg * 2: reg), buf, count)
/*
* The WaveLAN/IEEE cards contain an 802.11 MAC controller which Lucent
@@ -165,12 +175,13 @@
*/
/*
- * Size of Hermes I/O space.
+ * Size of Hermes & Prism2 I/O space.
*/
#define WI_IOSIZE 0x40
+#define WI_PCI_CBMA 0x10 /* Configuration Base Memory Address */
/*
- * Hermes register definitions and what little I know about them.
+ * Hermes & Prism2 register definitions
*/
/* Hermes command/status registers. */
@@ -285,7 +296,7 @@
#define WI_SW0 0x28
#define WI_SW1 0x2A
#define WI_SW2 0x2C
-#define WI_SW3 0x2E
+#define WI_SW3 0x2E /* does not appear in Prism2 */
#define WI_CNTL 0x14
@@ -300,6 +311,25 @@
#define WI_AUX_DATA 0x3E
/*
+ * PCI Host Interface Registers (HFA3842 Specific)
+ * The value of all Register's Offset, such as WI_INFO_FID and WI_PARAM0,
+ * has doubled.
+ */
+#define WI_PCI_COR 0x4C
+#define WI_PCI_HCR 0x5C
+#define WI_PCI_MASTER0_ADDRH 0x80
+#define WI_PCI_MASTER0_ADDRL 0x84
+#define WI_PCI_MASTER0_LEN 0x88
+#define WI_PCI_MASTER0_CON 0x8C
+
+#define WI_PCI_STATUS 0x98
+
+#define WI_PCI_MASTER1_ADDRH 0xA0
+#define WI_PCI_MASTER1_ADDRL 0xA4
+#define WI_PCI_MASTER1_LEN 0xA8
+#define WI_PCI_MASTER1_CON 0xAC
+
+/*
* One form of communication with the Hermes is with what Lucent calls
* LTV records, where LTV stands for Length, Type and Value. The length
* and type are 16 bits and are in native byte order. The value is in
@@ -381,6 +411,7 @@ struct wi_ltv_ver {
#define WI_NIC_HWB1153 0x8007
#define WI_NIC_P2_SST 0x8008 /* Prism2 with SST flush */
#define WI_NIC_PRISM2_5 0x800C
+#define WI_NIC_3874A 0x8013 /* Prism2.5 Mini-PCI */
};
/*
diff --git a/sys/dev/ic/wivar.h b/sys/dev/ic/wivar.h
index 5ee11613e62..c8e3f7c1e57 100644
--- a/sys/dev/ic/wivar.h
+++ b/sys/dev/ic/wivar.h
@@ -1,4 +1,4 @@
-/* $NetBSD: wivar.h,v 1.5 2001/09/22 17:22:25 explorer Exp $ */
+/* $NetBSD: wivar.h,v 1.6 2001/10/13 15:00:24 ichiro Exp $ */
/*
* Copyright (c) 1997, 1998, 1999
@@ -50,6 +50,7 @@ struct wi_softc {
int sc_enabled;
int sc_prism2;
int sc_prism2_ver;
+ int sc_pci; /* attach to PCI-Bus */
bus_space_tag_t sc_iot; /* bus cookie */
bus_space_handle_t sc_ioh; /* bus i/o handle */
@@ -96,3 +97,4 @@ int wi_activate __P((struct device *, enum devact));
int wi_intr __P((void *arg));
void wi_power __P((struct wi_softc *, int));
void wi_shutdown __P((struct wi_softc *));
+void wi_pci_reset __P((struct wi_softc *));