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authorjmcneill <jmcneill@NetBSD.org>2018-02-07 20:42:17 +0000
committerjmcneill <jmcneill@NetBSD.org>2018-02-07 20:42:17 +0000
commit08b28c678db8c941d5b7499ed4ddb36a3a067e47 (patch)
tree9908f805ec179c49d9ef61c2a13b89cdf8adc717 /sys/dev/microcode
parentb77998122bc6b673634d097e48b5f5dc64f3d8c3 (diff)
PR# port-evbarm/49468: Cortex GIC assertion triggered on Allwinner A80 SoC
The priority level is changed by writing to GICC_PMR with interrupts disabled. However, interrupts are enabled/disabled downstream of the GICC at the CPU. When raising priority level, there is a window between the time that interrupts are disabled and the GICC_PMR register is written. If an interrupt occurs at a previously allowed priority before GICC_PMR is changed, the CPU will receive the signal when interrupts are re-enabled. At this time, GICC_PMR is now the new priority level, so reads of GICC_IAR will report a spurious IRQ. Move the "old_ipl != IPL_HIGH" test until after we have confirmed that there is at least one pending IRQ.
Diffstat (limited to 'sys/dev/microcode')
0 files changed, 0 insertions, 0 deletions