diff options
| author | mycroft <mycroft@NetBSD.org> | 1994-04-14 03:54:07 +0000 |
|---|---|---|
| committer | mycroft <mycroft@NetBSD.org> | 1994-04-14 03:54:07 +0000 |
| commit | 07b358873549ddbdce25974faa32a2efd53309a7 (patch) | |
| tree | ca329e624f5164582edbe6cfa1558887b2dbfd3f /sys/dev | |
| parent | ecc12ef4198455e37d618eaf125fc5b44fbbfbd2 (diff) | |
Patches from David Greenman to eliminate magic constants and add delays when
switching to and fro 16-bit access for 790s.
Diffstat (limited to 'sys/dev')
| -rw-r--r-- | sys/dev/isa/if_ed.c | 45 | ||||
| -rw-r--r-- | sys/dev/isa/if_edreg.h | 57 |
2 files changed, 89 insertions, 13 deletions
diff --git a/sys/dev/isa/if_ed.c b/sys/dev/isa/if_ed.c index f0f239cc95c..374bb4fe97c 100644 --- a/sys/dev/isa/if_ed.c +++ b/sys/dev/isa/if_ed.c @@ -13,7 +13,7 @@ * Currently supports the Western Digital/SMC 8003 and 8013 series, the 3Com * 3c503, the NE1000 and NE2000, and a variety of similar clones. * - * $Id: if_ed.c,v 1.41 1994/04/08 17:16:39 mycroft Exp $ + * $Id: if_ed.c,v 1.42 1994/04/14 03:54:07 mycroft Exp $ */ #include "bpfilter.h" @@ -395,12 +395,16 @@ ed_probe_WD80x3(sc, cf, ia) */ sc->ed_cr_rd2 = ED_CR_RD2; if (sc->is790) { + u_char x; sc->ed_cr_rd2 = 0; /* Assemble together the encoded interrupt number. */ - outb(ia->ia_iobase + 0x04, inb(ia->ia_iobase + 0x04) | 0x80); - iptr = ((inb(ia->ia_iobase + 0x0d) & 0x0c) >> 2) | - ((inb(ia->ia_iobase + 0x0d) & 0x40) >> 4); - outb(ia->ia_iobase + 0x04, inb(ia->ia_iobase + 0x04) & ~0x80); + outb(ia->ia_iobase + ED_WD790_HWR, + inb(ia->ia_iobase + ED_WD790_HWR) | ED_WD790_HWR_SWH); + x = inb(ia->ia_iobase + ED_WD790_GCR); + iptr = ((x & ED_WD790_GCR_IR2) >> 4) | + ((x & (ED_WD790_GCR_IR1|ED_WD790_GCR_IR0)) >> 2); + outb(ia->ia_iobase + ED_WD790_HWR, + inb(ia->ia_iobase + ED_WD790_HWR) & ~ED_WD790_HWR_SWH); /* * Translate it using translation table, and check for * correctness. @@ -412,7 +416,8 @@ ed_probe_WD80x3(sc, cf, ia) return 0; } /* Enable the interrupt. */ - outb(ia->ia_iobase + 0x06, inb(ia->ia_iobase + 0x06) | 0x01); + outb(ia->ia_iobase + ED_WD790_ICR, + inb(ia->ia_iobase + ED_WD790_ICR) | ED_WD790_ICR_EIL); } else if (sc->type & ED_WD_SOFTCONFIG) { /* Assemble together the encoded interrupt number. */ iptr = (inb(ia->ia_iobase + ED_WD_ICR) & ED_WD_ICR_IR2) | @@ -509,6 +514,7 @@ ed_probe_WD80x3(sc, cf, ia) inb(sc->asic_addr + ED_WD_LAAR); outb(sc->asic_addr + ED_WD_LAAR, ED_WD_LAAR_M16EN); + (void) inb(0x84); } else { sc->wd_laar_proto = ED_WD_LAAR_L16EN | ED_WD_LAAR_M16EN | @@ -547,6 +553,7 @@ ed_probe_WD80x3(sc, cf, ia) sc->wd_laar_proto &= ~ED_WD_LAAR_M16EN; outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto); + (void) inb(0x84); } return 0; } @@ -562,6 +569,7 @@ ed_probe_WD80x3(sc, cf, ia) if (isa16bit) { sc->wd_laar_proto &= ~ED_WD_LAAR_M16EN; outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto); + (void) inb(0x84); } } @@ -1375,6 +1383,14 @@ outloop: case ED_VENDOR_WD_SMC: outb(sc->asic_addr + ED_WD_LAAR, (sc->wd_laar_proto | ED_WD_LAAR_M16EN)); + (void) inb(0x84); + if (sc->is790) { + outb(sc->asic_addr + ED_WD_MSR, + ED_WD_MSR_MENB); + (void) inb(0x84); + } + (void) inb(0x84); + break; } } @@ -1394,6 +1410,11 @@ outloop: case ED_VENDOR_WD_SMC: outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto); + (void) inb(0x84); + if (sc->is790) { + outb(sc->asic_addr + ED_WD_MSR, 0x00); + (void) inb(0x84); + } break; } } @@ -1705,6 +1726,12 @@ edintr(sc) sc->wd_laar_proto |= ED_WD_LAAR_M16EN; outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto); + (void) inb(0x84); + if (sc->is790) { + outb(sc->asic_addr + ED_WD_MSR, + ED_WD_MSR_MENB); + (void) inb(0x84); + } } ed_rint(sc); @@ -1715,6 +1742,12 @@ edintr(sc) sc->wd_laar_proto &= ~ED_WD_LAAR_M16EN; outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto); + (void) inb(0x84); + if (sc->is790) { + outb(sc->asic_addr + ED_WD_MSR, + 0x00); + (void) inb(0x84); + } } } } diff --git a/sys/dev/isa/if_edreg.h b/sys/dev/isa/if_edreg.h index 365f4ac3e55..7ff64a1f36a 100644 --- a/sys/dev/isa/if_edreg.h +++ b/sys/dev/isa/if_edreg.h @@ -1,7 +1,7 @@ /* * National Semiconductor DS8390 NIC register definitions * - * $Id: if_edreg.h,v 1.8 1994/03/02 22:47:41 mycroft Exp $ + * $Id: if_edreg.h,v 1.9 1994/04/14 03:54:14 mycroft Exp $ */ /* @@ -583,14 +583,14 @@ struct ed_ring { */ #define ED_WD_MSR 0 -#define ED_WD_MSR_ADDR 0x3f /* Memory decode bits 18-13 */ -#define ED_WD_MSR_MENB 0x40 /* Memory enable */ -#define ED_WD_MSR_RST 0x80 /* Reset board */ -#ifdef TOSH_ETHER +/* next three definitions for Toshiba */ #define ED_WD_MSR_POW 0x02 /* 0 = power save, 1 = normal (R/W) */ #define ED_WD_MSR_BSY 0x04 /* gate array busy (R) */ #define ED_WD_MSR_LEN 0x20 /* 0 = 16-bit, 1 = 8-bit (R/W) */ -#endif + +#define ED_WD_MSR_ADDR 0x3f /* Memory decode bits 18-13 */ +#define ED_WD_MSR_MENB 0x40 /* Memory enable */ +#define ED_WD_MSR_RST 0x80 /* Reset board */ /* * Interface Configuration Register (ICR) @@ -636,7 +636,7 @@ struct ed_ring { #define ED_WD_IRR_FLASH 0x10 /* Flash RAM is in the ROM socket */ /* - * The three bit of the encoded IRQ are decoded as follows: + * The three bits of the encoded IRQ are decoded as follows: * * IR2 IR1 IR0 IRQ * 0 0 0 2/9 @@ -665,6 +665,49 @@ struct ed_ring { /* i/o base offset to station address/card-ID PROM */ #define ED_WD_PROM 8 +/* + * 83C790 specific registers + */ +/* + * Hardware Support Register (HWR) ('790) + */ +#define ED_WD790_HWR 4 + +#define ED_WD790_HWR_RST 0x10 /* hardware reset */ +#define ED_WD790_HWR_LPRM 0x40 /* LAN PROM select */ +#define ED_WD790_HWR_SWH 0x80 /* switch register set */ + +/* + * ICR790 Interrupt Control Register for the 83C790 + */ +#define ED_WD790_ICR 6 + +#define ED_WD790_ICR_EIL 0x01 /* enable interrupts */ + +/* + * General Control Register (GCR) + * Eanbled with SWH bit == 1 in HWR register + */ +#define ED_WD790_GCR 0x0d + +#define ED_WD790_GCR_IR0 0x04 /* bit 0 of encoded IRQ */ +#define ED_WD790_GCR_IR1 0x08 /* bit 1 of encoded IRQ */ +#define ED_WD790_GCR_ZWSEN 0x20 /* zero wait state enable */ +#define ED_WD790_GCR_IR2 0x40 /* bit 2 of encoded IRQ */ +/* + * The three bits of the encoded IRQ are decoded as follows: + * + * IR2 IR1 IR0 IRQ + * 0 0 0 none + * 0 0 1 9 + * 0 1 0 3 + * 0 1 1 5 + * 1 0 0 7 + * 1 0 1 10 + * 1 1 0 11 + * 1 1 1 15 + */ + /* i/o base offset to CARD ID */ #define ED_WD_CARD_ID ED_WD_PROM+6 |
