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authormycroft <mycroft@NetBSD.org>1994-04-22 22:58:50 +0000
committermycroft <mycroft@NetBSD.org>1994-04-22 22:58:50 +0000
commit221b25fd9ddac3743fdc90f7451ac7e2d8f4b49d (patch)
tree31bf27490993f749ff9ad5372b8673189806d739 /sys/dev
parentb1196f172060d971c1c84170e1dbd7dcddc8064b (diff)
Separate DMA functions.
Diffstat (limited to 'sys/dev')
-rw-r--r--sys/dev/isa/isa.c286
-rw-r--r--sys/dev/isa/isadma.c248
-rw-r--r--sys/dev/isa/isadmareg.h19
-rw-r--r--sys/dev/isa/isadmavar.h4
-rw-r--r--sys/dev/isa/sb.c3
-rw-r--r--sys/dev/isa/wt.c3
6 files changed, 127 insertions, 436 deletions
diff --git a/sys/dev/isa/isa.c b/sys/dev/isa/isa.c
index 382fcb3c03f..7a435610dd7 100644
--- a/sys/dev/isa/isa.c
+++ b/sys/dev/isa/isa.c
@@ -35,7 +35,7 @@
* SUCH DAMAGE.
*
* from: @(#)isa.c 7.2 (Berkeley) 5/13/91
- * $Id: isa.c,v 1.50 1994/04/21 04:26:37 mycroft Exp $
+ * $Id: isa.c,v 1.51 1994/04/22 22:58:59 mycroft Exp $
*/
/*
@@ -46,22 +46,15 @@
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/conf.h>
-#include <sys/file.h>
-#include <sys/buf.h>
-#include <sys/uio.h>
-#include <sys/syslog.h>
#include <sys/malloc.h>
#include <sys/device.h>
-#include <vm/vm.h>
-
#include <machine/pio.h>
#include <machine/cpufunc.h>
#include <i386/isa/isa.h>
#include <i386/isa/isa_device.h>
#include <i386/isa/isavar.h>
-#include <i386/isa/ic/i8237.h>
#include <i386/isa/ic/i8042.h>
#include <i386/isa/timerreg.h>
#include <i386/isa/spkr_reg.h>
@@ -70,24 +63,6 @@
#include <machine/pc/display.h>
u_short *Crtat = (u_short *)MONO_BUF;
-/*
- * Register definitions for DMA controller 1 (channels 0..3):
- */
-#define DMA1_CHN(c) (IO_DMA1 + 1*(2*(c))) /* addr reg for channel c */
-#define DMA1_SR (IO_DMA1 + 1*8) /* status register */
-#define DMA1_SMSK (IO_DMA1 + 1*10) /* single mask register */
-#define DMA1_MODE (IO_DMA1 + 1*11) /* mode register */
-#define DMA1_FFC (IO_DMA1 + 1*12) /* clear first/last FF */
-
-/*
- * Register definitions for DMA controller 2 (channels 4..7):
- */
-#define DMA2_CHN(c) (IO_DMA2 + 2*(2*(c))) /* addr reg for channel c */
-#define DMA2_SR (IO_DMA2 + 2*8) /* status register */
-#define DMA2_SMSK (IO_DMA2 + 2*10) /* single mask register */
-#define DMA2_MODE (IO_DMA2 + 2*11) /* mode register */
-#define DMA2_FFC (IO_DMA2 + 2*12) /* clear first/last FF */
-
static void sysbeepstop(int);
/*
@@ -148,7 +123,8 @@ config_search(fn, parent, aux)
cd->cd_devs = nsp;
}
if (!cf) {
- cf = malloc(sizeof(struct cfdata), M_DEVBUF, M_NOWAIT); if (!cf)
+ cf = malloc(sizeof(struct cfdata), M_DEVBUF, M_NOWAIT);
+ if (!cf)
panic("config_search: creating cfdata");
}
cf->cf_driver = cd;
@@ -296,262 +272,6 @@ isa_configure()
spl0();
}
-/* region of physical memory known to be contiguous */
-vm_offset_t isaphysmem;
-static caddr_t dma_bounce[8]; /* XXX */
-static char bounced[8]; /* XXX */
-#define MAXDMASZ 512 /* XXX */
-
-/* high byte of address is stored in this port for i-th dma channel */
-static short dmapageport[8] =
- { 0x87, 0x83, 0x81, 0x82, 0x8f, 0x8b, 0x89, 0x8a };
-
-/*
- * isa_dmacascade(): program 8237 DMA controller channel to accept
- * external dma control by a board.
- */
-void
-isa_dmacascade(chan)
- int chan;
-{
-
-#ifdef DIAGNOSTIC
- if (chan < 0 || chan > 7)
- panic("isa_dmacascade: impossible request");
-#endif
-
- /* set dma channel mode, and set dma channel mode */
- if ((chan & 4) == 0) {
- outb(DMA1_MODE, DMA37MD_CASCADE | chan);
- outb(DMA1_SMSK, chan);
- } else {
- outb(DMA2_MODE, DMA37MD_CASCADE | (chan & 3));
- outb(DMA2_SMSK, chan & 3);
- }
-}
-
-/*
- * isa_dmastart(): program 8237 DMA controller channel, avoid page alignment
- * problems by using a bounce buffer.
- */
-void
-isa_dmastart(flags, addr, nbytes, chan)
- int flags;
- caddr_t addr;
- vm_size_t nbytes;
- int chan;
-{
- vm_offset_t phys;
- int waport;
- caddr_t newaddr;
-
-#ifdef DIAGNOSTIC
- if (chan < 0 || chan > 7 ||
- ((chan & 4) ? (nbytes >= (1<<17) || nbytes & 1 || (u_int)addr & 1) :
- (nbytes >= (1<<16))))
- panic("isa_dmastart: impossible request");
-#endif
-
- if (isa_dmarangecheck(addr, nbytes, chan)) {
- if (dma_bounce[chan] == 0)
- dma_bounce[chan] =
- /*(caddr_t)malloc(MAXDMASZ, M_TEMP, M_WAITOK);*/
- (caddr_t) isaphysmem + NBPG*chan;
- bounced[chan] = 1;
- newaddr = dma_bounce[chan];
- *(int *) newaddr = 0; /* XXX */
- /* copy bounce buffer on write */
- if ((flags & B_READ) == 0)
- bcopy(addr, newaddr, nbytes);
- addr = newaddr;
- }
-
- /* translate to physical */
- phys = pmap_extract(pmap_kernel(), (vm_offset_t)addr);
-
- if ((chan & 4) == 0) {
- /*
- * Program one of DMA channels 0..3. These are
- * byte mode channels.
- */
- /* set dma channel mode, and reset address ff */
- if (flags & B_READ)
- outb(DMA1_MODE, chan | DMA37MD_SINGLE | DMA37MD_WRITE);
- else
- outb(DMA1_MODE, chan | DMA37MD_SINGLE | DMA37MD_READ);
- outb(DMA1_FFC, 0);
-
- /* send start address */
- waport = DMA1_CHN(chan);
- outb(waport, phys);
- outb(waport, phys>>8);
- outb(dmapageport[chan], phys>>16);
-
- /* send count */
- outb(waport + 1, --nbytes);
- outb(waport + 1, nbytes>>8);
-
- /* unmask channel */
- outb(DMA1_SMSK, chan | DMA37SM_CLEAR);
- } else {
- /*
- * Program one of DMA channels 4..7. These are
- * word mode channels.
- */
- /* set dma channel mode, and reset address ff */
- if (flags & B_READ)
- outb(DMA2_MODE, (chan & 3) | DMA37MD_SINGLE | DMA37MD_WRITE);
- else
- outb(DMA2_MODE, (chan & 3) | DMA37MD_SINGLE | DMA37MD_READ);
- outb(DMA2_FFC, 0);
-
- /* send start address */
- waport = DMA2_CHN(chan & 3);
- outb(waport, phys>>1);
- outb(waport, phys>>9);
- outb(dmapageport[chan], phys>>16);
-
- /* send count */
- nbytes >>= 1;
- outb(waport + 2, --nbytes);
- outb(waport + 2, nbytes>>8);
-
- /* unmask channel */
- outb(DMA2_SMSK, (chan & 3) | DMA37SM_CLEAR);
- }
-}
-
-void
-isa_dmaabort(chan)
- int chan;
-{
-
-#ifdef DIAGNOSTIC
- if (chan < 0 || chan > 7)
- panic("isa_dmaabort: impossible request");
-#endif
-
- bounced[chan] = 0;
-
- /* mask channel */
- if ((chan & 4) == 0)
- outb(DMA1_SMSK, DMA37SM_SET | chan);
- else
- outb(DMA2_SMSK, DMA37SM_SET | (chan & 3));
-}
-
-void
-isa_dmadone(flags, addr, nbytes, chan)
- int flags;
- caddr_t addr;
- vm_size_t nbytes;
- int chan;
-{
- u_char tc;
-
-#ifdef DIAGNOSTIC
- if (chan < 0 || chan > 7)
- panic("isa_dmadone: impossible request");
-#endif
-
- /* check that the terminal count was reached */
- if ((chan & 4) == 0)
- tc = inb(DMA1_SR) & (1 << chan);
- else
- tc = inb(DMA2_SR) & (1 << (chan & 3));
- if (tc == 0)
- /* XXX probably should panic or something */
- log(LOG_ERR, "dma channel %d not finished\n", chan);
-
- /* copy bounce buffer on read */
- if (bounced[chan]) {
- bcopy(dma_bounce[chan], addr, nbytes);
- bounced[chan] = 0;
- }
-
- /* mask channel */
- if ((chan & 4) == 0)
- outb(DMA1_SMSK, DMA37SM_SET | chan);
- else
- outb(DMA2_SMSK, DMA37SM_SET | (chan & 3));
-}
-
-/*
- * Check for problems with the address range of a DMA transfer
- * (non-contiguous physical pages, outside of bus address space,
- * crossing DMA page boundaries).
- * Return true if special handling needed.
- */
-int
-isa_dmarangecheck(va, length, chan)
- vm_offset_t va;
- u_long length;
- int chan;
-{
- vm_offset_t phys, priorpage = 0, endva;
- u_int dma_pgmsk = (chan & 4) ? ~(128*1024-1) : ~(64*1024-1);
-
- endva = round_page(va + length);
- for (; va < endva ; va += NBPG) {
- phys = trunc_page(pmap_extract(pmap_kernel(), va));
- if (phys == 0)
- panic("isa_dmacheck: no physical page present");
- if (phys >= (1<<24))
- return 1;
- if (priorpage) {
- if (priorpage + NBPG != phys)
- return 1;
- /* check if crossing a DMA page boundary */
- if ((priorpage ^ phys) & dma_pgmsk)
- return 1;
- }
- priorpage = phys;
- }
- return 0;
-}
-
-/* head of queue waiting for physmem to become available */
-struct buf isa_physmemq;
-
-/* blocked waiting for resource to become free for exclusive use */
-static isaphysmemflag;
-/* if waited for and call requested when free (B_CALL) */
-static void (*isaphysmemunblock)(); /* needs to be a list */
-
-/*
- * Allocate contiguous physical memory for transfer, returning
- * a *virtual* address to region. May block waiting for resource.
- * (assumed to be called at splbio())
- */
-caddr_t
-isa_allocphysmem(caddr_t va, unsigned length, void (*func)()) {
-
- isaphysmemunblock = func;
- while (isaphysmemflag & B_BUSY) {
- isaphysmemflag |= B_WANTED;
- sleep((caddr_t)&isaphysmemflag, PRIBIO);
- }
- isaphysmemflag |= B_BUSY;
-
- return((caddr_t)isaphysmem);
-}
-
-/*
- * Free contiguous physical memory used for transfer.
- * (assumed to be called at splbio())
- */
-void
-isa_freephysmem(caddr_t va, unsigned length) {
-
- isaphysmemflag &= ~B_BUSY;
- if (isaphysmemflag & B_WANTED) {
- isaphysmemflag &= B_WANTED;
- wakeup((caddr_t)&isaphysmemflag);
- if (isaphysmemunblock)
- (*isaphysmemunblock)();
- }
-}
-
static int beeping;
static void
diff --git a/sys/dev/isa/isadma.c b/sys/dev/isa/isadma.c
index 60c8bf1694f..06e22e1a23a 100644
--- a/sys/dev/isa/isadma.c
+++ b/sys/dev/isa/isadma.c
@@ -1,131 +1,43 @@
-/*-
- * Copyright (c) 1993 Charles Hannum.
- * Copyright (c) 1991 The Regents of the University of California.
- * All rights reserved.
- *
- * This code is derived from software contributed to Berkeley by
- * William Jolitz.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- * must display the following acknowledgement:
- * This product includes software developed by the University of
- * California, Berkeley and its contributors.
- * 4. Neither the name of the University nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * from: @(#)isa.c 7.2 (Berkeley) 5/13/91
- * $Id: isadma.c,v 1.4 1993/10/22 20:24:14 mycroft Exp $
- */
-
-/*
- * code to deal with ISA DMA
- */
-
#include <sys/param.h>
#include <sys/systm.h>
-#include <sys/conf.h>
#include <sys/file.h>
+#include <sys/buf.h>
#include <sys/syslog.h>
-#include <sys/device.h>
+#include <sys/malloc.h>
+#include <sys/uio.h>
+
#include <vm/vm.h>
-#include <machine/cpu.h>
#include <machine/pio.h>
#include <i386/isa/isa.h>
-#include <i386/isa/isavar.h>
-#include <i386/isa/ic/i8237.h>
-
-/*
-** Register definitions for DMA controller 1 (channels 0..3):
-*/
-#define DMA1_CHN(c) (IO_DMA1 + 1*(2*(c))) /* addr reg for channel c */
-#define DMA1_SR (IO_DMA1 + 1*8) /* status register */
-#define DMA1_SMSK (IO_DMA1 + 1*10) /* single mask register */
-#define DMA1_MODE (IO_DMA1 + 1*11) /* mode register */
-#define DMA1_FFC (IO_DMA1 + 1*12) /* clear first/last FF */
-
-/*
-** Register definitions for DMA controller 2 (channels 4..7):
-*/
-#define DMA2_CHN(c) (IO_DMA2 + 2*(2*(c))) /* addr reg for channel c */
-#define DMA2_SR (IO_DMA2 + 2*8) /* status register */
-#define DMA2_SMSK (IO_DMA2 + 2*10) /* single mask register */
-#define DMA2_MODE (IO_DMA2 + 2*11) /* mode register */
-#define DMA2_FFC (IO_DMA2 + 2*12) /* clear first/last FF */
+#include <i386/isa/dmavar.h>
+#include <i386/isa/dmareg.h>
/* region of physical memory known to be contiguous */
-caddr_t isaphysmem;
-static caddr_t bouncebuf[8]; /* XXX */
-static caddr_t bounced[8]; /* XXX */
-static vm_size_t bouncesize[8]; /* XXX */
+vm_offset_t isaphysmem;
+static caddr_t dma_bounce[8]; /* XXX */
+static char bounced[8]; /* XXX */
+#define MAXDMASZ 512 /* XXX */
/* high byte of address is stored in this port for i-th dma channel */
-static u_short dmapageport[8] =
+static short dmapageport[8] =
{ 0x87, 0x83, 0x81, 0x82, 0x8f, 0x8b, 0x89, 0x8a };
/*
- * at_setup_dmachan(): allocate bounce buffer and check for conflicts.
- *
- * XXX
- * This sucks. We should be able to bounce more than NBPG bytes, but I
- * don't feel like writing the code to do contiguous allocation right now.
- */
-void
-at_setup_dmachan(chan, max)
- int chan;
- u_long max;
-{
-
-#ifdef DIAGNOSTIC
- if (chan > 7 || chan < 0)
- panic("at_setup_dmachan: impossible request");
- if (max > NBPG)
- panic("at_setup_dmachan: what a lose");
-#endif
-
- /* XXX check for drq conflict? */
-
- bouncebuf[chan] = (caddr_t) isaphysmem + NBPG*chan;
-}
-
-/*
- * at_dma_cascade(): program 8237 DMA controller channel to accept
+ * isa_dmacascade(): program 8237 DMA controller channel to accept
* external dma control by a board.
*/
void
-at_dma_cascade(chan)
+isa_dmacascade(chan)
int chan;
{
#ifdef DIAGNOSTIC
- if (chan > 7 || chan < 0)
- panic("at_dma_cascade: impossible request");
+ if (chan < 0 || chan > 7)
+ panic("isa_dmacascade: impossible request");
#endif
- /* XXX check for drq conflict? */
-
/* set dma channel mode, and set dma channel mode */
if ((chan & 4) == 0) {
outb(DMA1_MODE, DMA37MD_CASCADE | chan);
@@ -137,12 +49,12 @@ at_dma_cascade(chan)
}
/*
- * at_dma(): program 8237 DMA controller channel, avoid page alignment
+ * isa_dmastart(): program 8237 DMA controller channel, avoid page alignment
* problems by using a bounce buffer.
*/
void
-at_dma(read, addr, nbytes, chan)
- int read;
+isa_dmastart(flags, addr, nbytes, chan)
+ int flags;
caddr_t addr;
vm_size_t nbytes;
int chan;
@@ -152,27 +64,23 @@ at_dma(read, addr, nbytes, chan)
caddr_t newaddr;
#ifdef DIAGNOSTIC
- if (chan > 7 || chan < 0 ||
- (chan < 4 && nbytes > (1<<16)) ||
- (chan >= 4 && (nbytes > (1<<17) || nbytes & 1 || (u_int)addr & 1)))
- panic("at_dma: impossible request");
+ if (chan < 0 || chan > 7 ||
+ ((chan & 4) ? (nbytes >= (1<<17) || nbytes & 1 || (u_int)addr & 1) :
+ (nbytes >= (1<<16))))
+ panic("isa_dmastart: impossible request");
#endif
- if (at_dma_rangecheck((vm_offset_t)addr, nbytes, chan)) {
- if (bouncebuf[chan] == 0)
- /* some twit forgot to call at_setup_dmachan() */
- panic("at_dma: no bounce buffer");
- /* XXX totally braindead; NBPG is not enough */
- if (nbytes > NBPG)
- panic("at_dma: transfer too large");
- bouncesize[chan] = nbytes;
- newaddr = bouncebuf[chan];
+ if (isa_dmarangecheck(addr, nbytes, chan)) {
+ if (dma_bounce[chan] == 0)
+ dma_bounce[chan] =
+ /*(caddr_t)malloc(MAXDMASZ, M_TEMP, M_WAITOK);*/
+ (caddr_t) isaphysmem + NBPG*chan;
+ bounced[chan] = 1;
+ newaddr = dma_bounce[chan];
+ *(int *) newaddr = 0; /* XXX */
/* copy bounce buffer on write */
- if (!read) {
+ if ((flags & B_READ) == 0)
bcopy(addr, newaddr, nbytes);
- bounced[chan] = 0;
- } else
- bounced[chan] = addr;
addr = newaddr;
}
@@ -185,10 +93,10 @@ at_dma(read, addr, nbytes, chan)
* byte mode channels.
*/
/* set dma channel mode, and reset address ff */
- if (read)
- outb(DMA1_MODE, DMA37MD_SINGLE|DMA37MD_WRITE|chan);
+ if (flags & B_READ)
+ outb(DMA1_MODE, chan | DMA37MD_SINGLE | DMA37MD_WRITE);
else
- outb(DMA1_MODE, DMA37MD_SINGLE|DMA37MD_READ|chan);
+ outb(DMA1_MODE, chan | DMA37MD_SINGLE | DMA37MD_READ);
outb(DMA1_FFC, 0);
/* send start address */
@@ -202,17 +110,17 @@ at_dma(read, addr, nbytes, chan)
outb(waport + 1, nbytes>>8);
/* unmask channel */
- outb(DMA1_SMSK, DMA37SM_CLEAR | chan);
+ outb(DMA1_SMSK, chan | DMA37SM_CLEAR);
} else {
/*
* Program one of DMA channels 4..7. These are
* word mode channels.
*/
/* set dma channel mode, and reset address ff */
- if (read)
- outb(DMA2_MODE, DMA37MD_SINGLE|DMA37MD_WRITE|(chan&3));
+ if (flags & B_READ)
+ outb(DMA2_MODE, (chan & 3) | DMA37MD_SINGLE | DMA37MD_WRITE);
else
- outb(DMA2_MODE, DMA37MD_SINGLE|DMA37MD_READ|(chan&3));
+ outb(DMA2_MODE, (chan & 3) | DMA37MD_SINGLE | DMA37MD_READ);
outb(DMA2_FFC, 0);
/* send start address */
@@ -227,21 +135,18 @@ at_dma(read, addr, nbytes, chan)
outb(waport + 2, nbytes>>8);
/* unmask channel */
- outb(DMA2_SMSK, DMA37SM_CLEAR | (chan & 3));
+ outb(DMA2_SMSK, (chan & 3) | DMA37SM_CLEAR);
}
}
-/*
- * Abort a DMA request, clearing the bounce buffer, if any.
- */
void
-at_dma_abort(chan)
+isa_dmaabort(chan)
int chan;
{
#ifdef DIAGNOSTIC
- if (chan > 7 || chan < 0)
- panic("at_dma_abort: impossible request");
+ if (chan < 0 || chan > 7)
+ panic("isa_dmaabort: impossible request");
#endif
bounced[chan] = 0;
@@ -253,19 +158,18 @@ at_dma_abort(chan)
outb(DMA2_SMSK, DMA37SM_SET | (chan & 3));
}
-/*
- * End a DMA request, copying data from the bounce buffer, if any,
- * when reading.
- */
void
-at_dma_terminate(chan)
- unsigned chan;
+isa_dmadone(flags, addr, nbytes, chan)
+ int flags;
+ caddr_t addr;
+ vm_size_t nbytes;
+ int chan;
{
u_char tc;
#ifdef DIAGNOSTIC
- if (chan > 7 || chan < 0)
- panic("at_dma_terminate: impossible request");
+ if (chan < 0 || chan > 7)
+ panic("isa_dmadone: impossible request");
#endif
/* check that the terminal count was reached */
@@ -276,10 +180,10 @@ at_dma_terminate(chan)
if (tc == 0)
/* XXX probably should panic or something */
log(LOG_ERR, "dma channel %d not finished\n", chan);
-
+
/* copy bounce buffer on read */
if (bounced[chan]) {
- bcopy(bouncebuf[chan], bounced[chan], bouncesize[chan]);
+ bcopy(dma_bounce[chan], addr, nbytes);
bounced[chan] = 0;
}
@@ -297,20 +201,20 @@ at_dma_terminate(chan)
* Return true if special handling needed.
*/
int
-at_dma_rangecheck(va, length, chan)
+isa_dmarangecheck(va, length, chan)
vm_offset_t va;
u_long length;
int chan;
{
vm_offset_t phys, priorpage = 0, endva;
- u_int dma_pgmsk = (chan&4) ? ~(128*1024-1) : ~(64*1024-1);
+ u_int dma_pgmsk = (chan & 4) ? ~(128*1024-1) : ~(64*1024-1);
endva = round_page(va + length);
for (; va < endva ; va += NBPG) {
phys = trunc_page(pmap_extract(pmap_kernel(), va));
if (phys == 0)
- panic("at_dma_rangecheck: no physical page present");
- if (phys >= (1<<24))
+ panic("isa_dmacheck: no physical page present");
+ if (phys >= (1<<24))
return 1;
if (priorpage) {
if (priorpage + NBPG != phys)
@@ -323,3 +227,45 @@ at_dma_rangecheck(va, length, chan)
}
return 0;
}
+
+/* head of queue waiting for physmem to become available */
+struct buf isa_physmemq;
+
+/* blocked waiting for resource to become free for exclusive use */
+static isaphysmemflag;
+/* if waited for and call requested when free (B_CALL) */
+static void (*isaphysmemunblock)(); /* needs to be a list */
+
+/*
+ * Allocate contiguous physical memory for transfer, returning
+ * a *virtual* address to region. May block waiting for resource.
+ * (assumed to be called at splbio())
+ */
+caddr_t
+isa_allocphysmem(caddr_t va, unsigned length, void (*func)()) {
+
+ isaphysmemunblock = func;
+ while (isaphysmemflag & B_BUSY) {
+ isaphysmemflag |= B_WANTED;
+ sleep((caddr_t)&isaphysmemflag, PRIBIO);
+ }
+ isaphysmemflag |= B_BUSY;
+
+ return((caddr_t)isaphysmem);
+}
+
+/*
+ * Free contiguous physical memory used for transfer.
+ * (assumed to be called at splbio())
+ */
+void
+isa_freephysmem(caddr_t va, unsigned length) {
+
+ isaphysmemflag &= ~B_BUSY;
+ if (isaphysmemflag & B_WANTED) {
+ isaphysmemflag &= B_WANTED;
+ wakeup((caddr_t)&isaphysmemflag);
+ if (isaphysmemunblock)
+ (*isaphysmemunblock)();
+ }
+}
diff --git a/sys/dev/isa/isadmareg.h b/sys/dev/isa/isadmareg.h
new file mode 100644
index 00000000000..97c0d99cdab
--- /dev/null
+++ b/sys/dev/isa/isadmareg.h
@@ -0,0 +1,19 @@
+#include <i386/isa/ic/i8237.h>
+
+/*
+ * Register definitions for DMA controller 1 (channels 0..3):
+ */
+#define DMA1_CHN(c) (IO_DMA1 + 1*(2*(c))) /* addr reg for channel c */
+#define DMA1_SR (IO_DMA1 + 1*8) /* status register */
+#define DMA1_SMSK (IO_DMA1 + 1*10) /* single mask register */
+#define DMA1_MODE (IO_DMA1 + 1*11) /* mode register */
+#define DMA1_FFC (IO_DMA1 + 1*12) /* clear first/last FF */
+
+/*
+ * Register definitions for DMA controller 2 (channels 4..7):
+ */
+#define DMA2_CHN(c) (IO_DMA2 + 2*(2*(c))) /* addr reg for channel c */
+#define DMA2_SR (IO_DMA2 + 2*8) /* status register */
+#define DMA2_SMSK (IO_DMA2 + 2*10) /* single mask register */
+#define DMA2_MODE (IO_DMA2 + 2*11) /* mode register */
+#define DMA2_FFC (IO_DMA2 + 2*12) /* clear first/last FF */
diff --git a/sys/dev/isa/isadmavar.h b/sys/dev/isa/isadmavar.h
new file mode 100644
index 00000000000..2d9871a7646
--- /dev/null
+++ b/sys/dev/isa/isadmavar.h
@@ -0,0 +1,4 @@
+void isa_dmacascade __P((int));
+void isa_dmastart __P((int, caddr_t, vm_size_t, int));
+void isa_dmaabort __P((int));
+void isa_dmadone __P((int, caddr_t, vm_size_t, int));
diff --git a/sys/dev/isa/sb.c b/sys/dev/isa/sb.c
index 54344e15f7c..c2c7df84e9e 100644
--- a/sys/dev/isa/sb.c
+++ b/sys/dev/isa/sb.c
@@ -30,7 +30,7 @@
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
- * $Id: sb.c,v 1.7 1994/04/07 06:51:10 mycroft Exp $
+ * $Id: sb.c,v 1.8 1994/04/22 22:59:00 mycroft Exp $
*/
#include <sys/param.h>
@@ -45,6 +45,7 @@
#include <i386/isa/isa.h>
#include <i386/isa/isavar.h>
+#include <i386/isa/dmavar.h>
#include <i386/isa/icu.h>
#include "sbreg.h"
diff --git a/sys/dev/isa/wt.c b/sys/dev/isa/wt.c
index 7976586c0cd..3d485eb14dc 100644
--- a/sys/dev/isa/wt.c
+++ b/sys/dev/isa/wt.c
@@ -16,7 +16,7 @@
* This driver is derived from the old 386bsd Wangtek streamer tape driver,
* made by Robert Baron at CMU, based on Intel sources.
*
- * $Id: wt.c,v 1.12 1994/04/21 00:41:52 mycroft Exp $
+ * $Id: wt.c,v 1.13 1994/04/22 22:59:02 mycroft Exp $
*/
/*
@@ -65,6 +65,7 @@
#include <machine/pio.h>
#include <i386/isa/isavar.h>
+#include <i386/isa/dmavar.h>
#include <i386/isa/wtreg.h>
/*