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authormaxv <maxv@NetBSD.org>2018-01-05 08:04:20 +0000
committermaxv <maxv@NetBSD.org>2018-01-05 08:04:20 +0000
commit8964449a7e73dcb94f202a557f97db8ffdd63dde (patch)
treead1e6f8cfa746d85c9fd5afa0b988a48dda1d4c0 /sys/dev
parent501b79b2c63ee7a2b0c4f11470ec317a910918aa (diff)
Add a __HAVE_PCPU_AREA option, enabled by default on native amd64 but not
Xen. With this option, the CPU structures that must always be present in the CPU's page tables are moved on L4 slot 384, which means address 0xffffc00000000000. A new pcpu_area structure is defined. It contains shared structures (IDT, LDT), and then an array of pcpu_entry structures, indexed by cpu_index(ci). Theoretically the LDT should be in the array, but this will be done later. During the boot procedure, cpu0 calls pmap_init_pcpu, which creates a page tree that is able to map the pcpu_area structure entirely. cpu0 then immediately maps the shared structures. Later, every CPU goes through cpu_pcpuarea_init, which allocates physical pages and kenters the relevant pcpu_entry to them. Finally, each pointer is replaced to point to pcpuarea. The point of this change is to make sure that the structures that must always be present in the page tables have their own L4 slot. Until now their L4 slot was that of pmap_kernel, and making a distinction between what must be mapped and what does not need to be was complicated. Even in the non-speculative-bug case this change makes some sense: there are several x86 instructions that leak the addresses of the CPU structures, and putting these structures inside pmap_kernel actually offered a way to compute the address of the kernel heap - which would have made ASLR on it plainly useless, had we implemented that. Note that, for now, pcpuarea does not contain rsp0. Unfortunately this change adds many #ifdefs, and makes the code harder to understand. There is also some duplication, but that will be solved later.
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