diff options
| author | dyoung <dyoung@NetBSD.org> | 2006-08-31 19:24:37 +0000 |
|---|---|---|
| committer | dyoung <dyoung@NetBSD.org> | 2006-08-31 19:24:37 +0000 |
| commit | 8cd106d3d2fa257141d908b543155aa4e5938692 (patch) | |
| tree | d7430772384db6b6ede8872fe97e86f8885d978d /sys/dev | |
| parent | a714ccc7c214e4e62dac103fb1d9a2c196c0a73b (diff) | |
Per discussion on tech-kern and tech-userlevel, move the bit-twiddling
macros, __BIT, __BITS, SHIFTIN, SHIFTOUT, and __arraycount() from
lib/libkern/libkern.h to sys/cdefs.h. Add a __-prefix to SHIFTIN
and SHIFTOUT, and add a manual page for the bit-twiddling macros,
bits(3).
Make the __BIT and __BITS macros "widthless," as best I can, by
changing their type to uintmax_t from uint32_t. XXX The manual
page lags this change by a bit.
Define __PRIxBIT and __PRIxBITS printf(3) format strings.
Diffstat (limited to 'sys/dev')
| -rw-r--r-- | sys/dev/ic/atw.c | 193 | ||||
| -rw-r--r-- | sys/dev/ic/atwreg.h | 128 | ||||
| -rw-r--r-- | sys/dev/ic/atwvar.h | 4 | ||||
| -rw-r--r-- | sys/dev/ic/max2820reg.h | 42 | ||||
| -rw-r--r-- | sys/dev/ic/rtw.c | 68 | ||||
| -rw-r--r-- | sys/dev/ic/rtwphy.c | 28 | ||||
| -rw-r--r-- | sys/dev/ic/rtwphyio.c | 66 | ||||
| -rw-r--r-- | sys/dev/ic/rtwreg.h | 160 | ||||
| -rw-r--r-- | sys/dev/ic/sa2400reg.h | 38 | ||||
| -rw-r--r-- | sys/dev/ic/si4136reg.h | 8 |
10 files changed, 368 insertions, 367 deletions
diff --git a/sys/dev/ic/atw.c b/sys/dev/ic/atw.c index a4012ebec7b..421a5cc60f9 100644 --- a/sys/dev/ic/atw.c +++ b/sys/dev/ic/atw.c @@ -1,4 +1,4 @@ -/* $NetBSD: atw.c,v 1.118 2006/08/17 17:11:27 christos Exp $ */ +/* $NetBSD: atw.c,v 1.119 2006/08/31 19:24:37 dyoung Exp $ */ /*- * Copyright (c) 1998, 1999, 2000, 2002, 2003, 2004 The NetBSD Foundation, Inc. @@ -41,7 +41,7 @@ */ #include <sys/cdefs.h> -__KERNEL_RCSID(0, "$NetBSD: atw.c,v 1.118 2006/08/17 17:11:27 christos Exp $"); +__KERNEL_RCSID(0, "$NetBSD: atw.c,v 1.119 2006/08/31 19:24:37 dyoung Exp $"); #include "bpfilter.h" @@ -414,8 +414,9 @@ atw_read_srom(struct atw_softc *sc) sd.sd_chip = C46; break; default: - printf("%s: unknown SROM type %d\n", sc->sc_dev.dv_xname, - SHIFTOUT(test0, ATW_TEST0_EPTYP_MASK)); + printf("%s: unknown SROM type %d\n", + sc->sc_dev.dv_xname, + __SHIFTOUT(test0, ATW_TEST0_EPTYP_MASK)); return -1; } @@ -657,10 +658,10 @@ atw_attach(struct atw_softc *sc) if (atw_read_srom(sc) == -1) return; - sc->sc_rftype = SHIFTOUT(sc->sc_srom[ATW_SR_CSR20], + sc->sc_rftype = __SHIFTOUT(sc->sc_srom[ATW_SR_CSR20], ATW_SR_RFTYPE_MASK); - sc->sc_bbptype = SHIFTOUT(sc->sc_srom[ATW_SR_CSR20], + sc->sc_bbptype = __SHIFTOUT(sc->sc_srom[ATW_SR_CSR20], ATW_SR_BBPTYPE_MASK); if (sc->sc_rftype >= __arraycount(type_strings)) { @@ -679,7 +680,7 @@ atw_attach(struct atw_softc *sc) * MARVEL. My bug, or theirs? */ - reg = SHIFTIN(sc->sc_rftype, ATW_SYNCTL_RFTYPE_MASK); + reg = __SHIFTIN(sc->sc_rftype, ATW_SYNCTL_RFTYPE_MASK); switch (sc->sc_rftype) { case ATW_RFTYPE_INTERSIL: @@ -695,7 +696,7 @@ atw_attach(struct atw_softc *sc) sc->sc_synctl_rd = reg | ATW_SYNCTL_RD; sc->sc_synctl_wr = reg | ATW_SYNCTL_WR; - reg = SHIFTIN(sc->sc_bbptype, ATW_BBPCTL_TYPE_MASK); + reg = __SHIFTIN(sc->sc_bbptype, ATW_BBPCTL_TYPE_MASK); switch (sc->sc_bbptype) { case ATW_BBPTYPE_INTERSIL: @@ -728,22 +729,22 @@ atw_attach(struct atw_softc *sc) htole16(sc->sc_srom[ATW_SR_MAC01]), htole16(sc->sc_srom[ATW_SR_MAC10]))); - srom_major = SHIFTOUT(sc->sc_srom[ATW_SR_FORMAT_VERSION], + srom_major = __SHIFTOUT(sc->sc_srom[ATW_SR_FORMAT_VERSION], ATW_SR_MAJOR_MASK); if (srom_major < 2) sc->sc_rf3000_options1 = 0; else if (sc->sc_rev == ATW_REVISION_BA) { sc->sc_rf3000_options1 = - SHIFTOUT(sc->sc_srom[ATW_SR_CR28_CR03], + __SHIFTOUT(sc->sc_srom[ATW_SR_CR28_CR03], ATW_SR_CR28_MASK); } else sc->sc_rf3000_options1 = 0; - sc->sc_rf3000_options2 = SHIFTOUT(sc->sc_srom[ATW_SR_CTRY_CR29], + sc->sc_rf3000_options2 = __SHIFTOUT(sc->sc_srom[ATW_SR_CTRY_CR29], ATW_SR_CR29_MASK); - country_code = SHIFTOUT(sc->sc_srom[ATW_SR_CTRY_CR29], + country_code = __SHIFTOUT(sc->sc_srom[ATW_SR_CTRY_CR29], ATW_SR_CTRY_MASK); #define ADD_CHANNEL(_ic, _chan) do { \ @@ -782,13 +783,13 @@ atw_attach(struct atw_softc *sc) /* Read the MAC address. */ reg = ATW_READ(sc, ATW_PAR0); - ic->ic_myaddr[0] = SHIFTOUT(reg, ATW_PAR0_PAB0_MASK); - ic->ic_myaddr[1] = SHIFTOUT(reg, ATW_PAR0_PAB1_MASK); - ic->ic_myaddr[2] = SHIFTOUT(reg, ATW_PAR0_PAB2_MASK); - ic->ic_myaddr[3] = SHIFTOUT(reg, ATW_PAR0_PAB3_MASK); + ic->ic_myaddr[0] = __SHIFTOUT(reg, ATW_PAR0_PAB0_MASK); + ic->ic_myaddr[1] = __SHIFTOUT(reg, ATW_PAR0_PAB1_MASK); + ic->ic_myaddr[2] = __SHIFTOUT(reg, ATW_PAR0_PAB2_MASK); + ic->ic_myaddr[3] = __SHIFTOUT(reg, ATW_PAR0_PAB3_MASK); reg = ATW_READ(sc, ATW_PAR1); - ic->ic_myaddr[4] = SHIFTOUT(reg, ATW_PAR1_PAB4_MASK); - ic->ic_myaddr[5] = SHIFTOUT(reg, ATW_PAR1_PAB5_MASK); + ic->ic_myaddr[4] = __SHIFTOUT(reg, ATW_PAR1_PAB4_MASK); + ic->ic_myaddr[5] = __SHIFTOUT(reg, ATW_PAR1_PAB5_MASK); if (IEEE80211_ADDR_EQ(ic->ic_myaddr, empty_macaddr)) { printf(" could not get mac address, attach failed\n"); @@ -1048,7 +1049,7 @@ atw_wcsr_init(struct atw_softc *sc) wcsr = ATW_READ(sc, ATW_WCSR); wcsr &= ~(ATW_WCSR_BLN_MASK|ATW_WCSR_LSOE|ATW_WCSR_MPRE|ATW_WCSR_LSOE); - wcsr |= SHIFTIN(7, ATW_WCSR_BLN_MASK); + wcsr |= __SHIFTIN(7, ATW_WCSR_BLN_MASK); ATW_WRITE(sc, ATW_WCSR, wcsr); /* XXX resets wake-up status bits */ DPRINTF(sc, ("%s: %s reg[WCSR] = %08x\n", @@ -1075,24 +1076,24 @@ atw_tofs2_init(struct atw_softc *sc) uint32_t tofs2; /* XXX this magic can probably be figured out from the RFMD docs */ #ifndef ATW_REFSLAVE - tofs2 = SHIFTIN(4, ATW_TOFS2_PWR1UP_MASK) | /* 8 ms = 4 * 2 ms */ - SHIFTIN(13, ATW_TOFS2_PWR0PAPE_MASK) | /* 13 us */ - SHIFTIN(8, ATW_TOFS2_PWR1PAPE_MASK) | /* 8 us */ - SHIFTIN(5, ATW_TOFS2_PWR0TRSW_MASK) | /* 5 us */ - SHIFTIN(12, ATW_TOFS2_PWR1TRSW_MASK) | /* 12 us */ - SHIFTIN(13, ATW_TOFS2_PWR0PE2_MASK) | /* 13 us */ - SHIFTIN(4, ATW_TOFS2_PWR1PE2_MASK) | /* 4 us */ - SHIFTIN(5, ATW_TOFS2_PWR0TXPE_MASK); /* 5 us */ + tofs2 = __SHIFTIN(4, ATW_TOFS2_PWR1UP_MASK) | /* 8 ms = 4 * 2 ms */ + __SHIFTIN(13, ATW_TOFS2_PWR0PAPE_MASK) | /* 13 us */ + __SHIFTIN(8, ATW_TOFS2_PWR1PAPE_MASK) | /* 8 us */ + __SHIFTIN(5, ATW_TOFS2_PWR0TRSW_MASK) | /* 5 us */ + __SHIFTIN(12, ATW_TOFS2_PWR1TRSW_MASK) | /* 12 us */ + __SHIFTIN(13, ATW_TOFS2_PWR0PE2_MASK) | /* 13 us */ + __SHIFTIN(4, ATW_TOFS2_PWR1PE2_MASK) | /* 4 us */ + __SHIFTIN(5, ATW_TOFS2_PWR0TXPE_MASK); /* 5 us */ #else /* XXX new magic from reference driver source */ - tofs2 = SHIFTIN(8, ATW_TOFS2_PWR1UP_MASK) | /* 8 ms = 4 * 2 ms */ - SHIFTIN(8, ATW_TOFS2_PWR0PAPE_MASK) | /* 8 us */ - SHIFTIN(1, ATW_TOFS2_PWR1PAPE_MASK) | /* 1 us */ - SHIFTIN(5, ATW_TOFS2_PWR0TRSW_MASK) | /* 5 us */ - SHIFTIN(12, ATW_TOFS2_PWR1TRSW_MASK) | /* 12 us */ - SHIFTIN(13, ATW_TOFS2_PWR0PE2_MASK) | /* 13 us */ - SHIFTIN(1, ATW_TOFS2_PWR1PE2_MASK) | /* 1 us */ - SHIFTIN(8, ATW_TOFS2_PWR0TXPE_MASK); /* 8 us */ + tofs2 = __SHIFTIN(8, ATW_TOFS2_PWR1UP_MASK) | /* 8 ms = 4 * 2 ms */ + __SHIFTIN(8, ATW_TOFS2_PWR0PAPE_MASK) | /* 8 us */ + __SHIFTIN(1, ATW_TOFS2_PWR1PAPE_MASK) | /* 1 us */ + __SHIFTIN(5, ATW_TOFS2_PWR0TRSW_MASK) | /* 5 us */ + __SHIFTIN(12, ATW_TOFS2_PWR1TRSW_MASK) | /* 12 us */ + __SHIFTIN(13, ATW_TOFS2_PWR0PE2_MASK) | /* 13 us */ + __SHIFTIN(1, ATW_TOFS2_PWR1PE2_MASK) | /* 1 us */ + __SHIFTIN(8, ATW_TOFS2_PWR0TXPE_MASK); /* 8 us */ #endif ATW_WRITE(sc, ATW_TOFS2, tofs2); } @@ -1106,8 +1107,8 @@ atw_nar_init(struct atw_softc *sc) static void atw_txlmt_init(struct atw_softc *sc) { - ATW_WRITE(sc, ATW_TXLMT, SHIFTIN(512, ATW_TXLMT_MTMLT_MASK) | - SHIFTIN(1, ATW_TXLMT_SRTYLIM_MASK)); + ATW_WRITE(sc, ATW_TXLMT, __SHIFTIN(512, ATW_TXLMT_MTMLT_MASK) | + __SHIFTIN(1, ATW_TXLMT_SRTYLIM_MASK)); } static void @@ -1118,7 +1119,7 @@ atw_test1_init(struct atw_softc *sc) test1 = ATW_READ(sc, ATW_TEST1); test1 &= ~(ATW_TEST1_DBGREAD_MASK|ATW_TEST1_CONTROL); /* XXX magic 0x1 */ - test1 |= SHIFTIN(0x1, ATW_TEST1_DBGREAD_MASK) | ATW_TEST1_CONTROL; + test1 |= __SHIFTIN(0x1, ATW_TEST1_DBGREAD_MASK) | ATW_TEST1_CONTROL; ATW_WRITE(sc, ATW_TEST1, test1); } @@ -1141,7 +1142,7 @@ atw_cfp_init(struct atw_softc *sc) cfpp = ATW_READ(sc, ATW_CFPP); cfpp &= ~ATW_CFPP_CFPMD; - cfpp |= SHIFTIN(16, ATW_CFPP_CFPMD); + cfpp |= __SHIFTIN(16, ATW_CFPP_CFPMD); ATW_WRITE(sc, ATW_CFPP, cfpp); } @@ -1157,7 +1158,7 @@ atw_tofs0_init(struct atw_softc *sc) * these values. These values are also the power-on default. */ ATW_WRITE(sc, ATW_TOFS0, - SHIFTIN(22, ATW_TOFS0_USCNT_MASK) | + __SHIFTIN(22, ATW_TOFS0_USCNT_MASK) | ATW_TOFS0_TUCNT_MASK /* set all bits in TUCNT */); } @@ -1169,11 +1170,11 @@ atw_ifs_init(struct atw_softc *sc) /* XXX EIFS=0x64, SIFS=110 are used by the reference driver. * Go figure. */ - ifst = SHIFTIN(IEEE80211_DUR_DS_SLOT, ATW_IFST_SLOT_MASK) | - SHIFTIN(22 * 5 /* IEEE80211_DUR_DS_SIFS */ /* # of 22 MHz cycles */, + ifst = __SHIFTIN(IEEE80211_DUR_DS_SLOT, ATW_IFST_SLOT_MASK) | + __SHIFTIN(22 * 5 /* IEEE80211_DUR_DS_SIFS */ /* # of 22 MHz cycles */, ATW_IFST_SIFS_MASK) | - SHIFTIN(IEEE80211_DUR_DS_DIFS, ATW_IFST_DIFS_MASK) | - SHIFTIN(0x64 /* IEEE80211_DUR_DS_EIFS */, ATW_IFST_EIFS_MASK); + __SHIFTIN(IEEE80211_DUR_DS_DIFS, ATW_IFST_DIFS_MASK) | + __SHIFTIN(0x64 /* IEEE80211_DUR_DS_EIFS */, ATW_IFST_EIFS_MASK); ATW_WRITE(sc, ATW_IFST, ifst); } @@ -1187,8 +1188,8 @@ atw_response_times_init(struct atw_softc *sc) * it waits at most SIFS + MART microseconds for the response. * Surely this is not the ACK timeout? */ - ATW_WRITE(sc, ATW_RSPT, SHIFTIN(0xffff, ATW_RSPT_MART_MASK) | - SHIFTIN(0xff, ATW_RSPT_MIRT_MASK)); + ATW_WRITE(sc, ATW_RSPT, __SHIFTIN(0xffff, ATW_RSPT_MART_MASK) | + __SHIFTIN(0xff, ATW_RSPT_MIRT_MASK)); } /* Set up the MMI read/write addresses for the baseband. The Tx/Rx @@ -1269,8 +1270,8 @@ atw_init(struct ifnet *ifp) * * XXX Set transmit power for ATIM, RTS, Beacon. */ - ATW_WRITE(sc, ATW_PLCPHD, SHIFTIN(10, ATW_PLCPHD_SIGNAL_MASK) | - SHIFTIN(0xb0, ATW_PLCPHD_SERVICE_MASK)); + ATW_WRITE(sc, ATW_PLCPHD, __SHIFTIN(10, ATW_PLCPHD_SIGNAL_MASK) | + __SHIFTIN(0xb0, ATW_PLCPHD_SERVICE_MASK)); atw_tofs2_init(sc); @@ -1292,7 +1293,7 @@ atw_init(struct ifnet *ifp) * XXX A frame may only dribble in for 65536us. */ ATW_WRITE(sc, ATW_RMD, - SHIFTIN(1, ATW_RMD_PCNT) | SHIFTIN(0xffff, ATW_RMD_RMRD_MASK)); + __SHIFTIN(1, ATW_RMD_PCNT) | __SHIFTIN(0xffff, ATW_RMD_RMRD_MASK)); atw_response_times_init(sc); @@ -1610,7 +1611,7 @@ atw_si4126_tune(struct atw_softc *sc, u_int chan) * REFDIF This is different from the reference driver, which * always sets SI4126_GAIN to 0. */ - gain = SHIFTIN(((mhz - 374) > 2047) ? 1 : 0, SI4126_GAIN_KP2_MASK); + gain = __SHIFTIN(((mhz - 374) > 2047) ? 1 : 0, SI4126_GAIN_KP2_MASK); atw_si4126_write(sc, SI4126_GAIN, gain); @@ -1649,7 +1650,7 @@ atw_si4126_tune(struct atw_softc *sc, u_int chan) gpio = ATW_READ(sc, ATW_GPIO); gpio &= ~(ATW_GPIO_EN_MASK|ATW_GPIO_O_MASK|ATW_GPIO_I_MASK); - gpio |= SHIFTIN(1, ATW_GPIO_EN_MASK); + gpio |= __SHIFTIN(1, ATW_GPIO_EN_MASK); if ((sc->sc_if.if_flags & IFF_LINK1) != 0 && chan != 14) { /* Set a Prism RF front-end to a special mode for channel 14? @@ -1657,7 +1658,7 @@ atw_si4126_tune(struct atw_softc *sc, u_int chan) * Apparently the SMC2635W needs this, although I don't think * it has a Prism RF. */ - gpio |= SHIFTIN(1, ATW_GPIO_O_MASK); + gpio |= __SHIFTIN(1, ATW_GPIO_O_MASK); } ATW_WRITE(sc, ATW_GPIO, gpio); @@ -1682,7 +1683,7 @@ atw_rf3000_init(struct atw_softc *sc) /* CCA is acquisition sensitive */ rc = atw_rf3000_write(sc, RF3000_CCACTL, - SHIFTIN(RF3000_CCACTL_MODE_BOTH, RF3000_CCACTL_MODE_MASK)); + __SHIFTIN(RF3000_CCACTL_MODE_BOTH, RF3000_CCACTL_MODE_MASK)); if (rc != 0) goto out; @@ -1695,14 +1696,14 @@ atw_rf3000_init(struct atw_softc *sc) /* sensible setting from a binary-only driver */ rc = atw_rf3000_write(sc, RF3000_GAINCTL, - SHIFTIN(0x1d, RF3000_GAINCTL_TXVGC_MASK)); + __SHIFTIN(0x1d, RF3000_GAINCTL_TXVGC_MASK)); if (rc != 0) goto out; /* magic from a binary-only driver */ rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, - SHIFTIN(0x38, RF3000_LOGAINCAL_CAL_MASK)); + __SHIFTIN(0x38, RF3000_LOGAINCAL_CAL_MASK)); if (rc != 0) goto out; @@ -1786,7 +1787,7 @@ atw_rf3000_tune(struct atw_softc *sc, u_int chan) atw_bbp_io_enable(sc, 1); if ((rc = atw_rf3000_write(sc, RF3000_GAINCTL, - SHIFTIN(txpower, RF3000_GAINCTL_TXVGC_MASK))) != 0) + __SHIFTIN(txpower, RF3000_GAINCTL_TXVGC_MASK))) != 0) goto out; if ((rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, lpf_cutoff)) != 0) @@ -1815,7 +1816,7 @@ out: /* set beacon, rts, atim transmit power */ reg = ATW_READ(sc, ATW_PLCPHD); reg &= ~ATW_PLCPHD_SERVICE_MASK; - reg |= SHIFTIN(SHIFTIN(txpower, RF3000_GAINCTL_TXVGC_MASK), + reg |= __SHIFTIN(__SHIFTIN(txpower, RF3000_GAINCTL_TXVGC_MASK), ATW_PLCPHD_SERVICE_MASK); ATW_WRITE(sc, ATW_PLCPHD, reg); DELAY(atw_plcphd_delay); @@ -1835,8 +1836,8 @@ atw_rf3000_write(struct atw_softc *sc, u_int addr, u_int val) int i; reg = sc->sc_bbpctl_wr | - SHIFTIN(val & 0xff, ATW_BBPCTL_DATA_MASK) | - SHIFTIN(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); + __SHIFTIN(val & 0xff, ATW_BBPCTL_DATA_MASK) | + __SHIFTIN(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); for (i = 20000 / atw_pseudo_milli; --i >= 0; ) { ATW_WRITE(sc, ATW_BBPCTL, reg); @@ -1884,7 +1885,7 @@ atw_rf3000_read(struct atw_softc *sc, u_int addr, u_int *val) return ETIMEDOUT; } - reg = sc->sc_bbpctl_rd | SHIFTIN(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); + reg = sc->sc_bbpctl_rd | __SHIFTIN(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); ATW_WRITE(sc, ATW_BBPCTL, reg); @@ -1902,7 +1903,7 @@ atw_rf3000_read(struct atw_softc *sc, u_int addr, u_int *val) return ETIMEDOUT; } if (val != NULL) - *val = SHIFTOUT(reg, ATW_BBPCTL_DATA_MASK); + *val = __SHIFTOUT(reg, ATW_BBPCTL_DATA_MASK); return 0; } #endif /* ATW_BBPDEBUG */ @@ -1920,11 +1921,11 @@ atw_si4126_write(struct atw_softc *sc, u_int addr, u_int val) uint32_t bits, mask, reg; const int nbits = 22; - KASSERT((addr & ~SHIFTOUT_MASK(SI4126_TWI_ADDR_MASK)) == 0); - KASSERT((val & ~SHIFTOUT_MASK(SI4126_TWI_DATA_MASK)) == 0); + KASSERT((addr & ~__SHIFTOUT_MASK(SI4126_TWI_ADDR_MASK)) == 0); + KASSERT((val & ~__SHIFTOUT_MASK(SI4126_TWI_DATA_MASK)) == 0); - bits = SHIFTIN(val, SI4126_TWI_DATA_MASK) | - SHIFTIN(addr, SI4126_TWI_ADDR_MASK); + bits = __SHIFTIN(val, SI4126_TWI_DATA_MASK) | + __SHIFTIN(addr, SI4126_TWI_ADDR_MASK); reg = ATW_SYNRF_SELSYN; /* reference driver: reset Si4126 serial bus to initial @@ -1959,7 +1960,7 @@ atw_si4126_read(struct atw_softc *sc, u_int addr, u_int *val) u_int32_t reg; int i; - KASSERT((addr & ~SHIFTOUT_MASK(SI4126_TWI_ADDR_MASK)) == 0); + KASSERT((addr & ~__SHIFTOUT_MASK(SI4126_TWI_ADDR_MASK)) == 0); for (i = 1000; --i >= 0; ) { if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD|ATW_SYNCTL_WR) == 0) @@ -1973,7 +1974,7 @@ atw_si4126_read(struct atw_softc *sc, u_int addr, u_int *val) return ETIMEDOUT; } - reg = sc->sc_synctl_rd | SHIFTIN(addr, ATW_SYNCTL_DATA_MASK); + reg = sc->sc_synctl_rd | __SHIFTIN(addr, ATW_SYNCTL_DATA_MASK); ATW_WRITE(sc, ATW_SYNCTL, reg); @@ -1991,7 +1992,7 @@ atw_si4126_read(struct atw_softc *sc, u_int addr, u_int *val) return ETIMEDOUT; } if (val != NULL) - *val = SHIFTOUT(ATW_READ(sc, ATW_SYNCTL), + *val = __SHIFTOUT(ATW_READ(sc, ATW_SYNCTL), ATW_SYNCTL_DATA_MASK); return 0; } @@ -2087,16 +2088,16 @@ atw_write_bssid(struct atw_softc *sc) bssid = ic->ic_bss->ni_bssid; ATW_WRITE(sc, ATW_BSSID0, - SHIFTIN(bssid[0], ATW_BSSID0_BSSIDB0_MASK) | - SHIFTIN(bssid[1], ATW_BSSID0_BSSIDB1_MASK) | - SHIFTIN(bssid[2], ATW_BSSID0_BSSIDB2_MASK) | - SHIFTIN(bssid[3], ATW_BSSID0_BSSIDB3_MASK)); + __SHIFTIN(bssid[0], ATW_BSSID0_BSSIDB0_MASK) | + __SHIFTIN(bssid[1], ATW_BSSID0_BSSIDB1_MASK) | + __SHIFTIN(bssid[2], ATW_BSSID0_BSSIDB2_MASK) | + __SHIFTIN(bssid[3], ATW_BSSID0_BSSIDB3_MASK)); ATW_WRITE(sc, ATW_ABDA1, (ATW_READ(sc, ATW_ABDA1) & ~(ATW_ABDA1_BSSIDB4_MASK|ATW_ABDA1_BSSIDB5_MASK)) | - SHIFTIN(bssid[4], ATW_ABDA1_BSSIDB4_MASK) | - SHIFTIN(bssid[5], ATW_ABDA1_BSSIDB5_MASK)); + __SHIFTIN(bssid[4], ATW_ABDA1_BSSIDB4_MASK) | + __SHIFTIN(bssid[5], ATW_ABDA1_BSSIDB5_MASK)); DPRINTF(sc, ("%s: BSSID %s -> ", sc->sc_dev.dv_xname, ether_sprintf(sc->sc_bssid))); @@ -2124,11 +2125,11 @@ atw_write_sram(struct atw_softc *sc, u_int ofs, u_int8_t *buf, u_int buflen) for (i = 0; i < buflen; i += 2) { ATW_WRITE(sc, ATW_WEPCTL, ATW_WEPCTL_WR | - SHIFTIN((ofs + i) / 2, ATW_WEPCTL_TBLADD_MASK)); + __SHIFTIN((ofs + i) / 2, ATW_WEPCTL_TBLADD_MASK)); DELAY(atw_writewep_delay); ATW_WRITE(sc, ATW_WESK, - SHIFTIN((ptr[i + 1] << 8) | ptr[i], ATW_WESK_DATA_MASK)); + __SHIFTIN((ptr[i + 1] << 8) | ptr[i], ATW_WESK_DATA_MASK)); DELAY(atw_writewep_delay); } ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); /* restore WEP condition */ @@ -2245,7 +2246,7 @@ atw_write_wep(struct atw_softc *sc) reg = ATW_READ(sc, ATW_MACTEST); reg |= ATW_MACTEST_MMI_USETXCLK | ATW_MACTEST_FORCE_KEYID; reg &= ~ATW_MACTEST_KEYID_MASK; - reg |= SHIFTIN(ic->ic_def_txkey, ATW_MACTEST_KEYID_MASK); + reg |= __SHIFTIN(ic->ic_def_txkey, ATW_MACTEST_KEYID_MASK); ATW_WRITE(sc, ATW_MACTEST, reg); if ((ic->ic_flags & IEEE80211_F_PRIVACY) != 0) @@ -2397,14 +2398,14 @@ atw_start_beacon(struct atw_softc *sc, int start) /* set listen interval * XXX do software units agree w/ hardware? */ - bpli = SHIFTIN(ic->ic_bss->ni_intval, ATW_BPLI_BP_MASK) | - SHIFTIN(ic->ic_lintval / ic->ic_bss->ni_intval, ATW_BPLI_LI_MASK); + bpli = __SHIFTIN(ic->ic_bss->ni_intval, ATW_BPLI_BP_MASK) | + __SHIFTIN(ic->ic_lintval / ic->ic_bss->ni_intval, ATW_BPLI_LI_MASK); chan = ieee80211_chan2ieee(ic, ic->ic_curchan); - bcnt |= SHIFTIN(len, ATW_BCNT_BCNT_MASK); - cap0 |= SHIFTIN(chan, ATW_CAP0_CHN_MASK); - cap1 |= SHIFTIN(capinfo, ATW_CAP1_CAPI_MASK); + bcnt |= __SHIFTIN(len, ATW_BCNT_BCNT_MASK); + cap0 |= __SHIFTIN(chan, ATW_CAP0_CHN_MASK); + cap1 |= __SHIFTIN(capinfo, ATW_CAP1_CAPI_MASK); ATW_WRITE(sc, ATW_BCNT, bcnt); ATW_WRITE(sc, ATW_BPLI, bpli); @@ -2497,9 +2498,9 @@ atw_predict_beacon(struct atw_softc *sc) tbtt = past_even + ival * 10; ATW_WRITE(sc, ATW_TOFS1, - SHIFTIN(1, ATW_TOFS1_TSFTOFSR_MASK) | - SHIFTIN(TBTTOFS, ATW_TOFS1_TBTTOFS_MASK) | - SHIFTIN(SHIFTOUT(tbtt - TBTTOFS * IEEE80211_DUR_TU, + __SHIFTIN(1, ATW_TOFS1_TSFTOFSR_MASK) | + __SHIFTIN(TBTTOFS, ATW_TOFS1_TBTTOFS_MASK) | + __SHIFTIN(__SHIFTOUT(tbtt - TBTTOFS * IEEE80211_DUR_TU, ATW_TBTTPRE_MASK), ATW_TOFS1_TBTTPRE_MASK)); #undef TBTTOFS } @@ -2560,8 +2561,8 @@ atw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) * XXX do software units agree w/ hardware? */ ATW_WRITE(sc, ATW_BPLI, - SHIFTIN(ic->ic_bss->ni_intval, ATW_BPLI_BP_MASK) | - SHIFTIN(ic->ic_lintval / ic->ic_bss->ni_intval, + __SHIFTIN(ic->ic_bss->ni_intval, ATW_BPLI_BP_MASK) | + __SHIFTIN(ic->ic_lintval / ic->ic_bss->ni_intval, ATW_BPLI_LI_MASK)); DPRINTF(sc, ("%s: reg[ATW_BPLI] = %08x\n", sc->sc_dev.dv_xname, @@ -3004,7 +3005,7 @@ atw_idle(struct atw_softc *sc, u_int32_t bits) (test0 & ATW_TEST0_TS_MASK) != ATW_TEST0_TS_STOPPED) { printf("%s: transmit process not idle [%s]\n", sc->sc_dev.dv_xname, - atw_tx_state[SHIFTOUT(test0, ATW_TEST0_TS_MASK)]); + atw_tx_state[__SHIFTOUT(test0, ATW_TEST0_TS_MASK)]); printf("%s: bits %08x test0 %08x stsr %08x\n", sc->sc_dev.dv_xname, bits, test0, stsr); } @@ -3013,7 +3014,7 @@ atw_idle(struct atw_softc *sc, u_int32_t bits) (test0 & ATW_TEST0_RS_MASK) != ATW_TEST0_RS_STOPPED) { DPRINTF2(sc, ("%s: receive process not idle [%s]\n", sc->sc_dev.dv_xname, - atw_rx_state[SHIFTOUT(test0, ATW_TEST0_RS_MASK)])); + atw_rx_state[__SHIFTOUT(test0, ATW_TEST0_RS_MASK)])); DPRINTF2(sc, ("%s: bits %08x test0 %08x stsr %08x\n", sc->sc_dev.dv_xname, bits, test0, stsr)); } @@ -3085,7 +3086,7 @@ atw_rxintr(struct atw_softc *sc) rxstat = le32toh(sc->sc_rxdescs[i].ar_stat); rssi0 = le32toh(sc->sc_rxdescs[i].ar_rssi); - rate0 = SHIFTOUT(rxstat, ATW_RXSTAT_RXDR_MASK); + rate0 = __SHIFTOUT(rxstat, ATW_RXSTAT_RXDR_MASK); if (rxstat & ATW_RXSTAT_OWN) break; /* We have processed all receive buffers. */ @@ -3147,7 +3148,7 @@ atw_rxintr(struct atw_softc *sc) * No errors; receive the packet. Note the ADM8211 * includes the CRC in promiscuous mode. */ - len = SHIFTOUT(rxstat, ATW_RXSTAT_FL_MASK); + len = __SHIFTOUT(rxstat, ATW_RXSTAT_FL_MASK); /* * Allocate a new mbuf cluster. If that fails, we are @@ -3299,7 +3300,7 @@ atw_txintr(struct atw_softc *sc) txstat_buf, sizeof(txstat_buf)); printf("%s: txstat %s %d\n", sc->sc_dev.dv_xname, txstat_buf, - SHIFTOUT(txstat, ATW_TXSTAT_ARC_MASK)); + __SHIFTOUT(txstat, ATW_TXSTAT_ARC_MASK)); } /* @@ -3319,7 +3320,7 @@ atw_txintr(struct atw_softc *sc) if ((txstat & ATW_TXSTAT_ES) == 0) ifp->if_collisions += - SHIFTOUT(txstat, ATW_TXSTAT_ARC_MASK); + __SHIFTOUT(txstat, ATW_TXSTAT_ARC_MASK); else ifp->if_oerrors++; @@ -3689,11 +3690,11 @@ atw_start(struct ifnet *ifp) /* XXX arbitrary retry limit; 8 because I have seen it in * use already and maybe 0 means "no tries" ! */ - ctl = htole32(SHIFTIN(8, ATW_TXCTL_TL_MASK)); + ctl = htole32(__SHIFTIN(8, ATW_TXCTL_TL_MASK)); DPRINTF2(sc, ("%s: TXDR <- max(10, %d)\n", sc->sc_dev.dv_xname, rate * 5)); - ctl |= htole32(SHIFTIN(MAX(10, rate * 5), ATW_TXCTL_TXDR_MASK)); + ctl |= htole32(__SHIFTIN(MAX(10, rate * 5), ATW_TXCTL_TXDR_MASK)); /* * Initialize the transmit descriptors. @@ -3713,7 +3714,7 @@ atw_start(struct ifnet *ifp) txd->at_buf1 = htole32(dmamap->dm_segs[seg].ds_addr); txd->at_flags = - htole32(SHIFTIN(dmamap->dm_segs[seg].ds_len, + htole32(__SHIFTIN(dmamap->dm_segs[seg].ds_len, ATW_TXFLAG_TBS1_MASK)) | ((nexttx == (ATW_NTXDESC - 1)) ? htole32(ATW_TXFLAG_TER) : 0); diff --git a/sys/dev/ic/atwreg.h b/sys/dev/ic/atwreg.h index 0ac9b32bdd9..01bb8a7154d 100644 --- a/sys/dev/ic/atwreg.h +++ b/sys/dev/ic/atwreg.h @@ -1,4 +1,4 @@ -/* $NetBSD: atwreg.h,v 1.14 2006/03/08 08:26:50 dyoung Exp $ */ +/* $NetBSD: atwreg.h,v 1.15 2006/08/31 19:24:37 dyoung Exp $ */ /* * Copyright (c) 2003 The NetBSD Foundation, Inc. All rights reserved. @@ -151,19 +151,19 @@ #define ATW_PAR_CAL_MASK __BITS(14, 15) /* cache alignment */ #define ATW_PAR_CAL_PBL 0x0 /* min(8 DW, PBL) */ -#define ATW_PAR_CAL_8DW SHIFTIN(0x1, ATW_PAR_CAL_MASK) +#define ATW_PAR_CAL_8DW __SHIFTIN(0x1, ATW_PAR_CAL_MASK) /* min(16 DW, PBL) */ -#define ATW_PAR_CAL_16DW SHIFTIN(0x2, ATW_PAR_CAL_MASK) +#define ATW_PAR_CAL_16DW __SHIFTIN(0x2, ATW_PAR_CAL_MASK) /* min(32 DW, PBL) */ -#define ATW_PAR_CAL_32DW SHIFTIN(0x3, ATW_PAR_CAL_MASK) +#define ATW_PAR_CAL_32DW __SHIFTIN(0x3, ATW_PAR_CAL_MASK) #define ATW_PAR_PBL_MASK __BITS(8, 13) /* programmable burst length */ #define ATW_PAR_PBL_UNLIMITED 0x0 -#define ATW_PAR_PBL_1DW SHIFTIN(0x1, ATW_PAR_PBL_MASK) -#define ATW_PAR_PBL_2DW SHIFTIN(0x2, ATW_PAR_PBL_MASK) -#define ATW_PAR_PBL_4DW SHIFTIN(0x4, ATW_PAR_PBL_MASK) -#define ATW_PAR_PBL_8DW SHIFTIN(0x8, ATW_PAR_PBL_MASK) -#define ATW_PAR_PBL_16DW SHIFTIN(0x16, ATW_PAR_PBL_MASK) -#define ATW_PAR_PBL_32DW SHIFTIN(0x32, ATW_PAR_PBL_MASK) +#define ATW_PAR_PBL_1DW __SHIFTIN(0x1, ATW_PAR_PBL_MASK) +#define ATW_PAR_PBL_2DW __SHIFTIN(0x2, ATW_PAR_PBL_MASK) +#define ATW_PAR_PBL_4DW __SHIFTIN(0x4, ATW_PAR_PBL_MASK) +#define ATW_PAR_PBL_8DW __SHIFTIN(0x8, ATW_PAR_PBL_MASK) +#define ATW_PAR_PBL_16DW __SHIFTIN(0x16, ATW_PAR_PBL_MASK) +#define ATW_PAR_PBL_32DW __SHIFTIN(0x32, ATW_PAR_PBL_MASK) #define ATW_PAR_BLE __BIT(7) /* big/little endian selection */ #define ATW_PAR_DSL_MASK __BITS(2, 6) /* descriptor skip length */ #define ATW_PAR_BAR __BIT(1) /* bus arbitration */ @@ -274,16 +274,16 @@ * TX threshold */ #define ATW_NAR_TR_MASK __BITS(14, 15) /* TX threshold */ -#define ATW_NAR_TR_L64 SHIFTIN(0x0, ATW_NAR_TR_MASK) -#define ATW_NAR_TR_L160 SHIFTIN(0x2, ATW_NAR_TR_MASK) -#define ATW_NAR_TR_L192 SHIFTIN(0x3, ATW_NAR_TR_MASK) -#define ATW_NAR_TR_H96 SHIFTIN(0x0, ATW_NAR_TR_MASK) -#define ATW_NAR_TR_H288 SHIFTIN(0x2, ATW_NAR_TR_MASK) -#define ATW_NAR_TR_H544 SHIFTIN(0x3, ATW_NAR_TR_MASK) +#define ATW_NAR_TR_L64 __SHIFTIN(0x0, ATW_NAR_TR_MASK) +#define ATW_NAR_TR_L160 __SHIFTIN(0x2, ATW_NAR_TR_MASK) +#define ATW_NAR_TR_L192 __SHIFTIN(0x3, ATW_NAR_TR_MASK) +#define ATW_NAR_TR_H96 __SHIFTIN(0x0, ATW_NAR_TR_MASK) +#define ATW_NAR_TR_H288 __SHIFTIN(0x2, ATW_NAR_TR_MASK) +#define ATW_NAR_TR_H544 __SHIFTIN(0x3, ATW_NAR_TR_MASK) #define ATW_NAR_ST __BIT(13) /* start/stop transmit */ #define ATW_NAR_OM_MASK __BITS(10, 11) /* operating mode */ #define ATW_NAR_OM_NORMAL 0x0 -#define ATW_NAR_OM_LOOPBACK SHIFTIN(0x1, ATW_NAR_OM_MASK) +#define ATW_NAR_OM_LOOPBACK __SHIFTIN(0x1, ATW_NAR_OM_MASK) #define ATW_NAR_MM __BIT(7) /* RX any multicast */ #define ATW_NAR_PR __BIT(6) /* promiscuous mode */ #define ATW_NAR_EA __BIT(5) /* match ad hoc packets (?) */ @@ -342,20 +342,20 @@ * debug only" */ #define ATW_TEST1_TXWP_MASK __BITS(27,25) /* select ATW_WTDP content? */ -#define ATW_TEST1_TXWP_TDBD SHIFTIN(0x0, ATW_TEST1_TXWP_MASK) -#define ATW_TEST1_TXWP_TDBH SHIFTIN(0x1, ATW_TEST1_TXWP_MASK) -#define ATW_TEST1_TXWP_TDBB SHIFTIN(0x2, ATW_TEST1_TXWP_MASK) -#define ATW_TEST1_TXWP_TDBP SHIFTIN(0x3, ATW_TEST1_TXWP_MASK) +#define ATW_TEST1_TXWP_TDBD __SHIFTIN(0x0, ATW_TEST1_TXWP_MASK) +#define ATW_TEST1_TXWP_TDBH __SHIFTIN(0x1, ATW_TEST1_TXWP_MASK) +#define ATW_TEST1_TXWP_TDBB __SHIFTIN(0x2, ATW_TEST1_TXWP_MASK) +#define ATW_TEST1_TXWP_TDBP __SHIFTIN(0x3, ATW_TEST1_TXWP_MASK) #define ATW_TEST1_RSVD0_MASK __BITS(24,6) /* reserved */ #define ATW_TEST1_TESTMODE_MASK __BITS(5,4) /* normal operation */ -#define ATW_TEST1_TESTMODE_NORMAL SHIFTIN(0x0, ATW_TEST1_TESTMODE_MASK) +#define ATW_TEST1_TESTMODE_NORMAL __SHIFTIN(0x0, ATW_TEST1_TESTMODE_MASK) /* MAC-only mode */ -#define ATW_TEST1_TESTMODE_MACONLY SHIFTIN(0x1, ATW_TEST1_TESTMODE_MASK) +#define ATW_TEST1_TESTMODE_MACONLY __SHIFTIN(0x1, ATW_TEST1_TESTMODE_MASK) /* normal operation */ -#define ATW_TEST1_TESTMODE_NORMAL2 SHIFTIN(0x2, ATW_TEST1_TESTMODE_MASK) +#define ATW_TEST1_TESTMODE_NORMAL2 __SHIFTIN(0x2, ATW_TEST1_TESTMODE_MASK) /* monitor mode */ -#define ATW_TEST1_TESTMODE_MONITOR SHIFTIN(0x3, ATW_TEST1_TESTMODE_MASK) +#define ATW_TEST1_TESTMODE_MONITOR __SHIFTIN(0x3, ATW_TEST1_TESTMODE_MASK) #define ATW_TEST1_DUMP_MASK __BITS(3,0) /* select dump signal * from dxfer (huh?) @@ -371,48 +371,48 @@ #define ATW_TEST0_TS_MASK __BITS(28, 26) /* Transmit process state */ /* Stopped */ -#define ATW_TEST0_TS_STOPPED SHIFTIN(0, ATW_TEST0_TS_MASK) +#define ATW_TEST0_TS_STOPPED __SHIFTIN(0, ATW_TEST0_TS_MASK) /* Running - fetch transmit descriptor */ -#define ATW_TEST0_TS_FETCH SHIFTIN(1, ATW_TEST0_TS_MASK) +#define ATW_TEST0_TS_FETCH __SHIFTIN(1, ATW_TEST0_TS_MASK) /* Running - wait for end of transmission */ -#define ATW_TEST0_TS_WAIT SHIFTIN(2, ATW_TEST0_TS_MASK) +#define ATW_TEST0_TS_WAIT __SHIFTIN(2, ATW_TEST0_TS_MASK) /* Running - read buffer from memory and queue into FIFO */ -#define ATW_TEST0_TS_READING SHIFTIN(3, ATW_TEST0_TS_MASK) -#define ATW_TEST0_TS_RESERVED1 SHIFTIN(4, ATW_TEST0_TS_MASK) -#define ATW_TEST0_TS_RESERVED2 SHIFTIN(5, ATW_TEST0_TS_MASK) +#define ATW_TEST0_TS_READING __SHIFTIN(3, ATW_TEST0_TS_MASK) +#define ATW_TEST0_TS_RESERVED1 __SHIFTIN(4, ATW_TEST0_TS_MASK) +#define ATW_TEST0_TS_RESERVED2 __SHIFTIN(5, ATW_TEST0_TS_MASK) /* Suspended */ -#define ATW_TEST0_TS_SUSPENDED SHIFTIN(6, ATW_TEST0_TS_MASK) +#define ATW_TEST0_TS_SUSPENDED __SHIFTIN(6, ATW_TEST0_TS_MASK) /* Running - close transmit descriptor */ -#define ATW_TEST0_TS_CLOSE SHIFTIN(7, ATW_TEST0_TS_MASK) +#define ATW_TEST0_TS_CLOSE __SHIFTIN(7, ATW_TEST0_TS_MASK) /* ADM8211C/CR registers */ /* Suspended */ -#define ATW_C_TEST0_TS_SUSPENDED SHIFTIN(4, ATW_TEST0_TS_MASK) +#define ATW_C_TEST0_TS_SUSPENDED __SHIFTIN(4, ATW_TEST0_TS_MASK) /* Descriptor write */ -#define ATW_C_TEST0_TS_CLOSE SHIFTIN(5, ATW_TEST0_TS_MASK) +#define ATW_C_TEST0_TS_CLOSE __SHIFTIN(5, ATW_TEST0_TS_MASK) /* Last descriptor write */ -#define ATW_C_TEST0_TS_CLOSELAST SHIFTIN(6, ATW_TEST0_TS_MASK) +#define ATW_C_TEST0_TS_CLOSELAST __SHIFTIN(6, ATW_TEST0_TS_MASK) /* FIFO full */ -#define ATW_C_TEST0_TS_FIFOFULL SHIFTIN(7, ATW_TEST0_TS_MASK) +#define ATW_C_TEST0_TS_FIFOFULL __SHIFTIN(7, ATW_TEST0_TS_MASK) #define ATW_TEST0_RS_MASK __BITS(25, 23) /* Receive process state */ /* Stopped */ -#define ATW_TEST0_RS_STOPPED SHIFTIN(0, ATW_TEST0_RS_MASK) +#define ATW_TEST0_RS_STOPPED __SHIFTIN(0, ATW_TEST0_RS_MASK) /* Running - fetch receive descriptor */ -#define ATW_TEST0_RS_FETCH SHIFTIN(1, ATW_TEST0_RS_MASK) +#define ATW_TEST0_RS_FETCH __SHIFTIN(1, ATW_TEST0_RS_MASK) /* Running - check for end of receive */ -#define ATW_TEST0_RS_CHECK SHIFTIN(2, ATW_TEST0_RS_MASK) +#define ATW_TEST0_RS_CHECK __SHIFTIN(2, ATW_TEST0_RS_MASK) /* Running - wait for packet */ -#define ATW_TEST0_RS_WAIT SHIFTIN(3, ATW_TEST0_RS_MASK) +#define ATW_TEST0_RS_WAIT __SHIFTIN(3, ATW_TEST0_RS_MASK) /* Suspended */ -#define ATW_TEST0_RS_SUSPENDED SHIFTIN(4, ATW_TEST0_RS_MASK) +#define ATW_TEST0_RS_SUSPENDED __SHIFTIN(4, ATW_TEST0_RS_MASK) /* Running - close receive descriptor */ -#define ATW_TEST0_RS_CLOSE SHIFTIN(5, ATW_TEST0_RS_MASK) +#define ATW_TEST0_RS_CLOSE __SHIFTIN(5, ATW_TEST0_RS_MASK) /* Running - flush current frame from FIFO */ -#define ATW_TEST0_RS_FLUSH SHIFTIN(6, ATW_TEST0_RS_MASK) +#define ATW_TEST0_RS_FLUSH __SHIFTIN(6, ATW_TEST0_RS_MASK) /* Running - queue current frame from FIFO into buffer */ -#define ATW_TEST0_RS_QUEUE SHIFTIN(7, ATW_TEST0_RS_MASK) +#define ATW_TEST0_RS_QUEUE __SHIFTIN(7, ATW_TEST0_RS_MASK) #define ATW_TEST0_EPNE __BIT(18) /* SEEPROM not detected */ #define ATW_TEST0_EPSNM __BIT(17) /* SEEPROM bad signature */ @@ -464,7 +464,7 @@ /* Intersil 3-wire interface */ #define ATW_BBPCTL_TWI __BIT(31) #define ATW_BBPCTL_RF3KADDR_MASK __BITS(30, 24) /* Address for RF3000 */ -#define ATW_BBPCTL_RF3KADDR_ADDR SHIFTIN(0x20, ATW_BBPCTL_RF3KADDR_MASK) +#define ATW_BBPCTL_RF3KADDR_ADDR __SHIFTIN(0x20, ATW_BBPCTL_RF3KADDR_MASK) /* data-out on negative edge */ #define ATW_BBPCTL_NEGEDGE_DO __BIT(23) /* data-in on negative edge */ @@ -520,10 +520,10 @@ /* was magic 0x100E0C0A */ #define ATW_MMIWADDR_INTERSIL \ - (SHIFTIN(0x0c, ATW_MMIWADDR_GAIN_MASK) | \ - SHIFTIN(0x0a, ATW_MMIWADDR_RATE_MASK) | \ - SHIFTIN(0x0e, ATW_MMIWADDR_LENHI_MASK) | \ - SHIFTIN(0x10, ATW_MMIWADDR_LENLO_MASK)) + (__SHIFTIN(0x0c, ATW_MMIWADDR_GAIN_MASK) | \ + __SHIFTIN(0x0a, ATW_MMIWADDR_RATE_MASK) | \ + __SHIFTIN(0x0e, ATW_MMIWADDR_LENHI_MASK) | \ + __SHIFTIN(0x10, ATW_MMIWADDR_LENLO_MASK)) /* was magic 0x00009101 * @@ -532,8 +532,8 @@ * Tx length (high) and Tx length (low) registers back-to-back. */ #define ATW_MMIWADDR_RFMD \ - (SHIFTIN(RF3000_TWI_AI|RF3000_GAINCTL, ATW_MMIWADDR_GAIN_MASK) | \ - SHIFTIN(RF3000_CTL, ATW_MMIWADDR_RATE_MASK)) + (__SHIFTIN(RF3000_TWI_AI|RF3000_GAINCTL, ATW_MMIWADDR_GAIN_MASK) | \ + __SHIFTIN(RF3000_CTL, ATW_MMIWADDR_RATE_MASK)) #define ATW_MMIRADDR1_RSVD_MASK __BITS(31, 24) #define ATW_MMIRADDR1_PWRLVL_MASK __BITS(23, 16) @@ -545,23 +545,23 @@ * TBD document registers for Intersil 3861 baseband */ #define ATW_MMIRADDR1_INTERSIL \ - (SHIFTIN(0x7c, ATW_MMIRADDR1_RSSI_MASK) | \ - SHIFTIN(0x7e, ATW_MMIRADDR1_RXSTAT_MASK)) + (__SHIFTIN(0x7c, ATW_MMIRADDR1_RSSI_MASK) | \ + __SHIFTIN(0x7e, ATW_MMIRADDR1_RXSTAT_MASK)) /* was magic 0x00000301 */ #define ATW_MMIRADDR1_RFMD \ - (SHIFTIN(RF3000_RSSI, ATW_MMIRADDR1_RSSI_MASK) | \ - SHIFTIN(RF3000_RXSTAT, ATW_MMIRADDR1_RXSTAT_MASK)) + (__SHIFTIN(RF3000_RSSI, ATW_MMIRADDR1_RSSI_MASK) | \ + __SHIFTIN(RF3000_RXSTAT, ATW_MMIRADDR1_RXSTAT_MASK)) /* was magic 0x00100000 */ #define ATW_MMIRADDR2_INTERSIL \ - (SHIFTIN(0x0, ATW_MMIRADDR2_ID_MASK) | \ - SHIFTIN(0x10, ATW_MMIRADDR2_RXPECNT_MASK)) + (__SHIFTIN(0x0, ATW_MMIRADDR2_ID_MASK) | \ + __SHIFTIN(0x10, ATW_MMIRADDR2_RXPECNT_MASK)) /* was magic 0x7e100000 */ #define ATW_MMIRADDR2_RFMD \ - (SHIFTIN(0x7e, ATW_MMIRADDR2_ID_MASK) | \ - SHIFTIN(0x10, ATW_MMIRADDR2_RXPECNT_MASK)) + (__SHIFTIN(0x7e, ATW_MMIRADDR2_ID_MASK) | \ + __SHIFTIN(0x10, ATW_MMIRADDR2_RXPECNT_MASK)) #define ATW_MMIRADDR2_ID_MASK __BITS(31, 24) /* 1st element ID in WEP table * for Probe Response (huh?) @@ -628,13 +628,13 @@ #define ATW_CMDR_RTE __BIT(4) /* enable Rx FIFO threshold */ #define ATW_CMDR_DRT_MASK __BITS(3, 2) /* drain Rx FIFO threshold */ /* 32 bytes */ -#define ATW_CMDR_DRT_8DW SHIFTIN(0x0, ATW_CMDR_DRT_MASK) +#define ATW_CMDR_DRT_8DW __SHIFTIN(0x0, ATW_CMDR_DRT_MASK) /* 64 bytes */ -#define ATW_CMDR_DRT_16DW SHIFTIN(0x1, ATW_CMDR_DRT_MASK) +#define ATW_CMDR_DRT_16DW __SHIFTIN(0x1, ATW_CMDR_DRT_MASK) /* Store & Forward */ -#define ATW_CMDR_DRT_SF SHIFTIN(0x2, ATW_CMDR_DRT_MASK) +#define ATW_CMDR_DRT_SF __SHIFTIN(0x2, ATW_CMDR_DRT_MASK) /* Reserved */ -#define ATW_CMDR_DRT_RSVD SHIFTIN(0x3, ATW_CMDR_DRT_MASK) +#define ATW_CMDR_DRT_RSVD __SHIFTIN(0x3, ATW_CMDR_DRT_MASK) #define ATW_CMDR_SINT_MASK __BIT(1) /* software interrupt---huh? */ /* TBD PCIC */ diff --git a/sys/dev/ic/atwvar.h b/sys/dev/ic/atwvar.h index 260b71be293..d1412b3ab46 100644 --- a/sys/dev/ic/atwvar.h +++ b/sys/dev/ic/atwvar.h @@ -1,4 +1,4 @@ -/* $NetBSD: atwvar.h,v 1.21 2006/03/08 08:26:50 dyoung Exp $ */ +/* $NetBSD: atwvar.h,v 1.22 2006/08/31 19:24:37 dyoung Exp $ */ /* * Copyright (c) 2003, 2004 The NetBSD Foundation, Inc. All rights reserved. @@ -412,7 +412,7 @@ do { \ __rxd->ar_buf2 = /* for descriptor chaining */ \ htole32(ATW_CDRXADDR((sc), ATW_NEXTRX((x)))); \ __rxd->ar_ctl = \ - htole32(SHIFTIN(((__m->m_ext.ext_size - 1) & ~0x3U), \ + htole32(__SHIFTIN(((__m->m_ext.ext_size - 1) & ~0x3U), \ ATW_RXCTL_RBS1_MASK) | \ 0 /* ATW_RXCTL_RCH */ | \ ((x) == (ATW_NRXDESC - 1) ? ATW_RXCTL_RER : 0)); \ diff --git a/sys/dev/ic/max2820reg.h b/sys/dev/ic/max2820reg.h index 3ecbdb00629..5f84dba0dde 100644 --- a/sys/dev/ic/max2820reg.h +++ b/sys/dev/ic/max2820reg.h @@ -1,4 +1,4 @@ -/* $NetBSD: max2820reg.h,v 1.6 2006/05/14 21:42:27 elad Exp $ */ +/* $NetBSD: max2820reg.h,v 1.7 2006/08/31 19:24:37 dyoung Exp $ */ /* * Copyright (c) 2004 David Young. All rights reserved. @@ -115,18 +115,18 @@ * 0 = 22MHz * 1 = 44MHz */ -#define MAX2820_SYNTH_R_22MHZ SHIFTIN(0, MAX2820_SYNTH_R_MASK) -#define MAX2820_SYNTH_R_44MHZ SHIFTIN(1, MAX2820_SYNTH_R_MASK) +#define MAX2820_SYNTH_R_22MHZ __SHIFTIN(0, MAX2820_SYNTH_R_MASK) +#define MAX2820_SYNTH_R_44MHZ __SHIFTIN(1, MAX2820_SYNTH_R_MASK) #define MAX2820_SYNTH_ICP_DEFAULT MAX2820_SYNTH_ICP -#define MAX2820_SYNTH_R_DEFAULT SHIFTIN(0, MAX2820_SYNTH_R_MASK) +#define MAX2820_SYNTH_R_DEFAULT __SHIFTIN(0, MAX2820_SYNTH_R_MASK) #define MAX2820_CHANNEL 3 /* Channel Frequency Register */ #define MAX2820_CHANNEL_RSVD __BITS(11,7) /* reserved */ #define MAX2820_CHANNEL_CF_MASK __BITS(6,0) /* Channel Frequency Select * fLO = 2400MHz + CF * 1MHz */ -#define MAX2820_CHANNEL_RSVD_DEFAULT SHIFTIN(0, MAX2820_CHANNEL_RSVD) -#define MAX2820_CHANNEL_CF_DEFAULT SHIFTIN(37, MAX2820_CHANNEL_CF_MASK) +#define MAX2820_CHANNEL_RSVD_DEFAULT __SHIFTIN(0, MAX2820_CHANNEL_RSVD) +#define MAX2820_CHANNEL_CF_DEFAULT __SHIFTIN(37, MAX2820_CHANNEL_CF_MASK) #define MAX2820_RECEIVE 4 /* Receiver Settings Register * MAX2820/MAX2821 @@ -152,16 +152,16 @@ * approximate) */ /* 8.5MHz */ -#define MAX2820_RECEIVE_BW_8_5MHZ SHIFTIN(0, MAX2820_RECEIVE_BW_MASK) -#define MAX2820_RECEIVE_BW_8MHZ SHIFTIN(1, MAX2820_RECEIVE_BW_MASK) -#define MAX2820_RECEIVE_BW_7_5MHZ SHIFTIN(2, MAX2820_RECEIVE_BW_MASK) -#define MAX2820_RECEIVE_BW_7MHZ SHIFTIN(3, MAX2820_RECEIVE_BW_MASK) -#define MAX2820_RECEIVE_BW_6_5MHZ SHIFTIN(4, MAX2820_RECEIVE_BW_MASK) -#define MAX2820_RECEIVE_BW_6MHZ SHIFTIN(5, MAX2820_RECEIVE_BW_MASK) -#define MAX2820_RECEIVE_2C_DEFAULT SHIFTIN(7, MAX2820_RECEIVE_2C_MASK) -#define MAX2820_RECEIVE_1C_DEFAULT SHIFTIN(7, MAX2820_RECEIVE_1C_MASK) -#define MAX2820_RECEIVE_DL_DEFAULT SHIFTIN(1, MAX2820_RECEIVE_DL_MASK) -#define MAX2820_RECEIVE_SF_DEFAULT SHIFTIN(0, MAX2820_RECEIVE_SF) +#define MAX2820_RECEIVE_BW_8_5MHZ __SHIFTIN(0, MAX2820_RECEIVE_BW_MASK) +#define MAX2820_RECEIVE_BW_8MHZ __SHIFTIN(1, MAX2820_RECEIVE_BW_MASK) +#define MAX2820_RECEIVE_BW_7_5MHZ __SHIFTIN(2, MAX2820_RECEIVE_BW_MASK) +#define MAX2820_RECEIVE_BW_7MHZ __SHIFTIN(3, MAX2820_RECEIVE_BW_MASK) +#define MAX2820_RECEIVE_BW_6_5MHZ __SHIFTIN(4, MAX2820_RECEIVE_BW_MASK) +#define MAX2820_RECEIVE_BW_6MHZ __SHIFTIN(5, MAX2820_RECEIVE_BW_MASK) +#define MAX2820_RECEIVE_2C_DEFAULT __SHIFTIN(7, MAX2820_RECEIVE_2C_MASK) +#define MAX2820_RECEIVE_1C_DEFAULT __SHIFTIN(7, MAX2820_RECEIVE_1C_MASK) +#define MAX2820_RECEIVE_DL_DEFAULT __SHIFTIN(1, MAX2820_RECEIVE_DL_MASK) +#define MAX2820_RECEIVE_SF_DEFAULT __SHIFTIN(0, MAX2820_RECEIVE_SF) #define MAX2820_RECEIVE_BW_DEFAULT MAX2820_RECEIVE_BW_7_5MHZ #define MAX2820A_RECEIVE 4 /* Receiver Settings Register, @@ -169,14 +169,14 @@ */ /* VGA DC Offset Nulling Parameter 2 */ #define MAX2820A_RECEIVE_2C_MASK __BITS(11,9) -#define MAX2820A_RECEIVE_2C_DEFAULT SHIFTIN(7, MAX2820A_RECEIVE_2C_MASK) +#define MAX2820A_RECEIVE_2C_DEFAULT __SHIFTIN(7, MAX2820A_RECEIVE_2C_MASK) /* VGA DC Offset Nulling Parameter 1 */ #define MAX2820A_RECEIVE_1C_MASK __BITS(8,6) -#define MAX2820A_RECEIVE_1C_DEFAULT SHIFTIN(7, MAX2820A_RECEIVE_1C_MASK) +#define MAX2820A_RECEIVE_1C_DEFAULT __SHIFTIN(7, MAX2820A_RECEIVE_1C_MASK) #define MAX2820A_RECEIVE_RSVD0_MASK __BITS(5,3) -#define MAX2820A_RECEIVE_RSVD0_DEFAULT SHIFTIN(2, MAX2820A_RECEIVE_RSVD0_MASK) +#define MAX2820A_RECEIVE_RSVD0_DEFAULT __SHIFTIN(2, MAX2820A_RECEIVE_RSVD0_MASK) #define MAX2820A_RECEIVE_RSVD1_MASK __BITS(2,0) -#define MAX2820A_RECEIVE_RSVD1_DEFAULT SHIFTIN(2,MAX2820_RECEIVE_RSVD1_MASK) +#define MAX2820A_RECEIVE_RSVD1_DEFAULT __SHIFTIN(2,MAX2820_RECEIVE_RSVD1_MASK) #define MAX2820_TRANSMIT 5 /* Transmitter Settings Reg. */ #define MAX2820_TRANSMIT_RSVD_MASK __BITS(11,4) /* reserved */ @@ -184,6 +184,6 @@ * 15 = Highest * 0 = Lowest */ -#define MAX2820_TRANSMIT_PA_DEFAULT SHIFTIN(0, MAX2820_TRANSMIT_PA_MASK) +#define MAX2820_TRANSMIT_PA_DEFAULT __SHIFTIN(0, MAX2820_TRANSMIT_PA_MASK) #endif /* _DEV_IC_MAX2820REG_H_ */ diff --git a/sys/dev/ic/rtw.c b/sys/dev/ic/rtw.c index 6dec085aaef..94582632eae 100644 --- a/sys/dev/ic/rtw.c +++ b/sys/dev/ic/rtw.c @@ -1,4 +1,4 @@ -/* $NetBSD: rtw.c,v 1.74 2006/05/26 13:01:53 blymn Exp $ */ +/* $NetBSD: rtw.c,v 1.75 2006/08/31 19:24:38 dyoung Exp $ */ /*- * Copyright (c) 2004, 2005 David Young. All rights reserved. * @@ -34,7 +34,7 @@ */ #include <sys/cdefs.h> -__KERNEL_RCSID(0, "$NetBSD: rtw.c,v 1.74 2006/05/26 13:01:53 blymn Exp $"); +__KERNEL_RCSID(0, "$NetBSD: rtw.c,v 1.75 2006/08/31 19:24:38 dyoung Exp $"); #include "bpfilter.h" @@ -239,7 +239,7 @@ static int rtw_sysctl_verify_rfprog(SYSCTLFN_ARGS) { return rtw_sysctl_verify(SYSCTLFN_CALL(__UNCONST(rnode)), 0, - SHIFTOUT(RTW_CONFIG4_RFTYPE_MASK, RTW_CONFIG4_RFTYPE_MASK)); + __SHIFTOUT(RTW_CONFIG4_RFTYPE_MASK, RTW_CONFIG4_RFTYPE_MASK)); } static int @@ -550,7 +550,7 @@ rtw_chip_reset(struct rtw_regs *regs, const char *dvname) /* from Linux driver */ tcr = RTW_TCR_CWMIN | RTW_TCR_MXDMA_2048 | - SHIFTIN(7, RTW_TCR_SRL_MASK) | SHIFTIN(7, RTW_TCR_LRL_MASK); + __SHIFTIN(7, RTW_TCR_SRL_MASK) | __SHIFTIN(7, RTW_TCR_LRL_MASK); RTW_WRITE(regs, RTW_TCR, tcr); @@ -877,7 +877,7 @@ rtw_srom_parse(struct rtw_srom *sr, uint32_t *flags, uint8_t *cs_threshold, if ((RTW_SR_GET(sr, RTW_SR_RFPARM) & RTW_SR_RFPARM_DFLANTB) != 0) *flags |= RTW_F_DFLANTB; - *rcr |= SHIFTIN(SHIFTOUT(RTW_SR_GET(sr, RTW_SR_RFPARM), + *rcr |= __SHIFTIN(__SHIFTOUT(RTW_SR_GET(sr, RTW_SR_RFPARM), RTW_SR_RFPARM_CS_MASK), RTW_RCR_ENCS1); if ((RTW_SR_GET(sr, RTW_SR_CONFIG0) & RTW_CONFIG0_WEP104) != 0) @@ -1039,7 +1039,7 @@ rtw_set_rfprog(struct rtw_regs *regs, enum rtw_rfchipid rfchipid, switch (rfchipid) { default: - cfg4 |= SHIFTIN(rtw_rfprog_fallback, RTW_CONFIG4_RFTYPE_MASK); + cfg4 |= __SHIFTIN(rtw_rfprog_fallback, RTW_CONFIG4_RFTYPE_MASK); method = "fallback"; break; case RTW_RFCHIPID_INTERSIL: @@ -1139,13 +1139,13 @@ rtw_identify_sta(struct rtw_regs *regs, uint8_t (*addr)[IEEE80211_ADDR_LEN], uint32_t idr0 = RTW_READ(regs, RTW_IDR0), idr1 = RTW_READ(regs, RTW_IDR1); - (*addr)[0] = SHIFTOUT(idr0, __BITS(0, 7)); - (*addr)[1] = SHIFTOUT(idr0, __BITS(8, 15)); - (*addr)[2] = SHIFTOUT(idr0, __BITS(16, 23)); - (*addr)[3] = SHIFTOUT(idr0, __BITS(24 ,31)); + (*addr)[0] = __SHIFTOUT(idr0, __BITS(0, 7)); + (*addr)[1] = __SHIFTOUT(idr0, __BITS(8, 15)); + (*addr)[2] = __SHIFTOUT(idr0, __BITS(16, 23)); + (*addr)[3] = __SHIFTOUT(idr0, __BITS(24 ,31)); - (*addr)[4] = SHIFTOUT(idr1, __BITS(0, 7)); - (*addr)[5] = SHIFTOUT(idr1, __BITS(8, 15)); + (*addr)[4] = __SHIFTOUT(idr1, __BITS(0, 7)); + (*addr)[5] = __SHIFTOUT(idr1, __BITS(8, 15)); if (IEEE80211_ADDR_EQ(addr, empty_macaddr)) { printf("%s: could not get mac address, attach failed\n", @@ -1371,7 +1371,7 @@ rtw_rxdesc_init(struct rtw_rxdesc_blk *rdb, struct rtw_rxsoft *rs, obuf = rd->rd_buf; rd->rd_buf = htole32(rs->rs_dmamap->dm_segs[0].ds_addr); - ctl = SHIFTIN(rs->rs_mbuf->m_len, RTW_RXCTL_LENGTH_MASK) | + ctl = __SHIFTIN(rs->rs_mbuf->m_len, RTW_RXCTL_LENGTH_MASK) | RTW_RXCTL_OWN | RTW_RXCTL_FS | RTW_RXCTL_LS; if (is_last) @@ -1522,14 +1522,14 @@ rtw_intr_rx(struct rtw_softc *sc, uint16_t isr) #endif /* RTW_DEBUG */ if ((hstat & RTW_RXSTAT_IOERROR) != 0) { - printf("%s: DMA error/FIFO overflow %08x, " + printf("%s: DMA error/FIFO overflow %08" PRIx32 ", " "rx descriptor %d\n", sc->sc_dev.dv_xname, - hstat & RTW_RXSTAT_IOERROR, next); + hstat, next); ifp->if_ierrors++; goto next; } - len = SHIFTOUT(hstat, RTW_RXSTAT_LENGTH_MASK); + len = __SHIFTOUT(hstat, RTW_RXSTAT_LENGTH_MASK); if (len < IEEE80211_MIN_LEN) { sc->sc_ic.ic_stats.is_rx_tooshort++; goto next; @@ -1538,10 +1538,10 @@ rtw_intr_rx(struct rtw_softc *sc, uint16_t isr) /* CRC is included with the packet; trim it off. */ len -= IEEE80211_CRC_LEN; - hwrate = SHIFTOUT(hstat, RTW_RXSTAT_RATE_MASK); + hwrate = __SHIFTOUT(hstat, RTW_RXSTAT_RATE_MASK); if (hwrate >= sizeof(ratetbl) / sizeof(ratetbl[0])) { printf("%s: unknown rate #%d\n", sc->sc_dev.dv_xname, - SHIFTOUT(hstat, RTW_RXSTAT_RATE_MASK)); + __SHIFTOUT(hstat, RTW_RXSTAT_RATE_MASK)); ifp->if_ierrors++; goto next; } @@ -1584,16 +1584,16 @@ rtw_intr_rx(struct rtw_softc *sc, uint16_t isr) } if (sc->sc_rfchipid == RTW_RFCHIPID_PHILIPS) - rssi = SHIFTOUT(hrssi, RTW_RXRSSI_RSSI); + rssi = __SHIFTOUT(hrssi, RTW_RXRSSI_RSSI); else { - rssi = SHIFTOUT(hrssi, RTW_RXRSSI_IMR_RSSI); + rssi = __SHIFTOUT(hrssi, RTW_RXRSSI_IMR_RSSI); /* TBD find out each front-end's LNA gain in the * front-end's units */ if ((hrssi & RTW_RXRSSI_IMR_LNA) == 0) rssi |= 0x80; } - sq = SHIFTOUT(hrssi, RTW_RXRSSI_SQ); + sq = __SHIFTOUT(hrssi, RTW_RXRSSI_SQ); /* Note well: now we cannot recycle the rs_mbuf unless * we restore its original length. @@ -1703,8 +1703,8 @@ rtw_collect_txpkt(struct rtw_softc *sc, struct rtw_txdesc_blk *tdb, tdn = &tdb->tdb_desc[ts->ts_last]; hstat = le32toh(tdn->td_stat); - rts_retry = SHIFTOUT(hstat, RTW_TXSTAT_RTSRETRY_MASK); - data_retry = SHIFTOUT(hstat, RTW_TXSTAT_DRC_MASK); + rts_retry = __SHIFTOUT(hstat, RTW_TXSTAT_RTSRETRY_MASK); + data_retry = __SHIFTOUT(hstat, RTW_TXSTAT_DRC_MASK); ifp->if_collisions += rts_retry + data_retry; @@ -2541,7 +2541,7 @@ rtw_transmit_config(struct rtw_regs *regs) /* set short/long retry limits */ tcr &= ~(RTW_TCR_SRL_MASK|RTW_TCR_LRL_MASK); - tcr |= SHIFTIN(4, RTW_TCR_SRL_MASK) | SHIFTIN(4, RTW_TCR_LRL_MASK); + tcr |= __SHIFTIN(4, RTW_TCR_SRL_MASK) | __SHIFTIN(4, RTW_TCR_LRL_MASK); tcr &= ~RTW_TCR_CRC; /* NIC appends CRC32 */ @@ -3306,7 +3306,7 @@ rtw_start(struct ifnet *ifp) } #endif /* RTW_DEBUG */ ctl0 = proto_ctl0 | - SHIFTIN(m0->m_pkthdr.len, RTW_TXCTL0_TPKTSIZE_MASK); + __SHIFTIN(m0->m_pkthdr.len, RTW_TXCTL0_TPKTSIZE_MASK); switch (rate) { default: @@ -3332,7 +3332,7 @@ rtw_start(struct ifnet *ifp) * encryption. */ if (k != NULL) { - ctl0 |= SHIFTIN(k->wk_keyix, RTW_TXCTL0_KEYID_MASK) & + ctl0 |= __SHIFTIN(k->wk_keyix, RTW_TXCTL0_KEYID_MASK) & RTW_TXCTL0_KEYID_MASK; } @@ -3358,8 +3358,8 @@ rtw_start(struct ifnet *ifp) *(uint16_t*)wh->i_dur = htole16(d0->d_data_dur); - ctl1 = SHIFTIN(d0->d_plcp_len, RTW_TXCTL1_LENGTH_MASK) | - SHIFTIN(d0->d_rts_dur, RTW_TXCTL1_RTSDUR_MASK); + ctl1 = __SHIFTIN(d0->d_plcp_len, RTW_TXCTL1_LENGTH_MASK) | + __SHIFTIN(d0->d_rts_dur, RTW_TXCTL1_RTSDUR_MASK); if (d0->d_residue) ctl1 |= RTW_TXCTL1_LENGEXT; @@ -3554,18 +3554,18 @@ rtw_join_bss(struct rtw_softc *sc, uint8_t *bssid, uint16_t intval0) rtw_set_access(regs, RTW_ACCESS_CONFIG); - intval = MIN(intval0, SHIFTOUT_MASK(RTW_BCNITV_BCNITV_MASK)); + intval = MIN(intval0, __SHIFTOUT_MASK(RTW_BCNITV_BCNITV_MASK)); bcnitv = RTW_READ16(regs, RTW_BCNITV) & ~RTW_BCNITV_BCNITV_MASK; - bcnitv |= SHIFTIN(intval, RTW_BCNITV_BCNITV_MASK); + bcnitv |= __SHIFTIN(intval, RTW_BCNITV_BCNITV_MASK); RTW_WRITE16(regs, RTW_BCNITV, bcnitv); /* interrupt host 1ms before the TBTT */ bintritv = RTW_READ16(regs, RTW_BINTRITV) & ~RTW_BINTRITV_BINTRITV; - bintritv |= SHIFTIN(1000, RTW_BINTRITV_BINTRITV); + bintritv |= __SHIFTIN(1000, RTW_BINTRITV_BINTRITV); RTW_WRITE16(regs, RTW_BINTRITV, bintritv); /* magic from Linux */ - RTW_WRITE16(regs, RTW_ATIMWND, SHIFTIN(1, RTW_ATIMWND_ATIMWND)); - RTW_WRITE16(regs, RTW_ATIMTRITV, SHIFTIN(2, RTW_ATIMTRITV_ATIMTRITV)); + RTW_WRITE16(regs, RTW_ATIMWND, __SHIFTIN(1, RTW_ATIMWND_ATIMWND)); + RTW_WRITE16(regs, RTW_ATIMTRITV, __SHIFTIN(2, RTW_ATIMTRITV_ATIMTRITV)); rtw_set_access(regs, RTW_ACCESS_NONE); rtw_io_enable(regs, RTW_CR_RE | RTW_CR_TE, 1); @@ -4009,7 +4009,7 @@ rtw_check_phydelay(struct rtw_regs *regs, uint32_t old_rcr) #define REVAB (RTW_RCR_MXDMA_UNLIMITED | RTW_RCR_AICV) #define REVC (REVAB | RTW_RCR_RXFTH_WHOLE) - uint8_t phydelay = SHIFTIN(0x6, RTW_PHYDELAY_PHYDELAY); + uint8_t phydelay = __SHIFTIN(0x6, RTW_PHYDELAY_PHYDELAY); RTW_WRITE(regs, RTW_RCR, REVAB); RTW_WBW(regs, RTW_RCR, RTW_RCR); diff --git a/sys/dev/ic/rtwphy.c b/sys/dev/ic/rtwphy.c index 5e1a54a730c..c66c895a985 100644 --- a/sys/dev/ic/rtwphy.c +++ b/sys/dev/ic/rtwphy.c @@ -1,4 +1,4 @@ -/* $NetBSD: rtwphy.c,v 1.9 2006/03/08 00:24:06 dyoung Exp $ */ +/* $NetBSD: rtwphy.c,v 1.10 2006/08/31 19:24:38 dyoung Exp $ */ /*- * Copyright (c) 2004, 2005 David Young. All rights reserved. * @@ -35,7 +35,7 @@ */ #include <sys/cdefs.h> -__KERNEL_RCSID(0, "$NetBSD: rtwphy.c,v 1.9 2006/03/08 00:24:06 dyoung Exp $"); +__KERNEL_RCSID(0, "$NetBSD: rtwphy.c,v 1.10 2006/08/31 19:24:38 dyoung Exp $"); #include <sys/param.h> #include <sys/systm.h> @@ -91,7 +91,7 @@ rtw_bbp_init(struct rtw_regs *regs, struct rtw_bbpset *bb, int antdiv, if (antdiv) sys2 |= RTW_BBP_SYS2_ANTDIV; sys3 = bb->bb_sys3 | - SHIFTIN(cs_threshold, RTW_BBP_SYS3_CSTHRESH_MASK); + __SHIFTIN(cs_threshold, RTW_BBP_SYS3_CSTHRESH_MASK); #define RTW_BBP_WRITE_OR_RETURN(reg, val) \ if ((rc = rtw_bbp_write(regs, reg, val)) != 0) \ @@ -194,16 +194,16 @@ rtw_sa2400_tune(struct rtw_rf *rf, u_int freq) */ int n = freq / 4, nf = (freq % 4) * 2; - syna = SHIFTIN(nf, SA2400_SYNA_NF_MASK) | SHIFTIN(n, SA2400_SYNA_N_MASK); + syna = __SHIFTIN(nf, SA2400_SYNA_NF_MASK) | __SHIFTIN(n, SA2400_SYNA_N_MASK); verify_syna(freq, syna); /* Divide the 44MHz crystal down to 4MHz. Set the fractional * compensation charge pump value to agree with the fractional * modulus. */ - synb = SHIFTIN(11, SA2400_SYNB_R_MASK) | SA2400_SYNB_L_NORMAL | + synb = __SHIFTIN(11, SA2400_SYNB_R_MASK) | SA2400_SYNB_L_NORMAL | SA2400_SYNB_ON | SA2400_SYNB_ONE | - SHIFTIN(80, SA2400_SYNB_FC_MASK); /* agrees w/ SA2400_SYNA_FM = 0 */ + __SHIFTIN(80, SA2400_SYNB_FC_MASK); /* agrees w/ SA2400_SYNA_FM = 0 */ sync = SA2400_SYNC_CP_NORMAL; @@ -255,7 +255,7 @@ rtw_sa2400_manrx_init(struct rtw_sa2400 *sa) */ manrx = SA2400_MANRX_AHSN; manrx |= SA2400_MANRX_TEN; - manrx |= SHIFTIN(1023, SA2400_MANRX_RXGAIN_MASK); + manrx |= __SHIFTIN(1023, SA2400_MANRX_RXGAIN_MASK); return rtw_rfbus_write(&sa->sa_bus, RTW_RFCHIPID_PHILIPS, SA2400_MANRX, manrx); @@ -344,10 +344,10 @@ rtw_sa2400_agc_init(struct rtw_sa2400 *sa) { uint32_t agc; - agc = SHIFTIN(25, SA2400_AGC_MAXGAIN_MASK); - agc |= SHIFTIN(7, SA2400_AGC_BBPDELAY_MASK); - agc |= SHIFTIN(15, SA2400_AGC_LNADELAY_MASK); - agc |= SHIFTIN(27, SA2400_AGC_RXONDELAY_MASK); + agc = __SHIFTIN(25, SA2400_AGC_MAXGAIN_MASK); + agc |= __SHIFTIN(7, SA2400_AGC_BBPDELAY_MASK); + agc |= __SHIFTIN(15, SA2400_AGC_LNADELAY_MASK); + agc |= __SHIFTIN(27, SA2400_AGC_RXONDELAY_MASK); return rtw_rfbus_write(&sa->sa_bus, RTW_RFCHIPID_PHILIPS, SA2400_AGC, agc); @@ -638,7 +638,7 @@ rtw_max2820_tune(struct rtw_rf *rf, u_int freq) return -1; return rtw_rfbus_write(bus, RTW_RFCHIPID_MAXIM, MAX2820_CHANNEL, - SHIFTIN(freq - 2400, MAX2820_CHANNEL_CF_MASK)); + __SHIFTIN(freq - 2400, MAX2820_CHANNEL_CF_MASK)); } static void @@ -684,8 +684,8 @@ rtw_max2820_init(struct rtw_rf *rf, u_int freq, uint8_t opaque_txpower, */ if ((rc = rtw_rfbus_write(bus, RTW_RFCHIPID_MAXIM, MAX2820_RECEIVE, MAX2820_RECEIVE_DL_DEFAULT | - SHIFTIN(4, MAX2820A_RECEIVE_1C_MASK) | - SHIFTIN(1, MAX2820A_RECEIVE_2C_MASK))) != 0) + __SHIFTIN(4, MAX2820A_RECEIVE_1C_MASK) | + __SHIFTIN(1, MAX2820A_RECEIVE_2C_MASK))) != 0) return rc; return rtw_rfbus_write(bus, RTW_RFCHIPID_MAXIM, MAX2820_TRANSMIT, diff --git a/sys/dev/ic/rtwphyio.c b/sys/dev/ic/rtwphyio.c index a2feb9251bb..e048f8ff0e8 100644 --- a/sys/dev/ic/rtwphyio.c +++ b/sys/dev/ic/rtwphyio.c @@ -1,4 +1,4 @@ -/* $NetBSD: rtwphyio.c,v 1.11 2006/03/08 00:24:06 dyoung Exp $ */ +/* $NetBSD: rtwphyio.c,v 1.12 2006/08/31 19:24:38 dyoung Exp $ */ /*- * Copyright (c) 2004, 2005 David Young. All rights reserved. * @@ -35,7 +35,7 @@ */ #include <sys/cdefs.h> -__KERNEL_RCSID(0, "$NetBSD: rtwphyio.c,v 1.11 2006/03/08 00:24:06 dyoung Exp $"); +__KERNEL_RCSID(0, "$NetBSD: rtwphyio.c,v 1.12 2006/08/31 19:24:38 dyoung Exp $"); #include <sys/param.h> #include <sys/systm.h> @@ -64,12 +64,12 @@ static int rtw_macbangbits_timeout = 100; uint8_t rtw_bbp_read(struct rtw_regs *regs, u_int addr) { - KASSERT((addr & ~SHIFTOUT_MASK(RTW_BB_ADDR_MASK)) == 0); + KASSERT((addr & ~__SHIFTOUT_MASK(RTW_BB_ADDR_MASK)) == 0); RTW_WRITE(regs, RTW_BB, - SHIFTIN(addr, RTW_BB_ADDR_MASK) | RTW_BB_RD_MASK | RTW_BB_WR_MASK); + __SHIFTIN(addr, RTW_BB_ADDR_MASK) | RTW_BB_RD_MASK | RTW_BB_WR_MASK); delay(10); /* XXX */ RTW_WBR(regs, RTW_BB, RTW_BB); - return SHIFTOUT(RTW_READ(regs, RTW_BB), RTW_BB_RD_MASK); + return __SHIFTOUT(RTW_READ(regs, RTW_BB), RTW_BB_RD_MASK); } int @@ -83,13 +83,13 @@ rtw_bbp_write(struct rtw_regs *regs, u_int addr, u_int val) RTW_DPRINTF(RTW_DEBUG_PHYIO, ("%s: bbp[%u] <- %u\n", __func__, addr, val)); - KASSERT((addr & ~SHIFTOUT_MASK(RTW_BB_ADDR_MASK)) == 0); - KASSERT((val & ~SHIFTOUT_MASK(RTW_BB_WR_MASK)) == 0); + KASSERT((addr & ~__SHIFTOUT_MASK(RTW_BB_ADDR_MASK)) == 0); + KASSERT((val & ~__SHIFTOUT_MASK(RTW_BB_WR_MASK)) == 0); - wrbbp = SHIFTIN(addr, RTW_BB_ADDR_MASK) | RTW_BB_WREN | - SHIFTIN(val, RTW_BB_WR_MASK) | RTW_BB_RD_MASK, + wrbbp = __SHIFTIN(addr, RTW_BB_ADDR_MASK) | RTW_BB_WREN | + __SHIFTIN(val, RTW_BB_WR_MASK) | RTW_BB_RD_MASK, - rdbbp = SHIFTIN(addr, RTW_BB_ADDR_MASK) | + rdbbp = __SHIFTIN(addr, RTW_BB_ADDR_MASK) | RTW_BB_WR_MASK | RTW_BB_RD_MASK; RTW_DPRINTF(RTW_DEBUG_PHYIO, @@ -102,7 +102,7 @@ rtw_bbp_write(struct rtw_regs *regs, u_int addr, u_int val) RTW_WRITE(regs, RTW_BB, rdbbp); RTW_SYNC(regs, RTW_BB, RTW_BB); delay(BBP_WRITE_DELAY); /* 1 microsecond */ - if (SHIFTOUT(RTW_READ(regs, RTW_BB), + if (__SHIFTOUT(RTW_READ(regs, RTW_BB), RTW_BB_RD_MASK) == val) { RTW_DPRINTF(RTW_DEBUG_PHYIO, ("%s: finished in %dus\n", __func__, @@ -221,7 +221,7 @@ rtw_grf5101_mac_crypt(u_int addr, uint32_t val) (caesar[(addr >> 1) & 0xf] << 12) | ((addr & 0x1) << 16) | (caesar[EXTRACT_NIBBLE(val, 3)] << 24); - return SHIFTIN(data_and_addr, + return __SHIFTIN(data_and_addr, RTW_PHYCFG_MAC_PHILIPS_ADDR_MASK|RTW_PHYCFG_MAC_PHILIPS_DATA_MASK); #undef EXTRACT_NIBBLE } @@ -261,29 +261,29 @@ rtw_rf_hostwrite(struct rtw_regs *regs, enum rtw_rfchipid rfchipid, case RTW_RFCHIPID_MAXIM: nbits = 16; lo_to_hi = 0; - bits = SHIFTIN(val, MAX2820_TWI_DATA_MASK) | - SHIFTIN(addr, MAX2820_TWI_ADDR_MASK); + bits = __SHIFTIN(val, MAX2820_TWI_DATA_MASK) | + __SHIFTIN(addr, MAX2820_TWI_ADDR_MASK); break; case RTW_RFCHIPID_PHILIPS: - KASSERT((addr & ~SHIFTOUT_MASK(SA2400_TWI_ADDR_MASK)) == 0); - KASSERT((val & ~SHIFTOUT_MASK(SA2400_TWI_DATA_MASK)) == 0); - bits = SHIFTIN(val, SA2400_TWI_DATA_MASK) | - SHIFTIN(addr, SA2400_TWI_ADDR_MASK) | SA2400_TWI_WREN; + KASSERT((addr & ~__SHIFTOUT_MASK(SA2400_TWI_ADDR_MASK)) == 0); + KASSERT((val & ~__SHIFTOUT_MASK(SA2400_TWI_DATA_MASK)) == 0); + bits = __SHIFTIN(val, SA2400_TWI_DATA_MASK) | + __SHIFTIN(addr, SA2400_TWI_ADDR_MASK) | SA2400_TWI_WREN; nbits = 32; lo_to_hi = 1; break; case RTW_RFCHIPID_GCT: - KASSERT((addr & ~SHIFTOUT_MASK(SI4126_TWI_ADDR_MASK)) == 0); - KASSERT((val & ~SHIFTOUT_MASK(SI4126_TWI_DATA_MASK)) == 0); + KASSERT((addr & ~__SHIFTOUT_MASK(SI4126_TWI_ADDR_MASK)) == 0); + KASSERT((val & ~__SHIFTOUT_MASK(SI4126_TWI_DATA_MASK)) == 0); bits = rtw_grf5101_host_crypt(addr, val); nbits = 21; lo_to_hi = 1; break; case RTW_RFCHIPID_RFMD: - KASSERT((addr & ~SHIFTOUT_MASK(SI4126_TWI_ADDR_MASK)) == 0); - KASSERT((val & ~SHIFTOUT_MASK(SI4126_TWI_DATA_MASK)) == 0); - bits = SHIFTIN(val, SI4126_TWI_DATA_MASK) | - SHIFTIN(addr, SI4126_TWI_ADDR_MASK); + KASSERT((addr & ~__SHIFTOUT_MASK(SI4126_TWI_ADDR_MASK)) == 0); + KASSERT((val & ~__SHIFTOUT_MASK(SI4126_TWI_DATA_MASK)) == 0); + bits = __SHIFTIN(val, SI4126_TWI_DATA_MASK) | + __SHIFTIN(addr, SI4126_TWI_ADDR_MASK); nbits = 22; lo_to_hi = 0; break; @@ -304,11 +304,11 @@ rtw_maxim_swizzle(u_int addr, uint32_t val) uint32_t hidata, lodata; KASSERT((val & ~(RTW_MAXIM_LODATA_MASK|RTW_MAXIM_HIDATA_MASK)) == 0); - lodata = SHIFTOUT(val, RTW_MAXIM_LODATA_MASK); - hidata = SHIFTOUT(val, RTW_MAXIM_HIDATA_MASK); - return SHIFTIN(lodata, RTW_PHYCFG_MAC_MAXIM_LODATA_MASK) | - SHIFTIN(hidata, RTW_PHYCFG_MAC_MAXIM_HIDATA_MASK) | - SHIFTIN(addr, RTW_PHYCFG_MAC_MAXIM_ADDR_MASK); + lodata = __SHIFTOUT(val, RTW_MAXIM_LODATA_MASK); + hidata = __SHIFTOUT(val, RTW_MAXIM_HIDATA_MASK); + return __SHIFTIN(lodata, RTW_PHYCFG_MAC_MAXIM_LODATA_MASK) | + __SHIFTIN(hidata, RTW_PHYCFG_MAC_MAXIM_HIDATA_MASK) | + __SHIFTIN(addr, RTW_PHYCFG_MAC_MAXIM_ADDR_MASK); } /* Tell the MAC what to bang over the 3-wire interface. */ @@ -331,12 +331,12 @@ rtw_rf_macwrite(struct rtw_regs *regs, enum rtw_rfchipid rfchipid, default: /* XXX */ case RTW_RFCHIPID_PHILIPS: KASSERT( - (addr & ~SHIFTOUT_MASK(RTW_PHYCFG_MAC_PHILIPS_ADDR_MASK)) == 0); + (addr & ~__SHIFTOUT_MASK(RTW_PHYCFG_MAC_PHILIPS_ADDR_MASK)) == 0); KASSERT( - (val & ~SHIFTOUT_MASK(RTW_PHYCFG_MAC_PHILIPS_DATA_MASK)) == 0); + (val & ~__SHIFTOUT_MASK(RTW_PHYCFG_MAC_PHILIPS_DATA_MASK)) == 0); - reg = SHIFTIN(addr, RTW_PHYCFG_MAC_PHILIPS_ADDR_MASK) | - SHIFTIN(val, RTW_PHYCFG_MAC_PHILIPS_DATA_MASK); + reg = __SHIFTIN(addr, RTW_PHYCFG_MAC_PHILIPS_ADDR_MASK) | + __SHIFTIN(val, RTW_PHYCFG_MAC_PHILIPS_DATA_MASK); } switch (rfchipid) { diff --git a/sys/dev/ic/rtwreg.h b/sys/dev/ic/rtwreg.h index 1619df3a502..e54c3cbff4d 100644 --- a/sys/dev/ic/rtwreg.h +++ b/sys/dev/ic/rtwreg.h @@ -1,4 +1,4 @@ -/* $NetBSD: rtwreg.h,v 1.19 2006/03/10 23:37:35 dyoung Exp $ */ +/* $NetBSD: rtwreg.h,v 1.20 2006/08/31 19:24:38 dyoung Exp $ */ /*- * Copyright (c) 2004, 2005 David Young. All rights reserved. * @@ -63,10 +63,10 @@ * 0: use long PLCP header */ #define RTW_BRSR_MBR8180_MASK __BITS(1,0) /* Maximum Basic Service Rate */ -#define RTW_BRSR_MBR8180_1MBPS SHIFTIN(0, RTW_BRSR_MBR8180_MASK) -#define RTW_BRSR_MBR8180_2MBPS SHIFTIN(1, RTW_BRSR_MBR8180_MASK) -#define RTW_BRSR_MBR8180_5MBPS SHIFTIN(2, RTW_BRSR_MBR8180_MASK) -#define RTW_BRSR_MBR8180_11MBPS SHIFTIN(3, RTW_BRSR_MBR8180_MASK) +#define RTW_BRSR_MBR8180_1MBPS __SHIFTIN(0, RTW_BRSR_MBR8180_MASK) +#define RTW_BRSR_MBR8180_2MBPS __SHIFTIN(1, RTW_BRSR_MBR8180_MASK) +#define RTW_BRSR_MBR8180_5MBPS __SHIFTIN(2, RTW_BRSR_MBR8180_MASK) +#define RTW_BRSR_MBR8180_11MBPS __SHIFTIN(3, RTW_BRSR_MBR8180_MASK) /* 8181 and 8180 docs conflict! */ #define RTW_BRSR_MBR8181_1MBPS __BIT(0) @@ -158,8 +158,8 @@ */ /* Hardware version ID, read-only */ #define RTW_TCR_HWVERID_MASK __BITS(29, 25) -#define RTW_TCR_HWVERID_D SHIFTIN(26, RTW_TCR_HWVERID_MASK) -#define RTW_TCR_HWVERID_F SHIFTIN(27, RTW_TCR_HWVERID_MASK) +#define RTW_TCR_HWVERID_D __SHIFTIN(26, RTW_TCR_HWVERID_MASK) +#define RTW_TCR_HWVERID_F __SHIFTIN(27, RTW_TCR_HWVERID_MASK) #define RTW_TCR_HWVERID_RTL8180 RTW_TCR_HWVERID_F /* Set ACK/CTS Timeout (EIFS). @@ -169,14 +169,14 @@ #define RTW_TCR_SAT __BIT(24) /* Max DMA Burst Size per Tx DMA Burst */ #define RTW_TCR_MXDMA_MASK __BITS(23,21) -#define RTW_TCR_MXDMA_16 SHIFTIN(0, RTW_TCR_MXDMA_MASK) -#define RTW_TCR_MXDMA_32 SHIFTIN(1, RTW_TCR_MXDMA_MASK) -#define RTW_TCR_MXDMA_64 SHIFTIN(2, RTW_TCR_MXDMA_MASK) -#define RTW_TCR_MXDMA_128 SHIFTIN(3, RTW_TCR_MXDMA_MASK) -#define RTW_TCR_MXDMA_256 SHIFTIN(4, RTW_TCR_MXDMA_MASK) -#define RTW_TCR_MXDMA_512 SHIFTIN(5, RTW_TCR_MXDMA_MASK) -#define RTW_TCR_MXDMA_1024 SHIFTIN(6, RTW_TCR_MXDMA_MASK) -#define RTW_TCR_MXDMA_2048 SHIFTIN(7, RTW_TCR_MXDMA_MASK) +#define RTW_TCR_MXDMA_16 __SHIFTIN(0, RTW_TCR_MXDMA_MASK) +#define RTW_TCR_MXDMA_32 __SHIFTIN(1, RTW_TCR_MXDMA_MASK) +#define RTW_TCR_MXDMA_64 __SHIFTIN(2, RTW_TCR_MXDMA_MASK) +#define RTW_TCR_MXDMA_128 __SHIFTIN(3, RTW_TCR_MXDMA_MASK) +#define RTW_TCR_MXDMA_256 __SHIFTIN(4, RTW_TCR_MXDMA_MASK) +#define RTW_TCR_MXDMA_512 __SHIFTIN(5, RTW_TCR_MXDMA_MASK) +#define RTW_TCR_MXDMA_1024 __SHIFTIN(6, RTW_TCR_MXDMA_MASK) +#define RTW_TCR_MXDMA_2048 __SHIFTIN(7, RTW_TCR_MXDMA_MASK) /* disable 802.11 random backoff */ #define RTW_TCR_DISCW __BIT(20) @@ -186,10 +186,10 @@ /* Loopback Test: disables TXI/TXQ outputs. */ #define RTW_TCR_LBK_MASK __BITS(18,17) -#define RTW_TCR_LBK_NORMAL SHIFTIN(0, RTW_TCR_LBK_MASK) /* normal ops */ -#define RTW_TCR_LBK_MAC SHIFTIN(1, RTW_TCR_LBK_MASK) /* MAC loopback */ -#define RTW_TCR_LBK_BBP SHIFTIN(2, RTW_TCR_LBK_MASK) /* baseband loop. */ -#define RTW_TCR_LBK_CONT SHIFTIN(3, RTW_TCR_LBK_MASK) /* continuous Tx */ +#define RTW_TCR_LBK_NORMAL __SHIFTIN(0, RTW_TCR_LBK_MASK) /* normal ops */ +#define RTW_TCR_LBK_MAC __SHIFTIN(1, RTW_TCR_LBK_MASK) /* MAC loopback */ +#define RTW_TCR_LBK_BBP __SHIFTIN(2, RTW_TCR_LBK_MASK) /* baseband loop. */ +#define RTW_TCR_LBK_CONT __SHIFTIN(3, RTW_TCR_LBK_MASK) /* continuous Tx */ #define RTW_TCR_CRC __BIT(16) /* 0: RTL8180 appends CRC32 * 1: host appends CRC32 @@ -228,25 +228,25 @@ * bytes are received */ #define RTW_RCR_RXFTH_MASK __BITS(15,13) -#define RTW_RCR_RXFTH_64 SHIFTIN(2, RTW_RCR_RXFTH_MASK) -#define RTW_RCR_RXFTH_128 SHIFTIN(3, RTW_RCR_RXFTH_MASK) -#define RTW_RCR_RXFTH_256 SHIFTIN(4, RTW_RCR_RXFTH_MASK) -#define RTW_RCR_RXFTH_512 SHIFTIN(5, RTW_RCR_RXFTH_MASK) -#define RTW_RCR_RXFTH_1024 SHIFTIN(6, RTW_RCR_RXFTH_MASK) -#define RTW_RCR_RXFTH_WHOLE SHIFTIN(7, RTW_RCR_RXFTH_MASK) +#define RTW_RCR_RXFTH_64 __SHIFTIN(2, RTW_RCR_RXFTH_MASK) +#define RTW_RCR_RXFTH_128 __SHIFTIN(3, RTW_RCR_RXFTH_MASK) +#define RTW_RCR_RXFTH_256 __SHIFTIN(4, RTW_RCR_RXFTH_MASK) +#define RTW_RCR_RXFTH_512 __SHIFTIN(5, RTW_RCR_RXFTH_MASK) +#define RTW_RCR_RXFTH_1024 __SHIFTIN(6, RTW_RCR_RXFTH_MASK) +#define RTW_RCR_RXFTH_WHOLE __SHIFTIN(7, RTW_RCR_RXFTH_MASK) #define RTW_RCR_AICV __BIT(12)/* accept frames w/ ICV errors */ /* Max DMA Burst Size per Rx DMA Burst */ #define RTW_RCR_MXDMA_MASK __BITS(10,8) -#define RTW_RCR_MXDMA_16 SHIFTIN(0, RTW_RCR_MXDMA_MASK) -#define RTW_RCR_MXDMA_32 SHIFTIN(1, RTW_RCR_MXDMA_MASK) -#define RTW_RCR_MXDMA_64 SHIFTIN(2, RTW_RCR_MXDMA_MASK) -#define RTW_RCR_MXDMA_128 SHIFTIN(3, RTW_RCR_MXDMA_MASK) -#define RTW_RCR_MXDMA_256 SHIFTIN(4, RTW_RCR_MXDMA_MASK) -#define RTW_RCR_MXDMA_512 SHIFTIN(5, RTW_RCR_MXDMA_MASK) -#define RTW_RCR_MXDMA_1024 SHIFTIN(6, RTW_RCR_MXDMA_MASK) -#define RTW_RCR_MXDMA_UNLIMITED SHIFTIN(7, RTW_RCR_MXDMA_MASK) +#define RTW_RCR_MXDMA_16 __SHIFTIN(0, RTW_RCR_MXDMA_MASK) +#define RTW_RCR_MXDMA_32 __SHIFTIN(1, RTW_RCR_MXDMA_MASK) +#define RTW_RCR_MXDMA_64 __SHIFTIN(2, RTW_RCR_MXDMA_MASK) +#define RTW_RCR_MXDMA_128 __SHIFTIN(3, RTW_RCR_MXDMA_MASK) +#define RTW_RCR_MXDMA_256 __SHIFTIN(4, RTW_RCR_MXDMA_MASK) +#define RTW_RCR_MXDMA_512 __SHIFTIN(5, RTW_RCR_MXDMA_MASK) +#define RTW_RCR_MXDMA_1024 __SHIFTIN(6, RTW_RCR_MXDMA_MASK) +#define RTW_RCR_MXDMA_UNLIMITED __SHIFTIN(7, RTW_RCR_MXDMA_MASK) /* EEPROM type, read-only. 1: EEPROM is 93c56, 0: 93c46 */ #define RTW_RCR_9356SEL __BIT(6) @@ -295,19 +295,19 @@ */ #define RTW_9346CR 0x50 /* 93c46/93c56 Command Register, 8b */ #define RTW_9346CR_EEM_MASK __BITS(7,6) /* Operating Mode */ -#define RTW_9346CR_EEM_NORMAL SHIFTIN(0, RTW_9346CR_EEM_MASK) +#define RTW_9346CR_EEM_NORMAL __SHIFTIN(0, RTW_9346CR_EEM_MASK) /* Load the EEPROM. Reset registers to defaults. * Takes ~2ms. RTL8180 indicates completion with RTW_9346CR_EEM_NORMAL. * XXX RTL8180 only? */ -#define RTW_9346CR_EEM_AUTOLOAD SHIFTIN(1, RTW_9346CR_EEM_MASK) +#define RTW_9346CR_EEM_AUTOLOAD __SHIFTIN(1, RTW_9346CR_EEM_MASK) /* Disable network & bus-master operations and enable * _EECS, _EESK, _EEDI, _EEDO. * XXX RTL8180 only? */ -#define RTW_9346CR_EEM_PROGRAM SHIFTIN(2, RTW_9346CR_EEM_MASK) +#define RTW_9346CR_EEM_PROGRAM __SHIFTIN(2, RTW_9346CR_EEM_MASK) /* Enable RTW_CONFIG[0123] registers. */ -#define RTW_9346CR_EEM_CONFIG SHIFTIN(3, RTW_9346CR_EEM_MASK) +#define RTW_9346CR_EEM_CONFIG __SHIFTIN(3, RTW_9346CR_EEM_MASK) /* EEPROM pin status/control in _EEM_CONFIG, _EEM_AUTOLOAD modes. * XXX RTL8180 only? */ @@ -337,10 +337,10 @@ /* _RTW_CONFIG0_GL_* is what the datasheet says, but RTW_CONFIG0_GL_* * work. */ -#define _RTW_CONFIG0_GL_USA SHIFTIN(3, RTW_CONFIG0_GL_MASK) -#define RTW_CONFIG0_GL_EUROPE SHIFTIN(2, RTW_CONFIG0_GL_MASK) -#define RTW_CONFIG0_GL_JAPAN SHIFTIN(1, RTW_CONFIG0_GL_MASK) -#define RTW_CONFIG0_GL_USA SHIFTIN(0, RTW_CONFIG0_GL_MASK) +#define _RTW_CONFIG0_GL_USA __SHIFTIN(3, RTW_CONFIG0_GL_MASK) +#define RTW_CONFIG0_GL_EUROPE __SHIFTIN(2, RTW_CONFIG0_GL_MASK) +#define RTW_CONFIG0_GL_JAPAN __SHIFTIN(1, RTW_CONFIG0_GL_MASK) +#define RTW_CONFIG0_GL_USA __SHIFTIN(0, RTW_CONFIG0_GL_MASK) /* RTL8181 datasheet says RTW_CONFIG0_GL_JAPAN = 0. */ #define RTW_CONFIG1 0x52 /* Configuration Register 1, 8b */ @@ -355,10 +355,10 @@ * RTW_CONFIG1_LEDS_LINKACT_INFRA Link/Activity Infrastructure */ #define RTW_CONFIG1_LEDS_MASK __BITS(7,6) -#define RTW_CONFIG1_LEDS_ACT_INFRA SHIFTIN(0, RTW_CONFIG1_LEDS_MASK) -#define RTW_CONFIG1_LEDS_ACT_LINK SHIFTIN(1, RTW_CONFIG1_LEDS_MASK) -#define RTW_CONFIG1_LEDS_TX_RX SHIFTIN(2, RTW_CONFIG1_LEDS_MASK) -#define RTW_CONFIG1_LEDS_LINKACT_INFRA SHIFTIN(3, RTW_CONFIG1_LEDS_MASK) +#define RTW_CONFIG1_LEDS_ACT_INFRA __SHIFTIN(0, RTW_CONFIG1_LEDS_MASK) +#define RTW_CONFIG1_LEDS_ACT_LINK __SHIFTIN(1, RTW_CONFIG1_LEDS_MASK) +#define RTW_CONFIG1_LEDS_TX_RX __SHIFTIN(2, RTW_CONFIG1_LEDS_MASK) +#define RTW_CONFIG1_LEDS_LINKACT_INFRA __SHIFTIN(3, RTW_CONFIG1_LEDS_MASK) /* LWAKE Output Signal. Only applicable to Cardbus. Pulse width is 150ms. * @@ -413,42 +413,42 @@ /* * Maxim On/Sleep/Off control */ -#define RTW_ANAPARM_RFPOW_MAXIM_ON SHIFTIN(0x8, RTW_ANAPARM_RFPOW1_MASK) +#define RTW_ANAPARM_RFPOW_MAXIM_ON __SHIFTIN(0x8, RTW_ANAPARM_RFPOW1_MASK) /* reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF; */ -#define RTW_ANAPARM_RFPOW_MAXIM_SLEEP SHIFTIN(0x378, RTW_ANAPARM_RFPOW1_MASK) +#define RTW_ANAPARM_RFPOW_MAXIM_SLEEP __SHIFTIN(0x378, RTW_ANAPARM_RFPOW1_MASK) /* reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF; */ -#define RTW_ANAPARM_RFPOW_MAXIM_OFF SHIFTIN(0x379, RTW_ANAPARM_RFPOW1_MASK) +#define RTW_ANAPARM_RFPOW_MAXIM_OFF __SHIFTIN(0x379, RTW_ANAPARM_RFPOW1_MASK) /* * RFMD On/Sleep/Off control */ -#define RTW_ANAPARM_RFPOW_RFMD_ON SHIFTIN(0x408, RTW_ANAPARM_RFPOW1_MASK) +#define RTW_ANAPARM_RFPOW_RFMD_ON __SHIFTIN(0x408, RTW_ANAPARM_RFPOW1_MASK) /* reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF; */ -#define RTW_ANAPARM_RFPOW_RFMD_SLEEP SHIFTIN(0x378, RTW_ANAPARM_RFPOW1_MASK) +#define RTW_ANAPARM_RFPOW_RFMD_SLEEP __SHIFTIN(0x378, RTW_ANAPARM_RFPOW1_MASK) /* reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF; */ -#define RTW_ANAPARM_RFPOW_RFMD_OFF SHIFTIN(0x379, RTW_ANAPARM_RFPOW1_MASK) +#define RTW_ANAPARM_RFPOW_RFMD_OFF __SHIFTIN(0x379, RTW_ANAPARM_RFPOW1_MASK) /* * Philips On/Sleep/Off control */ #define RTW_ANAPARM_RFPOW_ANA_PHILIPS_ON \ - SHIFTIN(0x328, RTW_ANAPARM_RFPOW1_MASK) + __SHIFTIN(0x328, RTW_ANAPARM_RFPOW1_MASK) #define RTW_ANAPARM_RFPOW_DIG_PHILIPS_ON \ - SHIFTIN(0x008, RTW_ANAPARM_RFPOW1_MASK) + __SHIFTIN(0x008, RTW_ANAPARM_RFPOW1_MASK) /* reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF; */ #define RTW_ANAPARM_RFPOW_PHILIPS_SLEEP\ - SHIFTIN(0x378, RTW_ANAPARM_RFPOW1_MASK) + __SHIFTIN(0x378, RTW_ANAPARM_RFPOW1_MASK) /* reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF; */ #define RTW_ANAPARM_RFPOW_PHILIPS_OFF\ - SHIFTIN(0x379, RTW_ANAPARM_RFPOW1_MASK) + __SHIFTIN(0x379, RTW_ANAPARM_RFPOW1_MASK) -#define RTW_ANAPARM_RFPOW_PHILIPS_ON SHIFTIN(0x328, RTW_ANAPARM_RFPOW1_MASK) +#define RTW_ANAPARM_RFPOW_PHILIPS_ON __SHIFTIN(0x328, RTW_ANAPARM_RFPOW1_MASK) #define RTW_ANAPARM_CARDSP_MASK __BITS(19,0) /* undocumented * card-specific @@ -460,13 +460,13 @@ /* Network Type and Link Status */ #define RTW_MSR_NETYPE_MASK __BITS(3,2) /* AP, XXX RTL8181 only? */ -#define RTW_MSR_NETYPE_AP_OK SHIFTIN(3, RTW_MSR_NETYPE_MASK) +#define RTW_MSR_NETYPE_AP_OK __SHIFTIN(3, RTW_MSR_NETYPE_MASK) /* infrastructure link ok */ -#define RTW_MSR_NETYPE_INFRA_OK SHIFTIN(2, RTW_MSR_NETYPE_MASK) +#define RTW_MSR_NETYPE_INFRA_OK __SHIFTIN(2, RTW_MSR_NETYPE_MASK) /* ad-hoc link ok */ -#define RTW_MSR_NETYPE_ADHOC_OK SHIFTIN(1, RTW_MSR_NETYPE_MASK) +#define RTW_MSR_NETYPE_ADHOC_OK __SHIFTIN(1, RTW_MSR_NETYPE_MASK) /* no link */ -#define RTW_MSR_NETYPE_NOLINK SHIFTIN(0, RTW_MSR_NETYPE_MASK) +#define RTW_MSR_NETYPE_NOLINK __SHIFTIN(0, RTW_MSR_NETYPE_MASK) #define RTW_CONFIG3 0x59 /* Configuration Register 3, 8b */ #define RTW_CONFIG3_GNTSEL __BIT(7) /* Grant Select, read-only */ @@ -525,9 +525,9 @@ */ /* Radio Front-End Programming Method */ #define RTW_CONFIG4_RFTYPE_MASK __BITS(1,0) -#define RTW_CONFIG4_RFTYPE_INTERSIL SHIFTIN(1, RTW_CONFIG4_RFTYPE_MASK) -#define RTW_CONFIG4_RFTYPE_RFMD SHIFTIN(2, RTW_CONFIG4_RFTYPE_MASK) -#define RTW_CONFIG4_RFTYPE_PHILIPS SHIFTIN(3, RTW_CONFIG4_RFTYPE_MASK) +#define RTW_CONFIG4_RFTYPE_INTERSIL __SHIFTIN(1, RTW_CONFIG4_RFTYPE_MASK) +#define RTW_CONFIG4_RFTYPE_RFMD __SHIFTIN(2, RTW_CONFIG4_RFTYPE_MASK) +#define RTW_CONFIG4_RFTYPE_PHILIPS __SHIFTIN(3, RTW_CONFIG4_RFTYPE_MASK) #define RTW_TESTR 0x5B /* TEST mode register, 8b */ @@ -545,8 +545,8 @@ #define RTW_SCR 0x5f /* Security Configuration Register, 8b */ #define RTW_SCR_KM_MASK __BITS(5,4) /* Key Mode */ -#define RTW_SCR_KM_WEP104 SHIFTIN(1, RTW_SCR_KM_MASK) -#define RTW_SCR_KM_WEP40 SHIFTIN(0, RTW_SCR_KM_MASK) +#define RTW_SCR_KM_WEP104 __SHIFTIN(1, RTW_SCR_KM_MASK) +#define RTW_SCR_KM_WEP40 __SHIFTIN(0, RTW_SCR_KM_MASK) #define RTW_SCR_TXSECON __BIT(1)/* Enable Tx WEP. Invalid if * neither RTW_CONFIG0_WEP40 nor * RTW_CONFIG0_WEP104 is set. @@ -609,10 +609,10 @@ * 0: MAC bangs bits */ #define RTW_PHYCFG_MAC_RFTYPE_MASK __BITS(29,28) -#define RTW_PHYCFG_MAC_RFTYPE_INTERSIL SHIFTIN(0, RTW_PHYCFG_MAC_RFTYPE_MASK) -#define RTW_PHYCFG_MAC_RFTYPE_RFMD SHIFTIN(1, RTW_PHYCFG_MAC_RFTYPE_MASK) +#define RTW_PHYCFG_MAC_RFTYPE_INTERSIL __SHIFTIN(0, RTW_PHYCFG_MAC_RFTYPE_MASK) +#define RTW_PHYCFG_MAC_RFTYPE_RFMD __SHIFTIN(1, RTW_PHYCFG_MAC_RFTYPE_MASK) #define RTW_PHYCFG_MAC_RFTYPE_GCT RTW_PHYCFG_MAC_RFTYPE_RFMD -#define RTW_PHYCFG_MAC_RFTYPE_PHILIPS SHIFTIN(3, RTW_PHYCFG_MAC_RFTYPE_MASK) +#define RTW_PHYCFG_MAC_RFTYPE_PHILIPS __SHIFTIN(3, RTW_PHYCFG_MAC_RFTYPE_MASK) #define RTW_PHYCFG_MAC_PHILIPS_ADDR_MASK __BITS(27,24) #define RTW_PHYCFG_MAC_PHILIPS_DATA_MASK __BITS(23,0) #define RTW_PHYCFG_MAC_MAXIM_LODATA_MASK __BITS(27,24) @@ -850,18 +850,18 @@ struct rtw_txdesc { #define RTW_TXCTL0_LS __BIT(28) /* last segment */ #define RTW_TXCTL0_RATE_MASK __BITS(27,24) /* Tx rate */ -#define RTW_TXCTL0_RATE_1MBPS SHIFTIN(0, RTW_TXCTL0_RATE_MASK) -#define RTW_TXCTL0_RATE_2MBPS SHIFTIN(1, RTW_TXCTL0_RATE_MASK) -#define RTW_TXCTL0_RATE_5MBPS SHIFTIN(2, RTW_TXCTL0_RATE_MASK) -#define RTW_TXCTL0_RATE_11MBPS SHIFTIN(3, RTW_TXCTL0_RATE_MASK) +#define RTW_TXCTL0_RATE_1MBPS __SHIFTIN(0, RTW_TXCTL0_RATE_MASK) +#define RTW_TXCTL0_RATE_2MBPS __SHIFTIN(1, RTW_TXCTL0_RATE_MASK) +#define RTW_TXCTL0_RATE_5MBPS __SHIFTIN(2, RTW_TXCTL0_RATE_MASK) +#define RTW_TXCTL0_RATE_11MBPS __SHIFTIN(3, RTW_TXCTL0_RATE_MASK) #define RTW_TXCTL0_RTSEN __BIT(23) /* RTS Enable */ #define RTW_TXCTL0_RTSRATE_MASK __BITS(22,19) /* Tx rate */ -#define RTW_TXCTL0_RTSRATE_1MBPS SHIFTIN(0, RTW_TXCTL0_RTSRATE_MASK) -#define RTW_TXCTL0_RTSRATE_2MBPS SHIFTIN(1, RTW_TXCTL0_RTSRATE_MASK) -#define RTW_TXCTL0_RTSRATE_5MBPS SHIFTIN(2, RTW_TXCTL0_RTSRATE_MASK) -#define RTW_TXCTL0_RTSRATE_11MBPS SHIFTIN(3, RTW_TXCTL0_RTSRATE_MASK) +#define RTW_TXCTL0_RTSRATE_1MBPS __SHIFTIN(0, RTW_TXCTL0_RTSRATE_MASK) +#define RTW_TXCTL0_RTSRATE_2MBPS __SHIFTIN(1, RTW_TXCTL0_RTSRATE_MASK) +#define RTW_TXCTL0_RTSRATE_5MBPS __SHIFTIN(2, RTW_TXCTL0_RTSRATE_MASK) +#define RTW_TXCTL0_RTSRATE_11MBPS __SHIFTIN(3, RTW_TXCTL0_RTSRATE_MASK) #define RTW_TXCTL0_BEACON __BIT(18) /* packet is a beacon */ #define RTW_TXCTL0_MOREFRAG __BIT(17) /* another fragment @@ -928,10 +928,10 @@ struct rtw_rxdesc { */ #define RTW_RXSTAT_RSVD1 __BIT(24) /* reserved */ #define RTW_RXSTAT_RATE_MASK __BITS(23,20) /* Rx rate */ -#define RTW_RXSTAT_RATE_1MBPS SHIFTIN(0, RTW_RXSTAT_RATE_MASK) -#define RTW_RXSTAT_RATE_2MBPS SHIFTIN(1, RTW_RXSTAT_RATE_MASK) -#define RTW_RXSTAT_RATE_5MBPS SHIFTIN(2, RTW_RXSTAT_RATE_MASK) -#define RTW_RXSTAT_RATE_11MBPS SHIFTIN(3, RTW_RXSTAT_RATE_MASK) +#define RTW_RXSTAT_RATE_1MBPS __SHIFTIN(0, RTW_RXSTAT_RATE_MASK) +#define RTW_RXSTAT_RATE_2MBPS __SHIFTIN(1, RTW_RXSTAT_RATE_MASK) +#define RTW_RXSTAT_RATE_5MBPS __SHIFTIN(2, RTW_RXSTAT_RATE_MASK) +#define RTW_RXSTAT_RATE_11MBPS __SHIFTIN(3, RTW_RXSTAT_RATE_MASK) #define RTW_RXSTAT_MIC __BIT(19) /* XXX from reference driver */ #define RTW_RXSTAT_MAR __BIT(18) /* is multicast */ #define RTW_RXSTAT_PAR __BIT(17) /* matches RTL8180's MAC */ diff --git a/sys/dev/ic/sa2400reg.h b/sys/dev/ic/sa2400reg.h index 5b59cfc73df..e72d82b3756 100644 --- a/sys/dev/ic/sa2400reg.h +++ b/sys/dev/ic/sa2400reg.h @@ -1,4 +1,4 @@ -/* $NetBSD: sa2400reg.h,v 1.6 2006/03/08 08:26:50 dyoung Exp $ */ +/* $NetBSD: sa2400reg.h,v 1.7 2006/08/31 19:24:38 dyoung Exp $ */ /* * Copyright (c) 2005 David Young. All rights reserved. @@ -61,10 +61,10 @@ * 4 to 1023, default 11 */ #define SA2400_SYNB_L_MASK __BITS(11,10) /* lock detect mode */ -#define SA2400_SYNB_L_INACTIVE0 SHIFTIN(0, SA2400_SYNB_L_MASK) -#define SA2400_SYNB_L_INACTIVE1 SHIFTIN(1, SA2400_SYNB_L_MASK) -#define SA2400_SYNB_L_NORMAL SHIFTIN(2, SA2400_SYNB_L_MASK) -#define SA2400_SYNB_L_INACTIVE2 SHIFTIN(3, SA2400_SYNB_L_MASK) +#define SA2400_SYNB_L_INACTIVE0 __SHIFTIN(0, SA2400_SYNB_L_MASK) +#define SA2400_SYNB_L_INACTIVE1 __SHIFTIN(1, SA2400_SYNB_L_MASK) +#define SA2400_SYNB_L_NORMAL __SHIFTIN(2, SA2400_SYNB_L_MASK) +#define SA2400_SYNB_L_INACTIVE2 __SHIFTIN(3, SA2400_SYNB_L_MASK) #define SA2400_SYNB_ON __BIT(9) /* power on/off, * 0: inverted chip mode control @@ -81,10 +81,10 @@ #define SA2400_SYNC_CP_MASK __BITS(7,6) /* charge pump current * setting */ -#define SA2400_SYNC_CP_NORMAL_ SHIFTIN(0, SA2400_SYNC_CP_MASK) -#define SA2400_SYNC_CP_THIRD_ SHIFTIN(1, SA2400_SYNC_CP_MASK) -#define SA2400_SYNC_CP_NORMAL SHIFTIN(2, SA2400_SYNC_CP_MASK) /* recommended */ -#define SA2400_SYNC_CP_THIRD SHIFTIN(3, SA2400_SYNC_CP_MASK) +#define SA2400_SYNC_CP_NORMAL_ __SHIFTIN(0, SA2400_SYNC_CP_MASK) +#define SA2400_SYNC_CP_THIRD_ __SHIFTIN(1, SA2400_SYNC_CP_MASK) +#define SA2400_SYNC_CP_NORMAL __SHIFTIN(2, SA2400_SYNC_CP_MASK) /* recommended */ +#define SA2400_SYNC_CP_THIRD __SHIFTIN(3, SA2400_SYNC_CP_MASK) #define SA2400_SYNC_SM_MASK __BITS(5,3) /* comparison divider select, * 0 to 4, extra division @@ -144,19 +144,19 @@ */ /* main operating mode */ #define SA2400_OPMODE_MODE_MASK __BITS(3,0) -#define SA2400_OPMODE_MODE_SLEEP SHIFTIN(0, SA2400_OPMODE_MODE_MASK) -#define SA2400_OPMODE_MODE_TXRX SHIFTIN(1, SA2400_OPMODE_MODE_MASK) -#define SA2400_OPMODE_MODE_WAIT SHIFTIN(2, SA2400_OPMODE_MODE_MASK) -#define SA2400_OPMODE_MODE_RXMGC SHIFTIN(3, SA2400_OPMODE_MODE_MASK) -#define SA2400_OPMODE_MODE_FCALIB SHIFTIN(4, SA2400_OPMODE_MODE_MASK) -#define SA2400_OPMODE_MODE_DCALIB SHIFTIN(5, SA2400_OPMODE_MODE_MASK) -#define SA2400_OPMODE_MODE_FASTTXRXMGC SHIFTIN(6, SA2400_OPMODE_MODE_MASK) -#define SA2400_OPMODE_MODE_RESET SHIFTIN(7, SA2400_OPMODE_MODE_MASK) -#define SA2400_OPMODE_MODE_VCOCALIB SHIFTIN(8, SA2400_OPMODE_MODE_MASK) +#define SA2400_OPMODE_MODE_SLEEP __SHIFTIN(0, SA2400_OPMODE_MODE_MASK) +#define SA2400_OPMODE_MODE_TXRX __SHIFTIN(1, SA2400_OPMODE_MODE_MASK) +#define SA2400_OPMODE_MODE_WAIT __SHIFTIN(2, SA2400_OPMODE_MODE_MASK) +#define SA2400_OPMODE_MODE_RXMGC __SHIFTIN(3, SA2400_OPMODE_MODE_MASK) +#define SA2400_OPMODE_MODE_FCALIB __SHIFTIN(4, SA2400_OPMODE_MODE_MASK) +#define SA2400_OPMODE_MODE_DCALIB __SHIFTIN(5, SA2400_OPMODE_MODE_MASK) +#define SA2400_OPMODE_MODE_FASTTXRXMGC __SHIFTIN(6, SA2400_OPMODE_MODE_MASK) +#define SA2400_OPMODE_MODE_RESET __SHIFTIN(7, SA2400_OPMODE_MODE_MASK) +#define SA2400_OPMODE_MODE_VCOCALIB __SHIFTIN(8, SA2400_OPMODE_MODE_MASK) #define SA2400_OPMODE_DEFAULTS \ (SA2400_OPMODE_XO | SA2400_OPMODE_RXLV | SA2400_OPMODE_CLK | \ - SA2400_OPMODE_I0P3 | SHIFTIN(3, SA2400_OPMODE_FILTTUNE_MASK)) + SA2400_OPMODE_I0P3 | __SHIFTIN(3, SA2400_OPMODE_FILTTUNE_MASK)) #define SA2400_AGC 5 /* AGC adjustment */ #define SA2400_AGC_TARGETSIGN __BIT(23) /* fine-tune AGC target: diff --git a/sys/dev/ic/si4136reg.h b/sys/dev/ic/si4136reg.h index 41a9c0ab44b..5bed51e0769 100644 --- a/sys/dev/ic/si4136reg.h +++ b/sys/dev/ic/si4136reg.h @@ -1,4 +1,4 @@ -/* $NetBSD: si4136reg.h,v 1.4 2006/03/08 08:26:50 dyoung Exp $ */ +/* $NetBSD: si4136reg.h,v 1.5 2006/08/31 19:24:38 dyoung Exp $ */ /* * Copyright (c) 2005 David Young. All rights reserved. @@ -46,11 +46,11 @@ #define SI4126_MAIN 0 /* main configuration */ #define SI4126_MAIN_AUXSEL_MASK __BITS(13, 12) /* aux. output pin function */ /* reserved */ -#define SI4126_MAIN_AUXSEL_RSVD SHIFTIN(0x0, SI4126_MAIN_AUXSEL_MASK) +#define SI4126_MAIN_AUXSEL_RSVD __SHIFTIN(0x0, SI4126_MAIN_AUXSEL_MASK) /* force low */ -#define SI4126_MAIN_AUXSEL_FRCLOW SHIFTIN(0x1, SI4126_MAIN_AUXSEL_MASK) +#define SI4126_MAIN_AUXSEL_FRCLOW __SHIFTIN(0x1, SI4126_MAIN_AUXSEL_MASK) /* Lock Detect (LDETB) */ -#define SI4126_MAIN_AUXSEL_LDETB SHIFTIN(0x3, SI4126_MAIN_AUXSEL_MASK) +#define SI4126_MAIN_AUXSEL_LDETB __SHIFTIN(0x3, SI4126_MAIN_AUXSEL_MASK) #define SI4126_MAIN_IFDIV_MASK __BITS(11, 10) /* IFOUT = IFVCO * frequency / 2**IFDIV. |
