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authordrochner <drochner@NetBSD.org>1998-12-04 17:30:55 +0000
committerdrochner <drochner@NetBSD.org>1998-12-04 17:30:55 +0000
commit9175cc0ddfb79487f6b6bf79b15543df742af166 (patch)
treeeeb16ef62ce1e1d357b71085da5efd05931c5a21 /sys/dev
parent79410cf933e854e256a51693390b1eb2758315db (diff)
The chipset manual doesn't tell the truth about the channel enable
register bits. Replace by experimental result.
Diffstat (limited to 'sys/dev')
-rw-r--r--sys/dev/pci/pciide_sis_reg.h6
1 files changed, 3 insertions, 3 deletions
diff --git a/sys/dev/pci/pciide_sis_reg.h b/sys/dev/pci/pciide_sis_reg.h
index ba8aca28b37..965e4309673 100644
--- a/sys/dev/pci/pciide_sis_reg.h
+++ b/sys/dev/pci/pciide_sis_reg.h
@@ -1,4 +1,4 @@
-/* $NetBSD: pciide_sis_reg.h,v 1.4 1998/12/03 17:29:01 bouyer Exp $ */
+/* $NetBSD: pciide_sis_reg.h,v 1.5 1998/12/04 17:30:55 drochner Exp $ */
/*
* Copyright (c) 1998 Manuel Bouyer.
@@ -50,8 +50,8 @@
#define SIS_CTRL0_PCIBURST 0x80
#define SIS_CTRL0_FAST_PW 0x20
#define SIS_CTRL0_BO 0x08
-#define SIS_CTRL0_CHAN0_EN 0x04
-#define SIS_CTRL0_CHAN1_EN 0x02
+#define SIS_CTRL0_CHAN0_EN 0x02 /* manual (v2.0) is wrong!!! */
+#define SIS_CTRL0_CHAN1_EN 0x04 /* manual (v2.0) is wrong!!! */
/* IDE general control register 1 (8 bits) */
#define SIS_CTRL1 0x4b