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authorbouyer <bouyer@NetBSD.org>2003-06-28 23:13:26 +0000
committerbouyer <bouyer@NetBSD.org>2003-06-28 23:13:26 +0000
commit9a6b838fb4e5fa7bc49bafb1530c0e5c051b4057 (patch)
tree18a0842d0fa85774ec70b1045e251483f63d58d2 /sys/dev
parentab8781bdb6aa656445553a42543750d062588228 (diff)
Correct setup of General Purpose Register for PDC20265 (Ultra/100) and newer.
From Andreas Johansson in private mail.
Diffstat (limited to 'sys/dev')
-rw-r--r--sys/dev/pci/pciide.c8
-rw-r--r--sys/dev/pci/pciide_pdc202xx_reg.h5
2 files changed, 8 insertions, 5 deletions
diff --git a/sys/dev/pci/pciide.c b/sys/dev/pci/pciide.c
index 636ba8ec99b..c28bc6d9841 100644
--- a/sys/dev/pci/pciide.c
+++ b/sys/dev/pci/pciide.c
@@ -1,4 +1,4 @@
-/* $NetBSD: pciide.c,v 1.193 2003/06/28 23:04:11 bouyer Exp $ */
+/* $NetBSD: pciide.c,v 1.194 2003/06/28 23:13:26 bouyer Exp $ */
/*
@@ -76,7 +76,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pciide.c,v 1.193 2003/06/28 23:04:11 bouyer Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pciide.c,v 1.194 2003/06/28 23:13:26 bouyer Exp $");
#ifndef WDCDEBUG
#define WDCDEBUG
@@ -4394,7 +4394,9 @@ pdc202xx_chip_map(sc, pa)
}
mode = PDC2xx_SCR_DMA;
- if (PDC_IS_262(sc)) {
+ if (PDC_IS_265(sc)) {
+ mode = PDC2xx_SCR_SET_GEN(mode, PDC265_SCR_GEN_LAT);
+ } else if (PDC_IS_262(sc)) {
mode = PDC2xx_SCR_SET_GEN(mode, PDC262_SCR_GEN_LAT);
} else {
/* the BIOS set it up this way */
diff --git a/sys/dev/pci/pciide_pdc202xx_reg.h b/sys/dev/pci/pciide_pdc202xx_reg.h
index 532b9376207..35ba4e7959a 100644
--- a/sys/dev/pci/pciide_pdc202xx_reg.h
+++ b/sys/dev/pci/pciide_pdc202xx_reg.h
@@ -1,4 +1,4 @@
-/* $NetBSD: pciide_pdc202xx_reg.h,v 1.9 2003/04/28 05:20:33 nakayama Exp $ */
+/* $NetBSD: pciide_pdc202xx_reg.h,v 1.10 2003/06/28 23:13:27 bouyer Exp $ */
/*
* Copyright (c) 1999 Manuel Bouyer.
@@ -90,8 +90,9 @@
#define PDC2xx_SCR_FLOAT 0x08000000
#define PDC2xx_SCR_RSET 0x10000000
#define PDC2xx_SCR_TST 0x20000000
-/* Values for "General Purpose Register" (PDC20262 only) */
+/* Values for "General Purpose Register" (PDC2026{2|5} only) */
#define PDC262_SCR_GEN_LAT 0x20
+#define PDC265_SCR_GEN_LAT 0x03
/* ATAPI port ((PDC20262 only) (4 bytes) */
#define PDC262_ATAPI(chan) (0x20 + (4 * (chan)))