diff options
| author | mycroft <mycroft@NetBSD.org> | 1995-10-09 09:49:30 +0000 |
|---|---|---|
| committer | mycroft <mycroft@NetBSD.org> | 1995-10-09 09:49:30 +0000 |
| commit | b216bead497cf00b73fd04c0d54fc789d34c2efd (patch) | |
| tree | f99c340e56fcc701786c356dd9fb5be183078457 /sys/dev | |
| parent | d04fcadcc2e857a2d9caac5891c0662940e8a2c5 (diff) | |
Add an Adaptec 2940 driver, by John Aycock and Justin Gibbs, ported to NetBSD by Stefan
Grefen, with several bug fixes by me.
Diffstat (limited to 'sys/dev')
| -rw-r--r-- | sys/dev/ic/aic7xxx.c | 2227 | ||||
| -rw-r--r-- | sys/dev/ic/aic7xxxvar.h | 168 | ||||
| -rw-r--r-- | sys/dev/microcode/Makefile.inc | 1 | ||||
| -rw-r--r-- | sys/dev/microcode/aic7xxx/Makefile.inc | 10 | ||||
| -rw-r--r-- | sys/dev/microcode/aic7xxx/aic7xxx.seq | 1262 | ||||
| -rw-r--r-- | sys/dev/microcode/aic7xxx/aic7xxx_asm.1 | 70 | ||||
| -rw-r--r-- | sys/dev/microcode/aic7xxx/aic7xxx_asm.c | 651 | ||||
| -rw-r--r-- | sys/dev/pci/aic7870.c | 101 |
8 files changed, 4490 insertions, 0 deletions
diff --git a/sys/dev/ic/aic7xxx.c b/sys/dev/ic/aic7xxx.c new file mode 100644 index 00000000000..dd2ddf0a9fc --- /dev/null +++ b/sys/dev/ic/aic7xxx.c @@ -0,0 +1,2227 @@ +/* $NetBSD: aic7xxx.c,v 1.1 1995/10/09 09:49:30 mycroft Exp $ */ + +/* + * Generic driver for the aic7xxx based adaptec SCSI controllers + * Copyright (c) 1994, 1995 Justin T. Gibbs. + * All rights reserved. + * + * Product specific probe and attach routines can be found in: + * i386/isa/aic7770.c 27/284X and aic7770 motherboard controllers + * /pci/aic7870.c 294x and aic7870 motherboard controllers + * + * Portions of this driver are based on the FreeBSD 1742 Driver: + * + * Written by Julian Elischer (julian@tfs.com) + * for TRW Financial Systems for use under the MACH(2.5) operating system. + * + * TRW Financial Systems, in accordance with their agreement with Carnegie + * Mellon University, makes this software available to CMU to distribute + * or use in any manner that they see fit as long as this message is kept with + * the software. For this reason TFS also grants any other persons or + * organisations permission to use or modify this software. + * + * TFS supplies this software to be publicly redistributed + * on the understanding that TFS is not responsible for the correct + * functioning of this software in any circumstances. + * + * commenced: Sun Sep 27 18:14:01 PDT 1992 + */ +/* + * TODO: + * Add target reset capabilities + * Implement Target Mode + */ + +#include <sys/types.h> +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/kernel.h> +#include <sys/device.h> +#include <sys/malloc.h> +#include <sys/buf.h> +#include <sys/proc.h> +#include <sys/user.h> + +#include <machine/pio.h> + +#include <dev/isa/isareg.h> +#include <dev/pci/pcireg.h> +#include <dev/pci/pcivar.h> + +#include <scsi/scsi_all.h> +#include <scsi/scsi_debug.h> +#include <scsi/scsiconf.h> + +#include <dev/ic/aic7xxxvar.h> + +int ahc_init __P((struct ahc_softc *)); +void ahc_loadseq __P((int)); +int ahc_scsi_cmd __P((struct scsi_xfer *)); +void ahc_timeout __P((void *)); +void ahc_done __P((struct ahc_softc *, struct ahc_scb *)); +struct ahc_scb *ahc_get_scb __P((struct ahc_softc *, int)); +void ahc_free_scb __P((struct ahc_softc *, struct ahc_scb *, int)); +void ahc_abort_scb __P((struct ahc_softc *, struct ahc_scb *)); +void ahcminphys __P((struct buf *)); +int ahc_poll __P((struct ahc_softc *, struct scsi_xfer *, int)); + +/* Different debugging levels */ +#define AHC_SHOWMISC 0x0001 +#define AHC_SHOWCMDS 0x0002 +#define AHC_SHOWSCBS 0x0004 +/*#define AHC_DEBUG /**/ +int ahc_debug = AHC_SHOWMISC; + +/*#define AHC_MORE_DEBUG /**/ + +#ifdef AHC_MORE_DEBUG +#define DEBUGLEVEL -1 +#define DEBUGTARGET 0x0 +#endif + +/**** bit definitions for SCSIDEF ****/ +#define HSCSIID 0x07 /* our SCSI ID */ +#define HWSCSIID 0x0f /* our SCSI ID if Wide Bus */ + +struct scsi_adapter ahc_switch = { + ahc_scsi_cmd, + ahcminphys, + 0, + 0, +}; + + +/* the below structure is so we have a default dev struct for our link struct */ +struct scsi_device ahc_dev = { + NULL, /* Use default error handler */ + NULL, /* have a queue, served by this */ + NULL, /* have no async handler */ + NULL, /* Use default 'done' routine */ +}; + + +/* + * All of these should be in a separate header file shared by the sequencer + * code and the kernel level driver. The only catch is that we would need to + * add an additional 0xc00 offset when using them in the kernel driver. The + * aic7770 assembler must be modified to allow include files as well. All + * page numbers refer to the Adaptec AIC-7770 Data Book available from + * Adaptec's Technical Documents Department 1-800-934-2766 + */ + +/* -------------------- AIC-7770 offset definitions ----------------------- */ + +/* + * SCSI Sequence Control (p. 3-11). + * Each bit, when set starts a specific SCSI sequence on the bus + */ +#define SCSISEQ 0xc00ul +#define TEMODEO 0x80 +#define ENSELO 0x40 +#define ENSELI 0x20 +#define ENRSELI 0x10 +#define ENAUTOATNO 0x08 +#define ENAUTOATNI 0x04 +#define ENAUTOATNP 0x02 +#define SCSIRSTO 0x01 + +/* + * SCSI Transfer Control 1 Register (pp. 3-14,15). + * Controls the SCSI module data path. + */ +#define SXFRCTL1 0xc02ul +#define BITBUCKET 0x80 +#define SWRAPEN 0x40 +#define ENSPCHK 0x20 +#define STIMESEL 0x18 +#define ENSTIMER 0x04 +#define ACTNEGEN 0x02 +#define STPWEN 0x01 /* Powered Termination */ + +/* + * SCSI Interrrupt Mode 1 (pp. 3-28,29). + * Set bits in this register enable the corresponding + * interrupt source. + */ +#define SIMODE1 0xc11ul +#define ENSELTIMO 0x80 +#define ENATNTARG 0x40 +#define ENSCSIRST 0x20 +#define ENPHASEMIS 0x10 +#define ENBUSFREE 0x08 +#define ENSCSIPERR 0x04 +#define ENPHASECHG 0x02 +#define ENREQINIT 0x01 + +/* + * SCSI Control Signal Read Register (p. 3-15). + * Reads the actual state of the SCSI bus pins + */ +#define SCSISIGI 0xc03ul +#define CDI 0x80 +#define IOI 0x40 +#define MSGI 0x20 +#define ATNI 0x10 +#define SELI 0x08 +#define BSYI 0x04 +#define REQI 0x02 +#define ACKI 0x01 + +/* + * SCSI Contol Signal Write Register (p. 3-16). + * Writing to this register modifies the control signals on the bus. Only + * those signals that are allowed in the current mode (Initiator/Target) are + * asserted. + */ +#define SCSISIGO 0xc03ul +#define CDO 0x80 +#define IOO 0x40 +#define MSGO 0x20 +#define ATNO 0x10 +#define SELO 0x08 +#define BSYO 0x04 +#define REQO 0x02 +#define ACKO 0x01 + +/* XXX document this thing */ +#define SCSIRATE 0xc04ul + +/* + * SCSI ID (p. 3-18). + * Contains the ID of the board and the current target on the + * selected channel + */ +#define SCSIID 0xc05ul +#define TID 0xf0 /* Target ID mask */ +#define OID 0x0f /* Our ID mask */ + +/* + * SCSI Status 0 (p. 3-21) + * Contains one set of SCSI Interrupt codes + * These are most likely of interest to the sequencer + */ +#define SSTAT0 0xc0bul +#define TARGET 0x80 /* Board is a target */ +#define SELDO 0x40 /* Selection Done */ +#define SELDI 0x20 /* Board has been selected */ +#define SELINGO 0x10 /* Selection In Progress */ +#define SWRAP 0x08 /* 24bit counter wrap */ +#define SDONE 0x04 /* STCNT = 0x000000 */ +#define SPIORDY 0x02 /* SCSI PIO Ready */ +#define DMADONE 0x01 /* DMA transfer completed */ + +/* + * Clear SCSI Interrupt 1 (p. 3-23) + * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT1. + */ +#define CLRSINT1 0xc0cul +#define CLRSELTIMEO 0x80 +#define CLRATNO 0x40 +#define CLRSCSIRSTI 0x20 +/* UNUSED 0x10 */ +#define CLRBUSFREE 0x08 +#define CLRSCSIPERR 0x04 +#define CLRPHASECHG 0x02 +#define CLRREQINIT 0x01 + +/* + * SCSI Status 1 (p. 3-24) + * These interrupt bits are of interest to the kernel driver + */ +#define SSTAT1 0xc0cul +#define SELTO 0x80 +#define ATNTARG 0x40 +#define SCSIRSTI 0x20 +#define PHASEMIS 0x10 +#define BUSFREE 0x08 +#define SCSIPERR 0x04 +#define PHASECHG 0x02 +#define REQINIT 0x01 + +/* + * Selection/Reselection ID (p. 3-31) + * Upper four bits are the device id. The ONEBIT is set when the re/selecting + * device did not set its own ID. + */ +#define SELID 0xc19ul +#define SELID_MASK 0xf0 +#define ONEBIT 0x08 +/* UNUSED 0x07 */ + +/* + * SCSI Block Control (p. 3-32) + * Controls Bus type and channel selection. In a twin channel configuration + * addresses 0x00-0x1e are gated to the appropriate channel based on this + * register. SELWIDE allows for the coexistence of 8bit and 16bit devices + * on a wide bus. + */ +#define SBLKCTL 0xc1ful +/* UNUSED 0xc0 */ +#define AUTOFLUSHDIS 0x20 +/* UNUSED 0x10 */ +#define SELBUSB 0x08 +/* UNUSED 0x04 */ +#define SELWIDE 0x02 +/* UNUSED 0x01 */ + +/* + * Sequencer Control (p. 3-33) + * Error detection mode and speed configuration + */ +#define SEQCTL 0xc60ul +#define PERRORDIS 0x80 +#define PAUSEDIS 0x40 +#define FAILDIS 0x20 +#define FASTMODE 0x10 +#define BRKADRINTEN 0x08 +#define STEP 0x04 +#define SEQRESET 0x02 +#define LOADRAM 0x01 + +/* + * Sequencer RAM Data (p. 3-34) + * Single byte window into the Scratch Ram area starting at the address + * specified by SEQADDR0 and SEQADDR1. To write a full word, simply write + * four bytes in sucessesion. The SEQADDRs will increment after the most + * significant byte is written + */ +#define SEQRAM 0xc61ul + +/* + * Sequencer Address Registers (p. 3-35) + * Only the first bit of SEQADDR1 holds addressing information + */ +#define SEQADDR0 0xc62ul +#define SEQADDR1 0xc63ul +#define SEQADDR1_MASK 0x01 + +/* + * Accumulator + * We cheat by passing arguments in the Accumulator up to the kernel driver + */ +#define ACCUM 0xc64ul + +#define SINDEX 0xc65ul + +/* + * Board Control (p. 3-43) + */ +#define BCTL 0xc84ul +/* RSVD 0xf0 */ +#define ACE 0x08 /* Support for external processors */ +/* RSVD 0x06 */ +#define ENABLE 0x01 + +/* + * Host Control (p. 3-47) R/W + * Overal host control of the device. + */ +#define HCNTRL 0xc87ul +/* UNUSED 0x80 */ +#define POWRDN 0x40 +/* UNUSED 0x20 */ +#define SWINT 0x10 +#define IRQMS 0x08 +#define PAUSE 0x04 +#define INTEN 0x02 +#define CHIPRST 0x01 + +/* + * SCB Pointer (p. 3-49) + * Gate one of the four SCBs into the SCBARRAY window. + */ +#define SCBPTR 0xc90ul + +/* + * Interrupt Status (p. 3-50) + * Status for system interrupts + */ +#define INTSTAT 0xc91ul +#define SEQINT_MASK 0xf0 /* SEQINT Status Codes */ +#define BAD_PHASE 0x00 +#define SEND_REJECT 0x10 +#define NO_IDENT 0x20 +#define NO_MATCH 0x30 +#define MSG_SDTR 0x40 +#define MSG_WDTR 0x50 +#define MSG_REJECT 0x60 +#define BAD_STATUS 0x70 +#define RESIDUAL 0x80 +#define ABORT_TAG 0x90 +#define BRKADRINT 0x08 +#define SCSIINT 0x04 +#define CMDCMPLT 0x02 +#define SEQINT 0x01 +#define INT_PEND (BRKADRINT | SEQINT | SCSIINT | CMDCMPLT) + +/* + * Hard Error (p. 3-53) + * Reporting of catastrophic errors. You usually cannot recover from + * these without a full board reset. + */ +#define ERROR 0xc92ul +/* UNUSED 0xf0 */ +#define PARERR 0x08 +#define ILLOPCODE 0x04 +#define ILLSADDR 0x02 +#define ILLHADDR 0x01 + +/* + * Clear Interrupt Status (p. 3-52) + */ +#define CLRINT 0xc92ul +#define CLRBRKADRINT 0x08 +#define CLRSCSIINT 0x04 +#define CLRCMDINT 0x02 +#define CLRSEQINT 0x01 + +/* + * SCB Auto Increment (p. 3-59) + * Byte offset into the SCB Array and an optional bit to allow auto + * incrementing of the address during download and upload operations + */ +#define SCBCNT 0xc9aul +#define SCBAUTO 0x80 +#define SCBCNT_MASK 0x1f + +/* + * Queue In FIFO (p. 3-60) + * Input queue for queued SCBs (commands that the seqencer has yet to start) + */ +#define QINFIFO 0xc9bul + +/* + * Queue In Count (p. 3-60) + * Number of queued SCBs + */ +#define QINCNT 0xc9cul + +/* + * Queue Out FIFO (p. 3-61) + * Queue of SCBs that have completed and await the host + */ +#define QOUTFIFO 0xc9dul + +/* + * Queue Out Count (p. 3-61) + * Number of queued SCBs in the Out FIFO + */ +#define QOUTCNT 0xc9eul + +#define SCBARRAY 0xca0ul + +/* ---------------- END AIC-7770 Register Definitions ----------------- */ + +/* --------------------- AIC-7870-only definitions -------------------- */ + +#define DSPCISTATUS 0xc86ul + +/* ---------------------- Scratch RAM Offsets ------------------------- */ +/* These offsets are either to values that are initialized by the board's + * BIOS or are specified by the Linux sequencer code. If I can figure out + * how to read the EISA configuration info at probe time, the cards could + * be run without BIOS support installed + */ + +/* + * 1 byte per target starting at this address for configuration values + */ +#define HA_TARG_SCRATCH 0xc20ul + +/* + * The sequencer will stick the frist byte of any rejected message here so + * we can see what is getting thrown away. + */ +#define HA_REJBYTE 0xc31ul + +/* + * Length of pending message + */ +#define HA_MSG_LEN 0xc34ul + +/* + * message body + */ +#define HA_MSG_START 0xc35ul /* outgoing message body */ + +/* + * These are offsets into the card's scratch ram. Some of the values are + * specified in the AHA2742 technical reference manual and are initialized + * by the BIOS at boot time. + */ +#define HA_ARG_1 0xc4aul +#define HA_RETURN_1 0xc4aul +#define SEND_SENSE 0x80 +#define SEND_WDTR 0x80 +#define SEND_SDTR 0x80 +#define SEND_REJ 0x40 + +#define HA_SIGSTATE 0xc4bul + +#define HA_SCBCOUNT 0xc52ul +#define HA_FLAGS 0xc53ul +#define SINGLE_BUS 0x00 +#define TWIN_BUS 0x01 +#define WIDE_BUS 0x02 +#define ACTIVE_MSG 0x20 +#define IDENTIFY_SEEN 0x40 +#define RESELECTING 0x80 + +#define HA_ACTIVE0 0xc54ul +#define HA_ACTIVE1 0xc55ul +#define SAVED_TCL 0xc56ul +#define WAITING_SCBH 0xc57ul +#define WAITING_SCBT 0xc58ul + +#define HA_SCSICONF 0xc5aul +#define INTDEF 0xc5cul +#define HA_HOSTCONF 0xc5dul + +#define MSG_ABORT 0x06 +#define BUS_8_BIT 0x00 +#define BUS_16_BIT 0x01 +#define BUS_32_BIT 0x02 + +/* + * Since the sequencer can disable pausing in a critical section, we + * must loop until it actually stops. + * XXX Should add a timeout in here?? + */ +#define PAUSE_SEQUENCER(ahc) \ + do { \ + outb(HCNTRL + ahc->sc_iobase, ahc->pause); \ + while ((inb(HCNTRL + ahc->sc_iobase) & PAUSE) == 0) \ + ; \ + } while (0) + +#define UNPAUSE_SEQUENCER(ahc) \ + do { \ + outb(HCNTRL + ahc->sc_iobase, ahc->unpause); \ + } while (0) + +/* + * Restart the sequencer program from address zero + * XXX Should add a timeout in here?? + */ +#define RESET_SEQUENCER(ahc) \ + do { \ + do { \ + outb(SEQCTL + ahc->sc_iobase, SEQRESET|FASTMODE); \ + } while (inb(SEQADDR0 + ahc->sc_iobase) != 0 && \ + inb(SEQADDR1 + ahc->sc_iobase) != 0); \ + } while (0) + +#define RESTART_SEQUENCER(ahc) \ + do { \ + RESET_SEQUENCER(ahc); \ + UNPAUSE_SEQUENCER(ahc); \ + } while (0) + +#ifdef AHC_DEBUG +void +ahc_print_scb(scb) + struct ahc_scb *scb; +{ + + printf("scb:0x%x control:0x%x tcl:0x%x cmdlen:%d cmdpointer:0x%x\n", + scb, + scb->control, + scb->target_channel_lun, + scb->cmdlen, + scb->cmdpointer); + printf("\tdatlen:%d data:0x%x res:0x%x segs:0x%x segp:0x%x\n", + scb->datalen[2] << 16 | scb->datalen[1] << 8 | scb->datalen[0], + scb->data, + scb->RESERVED[1] << 8 | scb->RESERVED[0], + scb->SG_segment_count, + scb->SG_list_pointer); + printf("\tsg_addr:%x sg_len:%d\n", + scb->ahc_dma[0].addr, + scb->ahc_dma[0].len); + printf(" size:%d\n", + (int)&scb->next - (int)scb); +} + +void +ahc_print_active_scb(ahc) + struct ahc_softc *ahc; +{ + int iobase = ahc->sc_iobase; + int scb_index; + + PAUSE_SEQUENCER(ahc); + scb_index = inb(SCBPTR + iobase); + UNPAUSE_SEQUENCER(ahc); + + ahc_print_scb(ahc->scbarray[scb_index]); +} +#endif + +#define PARERR 0x08 +#define ILLOPCODE 0x04 +#define ILLSADDR 0x02 +#define ILLHADDR 0x01 + +static struct { + u_char errno; + char *errmesg; +} hard_error[] = { + { ILLHADDR, "Illegal Host Access" }, + { ILLSADDR, "Illegal Sequencer Address referrenced" }, + { ILLOPCODE, "Illegal Opcode in sequencer program" }, + { PARERR, "Sequencer Ram Parity Error" } +}; + + +/* + * Valid SCSIRATE values. (p. 3-17) + * Provides a mapping of tranfer periods in ns to the proper value to + * stick in the scsiscfr reg to use that transfer rate. + */ +static struct { + u_char sxfr; + int period; /* in ns */ + char *rate; +} ahc_syncrates[] = { + { 0x00, 100, "10.0" }, + { 0x10, 125, "8.0" }, + { 0x20, 150, "6.67" }, + { 0x30, 175, "5.7" }, + { 0x40, 200, "5.0" }, + { 0x50, 225, "4.4" }, + { 0x60, 250, "4.0" }, + { 0x70, 275, "3.6" } +}; + +static int ahc_num_syncrates = + sizeof(ahc_syncrates) / sizeof(ahc_syncrates[0]); + +/* + * Check if the device can be found at the port given + * and if so, determine configuration and set it up for further work. + */ + +int +ahcprobe(ahc, iobase) + struct ahc_softc *ahc; + int iobase; +{ + + ahc->sc_iobase = iobase; + + /* + * Try to initialize a unit at this location + * reset the AIC-7770, read its registers, + * and fill in the dev structure accordingly + */ + + if (ahc_init(ahc) != 0) + return (0); + + return (1); +} + + +/* + * Look up the valid period to SCSIRATE conversion in our table. + */ +static u_char +ahc_scsirate(offset, period, ahc, target) + u_char offset; + int period; + struct ahc_softc *ahc; + int target; +{ + u_char scsirate; + int i; + + for (i = 0; i < ahc_num_syncrates; i++) { + if ((ahc_syncrates[i].period - period) >= 0) { + printf("%s: target %d synchronous at %sMB/s, " + "offset = %d\n", + ahc->sc_dev.dv_xname, target, + ahc_syncrates[i].rate, offset); +#ifdef AHC_DEBUG +#endif /* AHC_DEBUG */ + return ((ahc_syncrates[i].sxfr) | (offset & 0x0f)); + } + } + + /* Default to asyncronous transfers. Also reject this SDTR request. */ + printf("%s: target %d using asyncronous transfers\n", + ahc->sc_dev.dv_xname, target); + return (0); +#ifdef AHC_DEBUG +#endif /* AHC_DEBUG */ +} + +ahcprint() +{ + +} + +/* + * Attach all the sub-devices we can find + */ +int +ahcattach(ahc) + struct ahc_softc *ahc; +{ + + TAILQ_INIT(&ahc->free_scb); + + /* + * fill in the prototype scsi_link. + */ + ahc->sc_link.adapter_softc = ahc; + ahc->sc_link.adapter_target = ahc->ahc_scsi_dev; + ahc->sc_link.adapter = &ahc_switch; + ahc->sc_link.device = &ahc_dev; + ahc->sc_link.openings = 1; + ahc->sc_link.flags = DEBUGLEVEL; + ahc->sc_link.quirks = 0; + + /* + * ask the adapter what subunits are present + */ + printf("%s: Probing channel A\n", ahc->sc_dev.dv_xname); + config_found((void *)ahc, &ahc->sc_link, ahcprint); + if (ahc->type & AHC_TWIN) { + /* Configure the second scsi bus */ + ahc->sc_link_b = ahc->sc_link; + /* XXXX Didn't do this before. */ + ahc->sc_link_b.adapter_target = ahc->ahc_scsi_dev_b; + ahc->sc_link_b.quirks = 0x0008; /**/ + printf("%s: Probing channel B\n", ahc->sc_dev.dv_xname); + config_found((void *)ahc, &ahc->sc_link_b, ahcprint); + } + + return 1; +} + +void +ahc_send_scb(ahc, scb) + struct ahc_softc *ahc; + struct ahc_scb *scb; +{ + int iobase = ahc->sc_iobase; + + PAUSE_SEQUENCER(ahc); + outb(QINFIFO + iobase, scb->position); + UNPAUSE_SEQUENCER(ahc); +} + +static void +ahc_getscb(iobase, scb) + int iobase; + struct ahc_scb *scb; +{ + + outb(SCBCNT + iobase, SCBAUTO); + insb(SCBARRAY + iobase, scb, SCB_UP_SIZE); + outb(SCBCNT + iobase, 0); +} + +/* + * Catch an interrupt from the adaptor + */ +int +ahcintr(ahc) + struct ahc_softc *ahc; +{ + int iobase = ahc->sc_iobase; + u_char intstat = inb(INTSTAT + iobase); + u_char status; + struct ahc_scb *scb = NULL; + struct scsi_xfer *xs = NULL; + + /* + * Is this interrupt for me? or for + * someone who is sharing my interrupt + */ + if ((intstat & INT_PEND) == 0) + return 0; + + if (intstat & BRKADRINT) { + /* We upset the sequencer :-( */ + + /* Lookup the error message */ + int i, error = inb(ERROR + iobase); + int num_errors = sizeof(hard_error)/sizeof(hard_error[0]); + for (i = 0; error != 1 && i < num_errors; i++) + error >>= 1; + panic("%s: brkadrint, %s at seqaddr = 0x%x\n", + ahc->sc_dev.dv_xname, hard_error[i].errmesg, + (inb(SEQADDR1 + iobase) << 8) | + (inb(SEQADDR0 + iobase) << 0)); + } + + if (intstat & SEQINT) { + switch (intstat & SEQINT_MASK) { + case BAD_PHASE: + panic("%s: unknown scsi bus phase. " + "Attempting to continue\n", + ahc->sc_dev.dv_xname); + break; + case SEND_REJECT: + printf("%s: Warning - " + "message reject, message type: 0x%x\n", + ahc->sc_dev.dv_xname, + inb(HA_REJBYTE + iobase)); + break; + case NO_IDENT: + panic("%s: No IDENTIFY message from reconnecting " + "target %d at seqaddr = 0x%lx " + "SAVED_TCL == 0x%x\n", + ahc->sc_dev.dv_xname, + (inb(SELID + iobase) >> 4) & 0xf, + (inb(SEQADDR1 + iobase) << 8) | + (inb(SEQADDR0 + iobase) << 0), + inb(SAVED_TCL + iobase)); + break; + case NO_MATCH: { + u_char active; + int active_port = HA_ACTIVE0 + iobase; + int tcl = inb(SCBARRAY+1 + iobase); + int target = (tcl >> 4) & 0x0f; + printf("%s: no active SCB for reconnecting " + "target %d, channel %c - issuing ABORT\n", + ahc->sc_dev.dv_xname, + target, tcl & 0x08 ? 'B' : 'A'); + printf("SAVED_TCL == 0x%x\n", inb(SAVED_TCL + iobase)); + if (tcl & 0x88) { + /* Second channel stores its info + * in byte two of HA_ACTIVE + */ + active_port++; + } + active = inb(active_port); + active &= ~(0x01 << (target & 0x07)); + outb(SCBARRAY + iobase, SCB_NEEDDMA); + outb(active_port, active); + outb(CLRSINT1 + iobase, CLRSELTIMEO); + RESTART_SEQUENCER(ahc); + break; + } + case MSG_SDTR: { + u_char scsi_id = + (inb(SCSIID + iobase) >> 0x4) | + (inb(SBLKCTL + iobase) & 0x08); + u_char scratch, offset; + int period; + + /* + * Help the sequencer to translate the + * negotiated transfer rate. Transfer is + * 1/4 the period in ns as is returned by + * the sync negotiation message. So, we must + * multiply by four + */ + period = inb(HA_ARG_1 + iobase) << 2; + /* The bottom half of SCSIXFER */ + offset = inb(ACCUM + iobase); + + printf("%s: SDTR, target %d period %d offset %d\n", + ahc->sc_dev.dv_xname, scsi_id, period, offset); + scratch = inb(HA_TARG_SCRATCH + iobase + scsi_id); + scratch &= 0x80; + scratch |= ahc_scsirate(offset, period, ahc, scsi_id); + + if ((scratch & 0x7f) == 0) { + /* + * The requested rate was so low + * that asyncronous transfers are + * faster (not to mention the + * controller won't support them), + * so we issue a message reject to + * ensure we go to asyncronous + * transfers. + */ + outb(HA_RETURN_1 + iobase, SEND_REJ); + } else if (ahc->sdtrpending & (0x01 << scsi_id)) { + /* + * Don't send an SDTR back to the + * target, since we asked first. + */ + outb(HA_RETURN_1 + iobase, 0); + } else { + /* + * Send our own SDTR in reply + */ +#ifdef AHC_DEBUG + if (ahc_debug & AHC_SHOWMISC) + printf("Sending SDTR!!\n"); +#endif + outb(HA_RETURN_1 + iobase, SEND_SDTR); + } + /* + * Negate the flags + */ + ahc->needsdtr &= ~(0x01 << scsi_id); + ahc->sdtrpending &= ~(0x01 << scsi_id); + + outb(HA_TARG_SCRATCH + iobase + scsi_id, scratch); + outb(SCSIRATE + iobase, scratch); + break; + } + case MSG_WDTR: { + u_char scsi_id = + (inb(SCSIID + iobase) >> 0x4) | + (inb(SBLKCTL + iobase) & 0x08); + u_char scratch, width; + + width = inb(ACCUM + iobase); + + scratch = inb(HA_TARG_SCRATCH + iobase + scsi_id); + + if (ahc->wdtrpending & (0x01 << scsi_id)) { + /* + * Don't send a WDTR back to the + * target, since we asked first. + */ + outb(HA_RETURN_1 + iobase, 0); + switch (width) { + case BUS_8_BIT: + scratch &= 0x7f; + break; + case BUS_16_BIT: + printf("%s: target %d using 16Bit " + "transfers\n", + ahc->sc_dev.dv_xname, scsi_id); + scratch &= 0xf8; + scratch |= 0x88; + break; + case BUS_32_BIT: + /* XXXX */ + } + } else { + /* + * Send our own WDTR in reply + */ + switch (width) { + case BUS_8_BIT: + scratch &= 0x7f; + break; + case BUS_32_BIT: + /* Negotiate 16_BITS */ + width = BUS_16_BIT; + case BUS_16_BIT: + printf("%s: target %d using 16Bit " + "transfers\n", + ahc->sc_dev.dv_xname, scsi_id); + scratch &= 0xf8; + scratch |= 0x88; + break; + } + outb(HA_RETURN_1 + iobase, + width | SEND_WDTR); + } + ahc->needwdtr &= ~(0x01 << scsi_id); + ahc->wdtrpending &= ~(0x01 << scsi_id); + + outb(HA_TARG_SCRATCH + iobase + scsi_id, scratch); + outb(SCSIRATE + iobase, scratch); + break; + } + case MSG_REJECT: { + /* + * What we care about here is if we had an + * outstanding SDTR or WDTR message for this + * target. If we did, this is a signal that + * the target is refusing negotiation. + */ + + u_char scsi_id = + (inb(SCSIID + iobase) >> 0x4) | + (inb(SBLKCTL + iobase) & 0x08); + u_char scratch; + u_short mask; + + scratch = inb(HA_TARG_SCRATCH + iobase + scsi_id); + + mask = (0x01 << scsi_id); + if (ahc->wdtrpending & mask) { + /* note 8bit xfers and clear flag */ + scratch &= 0x7f; + ahc->needwdtr &= ~mask; + ahc->wdtrpending &= ~mask; + printf("%s: target %d refusing " + "WIDE negotiation. Using " + "8bit transfers\n", + ahc->sc_dev.dv_xname, scsi_id); + } else if (ahc->sdtrpending & mask) { + /* note asynch xfers and clear flag */ + scratch &= 0xf0; + ahc->needsdtr &= ~mask; + ahc->sdtrpending &= ~mask; + printf("%s: target %d refusing " + "syncronous negotiation; using " + "asyncronous transfers\n", + ahc->sc_dev.dv_xname, scsi_id); + } else { + /* + * Otherwise, we ignore it. + */ +#ifdef AHC_DEBUG + if (ahc_debug & AHC_SHOWMISC) + printf("Message reject -- ignored\n"); +#endif + break; + } + + outb(HA_TARG_SCRATCH + iobase + scsi_id, scratch); + outb(SCSIRATE + iobase, scratch); + break; + } + case BAD_STATUS: { + int scb_index = inb(SCBPTR + iobase); + scb = ahc->scbarray[scb_index]; + + /* + * The sequencer will notify us when a command + * has an error that would be of interest to + * the kernel. This allows us to leave the sequencer + * running in the common case of command completes + * without error. + */ + + /* + * Set the default return value to 0 (don't + * send sense). The sense code with change + * this if needed and this reduces code + * duplication. + */ + outb(HA_RETURN_1 + iobase, 0); + if (!scb || scb->flags == SCB_FREE) { + printf("%s: ahcintr: referenced scb not " + "valid during seqint 0x%x scb(%d)\n", + ahc->sc_dev.dv_xname, intstat, scb_index); + goto clear; + } + + xs = scb->xs; + + ahc_getscb(iobase, scb); + +#ifdef AHC_DEBUG + if (xs->sc_link->target == DEBUGTARGET) + ahc_print_scb(scb); +#endif + xs->status = scb->target_status; + switch (scb->target_status) { + case SCSI_OK: + printf("%s: Interrupted for status of 0???\n", + ahc->sc_dev.dv_xname); + break; + case SCSI_CHECK: +#ifdef AHC_DEBUG + sc_print_addr(xs->sc_link); + printf("requests Check Status\n"); +#endif + + if (xs->error == XS_NOERROR && + scb->flags != SCB_CHKSENSE) { + u_char flags; + u_char head; + u_char tail; + struct ahc_dma_seg *sg = scb->ahc_dma; + struct scsi_sense *sc = &(scb->sense_cmd); + u_char control = scb->control; + u_char tcl = scb->target_channel_lun; +#ifdef AHC_DEBUG + sc_print_addr(xs->sc_link); + printf("Sending Sense\n"); +#endif + bzero(scb, SCB_DOWN_SIZE); + scb->flags = SCB_CHKSENSE; + scb->control = (control & SCB_TE); + sc->opcode = REQUEST_SENSE; + sc->byte2 = xs->sc_link->lun << 5; + sc->length = sizeof(struct scsi_sense_data); + sc->control = 0; + + sg->seg_addr = vtophys(&xs->sense); + sg->seg_len = sizeof(struct scsi_sense_data); + + scb->target_channel_lun = tcl; + scb->SG_segment_count = 1; + scb->SG_list_pointer = vtophys(sg); + scb->cmdpointer = vtophys(sc); + scb->cmdlen = sizeof(*sc); + + outb(SCBCNT + iobase, SCBAUTO); + outsb(SCBARRAY + iobase, scb, + SCB_DOWN_SIZE); + outb(SCBCNT + iobase, 0); + outb(SCBARRAY + iobase + 30, + SCB_LIST_NULL); + + /* + * Add this SCB to the "waiting for + * selection" list. + */ + head = inb(WAITING_SCBH + iobase); + tail = inb(WAITING_SCBT + iobase); + if (head & SCB_LIST_NULL) { + /* List was empty */ + head = scb->position; + tail = SCB_LIST_NULL; + } else if (tail & SCB_LIST_NULL) { + /* List had one element */ + tail = scb->position; + outb(SCBPTR + iobase, head); + outb(SCBARRAY + iobase + 30, + tail); + } else { + outb(SCBPTR + iobase, tail); + tail = scb->position; + outb(SCBARRAY + iobase + 30, + tail); + } + outb(WAITING_SCBH + iobase, head); + outb(WAITING_SCBT + iobase, tail); + outb(HA_RETURN_1 + iobase, SEND_SENSE); + break; + } + /* + * Have the sequencer do a normal command + * complete with either a "DRIVER_STUFFUP" + * error or whatever other error condition + * we already had. + */ + if (xs->error == XS_NOERROR) + xs->error = XS_DRIVER_STUFFUP; + break; + case SCSI_BUSY: + sc_print_addr(xs->sc_link); + printf("Target Busy\n"); + xs->error = XS_BUSY; + break; +#if 0 + case SCSI_QUEUE_FULL: + /* + * The upper level SCSI code will eventually + * handle this properly. + */ + sc_print_addr(xs->sc_link); + printf("Queue Full\n"); + xs->error = XS_BUSY; + break; +#endif + default: + sc_print_addr(xs->sc_link); + printf("unexpected targ_status: %x\n", + scb->target_status); + xs->error = XS_DRIVER_STUFFUP; + break; + } + break; + } + case RESIDUAL: { + int scb_index = inb(SCBPTR + iobase); + scb = ahc->scbarray[scb_index]; + + /* + * Don't clobber valid resid info with + * a resid coming from a check sense + * operation. + */ + if (scb->flags != SCB_CHKSENSE) + scb->xs->resid = + (inb(iobase + SCBARRAY + 17) << 16) | + (inb(iobase + SCBARRAY + 16) << 8) | + (inb(iobase + SCBARRAY + 15) << 0); +#ifdef AHC_MORE_DEBUG + printf("ahc: Handled Residual\n"); +#endif + break; + } + case ABORT_TAG: { + int scb_index = inb(SCBPTR + iobase); + scb = ahc->scbarray[scb_index]; + + /* + * We didn't recieve a valid tag back from + * the target on a reconnect. + */ + sc_print_addr(xs->sc_link); + printf("invalid tag recieved on channel %c " + "-- sending ABORT_TAG\n", + (xs->sc_link->quirks & 0x08) ? 'B' : 'A'); + scb->xs->error = XS_DRIVER_STUFFUP; + untimeout(ahc_timeout, scb); + ahc_done(ahc, scb); + break; + } + default: + printf("%s: seqint, intstat == 0x%x, scsisigi = 0x%x\n", + ahc->sc_dev.dv_xname, + intstat, inb(SCSISIGI + iobase)); + break; + } + + clear: + /* + * Clear the upper byte that holds SEQINT status + * codes and clear the SEQINT bit. + */ + outb(CLRINT + iobase, CLRSEQINT); + + /* + * The sequencer is paused immediately on + * a SEQINT, so we should restart it when + * we leave this section. + */ + UNPAUSE_SEQUENCER(ahc); + } + + if (intstat & SCSIINT) { + int scb_index = inb(SCBPTR + iobase); + scb = ahc->scbarray[scb_index]; + + status = inb(SSTAT1 + iobase); + + if (!scb || scb->flags == SCB_FREE) { + printf("%s: ahcintr - referenced scb not " + "valid during scsiint 0x%x scb(%d)\n", + ahc->sc_dev.dv_xname, status, scb_index); + outb(CLRSINT1 + iobase, status); + UNPAUSE_SEQUENCER(ahc); + outb(CLRINT + iobase, CLRSCSIINT); + scb = NULL; + goto cmdcomplete; + } + xs = scb->xs; + +#ifdef AHC_MORE_DEBUG + if ((xs->sc_link->target & 0xf) == DEBUGTARGET) + printf("Intr status %x\n", status); +#endif + + if (status & SELTO) { + u_char active; + u_char waiting; + u_char flags; + int active_port = HA_ACTIVE0 + iobase; + + outb(SCSISEQ + iobase, ENRSELI); + xs->error = XS_SELTIMEOUT; + /* + * Clear any pending messages for the timed out + * target, and mark the target as free + */ + flags = inb(HA_FLAGS + iobase); + outb(HA_FLAGS + iobase, flags & ~ACTIVE_MSG); + + if (scb->target_channel_lun & 0x88) + active_port++; + + active = inb(active_port) & + ~(0x01 << (xs->sc_link->target & 0x07)); + outb(active_port, active); + + outb(SCBARRAY + iobase, SCB_NEEDDMA); + + outb(CLRSINT1 + iobase, CLRSELTIMEO); + + outb(CLRINT + iobase, CLRSCSIINT); + + /* Shift the waiting for selection queue forward */ + waiting = inb(WAITING_SCBH + iobase); + outb(SCBPTR + iobase, waiting); + waiting = inb(SCBARRAY + iobase + 30); + outb(WAITING_SCBH + iobase, waiting); + + RESTART_SEQUENCER(ahc); + } + + if (status & SCSIPERR) { + sc_print_addr(xs->sc_link); + printf("parity error on channel %c\n", + (xs->sc_link->quirks & 0x08) ? 'B' : 'A'); + xs->error = XS_DRIVER_STUFFUP; + + outb(CLRSINT1 + iobase, CLRSCSIPERR); + UNPAUSE_SEQUENCER(ahc); + + outb(CLRINT + iobase, CLRSCSIINT); + scb = NULL; + } + if (status & BUSFREE) { +#if 0 + /* + * Has seen busfree since selection, i.e. + * a "spurious" selection. Shouldn't happen. + */ + printf("ahc: unexpected busfree\n"); +#if 0 + xs->error = XS_DRIVER_STUFFUP; + outb(CLRSINT1 + iobase, BUSFREE); /* CLRBUSFREE */ +#endif +#endif + } else { + printf("%s: Unknown SCSIINT. Status = 0x%x\n", + ahc->sc_dev.dv_xname, status); + outb(CLRSINT1 + iobase, status); + UNPAUSE_SEQUENCER(ahc); + outb(CLRINT + iobase, CLRSCSIINT); + scb = NULL; + } + if (scb != NULL) { + /* We want to process the command */ + untimeout(ahc_timeout, scb); + ahc_done(ahc, scb); + } + } + +cmdcomplete: + if (intstat & CMDCMPLT) { + int scb_index; + + do { + scb_index = inb(QOUTFIFO + iobase); + scb = ahc->scbarray[scb_index]; + + if (!scb || scb->flags == SCB_FREE) { + printf("%s: WARNING " + "no command for scb %d (cmdcmplt)\n" + "QOUTCNT == %d\n", + ahc->sc_dev.dv_xname, + scb_index, inb(QOUTCNT + iobase)); + outb(CLRINT + iobase, CLRCMDINT); + continue; + } + + /* XXXX Should do this before reading FIFO? */ + outb(CLRINT + iobase, CLRCMDINT); + untimeout(ahc_timeout, scb); + ahc_done(ahc, scb); + } while (inb(QOUTCNT + iobase)); + } + + return 1; +} + +/* + * We have a scb which has been processed by the + * adaptor, now we look to see how the operation + * went. + */ +void +ahc_done(ahc, scb) + struct ahc_softc *ahc; + struct ahc_scb *scb; +{ + struct scsi_xfer *xs = scb->xs; + +#ifdef AHC_MORE_DEBUG + if ((xs->sc_link->target & 0xf) == DEBUGTARGET) { + xs->sc_link->flags |= 0xf0; + SC_DEBUG(xs->sc_link, SDEV_DB2, ("ahc_done\n")); + printf("%x %x %x %x\n", + scb->flags, + scb->target_status, + xs->flags, + xs->error); + } +#endif + + /* + * Put the results of the operation + * into the xfer and call whoever started it + */ + if (xs->error == XS_NOERROR) { + if (scb->flags == SCB_ABORTED) + xs->error = XS_DRIVER_STUFFUP; + else if (scb->flags == SCB_CHKSENSE) + xs->error = XS_SENSE; + } + + xs->flags |= ITSDONE; + +#ifdef AHC_TAGENABLE + if (xs->cmd->opcode == 0x12 && xs->error == XS_NOERROR) { + struct scsi_inquiry_data *inq_data; + u_short mask = 0x01 << (xs->sc_link->target | + (scb->target_channel_lun & 0x08)); + /* + * Sneak a look at the results of the SCSI Inquiry + * command and see if we can do Tagged queing. XXX This + * should really be done by the higher level drivers. + */ + inq_data = (struct scsi_inquiry_data *)xs->data; + if (((inq_data->device & SID_TYPE) == 0) + && (inq_data->flags & SID_CmdQue) + && !(ahc->tagenable & mask)) { + /* + * Disk type device and can tag + */ + sc_print_addr(xs->sc_link); + printf("Tagged Queuing Device\n"); + ahc->tagenable |= mask; +#ifdef QUEUE_FULL_SUPPORTED + xs->sc_link->openings += 2; */ +#endif + } + } +#endif + + ahc_free_scb(ahc, scb, xs->flags); + scsi_done(xs); +} + +/* + * Start the board, ready for normal operation + */ +/* XXXX clean */ +int +ahc_init(ahc) + struct ahc_softc *ahc; +{ + int iobase = ahc->sc_iobase; + u_char scsi_conf, sblkctl, i; + int intdef, max_targ = 16, wait; + + /* + * Assume we have a board at this stage + * Find out the configured interupt and the card type. + */ + +#ifdef AHC_DEBUG + printf("%s: scb %d bytes; SCB_SIZE %d bytes, ahc_dma %d bytes\n", + ahc->sc_dev.dv_xname, sizeof(struct ahc_scb), SCB_DOWN_SIZE, + sizeof(struct ahc_dma_seg)); +#endif /* AHC_DEBUG */ + /*printf("%s: reading board settings\n", ahc->sc_dev.dv_xname);/**/ + + /* Save the IRQ type before we do a chip reset */ + + ahc->unpause = (inb(HCNTRL + iobase) & IRQMS) | INTEN; + ahc->pause = ahc->unpause | PAUSE; + outb(HCNTRL + iobase, CHIPRST | ahc->pause); + + /* + * Ensure that the reset has finished + */ + wait = 1000; + while (wait--) { + delay(1000); + if (!(inb(HCNTRL + iobase) & CHIPRST)) + break; + } + if (wait == 0) { + printf("\n%s: WARNING - Failed chip reset! " + "Trying to initialize anyway.\n", ahc->sc_dev.dv_xname); + /* Forcibly clear CHIPRST */ + outb(HCNTRL + iobase, ahc->pause); + } + + switch (ahc->type) { + case AHC_274: + printf(": 274x ", ahc->sc_dev.dv_xname); + ahc->maxscbs = 0x4; + break; + case AHC_284: + printf(": 284x ", ahc->sc_dev.dv_xname); + ahc->maxscbs = 0x4; + break; + case AHC_AIC7870: + case AHC_294: + if (ahc->type == AHC_AIC7870) + printf(": aic7870 ", ahc->sc_dev.dv_xname); + else + printf(": 294x ", ahc->sc_dev.dv_xname); + ahc->maxscbs = 0x10; + #define DFTHRESH 3 + outb(DSPCISTATUS + iobase, DFTHRESH << 6); + /* + * XXX Hard coded SCSI ID until we can read it from the + * SEEPROM or NVRAM. + */ + outb(HA_SCSICONF + iobase, 0x07 | (DFTHRESH << 6)); + /* In case we are a wide card */ + outb(HA_SCSICONF + 1 + iobase, 0x07); + break; + } + + /* Determine channel configuration and who we are on the scsi bus. */ + switch ((sblkctl = inb(SBLKCTL + iobase) & 0x0f)) { + case 0: + ahc->ahc_scsi_dev = (inb(HA_SCSICONF + iobase) & HSCSIID); + printf("Single Channel, SCSI Id=%d, ", ahc->ahc_scsi_dev); + outb(HA_FLAGS + iobase, SINGLE_BUS); + break; + case 2: + ahc->ahc_scsi_dev = (inb(HA_SCSICONF + 1 + iobase) & HWSCSIID); + printf("Wide Channel, SCSI Id=%d, ", ahc->ahc_scsi_dev); + ahc->type |= AHC_WIDE; + outb(HA_FLAGS + iobase, WIDE_BUS); + break; + case 8: + ahc->ahc_scsi_dev = (inb(HA_SCSICONF + iobase) & HSCSIID); + ahc->ahc_scsi_dev_b = (inb(HA_SCSICONF + 1 + iobase) & HSCSIID); + printf("Twin Channel, A SCSI Id=%d, B SCSI Id=%d, ", + ahc->ahc_scsi_dev, ahc->ahc_scsi_dev_b); + ahc->type |= AHC_TWIN; + outb(HA_FLAGS + iobase, TWIN_BUS); + break; + default: + printf(" Unsupported adapter type. %x Ignoring\n",sblkctl); + return(-1); + } + + /* + * Take the bus led out of diagnostic mode + */ + outb(SBLKCTL + iobase, sblkctl); + + /* + * Number of SCBs that will be used. Rev E aic7770s and + * aic7870s have 16. The rest have 4. + */ + if (!(ahc->type & AHC_AIC7870)) { + /* + * See if we have a Rev E or higher + * aic7770. Anything below a Rev E will + * have a R/O autoflush disable configuration + * bit. + */ + u_char sblkctl_orig; + sblkctl_orig = inb(SBLKCTL + iobase); + sblkctl = sblkctl_orig ^ AUTOFLUSHDIS; + outb(SBLKCTL + iobase, sblkctl); + sblkctl = inb(SBLKCTL + iobase); + if (sblkctl != sblkctl_orig) { + printf("aic7770 >= Rev E, "); + /* + * Ensure autoflush is enabled + */ + sblkctl &= ~AUTOFLUSHDIS; + outb(SBLKCTL + iobase, sblkctl); + } else + printf("aic7770 <= Rev C, "); + } else + printf("aic7870, "); + printf("%d SCBs\n", ahc->maxscbs); + + if (ahc->pause & IRQMS) + printf("%s: Using Level Sensitive Interrupts\n", + ahc->sc_dev.dv_xname); + else + printf("%s: Using Edge Triggered Interrupts\n", + ahc->sc_dev.dv_xname); + + if (!(ahc->type & AHC_AIC7870)) { + /* + * The 294x cards are PCI, so we get their interrupt from the + * PCI BIOS. + */ + + intdef = inb(INTDEF + iobase); + switch (intdef & 0xf) { + case 9: + ahc->sc_irq = 9; + break; + case 10: + ahc->sc_irq = 10; + break; + case 11: + ahc->sc_irq = 11; + break; + case 12: + ahc->sc_irq = 12; + break; + case 14: + ahc->sc_irq = 14; + break; + case 15: + ahc->sc_irq = 15; + break; + default: + printf("illegal irq setting\n"); + return (EIO); + } + } + + /* Set the SCSI Id, SXFRCTL1, and SIMODE1, for both channels */ + if (ahc->type & AHC_TWIN) { + /* + * The device is gated to channel B after a chip reset, + * so set those values first + */ + outb(SCSIID + iobase, ahc->ahc_scsi_dev_b); + scsi_conf = inb(HA_SCSICONF + 1 + iobase) & (ENSPCHK|STIMESEL); + outb(SXFRCTL1 + iobase, scsi_conf|ENSTIMER|ACTNEGEN|STPWEN); + outb(SIMODE1 + iobase, ENSELTIMO|ENSCSIPERR); + /* Select Channel A */ + outb(SBLKCTL + iobase, 0); + } + outb(SCSIID + iobase, ahc->ahc_scsi_dev); + scsi_conf = inb(HA_SCSICONF + iobase) & (ENSPCHK|STIMESEL); + outb(SXFRCTL1 + iobase, scsi_conf|ENSTIMER|ACTNEGEN|STPWEN); + outb(SIMODE1 + iobase, ENSELTIMO|ENSCSIPERR); + + /* + * Look at the information that board initialization or + * the board bios has left us. In the lower four bits of each + * target's scratch space any value other than 0 indicates + * that we should initiate syncronous transfers. If it's zero, + * the user or the BIOS has decided to disable syncronous + * negotiation to that target so we don't activate the needsdr + * flag. + */ + ahc->needsdtr_orig = 0; + ahc->needwdtr_orig = 0; + if (!(ahc->type & AHC_WIDE)) + max_targ = 8; + + for (i = 0; i < max_targ; i++) { + u_char target_settings = inb(HA_TARG_SCRATCH + i + iobase); +#if 0 /* XXXX */ + target_settings |= 0x8f; +#endif + if (target_settings & 0x0f) { + ahc->needsdtr_orig |= (0x01 << i); + /* Default to a asyncronous transfers (0 offset) */ + target_settings &= 0xf0; + } + if (target_settings & 0x80) { + ahc->needwdtr_orig |= (0x01 << i); + /* + * We'll set the Wide flag when we + * are successful with Wide negotiation, + * so turn it off for now so we aren't + * confused. + */ + target_settings &= 0x7f; + } + outb(HA_TARG_SCRATCH + i + iobase, target_settings); + } + /* + * If we are not a WIDE device, forget WDTR. This + * makes the driver work on some cards that don't + * leave these fields cleared when the BIOS is not + * installed. + */ + if (!(ahc->type & AHC_WIDE)) + ahc->needwdtr_orig = 0; + ahc->needsdtr = ahc->needsdtr_orig; + ahc->needwdtr = ahc->needwdtr_orig; + ahc->sdtrpending = 0; + ahc->wdtrpending = 0; + ahc->tagenable = 0; + + /* + * Clear the control byte for every SCB so that the sequencer + * doesn't get confused and think that one of them is valid + */ + for (i = 0; i < ahc->maxscbs; i++) { + outb(SCBPTR + iobase, i); + outb(SCBARRAY + iobase, 0); + } + +#ifdef AHC_DEBUG + printf("NEEDSDTR == 0x%x\nNEEDWDTR == 0x%x\n", ahc->needsdtr, + ahc->needwdtr); +#endif + + /* + * Set the number of availible SCBs + */ + outb(HA_SCBCOUNT + iobase, ahc->maxscbs); + + /* We don't have any busy targets right now */ + outb(HA_ACTIVE0 + iobase, 0); + outb(HA_ACTIVE1 + iobase, 0); + + /* We don't have any waiting selections */ + outb(WAITING_SCBH + iobase, SCB_LIST_NULL); + outb(WAITING_SCBT + iobase, SCB_LIST_NULL); + /* + * Load the Sequencer program and Enable the adapter. + * Place the aic7770 in fastmode which makes a big + * difference when doing many small block transfers. + */ + + printf("%s: Downloading Sequencer Program...", ahc->sc_dev.dv_xname); + ahc_loadseq(iobase); + printf("Done\n"); + + if (!(ahc->type & AHC_AIC7870)) + outb(BCTL + iobase, ENABLE); + + /* Reset the bus */ + outb(SCSISEQ + iobase, SCSIRSTO); + delay(1000); + outb(SCSISEQ + iobase, 0); + + RESTART_SEQUENCER(ahc); + + return (0); +} + +void +ahcminphys(bp) + struct buf *bp; +{ + + if (bp->b_bcount > ((AHC_NSEG - 1) << PGSHIFT)) + bp->b_bcount = ((AHC_NSEG - 1) << PGSHIFT); + minphys(bp); +} + +/* + * start a scsi operation given the command and + * the data address, target, and lun all of which + * are stored in the scsi_xfer struct + */ +int +ahc_scsi_cmd(xs) + struct scsi_xfer *xs; +{ + struct scsi_link *sc_link = xs->sc_link; + struct ahc_softc *ahc = sc_link->adapter_softc; + struct ahc_scb *scb; + struct ahc_dma_seg *sg; + int seg; /* scatter gather seg being worked on */ + u_long thiskv, thisphys, nextphys; + int bytes_this_seg, bytes_this_page, datalen, flags; + int s; + u_short mask = (0x01 << (sc_link->target | (sc_link->quirks & 0x08))); + +#ifdef AHC_MORE_DEBUG + if ((sc_link->target & 0xf) == DEBUGTARGET) { + printf("ahc ahc_scsi_cmd for %x\n", sc_link->target); + sc_link->flags = 0xf0; + SC_DEBUG(sc_link, SDEV_DB2, ("ahc_scsi_cmd\n")); + } +#endif + + /* + * get a scb to use. If the transfer + * is from a buf (possibly from interrupt time) + * then we can't allow it to sleep + */ + flags = xs->flags; + if ((flags & (ITSDONE|INUSE)) != INUSE) { + printf("%s: done or not in use?\n", ahc->sc_dev.dv_xname); + xs->flags &= ~ITSDONE; + xs->flags |= INUSE; + } + if ((scb = ahc_get_scb(ahc, flags)) == NULL) { + xs->error = XS_DRIVER_STUFFUP; + return (TRY_AGAIN_LATER); + } + scb->xs = xs; + +#ifdef AHC_MORE_DEBUG + if ((sc_link->target & 0xf) == DEBUGTARGET) { + sc_link->flags = 0xf0; + SC_DEBUG(sc_link, SDEV_DB3, ("start scb(%x)\n", scb)); + } +#endif + + if (flags & SCSI_RESET) { + /* XXX: Needs Implementation */ + printf("ahc: SCSI_RESET called.\n"); + } + + /* + * Put all the arguments for the xfer in the scb + */ + scb->control = 0; + if (ahc->tagenable & mask) + scb->control |= SCB_TE; + if ((ahc->needwdtr & mask) && !(ahc->wdtrpending & mask)) { + scb->control |= SCB_NEEDWDTR; + ahc->wdtrpending |= mask; + } + if ((ahc->needsdtr & mask) && !(ahc->sdtrpending & mask)) { + scb->control |= SCB_NEEDSDTR; + ahc->sdtrpending |= mask; + } + scb->target_channel_lun = ((sc_link->target << 4) & 0xF0) | + (sc_link->quirks & 0x08) | (sc_link->lun & 0x07); + scb->cmdlen = xs->cmdlen; + scb->cmdpointer = vtophys(xs->cmd); + + xs->resid = 0; + if (xs->datalen) { + scb->SG_list_pointer = vtophys(scb->ahc_dma); + sg = scb->ahc_dma; + seg = 0; + { + /* + * Set up the scatter gather block + */ +#ifdef AHC_MORE_DEBUG + if ((sc_link->target & 0xf) == DEBUGTARGET) { + sc_link->flags = 0xf0; + SC_DEBUG(sc_link, SDEV_DB4, + ("%ld @%x:- ", xs->datalen, xs->data)); + } +#endif + datalen = xs->datalen; + thiskv = (long) xs->data; + thisphys = vtophys(thiskv); + + while (datalen && seg < AHC_NSEG) { + bytes_this_seg = 0; + + /* put in the base address */ + sg->seg_addr = thisphys; + +#ifdef AHC_MORE_DEBUG + if ((sc_link->target & 0xf) == DEBUGTARGET) { + sc_link->flags = 0xf0; + SC_DEBUGN(sc_link, SDEV_DB4, ("0x%lx", + thisphys)); + } +#endif + + /* do it at least once */ + nextphys = thisphys; + while (datalen && thisphys == nextphys) { + /* + * This page is contiguous (physically) + * with the the last, just extend the + * length + */ + /* how far to the end of the page */ + nextphys = (thisphys & ~PGOFSET) + NBPG; + bytes_this_page = nextphys - thisphys; + /**** or the data ****/ + bytes_this_page = min(bytes_this_page, + datalen); + bytes_this_seg += bytes_this_page; + datalen -= bytes_this_page; + + /* get more ready for the next page */ + thiskv = (thiskv & ~PGOFSET) + NBPG; + if (datalen) + thisphys = vtophys(thiskv); + } + /* + * next page isn't contiguous, finish the seg + */ +#ifdef AHC_MORE_DEBUG + if ((sc_link->target & 0xf) == DEBUGTARGET) { + sc_link->flags = 0xf0; + SC_DEBUGN(sc_link, SDEV_DB4, ("(0x%x)", + bytes_this_seg)); + } +#endif + sg->seg_len = bytes_this_seg; + sg++; + seg++; + } + } + /*end of iov/kv decision */ + scb->SG_segment_count = seg; +#ifdef AHC_MORE_DEBUG + if ((sc_link->target & 0xf) == DEBUGTARGET) { + sc_link->flags = 0xf0; + SC_DEBUGN(sc_link, SDEV_DB4, ("\n")); + } +#endif + if (datalen) { + /* + * there's still data, must have run out of segs! + */ + printf("%s: ahc_scsi_cmd: more than %d dma segs\n", + ahc->sc_dev.dv_xname, AHC_NSEG); + xs->error = XS_DRIVER_STUFFUP; + ahc_free_scb(ahc, scb, flags); + return (COMPLETE); + } + } else { + scb->SG_list_pointer = (physaddr)0; + scb->SG_segment_count = 0; + } + +#ifdef AHC_DEBUG + if (sc_link->target == DEBUGTARGET) + ahc_print_scb(scb); +#endif + + s = splbio(); + + ahc_send_scb(ahc, scb); + + /* + * Usually return SUCCESSFULLY QUEUED + */ + if ((flags & SCSI_POLL) == 0) { + timeout(ahc_timeout, scb, (xs->timeout * hz) / 1000); + splx(s); +#ifdef AHC_MORE_DEBUG + if ((sc_link->target & 0xf) == DEBUGTARGET) { + sc_link->flags = 0xf0; + SC_DEBUG(sc_link, SDEV_DB3, ("cmd_sent\n")); + } +#endif + return (SUCCESSFULLY_QUEUED); + } + + splx(s); + + /* + * If we can't use interrupts, poll on completion + */ +#ifdef AHC_MORE_DEBUG + if ((sc_link->target & 0xf) == DEBUGTARGET) { + sc_link->flags = 0xf0; + SC_DEBUG(sc_link, SDEV_DB3, ("cmd_wait\n")); + } +#endif + if (ahc_poll(ahc, xs, xs->timeout)) { + ahc_timeout(scb); + if (ahc_poll(ahc, xs, 2000)) + ahc_timeout(scb); + } + return (COMPLETE); +} + + +/* + * A scb (and hence an scb entry on the board is put onto the + * free list. + */ +void +ahc_free_scb(ahc, scb, flags) + struct ahc_softc *ahc; + struct ahc_scb *scb; + int flags; +{ + int s; + + s = splbio(); + + scb->flags = SCB_FREE; + TAILQ_INSERT_TAIL(&ahc->free_scb, scb, chain); +#ifdef AHC_DEBUG + ahc->activescbs--; +#endif + + /* + * If there were none, wake anybody waiting for one to come free, + * starting with queued entries. + */ + if (scb->chain.tqe_next == 0) + wakeup(&ahc->free_scb); + + splx(s); +} + +/* XXXX check */ +static inline void +ahc_init_scb(ahc, scb) + struct ahc_softc *ahc; + struct ahc_scb *scb; +{ + int iobase = ahc->sc_iobase; + u_char scb_index; + + bzero(scb, sizeof(struct ahc_scb)); + scb->position = ahc->numscbs; + /* + * Place in the scbarray + * Never is removed. Position + * in ahc->scbarray is the scbarray + * position on the board we will + * load it into. + */ + ahc->scbarray[scb->position] = scb; + + /* + * Initialize the host memory location + * of this SCB down on the board and + * flag that it should be DMA's before + * reference. Also set its psuedo + * next pointer (for use in the psuedo + * list of SCBs waiting for selection) + * to SCB_LIST_NULL. + */ + scb->control = SCB_NEEDDMA; + scb->host_scb = vtophys(scb); + scb->next_waiting = SCB_LIST_NULL; + PAUSE_SEQUENCER(ahc); + scb_index = inb(SCBPTR + iobase); + outb(SCBPTR + iobase, scb->position); + outb(SCBCNT + iobase, SCBAUTO); + outsb(SCBARRAY + iobase, scb, 31); + outb(SCBCNT + iobase, 0); + outb(SCBPTR + iobase, scb_index); + UNPAUSE_SEQUENCER(ahc); + scb->control = 0; +} + +static inline void +ahc_reset_scb(ahc, scb) + struct ahc_softc *ahc; + struct ahc_scb *scb; +{ + + bzero(scb, SCB_BZERO_SIZE); +} + +/* + * Get a free scb + * + * If there are none, see if we can allocate a new one. + */ +struct ahc_scb * +ahc_get_scb(ahc, flags) + struct ahc_softc *ahc; + int flags; +{ + struct ahc_scb *scb; + int s; + + s = splbio(); + + /* + * If we can and have to, sleep waiting for one to come free + * but only if we can't allocate a new one. + */ + for (;;) { + scb = ahc->free_scb.tqh_first; + if (scb) { + TAILQ_REMOVE(&ahc->free_scb, scb, chain); + break; + } + if (ahc->numscbs < ahc->maxscbs) { + if (scb = (struct ahc_scb *) malloc(sizeof(struct ahc_scb), + M_TEMP, M_NOWAIT)) { + ahc_init_scb(ahc, scb); + ahc->numscbs++; + } else { + printf("%s: can't malloc scb\n", + ahc->sc_dev.dv_xname); + goto out; + } + break; + } + if ((flags & SCSI_NOSLEEP) != 0) + goto out; + tsleep(&ahc->free_scb, PRIBIO, "ahcscb", 0); + } + + ahc_reset_scb(ahc, scb); + scb->flags = SCB_ACTIVE; +#ifdef AHC_DEBUG + ahc->activescbs++; + if (ahc->activescbs == ahc->maxscbs) + printf("%s: Max SCBs active\n", ahc->sc_dev.dv_xname); +#endif + +out: + splx(s); + return (scb); +} + +/* XXXX check */ +void +ahc_loadseq(iobase) + int iobase; +{ + static u_char seqprog[] = { +# include "aic7xxx_seq.h" + }; + + outb(SEQCTL + iobase, PERRORDIS|SEQRESET|LOADRAM); + outsb(SEQRAM + iobase, seqprog, sizeof(seqprog)); + outb(SEQCTL + iobase, FASTMODE|SEQRESET); +} + +/* + * Function to poll for command completion when in poll mode + */ +int +ahc_poll(ahc, xs, count) + struct ahc_softc *ahc; + struct scsi_xfer *xs; + int count; +{ /* in msec */ + int iobase = ahc->sc_iobase; + int stport = INTSTAT + iobase; + + while (count) { + /* + * If we had interrupts enabled, would we + * have got an interrupt? + */ + if (inb(stport) & INT_PEND) + ahcintr(ahc); + if (xs->flags & ITSDONE) + return 0; + delay(1000); + count--; + } + return 1; +} + +/* XXXX check */ +void +ahc_abort_scb(ahc, scb) + struct ahc_softc *ahc; + struct ahc_scb *scb; +{ + int iobase = ahc->sc_iobase; + int found = 0; + int scb_index; + u_char flags; + u_char scb_control; + + PAUSE_SEQUENCER(ahc); + /* + * Case 1: In the QINFIFO + */ + { + int saved_queue[AHC_SCB_MAX]; + int i; + int queued = inb(QINCNT + iobase); + + for (i = 0; i < (queued - found); i++) { + saved_queue[i] = inb(QINFIFO + iobase); + if (saved_queue[i] == scb->position) { + i--; + found = 1; + } + } + /* Re-insert entries back into the queue */ + for (queued = 0; queued < i; queued++) + outb(QINFIFO + iobase, saved_queue[queued]); + + if (found) + goto done; + } + + scb_index = inb(SCBPTR + iobase); + /* + * Case 2: Not the active command + */ + if (scb_index != scb->position) { + /* + * Select the SCB we want to abort + * and turn off the disconnected bit. + * the driver will then abort the command + * and notify us of the abort. + */ + outb(SCBPTR + iobase, scb->position); + scb_control = inb(SCBARRAY + iobase); + scb_control &= ~SCB_DIS; + outb(SCBARRAY + iobase, scb_control); + outb(SCBPTR + iobase, scb_index); + goto done; + } + scb_control = inb(SCBARRAY + iobase); + if (scb_control & SCB_DIS) { + scb_control &= ~SCB_DIS; + outb(SCBARRAY + iobase, scb_control); + goto done; + } + /* + * Case 3: Currently active command + */ + if ((flags = inb(HA_FLAGS + iobase)) & ACTIVE_MSG) { + /* + * If there's a message in progress, + * reset the bus and have all devices renegotiate. + */ + if (scb->target_channel_lun & 0x08) { + ahc->needsdtr |= (ahc->needsdtr_orig & 0xff00); + ahc->sdtrpending &= 0x00ff; + outb(HA_ACTIVE1, 0); + } else if (ahc->type & AHC_WIDE) { + ahc->needsdtr = ahc->needsdtr_orig; + ahc->needwdtr = ahc->needwdtr_orig; + ahc->sdtrpending = 0; + ahc->wdtrpending = 0; + outb(HA_ACTIVE0, 0); + outb(HA_ACTIVE1, 0); + } else { + ahc->needsdtr |= (ahc->needsdtr_orig & 0x00ff); + ahc->sdtrpending &= 0xff00; + outb(HA_ACTIVE0, 0); + } + + /* Reset the bus */ + outb(SCSISEQ + iobase, SCSIRSTO); + delay(1000); + outb(SCSISEQ + iobase, 0); + goto done; + } + + /* + * Otherwise, set up an abort message and have the sequencer + * clean up + */ + outb(HA_FLAGS + iobase, flags | ACTIVE_MSG); + outb(HA_MSG_LEN + iobase, 1); + outb(HA_MSG_START + iobase, MSG_ABORT); + + outb(SCSISIGO + iobase, inb(HA_SIGSTATE + iobase) | 0x10); + +done: + scb->flags = SCB_ABORTED; + UNPAUSE_SEQUENCER(ahc); + ahc_done(ahc, scb); + return; +} + +void +ahc_timeout(arg) + void *arg; +{ + struct ahc_scb *scb = arg; + struct scsi_xfer *xs = scb->xs; + struct scsi_link *sc_link = xs->sc_link; + struct ahc_softc *ahc = sc_link->adapter_softc; + int s; + + sc_print_addr(sc_link); + printf("timed out"); + + s = splbio(); + +#ifdef SCSIDEBUG + show_scsi_cmd(scb->xs); +#endif +#ifdef AHC_DEBUG + if (ahc_debug & AHC_SHOWSCBS) + ahc_print_active_scb(ahc); +#endif /*AHC_DEBUG */ + + if (scb->flags & SCB_IMMED) { + printf("\n"); + scb->xs->retries = 0; /* I MEAN IT ! */ + scb->flags |= SCB_IMMED_FAIL; + ahc_done(ahc, scb); + splx(s); + return; + } + + /* + * If it has been through before, then + * a previous abort has failed, don't + * try abort again + */ + if (scb->flags == SCB_ABORTED) { + /* abort timed out */ + printf(" AGAIN\n"); + scb->xs->retries = 0; /* I MEAN IT ! */ + ahc_done(ahc, scb); + } else { + /* abort the operation that has timed out */ + printf("\n"); + scb->xs->error = XS_TIMEOUT; + scb->flags = SCB_ABORTED; + ahc_abort_scb(ahc, scb); + /* 2 secs for the abort */ + if ((xs->flags & SCSI_POLL) == 0) + timeout(ahc_timeout, scb, 2 * hz); + } + + splx(s); +} diff --git a/sys/dev/ic/aic7xxxvar.h b/sys/dev/ic/aic7xxxvar.h new file mode 100644 index 00000000000..2f98b187557 --- /dev/null +++ b/sys/dev/ic/aic7xxxvar.h @@ -0,0 +1,168 @@ +/* + * Interface to the generic driver for the aic7xxx based adaptec + * SCSI controllers. This is used to implement product specific + * probe and attach routines. + * + * Copyright (c) 1994, 1995 Justin T. Gibbs. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice immediately at the beginning of the file, without modification, + * this list of conditions, and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Absolutely no warranty of function or purpose is made by the author + * Justin T. Gibbs. + * 4. Modifications may be freely made to this file if the above conditions + * are met. + * + * $Id: aic7xxxvar.h,v 1.1 1995/10/09 09:49:31 mycroft Exp $ + */ + +#ifndef _AIC7XXX_H_ +#define _AIC7XXX_H_ + +/*#include "ahc.h" /* for NAHC from config */ + +#define AHC_NSEG 256 /* number of dma segments supported */ + +#define AHC_SCB_MAX 16 /* + * Up to 16 SCBs on some types of aic7xxx based + * boards. The aic7770 family only have 4 + */ + +/* #define AHCDEBUG */ + +typedef u_long physaddr; +typedef u_long physlen; + +struct ahc_dma_seg { + physaddr seg_addr; + physlen seg_len; +}; + +typedef u_char ahc_type; +#define AHC_NONE 0x00 +#define AHC_WIDE 0x02 /* Wide Channel */ +#define AHC_TWIN 0x08 /* Twin Channel */ +#define AHC_274 0x10 /* EISA Based Controller */ +#define AHC_284 0x20 /* VL/ISA Based Controller */ +#define AHC_AIC7870 0x40 /* PCI Based Controller */ +#define AHC_294 0xc0 /* PCI Based Controller */ + +/* + * The driver keeps up to MAX_SCB scb structures per card in memory. Only the + * first 26 bytes of the structure are valid for the hardware, the rest used + * for driver level bookeeping. The "__attribute ((packed))" tags ensure that + * gcc does not attempt to pad the long ints in the structure to word + * boundaries since the first 26 bytes of this structure must have the correct + * offsets for the hardware to find them. The driver is further optimized + * so that we only have to download the first 19 bytes since as long + * as we always use S/G, the last fields should be zero anyway. + */ +#if __GNUC__ >= 2 +#if __GNUC_MINOR__ <5 +#pragma pack(1) +#endif +#endif + +struct ahc_scb { +/* ------------ Begin hardware supported fields ---------------- */ +/*1*/ u_char control; +#define SCB_NEEDWDTR 0x80 /* Initiate Wide Negotiation */ +#define SCB_NEEDSDTR 0x40 /* Initiate Sync Negotiation */ +#define SCB_TE 0x20 /* Tag enable */ +#define SCB_NEEDDMA 0x08 /* Refresh SCB from host ram */ +#define SCB_DIS 0x04 +#define SCB_TAG_TYPE 0x3 +#define SIMPLE_QUEUE 0x0 +#define HEAD_QUEUE 0x1 +#define OR_QUEUE 0x2 +/*2*/ u_char target_channel_lun; /* 4/1/3 bits */ +/*3*/ u_char SG_segment_count; +/*7*/ physaddr SG_list_pointer __attribute__ ((packed)); +/*11*/ physaddr cmdpointer __attribute__ ((packed)); +/*12*/ u_char cmdlen; +/*14*/ u_char RESERVED[2]; /* must be zero */ +/*15*/ u_char target_status; +/*18*/ u_char residual_data_count[3]; +/*19*/ u_char residual_SG_segment_count; +#define SCB_DOWN_SIZE 19 /* amount to actually download */ +#define SCB_BZERO_SIZE 19 /* + * amount we need to clear between + * commands + */ +/*23*/ physaddr data __attribute__ ((packed)); +/*26*/ u_char datalen[3]; +#define SCB_UP_SIZE 26 /* + * amount we need to upload to perform + * a request sense. + */ +/*30*/ physaddr host_scb __attribute__ ((packed)); +/*31*/ u_char next_waiting; /* Used to thread SCBs awaiting + * selection + */ +#define SCB_LIST_NULL 0x10 /* SCB list equivelent to NULL */ +#if 0 + /* + * No real point in transferring this to the + * SCB registers. + */ + unsigned char RESERVED[1]; +#endif + /*-----------------end of hardware supported fields----------------*/ + TAILQ_ENTRY(ahc_scb) chain; + struct scsi_xfer *xs; /* the scsi_xfer for this cmd */ + int flags; +#define SCB_FREE 0 +#define SCB_ACTIVE 1 +#define SCB_ABORTED 2 +#define SCB_CHKSENSE 3 +#define SCB_IMMED 4 +#define SCB_IMMED_FAIL 8 + int position; /* Position in scbarray */ + struct ahc_dma_seg ahc_dma[AHC_NSEG] __attribute__ ((packed)); + struct scsi_sense sense_cmd; /* SCSI command block */ +}; + +#if __GNUC__ >= 2 +#if __GNUC_MINOR__ <5 +#pragma pack(4) +#endif +#endif + +struct ahc_softc { + struct device sc_dev; + void *sc_ih; + + int sc_iobase; + int sc_irq; + + ahc_type type; + + struct ahc_scb *scbarray[AHC_SCB_MAX]; /* Mirror boards scbarray */ + TAILQ_HEAD(, ahc_scb) free_scb; + int ahc_scsi_dev; /* our scsi id */ + int ahc_scsi_dev_b; /* B channel scsi id */ + struct ahc_scb *immed_ecb; /* an outstanding immediete command */ + struct scsi_link sc_link; + struct scsi_link sc_link_b; /* Second bus for Twin channel cards */ + u_short needsdtr_orig; /* Targets we initiate sync neg with */ + u_short needwdtr_orig; /* Targets we initiate wide neg with */ + u_short needsdtr; /* Current list of negotiated targets */ + u_short needwdtr; /* Current list of negotiated targets */ + u_short sdtrpending; /* Pending SDTR to these targets */ + u_short wdtrpending; /* Pending WDTR to these targets */ + u_short tagenable; /* Targets that can handle tagqueing */ + int numscbs; + int activescbs; + u_char maxscbs; + u_char unpause; + u_char pause; +}; + +#endif /* _AIC7XXX_H_ */ diff --git a/sys/dev/microcode/Makefile.inc b/sys/dev/microcode/Makefile.inc new file mode 100644 index 00000000000..8ec2e74ddd0 --- /dev/null +++ b/sys/dev/microcode/Makefile.inc @@ -0,0 +1 @@ +.include "$S/dev/microcode/aic7xxx/Makefile.inc" diff --git a/sys/dev/microcode/aic7xxx/Makefile.inc b/sys/dev/microcode/aic7xxx/Makefile.inc new file mode 100644 index 00000000000..b701d2c7747 --- /dev/null +++ b/sys/dev/microcode/aic7xxx/Makefile.inc @@ -0,0 +1,10 @@ +.if target(aic7xxx.o) +PATH: $S/dev/microcode/aic7xxx + +aic7xxx.o: aic7xxx_seq.h + +aic7xxx_seq.h: aic7xxx_asm $S/dev/microcode/aic7xxx/aic7xxx.seq + ./aic7xxx_asm -v -o ${.TARGET} $S/dev/microcode/aic7xxx/aic7xxx.seq + +aic7xxx_asm: $S/dev/microcode/aic7xxx/aic7xxx_asm.c +.endif diff --git a/sys/dev/microcode/aic7xxx/aic7xxx.seq b/sys/dev/microcode/aic7xxx/aic7xxx.seq new file mode 100644 index 00000000000..242115929b8 --- /dev/null +++ b/sys/dev/microcode/aic7xxx/aic7xxx.seq @@ -0,0 +1,1262 @@ +##+M######################################################################### +# Adaptec 274x/284x/294x device driver for Linux and FreeBSD. +# +# Copyright (c) 1994 John Aycock +# The University of Calgary Department of Computer Science. +# All rights reserved. +# +# Modifications/enhancements: +# Copyright (c) 1994, 1995 Justin Gibbs. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions, and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# 3. All advertising materials mentioning features or use of this software +# must display the following acknowledgement: +# This product includes software developed by the University of Calgary +# Department of Computer Science and its contributors. +# 4. Neither the name of the University nor the names of its contributors +# may be used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND +# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +# OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +# OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +# SUCH DAMAGE. +# +# FreeBSD, Twin, Wide, 2 command per target support, tagged queuing and other +# optimizations provided by Justin T. Gibbs (gibbs@FreeBSD.org) +# +##-M######################################################################### + +VERSION AIC7XXX_SEQ_VER "$Id: aic7xxx.seq,v 1.1 1995/10/09 09:49:37 mycroft Exp $" + +SCBMASK = 0x1f + +SCSISEQ = 0x00 +ENRSELI = 0x10 +SXFRCTL0 = 0x01 +SXFRCTL1 = 0x02 +SCSISIGI = 0x03 +SCSISIGO = 0x03 +SCSIRATE = 0x04 +SCSIID = 0x05 +SCSIDATL = 0x06 +STCNT = 0x08 +STCNT+0 = 0x08 +STCNT+1 = 0x09 +STCNT+2 = 0x0a +CLRSINT0 = 0x0b +SSTAT0 = 0x0b +SELDO = 0x40 +SELDI = 0x20 +CLRSINT1 = 0x0c +SSTAT1 = 0x0c +SIMODE1 = 0x11 +SCSIBUSL = 0x12 +SHADDR = 0x14 +SELID = 0x19 +SBLKCTL = 0x1f +SEQCTL = 0x60 +A = 0x64 # == ACCUM +SINDEX = 0x65 +DINDEX = 0x66 +ALLZEROS = 0x6a +NONE = 0x6a +SINDIR = 0x6c +DINDIR = 0x6d +FUNCTION1 = 0x6e +HADDR = 0x88 +HADDR+1 = 0x89 +HADDR+2 = 0x8a +HADDR+3 = 0x8b +HCNT = 0x8c +HCNT+0 = 0x8c +HCNT+1 = 0x8d +HCNT+2 = 0x8e +SCBPTR = 0x90 +INTSTAT = 0x91 +DFCNTRL = 0x93 +DFSTATUS = 0x94 +DFDAT = 0x99 +QINFIFO = 0x9b +QINCNT = 0x9c +QOUTFIFO = 0x9d + +SCSICONF_A = 0x5a +SCSICONF_B = 0x5b + +# The two reserved bytes at SCBARRAY+1[23] are expected to be set to +# zero, and the reserved bit in SCBARRAY+0 is used as an internal flag +# to indicate whether or not to reload scatter-gather parameters after +# a disconnect. We also use bits 6 & 7 to indicate whether or not to +# initiate SDTR or WDTR repectively when starting this command. +# +SCBARRAY+0 = 0xa0 + +DISCONNECTED = 0x04 +NEEDDMA = 0x08 +SG_LOAD = 0x10 +TAG_ENB = 0x20 +NEEDSDTR = 0x40 +NEEDWDTR = 0x80 + +SCBARRAY+1 = 0xa1 +SCBARRAY+2 = 0xa2 +SCBARRAY+3 = 0xa3 +SCBARRAY+4 = 0xa4 +SCBARRAY+5 = 0xa5 +SCBARRAY+6 = 0xa6 +SCBARRAY+7 = 0xa7 +SCBARRAY+8 = 0xa8 +SCBARRAY+9 = 0xa9 +SCBARRAY+10 = 0xaa +SCBARRAY+11 = 0xab +SCBARRAY+12 = 0xac +SCBARRAY+13 = 0xad +SCBARRAY+14 = 0xae +SCBARRAY+15 = 0xaf +SCBARRAY+16 = 0xb0 +SCBARRAY+17 = 0xb1 +SCBARRAY+18 = 0xb2 +SCBARRAY+19 = 0xb3 +SCBARRAY+20 = 0xb4 +SCBARRAY+21 = 0xb5 +SCBARRAY+22 = 0xb6 +SCBARRAY+23 = 0xb7 +SCBARRAY+24 = 0xb8 +SCBARRAY+25 = 0xb9 +SCBARRAY+26 = 0xba +SCBARRAY+27 = 0xbb +SCBARRAY+28 = 0xbc +SCBARRAY+29 = 0xbd +SCBARRAY+30 = 0xbe + +BAD_PHASE = 0x01 # unknown scsi bus phase +CMDCMPLT = 0x02 # Command Complete +SEND_REJECT = 0x11 # sending a message reject +NO_IDENT = 0x21 # no IDENTIFY after reconnect +NO_MATCH = 0x31 # no cmd match for reconnect +MSG_SDTR = 0x41 # SDTR message recieved +MSG_WDTR = 0x51 # WDTR message recieved +MSG_REJECT = 0x61 # Reject message recieved +BAD_STATUS = 0x71 # Bad status from target +RESIDUAL = 0x81 # Residual byte count != 0 +ABORT_TAG = 0x91 # Sent an ABORT_TAG message + +# The host adapter card (at least the BIOS) uses 20-2f for SCSI +# device information, 32-33 and 5a-5f as well. As it turns out, the +# BIOS trashes 20-2f, writing the synchronous negotiation results +# on top of the BIOS values, so we re-use those for our per-target +# scratchspace (actually a value that can be copied directly into +# SCSIRATE). The kernel driver will enable synchronous negotiation +# for all targets that have a value other than 0 in the lower four +# bits of the target scratch space. This should work irregardless of +# whether the bios has been installed. NEEDWDTR and NEEDSDTR are the top +# two bits of the SCB control byte. The kernel driver will set these +# when a WDTR or SDTR message should be sent to the target the SCB's +# command references. +# +# REJBYTE contains the first byte of a MESSAGE IN message, so the driver +# can report an intelligible error if a message is rejected. +# +# FLAGS's high bit is true if we are currently handling a reselect; +# its next-highest bit is true ONLY IF we've seen an IDENTIFY message +# from the reselecting target. If we haven't had IDENTIFY, then we have +# no idea what the lun is, and we can't select the right SCB register +# bank, so force a kernel panic if the target attempts a data in/out or +# command phase instead of corrupting something. FLAGS also contains +# configuration bits so that we can optimize for TWIN and WIDE controllers +# as well as the MAX_SYNC bit which we set when we want to negotiate for +# 10MHz irregardless of what the per target scratch space says. +# +# Note that SG_NEXT occupies four bytes. +# +SYNCNEG = 0x20 + +REJBYTE = 0x31 +DISC_DSB_A = 0x32 +DISC_DSB_B = 0x33 + +MSG_LEN = 0x34 +MSG_START+0 = 0x35 +MSG_START+1 = 0x36 +MSG_START+2 = 0x37 +MSG_START+3 = 0x38 +MSG_START+4 = 0x39 +MSG_START+5 = 0x3a +-MSG_START+0 = 0xcb # 2's complement of MSG_START+0 + +ARG_1 = 0x4a # sdtr conversion args & return +BUS_16_BIT = 0x01 +RETURN_1 = 0x4a + +SIGSTATE = 0x4b # value written to SCSISIGO + +# Linux users should use 0xc (12) for SG_SIZEOF +SG_SIZEOF = 0x8 # sizeof(struct ahc_dma) +#SG_SIZEOF = 0xc # sizeof(struct scatterlist) +SCB_SIZEOF = 0x13 # sizeof SCB to DMA (19 bytes) + +SG_NOLOAD = 0x4c # load SG pointer/length? +SG_COUNT = 0x4d # working value of SG count +SG_NEXT = 0x4e # working value of SG pointer +SG_NEXT+0 = 0x4e +SG_NEXT+1 = 0x4f +SG_NEXT+2 = 0x50 +SG_NEXT+3 = 0x51 + +SCBCOUNT = 0x52 # the actual number of SCBs +FLAGS = 0x53 # Device configuration flags +TWIN_BUS = 0x01 +WIDE_BUS = 0x02 +MAX_SYNC = 0x08 +ACTIVE_MSG = 0x20 +IDENTIFY_SEEN = 0x40 +RESELECTED = 0x80 + +ACTIVE_A = 0x54 +ACTIVE_B = 0x55 +SAVED_TCL = 0x56 # Temporary storage for the + # target/channel/lun of a + # reconnecting target + +# After starting the selection hardware, we return to the "poll_for_work" +# loop so that we can check for reconnecting targets as well as for our +# selection to complete just in case the reselection wins bus arbitration. +# The problem with this is that we must keep track of the SCB that we've +# already pulled from the QINFIFO and started the selection on just in case +# the reselection wins so that we can retry the selection at a later time. +# This problem cannot be resolved by holding a single entry in scratch +# ram since a reconnecting target can request sense and this will create +# yet another SCB waiting for selection. The solution used here is to +# use byte 31 of the SCB as a psuedo-next pointer and to thread a list +# of SCBs that are awaiting selection. Since 0 is a valid SCB offset, +# SCB_LIST_NULL is 0x10 which is out of range. The kernel driver must +# add an entry to this list everytime a request sense occurs. The sequencer +# will automatically consume the entries. + +WAITING_SCBH = 0x57 # head of list of SCBs awaiting + # selection +WAITING_SCBT = 0x58 # tail of list of SCBs awaiting + # selection +SCB_LIST_NULL = 0x10 + + +# Poll QINCNT for work - the lower bits contain +# the number of entries in the Queue In FIFO. +# +start: + test WAITING_SCBH,SCB_LIST_NULL jz start_waiting +poll_for_work: + test FLAGS,TWIN_BUS jz start2 # Are we a twin channel device? +# For fairness, we check the other bus first, since we just finished a +# transaction on the current channel. + xor SBLKCTL,0x08 # Toggle to the other bus + test SSTAT0,SELDI jnz reselect + test SSTAT0,SELDO jnz select + xor SBLKCTL,0x08 # Toggle to the original bus +start2: + test SSTAT0,SELDI jnz reselect + test SSTAT0,SELDO jnz select + test WAITING_SCBH,SCB_LIST_NULL jz start_waiting + test QINCNT,SCBMASK jz poll_for_work + +# We have at least one queued SCB now and we don't have any +# SCBs in the list of SCBs awaiting selection. Set the SCB +# pointer from the FIFO so we see the right bank of SCB +# registers, then set SCSI options and set the initiator and +# target SCSI IDs. +# + mov SCBPTR,QINFIFO + +# If the control byte of this SCB has the NEEDDMA flag set, we have +# yet to DMA it from host memory + +test SCBARRAY+0,NEEDDMA jz test_busy + clr HCNT+2 + clr HCNT+1 + mvi HCNT+0,SCB_SIZEOF + + mvi DINDEX,HADDR + mvi SCBARRAY+26 call bcopy_4 + + mvi DFCNTRL,0xd # HDMAEN|DIRECTION|FIFORESET + +# Wait for DMA from host memory to data FIFO to complete, then disable +# DMA and wait for it to acknowledge that it's off. +# + call dma_finish + +# Copy the SCB from the FIFO to the SCBARRAY + + mvi DINDEX, SCBARRAY+0 + call bcopy_3_dfdat + call bcopy_4_dfdat + call bcopy_4_dfdat + call bcopy_4_dfdat + call bcopy_4_dfdat + +# See if there is not already an active SCB for this target. This code +# locks out on a per target basis instead of target/lun. Although this +# is not ideal for devices that have multiple luns active at the same +# time, it is faster than looping through all SCB's looking for active +# commands. It may be benificial to make findscb a more general procedure +# to see if the added cost of the search is negligible. This code also +# assumes that the kernel driver will clear the active flags on board +# initialization, board reset, and a target's SELTO. + +test_busy: + test SCBARRAY+0,0x20 jnz start_scb + and FUNCTION1,0x70,SCBARRAY+1 + mov A,FUNCTION1 + test SCBARRAY+1,0x88 jz test_a # Id < 8 && A channel + + test ACTIVE_B,A jnz requeue + or ACTIVE_B,A # Mark the current target as busy + jmp start_scb + +# Place the currently active back on the queue for later processing +requeue: + mov QINFIFO, SCBPTR + jmp poll_for_work + +# Pull the first entry off of the waiting for selection list +start_waiting: + mov SCBPTR,WAITING_SCBH + jmp start_scb + +test_a: + test ACTIVE_A,A jnz requeue + or ACTIVE_A,A # Mark the current target as busy + +start_scb: + and SINDEX,0xf7,SBLKCTL #Clear the channel select bit + and A,0x08,SCBARRAY+1 #Get new channel bit + or SINDEX,A + mov SBLKCTL,SINDEX # select channel + mov SCBARRAY+1 call initialize_scsiid + +# Enable selection phase as an initiator, and do automatic ATN +# after the selection. We do this now so that we can overlap the +# rest of our work to set up this target with the arbitration and +# selection bus phases. +# +start_selection: + or SCSISEQ,0x48 # ENSELO|ENAUTOATNO + mov WAITING_SCBH, SCBPTR + clr SG_NOLOAD + and FLAGS,0x3f # !RESELECTING + +# As soon as we get a successful selection, the target should go +# into the message out phase since we have ATN asserted. Prepare +# the message to send, locking out the device driver. If the device +# driver hasn't beaten us with an ABORT or RESET message, then tack +# on an SDTR negotiation if required. +# +# Messages are stored in scratch RAM starting with a flag byte (high bit +# set means active message), one length byte, and then the message itself. +# + mov SCBARRAY+1 call disconnect # disconnect ok? + + and SINDEX,0x7,SCBARRAY+1 # lun + or SINDEX,A # return value from disconnect + or SINDEX,0x80 call mk_mesg # IDENTIFY message + + mov A,SINDEX + test SCBARRAY+0,0xe0 jz !message # WDTR, SDTR or TAG?? + cmp MSG_START+0,A jne !message # did driver beat us? + +# Tag Message if Tag enabled in SCB control block. Use SCBPTR as the tag +# value + +mk_tag: + mvi DINDEX, MSG_START+1 + test SCBARRAY+0,TAG_ENB jz mk_tag_done + and A,0x23,SCBARRAY+0 + mov DINDIR,A + mov DINDIR,SCBPTR + + add MSG_LEN,-MSG_START+0,DINDEX # update message length + +mk_tag_done: + + mov DINDEX call mk_dtr # build DTR message if needed + +!message: + jmp poll_for_work + +# Reselection has been initiated by a target. Make a note that we've been +# reselected, but haven't seen an IDENTIFY message from the target +# yet. +# +reselect: + mov SELID call initialize_scsiid + and FLAGS,0x3f # reselected, no IDENTIFY + or FLAGS,RESELECTED jmp select2 + +# After the selection, remove this SCB from the "waiting for selection" +# list. This is achieved by simply moving our "next" pointer into +# WAITING_SCBH and setting our next pointer to null so that the next +# time this SCB is used, we don't get confused. +# +select: + or SCBARRAY+0,NEEDDMA + mov WAITING_SCBH,SCBARRAY+30 + mvi SCBARRAY+30,SCB_LIST_NULL +select2: + call initialize_for_target + mvi SCSISEQ,ENRSELI + mvi CLRSINT0,0x60 # CLRSELDI|CLRSELDO + mvi CLRSINT1,0x8 # CLRBUSFREE + +# Main loop for information transfer phases. If BSY is false, then +# we have a bus free condition, expected or not. Otherwise, wait +# for the target to assert REQ before checking MSG, C/D and I/O +# for the bus phase. +# +# We can't simply look at the values of SCSISIGI here (if we want +# to do synchronous data transfer), because the target won't assert +# REQ if it's already sent us some data that we haven't acknowledged +# yet. +# +ITloop: + test SSTAT1,0x8 jnz p_busfree # BUSFREE + test SSTAT1,0x1 jz ITloop # REQINIT + + and A,0xe0,SCSISIGI # CDI|IOI|MSGI + + cmp ALLZEROS,A je p_dataout + cmp A,0x40 je p_datain + cmp A,0x80 je p_command + cmp A,0xc0 je p_status + cmp A,0xa0 je p_mesgout + cmp A,0xe0 je p_mesgin + + mvi INTSTAT,BAD_PHASE # unknown - signal driver + +p_dataout: + mvi 0 call scsisig # !CDO|!IOO|!MSGO + call assert + call sg_load + + mvi DINDEX,HADDR + mvi SCBARRAY+19 call bcopy_4 + +# mvi DINDEX,HCNT # implicit since HCNT is next to HADDR + mvi SCBARRAY+23 call bcopy_3 + + mvi DINDEX,STCNT + mvi SCBARRAY+23 call bcopy_3 + +# If we are the last SG block, don't set wideodd. + test SCBARRAY+18,0xff jnz p_dataout_wideodd + mvi 0x3d call dma # SCSIEN|SDMAEN|HDMAEN| + # DIRECTION|FIFORESET + jmp p_dataout_rest + +p_dataout_wideodd: + mvi 0xbd call dma # WIDEODD|SCSIEN|SDMAEN|HDMAEN| + # DIRECTION|FIFORESET + +p_dataout_rest: +# After a DMA finishes, save the final transfer pointer and count +# back into the SCB, in case a device disconnects in the middle of +# a transfer. Use SHADDR and STCNT instead of HADDR and HCNT, since +# it's a reflection of how many bytes were transferred on the SCSI +# (as opposed to the host) bus. +# + mvi DINDEX,SCBARRAY+23 + mvi STCNT call bcopy_3 + + mvi DINDEX,SCBARRAY+19 + mvi SHADDR call bcopy_4 + + call sg_advance + mov SCBARRAY+18,SG_COUNT # residual S/G count + + jmp ITloop + +p_datain: + mvi 0x40 call scsisig # !CDO|IOO|!MSGO + call assert + call sg_load + + mvi DINDEX,HADDR + mvi SCBARRAY+19 call bcopy_4 + +# mvi DINDEX,HCNT # implicit since HCNT is next to HADDR + mvi SCBARRAY+23 call bcopy_3 + + mvi DINDEX,STCNT + mvi SCBARRAY+23 call bcopy_3 + +# If we are the last SG block, don't set wideodd. + test SCBARRAY+18,0xff jnz p_datain_wideodd + mvi 0x39 call dma # SCSIEN|SDMAEN|HDMAEN| + # !DIRECTION|FIFORESET + jmp p_datain_rest +p_datain_wideodd: + mvi 0xb9 call dma # WIDEODD|SCSIEN|SDMAEN|HDMAEN| + # !DIRECTION|FIFORESET +p_datain_rest: + mvi DINDEX,SCBARRAY+23 + mvi STCNT call bcopy_3 + + mvi DINDEX,SCBARRAY+19 + mvi SHADDR call bcopy_4 + + call sg_advance + mov SCBARRAY+18,SG_COUNT # residual S/G count + + jmp ITloop + +# Command phase. Set up the DMA registers and let 'er rip - the +# two bytes after the SCB SCSI_cmd_length are zeroed by the driver, +# so we can copy those three bytes directly into HCNT. +# +p_command: + mvi 0x80 call scsisig # CDO|!IOO|!MSGO + call assert + + mvi DINDEX,HADDR + mvi SCBARRAY+7 call bcopy_4 + +# mvi DINDEX,HCNT # implicit since HCNT is next to HADDR + mvi SCBARRAY+11 call bcopy_3 + + mvi DINDEX,STCNT + mvi SCBARRAY+11 call bcopy_3 + + mvi 0x3d call dma # SCSIEN|SDMAEN|HDMAEN| + # DIRECTION|FIFORESET + jmp ITloop + +# Status phase. Wait for the data byte to appear, then read it +# and store it into the SCB. +# +p_status: + mvi 0xc0 call scsisig # CDO|IOO|!MSGO + + mvi SCBARRAY+14 call inb_first + jmp p_mesgin_done + +# Message out phase. If there is no active message, but the target +# took us into this phase anyway, build a no-op message and send it. +# +p_mesgout: + mvi 0xa0 call scsisig # CDO|!IOO|MSGO + mvi 0x8 call mk_mesg # build NOP message + + clr STCNT+2 + clr STCNT+1 + +# Set up automatic PIO transfer from MSG_START. Bit 3 in +# SXFRCTL0 (SPIOEN) is already on. +# + mvi SINDEX,MSG_START+0 + mov DINDEX,MSG_LEN + +# When target asks for a byte, drop ATN if it's the last one in +# the message. Otherwise, keep going until the message is exhausted. +# (We can't use outb for this since it wants the input in SINDEX.) +# +# Keep an eye out for a phase change, in case the target issues +# a MESSAGE REJECT. +# +p_mesgout2: + test SSTAT0,0x2 jz p_mesgout2 # SPIORDY + test SSTAT1,0x10 jnz p_mesgout6 # PHASEMIS + + cmp DINDEX,1 jne p_mesgout3 # last byte? + mvi CLRSINT1,0x40 # CLRATNO - drop ATN + +# Write a byte to the SCSI bus. The AIC-7770 refuses to automatically +# send ACKs in automatic PIO or DMA mode unless you make sure that the +# "expected" bus phase in SCSISIGO matches the actual bus phase. This +# behaviour is completely undocumented and caused me several days of +# grief. +# +# After plugging in different drives to test with and using a longer +# SCSI cable, I found that I/O in Automatic PIO mode ceased to function, +# especially when transferring >1 byte. It seems to be much more stable +# if STCNT is set to one before the transfer, and SDONE (in SSTAT0) is +# polled for transfer completion - for both output _and_ input. The +# only theory I have is that SPIORDY doesn't drop right away when SCSIDATL +# is accessed (like the documentation says it does), and that on a longer +# cable run, the sequencer code was fast enough to loop back and see +# an SPIORDY that hadn't dropped yet. +# +p_mesgout3: + mvi STCNT+0, 0x01 + mov SCSIDATL,SINDIR + +p_mesgout4: + test SSTAT0,0x4 jz p_mesgout4 # SDONE + dec DINDEX + test DINDEX,0xff jnz p_mesgout2 + +# If the next bus phase after ATN drops is a message out, it means +# that the target is requesting that the last message(s) be resent. +# +p_mesgout5: + test SSTAT1,0x8 jnz p_mesgout6 # BUSFREE + test SSTAT1,0x1 jz p_mesgout5 # REQINIT + + and A,0xe0,SCSISIGI # CDI|IOI|MSGI + cmp A,0xa0 jne p_mesgout6 + mvi 0x10 call scsisig # ATNO - re-assert ATN + + jmp ITloop + +p_mesgout6: + mvi CLRSINT1,0x40 # CLRATNO - in case of PHASEMIS + and FLAGS,0xdf # no active msg + jmp ITloop + +# Message in phase. Bytes are read using Automatic PIO mode, but not +# using inb. This alleviates a race condition, namely that if ATN had +# to be asserted under Automatic PIO mode, it had to beat the SCSI +# circuitry sending an ACK to the target. This showed up under heavy +# loads and really confused things, since ABORT commands wouldn't be +# seen by the drive after an IDENTIFY message in until it had changed +# to a data I/O phase. +# +p_mesgin: + mvi 0xe0 call scsisig # CDO|IOO|MSGO + mvi A call inb_first # read the 1st message byte + mvi REJBYTE,A # save it for the driver + + cmp ALLZEROS,A jne p_mesgin1 + +# We got a "command complete" message, so put the SCB pointer +# into the Queue Out, and trigger a completion interrupt. +# Check status for non zero return and interrupt driver if needed +# This allows the driver to interpret errors only when they occur +# instead of always uploading the scb. If the status is SCSI_CHECK, +# the driver will download a new scb requesting sense to replace +# the old one, modify the "waiting for selection" SCB list and set +# RETURN_1 to 0x80. If RETURN_1 is set to 0x80 the sequencer imediately +# jumps to main loop where it will run down the waiting SCB list. +# If the kernel driver does not wish to request sense, it need +# only clear RETURN_1, and the command is allowed to complete. We don't +# bother to post to the QOUTFIFO in the error case since it would require +# extra work in the kernel driver to ensure that the entry was removed +# before the command complete code tried processing it. + +# First check for residuals + test SCBARRAY+15,0xff jnz resid + test SCBARRAY+16,0xff jnz resid + test SCBARRAY+17,0xff jnz resid + +check_status: + test SCBARRAY+14,0xff jz status_ok # 0 Status? + mvi INTSTAT,BAD_STATUS # let driver know + test RETURN_1, 0x80 jz status_ok + jmp p_mesgin_done + +status_ok: +# First, mark this target as free. + test SCBARRAY+0,0x20 jnz complete # Tagged command + and FUNCTION1,0x70,SCBARRAY+1 + mov A,FUNCTION1 + test SCBARRAY+1,0x88 jz clear_a + xor ACTIVE_B,A + jmp complete + +clear_a: + xor ACTIVE_A,A + +complete: + mov QOUTFIFO,SCBPTR + mvi INTSTAT,CMDCMPLT + jmp p_mesgin_done + +# If we have a residual count, interrupt and tell the host. Other +# alternatives are to pause the sequencer on all command completes (yuck), +# dma the resid directly to the host (slick, but a ton of instructions), or +# have the sequencer pause itself when it encounters a non-zero resid +# (unecessary pause just to flag the command -- yuck, but takes few instructions +# and since it shouldn't happen that often is good enough for our purposes). + +resid: + mvi INTSTAT,RESIDUAL + jmp check_status + +# Is it an extended message? We only support the synchronous and wide data +# transfer request messages, which will probably be in response to +# WDTR or SDTR message outs from us. If it's not SDTR or WDTR, reject it - +# apparently this can be done after any message in byte, according +# to the SCSI-2 spec. +# +p_mesgin1: + cmp A,1 jne p_mesgin2 # extended message code? + + mvi ARG_1 call inb_next # extended message length + mvi A call inb_next # extended message code + + cmp A,1 je p_mesginSDTR # Syncronous negotiation message + cmp A,3 je p_mesginWDTR # Wide negotiation message + jmp p_mesginN + +p_mesginWDTR: + cmp ARG_1,2 jne p_mesginN # extended mesg length = 2 + mvi A call inb_next # Width of bus + mvi INTSTAT,MSG_WDTR # let driver know + test RETURN_1,0x80 jz p_mesgin_done# Do we need to send WDTR? + +# We didn't initiate the wide negotiation, so we must respond to the request + and RETURN_1,0x7f # Clear the SEND_WDTR Flag + or FLAGS,ACTIVE_MSG + mvi DINDEX,MSG_START+0 + mvi MSG_START+0 call mk_wdtr # build WDTR message + or SINDEX,0x10,SIGSTATE # turn on ATNO + call scsisig + jmp p_mesgin_done + +p_mesginSDTR: + cmp ARG_1,3 jne p_mesginN # extended mesg length = 3 + mvi ARG_1 call inb_next # xfer period + mvi A call inb_next # REQ/ACK offset + mvi INTSTAT,MSG_SDTR # call driver to convert + + test RETURN_1,0xc0 jz p_mesgin_done# Do we need to mk_sdtr or rej? + test RETURN_1,0x40 jnz p_mesginN # Requested SDTR too small - rej + or FLAGS,ACTIVE_MSG + mvi DINDEX, MSG_START+0 + mvi MSG_START+0 call mk_sdtr + or SINDEX,0x10,SIGSTATE # turn on ATNO + call scsisig + jmp p_mesgin_done + +# Is it a disconnect message? Set a flag in the SCB to remind us +# and await the bus going free. +# +p_mesgin2: + cmp A,4 jne p_mesgin3 # disconnect code? + + or SCBARRAY+0,0x4 # set "disconnected" bit + jmp p_mesgin_done + +# Save data pointers message? Copy working values into the SCB, +# usually in preparation for a disconnect. +# +p_mesgin3: + cmp A,2 jne p_mesgin4 # save data pointers code? + + call sg_ram2scb + jmp p_mesgin_done + +# Restore pointers message? Data pointers are recopied from the +# SCB anyway at the start of any DMA operation, so the only thing +# to copy is the scatter-gather values. +# +p_mesgin4: + cmp A,3 jne p_mesgin5 # restore pointers code? + + call sg_scb2ram + jmp p_mesgin_done + +# Identify message? For a reconnecting target, this tells us the lun +# that the reconnection is for - find the correct SCB and switch to it, +# clearing the "disconnected" bit so we don't "find" it by accident later. +# +p_mesgin5: + test A,0x80 jz p_mesgin6 # identify message? + + test A,0x78 jnz p_mesginN # !DiscPriv|!LUNTAR|!Reserved + + and A,0x07 # lun in lower three bits + or SAVED_TCL,A,SELID + and SAVED_TCL,0xf7 + and A,0x08,SBLKCTL # B Channel?? + or SAVED_TCL,A + call inb_last # ACK + mov ALLZEROS call findSCB +setup_SCB: + and SCBARRAY+0,0xfb # clear disconnect bit in SCB + or FLAGS,IDENTIFY_SEEN # make note of IDENTIFY + + call sg_scb2ram # implied restore pointers + # required on reselect + jmp ITloop +get_tag: + mvi A call inb_first + cmp A,0x20 jne return # Simple Tag message? + mvi A call inb_next + call inb_last + test A,0xf0 jnz abort_tag # Tag in range? + mov SCBPTR,A + mov A,SAVED_TCL + cmp SCBARRAY+1,A jne abort_tag + test SCBARRAY+0,TAG_ENB jz abort_tag + ret +abort_tag: + or SINDEX,0x10,SIGSTATE # turn on ATNO + call scsisig + mvi INTSTAT,ABORT_TAG # let driver know + mvi 0xd call mk_mesg # ABORT TAG message + ret + +# Message reject? Let the kernel driver handle this. If we have an +# outstanding WDTR or SDTR negotiation, assume that it's a response from +# the target selecting 8bit or asynchronous transfer, otherwise just ignore +# it since we have no clue what it pertains to. +# +p_mesgin6: + cmp A,7 jne p_mesgin7 # message reject code? + + mvi INTSTAT, MSG_REJECT + jmp p_mesgin_done + +# [ ADD MORE MESSAGE HANDLING HERE ] +# +p_mesgin7: + +# We have no idea what this message in is, and there's no way +# to pass it up to the kernel, so we issue a message reject and +# hope for the best. Since we're now using manual PIO mode to +# read in the message, there should no longer be a race condition +# present when we assert ATN. In any case, rejection should be a +# rare occurrence - signal the driver when it happens. +# +p_mesginN: + or SINDEX,0x10,SIGSTATE # turn on ATNO + call scsisig + mvi INTSTAT,SEND_REJECT # let driver know + + mvi 0x7 call mk_mesg # MESSAGE REJECT message + +p_mesgin_done: + call inb_last # ack & turn auto PIO back on + jmp ITloop + + +# Bus free phase. It might be useful to interrupt the device +# driver if we aren't expecting this. For now, make sure that +# ATN isn't being asserted and look for a new command. +# +p_busfree: + mvi CLRSINT1,0x40 # CLRATNO + clr SIGSTATE + jmp start + +# Instead of a generic bcopy routine that requires an argument, we unroll +# the two cases that are actually used, and call them explicitly. This +# not only reduces the overhead of doing a bcopy by 2/3rds, but ends up +# saving space in the program since you don't have to put the argument +# into the accumulator before the call. Both functions expect DINDEX to +# contain the destination address and SINDEX to contain the source +# address. +bcopy_3: + mov DINDIR,SINDIR + mov DINDIR,SINDIR + mov DINDIR,SINDIR ret + +bcopy_4: + mov DINDIR,SINDIR + mov DINDIR,SINDIR + mov DINDIR,SINDIR + mov DINDIR,SINDIR ret + +bcopy_3_dfdat: + mov DINDIR,DFDAT + mov DINDIR,DFDAT + mov DINDIR,DFDAT ret + +bcopy_4_dfdat: + mov DINDIR,DFDAT + mov DINDIR,DFDAT + mov DINDIR,DFDAT + mov DINDIR,DFDAT ret + +# Locking the driver out, build a one-byte message passed in SINDEX +# if there is no active message already. SINDEX is returned intact. +# +mk_mesg: + mvi SEQCTL,0x50 # PAUSEDIS|FASTMODE + test FLAGS,ACTIVE_MSG jnz mk_mesg1 # active message? + + or FLAGS,ACTIVE_MSG # if not, there is now + mvi MSG_LEN,1 # length = 1 + mov MSG_START+0,SINDEX # 1-byte message + +mk_mesg1: + mvi SEQCTL,0x10 ret # !PAUSEDIS|FASTMODE + +# Carefully read data in Automatic PIO mode. I first tried this using +# Manual PIO mode, but it gave me continual underrun errors, probably +# indicating that I did something wrong, but I feel more secure leaving +# Automatic PIO on all the time. +# +# According to Adaptec's documentation, an ACK is not sent on input from +# the target until SCSIDATL is read from. So we wait until SCSIDATL is +# latched (the usual way), then read the data byte directly off the bus +# using SCSIBUSL. When we have pulled the ATN line, or we just want to +# acknowledge the byte, then we do a dummy read from SCISDATL. The SCSI +# spec guarantees that the target will hold the data byte on the bus until +# we send our ACK. +# +# The assumption here is that these are called in a particular sequence, +# and that REQ is already set when inb_first is called. inb_{first,next} +# use the same calling convention as inb. +# +inb_first: + clr STCNT+2 + clr STCNT+1 + mov DINDEX,SINDEX + mov DINDIR,SCSIBUSL ret # read byte directly from bus + +inb_next: + mov DINDEX,SINDEX # save SINDEX + + mvi STCNT+0,1 # xfer one byte + mov NONE,SCSIDATL # dummy read from latch to ACK +inb_next1: + test SSTAT0,0x4 jz inb_next1 # SDONE +inb_next2: + test SSTAT0,0x2 jz inb_next2 # SPIORDY - wait for next byte + mov DINDIR,SCSIBUSL ret # read byte directly from bus + +inb_last: + mvi STCNT+0,1 # ACK with dummy read + mov NONE,SCSIDATL +inb_last1: + test SSTAT0,0x4 jz inb_last1 # wait for completion + ret + +# DMA data transfer. HADDR and HCNT must be loaded first, and +# SINDEX should contain the value to load DFCNTRL with - 0x3d for +# host->scsi, or 0x39 for scsi->host. The SCSI channel is cleared +# during initialization. +# +dma: + mov DFCNTRL,SINDEX +dma1: +dma2: + test SSTAT0,0x1 jnz dma3 # DMADONE + test SSTAT1,0x10 jz dma1 # PHASEMIS, ie. underrun + +# We will be "done" DMAing when the transfer count goes to zero, or +# the target changes the phase (in light of this, it makes sense that +# the DMA circuitry doesn't ACK when PHASEMIS is active). If we are +# doing a SCSI->Host transfer, the data FIFO should be flushed auto- +# magically on STCNT=0 or a phase change, so just wait for FIFO empty +# status. +# +dma3: + test SINDEX,0x4 jnz dma5 # DIRECTION +dma4: + test DFSTATUS,0x1 jz dma4 # !FIFOEMP + +# Now shut the DMA enables off, and copy STCNT (ie. the underrun +# amount, if any) to the SCB registers; SG_COUNT will get copied to +# the SCB's residual S/G count field after sg_advance is called. Make +# sure that the DMA enables are actually off first lest we get an ILLSADDR. +# +dma5: + clr DFCNTRL # disable DMA +dma6: + test DFCNTRL,0x38 jnz dma6 # SCSIENACK|SDMAENACK|HDMAENACK + + mvi DINDEX,SCBARRAY+15 + mvi STCNT call bcopy_3 + + ret + +dma_finish: + test DFSTATUS,0x8 jz dma_finish # HDONE + + clr DFCNTRL # disable DMA +dma_finish2: + test DFCNTRL,0x8 jnz dma_finish2 # HDMAENACK + ret + +# Common SCSI initialization for selection and reselection. Expects +# the target SCSI ID to be in the upper four bits of SINDEX, and A's +# contents are stomped on return. +# +initialize_scsiid: + and SINDEX,0xf0 # Get target ID + and A,0x0f,SCSIID + or SINDEX,A + mov SCSIID,SINDEX ret + +initialize_for_target: +# Turn on Automatic PIO mode now, before we expect to see a REQ +# from the target. It shouldn't hurt anything to leave it on. Set +# CLRCHN here before the target has entered a data transfer mode - +# with synchronous SCSI, if you do it later, you blow away some +# data in the SCSI FIFO that the target has already sent to you. +# + clr SIGSTATE + + mvi SXFRCTL0,0x8a # DFON|SPIOEN|CLRCHN + +# Initialize scatter-gather pointers by setting up the working copy +# in scratch RAM. +# + call sg_scb2ram + +# Initialize SCSIRATE with the appropriate value for this target. +# + call ndx_dtr + mov SCSIRATE,SINDIR ret + +# Assert that if we've been reselected, then we've seen an IDENTIFY +# message. +# +assert: + test FLAGS,RESELECTED jz return # reselected? + test FLAGS,IDENTIFY_SEEN jnz return # seen IDENTIFY? + + mvi INTSTAT,NO_IDENT ret # no - cause a kernel panic + +# Find out if disconnection is ok from the information the BIOS has left +# us. The tcl from SCBARRAY+1 should be in SINDEX; A will +# contain either 0x40 (disconnection ok) or 0x00 (disconnection not ok) +# on exit. +# +# To allow for wide or twin busses, we check the upper bit of the target ID +# and the channel ID and look at the appropriate disconnect register. +# +disconnect: + and FUNCTION1,0x70,SINDEX # strip off extra just in case + mov A,FUNCTION1 + test SINDEX, 0x88 jz disconnect_a + + test DISC_DSB_B,A jz disconnect1 # bit nonzero if DISabled + clr A ret + +disconnect_a: + test DISC_DSB_A,A jz disconnect1 # bit nonzero if DISabled + clr A ret + +disconnect1: + mvi A,0x40 ret + +# Locate the SCB matching the target ID/channel/lun in SAVED_TCL and switch +# the SCB to it. Have the kernel print a warning message if it can't be +# found, and generate an ABORT message to the target. SINDEX should be +# cleared on call. +# +findSCB: + mov A,SAVED_TCL + mov SCBPTR,SINDEX # switch to new SCB + cmp SCBARRAY+1,A jne findSCB1 # target ID/channel/lun match? + test SCBARRAY+0,0x4 jz findSCB1 # should be disconnected + test SCBARRAY+0,TAG_ENB jnz get_tag + ret + +findSCB1: + inc SINDEX + mov A,SCBCOUNT + cmp SINDEX,A jne findSCB + + mvi INTSTAT,NO_MATCH # not found - signal kernel + mvi 0x6 call mk_mesg # ABORT message + + or SINDEX,0x10,SIGSTATE # assert ATNO + call scsisig + ret + +# Make a working copy of the scatter-gather parameters in the SCB. +# +sg_scb2ram: + mov SG_COUNT,SCBARRAY+2 + + mvi DINDEX,SG_NEXT + mvi SCBARRAY+3 call bcopy_4 + + mvi SG_NOLOAD,0x80 + test SCBARRAY+0,0x10 jnz return # don't reload s/g? + clr SG_NOLOAD ret + +# Copying RAM values back to SCB, for Save Data Pointers message. +# +sg_ram2scb: + mov SCBARRAY+2,SG_COUNT + + mvi DINDEX,SCBARRAY+3 + mvi SG_NEXT call bcopy_4 + + and SCBARRAY+0,0xef,SCBARRAY+0 + test SG_NOLOAD,0x80 jz return # reload s/g? + or SCBARRAY+0,SG_LOAD ret + +# Load a struct scatter if needed and set up the data address and +# length. If the working value of the SG count is nonzero, then +# we need to load a new set of values. +# +# This, like the above DMA, assumes a little-endian host data storage. +# +sg_load: + test SG_COUNT,0xff jz return # SG being used? + test SG_NOLOAD,0x80 jnz return # don't reload s/g? + + clr HCNT+2 + clr HCNT+1 + mvi HCNT+0,SG_SIZEOF + + mvi DINDEX,HADDR + mvi SG_NEXT call bcopy_4 + + mvi DFCNTRL,0xd # HDMAEN|DIRECTION|FIFORESET + +# Wait for DMA from host memory to data FIFO to complete, then disable +# DMA and wait for it to acknowledge that it's off. +# + + call dma_finish + +# Copy data from FIFO into SCB data pointer and data count. This assumes +# that the struct scatterlist has this structure (this and sizeof(struct +# scatterlist) == 12 are asserted in aic7xxx.c): +# +# struct scatterlist { +# char *address; /* four bytes, little-endian order */ +# ... /* four bytes, ignored */ +# unsigned short length; /* two bytes, little-endian order */ +# } +# + +# Not in FreeBSD. the scatter list entry is only 8 bytes. +# +# struct ahc_dma_seg { +# physaddr addr; /* four bytes, little-endian order */ +# long len; /* four bytes, little endian order */ +# }; +# + + mvi DINDEX, SCBARRAY+19 + call bcopy_4_dfdat + +# For Linux, we must throw away four bytes since there is a 32bit gap +# in the middle of a struct scatterlist +# mov NONE,DFDAT +# mov NONE,DFDAT +# mov NONE,DFDAT +# mov NONE,DFDAT + + call bcopy_3_dfdat #Only support 24 bit length. + ret + +# Advance the scatter-gather pointers only IF NEEDED. If SG is enabled, +# and the SCSI transfer count is zero (note that this should be called +# right after a DMA finishes), then move the working copies of the SG +# pointer/length along. If the SCSI transfer count is not zero, then +# presumably the target is disconnecting - do not reload the SG values +# next time. +# +sg_advance: + test SG_COUNT,0xff jz return # s/g enabled? + + test STCNT+0,0xff jnz sg_advance1 # SCSI transfer count nonzero? + test STCNT+1,0xff jnz sg_advance1 + test STCNT+2,0xff jnz sg_advance1 + + clr SG_NOLOAD # reload s/g next time + dec SG_COUNT # one less segment to go + + clr A # add sizeof(struct scatter) + add SG_NEXT+0,SG_SIZEOF,SG_NEXT+0 + adc SG_NEXT+1,A,SG_NEXT+1 + adc SG_NEXT+2,A,SG_NEXT+2 + adc SG_NEXT+3,A,SG_NEXT+3 ret + +sg_advance1: + mvi SG_NOLOAD,0x80 ret # don't reload s/g next time + +# Add the array base SYNCNEG to the target offset (the target address +# is in SCSIID), and return the result in SINDEX. The accumulator +# contains the 3->8 decoding of the target ID on return. +# +ndx_dtr: + shr A,SCSIID,4 + test SBLKCTL,0x08 jz ndx_dtr_2 + or A,0x08 # Channel B entries add 8 +ndx_dtr_2: + add SINDEX,SYNCNEG,A + + and FUNCTION1,0x70,SCSIID # 3-bit target address decode + mov A,FUNCTION1 ret + +# If we need to negotiate transfer parameters, build the WDTR or SDTR message +# starting at the address passed in SINDEX. DINDEX is modified on return. +# The SCSI-II spec requires that Wide negotiation occur first and you can +# only negotiat one or the other at a time otherwise in the event of a message +# reject, you wouldn't be able to tell which message was the culpret. +# +mk_dtr: + test SCBARRAY+0,0xc0 jz return # NEEDWDTR|NEEDSDTR + test SCBARRAY+0,NEEDWDTR jnz mk_wdtr_16bit + or FLAGS, MAX_SYNC # Force an offset of 15 + +mk_sdtr: + mvi DINDIR,1 # extended message + mvi DINDIR,3 # extended message length = 3 + mvi DINDIR,1 # SDTR code + call sdtr_to_rate + mov DINDIR,RETURN_1 # REQ/ACK transfer period + test FLAGS, MAX_SYNC jnz mk_sdtr_max_sync + and DINDIR,0xf,SINDIR # Sync Offset + +mk_sdtr_done: + add MSG_LEN,-MSG_START+0,DINDEX ret # update message length + +mk_sdtr_max_sync: +# We're initiating sync negotiation, so request the max offset we can (15) + mvi DINDIR, 0x0f + xor FLAGS, MAX_SYNC + jmp mk_sdtr_done + +mk_wdtr_16bit: + mvi ARG_1,BUS_16_BIT +mk_wdtr: + mvi DINDIR,1 # extended message + mvi DINDIR,2 # extended message length = 2 + mvi DINDIR,3 # WDTR code + mov DINDIR,ARG_1 # bus width + + add MSG_LEN,-MSG_START+0,DINDEX ret # update message length + +# Set SCSI bus control signal state. This also saves the last-written +# value into a location where the higher-level driver can read it - if +# it has to send an ABORT or RESET message, then it needs to know this +# so it can assert ATN without upsetting SCSISIGO. The new value is +# expected in SINDEX. Change the actual state last to avoid contention +# from the driver. +# +scsisig: + mov SIGSTATE,SINDEX + mov SCSISIGO,SINDEX ret + +sdtr_to_rate: + call ndx_dtr # index scratch space for target + shr A,SINDIR,0x4 + dec SINDEX #Preserve SINDEX + and A,0x7 + clr RETURN_1 +sdtr_to_rate_loop: + test A,0x0f jz sdtr_to_rate_done + add RETURN_1,0x18 + dec A + jmp sdtr_to_rate_loop +sdtr_to_rate_done: + shr RETURN_1,0x2 + add RETURN_1,0x18 ret + +return: + ret diff --git a/sys/dev/microcode/aic7xxx/aic7xxx_asm.1 b/sys/dev/microcode/aic7xxx/aic7xxx_asm.1 new file mode 100644 index 00000000000..2ff33b78190 --- /dev/null +++ b/sys/dev/microcode/aic7xxx/aic7xxx_asm.1 @@ -0,0 +1,70 @@ +.\" Copyright (c) 1994, 1995 +.\" Justin T. Gibbs. All rights reserved. +.\" +.\" Redistribution and use in source and binary forms, with or without +.\" modification, are permitted provided that the following conditions +.\" are met: +.\" 1. Redistributions of source code must retain the above copyright +.\" notice, this list of conditions and the following disclaimer. +.\" 2. Redistributions in binary form must reproduce the above copyright +.\" notice, this list of conditions and the following disclaimer in the +.\" documentation and/or other materials provided with the distribution. +.\" 3. The name of the author may not be used to endorse or promote products +.\" derived from this software without specific prior written permission. +.\" +.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR +.\" IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +.\" OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +.\" IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, +.\" INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +.\" NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +.\" DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +.\" THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +.\" (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +.\" THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +.\" +.\" +.Dd November 11, 1994 +.Dt AIC7XXX_ASM 1 +.Os BSD 4 +.Sh NAME +.Nm aic7xxx_asm +.Nd Assembler for the Adaptec aic7xxx family of asics +.Sh SYNOPSIS +.Nm aic7xxx_asm +.Op Fl d +.Op Fl D Ar variable=value +.Op Fl v +.Op Fl o Ar file +.Ar source-file +.Sh DESCRIPTION +The Adaptec aic7xxx family of asics are single chip SCSI controllers with a +RISC like command processor. This assembler parses the language outlined +in the Adaptec technical document +.%T "AIC-7770 (EISA/ISA Bus Master Single-Chip SCSI Host Adaptor) Data Book" +and produces ascii output intended for a C byte array. +.Pp +The aic7xxx assembler is required to compile kernels with aic7xxx SCSI +adaptor support (AHA-274x, AHA-284x, AHA-294x controllers) and is compiled, +installed, and used automatically in the kernel compile directory when +necessary. +.Pp +The options are as follows: +.Bl -tag -width Ds +.It Fl D Ar variable=value +Define +.Ar variable +to be +.Ar value +in the global context +.It Fl d +Turn on debugging +.It Fl v +Print version information +.It Fl o Ar file +Redirect assembler output to +.Ar file +.Pp +.Sh AUTHOR +This aic7770 assembler was written by +John Aycock (aycock@cpsc.ucalgary.ca) diff --git a/sys/dev/microcode/aic7xxx/aic7xxx_asm.c b/sys/dev/microcode/aic7xxx/aic7xxx_asm.c new file mode 100644 index 00000000000..414f9ab0205 --- /dev/null +++ b/sys/dev/microcode/aic7xxx/aic7xxx_asm.c @@ -0,0 +1,651 @@ +/*+M************************************************************************* + * Adaptec AIC7770/AIC7870 sequencer code assembler. + * + * Copyright (c) 1994 John Aycock + * The University of Calgary Department of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions, and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of Calgary + * Department of Computer Science and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * Comments are started by `#' and continue to the end of the line; lines + * may be of the form: + * <label>* + * <label>* <undef-sym> = <value> + * <label>* <opcode> <operand>* + * + * A <label> is an <undef-sym> ending in a colon. Spaces, tabs, and commas + * are token separators. + * + *-M*************************************************************************/ +static char id[] = "$Id: aic7xxx_asm.c,v 1.1 1995/10/09 09:49:39 mycroft Exp $"; +#include <ctype.h> +#include <stdio.h> +#include <string.h> +#include <stdlib.h> +#include <unistd.h> + +#define MEMORY 448 +#define MAXLINE 1024 +#define MAXTOKEN 32 +#define ADOTOUT "a.out" +#define NOVALUE -1 + +/* + * AIC-7770/AIC-7870 register definitions + */ +#define R_SINDEX 0x65 +#define R_ALLONES 0x69 +#define R_ALLZEROS 0x6a +#define R_NONE 0x6a + +int debug; +int lineno, LC; +char *filename; +FILE *ifp, *ofp; +unsigned char M[MEMORY][4]; + +void +error(char *s) +{ + fprintf(stderr, "%s: %s at line %d\n", filename, s, lineno); + exit(EXIT_FAILURE); +} + +void * +Malloc(size_t size) +{ + void *p = malloc(size); + if (!p) + error("out of memory"); + return(p); +} + +void * +Realloc(void *ptr, size_t size) +{ + void *p = realloc(ptr, size); + if (!p) + error("out of memory"); + return(p); +} + +char * +Strdup(char *s) +{ + char *p = (char *)Malloc(strlen(s) + 1); + strcpy(p, s); + return(p); +} + +typedef struct sym_t { + struct sym_t *next; /* MUST BE FIRST */ + char *name; + int value; + int npatch; + int *patch; +} sym_t; + +sym_t *head; + +void +define(char *name, int value) +{ + sym_t *p, *q; + + for (p = head, q = (sym_t *)&head; p; p = p->next) { + if (!strcmp(p->name, name)) + error("redefined symbol"); + q = p; + } + + p = q->next = (sym_t *)Malloc(sizeof(sym_t)); + p->next = NULL; + p->name = Strdup(name); + p->value = value; + p->npatch = 0; + p->patch = NULL; + + if (debug) { + fprintf(stderr, "\"%s\" ", p->name); + if (p->value != NOVALUE) + fprintf(stderr, "defined as 0x%x\n", p->value); + else + fprintf(stderr, "undefined\n"); + } +} + +sym_t * +lookup(char *name) +{ + sym_t *p; + + for (p = head; p; p = p->next) + if (!strcmp(p->name, name)) + return(p); + return(NULL); +} + +void +patch(sym_t *p, int location) +{ + p->npatch += 1; + p->patch = (int *)Realloc(p->patch, p->npatch * sizeof(int *)); + + p->patch[p->npatch - 1] = location; +} + +void backpatch(void) +{ + int i; + sym_t *p; + + for (p = head; p; p = p->next) { + + if (p->value == NOVALUE) { + fprintf(stderr, + "%s: undefined symbol \"%s\"\n", + filename, p->name); + exit(EXIT_FAILURE); + } + + if (p->npatch) { + if (debug) + fprintf(stderr, + "\"%s\" (0x%x) patched at", + p->name, p->value); + + for (i = 0; i < p->npatch; i++) { + M[p->patch[i]][0] &= ~1; + M[p->patch[i]][0] |= ((p->value >> 8) & 1); + M[p->patch[i]][1] = p->value & 0xff; + + if (debug) + fprintf(stderr, " 0x%x", p->patch[i]); + } + + if (debug) + fputc('\n', stderr); + } + } +} + +/* + * Output words in byte-reversed order (least significant first) + * since the sequencer RAM is loaded that way. + */ +void +output(FILE *fp) +{ + int i; + + for (i = 0; i < LC; i++) + fprintf(fp, "\t0x%02x, 0x%02x, 0x%02x, 0x%02x,\n", + M[i][3], + M[i][2], + M[i][1], + M[i][0]); + printf("%d out of %d instructions used.\n", LC, MEMORY); +} + +char ** +getl(int *n) +{ + int i; + char *p, *quote; + static char buf[MAXLINE]; + static char *a[MAXTOKEN]; + + i = 0; + + while (fgets(buf, sizeof(buf), ifp)) { + + lineno += 1; + + if (buf[strlen(buf)-1] != '\n') + error("line too long"); + + p = strchr(buf, '#'); + if (p) + *p = '\0'; + p = buf; +rescan: + quote = strchr(p, '\"'); + if (quote) + *quote = '\0'; + for (p = strtok(p, ", \t\n"); p; p = strtok(NULL, ", \t\n")) + if (i < MAXTOKEN-1) + a[i++] = p; + else + error("too many tokens"); + if (quote) { + quote++; + p = strchr(quote, '\"'); + if (!p) + error("unterminated string constant"); + else if (i < MAXTOKEN-1) { + a[i++] = quote; + *p = '\0'; + p++; + } + else + error("too many tokens"); + goto rescan; + } + if (i) { + *n = i; + return(a); + } + } + return(NULL); +} + +#define A 0x8000 /* `A'ccumulator ok */ +#define I 0x4000 /* use as immediate value */ +#define SL 0x2000 /* shift left */ +#define SR 0x1000 /* shift right */ +#define RL 0x0800 /* rotate left */ +#define RR 0x0400 /* rotate right */ +#define LO 0x8000 /* lookup: ori-{jmp,jc,jnc,call} */ +#define LA 0x4000 /* lookup: and-{jz,jnz} */ +#define LX 0x2000 /* lookup: xor-{je,jne} */ +#define NA -1 /* not applicable */ + +struct { + char *name; + int n; /* number of operands, including opcode */ + unsigned int op; /* immediate or L?|pos_from_0 */ + unsigned int dest; /* NA, pos_from_0, or I|immediate */ + unsigned int src; /* NA, pos_from_0, or I|immediate */ + unsigned int imm; /* pos_from_0, A|pos_from_0, or I|immediate */ + unsigned int addr; /* NA or pos_from_0 */ + int fmt; /* instruction format - 1, 2, or 3 */ +} instr[] = { +/* + * N OP DEST SRC IMM ADDR FMT + */ + { "mov", 3, 1, 1, 2, I|0xff, NA, 1 }, + { "mov", 4, LO|2, NA, 1, I|0, 3, 3 }, + { "mvi", 3, 0, 1, I|R_ALLZEROS, A|2, NA, 1 }, + { "mvi", 4, LO|2, NA, I|R_ALLZEROS, 1, 3, 3 }, + { "not", 2, 2, 1, 1, I|0xff, NA, 1 }, + { "and", 3, 1, 1, 1, A|2, NA, 1 }, + { "and", 4, 1, 1, 3, A|2, NA, 1 }, + { "or", 3, 0, 1, 1, A|2, NA, 1 }, + { "or", 4, 0, 1, 3, A|2, NA, 1 }, + { "or", 5, LO|3, NA, 1, 2, 4, 3 }, + { "xor", 3, 2, 1, 1, A|2, NA, 1 }, + { "xor", 4, 2, 1, 3, A|2, NA, 1 }, + { "nop", 1, 1, I|R_NONE, I|R_ALLZEROS, I|0xff, NA, 1 }, + { "inc", 2, 3, 1, 1, I|1, NA, 1 }, + { "inc", 3, 3, 1, 2, I|1, NA, 1 }, + { "dec", 2, 3, 1, 1, I|0xff, NA, 1 }, + { "dec", 3, 3, 1, 2, I|0xff, NA, 1 }, + { "jmp", 2, LO|0, NA, I|R_SINDEX, I|0, 1, 3 }, + { "jc", 2, LO|0, NA, I|R_SINDEX, I|0, 1, 3 }, + { "jnc", 2, LO|0, NA, I|R_SINDEX, I|0, 1, 3 }, + { "call", 2, LO|0, NA, I|R_SINDEX, I|0, 1, 3 }, + { "test", 5, LA|3, NA, 1, A|2, 4, 3 }, + { "cmp", 5, LX|3, NA, 1, A|2, 4, 3 }, + { "ret", 1, 1, I|R_NONE, I|R_ALLZEROS, I|0xff, NA, 1 }, + { "ret", 1, 1, I|R_NONE, I|R_ALLZEROS, I|0xff, NA, 1 }, + { "clc", 1, 3, I|R_NONE, I|R_ALLZEROS, I|1, NA, 1 }, + { "clc", 4, 3, 2, I|R_ALLZEROS, A|3, NA, 1 }, + { "stc", 2, 3, 1, I|R_ALLONES, I|1, NA, 1 }, + { "add", 3, 3, 1, 1, A|2, NA, 1 }, + { "add", 4, 3, 1, 3, A|2, NA, 1 }, + { "adc", 3, 4, 1, 1, A|2, NA, 1 }, + { "adc", 4, 4, 1, 3, A|2, NA, 1 }, + { "shl", 3, 5, 1, 1, SL|2, NA, 2 }, + { "shl", 4, 5, 1, 2, SL|3, NA, 2 }, + { "shr", 3, 5, 1, 1, SR|2, NA, 2 }, + { "shr", 4, 5, 1, 2, SR|3, NA, 2 }, + { "rol", 3, 5, 1, 1, RL|2, NA, 2 }, + { "rol", 4, 5, 1, 2, RL|3, NA, 2 }, + { "ror", 3, 5, 1, 1, RR|2, NA, 2 }, + { "ror", 4, 5, 1, 2, RR|3, NA, 2 }, + /* + * Extensions (note also that mvi allows A) + */ + { "clr", 2, 1, 1, I|R_ALLZEROS, I|0xff, NA, 1 }, + { 0, 0, 0, 0, 0, 0, 0, 0 } +}; + +int +eval_operand(char **a, int spec) +{ + int i; + unsigned int want = spec & (LO|LA|LX); + + static struct { + unsigned int what; + char *name; + int value; + } jmptab[] = { + { LO, "jmp", 8 }, + { LO, "jc", 9 }, + { LO, "jnc", 10 }, + { LO, "call", 11 }, + { LA, "jz", 15 }, + { LA, "jnz", 13 }, + { LX, "je", 14 }, + { LX, "jne", 12 }, + }; + + spec &= ~(LO|LA|LX); + + for (i = 0; i < sizeof(jmptab)/sizeof(jmptab[0]); i++) + if (jmptab[i].what == want && + !strcmp(jmptab[i].name, a[spec])) + { + return(jmptab[i].value); + } + + if (want) + error("invalid jump"); + + return(spec); /* "case 0" - no flags set */ +} + +int +eval_sdi(char **a, int spec) +{ + sym_t *p; + unsigned val; + + if (spec == NA) + return(NA); + + switch (spec & (A|I|SL|SR|RL|RR)) { + case SL: + case SR: + case RL: + case RR: + if (isdigit(*a[spec &~ (SL|SR|RL|RR)])) + val = strtol(a[spec &~ (SL|SR|RL|RR)], NULL, 0); + else { + p = lookup(a[spec &~ (SL|SR|RL|RR)]); + if (!p) + error("undefined symbol used"); + val = p->value; + } + + switch (spec & (SL|SR|RL|RR)) { /* blech */ + case SL: + if (val > 7) + return(0xf0); + return(((val % 8) << 4) | + (val % 8)); + case SR: + if (val > 7) + return(0xf0); + return(((val % 8) << 4) | + (1 << 3) | + ((8 - (val % 8)) % 8)); + case RL: + return(val % 8); + case RR: + return((8 - (val % 8)) % 8); + } + case I: + return(spec &~ I); + case A: + /* + * An immediate field of zero selects + * the accumulator. Vigorously object + * if zero is given otherwise - it's + * most likely an error. + */ + spec &= ~A; + if (!strcmp("A", a[spec])) + return(0); + if (isdigit(*a[spec]) && + strtol(a[spec], NULL, 0) == 0) + { + error("immediate value of zero selects accumulator"); + } + /* falls through */ + case 0: + if (isdigit(*a[spec])) + return(strtol(a[spec], NULL, 0)); + p = lookup(a[spec]); + if (p) + return(p->value); + error("undefined symbol used"); + } + + return(NA); /* shut the compiler up */ +} + +int +eval_addr(char **a, int spec) +{ + sym_t *p; + + if (spec == NA) + return(NA); + if (isdigit(*a[spec])) + return(strtol(a[spec], NULL, 0)); + + p = lookup(a[spec]); + + if (p) { + if (p->value != NOVALUE) + return(p->value); + patch(p, LC); + } else { + define(a[spec], NOVALUE); + p = lookup(a[spec]); + patch(p, LC); + } + + return(NA); /* will be patched in later */ +} + +int +crack(char **a, int n) +{ + int i; + int I_imm, I_addr; + int I_op, I_dest, I_src, I_ret; + + /* + * Check for "ret" at the end of the line; remove + * it unless it's "ret" alone - we still want to + * look it up in the table. + */ + I_ret = (strcmp(a[n-1], "ret") ? 0 : !0); + if (I_ret && n > 1) + n -= 1; + + for (i = 0; instr[i].name; i++) { + /* + * Look for match in table given constraints, + * currently just the name and the number of + * operands. + */ + if (!strcmp(instr[i].name, *a) && instr[i].n == n) + break; + } + if (!instr[i].name) + error("unknown opcode or wrong number of operands"); + + I_op = eval_operand(a, instr[i].op); + I_src = eval_sdi(a, instr[i].src); + I_imm = eval_sdi(a, instr[i].imm); + I_dest = eval_sdi(a, instr[i].dest); + I_addr = eval_addr(a, instr[i].addr); + + if( LC >= MEMORY ) + error("Memory exhausted!\n"); + + switch (instr[i].fmt) { + case 1: + case 2: + M[LC][0] = (I_op << 1) | I_ret; + M[LC][1] = I_dest; + M[LC][2] = I_src; + M[LC][3] = I_imm; + break; + case 3: + if (I_ret) + error("illegal use of \"ret\""); + M[LC][0] = (I_op << 1) | ((I_addr >> 8) & 1); + M[LC][1] = I_addr & 0xff; + M[LC][2] = I_src; + M[LC][3] = I_imm; + break; + } + + return (1); /* no two-byte instructions yet */ +} + +#undef SL +#undef SR +#undef RL +#undef RR +#undef LX +#undef LA +#undef LO +#undef I +#undef A + +void +assemble(void) +{ + int n; + char **a; + sym_t *p; + + while ((a = getl(&n))) { + + while (a[0][strlen(*a)-1] == ':') { + a[0][strlen(*a)-1] = '\0'; + p = lookup(*a); + if (p) + p->value = LC; + else + define(*a, LC); + a += 1; + n -= 1; + } + + if (!n) /* line was all labels */ + continue; + + if (n == 3 && !strcmp("VERSION", *a)) + fprintf(ofp, "#define %s \"%s\"\n", a[1], a[2]); + else { + if (n == 3 && !strcmp("=", a[1])) + define(*a, strtol(a[2], NULL, 0)); + else + LC += crack(a, n); + } + } + + backpatch(); + output(ofp); + + if (debug) + output(stderr); +} + +int +main(int argc, char **argv) +{ int my_version_print_flag; + int c; + + my_version_print_flag=0; + + while ((c = getopt(argc, argv, "dho:vD")) != EOF) { + switch (c) { + case 'd': + debug = !0; + break; + case 'D': + { + char *p; + if ((p = strchr(optarg, '=')) != NULL) { + *p = '\0'; + define(optarg, strtol(p + 1, NULL, 0)); + } + else + define(optarg, 1); + break; + } + case 'o': + ofp = fopen(optarg, "w"); + if (!ofp) { + perror(optarg); + exit(EXIT_FAILURE); + } + break; + case 'h': + printf("usage: %s [-d] [-Dname] [-ooutput] input\n", + *argv); + exit(EXIT_SUCCESS); + break; + case 'v': + if (!my_version_print_flag) + { printf("%s\n",id); + + my_version_print_flag=1; + } + break; + default: + exit(EXIT_FAILURE); + break; + } + } + + if (argc - optind != 1) { + if (my_version_print_flag) + { exit(EXIT_SUCCESS); + } + fprintf(stderr, "%s: must have one input file\n", *argv); + exit(EXIT_FAILURE); + } + filename = argv[optind]; + + ifp = fopen(filename, "r"); + if (!ifp) { + perror(filename); + exit(EXIT_FAILURE); + } + + if (!ofp) { + ofp = fopen(ADOTOUT, "w"); + if (!ofp) { + perror(ADOTOUT); + exit(EXIT_FAILURE); + } + } + + assemble(); + exit(EXIT_SUCCESS); +} diff --git a/sys/dev/pci/aic7870.c b/sys/dev/pci/aic7870.c new file mode 100644 index 00000000000..21e02a8b4f1 --- /dev/null +++ b/sys/dev/pci/aic7870.c @@ -0,0 +1,101 @@ +/* + * Product specific probe and attach routines for: + * 294X and aic7870 motherboard SCSI controllers + * + * Copyright (c) 1995 Justin T. Gibbs + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice immediately at the beginning of the file, without modification, + * this list of conditions, and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Absolutely no warranty of function or purpose is made by the author + * Justin T. Gibbs. + * 4. Modifications may be freely made to this file if the above conditions + * are met. + * + * $Id: aic7870.c,v 1.1 1995/10/09 09:49:33 mycroft Exp $ + */ + +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/malloc.h> +#include <sys/kernel.h> +#include <sys/device.h> + +#include <scsi/scsi_all.h> +#include <scsi/scsiconf.h> + +#include <dev/pci/pcireg.h> +#include <dev/pci/pcivar.h> +#include <dev/ic/aic7xxxvar.h> + + +#define PCI_BASEADR0 PCI_MAP_REG_START +#define PCI_DEVICE_ID_ADAPTEC_2940 0x71789004ul +#define PCI_DEVICE_ID_ADAPTEC_AIC7870 0x70789004ul + + +static int aic7870_probe(); +static void aic7870_attach(); + +struct cfdriver ahccd = { + NULL, "ahc", aic7870_probe, aic7870_attach, DV_DULL, + sizeof(struct ahc_softc) +}; + +int ahcintr __P((void *)); + + +int +aic7870_probe(parent, match, aux) + struct device *parent; + void *match, *aux; +{ + struct pci_attach_args *pa = aux; + + if (pa->pa_id != PCI_DEVICE_ID_ADAPTEC_2940 && + pa->pa_id != PCI_DEVICE_ID_ADAPTEC_AIC7870) + return (0); + + return (1); +} + +void +aic7870_attach(parent, self, aux) + struct device *parent, *self; + void *aux; +{ + struct pci_attach_args *pa = aux; + struct ahc_softc *ahc = (void *)self; + int iobase; + + switch (pa->pa_id) { + case PCI_DEVICE_ID_ADAPTEC_2940: + ahc->type = AHC_294; + break; + case PCI_DEVICE_ID_ADAPTEC_AIC7870: + ahc->type = AHC_AIC7870; + break; + } + + if (pci_map_io(pa->pa_tag, PCI_BASEADR0, &iobase)) + return; + + /* + * Make the offsets the same as for EISA + */ + iobase -= 0xc00ul; + + if (ahcprobe(ahc, iobase) == 0) + return; + + ahcattach(ahc); + + ahc->sc_ih = pci_map_int(pa->pa_tag, PCI_IPL_BIO, ahcintr, ahc); +} |
