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authorbjh21 <bjh21@NetBSD.org>2006-08-27 22:32:54 +0000
committerbjh21 <bjh21@NetBSD.org>2006-08-27 22:32:54 +0000
commitb42a1dca38d2c56078510abbcc3fbf1023ec9182 (patch)
tree7b9d33566783a8b6cae9d5fd11780da848314386 /sys/dev
parent2c9106f6fe6f129cd6bfdeaf86974fc4f0b31d25 (diff)
Revert revision 1.4: it seems to have caused serious problems on sgimips,
so I should probably leave it until I get my Indy going.
Diffstat (limited to 'sys/dev')
-rw-r--r--sys/dev/ic/wd33c93.c23
1 files changed, 5 insertions, 18 deletions
diff --git a/sys/dev/ic/wd33c93.c b/sys/dev/ic/wd33c93.c
index 943a5047929..41bd1bcc5d4 100644
--- a/sys/dev/ic/wd33c93.c
+++ b/sys/dev/ic/wd33c93.c
@@ -1,4 +1,4 @@
-/* $NetBSD: wd33c93.c,v 1.5 2006/08/27 13:13:36 bjh21 Exp $ */
+/* $NetBSD: wd33c93.c,v 1.6 2006/08/27 22:32:54 bjh21 Exp $ */
/*
* Copyright (c) 1990 The Regents of the University of California.
@@ -79,7 +79,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: wd33c93.c,v 1.5 2006/08/27 13:13:36 bjh21 Exp $");
+__KERNEL_RCSID(0, "$NetBSD: wd33c93.c,v 1.6 2006/08/27 22:32:54 bjh21 Exp $");
#include "opt_ddb.h"
@@ -1421,9 +1421,6 @@ wd33c93_msgin_phase(struct wd33c93_softc *dev, int reselect)
SBIC_WAIT(dev, SBIC_ASR_INT, 0);
GET_SBIC_csr(dev, csr);
- if (__verify_msg_format(dev->sc_imsg, len))
- break; /* Complete message recieved */
-
/*
* Clear ACK, and wait for the interrupt
* for the next byte or phase change
@@ -1431,25 +1428,15 @@ wd33c93_msgin_phase(struct wd33c93_softc *dev, int reselect)
SET_SBIC_cmd(dev, SBIC_CMD_CLR_ACK);
SBIC_WAIT(dev, SBIC_ASR_INT, 0);
+ if (__verify_msg_format(dev->sc_imsg, len))
+ break; /* Complete message recieved */
+
GET_SBIC_csr(dev, csr);
} while (len < SBIC_MAX_MSGLEN);
- /*
- * Handle the message before deasserting ACK, since if we need to
- * reply we have to assert ATN first.
- */
if (__verify_msg_format(dev->sc_imsg, len))
wd33c93_msgin(dev, dev->sc_imsg, len);
- /*
- * Clear ACK, and wait for the interrupt
- * for the phase change
- */
- SET_SBIC_cmd(dev, SBIC_CMD_CLR_ACK);
- SBIC_WAIT(dev, SBIC_ASR_INT, 0);
-
- GET_SBIC_csr(dev, csr);
-
/* Should still have one CSR to read */
return SBIC_STATE_RUNNING;
}