diff options
| author | mrg <mrg@NetBSD.org> | 2022-09-20 23:01:42 +0000 |
|---|---|---|
| committer | mrg <mrg@NetBSD.org> | 2022-09-20 23:01:42 +0000 |
| commit | d69eb2cc32ee990625006ab5b148abf0c7728ddd (patch) | |
| tree | 87725c246ed6fe5de75be262b6db5ab575dde3b0 /sys/dev | |
| parent | 56ea27f598d56ead6c66e7438186fe6bb62fcae6 (diff) | |
fill out more of the linux pci API compat
- implement pcie_get_speed_cap(), pcie_bandwidth_available(), and
pci_is_root_bus().
- expand "enum pci_bus_speed" to add PCIe 5.x and 6.x speeds.
- add "enum pcie_link_width".
- add defines for PCIE_LCSR_LINKSPEED (PCIe generation) and PCIE_LCSR_NLW
(negotiated lane width) to pcireg.h
- enable amdgpu_device_get_pcie_info() code now it works.
ok riastradh@
Diffstat (limited to 'sys/dev')
| -rw-r--r-- | sys/dev/pci/pcireg.h | 15 |
1 files changed, 14 insertions, 1 deletions
diff --git a/sys/dev/pci/pcireg.h b/sys/dev/pci/pcireg.h index 8f6557c8705..1c66f2febf4 100644 --- a/sys/dev/pci/pcireg.h +++ b/sys/dev/pci/pcireg.h @@ -1,4 +1,4 @@ -/* $NetBSD: pcireg.h,v 1.165 2022/01/31 10:14:55 msaitoh Exp $ */ +/* $NetBSD: pcireg.h,v 1.166 2022/09/20 23:01:42 mrg Exp $ */ /* * Copyright (c) 1995, 1996, 1999, 2000 @@ -1063,7 +1063,20 @@ typedef u_int8_t pci_revision_t; #define PCIE_LCSR_LABIE __BIT(11) /* Link Autonomous BW Intr En */ #define PCIE_LCSR_DRSSGNL __BITS(15, 14) /* DRS Signaling */ #define PCIE_LCSR_LINKSPEED __BITS(19, 16) /* Link Speed */ +#define PCIE_LCSR_LINKSPEED_2 1 /* 2.5GT/s */ +#define PCIE_LCSR_LINKSPEED_5 2 /* 5GT/s */ +#define PCIE_LCSR_LINKSPEED_8 3 /* 8GT/s */ +#define PCIE_LCSR_LINKSPEED_16 4 /* 16GT/s */ +#define PCIE_LCSR_LINKSPEED_32 5 /* 32GT/s */ +#define PCIE_LCSR_LINKSPEED_64 6 /* 64GT/s */ #define PCIE_LCSR_NLW __BITS(25, 20) /* Negotiated Link Width */ +#define PCIE_LCSR_NLW_X1 __BIT(20) /* Negotiated x1 */ +#define PCIE_LCSR_NLW_X2 __BIT(21) /* Negotiated x2 */ +#define PCIE_LCSR_NLW_X4 __BIT(22) /* Negotiated x4 */ +#define PCIE_LCSR_NLW_X8 __BIT(23) /* Negotiated x8 */ +#define PCIE_LCSR_NLW_X12 __BITS(22, 23) /* Negotiated x12 */ +#define PCIE_LCSR_NLW_X16 __BIT(24) /* Negotiated x16 */ +#define PCIE_LCSR_NLW_X32 __BIT(25) /* Negotiated x32 */ #define PCIE_LCSR_LINKTRAIN_ERR __BIT(10 + 16) /* Link Training Error */ #define PCIE_LCSR_LINKTRAIN __BIT(11 + 16) /* Link Training */ #define PCIE_LCSR_SLOTCLKCFG __BIT(12 + 16) /* Slot Clock Configuration */ |
