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authorgwr <gwr@NetBSD.org>1996-01-30 22:34:52 +0000
committergwr <gwr@NetBSD.org>1996-01-30 22:34:52 +0000
commitf2e57c6dc808c313abb0ca01faec5df913f6253f (patch)
tree4ea6e8b31549733f23bed935c3f4d05b93381812 /sys/dev
parent99686e00591f6e8010d12c01588d0ed8a0ec9701 (diff)
Eliminate remaining direct references to the z8530 chip
to allow the MD access functions to do delays, etc.
Diffstat (limited to 'sys/dev')
-rw-r--r--sys/dev/ic/z8530sc.c64
-rw-r--r--sys/dev/ic/z8530tty.c57
-rw-r--r--sys/dev/sun/kbd.c25
-rw-r--r--sys/dev/sun/ms.c22
4 files changed, 69 insertions, 99 deletions
diff --git a/sys/dev/ic/z8530sc.c b/sys/dev/ic/z8530sc.c
index 7b7ef11d4aa..b564817822e 100644
--- a/sys/dev/ic/z8530sc.c
+++ b/sys/dev/ic/z8530sc.c
@@ -1,4 +1,4 @@
-/* $NetBSD: z8530sc.c,v 1.1 1996/01/24 01:07:23 gwr Exp $ */
+/* $NetBSD: z8530sc.c,v 1.2 1996/01/30 22:35:09 gwr Exp $ */
/*
* Copyright (c) 1994 Gordon W. Ross
@@ -82,7 +82,7 @@ zs_break(cs, set)
cs->cs_preg[5] &= ~ZSWR5_BREAK;
cs->cs_creg[5] &= ~ZSWR5_BREAK;
}
- ZS_WRITE(cs, 5, cs->cs_creg[5]);
+ zs_write_reg(cs, 5, cs->cs_creg[5]);
splx(s);
}
@@ -96,8 +96,8 @@ zs_getspeed(cs)
{
int tconst;
- tconst = ZS_READ(cs, 12);
- tconst |= ZS_READ(cs, 13) << 8;
+ tconst = zs_read_reg(cs, 12);
+ tconst |= zs_read_reg(cs, 13) << 8;
return (TCONST_TO_BPS(cs->cs_pclk_div16, tconst));
}
@@ -112,21 +112,18 @@ zs_iflush(cs)
for (;;) {
/* Is there input available? */
- rr0 = *(cs->cs_reg_csr);
- ZS_DELAY();
+ rr0 = zs_read_csr(cs);
if ((rr0 & ZSRR0_RX_READY) == 0)
break;
/* Read the data. */
- c = *(cs->cs_reg_data);
- ZS_DELAY();
+ c = zs_read_data(cs);
/* Need to read status register too? */
- rr1 = ZS_READ(cs, 1);
+ rr1 = zs_read_reg(cs, 1);
if (rr1 & (ZSRR1_FE | ZSRR1_DO | ZSRR1_PE)) {
/* Clear the receive error. */
- *(cs->cs_reg_csr) = ZSWR0_RESET_ERRORS;
- ZS_DELAY();
+ zs_write_csr(cs, ZSWR0_RESET_ERRORS);
}
}
}
@@ -149,8 +146,7 @@ zs_loadchannelregs(cs)
bcopy((caddr_t)cs->cs_preg, (caddr_t)cs->cs_creg, 16);
reg = cs->cs_creg; /* current regs */
- *(cs->cs_reg_csr) = ZSM_RESET_ERR; /* XXX: reset error condition */
- ZS_DELAY();
+ zs_write_csr(cs, ZSM_RESET_ERR); /* XXX: reset error condition */
#if 1
/*
@@ -161,17 +157,17 @@ zs_loadchannelregs(cs)
#endif
/* baud clock divisor, stop bits, parity */
- ZS_WRITE(cs, 4, reg[4]);
+ zs_write_reg(cs, 4, reg[4]);
/* misc. TX/RX control bits */
- ZS_WRITE(cs, 10, reg[10]);
+ zs_write_reg(cs, 10, reg[10]);
/* char size, enable (RX/TX) */
- ZS_WRITE(cs, 3, reg[3] & ~ZSWR3_RX_ENABLE);
- ZS_WRITE(cs, 5, reg[5] & ~ZSWR5_TX_ENABLE);
+ zs_write_reg(cs, 3, reg[3] & ~ZSWR3_RX_ENABLE);
+ zs_write_reg(cs, 5, reg[5] & ~ZSWR5_TX_ENABLE);
/* interrupt enables: TX, TX, STATUS */
- ZS_WRITE(cs, 1, reg[1]);
+ zs_write_reg(cs, 1, reg[1]);
#if 0
/*
@@ -182,27 +178,27 @@ zs_loadchannelregs(cs)
* and they should not be touched thereafter.
*/
/* interrupt vector */
- ZS_WRITE(cs, 2, reg[2]);
+ zs_write_reg(cs, 2, reg[2]);
/* master interrupt control */
- ZS_WRITE(cs, 9, reg[9]);
+ zs_write_reg(cs, 9, reg[9]);
#endif
/* clock mode control */
- ZS_WRITE(cs, 11, reg[11]);
+ zs_write_reg(cs, 11, reg[11]);
/* baud rate (lo/hi) */
- ZS_WRITE(cs, 12, reg[12]);
- ZS_WRITE(cs, 13, reg[13]);
+ zs_write_reg(cs, 12, reg[12]);
+ zs_write_reg(cs, 13, reg[13]);
/* Misc. control bits */
- ZS_WRITE(cs, 14, reg[14]);
+ zs_write_reg(cs, 14, reg[14]);
/* which lines cause status interrupts */
- ZS_WRITE(cs, 15, reg[15]);
+ zs_write_reg(cs, 15, reg[15]);
/* char size, enable (RX/TX)*/
- ZS_WRITE(cs, 3, reg[3]);
- ZS_WRITE(cs, 5, reg[5]);
+ zs_write_reg(cs, 3, reg[3]);
+ zs_write_reg(cs, 5, reg[5]);
}
@@ -233,7 +229,7 @@ zsc_intr_hard(arg)
soft = 0;
/* Note: only channel A has an RR3 */
- rr3 = ZS_READ(cs_a, 3);
+ rr3 = zs_read_reg(cs_a, 3);
/* Handle receive interrupts first. */
if (rr3 & ZSRR3_IP_A_RX)
@@ -255,19 +251,17 @@ zsc_intr_hard(arg)
/* Clear interrupt. */
if (rr3 & (ZSRR3_IP_A_RX | ZSRR3_IP_A_TX | ZSRR3_IP_A_STAT)) {
- *(cs_a->cs_reg_csr) = ZSWR0_CLR_INTR;
- ZS_DELAY();
+ zs_write_csr(cs_a, ZSWR0_CLR_INTR);
rval |= 1;
}
if (rr3 & (ZSRR3_IP_B_RX | ZSRR3_IP_B_TX | ZSRR3_IP_B_STAT)) {
- *(cs_b->cs_reg_csr) = ZSWR0_CLR_INTR;
- ZS_DELAY();
+ zs_write_csr(cs_b, ZSWR0_CLR_INTR);
rval |= 2;
}
if ((cs_a->cs_softreq) || (cs_b->cs_softreq))
{
- /* This is a machine-dependent function. */
+ /* This is a machine-dependent function (or macro). */
zsc_req_softint(zsc);
}
@@ -308,8 +302,8 @@ static int
zsnull_intr(cs)
struct zs_chanstate *cs;
{
- ZS_WRITE(cs, 1, 0);
- ZS_WRITE(cs, 15, 0);
+ zs_write_reg(cs, 1, 0);
+ zs_write_reg(cs, 15, 0);
}
static int
diff --git a/sys/dev/ic/z8530tty.c b/sys/dev/ic/z8530tty.c
index 276ceb0cd1c..09644636fca 100644
--- a/sys/dev/ic/z8530tty.c
+++ b/sys/dev/ic/z8530tty.c
@@ -1,4 +1,4 @@
-/* $NetBSD: z8530tty.c,v 1.1 1996/01/24 01:07:25 gwr Exp $ */
+/* $NetBSD: z8530tty.c,v 1.2 1996/01/30 22:35:11 gwr Exp $ */
/*
* Copyright (c) 1994 Gordon W. Ross
@@ -244,7 +244,7 @@ zstty_attach(parent, self, aux)
reset = (channel == 0) ?
ZSWR9_A_RESET : ZSWR9_B_RESET;
s = splzs();
- ZS_WRITE(cs, 9, reset);
+ zs_write_reg(cs, 9, reset);
splx(s);
}
@@ -347,8 +347,7 @@ zsopen(dev, flags, mode, p)
register int rr0;
/* Might never get status intr if carrier already on. */
- rr0 = *(cs->cs_reg_csr);
- ZS_DELAY();
+ rr0 = zs_read_csr(cs);
if (rr0 & ZSRR0_DCD) {
tp->t_state |= TS_CARR_ON;
break;
@@ -574,9 +573,8 @@ zsstart(tp)
cs->cs_preg[1] |= ZSWR1_TIE;
cs->cs_creg[1] |= ZSWR1_TIE;
- ZS_WRITE(cs, 1, cs->cs_creg[1]);
- *(cs->cs_reg_data) = *p;
- ZS_DELAY();
+ zs_write_reg(cs, 1, cs->cs_creg[1]);
+ zs_write_data(cs, *p);
zst->zst_tba = p + 1;
zst->zst_tbc = nch - 1;
} else {
@@ -587,7 +585,7 @@ zsstart(tp)
(void) splzs();
cs->cs_preg[1] &= ~ZSWR1_TIE;
cs->cs_creg[1] &= ~ZSWR1_TIE;
- ZS_WRITE(cs, 1, cs->cs_creg[1]);
+ zs_write_reg(cs, 1, cs->cs_creg[1]);
}
out:
splx(s);
@@ -709,9 +707,8 @@ zsparam(tp, t)
*/
tmp3 |= ZSWR3_RX_ENABLE;
if (cflag & CCTS_OFLOW) {
- if (*(cs->cs_reg_csr) & ZSRR0_DCD)
+ if (zs_read_csr(cs) & ZSRR0_DCD)
tmp3 |= ZSWR3_HFC;
- ZS_DELAY();
}
cs->cs_preg[3] = tmp3;
@@ -773,7 +770,7 @@ zs_modem(zst, onoff)
cs->cs_heldchange = 1;
} else {
cs->cs_creg[5] = (cs->cs_creg[5] | bis) & and;
- ZS_WRITE(cs, 5, cs->cs_creg[5]);
+ zs_write_reg(cs, 5, cs->cs_creg[5]);
}
}
splx(s);
@@ -797,16 +794,14 @@ zstty_rxint(cs)
nextchar:
/* Read the input data ASAP. */
- c = *(cs->cs_reg_data);
- ZS_DELAY();
+ c = zs_read_data(cs);
/* Save the status register too. */
- rr1 = ZS_READ(cs, 1);
+ rr1 = zs_read_reg(cs, 1);
if (rr1 & (ZSRR1_FE | ZSRR1_DO | ZSRR1_PE)) {
/* Clear the receive error. */
- *(cs->cs_reg_csr) = ZSWR0_RESET_ERRORS;
- ZS_DELAY();
+ zs_write_csr(cs, ZSWR0_RESET_ERRORS);
}
zst->zst_rbuf[put] = (c << 8) | rr1;
@@ -821,8 +816,7 @@ nextchar:
}
/* Keep reading until the FIFO is empty. */
- rr0 = *(cs->cs_reg_csr);
- ZS_DELAY();
+ rr0 = zs_read_csr(cs);
if (rr0 & ZSRR0_RX_READY)
goto nextchar;
@@ -846,14 +840,13 @@ zstty_txint(cs)
if (count > 0) {
/* Send the next char. */
- *(cs->cs_reg_data) = *zst->zst_tba++;
- ZS_DELAY();
+ zs_write_data(cs, *zst->zst_tba);
+ zst->zst_tba++;
zst->zst_tbc = --count;
rval = 0;
} else {
/* Nothing more to send. */
- *(cs->cs_reg_csr) = ZSWR0_RESET_TXINT;
- ZS_DELAY();
+ zs_write_csr(cs, ZSWR0_RESET_TXINT);
zst->zst_intr_flags |= INTR_TX_EMPTY;
rval = 1; /* want softcall */
}
@@ -871,11 +864,8 @@ zstty_stint(cs)
zst = cs->cs_private;
- rr0 = *(cs->cs_reg_csr);
- ZS_DELAY();
-
- *(cs->cs_reg_csr) = ZSWR0_RESET_STATUS;
- ZS_DELAY();
+ rr0 = zs_read_csr(cs);
+ zs_write_csr(cs, ZSWR0_RESET_STATUS);
if ((rr0 & ZSRR0_BREAK) &&
(zst->zst_hwflags & ZS_HWFLAG_CONSOLE))
@@ -968,8 +958,7 @@ zstty_softint(cs)
*/
if (cs->cs_heldchange) {
s = splzs();
- rr0 = *(cs->cs_reg_csr);
- ZS_DELAY();
+ rr0 = zs_read_csr(cs);
if ((rr0 & ZSRR0_DCD) == 0)
cs->cs_preg[3] &= ~ZSWR3_HFC;
zs_loadchannelregs(cs);
@@ -980,8 +969,8 @@ zstty_softint(cs)
(tp->t_state & TS_TTSTOP) == 0)
{
zst->zst_tbc = zst->zst_heldtbc - 1;
- *(cs->cs_reg_data) = *zst->zst_tba++;
- ZS_DELAY();
+ zs_write_data(cs, *zst->zst_tba);
+ zst->zst_tba++;
goto tx_resumed;
}
}
@@ -1006,17 +995,17 @@ zstty_softint(cs)
* HFC now but carrier has gone low, turn it off.
*/
s = splzs();
- rr0 = *(cs->cs_reg_csr);
+ rr0 = zs_read_csr(cs);
if (rr0 & ZSRR0_DCD) {
if (tp->t_cflag & CCTS_OFLOW &&
(cs->cs_creg[3] & ZSWR3_HFC) == 0) {
cs->cs_creg[3] |= ZSWR3_HFC;
- ZS_WRITE(cs, 3, cs->cs_creg[3]);
+ zs_write_reg(cs, 3, cs->cs_creg[3]);
}
} else {
if (cs->cs_creg[3] & ZSWR3_HFC) {
cs->cs_creg[3] &= ~ZSWR3_HFC;
- ZS_WRITE(cs, 3, cs->cs_creg[3]);
+ zs_write_reg(cs, 3, cs->cs_creg[3]);
}
}
splx(s);
diff --git a/sys/dev/sun/kbd.c b/sys/dev/sun/kbd.c
index 999663a6668..b32ac07d320 100644
--- a/sys/dev/sun/kbd.c
+++ b/sys/dev/sun/kbd.c
@@ -1,4 +1,4 @@
-/* $NetBSD: kbd.c,v 1.1.1.1 1996/01/24 01:15:35 gwr Exp $ */
+/* $NetBSD: kbd.c,v 1.2 1996/01/30 22:35:16 gwr Exp $ */
/*
* Copyright (c) 1992, 1993
@@ -251,7 +251,7 @@ kbd_attach(parent, self, aux)
/* Not the console; may need reset. */
reset = (channel == 0) ?
ZSWR9_A_RESET : ZSWR9_B_RESET;
- ZS_WRITE(cs, 9, reset);
+ zs_write_reg(cs, 9, reset);
}
/* These are OK as set by zscc: WR3, WR4, WR5 */
cs->cs_preg[5] |= ZSWR5_DTR | ZSWR5_RTS;
@@ -875,16 +875,14 @@ kbd_rxint(cs)
put = k->k_rbput;
/* Read the input data ASAP. */
- c = *(cs->cs_reg_data);
- ZS_DELAY();
+ c = zs_read_data(cs);
/* Save the status register too. */
- rr1 = ZS_READ(cs, 1);
+ rr1 = zs_read_reg(cs, 1);
if (rr1 & (ZSRR1_FE | ZSRR1_DO | ZSRR1_PE)) {
/* Clear the receive error. */
- *(cs->cs_reg_csr) = ZSWR0_RESET_ERRORS;
- ZS_DELAY();
+ zs_write_csr(cs, ZSWR0_RESET_ERRORS);
}
/*
@@ -934,8 +932,7 @@ kbd_txint(cs)
k = cs->cs_private;
- *(cs->cs_reg_csr) = ZSWR0_RESET_TXINT;
- ZS_DELAY();
+ zs_write_csr(cs, ZSWR0_RESET_TXINT);
k->k_intr_flags |= INTR_TX_EMPTY;
/* Ask for softint() call. */
@@ -953,11 +950,8 @@ kbd_stint(cs)
k = cs->cs_private;
- rr0 = *(cs->cs_reg_csr);
- ZS_DELAY();
-
- *(cs->cs_reg_csr) = ZSWR0_RESET_STATUS;
- ZS_DELAY();
+ rr0 = zs_read_csr(cs);
+ zs_write_csr(cs, ZSWR0_RESET_STATUS);
#if 0
if (rr0 & ZSRR0_BREAK) {
@@ -1267,8 +1261,7 @@ kbd_start_tx(k)
/* Need splzs to avoid interruption of the delay. */
(void) splzs();
- *(cs->cs_reg_data) = c;
- ZS_DELAY();
+ zs_write_data(cs, c);
out:
splx(s);
diff --git a/sys/dev/sun/ms.c b/sys/dev/sun/ms.c
index 275481c76f7..c193db6a435 100644
--- a/sys/dev/sun/ms.c
+++ b/sys/dev/sun/ms.c
@@ -1,4 +1,4 @@
-/* $NetBSD: ms.c,v 1.1.1.1 1996/01/24 01:15:35 gwr Exp $ */
+/* $NetBSD: ms.c,v 1.2 1996/01/30 22:35:19 gwr Exp $ */
/*
* Copyright (c) 1992, 1993
@@ -196,7 +196,7 @@ ms_attach(parent, self, aux)
/* May need reset... */
reset = (channel == 0) ?
ZSWR9_A_RESET : ZSWR9_B_RESET;
- ZS_WRITE(cs, 9, reset);
+ zs_write_reg(cs, 9, reset);
/* These are OK as set by zscc: WR3, WR4, WR5 */
cs->cs_preg[5] |= ZSWR5_DTR | ZSWR5_RTS;
cs->cs_preg[12] = tconst;
@@ -487,16 +487,14 @@ ms_rxint(cs)
put = ms->ms_rbput;
/* Read the input data ASAP. */
- c = *(cs->cs_reg_data);
- ZS_DELAY();
+ c = zs_read_data(cs);
/* Save the status register too. */
- rr1 = ZS_READ(cs, 1);
+ rr1 = zs_read_reg(cs, 1);
if (rr1 & (ZSRR1_FE | ZSRR1_DO | ZSRR1_PE)) {
/* Clear the receive error. */
- *(cs->cs_reg_csr) = ZSWR0_RESET_ERRORS;
- ZS_DELAY();
+ zs_write_csr(cs, ZSWR0_RESET_ERRORS);
}
ms->ms_rbuf[put] = (c << 8) | rr1;
@@ -528,8 +526,7 @@ ms_txint(cs)
ms = cs->cs_private;
- *(cs->cs_reg_csr) = ZSWR0_RESET_TXINT;
- ZS_DELAY();
+ zs_write_csr(cs, ZSWR0_RESET_TXINT);
ms->ms_intr_flags |= INTR_TX_EMPTY;
/* Ask for softint() call. */
@@ -547,11 +544,8 @@ ms_stint(cs)
ms = cs->cs_private;
- rr0 = *(cs->cs_reg_csr);
- ZS_DELAY();
-
- *(cs->cs_reg_csr) = ZSWR0_RESET_STATUS;
- ZS_DELAY();
+ rr0 = zs_read_csr(cs);
+ zs_write_csr(cs, ZSWR0_RESET_STATUS);
ms->ms_intr_flags |= INTR_ST_CHECK;
/* Ask for softint() call. */