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authormatt <matt@NetBSD.org>2008-10-24 04:43:08 +0000
committermatt <matt@NetBSD.org>2008-10-24 04:43:08 +0000
commitf759cc96ec975bb1f9e1ca3a4085313e54337abb (patch)
tree3904568d8ac1df151f5b86a9b50ee1ce2a8c9171 /sys/dev
parentf5d7ce3d2fc36b2965729a33eb02fb95c9fb56cd (diff)
Add support for 16550 chips without an Enhanced Register Set.
Diffstat (limited to 'sys/dev')
-rw-r--r--sys/dev/ic/com.c27
-rw-r--r--sys/dev/ic/comvar.h1
2 files changed, 17 insertions, 11 deletions
diff --git a/sys/dev/ic/com.c b/sys/dev/ic/com.c
index 6cc46b76986..3e56c9a4c50 100644
--- a/sys/dev/ic/com.c
+++ b/sys/dev/ic/com.c
@@ -434,25 +434,26 @@ com_attach_subr(struct com_softc *sc)
* setting DLAB enable gives access to the EFR on
* these chips.
*/
- lcr = CSR_READ_1(regsp, COM_REG_LCR);
- CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS);
- CSR_WRITE_1(regsp, COM_REG_EFR, 0);
- if (CSR_READ_1(regsp, COM_REG_EFR) == 0) {
- CSR_WRITE_1(regsp, COM_REG_LCR,
- lcr | LCR_DLAB);
+ if (type != COM_TYPE_16550_NOERS) {
+ lcr = CSR_READ_1(regsp, COM_REG_LCR);
+ CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS);
+ CSR_WRITE_1(regsp, COM_REG_EFR, 0);
+
if (CSR_READ_1(regsp, COM_REG_EFR) == 0) {
+ CSR_WRITE_1(regsp, COM_REG_LCR,
+ lcr | LCR_DLAB);
CLR(sc->sc_hwflags, COM_HW_FIFO);
sc->sc_fifolen = 0;
} else {
SET(sc->sc_hwflags, COM_HW_FLOW);
sc->sc_fifolen = 32;
}
+ CSR_WRITE_1(regsp, COM_REG_LCR, lcr);
} else
#endif
sc->sc_fifolen = 16;
#ifdef COM_16650
- CSR_WRITE_1(regsp, COM_REG_LCR, lcr);
if (sc->sc_fifolen == 0)
fifo_msg = "st16650, broken fifo";
else if (sc->sc_fifolen == 32)
@@ -1454,7 +1455,9 @@ com_loadchannelregs(struct com_softc *sc)
}
if (ISSET(sc->sc_hwflags, COM_HW_FLOW)) {
- if (sc->sc_type != COM_TYPE_AU1x00) { /* no EFR on alchemy */
+ if (sc->sc_type != COM_TYPE_AU1x00
+ && sc->sc_type != COM_TYPE_16550_NOERS) {
+ /* no EFR on alchemy */
CSR_WRITE_1(regsp, COM_REG_EFR, sc->sc_efr);
CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS);
}
@@ -2146,9 +2149,11 @@ cominit(struct com_regs *regsp, int rate, int frequency, int type,
rate = comspeed(rate, frequency, type);
if (type != COM_TYPE_AU1x00) {
- /* no EFR on alchemy */
- CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS);
- CSR_WRITE_1(regsp, COM_REG_EFR, 0);
+ /* no EFR on alchemy */
+ if (type != COM_TYPE_16550_NOERS) {
+ CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS);
+ CSR_WRITE_1(regsp, COM_REG_EFR, 0);
+ }
CSR_WRITE_1(regsp, COM_REG_LCR, LCR_DLAB);
CSR_WRITE_1(regsp, COM_REG_DLBL, rate & 0xff);
CSR_WRITE_1(regsp, COM_REG_DLBH, rate >> 8);
diff --git a/sys/dev/ic/comvar.h b/sys/dev/ic/comvar.h
index bf4554fe4d4..a9006bac0e5 100644
--- a/sys/dev/ic/comvar.h
+++ b/sys/dev/ic/comvar.h
@@ -207,6 +207,7 @@ struct com_softc {
#define COM_TYPE_PXA2x0 2 /* Intel PXA2x0 processor built-in */
#define COM_TYPE_AU1x00 3 /* AMD/Alchemy Au1x000 proc. built-in */
#define COM_TYPE_OMAP 4 /* TI OMAP processor built-in */
+#define COM_TYPE_16550_NOERS 5 /* like a 16550, no ERS */
/* power management hooks */
int (*enable)(struct com_softc *);