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authortsutsui <tsutsui@NetBSD.org>2002-09-29 17:10:37 +0000
committertsutsui <tsutsui@NetBSD.org>2002-09-29 17:10:37 +0000
commitf84a0fccc0b1bb369cdc7c83273bddb64ab59d99 (patch)
treea0ee152854b3a8f53cb9cb6ef9a805d36703da99 /sys/dev
parent50d060cc528533878c2f22090902cdb1f67483b9 (diff)
Fix chip identification bit definitions in DLC7 register,
from Christian Groessler on port-dreamcast.
Diffstat (limited to 'sys/dev')
-rw-r--r--sys/dev/ic/mb86960.c6
-rw-r--r--sys/dev/ic/mb86960reg.h16
2 files changed, 15 insertions, 7 deletions
diff --git a/sys/dev/ic/mb86960.c b/sys/dev/ic/mb86960.c
index 118f7d5e67f..541c310502c 100644
--- a/sys/dev/ic/mb86960.c
+++ b/sys/dev/ic/mb86960.c
@@ -1,4 +1,4 @@
-/* $NetBSD: mb86960.c,v 1.51 2002/09/28 17:22:49 tsutsui Exp $ */
+/* $NetBSD: mb86960.c,v 1.52 2002/09/29 17:10:37 tsutsui Exp $ */
/*
* All Rights Reserved, Copyright (C) Fujitsu Limited 1995
@@ -32,7 +32,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: mb86960.c,v 1.51 2002/09/28 17:22:49 tsutsui Exp $");
+__KERNEL_RCSID(0, "$NetBSD: mb86960.c,v 1.52 2002/09/29 17:10:37 tsutsui Exp $");
/*
* Device driver for Fujitsu MB86960A/MB86965A based Ethernet cards.
@@ -144,7 +144,7 @@ mb86960_attach(sc, type, myea)
switch (sc->type) {
case MB86960_TYPE_86960:
- sc->proto_dlcr7 = FE_D7_BYTSWP_LH | FE_D7_IDENT_EC;
+ sc->proto_dlcr7 = FE_D7_BYTSWP_LH | FE_D7_ED_TEST; /* XXX */
break;
case MB86960_TYPE_86965:
sc->proto_dlcr7 = FE_D7_BYTSWP_LH;
diff --git a/sys/dev/ic/mb86960reg.h b/sys/dev/ic/mb86960reg.h
index f509777d71b..aa1dda1074e 100644
--- a/sys/dev/ic/mb86960reg.h
+++ b/sys/dev/ic/mb86960reg.h
@@ -1,4 +1,4 @@
-/* $NetBSD: mb86960reg.h,v 1.5 2002/09/28 17:52:59 tsutsui Exp $ */
+/* $NetBSD: mb86960reg.h,v 1.6 2002/09/29 17:10:37 tsutsui Exp $ */
/*
* All Rights Reserved, Copyright (C) Fujitsu Limited 1995
@@ -200,6 +200,7 @@
#define FE_D7_RBS 0x0C /* Register bank select */
#define FE_D7_RDYPNS 0x10 /* Senses RDYPNSEL input signal */
#define FE_D7_POWER 0x20 /* Stand-by (power down) mode control */
+#define FE_D7_ED 0xC0 /* Encoder/Decoder config (for MB86960) */
#define FE_D7_IDENT 0xC0 /* Chip identification */
#define FE_D7_BYTSWP_LH 0x00 /* DEC/Intel byte order */
@@ -212,12 +213,19 @@
#define FE_D7_POWER_DOWN 0x00 /* Power down (stand-by) mode */
#define FE_D7_POWER_UP 0x20 /* Normal operation */
-#define FE_D7_IDENT_NICE 0x80
-#define FE_D7_IDENT_EC 0xC0
+#define FE_D7_ED_NORMAL 0x00 /* Normal NICE */
+#define FE_D7_ED_MON 0x40 /* NICE + Monitor */
+#define FE_D7_ED_BYPASS 0x80 /* Encoder/Decorder Bypass */
+#define FE_D7_ED_TEST 0xC0 /* Encoder/Decorder Test */
+
+#define FE_D7_IDENT_86960 0x00 /* MB86960 (NICE) */
+#define FE_D7_IDENT_86964 0x40 /* MB86964 */
+#define FE_D7_IDENT_86967 0x80 /* MB86967 */
+#define FE_D7_IDENT_86965 0xC0 /* MB86965 (EtherCoupler) */
/* DLCR8 thru DLCR13 are for Ethernet station address. */
-/* DLCR14 and DLCR15 are for TDR. (BTW, what is TDR? FIXME.) */
+/* DLCR14 and DLCR15 are for TDR (Time Domain Reflectometry). */
/* MAR8 thru MAR15 are for Multicast address filter. */