diff options
| author | bad <bad@NetBSD.org> | 2013-11-17 23:20:18 +0000 |
|---|---|---|
| committer | bad <bad@NetBSD.org> | 2013-11-17 23:20:18 +0000 |
| commit | fdd2e1a43e1d07e98b308db34d8763a6c55ffc4a (patch) | |
| tree | 0972e9bba85df64127f1ea7da216c29602236abb /sys/dev | |
| parent | b0dea518cb47681b49e44153a853ef1b8b107018 (diff) | |
Add support for BCM5825, and BCM5860, 5861, 5862 from OpenBSD rev 1.143:
Add support for the BCM5825 and the next-generation BCM5860, 5861,
5862 Broadcom CryptoNetX IPSec/SSL Security Processors. The 5825 is a
faster version of the already supported 5823, and the even faster 586x
series is a bit different and needed some more changes.
AES support hasn't been pulled in yet.
Diffstat (limited to 'sys/dev')
| -rw-r--r-- | sys/dev/pci/ubsec.c | 208 | ||||
| -rw-r--r-- | sys/dev/pci/ubsecreg.h | 21 | ||||
| -rw-r--r-- | sys/dev/pci/ubsecvar.h | 15 |
3 files changed, 218 insertions, 26 deletions
diff --git a/sys/dev/pci/ubsec.c b/sys/dev/pci/ubsec.c index b4e41b76c18..54d31f9c54e 100644 --- a/sys/dev/pci/ubsec.c +++ b/sys/dev/pci/ubsec.c @@ -1,4 +1,4 @@ -/* $NetBSD: ubsec.c,v 1.33 2013/11/17 22:52:14 bad Exp $ */ +/* $NetBSD: ubsec.c,v 1.34 2013/11/17 23:20:18 bad Exp $ */ /* $FreeBSD: src/sys/dev/ubsec/ubsec.c,v 1.6.2.6 2003/01/23 21:06:43 sam Exp $ */ /* $OpenBSD: ubsec.c,v 1.127 2003/06/04 14:04:58 jason Exp $ */ @@ -35,7 +35,7 @@ */ #include <sys/cdefs.h> -__KERNEL_RCSID(0, "$NetBSD: ubsec.c,v 1.33 2013/11/17 22:52:14 bad Exp $"); +__KERNEL_RCSID(0, "$NetBSD: ubsec.c,v 1.34 2013/11/17 23:20:18 bad Exp $"); #undef UBSEC_DEBUG @@ -122,6 +122,7 @@ static void ubsec_feed(struct ubsec_softc *); static void ubsec_mcopy(struct mbuf *, struct mbuf *, int, int); static void ubsec_callback2(struct ubsec_softc *, struct ubsec_q2 *); static void ubsec_feed2(struct ubsec_softc *); +static void ubsec_feed4(struct ubsec_softc *); #ifndef UBSEC_NO_RNG static void ubsec_rng(void *); static void ubsec_rng_locked(void *); @@ -188,34 +189,40 @@ static const struct ubsec_product { pci_product_id_t ubsec_product; int ubsec_flags; int ubsec_statmask; + int ubsec_maxaggr; const char *ubsec_name; } ubsec_products[] = { { PCI_VENDOR_BLUESTEEL, PCI_PRODUCT_BLUESTEEL_5501, 0, BS_STAT_MCR1_DONE | BS_STAT_DMAERR, + UBS_MIN_AGGR, "Bluesteel 5501" }, { PCI_VENDOR_BLUESTEEL, PCI_PRODUCT_BLUESTEEL_5601, UBS_FLAGS_KEY | UBS_FLAGS_RNG, BS_STAT_MCR1_DONE | BS_STAT_DMAERR, + UBS_MIN_AGGR, "Bluesteel 5601" }, { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5801, 0, BS_STAT_MCR1_DONE | BS_STAT_DMAERR, + UBS_MIN_AGGR, "Broadcom BCM5801" }, { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5802, UBS_FLAGS_KEY | UBS_FLAGS_RNG, BS_STAT_MCR1_DONE | BS_STAT_DMAERR, + UBS_MIN_AGGR, "Broadcom BCM5802" }, { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5805, UBS_FLAGS_KEY | UBS_FLAGS_RNG, BS_STAT_MCR1_DONE | BS_STAT_DMAERR, + UBS_MIN_AGGR, "Broadcom BCM5805" }, @@ -223,6 +230,7 @@ static const struct ubsec_product { UBS_FLAGS_KEY | UBS_FLAGS_RNG | UBS_FLAGS_LONGCTX | UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY, BS_STAT_MCR1_DONE | BS_STAT_DMAERR, + UBS_MIN_AGGR, "Broadcom BCM5820" }, @@ -231,6 +239,7 @@ static const struct ubsec_product { UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY, BS_STAT_MCR1_DONE | BS_STAT_DMAERR | BS_STAT_MCR1_ALLEMPTY | BS_STAT_MCR2_ALLEMPTY, + UBS_MIN_AGGR, "Broadcom BCM5821" }, { PCI_VENDOR_SUN, PCI_PRODUCT_SUN_SCA1K, @@ -238,6 +247,7 @@ static const struct ubsec_product { UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY, BS_STAT_MCR1_DONE | BS_STAT_DMAERR | BS_STAT_MCR1_ALLEMPTY | BS_STAT_MCR2_ALLEMPTY, + UBS_MIN_AGGR, "Sun Crypto Accelerator 1000" }, { PCI_VENDOR_SUN, PCI_PRODUCT_SUN_5821, @@ -245,6 +255,7 @@ static const struct ubsec_product { UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY, BS_STAT_MCR1_DONE | BS_STAT_DMAERR | BS_STAT_MCR1_ALLEMPTY | BS_STAT_MCR2_ALLEMPTY, + UBS_MIN_AGGR, "Broadcom BCM5821 (Sun)" }, @@ -253,6 +264,7 @@ static const struct ubsec_product { UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY, BS_STAT_MCR1_DONE | BS_STAT_DMAERR | BS_STAT_MCR1_ALLEMPTY | BS_STAT_MCR2_ALLEMPTY, + UBS_MIN_AGGR, "Broadcom BCM5822" }, @@ -261,12 +273,59 @@ static const struct ubsec_product { UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY, BS_STAT_MCR1_DONE | BS_STAT_DMAERR | BS_STAT_MCR1_ALLEMPTY | BS_STAT_MCR2_ALLEMPTY, + UBS_MIN_AGGR, "Broadcom BCM5823" }, + { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5825, + UBS_FLAGS_KEY | UBS_FLAGS_RNG | UBS_FLAGS_LONGCTX | + UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY, + BS_STAT_MCR1_DONE | BS_STAT_DMAERR | + BS_STAT_MCR1_ALLEMPTY | BS_STAT_MCR2_ALLEMPTY, + UBS_MIN_AGGR, + "Broadcom BCM5825" + }, + + { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5860, + UBS_FLAGS_MULTIMCR | UBS_FLAGS_HWNORM | + UBS_FLAGS_LONGCTX | + UBS_FLAGS_RNG | UBS_FLAGS_RNG4 | + UBS_FLAGS_KEY | UBS_FLAGS_BIGKEY, + BS_STAT_MCR1_DONE | BS_STAT_DMAERR | + BS_STAT_MCR1_ALLEMPTY | BS_STAT_MCR2_ALLEMPTY | + BS_STAT_MCR3_ALLEMPTY | BS_STAT_MCR4_ALLEMPTY, + UBS_MAX_AGGR, + "Broadcom BCM5860" + }, + + { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5861, + UBS_FLAGS_MULTIMCR | UBS_FLAGS_HWNORM | + UBS_FLAGS_LONGCTX | + UBS_FLAGS_RNG | UBS_FLAGS_RNG4 | + UBS_FLAGS_KEY | UBS_FLAGS_BIGKEY, + BS_STAT_MCR1_DONE | BS_STAT_DMAERR | + BS_STAT_MCR1_ALLEMPTY | BS_STAT_MCR2_ALLEMPTY | + BS_STAT_MCR3_ALLEMPTY | BS_STAT_MCR4_ALLEMPTY, + UBS_MAX_AGGR, + "Broadcom BCM5861" + }, + + { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5862, + UBS_FLAGS_MULTIMCR | UBS_FLAGS_HWNORM | + UBS_FLAGS_LONGCTX | + UBS_FLAGS_RNG | UBS_FLAGS_RNG4 | + UBS_FLAGS_KEY | UBS_FLAGS_BIGKEY, + BS_STAT_MCR1_DONE | BS_STAT_DMAERR | + BS_STAT_MCR1_ALLEMPTY | BS_STAT_MCR2_ALLEMPTY | + BS_STAT_MCR3_ALLEMPTY | BS_STAT_MCR4_ALLEMPTY, + UBS_MAX_AGGR, + "Broadcom BCM5862" + }, + { 0, 0, 0, 0, + 0, NULL } }; @@ -304,6 +363,7 @@ ubsec_attach(device_t parent, device_t self, void *aux) pci_chipset_tag_t pc = pa->pa_pc; pci_intr_handle_t ih; const char *intrstr = NULL; + pcireg_t memtype; struct ubsec_dma *dmap; u_int32_t cmd, i; @@ -322,16 +382,20 @@ ubsec_attach(device_t parent, device_t self, void *aux) SIMPLEQ_INIT(&sc->sc_qchip); SIMPLEQ_INIT(&sc->sc_queue2); SIMPLEQ_INIT(&sc->sc_qchip2); + SIMPLEQ_INIT(&sc->sc_queue4); + SIMPLEQ_INIT(&sc->sc_qchip4); SIMPLEQ_INIT(&sc->sc_q2free); sc->sc_flags = up->ubsec_flags; sc->sc_statmask = up->ubsec_statmask; + sc->sc_maxaggr = up->ubsec_maxaggr; cmd = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); cmd |= PCI_COMMAND_MASTER_ENABLE; pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, cmd); - if (pci_mapreg_map(pa, BS_BAR, PCI_MAPREG_TYPE_MEM, 0, + memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BS_BAR); + if (pci_mapreg_map(pa, BS_BAR, memtype, 0, &sc->sc_st, &sc->sc_sh, NULL, &sc->sc_memsize)) { aprint_error_dev(self, "can't find mem space"); return; @@ -416,7 +480,10 @@ ubsec_attach(device_t parent, device_t self, void *aux) #ifndef UBSEC_NO_RNG if (sc->sc_flags & UBS_FLAGS_RNG) { - sc->sc_statmask |= BS_STAT_MCR2_DONE; + if (sc->sc_flags & UBS_FLAGS_RNG4) + sc->sc_statmask |= BS_STAT_MCR4_DONE; + else + sc->sc_statmask |= BS_STAT_MCR2_DONE; if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), &sc->sc_rng.rng_q.q_mcr, 0)) @@ -596,6 +663,7 @@ ubsec_intr(void *arg) volatile u_int32_t stat; struct ubsec_q *q; struct ubsec_dma *dmap; + int flags; int npkts = 0, i; mutex_spin_enter(&sc->sc_mtx); @@ -662,7 +730,13 @@ ubsec_intr(void *arg) BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); mcr = (struct ubsec_mcr *)q2->q_mcr.dma_vaddr; - if ((mcr->mcr_flags & htole16(UBS_MCR_DONE)) == 0) { + + /* A bug in new devices requires to swap this field */ + if (sc->sc_flags & UBS_FLAGS_MULTIMCR) + flags = htole16(mcr->mcr_flags); + else + flags = mcr->mcr_flags; + if ((flags & htole16(UBS_MCR_DONE)) == 0) { bus_dmamap_sync(sc->sc_dmat, q2->q_mcr.dma_map, 0, q2->q_mcr.dma_map->dm_mapsize, @@ -680,6 +754,39 @@ ubsec_intr(void *arg) ubsec_feed2(sc); } } + if ((sc->sc_flags & UBS_FLAGS_RNG4) && (stat & BS_STAT_MCR4_DONE)) { + struct ubsec_q2 *q2; + struct ubsec_mcr *mcr; + + while (!SIMPLEQ_EMPTY(&sc->sc_qchip4)) { + q2 = SIMPLEQ_FIRST(&sc->sc_qchip4); + + bus_dmamap_sync(sc->sc_dmat, q2->q_mcr.dma_map, + 0, q2->q_mcr.dma_map->dm_mapsize, + BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); + + mcr = (struct ubsec_mcr *)q2->q_mcr.dma_vaddr; + + /* A bug in new devices requires to swap this field */ + flags = htole16(mcr->mcr_flags); + + if ((flags & htole16(UBS_MCR_DONE)) == 0) { + bus_dmamap_sync(sc->sc_dmat, + q2->q_mcr.dma_map, 0, + q2->q_mcr.dma_map->dm_mapsize, + BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); + break; + } + SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip4, q_next); + ubsec_callback2(sc, q2); + /* + * Don't send any more packet to chip if there has been + * a DMAERR. + */ + if (!(stat & BS_STAT_DMAERR)) + ubsec_feed4(sc); + } + } /* * Check to see if we got any DMA Error @@ -747,8 +854,8 @@ ubsec_feed(struct ubsec_softc *sc) * completed ops as we only get an interrupt when all aggregated * ops have completed. */ - if (npkts > UBS_MAX_AGGR) - npkts = UBS_MAX_AGGR; + if (npkts > sc->sc_maxaggr) + npkts = sc->sc_maxaggr; if (npkts > ubsec_maxaggr) npkts = ubsec_maxaggr; if (npkts > ubsecstats.hst_maxbatch) @@ -1737,6 +1844,33 @@ ubsec_feed2(struct ubsec_softc *sc) } /* + * feed the RNG (used instead of ubsec_feed2() on 5827+ devices) + */ +void +ubsec_feed4(struct ubsec_softc *sc) +{ + struct ubsec_q2 *q; + + while (!SIMPLEQ_EMPTY(&sc->sc_queue4)) { + if (READ_REG(sc, BS_STAT) & BS_STAT_MCR4_FULL) + break; + q = SIMPLEQ_FIRST(&sc->sc_queue4); + + bus_dmamap_sync(sc->sc_dmat, q->q_mcr.dma_map, 0, + q->q_mcr.dma_map->dm_mapsize, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); + bus_dmamap_sync(sc->sc_dmat, q->q_ctx.dma_map, 0, + q->q_ctx.dma_map->dm_mapsize, + BUS_DMASYNC_PREWRITE); + + WRITE_REG(sc, BS_MCR4, q->q_mcr.dma_paddr); + SIMPLEQ_REMOVE_HEAD(&sc->sc_queue4, q_next); + --sc->sc_nqueue4; + SIMPLEQ_INSERT_TAIL(&sc->sc_qchip4, q, q_next); + } +} + +/* * Callback for handling random numbers */ static void @@ -1763,13 +1897,12 @@ ubsec_callback2(struct ubsec_softc *sc, struct ubsec_q2 *q) #ifndef __NetBSD__ for (i = 0; i < UBSEC_RNG_BUFSIZ; p++, i++) add_true_randomness(letoh32(*p)); - rng->rng_used = 0; #else i = UBSEC_RNG_BUFSIZ * sizeof(u_int32_t); rnd_add_data(&sc->sc_rnd_source, (char *)p, i, i * NBBY); sc->sc_rng_need -= i; - rng->rng_used = 0; #endif + rng->rng_used = 0; #ifdef __OpenBSD__ timeout_add(&sc->sc_rngto, sc->sc_rnghz); #else @@ -1887,6 +2020,7 @@ ubsec_rng_locked(void *vsc) struct ubsec_q2_rng *rng = &sc->sc_rng; struct ubsec_mcr *mcr; struct ubsec_ctx_rngbypass *ctx; + int *nqueue; /* Caller is responsible to lock and release sc_mtx. */ KASSERT(mutex_owned(&sc->sc_mtx)); @@ -1900,9 +2034,14 @@ ubsec_rng_locked(void *vsc) return; } - sc->sc_nqueue2++; - if (sc->sc_nqueue2 >= UBS_MAX_NQUEUE) - goto out; + if (sc->sc_flags & UBS_FLAGS_RNG4) + nqueue = &sc->sc_nqueue4; + else + nqueue = &sc->sc_nqueue2; + + (*nqueue)++; + if (*nqueue >= UBS_MAX_NQUEUE) + goto out; mcr = (struct ubsec_mcr *)rng->rng_q.q_mcr.dma_vaddr; ctx = (struct ubsec_ctx_rngbypass *)rng->rng_q.q_ctx.dma_vaddr; @@ -1925,9 +2064,14 @@ ubsec_rng_locked(void *vsc) bus_dmamap_sync(sc->sc_dmat, rng->rng_buf.dma_map, 0, rng->rng_buf.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); - SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &rng->rng_q, q_next); + if (sc->sc_flags & UBS_FLAGS_RNG4) { + SIMPLEQ_INSERT_TAIL(&sc->sc_queue4, &rng->rng_q, q_next); + ubsec_feed4(sc); + } else { + SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &rng->rng_q, q_next); + ubsec_feed2(sc); + } rng->rng_used = 1; - ubsec_feed2(sc); ubsecstats.hst_rng++; return; @@ -1936,7 +2080,7 @@ out: /* * Something weird happened, generate our own call back. */ - sc->sc_nqueue2--; + (*nqueue)--; #ifdef __OpenBSD__ timeout_add(&sc->sc_rngto, sc->sc_rnghz); #else @@ -1998,16 +2142,24 @@ ubsec_dma_free(struct ubsec_softc *sc, struct ubsec_dma_alloc *dma) static void ubsec_reset_board(struct ubsec_softc *sc) { - volatile u_int32_t ctrl; + volatile u_int32_t ctrl; + + ctrl = READ_REG(sc, BS_CTRL); + ctrl |= BS_CTRL_RESET; + WRITE_REG(sc, BS_CTRL, ctrl); - ctrl = READ_REG(sc, BS_CTRL); - ctrl |= BS_CTRL_RESET; - WRITE_REG(sc, BS_CTRL, ctrl); + /* + * Wait aprox. 30 PCI clocks = 900 ns = 0.9 us + */ + DELAY(10); - /* - * Wait aprox. 30 PCI clocks = 900 ns = 0.9 us - */ - DELAY(10); + /* Enable RNG and interrupts on newer devices */ + if (sc->sc_flags & UBS_FLAGS_MULTIMCR) { +#ifndef UBSEC_NO_RNG + WRITE_REG(sc, BS_CFG, BS_CFG_RNG); +#endif + WRITE_REG(sc, BS_INT, BS_INT_DMAINT); + } } /* @@ -2034,6 +2186,16 @@ ubsec_init_board(struct ubsec_softc *sc) if (sc->sc_flags & UBS_FLAGS_HWNORM) ctrl &= ~BS_CTRL_SWNORM; + if (sc->sc_flags & UBS_FLAGS_MULTIMCR) { + ctrl |= BS_CTRL_BSIZE240; + ctrl &= ~BS_CTRL_MCR3INT; /* MCR3 is reserved for SSL */ + + if (sc->sc_flags & UBS_FLAGS_RNG4) + ctrl |= BS_CTRL_MCR4INT; + else + ctrl &= ~BS_CTRL_MCR4INT; + } + WRITE_REG(sc, BS_CTRL, ctrl); } diff --git a/sys/dev/pci/ubsecreg.h b/sys/dev/pci/ubsecreg.h index 0bc13a8a471..d6ee66abc38 100644 --- a/sys/dev/pci/ubsecreg.h +++ b/sys/dev/pci/ubsecreg.h @@ -1,4 +1,4 @@ -/* $NetBSD: ubsecreg.h,v 1.2 2005/12/11 12:22:51 christos Exp $ */ +/* $NetBSD: ubsecreg.h,v 1.3 2013/11/17 23:20:18 bad Exp $ */ /* $OpenBSD: ubsecreg.h,v 1.28 2003/06/04 16:02:41 jason Exp $ */ /* @@ -60,6 +60,10 @@ #define BS_STAT 0x08 /* DMA Status */ #define BS_ERR 0x0c /* DMA Error Address */ #define BS_MCR2 0x10 /* DMA Master Command Record 2 */ +#define BS_MCR3 0x0014 /* 5827+, DMA Master Command Record 3 */ +#define BS_MCR4 0x001c /* 5827+, DMA Master Command Record 4 */ +#define BS_CFG 0x0700 /* 5827+, Configuration Register */ +#define BS_INT 0x0f00 /* 5827+, Interrupt Register */ /* BS_CTRL - DMA Control */ #define BS_CTRL_RESET 0x80000000 /* hardware reset, 5805/5820 */ @@ -75,6 +79,9 @@ #define BS_CTRL_RNG_8 0x01000000 /* 1bit rn/eight slow clocks */ #define BS_CTRL_RNG_16 0x01800000 /* 1bit rn/16 slow clocks */ #define BS_CTRL_SWNORM 0x00400000 /* 582[01], sw normalization */ +#define BS_CTRL_MCR3INT 0x00400000 /* 5827+, intr for MCR3 */ +#define BS_CTRL_MCR4INT 0x00200000 /* 5827+, intr for MCR4 */ +#define BS_CTRL_BSIZE240 0x000f0000 /* 5827+, burst size 240 */ #define BS_CTRL_FRAG_M 0x0000ffff /* output fragment size mask */ #define BS_CTRL_LITTLE_ENDIAN (BS_CTRL_BE32 | BS_CTRL_BE64) @@ -87,11 +94,23 @@ #define BS_STAT_MCR2_DONE 0x04000000 /* MCR2 is done */ #define BS_STAT_MCR1_ALLEMPTY 0x02000000 /* 5821, MCR1 is empty */ #define BS_STAT_MCR2_ALLEMPTY 0x01000000 /* 5821, MCR2 is empty */ +#define BS_STAT_MCR3_ALLEMPTY 0x00800000 /* 5827+, MCR3 is empty */ +#define BS_STAT_MCR4_ALLEMPTY 0x00400000 /* 5827+, MCR4 is empty */ +#define BS_STAT_MCR3_FULL 0x00080000 /* 5827+, MCR3 is full */ +#define BS_STAT_MCR3_DONE 0x00040000 /* 5827+, MCR3 is done */ +#define BS_STAT_MCR4_FULL 0x00020000 /* 5827+, MCR4 is full */ +#define BS_STAT_MCR4_DONE 0x00010000 /* 5827+, MCR4 is done */ /* BS_ERR - DMA Error Address */ #define BS_ERR_ADDR 0xfffffffc /* error address mask */ #define BS_ERR_READ 0x00000002 /* fault was on read */ +/* BS_CFG */ +#define BS_CFG_RNG 0x00000001 /* 5827+, enable RNG */ + +/* BS_INT */ +#define BS_INT_DMAINT 0x80000000 /* 5827+, enable DMA intr */ + struct ubsec_pktctx { u_int32_t pc_deskey[6]; /* 3DES key */ u_int32_t pc_hminner[5]; /* hmac inner state */ diff --git a/sys/dev/pci/ubsecvar.h b/sys/dev/pci/ubsecvar.h index 0f51348a57e..cc153f188df 100644 --- a/sys/dev/pci/ubsecvar.h +++ b/sys/dev/pci/ubsecvar.h @@ -1,4 +1,4 @@ -/* $NetBSD: ubsecvar.h,v 1.6 2013/11/17 17:16:25 bad Exp $ */ +/* $NetBSD: ubsecvar.h,v 1.7 2013/11/17 23:20:18 bad Exp $ */ /* $OpenBSD: ubsecvar.h,v 1.36 2003/06/04 16:02:41 jason Exp $ */ /* @@ -40,7 +40,11 @@ #define UBS_MAX_SCATTER 64 /* Maximum scatter/gather depth */ #ifndef UBS_MAX_AGGR -#define UBS_MAX_AGGR 5 /* Maximum aggregation count */ +#define UBS_MAX_AGGR 17 /* Maximum aggregation count */ +#endif + +#ifndef UBS_MIN_AGGR +#define UBS_MIN_AGGR 5 /* < 5827, Maximum aggregation count */ #endif #define UBSEC_CARD(sid) (((sid) & 0xf0000000) >> 28) @@ -128,6 +132,9 @@ struct ubsec_dma { #define UBS_FLAGS_BIGKEY 0x04 /* 2048bit keys */ #define UBS_FLAGS_HWNORM 0x08 /* hardware normalization */ #define UBS_FLAGS_RNG 0x10 /* hardware rng */ +#define UBS_FLAGS_AES 0x20 /* supports AES */ +#define UBS_FLAGS_MULTIMCR 0x40 /* 5827+ with 4 MCRs */ +#define UBS_FLAGS_RNG4 0x80 /* 5827+ RNG on MCR4 */ struct ubsec_q { SIMPLEQ_ENTRY(ubsec_q) q_next; @@ -159,6 +166,7 @@ struct ubsec_softc { int sc_needwakeup; /* notify crypto layer */ u_int32_t sc_statmask; /* interrupt status mask */ int32_t sc_cid; /* crypto tag */ + int sc_maxaggr; /* max pkt aggregation */ SIMPLEQ_HEAD(,ubsec_q) sc_queue; /* packet queue, mcr1 */ int sc_nqueue; /* count enqueued, mcr1 */ SIMPLEQ_HEAD(,ubsec_q) sc_qchip; /* on chip, mcr1 */ @@ -167,6 +175,9 @@ struct ubsec_softc { SIMPLEQ_HEAD(,ubsec_q2) sc_queue2; /* packet queue, mcr2 */ int sc_nqueue2; /* count enqueued, mcr2 */ SIMPLEQ_HEAD(,ubsec_q2) sc_qchip2; /* on chip, mcr2 */ + SIMPLEQ_HEAD(,ubsec_q2) sc_queue4; /* packet queue, mcr4 */ + int sc_nqueue4; /* count enqueued, mcr4 */ + SIMPLEQ_HEAD(,ubsec_q2) sc_qchip4; /* on chip, mcr4 */ int sc_nsessions; /* # of sessions */ struct ubsec_session *sc_sessions; /* sessions */ struct callout sc_rngto; /* rng timeout */ |
