diff options
| author | mark <mark@NetBSD.org> | 1996-03-07 23:54:28 +0000 |
|---|---|---|
| committer | mark <mark@NetBSD.org> | 1996-03-07 23:54:28 +0000 |
| commit | 095bb565ba62eb747c11cfbee08030335fd22013 (patch) | |
| tree | 0520acfab041e3d5af0d1f9ed4cf44bb79f3b191 /sys | |
| parent | 3506c48c2a41e3bd6b218b10926f215096a22895 (diff) | |
Files for the new Acorn SCSI driver that uses the generic SBIC driver
code. This is a much better version that does not trash your HD.
Diffstat (limited to 'sys')
| -rw-r--r-- | sys/arch/arm32/podulebus/asc.c | 467 | ||||
| -rw-r--r-- | sys/arch/arm32/podulebus/ascreg.h | 279 | ||||
| -rw-r--r-- | sys/arch/arm32/podulebus/ascvar.h | 52 |
3 files changed, 798 insertions, 0 deletions
diff --git a/sys/arch/arm32/podulebus/asc.c b/sys/arch/arm32/podulebus/asc.c new file mode 100644 index 00000000000..ed46869ec0d --- /dev/null +++ b/sys/arch/arm32/podulebus/asc.c @@ -0,0 +1,467 @@ +/* $NetBSD: asc.c,v 1.1 1996/03/07 23:54:28 mark Exp $ */ + +/* + * Copyright (c) 1996 Mark Brinicombe + * Copyright (c) 1982, 1990 The Regents of the University of California. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * from:ahsc.c + */ + +/* + * Ok this driver is not wonderful yet. It only supports POLLING mode + * The Acorn SCSI card (or any WD3393 based card) does not support + * DMA so the DMA section of this driver and the sbic driver needs + * to be rewritten. + */ + +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/kernel.h> +#include <sys/device.h> +#include <scsi/scsi_all.h> +#include <scsi/scsiconf.h> +#include <machine/io.h> +#include <machine/irqhandler.h> +#include <machine/katelib.h> +#include <arm32/podulebus/podulebus.h> +#include <arm32/podulebus/sbicreg.h> +#include <arm32/podulebus/sbicvar.h> +#include <arm32/podulebus/ascreg.h> +#include <arm32/podulebus/ascvar.h> + +int ascprint __P((void *auxp, char *)); +void ascattach __P((struct device *, struct device *, void *)); +int ascmatch __P((struct device *, struct cfdata *, void *)); + +void asc_enintr __P((struct sbic_softc *)); +void asc_dmastop __P((struct sbic_softc *)); +int asc_dmanext __P((struct sbic_softc *)); +int asc_dmaintr __P((struct sbic_softc *)); +int asc_dmago __P((struct sbic_softc *, char *, int, int)); +int asc_scsicmd __P((struct scsi_xfer *xs)); +int asc_intr __P((struct asc_softc *)); + +char *strstr __P((char */*s1*/, char */*s2*/)); + +struct scsi_adapter asc_scsiswitch = { + asc_scsicmd, + sbic_minphys, + 0, /* no lun support */ + 0, /* no lun support */ +}; + +struct scsi_device asc_scsidev = { + NULL, /* use default error handler */ + NULL, /* do not have a start functio */ + NULL, /* have no async handler */ + NULL, /* Use default done routine */ +}; + + +#ifdef DEBUG +int asc_dmadebug = 0; +#endif + +struct cfdriver asccd = { + NULL, "asc", (cfmatch_t)ascmatch, ascattach, + DV_DULL, sizeof(struct asc_softc), NULL, 0 }; + +u_long scsi_nosync; +int shift_nosync; + +#if ASC_POLL > 0 +int asc_poll = 1; + +extern char *boot_args; +#endif + +int +ascmatch(pdp, cdp, auxp) + struct device *pdp; + struct cfdata *cdp; + void *auxp; +{ + struct podule_attach_args *pa = (struct podule_attach_args *)auxp; + int podule; + + podule = findpodule(0x00, 0x02, pa->pa_podule_number); + + if (podule == -1) + return(0); + + pa->pa_podule_number = podule; + pa->pa_podule = &podules[podule]; + + return(1); +} + +void +ascattach(pdp, dp, auxp) + struct device *pdp, *dp; + void *auxp; +{ + volatile struct sdmac *rp; + struct asc_softc *sc; + struct sbic_softc *sbic; + struct podule_attach_args *pa; + + sc = (struct asc_softc *)dp; + + pa = (struct podule_attach_args *)auxp; + sc->sc_podule_number = pa->pa_podule_number; + if (sc->sc_podule_number == -1) + panic("Podule has disappeared !"); + + sc->sc_podule = &podules[sc->sc_podule_number]; + podules[sc->sc_podule_number].attached = 1; + +#if ASC_POLL > 0 + if (boot_args) { + char *ptr; + + ptr = strstr(boot_args, "noascpoll"); + if (ptr) + asc_poll = 0; + } + + if (asc_poll) + printf(" polling"); + else + printf(" using interrupts"); +#endif + printf("\n"); + + sbic = &sc->sc_softc; + + sbic->sc_enintr = asc_enintr; + sbic->sc_dmago = asc_dmago; + sbic->sc_dmanext = asc_dmanext; + sbic->sc_dmastop = asc_dmastop; + sbic->sc_dmacmd = 0; + + /* + * eveything is a valid dma address + */ + sbic->sc_dmamask = 0; + sbic->sc_sbicp = (sbic_regmap_p) (sc->sc_podule->mod_base + ASC_SBIC); + sbic->sc_clkfreq = sbic_clock_override ? sbic_clock_override : 143; + + sbic->sc_link.adapter_softc = sbic; + sbic->sc_link.adapter_target = 7; + sbic->sc_link.adapter = &asc_scsiswitch; + sbic->sc_link.device = &asc_scsidev; + sbic->sc_link.openings = 1; /* was 2 */ + + sc->sc_pagereg = sc->sc_podule->fast_base + ASC_PAGEREG; + sc->sc_intstat = sc->sc_podule->fast_base + ASC_INTSTATUS; + + /* Reset the card */ + + WriteByte(sc->sc_pagereg, 0x80); + DELAY(500000); + WriteByte(sc->sc_pagereg, 0x00); + DELAY(250000); + + sbicinit(sbic); + +/* If we are polling only then we don't need a interrupt handler */ + + sc->sc_ih.ih_func = asc_intr; + sc->sc_ih.ih_arg = sc; + sc->sc_ih.ih_level = IPL_BIO; +#ifdef ASC_POLL + if (!asc_poll) +#endif + if (irq_claim(IRQ_PODULE, &sc->sc_ih)) + panic("asc: Cannot claim podule IRQ\n"); + + /* + * attach all scsi units on us + */ + config_found(dp, &sbic->sc_link, ascprint); +} + +/* + * print diag if pnp is NULL else just extra + */ +int +ascprint(auxp, pnp) + void *auxp; + char *pnp; +{ + if (pnp == NULL) + return(UNCONF); + return(QUIET); +} + + +void +asc_enintr(sbicsc) + struct sbic_softc *sbicsc; +{ + struct asc_softc *sc = (struct asc_softc *)sbicsc; +/* printf("asc_enintr\n");*/ +/* + volatile struct sdmac *sdp; + + sdp = dev->sc_cregs; + + dev->sc_flags |= SBICF_INTR; + sdp->CNTR = CNTR_PDMD | CNTR_INTEN; +*/ + sbicsc->sc_flags |= SBICF_INTR; + WriteByte(sc->sc_pagereg, 0x40); +} + + +int +asc_dmago(dev, addr, count, flags) + struct sbic_softc *dev; + char *addr; + int count, flags; +{ + printf("asc_dmago\n"); + Debugger(); +#if 0 + volatile struct sdmac *sdp; + + sdp = dev->sc_cregs; + /* + * Set up the command word based on flags + */ + dev->sc_dmacmd = CNTR_PDMD | CNTR_INTEN; + if ((flags & DMAGO_READ) == 0) + dev->sc_dmacmd |= CNTR_DDIR; +#ifdef DEBUG + if (ahsc_dmadebug & DDB_IO) + printf("ahsc_dmago: cmd %x\n", dev->sc_dmacmd); +#endif + + dev->sc_flags |= SBICF_INTR; + sdp->CNTR = dev->sc_dmacmd; + sdp->ACR = (u_int) dev->sc_cur->dc_addr; + sdp->ST_DMA = 1; + + return(dev->sc_tcnt); +#endif +} + +void +asc_dmastop(dev) + struct sbic_softc *dev; +{ +/* printf("asc_dmastop\n");*/ +#if 0 + volatile struct sdmac *sdp; + int s; + + sdp = dev->sc_cregs; + +#ifdef DEBUG + if (ahsc_dmadebug & DDB_FOLLOW) + printf("ahsc_dmastop()\n"); +#endif + if (dev->sc_dmacmd) { + s = splbio(); + if ((dev->sc_dmacmd & (CNTR_TCEN | CNTR_DDIR)) == 0) { + /* + * only FLUSH if terminal count not enabled, + * and reading from peripheral + */ + sdp->FLUSH = 1; + while ((sdp->ISTR & ISTR_FE_FLG) == 0) + ; + } + /* + * clear possible interrupt and stop dma + */ + sdp->CINT = 1; + sdp->SP_DMA = 1; + dev->sc_dmacmd = 0; + splx(s); + } +#endif +} + +int +asc_dmaintr(dev) + struct sbic_softc *dev; +{ + panic("asc_dmaintr"); +#if 0 + volatile struct sdmac *sdp; + int stat, found; + + sdp = dev->sc_cregs; + stat = sdp->ISTR; + + if ((stat & (ISTR_INT_F|ISTR_INT_P)) == 0) + return (0); + +#ifdef DEBUG + if (ahsc_dmadebug & DDB_FOLLOW) + printf("%s: dmaintr 0x%x\n", dev->sc_dev.dv_xname, stat); +#endif + + /* + * both, SCSI and DMA interrupts arrive here. I chose + * arbitrarily that DMA interrupts should have higher + * precedence than SCSI interrupts. + */ + found = 0; + if (stat & ISTR_E_INT) { + ++found; + + sdp->CINT = 1; /* clear possible interrupt */ + + /* + * check for SCSI ints in the same go and + * eventually save an interrupt + */ + } + + if (dev->sc_flags & SBICF_INTR && stat & ISTR_INTS) + found += sbicintr(dev); + return(found); +#endif +} + + +int +asc_dmanext(dev) + struct sbic_softc *dev; +{ + printf("asc_dmanext\n"); + Debugger(); +#if 0 + volatile struct sdmac *sdp; + int i, stat; + + sdp = dev->sc_cregs; + + if (dev->sc_cur > dev->sc_last) { + /* shouldn't happen !! */ + printf("ahsc_dmanext at end !!!\n"); + asc_dmastop(dev); + return(0); + } + if ((dev->sc_dmacmd & (CNTR_TCEN | CNTR_DDIR)) == 0) { + /* + * only FLUSH if terminal count not enabled, + * and reading from peripheral + */ + sdp->FLUSH = 1; + while ((sdp->ISTR & ISTR_FE_FLG) == 0) + ; + } + /* + * clear possible interrupt and stop dma + */ + sdp->CINT = 1; /* clear possible interrupt */ + sdp->SP_DMA = 1; /* stop dma */ + sdp->CNTR = dev->sc_dmacmd; + sdp->ACR = (u_int)dev->sc_cur->dc_addr; + sdp->ST_DMA = 1; + + dev->sc_tcnt = dev->sc_cur->dc_count << 1; + return(dev->sc_tcnt); +#endif +} + +#ifdef DEBUG +void +asc_dump() +{ + int i; + + for (i = 0; i < ahsccd.cd_ndevs; ++i) + if (ahsccd.cd_devs[i]) + sbic_dump(ahsccd.cd_devs[i]); +} +#endif + +int +asc_scsicmd(xs) + struct scsi_xfer *xs; +{ + struct scsi_link *sc_link = xs->sc_link; + + /* ensure command is polling for the moment */ +#if ASC_POLL > 0 + if (asc_poll) + xs->flags |= SCSI_POLL; +#endif + +/* printf("id=%d lun=%dcmdlen=%d datalen=%d opcode=%02x flags=%08x status=%02x blk=%02x %02x\n", + sc_link->target, sc_link->lun, xs->cmdlen, xs->datalen, xs->cmd->opcode, + xs->flags, xs->status, xs->cmd->bytes[0], xs->cmd->bytes[1]);*/ + + return(sbic_scsicmd(xs)); +} + + +int +asc_intr(sc) + struct asc_softc *sc; +{ + int intr; + +/* printf("ascintr:");*/ + intr = ReadByte(sc->sc_intstat); +/* printf("%02x\n", intr);*/ + + if (intr & IS_SBIC_IRQ) + sbicintr((struct sbic_softc *)sc); + return(0); +} + + +int kvtop() +{ + Debugger(); + return(0); +} + +void alloc_z2mem() +{ + panic("allocz2mem"); +} + +void isztwomem() +{ + panic("isz2mem"); +} + +void PREP_DMA_MEM() +{ + panic("PREP_DMA_MEM"); +} diff --git a/sys/arch/arm32/podulebus/ascreg.h b/sys/arch/arm32/podulebus/ascreg.h new file mode 100644 index 00000000000..dba455eb84a --- /dev/null +++ b/sys/arch/arm32/podulebus/ascreg.h @@ -0,0 +1,279 @@ +/* $NetBSD: ascreg.h,v 1.4 1996/03/07 23:54:29 mark Exp $ */ + +/* + * Copyright (c) 1996 Mark Brinicombe + * Copyright (c) 1994 Christian E. Hopps + * Copyright (c) 1982, 1990 The Regents of the University of California. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * from:ahscreg.h,v 1.2 1994/10/26 02:02:46 + */ + +#ifndef _ASCREG_H_ +#define _ASCREG_H_ + +/* + * Hardware layout of the A3000 SDMAC. This also contains the + * registers for the sbic chip, but in favor of separating DMA and + * scsi, the scsi-driver doesn't make use of this dependency + */ + +#define v_char volatile char +#define v_int volatile int +#define vu_char volatile u_char +#define vu_short volatile u_short +#define vu_int volatile u_int + +struct sdmac { + short pad0; + vu_short DAWR; /* DACK Width Register WO */ + vu_int WTC; /* Word Transfer Count Register RW */ + short pad1; + vu_short CNTR; /* Control Register RW */ + vu_int ACR; /* Address Count Register RW */ + short pad2; + vu_short ST_DMA; /* Start DMA Transfers RW-Strobe */ + short pad3; + vu_short FLUSH; /* Flush FIFO RW-Strobe */ + short pad4; + vu_short CINT; /* Clear Interrupts RW-Strobe */ + short pad5; + vu_short ISTR; /* Interrupt Status Register RO */ + int pad6[7]; + short pad7; + vu_short SP_DMA; /* Stop DMA Transfers RW-Strobe */ + char pad8; + vu_char SASR; /* sbic asr */ + char pad9; + vu_char SCMD; /* sbic data */ +}; + +/* + * value to go into DAWR + */ +#define DAWR_AHSC 3 /* according to A3000T service-manual */ + +/* + * bits defined for CNTR + */ +#define CNTR_TCEN (1<<5) /* Terminal Count Enable */ +#define CNTR_PREST (1<<4) /* Perp Reset (not implemented :-((( ) */ +#define CNTR_PDMD (1<<3) /* Perp Device Mode Select (1=SCSI,0=XT/AT) */ +#define CNTR_INTEN (1<<2) /* Interrupt Enable */ +#define CNTR_DDIR (1<<1) /* Device Direction. 1==rd host, wr perp */ +#define CNTR_IO_DX (1<<0) /* IORDY & CSX1 Polarity Select */ + +/* + * bits defined for ISTR + */ +#define ISTR_INTX (1<<8) /* XT/AT Interrupt pending */ +#define ISTR_INT_F (1<<7) /* Interrupt Follow */ +#define ISTR_INTS (1<<6) /* SCSI Peripheral Interrupt */ +#define ISTR_E_INT (1<<5) /* End-Of-Process Interrupt */ +#define ISTR_INT_P (1<<4) /* Interrupt Pending */ +#define ISTR_UE_INT (1<<3) /* Under-Run FIFO Error Interrupt */ +#define ISTR_OE_INT (1<<2) /* Over-Run FIFO Error Interrupt */ +#define ISTR_FF_FLG (1<<1) /* FIFO-Full Flag */ +#define ISTR_FE_FLG (1<<0) /* FIFO-Empty Flag */ + +#define DMAGO_READ 0x01 + + +/* Addresses relative to podule base */ + +#define ASC_INTSTATUS 0x2000 +#define ASC_CLRINT 0x2000 +#define ASC_PAGEREG 0x3000 + +/* Addresses relative to module base */ + +#define ASC_DMAC 0x3000 +#define ASC_SBIC 0x2000 +#define ASC_SRAM 0x0000 + +#define ASC_SRAM_BLKSIZE 0x1000 + +#define IS_IRQREQ 0x01 +#define IS_DMAC_IRQ 0x02 +#define IS_SBIC_IRQ 0x08 + +#if 0 +/* SBIC Commands */ + +#define SBIC_CMD_Reset 0x00 /* Reset the SBIC */ +#define SBIC_Abort 0x01 /* Abort command */ +#define SBIC_Sel_tx_wATN 0x08 /* Select and Transfer with ATN */ +#define SBIC_Sel_tx_woATN 0x09 /* Select and Transfer without ATN */ + +/* SBIC status codes */ + +#define SBIC_ResetOk 0x00 +#define SBIC_ResetAFOk 0x01 + +/* SBIC registers bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 */ + +#define SBIC_OWNID 0x00 /* RW FS1 FS0 0 EHP EAF ID2 ID1 ID0 */ +#define SBIC_CONTROL 0x01 /* RW DM2 DM1 DM0 HHP EDI IDI HA HSP */ +#define SBIC_TIMEREG 0x02 /* RW timeout period value = Tper*Ficlk/80d */ +#define SBIC_CDB1TSECT 0x03 /* RW CDB byte 1 & Total sectors per track */ +#define SBIC_CDB2THEAD 0x04 /* RW CDB byte 2 & Total number of heads */ +#define SBIC_CDB3TCYL1 0x05 /* RW CDB byte 3 & Total no. of cylinders MSB */ +#define SBIC_CDB4TCYL2 0x06 /* RW CDB byte 4 & Total no. of cylinders LSB */ +#define SBIC_CDB5LADR1 0x07 /* RW CDB byte 5 & Logical addr to translate */ +#define SBIC_CBD6LADR2 0x08 /* RW CDB byte 6 & Logical addr to translate */ +#define SBIC_CDB7LADR3 0x09 /* RW CDB byte 7 & Logical addr to translate */ +#define SBIC_CDB8LADR4 0x0A /* RW CDB byte 8 & Logical addr to translate */ +#define SBIC_CDB9SECT 0x0B /* RW CDB byte 9 & Translation sector result */ +#define SBIC_CDB10HEAD 0x0C /* RW CDB byte 10 & Translation head result */ +#define SBIC_CDB11CYL1 0x0D /* RW CDB byte 11 & Translation cyl result MSB*/ +#define SBIC_CDB12CYL2 0x0E /* RW CDB byte 12 & Translation cyl result LSB*/ +#define SBIC_TARGETLUN 0x0F /* RW TLV DOK 0 0 0 TL2 TL1 TL0 */ +#define SBIC_COMPHASE 0x10 /* RW Command Phase Register for multi-phase */ +#define SBIC_SYNCTX 0x11 /* RW 0 TP2 TP1 TP0 OF3 OF2 OF1 OF0 */ +#define SBIC_TXCOUNT1 0x12 /* RW Transfer count MSB */ +#define SBIC_TXCOUNT2 0x13 /* RW Transfer count */ +#define SBIC_TXCOUNT3 0x14 /* RW Transfer count LSB */ +#define SBIC_DESTID 0x15 /* RW SCC DPD 0 0 0 DI2 DI1 DI0 */ +#define SBIC_SOURCEID 0x16 /* RW ER ES DSP 0 SIV SI2 SI1 SI0 */ +#define SBIC_SCSISTAT 0x17 /* RO **Interrupt type*** **Int. qualifier** */ +#define SBIC_COMMAND 0x18 /* RW SBT *********Command code************* */ +#define SBIC_DATA 0x19 /* RW Access to data i/o FIFO for polled use */ + +#define SBIC_ADDRREG 0x00 +#define SBIC_DATAREG 0x04 +#define SBIC_AUX_STATUS 0x00 + +/* + * My ID register, and/or CDB Size + */ + +#define SBIC_ID_FS_8_10 0x00 /* Input clock is 8-10 Mhz */ + /* 11 Mhz is invalid */ +#define SBIC_ID_FS_12_15 0x40 /* Input clock is 12-15 Mhz */ +#define SBIC_ID_FS_16_20 0x80 /* Input clock is 16-20 Mhz */ +#define SBIC_ID_EHP 0x10 /* Enable host parity */ +#define SBIC_ID_EAF 0x08 /* Enable Advanced Features */ +#define SBIC_ID_MASK 0x07 +#define SBIC_ID_CBDSIZE_MASK 0x0f /* if unk SCSI cmd group */ + +/* + * Control register +*/ + +#define SBIC_CTL_DMA 0x80 /* Single byte dma */ +#define SBIC_CTL_DBA_DMA 0x40 /* direct buffer acces (bus master)*/ +#define SBIC_CTL_BURST_DMA 0x20 /* continuous mode (8237) */ +#define SBIC_CTL_NO_DMA 0x00 /* Programmed I/O */ +#define SBIC_CTL_HHP 0x10 /* Halt on host parity error */ +#define SBIC_CTL_EDI 0x08 /* Ending disconnect interrupt */ +#define SBIC_CTL_IDI 0x04 /* Intermediate disconnect interrupt*/ +#define SBIC_CTL_HA 0x02 /* Halt on ATN */ +#define SBIC_CTL_HSP 0x01 /* Halt on SCSI parity error */ + +/* + * Destination ID register + */ + +#define SBIC_DID_DPD 0x40 /* Data Phase Direction */ + +/* + * Auxiliary Status Register + */ + +#define SBIC_ASR_INT 0x80 /* Interrupt pending */ +#define SBIC_ASR_LCI 0x40 /* Last command ignored */ +#define SBIC_ASR_BSY 0x20 /* Busy, only cmd/data/asr readable */ +#define SBIC_ASR_CIP 0x10 /* Busy, cmd unavail also */ +#define SBIC_ASR_xxx 0x0c +#define SBIC_ASR_PE 0x02 /* Parity error (even) */ +#define SBIC_ASR_DBR 0x01 /* Data Buffer Ready */ + +/* DMAC constants */ + +#define DMAC_Bits 0x01 +#define DMAC_Ctrl1 0x60 +#define DMAC_Ctrl2 0x01 +#define DMAC_CLEAR_MASK 0x0E +#define DMAC_SET_MASK 0x0F +#define DMAC_DMA_RD_MODE 0x04 +#define DMAC_DMA_WR_MODE 0x08 + +/* DMAC registers */ + +#define DMAC_INITIALISE 0x0000 /* WO ---- ---- ---- ---- ---- ---- 16B RES */ +#define DMAC_CHANNEL 0x0200 /* R ---- ---- ---- BASE SEL3 SEL2 SEL1 SEL0 */ + /* W ---- ---- ---- ---- ---- BASE *SELECT** */ +#define DMAC_TXCNTLO 0x0004 /* RW C7 C6 C5 C4 C3 C2 C1 C0 */ +#define DMAC_TXCNTHI 0x0204 /* RW C15 C14 C13 C12 C11 C10 C9 C8 */ +#define DMAC_TXADRLO 0x0008 /* RW A7 A6 A5 A4 A3 A2 A1 A0 */ +#define DMAC_TXADRMD 0x0208 /* RW A15 A14 A13 A12 A11 A10 A9 A8 */ +#define DMAC_TXADRHI 0x000C /* RW A23 A22 A21 A20 A19 A18 A17 A16 */ +#define DMAC_DEVCON1 0x0010 /* RW AKL RQL EXW ROT CMP DDMA AHLD MTM */ +#define DMAC_DEVCON2 0x0210 /* RW ---- ---- ---- ---- ---- ---- WEV BHLD */ +#define DMAC_MODECON 0x0014 /* RW **TMODE** ADIR AUTI **TDIR*** ---- WORD */ +#define DMAC_STATUS 0x0214 /* RO RQ3 RQ2 RQ1 RQ0 TC3 TC2 TC1 TC0 */ +#if 0 +templo = dmac + 0x0018;/* RO T7 T6 T5 T4 T3 T2 T1 T0 */ +temphi = dmac + 0x0218;/* RO T15 T14 T13 T12 T11 T10 T9 T8 */ +#endif +#define DMAC_REQREG 0x001C /* RW ---- ---- ---- ---- SRQ3 SRQ2 SRQ1 SRQ0 */ +#define DMAC_MASKREG 0x021C /* RW ---- ---- ---- ---- M3 M2 M1 M0 */ + +#ifndef _LOCORE +#define WriteSBIC(a, d) \ + WriteByte(sbic_base + SBIC_ADDRREG, a); \ + WriteByte(sbic_base + SBIC_DATAREG, d); + +/* +#define ReadSBIC(a) \ + (WriteByte(sbic_base, a), ReadWord(sbic_base + 4) & 0xff) +*/ +#define ReadSBIC(a) \ + ReadSBIC1(sbic_base, a) + + +static inline int +ReadSBIC1(sbic_base, a) + u_int sbic_base; + int a; +{ + WriteByte(sbic_base + SBIC_ADDRREG, a); + return(ReadByte(sbic_base + SBIC_DATAREG)); +} + + +#define WriteDMAC(a, d) WriteByte(dmac_base + a, d) +#define ReadDMAC(a) ReadByte(dmac_base + a) +#endif + + +#endif +#endif /* _ASCREG_H_ */ diff --git a/sys/arch/arm32/podulebus/ascvar.h b/sys/arch/arm32/podulebus/ascvar.h new file mode 100644 index 00000000000..a722f2f05dc --- /dev/null +++ b/sys/arch/arm32/podulebus/ascvar.h @@ -0,0 +1,52 @@ +/* $NetBSD: ascvar.h,v 1.1 1996/03/07 23:54:31 mark Exp $ */ + +/* + * Copyright (c) 1996 Mark Brinicombe + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Mark Brinicombe + * for the NetBSD Project. + * 4. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _ASCVAR_H_ +#define _ASCVAR_H_ + +#include <arm32/podulebus/sbicvar.h> +#include <arm32/podulebus/ascreg.h> + +#define ASC_POLL 1 + +struct asc_softc { + struct sbic_softc sc_softc; + + podule_t *sc_podule; + int sc_podule_number; + irqhandler_t sc_ih; + + vu_int sc_pagereg; + vu_int sc_intstat; + }; + +#endif /* _ASCVAR_H_ */ |
