diff options
| author | jakllsch <jakllsch@NetBSD.org> | 2010-07-23 02:23:58 +0000 |
|---|---|---|
| committer | jakllsch <jakllsch@NetBSD.org> | 2010-07-23 02:23:58 +0000 |
| commit | 1bccaf8fad4fb85bdbd2b2f6fa0fcf623a5be799 (patch) | |
| tree | 4bd97b7783affbf4b04f548094c3b60aa1369afc /sys | |
| parent | e7eb790b7b9fe63b1db5fbd25d900a39c9300cfa (diff) | |
Finish cleaning up pchb from recent change.
Use fewer magic numbers in ichlpcib.
Slightly improve style conformance.
Update paths in cpp re-inclusion guards.
Diffstat (limited to 'sys')
| -rw-r--r-- | sys/arch/x86/pci/ichlpcib.c | 18 | ||||
| -rw-r--r-- | sys/arch/x86/pci/pchbvar.h | 14 | ||||
| -rw-r--r-- | sys/dev/ic/i82801lpcreg.h | 12 |
3 files changed, 21 insertions, 23 deletions
diff --git a/sys/arch/x86/pci/ichlpcib.c b/sys/arch/x86/pci/ichlpcib.c index 8245b6b5d4f..f41bafdf289 100644 --- a/sys/arch/x86/pci/ichlpcib.c +++ b/sys/arch/x86/pci/ichlpcib.c @@ -1,4 +1,4 @@ -/* $NetBSD: ichlpcib.c,v 1.25 2010/07/23 00:43:21 jakllsch Exp $ */ +/* $NetBSD: ichlpcib.c,v 1.26 2010/07/23 02:23:58 jakllsch Exp $ */ /*- * Copyright (c) 2004 The NetBSD Foundation, Inc. @@ -39,7 +39,7 @@ */ #include <sys/cdefs.h> -__KERNEL_RCSID(0, "$NetBSD: ichlpcib.c,v 1.25 2010/07/23 00:43:21 jakllsch Exp $"); +__KERNEL_RCSID(0, "$NetBSD: ichlpcib.c,v 1.26 2010/07/23 02:23:58 jakllsch Exp $"); #include <sys/types.h> #include <sys/param.h> @@ -1241,10 +1241,11 @@ lpcib_gpio_pin_ctl(void *arg, int pin, int flags) static void lpcib_fwh_configure(device_t self) { - struct lpcib_softc *sc = device_private(self); - + struct lpcib_softc *sc; pcireg_t pr; + sc = device_private(self); + if (sc->sc_has_rcba) { /* * Very unlikely to find a 82802 on a ICH6 or newer. @@ -1254,15 +1255,16 @@ lpcib_fwh_configure(device_t self) } else { /* Enable FWH write to identify FWH. */ pr = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, - 0x4c); + LPCIB_PCI_BIOS_CNTL); pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, - 0x4c, pr|__BIT(16)); + LPCIB_PCI_BIOS_CNTL, pr|LPCIB_PCI_BIOS_CNTL_BWE); } sc->sc_fwhbus = config_found_ia(self, "fwhichbus", NULL, NULL); - /* disable write */ - pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 0x4c, pr); + /* restore previous write enable setting */ + pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, + LPCIB_PCI_BIOS_CNTL, pr); } static int diff --git a/sys/arch/x86/pci/pchbvar.h b/sys/arch/x86/pci/pchbvar.h index 1c3656c242d..4ff12dd7a5c 100644 --- a/sys/arch/x86/pci/pchbvar.h +++ b/sys/arch/x86/pci/pchbvar.h @@ -1,4 +1,4 @@ -/* $NetBSD: pchbvar.h,v 1.6 2010/07/23 00:43:21 jakllsch Exp $ */ +/* $NetBSD: pchbvar.h,v 1.7 2010/07/23 02:23:58 jakllsch Exp $ */ /*- * Copyright (c) 2000 The NetBSD Foundation, Inc. @@ -29,11 +29,8 @@ * POSSIBILITY OF SUCH DAMAGE. */ -#ifndef _I386_PCI_PCHBVAR_H_ -#define _I386_PCI_PCHBVAR_H_ - -#include <sys/callout.h> -#include <sys/rnd.h> +#ifndef _X86_PCI_PCHBVAR_H_ +#define _X86_PCI_PCHBVAR_H_ struct pchb_softc { device_t sc_dev; @@ -44,7 +41,4 @@ struct pchb_softc { pcireg_t sc_pciconfext[48]; }; -void pchb_attach_rnd(struct pchb_softc *, struct pci_attach_args *); -void pchb_detach_rnd(struct pchb_softc *); - -#endif /* _I386_PCI_PCHBVAR_H_ */ +#endif /* _X86_PCI_PCHBVAR_H_ */ diff --git a/sys/dev/ic/i82801lpcreg.h b/sys/dev/ic/i82801lpcreg.h index 3f0e13ba609..f80505d7d9b 100644 --- a/sys/dev/ic/i82801lpcreg.h +++ b/sys/dev/ic/i82801lpcreg.h @@ -1,4 +1,4 @@ -/* $NetBSD: i82801lpcreg.h,v 1.10 2009/09/27 17:55:32 jakllsch Exp $ */ +/* $NetBSD: i82801lpcreg.h,v 1.11 2010/07/23 02:23:58 jakllsch Exp $ */ /*- * Copyright (c) 2004 The NetBSD Foundation, Inc. @@ -34,8 +34,8 @@ * register definitions. */ -#ifndef _DEV_IC_I82801LPGREG_H_ -#define _DEV_IC_I82801LPGREG_H_ +#ifndef _DEV_IC_I82801LPCREG_H_ +#define _DEV_IC_I82801LPCREG_H_ /* * PCI configuration registers */ @@ -45,7 +45,9 @@ /* GPIO config registers ICH6+ */ #define LPCIB_PCI_GPIO_BASE_ICH6 0x48 #define LPCIB_PCI_GPIO_CNTL_ICH6 0x4c -#define LPCIB_PCI_BIOS_CNTL 0x4e +#define LPCIB_PCI_BIOS_CNTL 0x4c /* actually 0x4e */ +#define LPCIB_PCI_BIOS_CNTL_BWE (0x0001 << 16) /* write enable */ +#define LPCIB_PCI_BIOS_CNTL_BLE (0x0002 << 16) /* lock enable */ #define LPCIB_PCI_TCO_CNTL 0x54 /* GPIO config registers ICH0-ICH5 */ #define LPCIB_PCI_GPIO_BASE 0x58 @@ -297,4 +299,4 @@ lpcib_tcotimer_second_to_tick(int ltick) #define LPCIB_TCOTIMER_MAX_TICK 0x3f /* 39 seconds max */ #define LPCIB_TCOTIMER2_MAX_TICK 0x265 /* 613 seconds max */ -#endif /* _DEV_IC_I82801LPGREG_H_ */ +#endif /* _DEV_IC_I82801LPCREG_H_ */ |
