diff options
| author | mycroft <mycroft@NetBSD.org> | 1999-03-27 09:41:03 +0000 |
|---|---|---|
| committer | mycroft <mycroft@NetBSD.org> | 1999-03-27 09:41:03 +0000 |
| commit | a1784400cd63ace82112ea3bb2599fb06fd273bf (patch) | |
| tree | 8346f9e75ffff874de250f486c88c8a1c443b7b7 /sys | |
| parent | 11f0bebf2b08f461e62cec152490f71b6ff43e2d (diff) | |
GC PT_Us, add more DIAGNOSTIC checks.
Diffstat (limited to 'sys')
| -rw-r--r-- | sys/arch/arm32/arm32/pmap.c | 81 | ||||
| -rw-r--r-- | sys/arch/arm32/include/pte.h | 10 |
2 files changed, 49 insertions, 42 deletions
diff --git a/sys/arch/arm32/arm32/pmap.c b/sys/arch/arm32/arm32/pmap.c index 5118ee91431..3a3c7c272ca 100644 --- a/sys/arch/arm32/arm32/pmap.c +++ b/sys/arch/arm32/arm32/pmap.c @@ -1,4 +1,4 @@ -/* $NetBSD: pmap.c,v 1.51 1999/03/27 05:57:03 mycroft Exp $ */ +/* $NetBSD: pmap.c,v 1.52 1999/03/27 09:41:03 mycroft Exp $ */ /* * Copyright (c) 1994-1998 Mark Brinicombe. @@ -1954,6 +1954,13 @@ pmap_enter(pmap, va, pa, prot, wired, access_type) panic("pmap_enter: too big"); if (va >= VM_MAXUSER_ADDRESS && va < VM_MAX_ADDRESS) panic("pmap_enter: entering PT page"); + if (pmap != pmap_kernel() && va != 0) { + if (va < VM_MIN_ADDRESS || va >= VM_MAXUSER_ADDRESS) + panic("pmap_enter: kernel page in user map"); + } else { + if (va >= VM_MIN_ADDRESS && va < VM_MAXUSER_ADDRESS) + panic("pmap_enter: user page in kernel map"); + } #endif /* @@ -2008,8 +2015,6 @@ pmap_enter(pmap, va, pa, prot, wired, access_type) flags = 0; if (prot & VM_PROT_WRITE) flags |= PT_Wr; - if (va >= VM_MIN_ADDRESS && va < VM_MAXUSER_ADDRESS) - flags |= PT_Us; if (wired) flags |= PT_W; @@ -2036,7 +2041,7 @@ pmap_enter(pmap, va, pa, prot, wired, access_type) if ((bank = vm_physseg_find(atop(pa), &off)) != -1) { pv = &vm_physmem[bank].pmseg.pvent[off]; (void) pmap_modify_pv(pmap, va, pv, - PT_Wr | PT_Us | PT_W, flags); + PT_Wr | PT_W, flags); } } else { /* We are replacing the page with a new one. */ @@ -2077,10 +2082,11 @@ pmap_enter(pmap, va, pa, prot, wired, access_type) printf("pmap_enter: pmap=%p va=%lx pa=%lx opa=%lx bank=%d off=%d pv=%p\n", pmap, va, pa, opa, bank, off, pv); #endif - /* Construct the pte, giving the correct access */ + /* Construct the pte, giving the correct access. */ npte = (pa & PG_FRAME); - if (flags & PT_Us) + /* VA 0 is magic. */ + if (pmap != pmap_kernel() && va != 0) npte |= PT_AP(AP_U); if (bank != -1) { @@ -2428,9 +2434,8 @@ pmap_testbit(pa, setbits) */ void -pmap_changebit(pa, setbits, maskbits) +pmap_clearbit(pa, maskbits) vm_offset_t pa; - int setbits; int maskbits; { struct pv_entry *pv; @@ -2439,8 +2444,8 @@ pmap_changebit(pa, setbits, maskbits) int bank, off; int s; - PDEBUG(1, printf("pmap_changebit: pa=%08lx set=%08x mask=%08x\n", - pa, setbits, maskbits)); + PDEBUG(1, printf("pmap_clearbit: pa=%08lx mask=%08x\n", + pa, maskbits)); if ((bank = vm_physseg_find(atop(pa), &off)) == -1) return; pv = &vm_physmem[bank].pmseg.pvent[off]; @@ -2449,35 +2454,36 @@ pmap_changebit(pa, setbits, maskbits) /* * Clear saved attributes (modify, reference) */ - if (maskbits) - vm_physmem[bank].pmseg.attrs[off] &= ~maskbits; + vm_physmem[bank].pmseg.attrs[off] &= ~maskbits; + + if (pv->pv_pmap == NULL) { + splx(s); + return; + } /* * Loop over all current mappings setting/clearing as appropos */ - if (pv->pv_pmap != NULL) { - for (; pv; pv = pv->pv_next) { - va = pv->pv_va; - - /* - * XXX don't write protect pager mappings - */ - if (maskbits & (PT_Wr|PT_M|PT_H)) { - if (va >= uvm.pager_sva && va < uvm.pager_eva) - continue; - } + for (; pv; pv = pv->pv_next) { + va = pv->pv_va; - pv->pv_flags = (pv->pv_flags & ~maskbits) | setbits; - pte = pmap_pte(pv->pv_pmap, va); - if (maskbits & (PT_Wr|PT_M)) - *pte = (*pte) & ~PT_AP(AP_W); - if (setbits & PT_Wr) - *pte = (*pte) | PT_AP(AP_W); - if (maskbits & PT_H) - *pte = ((*pte) & ~L2_MASK) | L2_INVAL; + /* + * XXX don't write protect pager mappings + */ + if (va >= uvm.pager_sva && va < uvm.pager_eva) { + printf("pmap_clearbit: bogon alpha\n"); + continue; } - cpu_tlb_flushID(); + + pv->pv_flags &= ~maskbits; + pte = pmap_pte(pv->pv_pmap, va); + if (maskbits & (PT_Wr|PT_M)) + *pte = *pte & ~PT_AP(AP_W); + if (maskbits & PT_H) + *pte = (*pte & ~L2_MASK) | L2_INVAL; } + cpu_tlb_flushID(); + splx(s); } @@ -2487,7 +2493,7 @@ pmap_clear_modify(pa) vm_offset_t pa; { PDEBUG(0, printf("pmap_clear_modify pa=%08lx\n", pa)); - pmap_changebit(pa, 0, PT_M); + pmap_clearbit(pa, PT_M); } @@ -2496,7 +2502,7 @@ pmap_clear_reference(pa) vm_offset_t pa; { PDEBUG(0, printf("pmap_clear_reference pa=%08lx\n", pa)); - pmap_changebit(pa, 0, PT_H); + pmap_clearbit(pa, PT_H); } @@ -2505,9 +2511,10 @@ pmap_copy_on_write(pa) vm_offset_t pa; { PDEBUG(0, printf("pmap_copy_on_write pa=%08lx\n", pa)); - pmap_changebit(pa, 0, PT_Wr); + pmap_clearbit(pa, PT_Wr); } + boolean_t pmap_is_modified(pa) vm_offset_t pa; @@ -2516,7 +2523,7 @@ pmap_is_modified(pa) result = pmap_testbit(pa, PT_M); PDEBUG(0, printf("pmap_is_modified pa=%08lx %x\n", pa, result)); - return(result); + return (result); } @@ -2528,7 +2535,7 @@ pmap_is_referenced(pa) result = pmap_testbit(pa, PT_H); PDEBUG(0, printf("pmap_is_referenced pa=%08lx %x\n", pa, result)); - return(result); + return (result); } diff --git a/sys/arch/arm32/include/pte.h b/sys/arch/arm32/include/pte.h index deb26420e22..4aa8f96a529 100644 --- a/sys/arch/arm32/include/pte.h +++ b/sys/arch/arm32/include/pte.h @@ -1,4 +1,4 @@ -/* $NetBSD: pte.h,v 1.8 1998/08/30 23:15:14 mark Exp $ */ +/* $NetBSD: pte.h,v 1.9 1999/03/27 09:41:04 mycroft Exp $ */ /* * Copyright (c) 1994 Mark Brinicombe. @@ -76,12 +76,12 @@ typedef int pt_entry_t; /* page table entry */ #define PT_CACHEABLE (PT_B | PT_C) -/* Virtual bits in a pte (maintained in software) */ +/* Page R/M attributes (in pmseg.attrs). */ #define PT_M 0x01 /* Virt - Modified */ #define PT_H 0x02 /* Virt - Handled (Used) */ -#define PT_W 0x40 /* Virt - Wired */ -#define PT_Wr 0x10 /* Virt / Phys Write */ -#define PT_Us 0x20 /* Virt / Phys User */ +/* Mapping wired/writeable attributes (in pv_flags). */ +#define PT_W 0x04 /* Virt - Wired */ +#define PT_Wr 0x08 /* Virt / Phys Write */ /* access permissions for L2 pages (all sub pages have the same perms) */ #define PT_AP(x) ((x << 10) | (x << 8) | (x << 6) | (x << 4)) |
