diff options
| author | tsutsui <tsutsui@NetBSD.org> | 2007-06-08 15:44:34 +0000 |
|---|---|---|
| committer | tsutsui <tsutsui@NetBSD.org> | 2007-06-08 15:44:34 +0000 |
| commit | dadbb85281dfb7dc046611cfa55fc418ed40c792 (patch) | |
| tree | b3a2be11fa93871530c4b4acd869c7dacae73790 /sys | |
| parent | 792b0b87002c857b04eb01dda042c3c706d14904 (diff) | |
DCFA(), DCPA(), ICPL(), ICPP(), DCPL(), DCPP, DCFL(), and DCFP()
cache ops are identical between M68040 and M68060 and they are not
available on M68020 and M68030, so no need to check cputype even on
multi CPU kernels and they can always be inlined.
This improves MI Sonic xfer speed ~5%.
http://mail-index.netbsd.org/port-mac68k/2007/06/07/0003.html
Diffstat (limited to 'sys')
| -rw-r--r-- | sys/arch/m68k/include/cacheops.h | 44 | ||||
| -rw-r--r-- | sys/arch/m68k/include/cacheops_60.h | 76 | ||||
| -rw-r--r-- | sys/arch/m68k/m68k/cacheops.c | 157 |
3 files changed, 30 insertions, 247 deletions
diff --git a/sys/arch/m68k/include/cacheops.h b/sys/arch/m68k/include/cacheops.h index 67149e291cf..09f51ce464b 100644 --- a/sys/arch/m68k/include/cacheops.h +++ b/sys/arch/m68k/include/cacheops.h @@ -1,4 +1,4 @@ -/* $NetBSD: cacheops.h,v 1.11 2005/12/11 12:17:53 christos Exp $ */ +/* $NetBSD: cacheops.h,v 1.12 2007/06/08 15:44:34 tsutsui Exp $ */ /*- * Copyright (c) 1997 The NetBSD Foundation, Inc. @@ -83,20 +83,12 @@ #elif defined(M68040) -#define DCFA() DCFA_40() -#define DCFL(pa) DCFL_40((pa)) -#define DCFP(pa) DCFP_40((pa)) #define DCIA() DCIA_40() #define DCIAS(pa) DCIAS_40((pa)) #define DCIS() DCIS_40() #define DCIU() DCIU_40() -#define DCPA() DCPA_40() -#define DCPL(pa) DCPL_40((pa)) -#define DCPP(pa) DCPP_40((pa)) #define ICIA() ICIA_40() #define ICPA() ICPA_40() -#define ICPL(pa) ICPL_40((pa)) -#define ICPP(pa) ICPP_40((pa)) #define PCIA() PCIA_40() #define TBIA() TBIA_40() #define TBIAS() TBIAS_40() @@ -129,20 +121,12 @@ #else /* M68K_CACHEOPS_NTYPES == 1 */ -#define DCFA() _DCFA() -#define DCFL(pa) _DCFL((pa)) -#define DCFP(pa) _DCFP((pa)) #define DCIA() _DCIA() #define DCIAS(pa) _DCIAS((pa)) #define DCIS() _DCIS() #define DCIU() _DCIU() -#define DCPA() _DCPA() -#define DCPL(pa) _DCPL((pa)) -#define DCPP(pa) _DCPP((pa)) #define ICIA() _ICIA() #define ICPA() _ICPA() -#define ICPL(pa) _ICPL((pa)) -#define ICPP(pa) _ICPP((pa)) #define PCIA() _PCIA() #define TBIA() _TBIA() #define TBIAS() _TBIAS() @@ -151,24 +135,34 @@ #endif /* M68K_CACHEOPS_NTYPES == 1 */ -void _DCFA(void); -void _DCFL(paddr_t); -void _DCFP(paddr_t); void _DCIA(void); void _DCIAS(paddr_t); void _DCIS(void); void _DCIU(void); -void _DCPA(void); -void _DCPL(paddr_t); -void _DCPP(paddr_t); void _ICIA(void); void _ICPA(void); -void _ICPL(paddr_t); -void _ICPP(paddr_t); void _PCIA(void); void _TBIA(void); void _TBIAS(void); void _TBIAU(void); void _TBIS(vaddr_t); + +#if defined(M68040) || defined(M68060) + +/* + * These cache ops are identical between M68040 and M68060 + * and not available on M68020 and M68030 so no need to check cputype. + */ +#define DCFA() DCFA_40() +#define DCPA() DCPA_40() +#define ICPL(pa) ICPL_40(pa) +#define ICPP(pa) ICPP_40(pa) +#define DCPL(pa) DCPL_40(pa) +#define DCPP(pa) DCPP_40(pa) +#define DCFL(pa) DCFL_40(pa) +#define DCFP(pa) DCFP_40(pa) + +#endif + #endif /* _M68K_CACHEOPS_H_ */ diff --git a/sys/arch/m68k/include/cacheops_60.h b/sys/arch/m68k/include/cacheops_60.h index 4b2f66166b6..6e245ce55ad 100644 --- a/sys/arch/m68k/include/cacheops_60.h +++ b/sys/arch/m68k/include/cacheops_60.h @@ -1,4 +1,4 @@ -/* $NetBSD: cacheops_60.h,v 1.7 2006/02/16 20:17:13 perry Exp $ */ +/* $NetBSD: cacheops_60.h,v 1.8 2007/06/08 15:44:34 tsutsui Exp $ */ /*- * Copyright (c) 1997 The NetBSD Foundation, Inc. @@ -156,69 +156,11 @@ PCIA_60(void) __asm volatile (" .word 0xf478;"); /* cpusha dc */ } -static __inline void __attribute__((__unused__)) -DCFA_60(void) -{ - __asm volatile (" .word 0xf478;"); /* cpusha dc */ -} - -/* invalidate instruction physical cache line */ -static __inline void __attribute__((__unused__)) -ICPL_60(paddr_t pa) -{ - register paddr_t r_pa __asm("%a0") = pa; - - __asm volatile (" .word 0xf488;" : : "a" (r_pa)); /* cinvl ic,%a0@ */ -} - -/* invalidate instruction physical cache page */ -static __inline void __attribute__((__unused__)) -ICPP_60(paddr_t pa) -{ - register paddr_t r_pa __asm("%a0") = pa; - - __asm volatile (" .word 0xf490;" : : "a" (r_pa)); /* cinvp ic,%a0@ */ -} - -/* invalidate data physical cache line */ -static __inline void __attribute__((__unused__)) -DCPL_60(paddr_t pa) -{ - register paddr_t r_pa __asm("%a0") = pa; - - __asm volatile (" .word 0xf448;" : : "a" (r_pa)); /* cinvl dc,%a0@ */ -} - -/* invalidate data physical cache page */ -static __inline void __attribute__((__unused__)) -DCPP_60(paddr_t pa) -{ - register paddr_t r_pa __asm("%a0") = pa; - - __asm volatile (" .word 0xf450;" : : "a" (r_pa)); /* cinvp dc,%a0@ */ -} - -/* invalidate data physical all */ -static __inline void __attribute__((__unused__)) -DCPA_60(void) -{ - __asm volatile (" .word 0xf458;"); /* cinva dc */ -} - -/* data cache flush line */ -static __inline void __attribute__((__unused__)) -DCFL_60(paddr_t pa) -{ - register paddr_t r_pa __asm("%a0") = pa; - - __asm volatile (" .word 0xf468;" : : "a" (r_pa)); /* cpushl dc,%a0@ */ -} - -/* data cache flush page */ -static __inline void __attribute__((__unused__)) -DCFP_60(paddr_t pa) -{ - register paddr_t r_pa __asm("%a0") = pa; - - __asm volatile (" .word 0xf470;" : : "a" (r_pa)); /* cpushp dc,%a0@ */ -} +#define DCFA_60() DCFA_40() +#define DCPA_60() DCPA_40() +#define ICPL_60(pa) ICPL_40(pa) +#define ICPP_60(pa) ICPP_40(pa) +#define DCPL_60(pa) DCPL_40(pa) +#define DCPP_60(pa) DCPP_40(pa) +#define DCFL_60(pa) DCFL_40(pa) +#define DCFP_60(pa) DCFP_40(pa) diff --git a/sys/arch/m68k/m68k/cacheops.c b/sys/arch/m68k/m68k/cacheops.c index d7848c0a575..ed940486e60 100644 --- a/sys/arch/m68k/m68k/cacheops.c +++ b/sys/arch/m68k/m68k/cacheops.c @@ -1,4 +1,4 @@ -/* $NetBSD: cacheops.c,v 1.11 2006/07/22 06:36:06 tsutsui Exp $ */ +/* $NetBSD: cacheops.c,v 1.12 2007/06/08 15:44:35 tsutsui Exp $ */ /*- * Copyright (c) 1997 The NetBSD Foundation, Inc. @@ -37,7 +37,7 @@ */ #include <sys/cdefs.h> -__KERNEL_RCSID(0, "$NetBSD: cacheops.c,v 1.11 2006/07/22 06:36:06 tsutsui Exp $"); +__KERNEL_RCSID(0, "$NetBSD: cacheops.c,v 1.12 2007/06/08 15:44:35 tsutsui Exp $"); #include <sys/types.h> #include <machine/cpu.h> @@ -404,156 +404,3 @@ _DCIAS(paddr_t pa) #endif } } - -#if defined(M68040) || defined(M68060) -void -_DCFA(void) -{ - - switch (cputype) { -#ifdef M68040 - case CPU_68040: - DCFA_40(); - break; -#endif -#ifdef M68060 - case CPU_68060: - DCFA_60(); - break; -#endif - } -} - -void -_DCPA(void) -{ - - switch (cputype) { - default: -#ifdef M68040 - case CPU_68040: - DCPA_40(); - break; -#endif -#ifdef M68060 - case CPU_68060: - DCPA_60(); - break; -#endif - } -} - -void -_ICPL(paddr_t pa) -{ - - switch (cputype) { - default: -#ifdef M68040 - case CPU_68040: - ICPL_40(pa); - break; -#endif -#ifdef M68060 - case CPU_68060: - ICPL_60(pa); - break; -#endif - } -} - -void -_ICPP(paddr_t pa) -{ - - switch (cputype) { - default: -#ifdef M68040 - case CPU_68040: - ICPP_40(pa); - break; -#endif -#ifdef M68060 - case CPU_68060: - ICPP_60(pa); - break; -#endif - } -} - -void -_DCPL(paddr_t pa) -{ - - switch (cputype) { - default: -#ifdef M68040 - case CPU_68040: - DCPL_40(pa); - break; -#endif -#ifdef M68060 - case CPU_68060: - DCPL_60(pa); - break; -#endif - } -} - -void -_DCPP(paddr_t pa) -{ - - switch (cputype) { - default: -#ifdef M68040 - case CPU_68040: - DCPP_40(pa); - break; -#endif -#ifdef M68060 - case CPU_68060: - DCPP_60(pa); - break; -#endif - } -} - -void -_DCFL(paddr_t pa) -{ - - switch (cputype) { - default: -#ifdef M68040 - case CPU_68040: - DCFL_40(pa); - break; -#endif -#ifdef M68060 - case CPU_68060: - DCFL_60(pa); - break; -#endif - } -} - -void -_DCFP(paddr_t pa) -{ - - switch (cputype) { - default: -#ifdef M68040 - case CPU_68040: - DCFP_40(pa); - break; -#endif -#ifdef M68060 - case CPU_68060: - DCFP_60(pa); - break; -#endif - } -} -#endif /* M68040 || M68060 */ |
