diff options
| author | mgorny <mgorny@NetBSD.org> | 2020-10-24 07:14:29 +0000 |
|---|---|---|
| committer | mgorny <mgorny@NetBSD.org> | 2020-10-24 07:14:29 +0000 |
| commit | d1c7a51dbc4495f09e6fd121b6ec87ce7fb76fbc (patch) | |
| tree | 9a33b11bda02f97ed347c9f3a465839d50864730 /tests/lib/libc/sys | |
| parent | dbc8789c7a28eacf97f6bfc082d7cbe9061a6bd3 (diff) | |
Issue 64-bit versions of *XSAVE* for 64-bit amd64 programs
When calling FXSAVE, XSAVE, FXRSTOR, ... for 64-bit programs on amd64
use the 64-suffixed variant in order to include the complete FIP/FDP
registers in the x87 area.
The difference between the two variants is that the FXSAVE64 (new)
variant represents FIP/FDP as 64-bit fields (union fp_addr.fa_64),
while the legacy FXSAVE variant uses split fields: 32-bit offset,
16-bit segment and 16-bit reserved field (union fp_addr.fa_32).
The latter implies that the actual addresses are truncated to 32 bits
which is insufficient in modern programs.
The change is applied only to 64-bit programs on amd64. Plain i386
and compat32 continue using plain FXSAVE. Similarly, NVMM is not
changed as I am not familiar with that code.
This is a potentially breaking change. However, I don't think it likely
to actually break anything because the data provided by the old variant
were not meaningful (because of the truncated pointer).
Diffstat (limited to 'tests/lib/libc/sys')
| -rw-r--r-- | tests/lib/libc/sys/t_ptrace_x86_wait.h | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/tests/lib/libc/sys/t_ptrace_x86_wait.h b/tests/lib/libc/sys/t_ptrace_x86_wait.h index 94758bea055..303a9b0d729 100644 --- a/tests/lib/libc/sys/t_ptrace_x86_wait.h +++ b/tests/lib/libc/sys/t_ptrace_x86_wait.h @@ -1,4 +1,4 @@ -/* $NetBSD: t_ptrace_x86_wait.h,v 1.29 2020/10/16 08:51:12 mgorny Exp $ */ +/* $NetBSD: t_ptrace_x86_wait.h,v 1.30 2020/10/24 07:14:30 mgorny Exp $ */ /*- * Copyright (c) 2016, 2017, 2018, 2019 The NetBSD Foundation, Inc. @@ -3387,12 +3387,10 @@ x86_register_test(enum x86_test_regset regset, enum x86_test_registers regs, ATF_CHECK_EQ(fxs->fx_opcode, expected_fpu.opcode); #if defined(__x86_64__) -#if 0 /* TODO: kernel needs patching to call *XSAVE64 */ ATF_CHECK_EQ(fxs->fx_ip.fa_64, ((uint64_t)gpr.regs[_REG_RIP]) - 3); ATF_CHECK_EQ(fxs->fx_dp.fa_64, (uint64_t)&x86_test_zero); -#endif #else ATF_CHECK_EQ(fxs->fx_ip.fa_32.fa_off, (uint32_t)gpr.r_eip - 3); |
