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authormartin <martin@NetBSD.org>2021-12-08 15:44:16 +0000
committermartin <martin@NetBSD.org>2021-12-08 15:44:16 +0000
commitffca8cf2c8cf3ef5c67f208265d20c117ce2872b (patch)
tree38e9ccc96d431f4f0d49007e4b3c3685a6f46710 /usr.sbin
parentbef619f5c745f259dc3444b0382b3b402540f510 (diff)
Pull up the following revisions, requested by msaitoh in ticket #1391:
sys/arch/x86/include/specialreg.h 1.171, 1.173-1.178 sys/arch/x86/x86/identcpu.c 1.106, 1.117, 1.122 via patch sys/dev/nvmm/x86/nvmm_x86.c 1.18 sys/external/bsd/drm2/drm/drm_cache.c 1.14 sys/external/bsd/drm2/include/asm/cpufeature.h 1.5 usr.sbin/cpuctl/arch/i386.c 1.114-1.117 - Add LA57, PKE, PKS, CET, CET_U, CET_S, HWP, KL, AVX512_BF16, TME_EN and PCONFIG. - Rename some macros to match the x86 specification and the other OSes. - Print CPUID 0x8000008 %ebx on Intel, too. - Print CPUID leaf 7 subleaf 1. - Identify Tiger Lake, 3rd gen Xeon Scalable (Ice Lake), Elkhart Lake and Jasper Lake. - Add comment. - KNF. Whitespace fix.
Diffstat (limited to 'usr.sbin')
-rw-r--r--usr.sbin/cpuctl/arch/i386.c26
1 files changed, 18 insertions, 8 deletions
diff --git a/usr.sbin/cpuctl/arch/i386.c b/usr.sbin/cpuctl/arch/i386.c
index b75bdb0ea92..7a03a99ea1b 100644
--- a/usr.sbin/cpuctl/arch/i386.c
+++ b/usr.sbin/cpuctl/arch/i386.c
@@ -1,4 +1,4 @@
-/* $NetBSD: i386.c,v 1.104.2.7 2021/11/22 17:05:32 martin Exp $ */
+/* $NetBSD: i386.c,v 1.104.2.8 2021/12/08 15:44:16 martin Exp $ */
/*-
* Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
#include <sys/cdefs.h>
#ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.104.2.7 2021/11/22 17:05:32 martin Exp $");
+__RCSID("$NetBSD: i386.c,v 1.104.2.8 2021/12/08 15:44:16 martin Exp $");
#endif /* not lint */
#include <sys/types.h>
@@ -344,14 +344,18 @@ const struct cpu_cpuid_nameclass i386_cpuid_cpus[] = {
[0x5e] = "6th gen Core, Xeon E3-1[25]00 v5 (Skylake)",
[0x5f] = "Atom (Goldmont, Denverton)",
[0x66] = "8th gen Core i3 (Cannon Lake)",
- [0x6a] = "Future Xeon (Ice Lake)",
- [0x6c] = "Future Xeon (Ice Lake)",
+ [0x6a] = "3rd gen Xeon Scalable (Ice Lake)",
+ [0x6c] = "3rd gen Xeon Scalable (Ice Lake)",
[0x7a] = "Atom (Goldmont Plus)",
[0x7d] = "10th gen Core (Ice Lake)",
[0x7e] = "10th gen Core (Ice Lake)",
[0x85] = "Xeon Phi 7215, 7285, 7295 (Knights Mill)",
[0x86] = "Atom (Tremont)",
+ [0x8c] = "11th gen Core (Tiger Lake)",
+ [0x8d] = "11th gen Core (Tiger Lake)",
[0x8e] = "7th or 8th gen Core (Kaby Lake, Coffee Lake) or Xeon E (Coffee Lake)",
+ [0x96] = "Atom x6000E (Elkhart Lake)",
+ [0x9c] = "Pentium Silver N6xxx, Celeron N45xx, Celeron N51xx (Jasper Lake)",
[0x9e] = "7th or 8th gen Core (Kaby Lake, Coffee Lake) or Xeon E (Coffee Lake)",
[0xa5] = "10th gen Core (Comet Lake)",
[0xa6] = "10th gen Core (Comet Lake)",
@@ -1627,7 +1631,7 @@ cpu_probe_base_features(struct cpu_info *ci, const char *cpuname)
* If the processor serial number misfeature is present and supported,
* extract it here.
*/
- if ((ci->ci_feat_val[0] & CPUID_PN) != 0) {
+ if ((ci->ci_feat_val[0] & CPUID_PSN) != 0) {
ci->ci_cpu_serial[0] = ci->ci_signature;
x86_cpuid(3, descs);
ci->ci_cpu_serial[2] = descs[2];
@@ -2183,7 +2187,7 @@ identifycpu(int fd, const char *cpuname)
x86_print_cache_and_tlb_info(ci);
- if (ci->ci_max_cpuid >= 3 && (ci->ci_feat_val[0] & CPUID_PN)) {
+ if (ci->ci_max_cpuid >= 3 && (ci->ci_feat_val[0] & CPUID_PSN)) {
aprint_verbose("%s: serial number %04X-%04X-%04X-%04X-%04X-%04X\n",
cpuname,
ci->ci_cpu_serial[0] / 65536, ci->ci_cpu_serial[0] % 65536,
@@ -2250,19 +2254,25 @@ identifycpu(int fd, const char *cpuname)
x86_cpuid(7, descs);
aprint_verbose("%s: SEF highest subleaf %08x\n",
cpuname, descs[0]);
+ if (descs[0] >= 1) {
+ x86_cpuid2(7, 1, descs);
+ print_bits(cpuname, "SEF-subleaf1-eax",
+ CPUID_SEF1_FLAGS_A, descs[0]);
+ }
}
- if ((cpu_vendor == CPUVENDOR_INTEL) || (cpu_vendor == CPUVENDOR_AMD))
+ if ((cpu_vendor == CPUVENDOR_INTEL) || (cpu_vendor == CPUVENDOR_AMD)) {
if (ci->ci_max_ext_cpuid >= 0x80000007)
powernow_probe(ci);
- if (cpu_vendor == CPUVENDOR_AMD) {
if (ci->ci_max_ext_cpuid >= 0x80000008) {
x86_cpuid(0x80000008, descs);
print_bits(cpuname, "AMD Extended features",
CPUID_CAPEX_FLAGS, descs[1]);
}
+ }
+ if (cpu_vendor == CPUVENDOR_AMD) {
if ((ci->ci_max_ext_cpuid >= 0x8000000a)
&& (ci->ci_feat_val[3] & CPUID_SVM) != 0) {
x86_cpuid(0x8000000a, descs);