diff options
Diffstat (limited to 'external/gpl3/binutils/dist/include/opcode/ChangeLog')
| -rw-r--r-- | external/gpl3/binutils/dist/include/opcode/ChangeLog | 901 |
1 files changed, 846 insertions, 55 deletions
diff --git a/external/gpl3/binutils/dist/include/opcode/ChangeLog b/external/gpl3/binutils/dist/include/opcode/ChangeLog index cb9f60f335f..0aee1949909 100644 --- a/external/gpl3/binutils/dist/include/opcode/ChangeLog +++ b/external/gpl3/binutils/dist/include/opcode/ChangeLog @@ -1,40 +1,825 @@ -2013-02-12 Yufeng Zhang <yufeng.zhang@arm.com> +2015-12-15 Matthew Wahab <matthew.wahab@arm.com> + + * aarch64.h (enum aarch64_opnd_qualifier): Add + AARCH64_OPND_QLF_V_2H. + +2015-12-14 Matthew Wahab <matthew.wahab@arm.com> + + * aarch64.h (aarch64_opnd): Add AARCH64_OPND_BARRIER_PSB. + * aarch64-asm-2.c: Regenerate. + * aarch64-dis-2.c: Regenerate. + * aarch64-opc-2.c: Regenerate. + * aarch64-opc.c (aarch64_hint_options): Add "csync". + (aarch64_print_operands): Handle AARCH64_OPND_BARRIER_PSB. + * aarch64-tbl.h (aarch64_feature_stat_profile): New. + (STAT_PROFILE): New. + (aarch64_opcode_table): Add "psb". + (AARCH64_OPERANDS): Add "BARRIER_PSB". + +2015-12-14 Matthew Wahab <matthew.wahab@arm.com> + + * aarch64.h (aarch64_hint_options): Declare. + (aarch64_opnd_info): Add field hint_option. + +2015-12-14 Matthew Wahab <matthew.wahab@arm.com> + + * aarch64.h (AARCH64_FEATURE_PROFILE): New. + +2015-12-14 Matthew Wahab <matthew.wahab@arm.com> + + * aarch64.h (aarch64_sys_ins_reg_supported_p): Declare. + +2015-12-14 Matthew Wahab <matthew.wahab@arm.com> + + * aarch64.h (aarch64_sys_ins_reg): Replace has_xt with flags. + (aarch64_sys_ins_reg_has_xt): Declare. + +2015-12-14 Matthew Wahab <matthew.wahab@arm.com> + + * aarch64.h (AARCH64_FEATURE_RAS): New. + (AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_RAS. + +2015-12-14 Matthew Wahab <matthew.wahab@arm.com> + + * aarch64.h (AARCH64_FEATURE_F16): Fix clash with + AARCH64_FEATURE_V8_1. + (AARCH64_ARCH_V8_1): Add AARCH64_FEATURE_CRC. + (AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_CRC and + AARCH64_FEATURE_V8_1. + +2015-12-14 Matthew Wahab <matthew.wahab@arm.com> + + * aarch64.h (AARCH64_FEATURE_F16): New. + (AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_F16 to ARMv8.2 + features. + +2015-12-14 Matthew Wahab <matthew.wahab@arm.com> + + * aarch64.h (aarch64_op): Add OP_BFC. + +2015-12-09 Matthew Wahab <matthew.wahab@arm.com> + + * aarch64.h (AARCH64_FEATURE_V8_2): New. + (AARCH64_ARCH_V8_2): New. + +2015-12-08 Matthew Wahab <matthew.wahab@arm.com> + + * aarch64.h (AARCH64_FEATURE_V8_1): New. + (AARCH64_ARCH_v8_1): Add AARCH64_FEATURE_V8_1. + +2015-11-11 Alan Modra <amodra@gmail.com> + Peter Bergner <bergner@vnet.ibm.com> + + * ppc.h (PPC_OPCODE_POWER9): New define. + (PPC_OPCODE_VSX3): Likewise. + +2015-11-02 Nick Clifton <nickc@redhat.com> + + * rx.h (enum RX_Opcode_ID): Add more NOP opcodes. + +2015-11-02 Nick Clifton <nickc@redhat.com> + + * rx.h (enum RX_Operand_Type): Add RX_Operand_Zero_Indirect. + +2015-10-28 Yao Qi <yao.qi@linaro.org> + + * aarch64.h (aarch64_decode_insn): Update declaration. + +2015-10-07 Yao Qi <yao.qi@linaro.org> + + * aarch64.h (aarch64_sys_ins_reg) <template>: Removed. + <name>: New field. + +2015-10-07 Yao Qi <yao.qi@linaro.org> + + * aarch64.h [__cplusplus]: Wrap in extern "C". + +2015-10-07 Claudiu Zissulescu <claziss@synopsys.com> + Cupertino Miranda <cmiranda@synopsys.com> + + * arc-func.h: New file. + * arc.h: Likewise. + +2015-10-02 Yao Qi <yao.qi@linaro.org> + + * aarch64.h (aarch64_zero_register_p): Move the declaration + to column one. + +2015-10-02 Yao Qi <yao.qi@linaro.org> + + * aarch64.h (aarch64_decode_insn): Declare it. + +2015-09-29 Dominik Vogt <vogt@linux.vnet.ibm.com> + + * s390.h (S390_INSTR_FLAG_HTM): New flag. + (S390_INSTR_FLAG_VX): New flag. + (S390_INSTR_FLAG_FACILITY_MASK): New flag mask. + +2015-09-23 Nick Clifton <nickc@redhat.com> + + * ppc.h (PPC_OPSHIFT_INV): Use an unsigned constant when left + shifting. + +2015-09-22 Nick Clifton <nickc@redhat.com> + + * rx.h (enum RX_Size): Add RX_Bad_Size entry. + +2015-09-09 Daniel Santos <daniel.santos@pobox.com> + + * visium.h (gen_reg_table): Make static. + (fp_reg_table): Likewise. + (cc_table): Likewise. + +2015-07-20 Matthew Wahab <matthew.wahab@arm.com> + + * arm.h (ARM_AEXT_V6ZK): Rename to ARM_AEXT_V6KZ. + (ARM_AEXT_V6ZKT2): Rename to ARM_AEXT_V6KZT2. + (ARM_ARCH_V6ZK): Rename to ARM_ARCH_V6KZ. + (ARM_ARCH_V6ZKT2): Rename to ARM_ARCH_V6KZT2. + +2015-07-03 Alan Modra <amodra@gmail.com> + + * ppc.h (PPC_OPCODE_750, PPC_OPCODE_7450, PPC_OPCODE_860): Define. + +2015-07-01 Sandra Loosemore <sandra@codesourcery.com> + Cesar Philippidis <cesar@codesourcery.com> + + * nios2.h (enum iw_format_type): Add R2 formats. + (enum overflow_type): Add signed_immed12_overflow and + enumeration_overflow for R2. + (struct nios2_opcode): Document new argument letters for R2. + (REG_3BIT, REG_LDWM, REG_POP): Define. + (includes): Include nios2r2.h. + (nios2_r2_opcodes, nios2_num_r2_opcodes): Declare. + (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): Declare. + (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): Declare. + (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): Declare. + (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): Declare. + (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): + Declare. + * nios2r2.h: New file. + +2015-06-19 Peter Bergner <bergner@vnet.ibm.com> + + * ppc.h (PPC_OPERAND_OPTIONAL_VALUE): New. + (ppc_optional_operand_value): New inline function. + +2015-06-04 Matthew Wahab <matthew.wahab@arm.com> + + * aarch64.h (AARCH64_V8_1): New. + +2015-06-03 Matthew Wahab <matthew.wahab@arm.com> + + * arm.h (FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1): New. + (ARM_ARCH_V8_1A): New. + (ARM_ARCH_V8_1A_FP): New. + (ARM_ARCH_V8_1A_SIMD): New. + (ARM_ARCH_V8_1A_CRYPTOV1): New. + (ARM_FEATURE_CORE): New. + +2015-06-02 Matthew Wahab <matthew.wahab@arm.com> + + * arm.h (ARM_EXT2_PAN): New. + (ARM_FEATURE_CORE_HIGH): New. + +2015-06-02 Matthew Wahab <matthew.wahab@arm.com> + + * arm.h (ARM_FEATURE_ALL): New. + +2015-06-02 Matthew Wahab <matthew.wahab@arm.com> + + * aarch64.h (AARCH64_FEATURE_RDMA): New. + +2015-06-02 Matthew Wahab <matthew.wahab@arm.com> + + * aarch64.h (AARCH64_FEATURE_LOR): New. + +2015-06-01 Matthew Wahab <matthew.wahab@arm.com> + + * aarch64.h (AARCH64_FEATURE_PAN): New. + (aarch64_sys_reg_supported_p): Declare. + (aarch64_pstatefield_supported_p): Declare. + +2015-04-30 DJ Delorie <dj@redhat.com> + + * rl78.h (RL78_Dis_Isa): New. + (rl78_decode_opcode): Add ISA parameter. + +2015-03-24 Terry Guo <terry.guo@arm.com> + + * arm.h (arm_feature_set): Extended to provide more available bits. + (ARM_ANY): Updated to follow above new definition. + (ARM_CPU_HAS_FEATURE): Likewise. + (ARM_CPU_IS_ANY): Likewise. + (ARM_MERGE_FEATURE_SETS): Likewise. + (ARM_CLEAR_FEATURE): Likewise. + (ARM_FEATURE): Likewise. + (ARM_FEATURE_COPY): New macro. + (ARM_FEATURE_EQUAL): Likewise. + (ARM_FEATURE_ZERO): Likewise. + (ARM_FEATURE_CORE_EQUAL): Likewise. + (ARM_FEATURE_LOW): Likewise. + (ARM_FEATURE_CORE_LOW): Likewise. + (ARM_FEATURE_CORE_COPROC): Likewise. + +2015-02-19 Pedro Alves <palves@redhat.com> + + * cgen.h [__cplusplus]: Wrap in extern "C". + * msp430-decode.h [__cplusplus]: Likewise. + * nios2.h [__cplusplus]: Likewise. + * rl78.h [__cplusplus]: Likewise. + * rx.h [__cplusplus]: Likewise. + * tilegx.h [__cplusplus]: Likewise. + +2015-01-28 James Bowman <james.bowman@ftdichip.com> + + * ft32.h: New file. + +2015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com> + + * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_Z13. + +2015-01-01 Alan Modra <amodra@gmail.com> + + Update year range in copyright notice of all files. + +2014-12-27 Anthony Green <green@moxielogic.com> + + * moxie.h (MOXIE_F1_AiB2, MOXIE_F1_ABi2): Renamed from + MOXIE_F1_AiB4 and MOXIE_F1_ABi2. + +2014-12-06 Eric Botcazou <ebotcazou@adacore.com> + + * visium.h: New file. + +2014-11-28 Sandra Loosemore <sandra@codesourcery.com> + + * nios2.h (NIOS2_INSN_ADDI, NIOS2_INSN_ANDI): Delete. + (NIOS2_INSN_ORI, NIOS2_INSN_XORI): Delete. + (NIOS2_INSN_OPTARG): Renumber. + +2014-11-06 Sandra Loosemore <sandra@codesourcery.com> + + * nios2.h (nios2_find_opcode_hash): Add mach parameter to + declaration. Fix obsolete comment. + +2014-10-23 Sandra Loosemore <sandra@codesourcery.com> + + * nios2.h (enum iw_format_type): New. + (struct nios2_opcode): Update comments. Add size and format fields. + (NIOS2_INSN_OPTARG): New. + (REG_NORMAL, REG_CONTROL, REG_COPROCESSOR): New. + (struct nios2_reg): Add regtype field. + (GET_INSN_FIELD, SET_INSN_FIELD): Delete. + (IW_A_LSB, IW_A_MSB, IW_A_SZ, IW_A_MASK): Delete. + (IW_B_LSB, IW_B_MSB, IW_B_SZ, IW_B_MASK): Delete. + (IW_C_LSB, IW_C_MSB, IW_C_SZ, IW_C_MASK): Delete. + (IW_IMM16_LSB, IW_IMM16_MSB, IW_IMM16_SZ, IW_IMM16_MASK): Delete. + (IW_IMM26_LSB, IW_IMM26_MSB, IW_IMM26_SZ, IW_IMM26_MASK): Delete. + (IW_OP_LSB, IW_OP_MSB, IW_OP_SZ, IW_OP_MASK): Delete. + (IW_OPX_LSB, IW_OPX_MSB, IW_OPX_SZ, IW_OPX_MASK): Delete. + (IW_SHIFT_IMM5_LSB, IW_SHIFT_IMM5_MSB): Delete. + (IW_SHIFT_IMM5_SZ, IW_SHIFT_IMM5_MASK): Delete. + (IW_CONTROL_REGNUM_LSB, IW_CONTROL_REGNUM_MSB): Delete. + (IW_CONTROL_REGNUM_SZ, IW_CONTROL_REGNUM_MASK): Delete. + (OP_MASK_OP, OP_SH_OP): Delete. + (OP_MASK_IOP, OP_SH_IOP): Delete. + (OP_MASK_IRD, OP_SH_IRD): Delete. + (OP_MASK_IRT, OP_SH_IRT): Delete. + (OP_MASK_IRS, OP_SH_IRS): Delete. + (OP_MASK_ROP, OP_SH_ROP): Delete. + (OP_MASK_RRD, OP_SH_RRD): Delete. + (OP_MASK_RRT, OP_SH_RRT): Delete. + (OP_MASK_RRS, OP_SH_RRS): Delete. + (OP_MASK_JOP, OP_SH_JOP): Delete. + (OP_MASK_IMM26, OP_SH_IMM26): Delete. + (OP_MASK_RCTL, OP_SH_RCTL): Delete. + (OP_MASK_IMM5, OP_SH_IMM5): Delete. + (OP_MASK_CACHE_OPX, OP_SH_CACHE_OPX): Delete. + (OP_MASK_CACHE_RRS, OP_SH_CACHE_RRS): Delete. + (OP_MASK_CUSTOM_A, OP_SH_CUSTOM_A): Delete. + (OP_MASK_CUSTOM_B, OP_SH_CUSTOM_B): Delete. + (OP_MASK_CUSTOM_C, OP_SH_CUSTOM_C): Delete. + (OP_MASK_CUSTOM_N, OP_SH_CUSTOM_N): Delete. + (OP_<insn>, OPX_<insn>, OP_MATCH_<insn>, OPX_MATCH_<insn>): Delete. + (OP_MASK_<insn>, OP_MASK): Delete. + (GET_IW_A, GET_IW_B, GET_IW_C, GET_IW_CONTROL_REGNUM): Delete. + (GET_IW_IMM16, GET_IW_IMM26, GET_IW_OP, GET_IW_OPX): Delete. + Include nios2r1.h to define new instruction opcode constants + and accessors. + (nios2_builtin_opcodes): Rename to nios2_r1_opcodes. + (bfd_nios2_num_builtin_opcodes): Rename to nios2_num_r1_opcodes. + (bfd_nios2_num_opcodes): Rename to nios2_num_opcodes. + (NUMOPCODES, NUMREGISTERS): Delete. + * nios2r1.h: New file. + +2014-10-17 Jose E. Marchesi <jose.marchesi@oracle.com> + + * sparc.h (HWCAP2_VIS3B): Documentation improved. + +2014-10-09 Jose E. Marchesi <jose.marchesi@oracle.com> + + * sparc.h (sparc_opcode): new field `hwcaps2'. + (HWCAP2_FJATHPLUS): New define. + (HWCAP2_VIS3B): Likewise. + (HWCAP2_ADP): Likewise. + (HWCAP2_SPARC5): Likewise. + (HWCAP2_MWAIT): Likewise. + (HWCAP2_XMPMUL): Likewise. + (HWCAP2_XMONT): Likewise. + (HWCAP2_NSEC): Likewise. + (HWCAP2_FJATHHPC): Likewise. + (HWCAP2_FJDES): Likewise. + (HWCAP2_FJAES): Likewise. + Document the new operand kind `{', corresponding to the mcdper + ancillary state register. + Document the new operand kind }, which represents frsd floating + point registers (double precision) which must be the same than + frs1 in its containing instruction. + +2014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com> + + * nds32.h: Add new opcode declaration. + +2014-09-15 Andrew Bennett <andrew.bennett@imgtec.com> + Matthew Fortune <matthew.fortune@imgtec.com> + + * mips.h (mips_operand_type): Add new entries: OP_SAME_RS_RT, + OP_CHECK_PREV and OP_NON_ZERO_REG. Add descriptions for the MIPS R6 + instruction arguments: -a, -b, -d, -s, -t, -u, -v, -w, -x, -y, -A, -B, + +I, +O, +R, +:, +\, +", +; + (mips_check_prev_operand): New struct. + (INSN2_FORBIDDEN_SLOT): New define. + (INSN_ISA32R6): New define. + (INSN_ISA64R6): New define. + (INSN_UPTO32R6): New define. + (INSN_UPTO64R6): New define. + (mips_isa_table): Add INSN_UPTO32R6 and INSN_UPTO64R6. + (ISA_MIPS32R6): New define. + (ISA_MIPS64R6): New define. + (CPU_MIPS32R6): New define. + (CPU_MIPS64R6): New define. + (cpu_is_member): Add cases for CPU_MIPS32R6, and CPU_MIPS64R6. + +2014-09-03 Jiong Wang <jiong.wang@arm.com> + + * aarch64.h (AARCH64_FEATURE_LSE): New feature added. + (aarch64_opnd): Add AARCH64_OPND_PAIRREG. + (aarch64_insn_class): Add lse_atomic. + (F_LSE_SZ): New field added. + (opcode_has_special_coder): Recognize F_LSE_SZ. + +2014-08-26 Maciej W. Rozycki <macro@codesourcery.com> + + * mips.h: Document the move of `MICROMIPSOP_*_CODE10' from `B' + over to `+J'. + +2014-07-29 Matthew Fortune <matthew.fortune@imgtec.com> + + * mips.h (INSN_LOAD_COPROC_DELAY): Rename to... + (INSN_LOAD_COPROC): New define. + (INSN_COPROC_MOVE_DELAY): Rename to... + (INSN_COPROC_MOVE): New define. + +2014-07-01 Barney Stratford <barney_stratford@fastmail.fm> + Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com> + Pitchumani Sivanupandi <pitchumani.s@atmel.com> + Soundararajan <Sounderarajan.D@atmel.com> + + * avr.h (AVR_ISA_TINY): Define avrtiny specific ISA. + (AVR_ISA_2xxxa): Define ISA without LPM. + (AVR_ISA_AVRTINY): Define avrtiny arch ISA. + Add doc for contraint used in 16 bit lds/sts. + Adjust ISA group for icall, ijmp, pop and push. + Add 16 bit lds/sts encoding and update 32 bit lds/sts constraints. + +2014-05-19 Nick Clifton <nickc@redhat.com> + + * msp430.h (struct msp430_operand_s): Add vshift field. + +2014-05-07 Andrew Bennett <andrew.bennett@imgtec.com> + + * mips.h (INSN_ISA_MASK): Updated. + (INSN_ISA32R3): New define. + (INSN_ISA32R5): New define. + (INSN_ISA64R3): New define. + (INSN_ISA64R5): New define. + (INSN_ISA64, INSN_ISA64R2, INSN_ISA3_32, INSN_ISA3_32R2, INSN_ISA4_32 + INSN_ISA4_32R2, INSN_ISA5_32R2): Renumbered. + (mips_isa_table): Add entries for mips32r3, mips32r5, mips64r3 and + mips64r5. + (INSN_UPTO32R3): New define. + (INSN_UPTO32R5): New define. + (INSN_UPTO64R3): New define. + (INSN_UPTO64R5): New define. + (ISA_MIPS32R3): New define. + (ISA_MIPS32R5): New define. + (ISA_MIPS64R3): New define. + (ISA_MIPS64R5): New define. + (CPU_MIPS32R3): New define. + (CPU_MIPS32R5): New define. + (CPU_MIPS64R3): New define. + (CPU_MIPS64R5): New define. + +2014-05-01 Richard Sandiford <rdsandiford@googlemail.com> + + * mips.h (mips_isa_table): Avoid hard-coding INSN_ISA* values. + +2014-04-22 Christian Svensson <blue@cmd.nu> + + * or32.h: Delete. + +2014-03-05 Alan Modra <amodra@gmail.com> + + Update copyright years. + +2013-12-16 Andrew Bennett <andrew.bennett@imgtec.com> + + * mips.h: Updated description of +o, +u, +v and +w for MIPS and + microMIPS. + +2013-12-13 Kuan-Lin Chen <kuanlinchentw@gmail.com> + Wei-Cheng Wang <cole945@gmail.com> + + * nds32.h: New file for Andes NDS32. + +2013-12-07 Mike Frysinger <vapier@gentoo.org> + + * bfin.h: Remove +x file mode. + +2013-11-20 Yufeng Zhang <yufeng.zhang@arm.com> + + * aarch64.h (aarch64_pstatefields): Change element type to + aarch64_sys_reg. + +2013-11-18 Renlin Li <Renlin.Li@arm.com> + + * arm.h (ARM_AEXT_V7VE): New define. + (ARM_ARCH_V7VE): New define. + (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): Removed. + +2013-11-18 Yufeng Zhang <yufeng.zhang@arm.com> + + Revert + + 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com> + + * aarch64.h (aarch64_sys_reg_readonly_p): New declaration. + (aarch64_sys_reg_writeonly_p): Ditto. + +2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com> + + * aarch64.h (aarch64_sys_reg_readonly_p): New declaration. + (aarch64_sys_reg_writeonly_p): Ditto. + +2013-11-05 Yufeng Zhang <yufeng.zhang@arm.com> + + * aarch64.h (aarch64_sys_reg): New typedef. + (aarch64_sys_regs): Change to define with the new type. + (aarch64_sys_reg_deprecated_p): Declare. + +2013-11-05 Yufeng Zhang <yufeng.zhang@arm.com> + + * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND. + (enum aarch64_opnd): Add AARCH64_OPND_COND1. + +2013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com> + + * mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX. + (mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL. + For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w, + +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|. + For MIPS, update extension character sequences after +. + (ASE_MSA): New define. + (ASE_MSA64): New define. + For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w, + +x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|. + For microMIPS, update extension character sequences after +. + +2013-08-23 Yuri Chornoivan <yurchor@ukr.net> + + PR binutils/15834 + * i960.h: Fix typos. + +2013-08-19 Richard Sandiford <rdsandiford@googlemail.com> + + * mips.h: Remove references to "+I" and imm2_expr. + +2013-08-19 Richard Sandiford <rdsandiford@googlemail.com> + + * mips.h (M_DEXT, M_DINS): Delete. + +2013-08-19 Richard Sandiford <rdsandiford@googlemail.com> + + * mips.h (OP_OPTIONAL_REG): New mips_operand_type. + (mips_optional_operand_p): New function. + +2013-08-04 Jürgen Urban <JuergenUrban@gmx.de> + Richard Sandiford <rdsandiford@googlemail.com> + + * mips.h: Document new VU0 operand characters. + (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types. + (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R) + (OP_REG_R5900_ACC): New mips_reg_operand_types. + (INSN2_VU0_CHANNEL_SUFFIX): New macro. + (mips_vu0_channel_mask): Declare. + +2013-08-03 Richard Sandiford <rdsandiford@googlemail.com> + + * mips.h (mips_pcrel_operand): Inherit from mips_int_operand. + (mips_int_operand_min, mips_int_operand_max): New functions. + (mips_decode_pcrel_operand): Use mips_decode_int_operand. + +2013-08-01 Richard Sandiford <rdsandiford@googlemail.com> + + * mips.h (mips_decode_reg_operand): New function. + (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL) + (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4) + (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI): + New macros. + (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D) + (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T) + (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S) + (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z) + (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D) + (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD) + (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG) + (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP) + (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP) + (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other + macros to cover the gaps. + (INSN2_MOD_SP): Replace with... + (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros. + (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z) + (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y) + (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z) + (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X): + Delete. + +2013-08-01 Richard Sandiford <rdsandiford@googlemail.com> + + * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31) + (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH) + (MIPS16_INSN_COND_BRANCH): Delete. + +2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com> + Kirill Yukhin <kirill.yukhin@intel.com> + Michael Zolotukhin <michael.v.zolotukhin@intel.com> + + * i386.h (BND_PREFIX_OPCODE): New. + +2013-07-14 Richard Sandiford <rdsandiford@googlemail.com> + + * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and + OP_SAVE_RESTORE_LIST. + (decode_mips16_operand): Declare. + +2013-07-14 Richard Sandiford <rdsandiford@googlemail.com> + + * mips.h (mips_operand_type, mips_reg_operand_type): New enums. + (mips_operand, mips_int_operand, mips_mapped_int_operand) + (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand) + (mips_pcrel_operand): New structures. + (mips_insert_operand, mips_extract_operand, mips_signed_operand) + (mips_decode_int_operand, mips_decode_pcrel_operand): New functions. + (decode_mips_operand, decode_micromips_operand): Declare. + +2013-07-14 Richard Sandiford <rdsandiford@googlemail.com> + + * mips.h: Document MIPS16 "I" opcode. + +2013-07-07 Richard Sandiford <rdsandiford@googlemail.com> + + * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB) + (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB) + (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A) + (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB) + (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB) + (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB) + (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB) + (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB) + (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A) + (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A) + (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB) + (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete. + (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A): + Rename to... + (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB) + (M_USD_AB): ...these. + +2013-07-07 Richard Sandiford <rdsandiford@googlemail.com> + + * mips.h: Remove documentation of "[" and "]". Update documentation + of "k" and the MDMX formats. + +2013-07-07 Richard Sandiford <rdsandiford@googlemail.com> + + * mips.h: Update documentation of "+s" and "+S". + +2013-07-07 Richard Sandiford <rdsandiford@googlemail.com> + + * mips.h: Document "+i". + +2013-07-07 Richard Sandiford <rdsandiford@googlemail.com> + + * mips.h: Remove "mi" documentation. Update "mh" documentation. + (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI): + Delete. + (INSN2_WRITE_GPR_MHI): Rename to... + (INSN2_WRITE_GPR_MH): ...this. + +2013-07-07 Richard Sandiford <rdsandiford@googlemail.com> + + * mips.h: Remove documentation of "+D" and "+T". + +2013-06-26 Richard Sandiford <rdsandiford@googlemail.com> + + * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT. + Use "source" rather than "destination" for microMIPS "G". + +2013-06-25 Maciej W. Rozycki <macro@codesourcery.com> + + * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum + values. + +2013-06-23 Richard Sandiford <rdsandiford@googlemail.com> + + * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS. + +2013-06-17 Catherine Moore <clm@codesourcery.com> + Maciej W. Rozycki <macro@codesourcery.com> + Chao-Ying Fu <fu@mips.com> + + * mips.h (OP_SH_EVAOFFSET): Define. + (OP_MASK_EVAOFFSET): Define. + (INSN_ASE_MASK): Delete. + (ASE_EVA): Define. + (M_CACHEE_AB, M_CACHEE_OB): New. + (M_LBE_OB, M_LBE_AB): New. + (M_LBUE_OB, M_LBUE_AB): New. + (M_LHE_OB, M_LHE_AB): New. + (M_LHUE_OB, M_LHUE_AB): New. + (M_LLE_AB, M_LLE_OB): New. + (M_LWE_OB, M_LWE_AB): New. + (M_LWLE_AB, M_LWLE_OB): New. + (M_LWRE_AB, M_LWRE_OB): New. + (M_PREFE_AB, M_PREFE_OB): New. + (M_SCE_AB, M_SCE_OB): New. + (M_SBE_OB, M_SBE_AB): New. + (M_SHE_OB, M_SHE_AB): New. + (M_SWE_OB, M_SWE_AB): New. + (M_SWLE_AB, M_SWLE_OB): New. + (M_SWRE_AB, M_SWRE_OB): New. + (MICROMIPSOP_SH_EVAOFFSET): Define. + (MICROMIPSOP_MASK_EVAOFFSET): Define. + +2013-06-12 Sandra Loosemore <sandra@codesourcery.com> + + * nios2.h (OP_MATCH_ERET): Correct eret encoding. + +2013-05-22 Jürgen Urban <JuergenUrban@gmx.de> + + * mips.h (M_LQC2_AB, M_SQC2_AB): New macros. + +2013-05-09 Andrew Pinski <apinski@cavium.com> + + * mips.h (OP_MASK_CODE10): Correct definition. + (OP_SH_CODE10): Likewise. + Add a comment that "+J" is used now for OP_*CODE10. + (INSN_ASE_MASK): Update. + (INSN_VIRT): New macro. + (INSN_VIRT64): New macro + +2013-05-02 Nick Clifton <nickc@redhat.com> + + * msp430.h: Add patterns for MSP430X instructions. + +2013-04-06 David S. Miller <davem@davemloft.net> + + * sparc.h (F_PREFERRED): Define. + (F_PREF_ALIAS): Define. + +2013-04-03 Nick Clifton <nickc@redhat.com> + + * v850.h (V850_INVERSE_PCREL): Define. + +2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com> + + PR binutils/15068 + * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor. + +2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com> + + PR binutils/15068 + * tic6xc-insn-formats.h (FLD): Add use of bitfield array. + Add 16-bit opcodes. + * tic6xc-opcode-table.h: Add 16-bit insns. + * tic6x.h: Add support for 16-bit insns. + +2013-03-21 Michael Schewe <michael.schewe@gmx.net> + + * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd + and mov.b/w/l Rs,@(d:32,ERd). + +2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com> + + PR gas/15082 + * tic6x-opcode-table.h: Rename mpydp's specific operand type macro + from ORREGD1324 to ORXREGD1324 and make it cross-path-able through + tic6x_operand_xregpair operand coding type. + Make mpydp instruction cross-path-able, ie: remove the FIXed 'x' + opcode field, usu ORXREGD1324 for the src2 operand and remove the + TIC6X_FLAG_NO_CROSS. + +2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com> + + PR gas/15095 + * tic6x.h (enum tic6x_coding_method): Add + tic6x_coding_dreg_(msb|lsb) field coding type in order to encode + separately the msb and lsb of a register pair. This is needed to + encode the opcodes in the same way as TI assembler does. + * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp + and rsqrdp opcodes to use the new field coding types. + +2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com> + + * arm.h (CRC_EXT_ARMV8): New constant. + (ARCH_CRC_ARMV8): New macro. + +2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com> + + * aarch64.h (AARCH64_FEATURE_CRC): New macro. + +2013-02-06 Sandra Loosemore <sandra@codesourcery.com> + Andrew Jenner <andrew@codesourcery.com> + + Based on patches from Altera Corporation. + + * nios2.h: New file. + +2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com> * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2. -2013-01-22 Alan Modra <amodra@gmail.com> +2013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com> + + PR gas/15069 + * tic6x-opcode-table.h: Fix encoding of BNOP instruction. + +2013-01-24 Nick Clifton <nickc@redhat.com> + + * v850.h: Add e3v5 support. + +2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com> + + * aarch64.h (aarch64_op): Remove OP_V_MOVI_B. + +2013-01-10 Peter Bergner <bergner@vnet.ibm.com> + + * ppc.h (PPC_OPCODE_POWER8): New define. + (PPC_OPCODE_HTM): Likewise. + +2013-01-10 Will Newton <will.newton@imgtec.com> + + * metag.h: New file. + +2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com> + + * cr16.h (make_instruction): Rename to cr16_make_instruction. + (match_opcode): Rename to cr16_match_opcode. + +2013-01-04 Juergen Urban <JuergenUrban@gmx.de> + + * mips.h: Add support for r5900 instructions including lq and sq. + +2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com> + + * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c + (make_instruction,match_opcode): Added function prototypes. + (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern. + +2012-11-23 Alan Modra <amodra@gmail.com> - Apply mainline patches - 2012-11-23 Alan Modra <amodra@gmail.com> * ppc.h (ppc_parse_cpu): Update prototype. -2012-08-13 Richard Sandiford <rdsandiford@googlemail.com> - Maciej W. Rozycki <macro@codesourcery.com> +2012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> - * mips.h (mips_opcode): Add the exclusions field. - (OPCODE_IS_MEMBER): Remove macro. - (cpu_is_member): New inline function. - (opcode_is_member): Likewise. + * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx + opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes. -2012-07-31 Chao-Ying Fu <fu@mips.com> - Catherine Moore <clm@codesourcery.com> - Maciej W. Rozycki <macro@codesourcery.com> +2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> - * mips.h: Document microMIPS DSP ASE usage. - (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for - microMIPS DSP ASE support. - (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise. - (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise. - (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise. - (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise. - (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise. - (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise. - (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise. + * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12. 2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com> * ia64.h (ia64_opnd): Add new operand types. +2012-08-21 David S. Miller <davem@davemloft.net> + + * sparc.h (F3F4): New macro. + +2012-08-13 Ian Bolton <ian.bolton@arm.com> Laurent Desnogues <laurent.desnogues@arm.com> Jim MacArthur <jim.macarthur@arm.com> Marcus Shawcroft <marcus.shawcroft@arm.com> @@ -44,31 +829,31 @@ Sofiane Naci <sofiane.naci@arm.com> Tejas Belagod <tejas.belagod@arm.com> Yufeng Zhang <yufeng.zhang@arm.com> + + * aarch64.h: New file. + +2012-08-13 Richard Sandiford <rdsandiford@googlemail.com> Maciej W. Rozycki <macro@codesourcery.com> + + * mips.h (mips_opcode): Add the exclusions field. + (OPCODE_IS_MEMBER): Remove macro. + (cpu_is_member): New inline function. + (opcode_is_member): Likewise. + +2012-07-31 Chao-Ying Fu <fu@mips.com> Catherine Moore <clm@codesourcery.com> Maciej W. Rozycki <macro@codesourcery.com> - Adam Nemet <anemet@caviumnetworks.com> - Maciej W. Rozycki <macro@codesourcery.com> - Maciej W. Rozycki <macro@codesourcery.com> - (OPCODE_IS_MEMBER): Include R14000, R16000 in test. - Joseph Myers <joseph@codesourcery.com> - Ian Lance Taylor <ian@wasabisystems.com> - Ben Elliston <bje@wasabisystems.com> - David Ung <davidu@mips.com> - Nigel Stephens <nigel@mips.com> - David Ung <davidu@mips.com> -2012-08-16 Ian Bolton <ian.bolton@arm.com> - Laurent Desnogues <laurent.desnogues@arm.com> - Jim MacArthur <jim.macarthur@arm.com> - Marcus Shawcroft <marcus.shawcroft@arm.com> - Nigel Stephens <nigel.stephens@arm.com> - Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> - Richard Earnshaw <rearnsha@arm.com> - Sofiane Naci <sofiane.naci@arm.com> - Tejas Belagod <tejas.belagod@arm.com> - Yufeng Zhang <yufeng.zhang@arm.com> - * aarch64.h: New file. + * mips.h: Document microMIPS DSP ASE usage. + (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for + microMIPS DSP ASE support. + (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise. + (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise. + (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise. + (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise. + (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise. + (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise. + (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise. 2012-07-06 Maciej W. Rozycki <macro@codesourcery.com> @@ -142,7 +927,7 @@ (XRELEASE_PREFIX_OPCODE): Likewise. 2011-12-08 Andrew Pinski <apinski@cavium.com> - Adam Nemet <anemet@caviumnetworks.com> + Adam Nemet <anemet@caviumnetworks.com> * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2. (INSN_OCTEON2): New macro. @@ -173,7 +958,7 @@ F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits. 2011-08-09 Chao-ying Fu <fu@mips.com> - Maciej W. Rozycki <macro@codesourcery.com> + Maciej W. Rozycki <macro@codesourcery.com> * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros. (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine. @@ -219,7 +1004,7 @@ (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros. 2011-07-24 Chao-ying Fu <fu@mips.com> - Maciej W. Rozycki <macro@codesourcery.com> + Maciej W. Rozycki <macro@codesourcery.com> * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros. (OP_MASK_STYPE, OP_SH_STYPE): Likewise. @@ -782,7 +1567,7 @@ 2008-11-28 Joshua Kinard <kumba@gentoo.org> * mips.h: Define CPU_R14000, CPU_R16000. - (OPCODE_IS_MEMBER): Include R14000, R16000 in test. + (OPCODE_IS_MEMBER): Include R14000, R16000 in test. 2008-11-18 Catherine Moore <clm@codesourcery.com> @@ -828,7 +1613,7 @@ 2008-04-28 Adam Nemet <anemet@caviumnetworks.com> - * mips.h (INSN_MACRO): Move it up to the the pinfo macros. + * mips.h (INSN_MACRO): Move it up to the pinfo macros. (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros. 2008-04-14 Edmar Wienskoski <edmar@freescale.com> @@ -1021,9 +1806,9 @@ * i386.h: Replace CpuMNI with CpuSSSE3. 2006-09-26 Mark Shinwell <shinwell@codesourcery.com> - Joseph Myers <joseph@codesourcery.com> - Ian Lance Taylor <ian@wasabisystems.com> - Ben Elliston <bje@wasabisystems.com> + Joseph Myers <joseph@codesourcery.com> + Ian Lance Taylor <ian@wasabisystems.com> + Ben Elliston <bje@wasabisystems.com> * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define. @@ -1066,18 +1851,18 @@ * m68k.h (mcf_mask): Define. 2006-05-05 Thiemo Seufer <ths@mips.com> - David Ung <davidu@mips.com> + David Ung <davidu@mips.com> * mips.h (enum): Add macro M_CACHE_AB. 2006-05-04 Thiemo Seufer <ths@mips.com> - Nigel Stephens <nigel@mips.com> + Nigel Stephens <nigel@mips.com> David Ung <davidu@mips.com> * mips.h: Add INSN_SMARTMIPS define. 2006-04-30 Thiemo Seufer <ths@mips.com> - David Ung <davidu@mips.com> + David Ung <davidu@mips.com> * mips.h: Defines udi bits and masks. Add description of characters which may appear in the args field of udi @@ -1602,6 +2387,12 @@ For older changes see ChangeLog-9103 +Copyright (C) 2004-2015 Free Software Foundation, Inc. + +Copying and distribution of this file, with or without modification, +are permitted in any medium without royalty provided the copyright +notice and this notice are preserved. + Local Variables: mode: change-log left-margin: 8 |
