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2023-03-30libc: Define __atomic_is_lock_free.riastradh
Limited to architectures where it is actually needed by gcc for any calls to stdatomic.h atomic_is_lock_free for now. We should also add it to other architectures too, along with lockful atomic r/m/w operations for sizes that can't be handled natively, but that's a lot more work. It is also necessary for -fno-inline-atomics but we're missing a lot of other symbols for that too, to be fixed. For now, this should enable the OpenSSL build to complete on these architectures again after I reverted a local change. XXX pullup-10
2022-04-21mips/cavium: Take advantage of Octeon's guaranteed r/rw ordering.riastradh
2022-04-09Introduce membar_acquire/release. Deprecate membar_enter/exit.riastradh
The names membar_enter/exit were unclear, and the documentation of membar_enter has disagreed with the implementations on sparc, powerpc, and even x86(!) for the entire time it has been in NetBSD. The terms `acquire' and `release' are ubiquitous in the literature today, and have been adopted in the C and C++ standards to mean load-before-load/store and load/store-before-store, respectively, which are exactly the orderings required by acquiring and releasing a mutex, as well as other useful applications like decrementing a reference count and then freeing the underlying object if it went to zero. Originally I proposed changing one word in the documentation for membar_enter to make it load-before-load/store instead of store-before-load/store, i.e., to make it an acquire barrier. I proposed this on the grounds that (a) all implementations guarantee load-before-load/store, (b) some implementations fail to guarantee store-before-load/store, and (c) all uses in-tree assume load-before-load/store. I verified parts (a) and (b) (except, for (a), powerpc didn't even guarantee load-before-load/store -- isync isn't necessarily enough; need lwsync in general -- but it _almost_ did, and it certainly didn't guarantee store-before-load/store). Part (c) might not be correct, however: under the mistaken assumption that atomic-r/m/w then membar-w/rw is equivalent to atomic-r/m/w then membar-r/rw, I only audited the cases of membar_enter that _aren't_ immediately after an atomic-r/m/w. All of those cases assume load-before-load/store. But my assumption was wrong -- there are cases of atomic-r/m/w then membar-w/rw that would be broken by changing to atomic-r/m/w then membar-r/rw: https://mail-index.netbsd.org/tech-kern/2022/03/29/msg028044.html Furthermore, the name membar_enter has been adopted in other places like OpenBSD where it actually does follow the documentation and guarantee store-before-load/store, even if that order is not useful. So the name membar_enter currently lives in a bad place where it means either of two things -- r/rw or w/rw. With this change, we deprecate membar_enter/exit, introduce membar_acquire/release as better names for the useful pair (r/rw and rw/w), and make sure the implementation of membar_enter guarantees both what was documented _and_ what was implemented, making it an alias for membar_sync. While here, rework all of the membar_* definitions and aliases. The new logic follows a rule to make it easier to audit: membar_X is defined as an alias for membar_Y iff membar_X is guaranteed by membar_Y. The `no stronger than' relation is (the transitive closure of): - membar_consumer (r/r) is guaranteed by membar_acquire (r/rw) - membar_producer (w/w) is guaranteed by membar_release (rw/w) - membar_acquire (r/rw) is guaranteed by membar_sync (rw/rw) - membar_release (rw/w) is guaranteed by membar_sync (rw/rw) And, for the deprecated membars: - membar_enter (whether r/rw, w/rw, or rw/rw) is guaranteed by membar_sync (rw/rw) - membar_exit (rw/w) is guaranteed by membar_release (rw/w) (membar_exit is identical to membar_release, but the name is deprecated.) Finally, while here, annotate some of the instructions with their semantics. For powerpc, leave an essay with citations on the unfortunate but -- as far as I can tell -- necessary decision to use lwsync, not isync, for membar_acquire and membar_consumer. Also add membar(3) and atomic(3) man page links.
2022-02-27mips: Membar audit.riastradh
This change should be safe because it doesn't remove or weaken any memory barriers, but does add, clarify, or strengthen barriers. Goals: - Make sure mutex_enter/exit and mutex_spin_enter/exit have acquire/release semantics. - New macros make maintenance easier and purpose clearer: . SYNC_ACQ is for load-before-load/store barrier, and BDSYNC_ACQ for a branch delay slot -- currently defined as plain sync for MP and nothing, or nop, for UP; thus it is no weaker than SYNC and BDSYNC as currently defined, which is syncw on Octeon, plain sync on non-Octeon MP, and nothing/nop on UP. It is not clear to me whether load-then-syncw or ll/sc-then-syncw or even bare load provides load-acquire semantics on Octeon -- if no, this will fix bugs; if yes (like it is on SPARC PSO), we can relax SYNC_ACQ to be syncw or nothing later. . SYNC_REL is for load/store-before-store barrier -- currently defined as plain sync for MP and nothing for UP. It is not clear to me whether syncw-then-store is enough for store-release on Octeon -- if no, we can leave this as is; if yes, we can relax SYNC_REL to be syncw on Octeon. . SYNC_PLUNGER is there to flush clogged Cavium store buffers, and BDSYNC_PLUNGER for a branch delay slot -- syncw on Octeon, nothing or nop on non-Octeon. => This is not necessary (or, as far as I'm aware, sufficient) for acquire semantics -- it serves only to flush store buffers where stores might otherwise linger for hundreds of thousands of cycles, which would, e.g., cause spin locks to be held for unreasonably long durations. Newerish revisions of the MIPS ISA also have finer-grained sync variants that could be plopped in here. Mechanism: Insert these barriers in the right places, replacing only those where the definition is currently equivalent, so this change is safe. - Replace #ifdef _MIPS_ARCH_OCTEONP / syncw / #endif at the end of atomic_cas_* by SYNC_PLUNGER, which is `sync 4' (a.k.a. syncw) if __OCTEON__ and empty otherwise. => From what I can tell, __OCTEON__ is defined in at least as many contexts as _MIPS_ARCH_OCTEONP -- i.e., there are some Octeons with no _MIPS_ARCH_OCTEONP, but I don't know if any of them are relevant to us or ever saw the light of day outside Cavium; we seem to buid with `-march=octeonp' so this is unlikely to make a difference. If it turns out that we do care, well, now there's a central place to make the distinction for sync instructions. - Replace post-ll/sc SYNC by SYNC_ACQ in _atomic_cas_*, which are internal kernel versions used in sys/arch/mips/include/lock.h where it assumes they have load-acquire semantics. Should move this to lock.h later, since we _don't_ define __HAVE_ATOMIC_AS_MEMBAR on MIPS and so the extra barrier might be costly. - Insert SYNC_REL before ll/sc, and replace post-ll/sc SYNC by SYNC_ACQ, in _ucas_*, which is used without any barriers in futex code and doesn't mention barriers in the man page so I have to assume it is required to be a release/acquire barrier. - Change BDSYNC to BDSYNC_ACQ in mutex_enter and mutex_spin_enter. This is necessary to provide load-acquire semantics -- unclear if it was provided already by syncw on Octeon, but it seems more likely that either (a) no sync or syncw is needed at all, or (b) syncw is not enough and sync is needed, since syncw is only a store-before-store ordering barrier. - Insert SYNC_REL before ll/sc in mutex_exit and mutex_spin_exit. This is currently redundant with the SYNC already there, but SYNC_REL more clearly identifies the necessary semantics in case we want to define it differently on different systems, and having a sync in the middle of an ll/sc is a bit weird and possibly not a good idea, so I intend to (carefully) remove the redundant SYNC in a later change. - Change BDSYNC to BDSYNC_PLUNGER at the end of mutex_exit. This has no semantic change right now -- it's syncw on Octeon, sync on non-Octeon MP, nop on UP -- but we can relax it later to nop on non-Cavium MP. - Leave LLSCSYNC in for now -- it is apparently there for a Cavium erratum, but I'm not sure what the erratum is, exactly, and I have no reference for it. I suspect these can be safely removed, but we might have to double up some other syncw instructions -- Linux uses it only in store-release sequences, not at the head of every ll/sc.
2022-02-12mips: Brush up __cpu_simple_lock.riastradh
- Eradicate last vestiges of mb_* barriers. - In __cpu_simple_lock_init, omit needless barrier. It is the caller's responsibility to ensure __cpu_simple_lock_init happens before other operations on it anyway, so there was never any need for a barrier here. - In __cpu_simple_lock_try, leave comments about memory ordering guarantees of the kernel's _atomic_cas_uint, which are inexplicably different from the non-underscored atomic_cas_uint. - In __cpu_simple_unlock, use membar_exit instead of mb_memory, and do it unconditionally. This ensures that in __cpu_simple_lock/.../__cpu_simple_unlock, all memory operations in the ellipsis happen before the store that releases the lock. - On Octeon, the barrier was omitted altogether, which is a bug -- it needs to be there or else there is no happens-before relation and whoever takes the lock next might see stale values stored or even stomp over the unlocking CPU's delayed loads. - On non-Octeon, the mb_memory was sync. Using membar_exit preserves this. XXX On Octeon, membar_exit only issues syncw -- this seems wrong, only store-before-store and not load/store-before-store, unless the CNMIPS architecture guarantees it is sufficient here like SPARCv8/v9 PSO (`Partial Store Order'). - Leave an essay with citations about why we have an apparently pointless syncw _after_ releasing a lock, to work around a design bug^W^Wquirk in cnmips which sometimes buffers stores for hundreds of thousands of cycles for fun unless you issue syncw.
2021-04-25use ${MACHINE_MIPS64}christos
2020-08-10More SYNC centralisationskrll
2020-08-06Centralise SYNC/BDSYNC in asm.h and introduce a new LLCSCSYNC and use itskrll
before any ll/sc sequences. Define LLSCSYNC as syncw; syncw for cnMIPS - issue two as early cnMIPS has errat{um,a} that means the first can fail.
2020-08-01Trailing whitespaceskrll
2019-02-28Add missing atomic_and_{8,16}_nv_cas.c for __sync_and_and_fetch_{1,2}.isaki
XXX why is not only atomic_and_* symmetric unlike the others? (in common/lib/libc/atomic/)
2019-02-20Export atomic_cas_32_ni in a similar manner to its 64-bit counterpart.rin
Compile test only, but seems trivial enough for me. Fix build error due to test/lib/libc/atomic/t_atomic_cas. Note that mips32 does not use atomic_cas.S.
2019-02-19Add atomic_cas_64_ni aliasmartin
2017-02-25Switch from __ABICALLS__ to __mips_abicalls like upstream GCC does injoerg
the generic MIPS target logic.
2015-06-23Always use sync if mips3 or later or not using O32 ABI. (A little redundantmatt
since not using O32 means you are using mips3 or later.)
2015-06-22#include "assym.h"matt
Don't include "assym.h" with _RUMPKERNEL defined.
2015-06-01Include OCTEON support for syncw and saa/saad (Store Atomic Add).matt
2015-05-26force 2nd to argument to unsigned byte value.matt
(found by t_strchr and t_strrchr tests)
2014-10-13Provide <atomic> C++ 2011 support functions for mips and sh3.martin
2014-02-24Provide cas_16 and cas_8 emulation via cas_32 and use that for mips64martin
2014-02-21Provide all __sync_* ops in libc.martin
2012-08-03Add a missing .set noreordermatt
2012-03-14don't include <sys/cdefs.h> from assembly.christos
2011-08-27loongson2f support:bouyer
- Add some loongson2 definitions to cpuregs.h, from OpenBSD - Make sure that the at register is useable before every jump register instruction (exept when register is k0 or k1) because -mfix-loongson2f-btb needs the at register for its workaround - add code to mips_fixup.c to handle the instructions added by -mfix-loongson2f-btb - Add a ls2-specific tlb miss handler: it doesn't have separate handler for the xtlbmiss exeption. - Fixes for some #ifdef MIPS3_LOONGSON2 assembly code (using the wrong register)
2011-07-04add a weak alias from ffs to __ffssi2. newsmips kernels link now.mrg
2011-01-23Add a new O(log(2) implementation. On mips32/mips64, use clz/dclz.matt
2011-01-02Make these 64-bit clean.matt
2009-12-14Merge from matt-nb5-mips64matt
2009-07-17Change all archs so that strchr.[cS] and strrchr.[cS] exist and generatedsl
duplicate symbols for index() and rindex().
2009-07-16Add asm files for str(r)chr by copying the files for (r)index fromdsl
src/libc/arch/mips/string. Add XLEAF() for index entry points.
2009-01-04allow inclusion of atomic ops in librumppooka
2008-09-29Allow atomic ops to be built as part of libpthread.ad
2008-05-25enable profiling of assembly functions.chs
2008-04-30Assembly _atomic_cas_up() for mips. PR lib/38482.ad
2008-04-28Remove clause 3 and 4 from TNF licensesmartin
2008-02-11Only build atomic ops for libkern/libc.ad
2008-02-10Enable the atomic ops in userspace.ad
2007-11-30Memory barriers for MIPS.ad
2007-11-29Use the CAS-based inc/dec variants, since these CPUs don't have atomicad
add in hardware (does arm?).
2007-11-29Make the 64-bit operations available when possible.ad
2007-11-29Atomic ops for MIPS. Use the CAS functions already provided by the kernel,ad
and use the generic C code to provide the rest. Unfortunatley the C code assembles up pretty badly on MIPS but at least it will work.
2006-02-08Don't rename bswap{16,32} if either _KERNEL or _STANDALONE are defined,simonb
instead of just if _KERNEL was defined. Fixes sbmips bootblocks build problems. Thanks to Valeriy Ushakov for showing me where the problem was.
2005-12-27Don't redefine _LOCORE if it's already defined.tsutsui
Some Makefiles for standalone programs already have it. XXX Old src/sys/lib/libkern/arch/mips/memcpy.S had some #ifdef MIPS3_5900 XXX which added some extra nops, but this new common bcopy.S doesn't.
2005-12-21move from libc.christos
2005-12-20Merge libkern + libc common files. As requested by core.christos